From 90f33674a0756a6f0907b8f6350cec3f7be4032c Mon Sep 17 00:00:00 2001 From: Martin Leung Date: Fri, 13 May 2022 17:40:42 -0400 Subject: drm/amd/display: Prepare for new interfaces [WHY]: Lut pipeline will be hooked up differently in some asics need to add new interfaces and missing registers. [HOW]: Add missing registers and hook up programming from DPP for pre-blend lut. Acked-by: Rodrigo Siqueira Signed-off-by: Martin Leung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h') diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h index 170cf4ae03b6..494cb3a47435 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.h @@ -47,6 +47,13 @@ void dcn32_cab_for_ss_control(struct dc *dc, bool enable); void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context); +bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); + +bool dcn32_set_input_transfer_func(struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); + bool dcn32_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); -- cgit v1.2.3