From 06ab6832ac06c77332e3b0415977acf68ea364cf Mon Sep 17 00:00:00 2001 From: Nils Wallménius Date: Mon, 2 May 2016 12:46:15 -0400 Subject: drm/amdgpu: Mark all instances of struct drm_info_list as const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All these are compile time constand and the drm_debugfs_create/remove_files functions take a const pointer argument. Reviewed-by: Christian König Signed-off-by: Nils Wallménius Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index ff9597ce268c..6d44d4a64698 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1212,7 +1212,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) return 0; } -static struct drm_info_list amdgpu_pm_info_list[] = { +static const struct drm_info_list amdgpu_pm_info_list[] = { {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, }; #endif -- cgit v1.2.3 From 5632708f4452eb9afb985b245b98dac9a5feeac2 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Tue, 12 Apr 2016 14:57:23 -0400 Subject: drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) Allows you to force multiple levels rather than just one via the new sysfs interrface. v2: squash in: drm/amd/powerplay: ensure clock level set by user is valid. From Rex. Reviewed-by: Alex Deucher Signed-off-by: Eric Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 51 +++++++++++++++------- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +- drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 6 +-- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 18 ++++++-- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 16 +++++-- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 16 +++++-- drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 2 +- drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +- 8 files changed, 81 insertions(+), 34 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6d44d4a64698..589b36e8c5cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -362,16 +362,23 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; int ret; long level; + uint32_t i, mask = 0; + char sub_str[2]; - ret = kstrtol(buf, 0, &level); + for (i = 0; i < strlen(buf) - 1; i++) { + sub_str[0] = *(buf + i); + sub_str[1] = '\0'; + ret = kstrtol(sub_str, 0, &level); - if (ret) { - count = -EINVAL; - goto fail; + if (ret) { + count = -EINVAL; + goto fail; + } + mask |= 1 << level; } if (adev->pp_enabled) - amdgpu_dpm_force_clock_level(adev, PP_SCLK, level); + amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); fail: return count; } @@ -399,16 +406,23 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; int ret; long level; + uint32_t i, mask = 0; + char sub_str[2]; - ret = kstrtol(buf, 0, &level); + for (i = 0; i < strlen(buf) - 1; i++) { + sub_str[0] = *(buf + i); + sub_str[1] = '\0'; + ret = kstrtol(sub_str, 0, &level); - if (ret) { - count = -EINVAL; - goto fail; + if (ret) { + count = -EINVAL; + goto fail; + } + mask |= 1 << level; } if (adev->pp_enabled) - amdgpu_dpm_force_clock_level(adev, PP_MCLK, level); + amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); fail: return count; } @@ -436,16 +450,23 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, struct amdgpu_device *adev = ddev->dev_private; int ret; long level; + uint32_t i, mask = 0; + char sub_str[2]; - ret = kstrtol(buf, 0, &level); + for (i = 0; i < strlen(buf) - 1; i++) { + sub_str[0] = *(buf + i); + sub_str[1] = '\0'; + ret = kstrtol(sub_str, 0, &level); - if (ret) { - count = -EINVAL; - goto fail; + if (ret) { + count = -EINVAL; + goto fail; + } + mask |= 1 << level; } if (adev->pp_enabled) - amdgpu_dpm_force_clock_level(adev, PP_PCIE, level); + amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); fail: return count; } diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index ce8d9bf8d68d..0527ae3d10f9 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -763,7 +763,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) } static int pp_dpm_force_clock_level(void *handle, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct pp_hwmgr *hwmgr; @@ -779,7 +779,7 @@ static int pp_dpm_force_clock_level(void *handle, return 0; } - return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level); + return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); } static int pp_dpm_print_clock_levels(void *handle, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c index 648394fff69a..1f14c477d15d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c @@ -1729,7 +1729,7 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr, } static int cz_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) return -EINVAL; @@ -1738,10 +1738,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr, case PP_SCLK: smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSclkSoftMin, - (1 << level)); + mask); smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetSclkSoftMax, - (1 << level)); + mask); break; default: break; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index dc836d3e92b5..f8d49f1b44f5 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c @@ -5113,7 +5113,7 @@ static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t siz } static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); @@ -5125,20 +5125,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, if (!data->sclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; + case PP_MCLK: if (!data->mclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; + case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + if (!data->pcie_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_PCIeDPM_ForceLevel, - (1 << level)); + level); break; + } default: break; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index 2ab3bb25d175..79192c301d78 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@ -4767,7 +4767,7 @@ static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_ } static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); @@ -4779,20 +4779,28 @@ static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr, if (!data->sclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; case PP_MCLK: if (!data->mclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + if (!data->pcie_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_PCIeDPM_ForceLevel, - (1 << level)); + level); break; + } default: break; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 0242e348e755..9040225bec90 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c @@ -6075,7 +6075,7 @@ static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t si } static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); @@ -6087,20 +6087,28 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr, if (!data->sclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; case PP_MCLK: if (!data->mclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + if (!data->pcie_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_PCIeDPM_ForceLevel, - (1 << level)); + level); break; + } default: break; } diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index e5f2ee749fa6..50b367d44307 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -340,7 +340,7 @@ struct amd_powerplay_funcs { int (*get_pp_num_states)(void *handle, struct pp_states_info *data); int (*get_pp_table)(void *handle, char **table); int (*set_pp_table)(void *handle, const char *buf, size_t size); - int (*force_clock_level)(void *handle, enum pp_clock_type type, int level); + int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); }; diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 12285a989eff..b1a9ae509ed8 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -335,7 +335,7 @@ struct pp_hwmgr_func { int (*power_off_asic)(struct pp_hwmgr *hwmgr); int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table); int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size); - int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level); + int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable); }; -- cgit v1.2.3 From 041bf0225552044b85ce7ee7981e790d987d6ceb Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 16 Jun 2016 11:30:23 +0300 Subject: drm/amdgpu: missing bounds check in amdgpu_set_pp_force_state() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no limit on high "idx" can go. It should be less than ARRAY_SIZE(data.states) which is 16. The "data" variable wasn't declared in that scope so I shifted the code around a bit to make it work. Also I made "idx" unsigned. Fixes: f3898ea12fc1 ('drm/amd/powerplay: add some sysfs interfaces for powerplay.') Acked-by: Christian König Signed-off-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 589b36e8c5cf..0e13d80d2a95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -270,30 +270,28 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = ddev->dev_private; enum amd_pm_state_type state = 0; - long idx; + unsigned long idx; int ret; if (strlen(buf) == 1) adev->pp_force_state_enabled = false; - else { - ret = kstrtol(buf, 0, &idx); + else if (adev->pp_enabled) { + struct pp_states_info data; - if (ret) { + ret = kstrtoul(buf, 0, &idx); + if (ret || idx >= ARRAY_SIZE(data.states)) { count = -EINVAL; goto fail; } - if (adev->pp_enabled) { - struct pp_states_info data; - amdgpu_dpm_get_pp_num_states(adev, &data); - state = data.states[idx]; - /* only set user selected power states */ - if (state != POWER_STATE_TYPE_INTERNAL_BOOT && - state != POWER_STATE_TYPE_DEFAULT) { - amdgpu_dpm_dispatch_task(adev, - AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL); - adev->pp_force_state_enabled = true; - } + amdgpu_dpm_get_pp_num_states(adev, &data); + state = data.states[idx]; + /* only set user selected power states */ + if (state != POWER_STATE_TYPE_INTERNAL_BOOT && + state != POWER_STATE_TYPE_DEFAULT) { + amdgpu_dpm_dispatch_task(adev, + AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL); + adev->pp_force_state_enabled = true; } } fail: -- cgit v1.2.3