From 811fce4f2a7aea0cd93815d0eaf42fbcc98bd930 Mon Sep 17 00:00:00 2001 From: Thor Thayer Date: Mon, 21 Mar 2016 11:01:42 -0500 Subject: EDAC, altera: Add register offset for ECC Error Inject In preparation for the Arria10 peripheral ECCs, add a register offset from the ECC base to the private data structure to index to the error injection register. Signed-off-by: Thor Thayer Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-edac Link: http://lkml.kernel.org/r/1458576106-24505-6-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov --- drivers/edac/altera_edac.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/edac/altera_edac.h') diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h index 32c798a6f980..d7ef94c13b98 100644 --- a/drivers/edac/altera_edac.h +++ b/drivers/edac/altera_edac.h @@ -205,6 +205,7 @@ struct altr_sdram_mc_data { /******* Cyclone5 and Arria5 Defines *******/ /* OCRAM ECC Management Group Defines */ #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04 +#define ALTR_OCR_ECC_REG_OFFSET 0x00 #define ALTR_OCR_ECC_EN BIT(0) #define ALTR_OCR_ECC_INJS BIT(1) #define ALTR_OCR_ECC_INJD BIT(2) @@ -213,6 +214,7 @@ struct altr_sdram_mc_data { /* L2 ECC Management Group Defines */ #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00 +#define ALTR_L2_ECC_REG_OFFSET 0x00 #define ALTR_L2_ECC_EN BIT(0) #define ALTR_L2_ECC_INJS BIT(1) #define ALTR_L2_ECC_INJD BIT(2) @@ -229,6 +231,7 @@ struct edac_device_prv_data { int ecc_enable_mask; int ce_set_mask; int ue_set_mask; + int set_err_ofst; int trig_alloc_sz; }; -- cgit v1.2.3