From ccc077292733f3143b444255fa5ec49a8ff2763b Mon Sep 17 00:00:00 2001 From: Thomas Breitung Date: Mon, 19 Jun 2017 16:40:04 +0200 Subject: dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared before a new value can be or-ed in. Signed-off-by: Thomas Breitung Signed-off-by: Wolfgang Ocker Signed-off-by: Vinod Koul --- drivers/dma/fsldma.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/dma/fsldma.h') diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 31bffccdcc75..4787d485dd76 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -36,6 +36,10 @@ #define FSL_DMA_MR_DAHE 0x00002000 #define FSL_DMA_MR_SAHE 0x00001000 +#define FSL_DMA_MR_SAHTS_MASK 0x0000C000 +#define FSL_DMA_MR_DAHTS_MASK 0x00030000 +#define FSL_DMA_MR_BWC_MASK 0x0f000000 + /* * Bandwidth/pause control determines how many bytes a given * channel is allowed to transfer before the DMA engine pauses -- cgit v1.2.3