From 53fa1bff3426344d466d91e81f076eab677d0ece Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Sun, 23 Jan 2022 16:29:53 -0800 Subject: cxl/core: Track port depth In preparation for proving CXL subsystem usage of the device_lock() order track the depth of ports with the expectation that shallower port locks can be held over deeper port locks. Signed-off-by: Ben Widawsky Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams --- drivers/cxl/cxl.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/cxl/cxl.h') diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 621a70e023c1..7ade555076bc 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -252,6 +252,7 @@ struct cxl_walk_context { * @dports: cxl_dport instances referenced by decoders * @decoder_ida: allocator for decoder ids * @component_reg_phys: component register capability base address (optional) + * @depth: How deep this port is relative to the root. depth 0 is the root. */ struct cxl_port { struct device dev; @@ -260,6 +261,7 @@ struct cxl_port { struct list_head dports; struct ida decoder_ida; resource_size_t component_reg_phys; + unsigned int depth; }; /** -- cgit v1.2.3