From 30a85eb64347ef16aefba3aa96cb7f2c1615290a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 13 Oct 2018 13:22:22 +0300 Subject: clocksource/drivers/timer-vt8500: Remove duplicate function name We print the function name twice in a row in the error message so I've removed one. Signed-off-by: Dan Carpenter Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vt8500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-vt8500.c b/drivers/clocksource/timer-vt8500.c index e0f7489cfc8e..c3aff1a8f7d5 100644 --- a/drivers/clocksource/timer-vt8500.c +++ b/drivers/clocksource/timer-vt8500.c @@ -145,7 +145,7 @@ static int __init vt8500_timer_init(struct device_node *np) ret = clocksource_register_hz(&clocksource, VT8500_TIMER_HZ); if (ret) { - pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n", + pr_err("%s: clocksource_register failed for %s\n", __func__, clocksource.name); return ret; } -- cgit v1.2.3 From bc0750e464d41e1234f56471b8f626b8d945b1a8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 15 Nov 2018 14:32:02 +0100 Subject: clocksource/drivers/dbx500: Demote dbx500 PRCMU clocksource Demote the DBx500 PRCMU clocksource to quality 100 and mark it as NONSTOP so it will still be used for timekeeping across suspend/resume. The Nomadik MTU timer which has higher precision will be used when the system is up and running, thanks to the recent changes properly utilizing the suspend clocksources. This was discussed back in 2011 when the driver was written, but the infrastructure was not available upstream to use this timer properly. Now the infrastructure is there, so let's finalize the work. Cc: Baolin Wang Signed-off-by: Linus Walleij Reviewed-by: Baolin Wang Signed-off-by: Daniel Lezcano --- drivers/clocksource/clksrc-dbx500-prcmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index c1b96dc5f444..4054539fe066 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -46,10 +46,10 @@ static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) static struct clocksource clocksource_dbx500_prcmu = { .name = "dbx500-prcmu-timer", - .rating = 300, + .rating = 100, .read = clksrc_dbx500_prcmu_read, .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK -- cgit v1.2.3 From 85b6fcadcf6626ad520376eacfb2b77090e782ab Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 15 Nov 2018 14:32:03 +0100 Subject: clocksource/drivers/ux500: Drop Ux500 custom SCHED_CLOCK The two drivers used for Ux500 sched_clock use two Kconfig symbols to select which of the two gets used as sched_clock. This isn't right: the workaround is trying to make sure that the NONSTOP timer is used for sched_clock in order to keep that clock ticking consistently over a suspend/resume cycle. (Otherwise sched_clock simply stops during suspend and continues after resume). This will notably affect any timetstamped debug prints, so that they show the absolute number of seconds since the system was booted and does not loose wall-clock time during suspend and resume as if time stood still. The real way to fix this problem is to make sched_clock take advantage of any NONSTOP clock source on the system and adjust accordingly, not to try to work around this by using a different sched_clock depending on what system we are compiling for. This can solve the problem for everyone instead of providing a local solution. Cc: Baolin Wang Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 13 ------------- drivers/clocksource/clksrc-dbx500-prcmu.c | 18 ------------------ drivers/clocksource/nomadik-mtu.c | 4 ---- 3 files changed, 35 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 55c77e44bb2d..64d5759ddf0e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -163,12 +163,6 @@ config CLKSRC_NOMADIK_MTU to multiple interrupt generating programmable 32-bit free running decrementing counters. -config CLKSRC_NOMADIK_MTU_SCHED_CLOCK - bool - depends on CLKSRC_NOMADIK_MTU - help - Use the Multi Timer Unit as the sched_clock. - config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" if COMPILE_TEST depends on HAS_IOMEM @@ -226,13 +220,6 @@ config INTEGRATOR_AP_TIMER help Enables support for the Integrator-ap timer. -config CLKSRC_DBX500_PRCMU_SCHED_CLOCK - bool "Clocksource PRCMU Timer sched_clock" - depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK) - default y - help - Use the always on PRCMU Timer as sched_clock - config CLKSRC_EFM32 bool "Clocksource for Energy Micro's EFM32 SoCs" if !ARCH_EFM32 depends on OF && ARM && (ARCH_EFM32 || COMPILE_TEST) diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index 4054539fe066..51d53c4e646f 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -15,7 +15,6 @@ #include #include #include -#include #define RATE_32K 32768 @@ -26,8 +25,6 @@ #define PRCMU_TIMER_DOWNCOUNT 0x4 #define PRCMU_TIMER_MODE 0x8 -#define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */ - static void __iomem *clksrc_dbx500_timer_base; static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs) @@ -52,18 +49,6 @@ static struct clocksource clocksource_dbx500_prcmu = { .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK - -static u64 notrace dbx500_prcmu_sched_clock_read(void) -{ - if (unlikely(!clksrc_dbx500_timer_base)) - return 0; - - return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu); -} - -#endif - static int __init clksrc_dbx500_prcmu_init(struct device_node *node) { clksrc_dbx500_timer_base = of_iomap(node, 0); @@ -81,9 +66,6 @@ static int __init clksrc_dbx500_prcmu_init(struct device_node *node) writel(TIMER_DOWNCOUNT_VAL, clksrc_dbx500_timer_base + PRCMU_TIMER_REF); } -#ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK - sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K); -#endif return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); } TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4", diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c index 8e4ddb9420c6..19b336c9b417 100644 --- a/drivers/clocksource/nomadik-mtu.c +++ b/drivers/clocksource/nomadik-mtu.c @@ -69,7 +69,6 @@ static u32 clk_prescale; static u32 nmdk_cycle; /* write-once */ static struct delay_timer mtu_delay_timer; -#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK /* * Override the global weak sched_clock symbol with this * local implementation which uses the clocksource to get some @@ -82,7 +81,6 @@ static u64 notrace nomadik_read_sched_clock(void) return -readl(mtu_base + MTU_VAL(0)); } -#endif static unsigned long nmdk_timer_read_current_timer(void) { @@ -234,9 +232,7 @@ static int __init nmdk_timer_init(void __iomem *base, int irq, return ret; } -#ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK sched_clock_register(nomadik_read_sched_clock, 32, rate); -#endif /* Timer 1 is used for events, register irq and clockevents */ setup_irq(irq, &nmdk_timer_irq); -- cgit v1.2.3 From 63136299721b4bfbd51ddd41181ab3a5897958bb Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 14 Nov 2018 10:53:12 +0100 Subject: clocksource/drivers/timer-ti-dm: Remove the early platform driver registration This driver is no longer used as an early platform driver. Remove the registration macro. Signed-off-by: Bartosz Golaszewski Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-ti-dm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-ti-dm.c index 4cce6b224b87..595124074821 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -991,7 +991,6 @@ static struct platform_driver omap_dm_timer_driver = { }, }; -early_platform_init("earlytimer", &omap_dm_timer_driver); module_platform_driver(omap_dm_timer_driver); MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); -- cgit v1.2.3 From 7b59263801077e480be79e5f9a3a3bcdefeb05b8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 15 Nov 2018 11:00:37 +0100 Subject: clockevents/drivers/tegra20: Remove obsolete inclusion of As of commit da4a686a2cfb077a ("ARM: smp_twd: convert to use CLKSRC_OF init"), this header file is no longer used. Signed-off-by: Geert Uytterhoeven Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/tegra20_timer.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index aa624885e0e2..4293943f4e2b 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -30,7 +30,6 @@ #include #include -#include #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c -- cgit v1.2.3 From bed8fc137e20df7dabcaff0bf2bfe494766aa556 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Nov 2018 23:46:56 +0100 Subject: clocksource/drivers/meson6_timer: Use register names from the datasheet This makes the driver use the names from S805 datasheet for the preprocessor #defines. This makes it easier to spot that the driver currently only supports Timer A (as clockevent with interrupt support) and Timer E (as clocksource without interrupts). Timer B, C and D (which are similar to Timer A) are currently not supported by the driver. While here, this also removes the internal "CED_ID" and "CSD_ID" defines which are used to identify the timer. These IDs are not described in the datasheet and thus make it harder to compare the code to what's written in the datasheet. Signed-off-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/meson6_timer.c | 108 ++++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 44 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 92f20991a937..23c7638e2bb3 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -10,6 +10,8 @@ * warranty of any kind, whether express or implied. */ +#include +#include #include #include #include @@ -20,80 +22,96 @@ #include #include -#define CED_ID 0 -#define CSD_ID 4 - -#define TIMER_ISA_MUX 0 -#define TIMER_ISA_VAL(t) (((t) + 1) << 2) - -#define TIMER_INPUT_BIT(t) (2 * (t)) -#define TIMER_ENABLE_BIT(t) (16 + (t)) -#define TIMER_PERIODIC_BIT(t) (12 + (t)) - -#define TIMER_CED_INPUT_MASK (3UL << TIMER_INPUT_BIT(CED_ID)) -#define TIMER_CSD_INPUT_MASK (7UL << TIMER_INPUT_BIT(CSD_ID)) - -#define TIMER_CED_UNIT_1US 0 -#define TIMER_CSD_UNIT_1US 1 +#define MESON_ISA_TIMER_MUX 0x00 +#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) +#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) +#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17) +#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16) +#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15) +#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14) +#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13) +#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4 +#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6) +#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4) +#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2) +#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0) +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3 + +#define MESON_ISA_TIMERA 0x04 +#define MESON_ISA_TIMERB 0x08 +#define MESON_ISA_TIMERC 0x0c +#define MESON_ISA_TIMERD 0x10 +#define MESON_ISA_TIMERE 0x14 static void __iomem *timer_base; static u64 notrace meson6_timer_sched_read(void) { - return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID)); + return (u64)readl(timer_base + MESON_ISA_TIMERE); } -static void meson6_clkevt_time_stop(unsigned char timer) +static void meson6_clkevt_time_stop(void) { - u32 val = readl(timer_base + TIMER_ISA_MUX); + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); - writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); + writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); } -static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay) +static void meson6_clkevt_time_setup(unsigned long delay) { - writel(delay, timer_base + TIMER_ISA_VAL(timer)); + writel(delay, timer_base + MESON_ISA_TIMERA); } -static void meson6_clkevt_time_start(unsigned char timer, bool periodic) +static void meson6_clkevt_time_start(bool periodic) { - u32 val = readl(timer_base + TIMER_ISA_MUX); + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); if (periodic) - val |= TIMER_PERIODIC_BIT(timer); + val |= MESON_ISA_TIMER_MUX_TIMERA_MODE; else - val &= ~TIMER_PERIODIC_BIT(timer); + val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE; - writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); + writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); } static int meson6_shutdown(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); + meson6_clkevt_time_stop(); return 0; } static int meson6_set_oneshot(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_start(CED_ID, false); + meson6_clkevt_time_stop(); + meson6_clkevt_time_start(false); return 0; } static int meson6_set_periodic(struct clock_event_device *evt) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_setup(CED_ID, USEC_PER_SEC / HZ - 1); - meson6_clkevt_time_start(CED_ID, true); + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1); + meson6_clkevt_time_start(true); return 0; } static int meson6_clkevt_next_event(unsigned long evt, struct clock_event_device *unused) { - meson6_clkevt_time_stop(CED_ID); - meson6_clkevt_time_setup(CED_ID, evt); - meson6_clkevt_time_start(CED_ID, false); + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(evt); + meson6_clkevt_time_start(false); return 0; } @@ -144,22 +162,24 @@ static int __init meson6_timer_init(struct device_node *node) } /* Set 1us for timer E */ - val = readl(timer_base + TIMER_ISA_MUX); - val &= ~TIMER_CSD_INPUT_MASK; - val |= TIMER_CSD_UNIT_1US << TIMER_INPUT_BIT(CSD_ID); - writel(val, timer_base + TIMER_ISA_MUX); + val = readl(timer_base + MESON_ISA_TIMER_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC); - clocksource_mmio_init(timer_base + TIMER_ISA_VAL(CSD_ID), node->name, + clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name, 1000 * 1000, 300, 32, clocksource_mmio_readl_up); /* Timer A base 1us */ - val &= ~TIMER_CED_INPUT_MASK; - val |= TIMER_CED_UNIT_1US << TIMER_INPUT_BIT(CED_ID); - writel(val, timer_base + TIMER_ISA_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); /* Stop the timer A */ - meson6_clkevt_time_stop(CED_ID); + meson6_clkevt_time_stop(); ret = setup_irq(irq, &meson6_timer_irq); if (ret) { -- cgit v1.2.3 From fa83c6f45aa560f814adfdf1a0bf523c1157dfe1 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Thu, 15 Nov 2018 23:46:57 +0100 Subject: clocksource/drivers/meson6_timer: Implement the ARM delay timer Implement an ARM delay timer to be used for udelay(). This allows us to skip the delay loop calibration at boot. With this patch udelay() is now independent of CPU frequency changes. This is a good thing on Meson8, Meson8b and Meson8m2 because changing the CPU frequency requires running the CPU clock off the XTAL while changing the PLL or it's dividers. After changing the CPU clocks we need to wait a few usecs for the clock to become stable. So having an udelay() implementation that doesn't depend on the CPU frequency is beneficial. Suggested-by: Jianxin Pan Signed-off-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/meson6_timer.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c index 23c7638e2bb3..84bd9479c3f8 100644 --- a/drivers/clocksource/meson6_timer.c +++ b/drivers/clocksource/meson6_timer.c @@ -22,6 +22,10 @@ #include #include +#ifdef CONFIG_ARM +#include +#endif + #define MESON_ISA_TIMER_MUX 0x00 #define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) #define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) @@ -54,6 +58,18 @@ static void __iomem *timer_base; +#ifdef CONFIG_ARM +static unsigned long meson6_read_current_timer(void) +{ + return readl_relaxed(timer_base + MESON_ISA_TIMERE); +} + +static struct delay_timer meson6_delay_timer = { + .read_current_timer = meson6_read_current_timer, + .freq = 1000 * 1000, +}; +#endif + static u64 notrace meson6_timer_sched_read(void) { return (u64)readl(timer_base + MESON_ISA_TIMERE); @@ -192,6 +208,12 @@ static int __init meson6_timer_init(struct device_node *node) clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, 1, 0xfffe); + +#ifdef CONFIG_ARM + /* Also use MESON_ISA_TIMERE for delays */ + register_current_timer_delay(&meson6_delay_timer); +#endif + return 0; } TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer", -- cgit v1.2.3 From df181e38281602bb404c5c8158a87317274dc653 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 5 Nov 2018 01:10:27 +0000 Subject: clocksource/drivers/imx-gpt: Add support for ARM64 This patch allows building and compile-testing the i.MX GPT driver also for ARM64. The delay_timer is only supported on ARMv7. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-imx-gpt.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 64d5759ddf0e..8761a1c21b6c 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -567,7 +567,7 @@ config H8300_TPU config CLKSRC_IMX_GPT bool "Clocksource using i.MX GPT" if COMPILE_TEST - depends on ARM && CLKDEV_LOOKUP + depends on (ARM || ARM64) && CLKDEV_LOOKUP select CLKSRC_MMIO config CLKSRC_IMX_TPM diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index 165fbbb1c9a0..a3d6ccbf4a16 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -141,21 +141,25 @@ static u64 notrace mxc_read_sched_clock(void) return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; } +#if defined(CONFIG_ARM) static struct delay_timer imx_delay_timer; static unsigned long imx_read_current_timer(void) { return readl_relaxed(sched_clock_reg); } +#endif static int __init mxc_clocksource_init(struct imx_timer *imxtm) { unsigned int c = clk_get_rate(imxtm->clk_per); void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; +#if defined(CONFIG_ARM) imx_delay_timer.read_current_timer = &imx_read_current_timer; imx_delay_timer.freq = c; register_current_timer_delay(&imx_delay_timer); +#endif sched_clock_reg = reg; -- cgit v1.2.3 From ec3372f28f7bf589388780df5eda945d4cdd7c4b Mon Sep 17 00:00:00 2001 From: Clément Péron Date: Mon, 5 Nov 2018 15:15:11 +0100 Subject: clocksource/drivers/imx-gpt: Remove unnecessary irq protection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit shutdown and oneshot are already protected against irq interruptions Signed-off-by: Clément Péron Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-gpt.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index a3d6ccbf4a16..706c0d0ff56c 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -202,15 +202,8 @@ static int v2_set_next_event(unsigned long evt, static int mxc_shutdown(struct clock_event_device *ced) { struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long flags; u32 tcn; - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); - /* Disable interrupt in GPT module */ imxtm->gpt->gpt_irq_disable(imxtm); @@ -225,21 +218,12 @@ static int mxc_shutdown(struct clock_event_device *ced) printk(KERN_INFO "%s: changing mode\n", __func__); #endif /* DEBUG */ - local_irq_restore(flags); - return 0; } static int mxc_set_oneshot(struct clock_event_device *ced) { struct imx_timer *imxtm = to_imx_timer(ced); - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); /* Disable interrupt in GPT module */ imxtm->gpt->gpt_irq_disable(imxtm); @@ -264,7 +248,6 @@ static int mxc_set_oneshot(struct clock_event_device *ced) * mode switching */ imxtm->gpt->gpt_irq_enable(imxtm); - local_irq_restore(flags); return 0; } -- cgit v1.2.3 From bf287607c80f24387fedb431a346dc67f25be12c Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 19 Nov 2018 14:29:17 +0300 Subject: clocksource/drivers/arc_timer: Utilize generic sched_clock It turned out we used to use default implementation of sched_clock() from kernel/sched/clock.c which was as precise as 1/HZ, i.e. by default we had 10 msec granularity of time measurement. Now given ARC built-in timers are clocked with the same frequency as CPU cores we may get much higher precision of time tracking. Thus we switch to generic sched_clock which really reads ARC hardware counters. This is especially helpful for measuring short events. That's what we used to have: ------------------------------>8------------------------ $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello': 10.000000 task-clock (msec) # 2.832 CPUs utilized 1 context-switches # 0.100 K/sec 1 cpu-migrations # 0.100 K/sec 63 page-faults # 0.006 M/sec 3049480 cycles # 0.305 GHz 1091259 instructions # 0.36 insn per cycle 256828 branches # 25.683 M/sec 27026 branch-misses # 10.52% of all branches 0.003530687 seconds time elapsed 0.000000000 seconds user 0.010000000 seconds sys ------------------------------>8------------------------ And now we'll see: ------------------------------>8------------------------ $ perf stat /bin/sh -c /root/lmbench-master/bin/arc/hello > /dev/null Performance counter stats for '/bin/sh -c /root/lmbench-master/bin/arc/hello': 3.004322 task-clock (msec) # 0.865 CPUs utilized 1 context-switches # 0.333 K/sec 1 cpu-migrations # 0.333 K/sec 63 page-faults # 0.021 M/sec 2986734 cycles # 0.994 GHz 1087466 instructions # 0.36 insn per cycle 255209 branches # 84.947 M/sec 26002 branch-misses # 10.19% of all branches 0.003474829 seconds time elapsed 0.003519000 seconds user 0.000000000 seconds sys ------------------------------>8------------------------ Note how much more meaningful is the second output - time spent for execution pretty much matches number of cycles spent (we're runnign @ 1GHz here). Signed-off-by: Alexey Brodkin Cc: Daniel Lezcano Cc: Vineet Gupta Cc: Thomas Gleixner Cc: stable@vger.kernel.org Acked-by: Vineet Gupta Signed-off-by: Daniel Lezcano --- arch/arc/Kconfig | 1 + drivers/clocksource/Kconfig | 1 + drivers/clocksource/arc_timer.c | 22 ++++++++++++++++++++++ 3 files changed, 24 insertions(+) (limited to 'drivers/clocksource') diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index c9e2a1323536..74b5a654f664 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -26,6 +26,7 @@ config ARC select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP select GENERIC_PENDING_IRQ if SMP + select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 8761a1c21b6c..c57b156f49a2 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -277,6 +277,7 @@ config CLKSRC_MPS2 config ARC_TIMERS bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST + depends on GENERIC_SCHED_CLOCK select TIMER_OF help These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c index 20da9b1d7f7d..b28970ca4a7a 100644 --- a/drivers/clocksource/arc_timer.c +++ b/drivers/clocksource/arc_timer.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -88,6 +89,11 @@ static u64 arc_read_gfrc(struct clocksource *cs) return (((u64)h) << 32) | l; } +static notrace u64 arc_gfrc_clock_read(void) +{ + return arc_read_gfrc(NULL); +} + static struct clocksource arc_counter_gfrc = { .name = "ARConnect GFRC", .rating = 400, @@ -111,6 +117,8 @@ static int __init arc_cs_setup_gfrc(struct device_node *node) if (ret) return ret; + sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq); + return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq); } TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc); @@ -139,6 +147,11 @@ static u64 arc_read_rtc(struct clocksource *cs) return (((u64)h) << 32) | l; } +static notrace u64 arc_rtc_clock_read(void) +{ + return arc_read_rtc(NULL); +} + static struct clocksource arc_counter_rtc = { .name = "ARCv2 RTC", .rating = 350, @@ -170,6 +183,8 @@ static int __init arc_cs_setup_rtc(struct device_node *node) write_aux_reg(AUX_RTC_CTRL, 1); + sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq); + return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq); } TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc); @@ -185,6 +200,11 @@ static u64 arc_read_timer1(struct clocksource *cs) return (u64) read_aux_reg(ARC_REG_TIMER1_CNT); } +static notrace u64 arc_timer1_clock_read(void) +{ + return arc_read_timer1(NULL); +} + static struct clocksource arc_counter_timer1 = { .name = "ARC Timer1", .rating = 300, @@ -209,6 +229,8 @@ static int __init arc_cs_setup_timer1(struct device_node *node) write_aux_reg(ARC_REG_TIMER1_CNT, 0); write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); + sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq); + return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq); } -- cgit v1.2.3 From 3825603a8076738d95b430d36896a760d7fc4909 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 6 Nov 2018 05:15:58 +0000 Subject: clocksource/drivers/timer-imx-tpm: Convert the driver to timer-of Convert the driver to use the timer_of helpers. This allows to handle timer base, clock and irq using common timer_of driver and it simplifies the code. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 136 +++++++++++++++--------------------- 1 file changed, 55 insertions(+), 81 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index b7aa2b817078..c3dd4d2f2a6e 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -12,6 +12,8 @@ #include #include +#include "timer-of.h" + #define TPM_PARAM 0x4 #define TPM_PARAM_WIDTH_SHIFT 16 #define TPM_PARAM_WIDTH_MASK (0xff << 16) @@ -33,9 +35,7 @@ #define TPM_C0V 0x24 static int counter_width; -static int rating; static void __iomem *timer_base; -static struct clock_event_device clockevent_tpm; static inline void tpm_timer_disable(void) { @@ -80,19 +80,6 @@ static u64 notrace tpm_read_sched_clock(void) return tpm_read_counter(); } -static int __init tpm_clocksource_init(unsigned long rate) -{ - tpm_delay_timer.read_current_timer = &tpm_read_current_timer; - tpm_delay_timer.freq = rate; - register_current_timer_delay(&tpm_delay_timer); - - sched_clock_register(tpm_read_sched_clock, counter_width, rate); - - return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm", - rate, rating, counter_width, - clocksource_mmio_readl_up); -} - static int tpm_set_next_event(unsigned long delta, struct clock_event_device *evt) { @@ -137,74 +124,77 @@ static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static struct clock_event_device clockevent_tpm = { - .name = "i.MX7ULP TPM Timer", - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_state_oneshot = tpm_set_state_oneshot, - .set_next_event = tpm_set_next_event, - .set_state_shutdown = tpm_set_state_shutdown, +static struct timer_of to_tpm = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + .clkevt = { + .name = "i.MX7ULP TPM Timer", + .rating = 200, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = tpm_set_state_shutdown, + .set_state_oneshot = tpm_set_state_oneshot, + .set_next_event = tpm_set_next_event, + .cpumask = cpu_possible_mask, + }, + .of_irq = { + .handler = tpm_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, }; -static int __init tpm_clockevent_init(unsigned long rate, int irq) +static int __init tpm_clocksource_init(void) { - int ret; + tpm_delay_timer.read_current_timer = &tpm_read_current_timer; + tpm_delay_timer.freq = timer_of_rate(&to_tpm) >> 3; + register_current_timer_delay(&tpm_delay_timer); - ret = request_irq(irq, tpm_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "i.MX7ULP TPM Timer", &clockevent_tpm); + sched_clock_register(tpm_read_sched_clock, counter_width, + timer_of_rate(&to_tpm) >> 3); - clockevent_tpm.rating = rating; - clockevent_tpm.cpumask = cpumask_of(0); - clockevent_tpm.irq = irq; - clockevents_config_and_register(&clockevent_tpm, rate, 300, - GENMASK(counter_width - 1, 1)); + return clocksource_mmio_init(timer_base + TPM_CNT, + "imx-tpm", + timer_of_rate(&to_tpm) >> 3, + to_tpm.clkevt.rating, + counter_width, + clocksource_mmio_readl_up); +} - return ret; +static void __init tpm_clockevent_init(void) +{ + clockevents_config_and_register(&to_tpm.clkevt, + timer_of_rate(&to_tpm) >> 3, + 300, + GENMASK(counter_width - 1, + 1)); } static int __init tpm_timer_init(struct device_node *np) { - struct clk *ipg, *per; - int irq, ret; - u32 rate; - - timer_base = of_iomap(np, 0); - if (!timer_base) { - pr_err("tpm: failed to get base address\n"); - return -ENXIO; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - pr_err("tpm: failed to get irq\n"); - ret = -ENOENT; - goto err_iomap; - } + struct clk *ipg; + int ret; ipg = of_clk_get_by_name(np, "ipg"); - per = of_clk_get_by_name(np, "per"); - if (IS_ERR(ipg) || IS_ERR(per)) { - pr_err("tpm: failed to get ipg or per clk\n"); - ret = -ENODEV; - goto err_clk_get; + if (IS_ERR(ipg)) { + pr_err("tpm: failed to get ipg clk\n"); + return -ENODEV; } - /* enable clk before accessing registers */ ret = clk_prepare_enable(ipg); if (ret) { pr_err("tpm: ipg clock enable failed (%d)\n", ret); - goto err_clk_get; + clk_put(ipg); + return ret; } - ret = clk_prepare_enable(per); - if (ret) { - pr_err("tpm: per clock enable failed (%d)\n", ret); - goto err_per_clk_enable; - } + ret = timer_of_init(np, &to_tpm); + if (ret) + return ret; + + timer_base = timer_of_base(&to_tpm); - counter_width = (readl(timer_base + TPM_PARAM) & TPM_PARAM_WIDTH_MASK) - >> TPM_PARAM_WIDTH_SHIFT; + counter_width = (readl(timer_base + TPM_PARAM) + & TPM_PARAM_WIDTH_MASK) >> TPM_PARAM_WIDTH_SHIFT; /* use rating 200 for 32-bit counter and 150 for 16-bit counter */ - rating = counter_width == 0x20 ? 200 : 150; + to_tpm.clkevt.rating = counter_width == 0x20 ? 200 : 150; /* * Initialize tpm module to a known state @@ -229,29 +219,13 @@ static int __init tpm_timer_init(struct device_node *np) writel(TPM_SC_CMOD_INC_PER_CNT | (counter_width == 0x20 ? TPM_SC_CMOD_DIV_DEFAULT : TPM_SC_CMOD_DIV_MAX), - timer_base + TPM_SC); + timer_base + TPM_SC); /* set MOD register to maximum for free running mode */ writel(GENMASK(counter_width - 1, 0), timer_base + TPM_MOD); - rate = clk_get_rate(per) >> 3; - ret = tpm_clocksource_init(rate); - if (ret) - goto err_per_clk_enable; - - ret = tpm_clockevent_init(rate, irq); - if (ret) - goto err_per_clk_enable; - - return 0; + tpm_clockevent_init(); -err_per_clk_enable: - clk_disable_unprepare(ipg); -err_clk_get: - clk_put(per); - clk_put(ipg); -err_iomap: - iounmap(timer_base); - return ret; + return tpm_clocksource_init(); } TIMER_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init); -- cgit v1.2.3 From 64db8bb157cb8108ae017f00c2d47f03d4ebe8a6 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 10 Nov 2018 16:28:39 +0100 Subject: clocksource/drivers/bcm2835: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Also drop the FSF address. Cc: Simon Arlott Signed-off-by: Stefan Wahren Reviewed-by: Eric Anholt Acked-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- drivers/clocksource/bcm2835_timer.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c index 60da2537bef9..2b196cbfadb6 100644 --- a/drivers/clocksource/bcm2835_timer.c +++ b/drivers/clocksource/bcm2835_timer.c @@ -1,19 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2012 Simon Arlott - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include -- cgit v1.2.3 From 5eb73c831171115d3b4347e1e7124a5a35d8086c Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Sun, 25 Nov 2018 00:00:49 -0500 Subject: clocksource/drivers/integrator-ap: Add missing of_node_put() The function of_find_node_by_path() acquires a reference to the node returned by it and that reference needs to be dropped by its caller. integrator_ap_timer_init_of() doesn't do that. The pri_node and the sec_node are used as an identifier to compare against the current node, so we can directly drop the refcount after getting the node from the path as it is not used as pointer. By dropping the refcount right after getting it, a single variable is needed instead of two. Fix this by use a single variable and drop the refcount right after of_find_node_by_path(). Signed-off-by: Yangtao Li Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-integrator-ap.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-integrator-ap.c b/drivers/clocksource/timer-integrator-ap.c index 76e526f58620..19fb7de4b928 100644 --- a/drivers/clocksource/timer-integrator-ap.c +++ b/drivers/clocksource/timer-integrator-ap.c @@ -181,8 +181,7 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) int irq; struct clk *clk; unsigned long rate; - struct device_node *pri_node; - struct device_node *sec_node; + struct device_node *alias_node; base = of_io_request_and_map(node, 0, "integrator-timer"); if (IS_ERR(base)) @@ -204,7 +203,18 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) return err; } - pri_node = of_find_node_by_path(path); + alias_node = of_find_node_by_path(path); + + /* + * The pointer is used as an identifier not as a pointer, we + * can drop the refcount on the of__node immediately after + * getting it. + */ + of_node_put(alias_node); + + if (node == alias_node) + /* The primary timer lacks IRQ, use as clocksource */ + return integrator_clocksource_init(rate, base); err = of_property_read_string(of_aliases, "arm,timer-secondary", &path); @@ -213,14 +223,11 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) return err; } + alias_node = of_find_node_by_path(path); - sec_node = of_find_node_by_path(path); - - if (node == pri_node) - /* The primary timer lacks IRQ, use as clocksource */ - return integrator_clocksource_init(rate, base); + of_node_put(alias_node); - if (node == sec_node) { + if (node == alias_node) { /* The secondary timer will drive the clock event */ irq = irq_of_parse_and_map(node, 0); return integrator_clockevent_init(rate, base, irq); -- cgit v1.2.3 From 86fe57fc47b17b3528fa5497fc57e158d846c4ea Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 3 Oct 2018 14:53:50 -0700 Subject: clocksource/drivers/fttmr010: Fix invalid interrupt register access TIMER_INTR_MASK register (Base Address of Timer + 0x38) is not designed for masking interrupts on ast2500 chips, and it's not even listed in ast2400 datasheet, so it's not safe to access TIMER_INTR_MASK on aspeed chips. Similarly, TIMER_INTR_STATE register (Base Address of Timer + 0x34) is not interrupt status register on ast2400 and ast2500 chips. Although there is no side effect to reset the register in fttmr010_common_init(), it's just misleading to do so. Besides, "count_down" is renamed to "is_aspeed" in "fttmr010" structure, and more comments are added so the code is more readble. Signed-off-by: Tao Ren Reviewed-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 73 +++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 31 deletions(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index cf93f6419b51..fadff7915dd9 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -21,7 +21,7 @@ #include /* - * Register definitions for the timers + * Register definitions common for all the timer variants. */ #define TIMER1_COUNT (0x00) #define TIMER1_LOAD (0x04) @@ -36,9 +36,10 @@ #define TIMER3_MATCH1 (0x28) #define TIMER3_MATCH2 (0x2c) #define TIMER_CR (0x30) -#define TIMER_INTR_STATE (0x34) -#define TIMER_INTR_MASK (0x38) +/* + * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers. + */ #define TIMER_1_CR_ENABLE BIT(0) #define TIMER_1_CR_CLOCK BIT(1) #define TIMER_1_CR_INT BIT(2) @@ -53,8 +54,9 @@ #define TIMER_3_CR_UPDOWN BIT(11) /* - * The Aspeed AST2400 moves bits around in the control register - * and lacks bits for setting the timer to count upwards. + * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers. + * The aspeed timers move bits around in the control register and lacks + * bits for setting the timer to count upwards. */ #define TIMER_1_CR_ASPEED_ENABLE BIT(0) #define TIMER_1_CR_ASPEED_CLOCK BIT(1) @@ -66,6 +68,18 @@ #define TIMER_3_CR_ASPEED_CLOCK BIT(9) #define TIMER_3_CR_ASPEED_INT BIT(10) +/* + * Interrupt status/mask register definitions for fttmr010/gemini/moxart + * timers. + * The registers don't exist and they are not needed on aspeed timers + * because: + * - aspeed timer overflow interrupt is controlled by bits in Control + * Register (TMC30). + * - aspeed timers always generate interrupt when either one of the + * Match registers equals to Status register. + */ +#define TIMER_INTR_STATE (0x34) +#define TIMER_INTR_MASK (0x38) #define TIMER_1_INT_MATCH1 BIT(0) #define TIMER_1_INT_MATCH2 BIT(1) #define TIMER_1_INT_OVERFLOW BIT(2) @@ -80,7 +94,7 @@ struct fttmr010 { void __iomem *base; unsigned int tick_rate; - bool count_down; + bool is_aspeed; u32 t1_enable_val; struct clock_event_device clkevt; #ifdef CONFIG_ARM @@ -130,7 +144,7 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, cr &= ~fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); - if (fttmr010->count_down) { + if (fttmr010->is_aspeed) { /* * ASPEED Timer Controller will load TIMER1_LOAD register * into TIMER1_COUNT register when the timer is re-enabled. @@ -175,16 +189,17 @@ static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) /* Setup counter start from 0 or ~0 */ writel(0, fttmr010->base + TIMER1_COUNT); - if (fttmr010->count_down) + if (fttmr010->is_aspeed) { writel(~0, fttmr010->base + TIMER1_LOAD); - else + } else { writel(0, fttmr010->base + TIMER1_LOAD); - /* Enable interrupt */ - cr = readl(fttmr010->base + TIMER_INTR_MASK); - cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); - cr |= TIMER_1_INT_MATCH1; - writel(cr, fttmr010->base + TIMER_INTR_MASK); + /* Enable interrupt */ + cr = readl(fttmr010->base + TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_MATCH1; + writel(cr, fttmr010->base + TIMER_INTR_MASK); + } return 0; } @@ -201,9 +216,8 @@ static int fttmr010_timer_set_periodic(struct clock_event_device *evt) writel(cr, fttmr010->base + TIMER_CR); /* Setup timer to fire at 1/HZ intervals. */ - if (fttmr010->count_down) { + if (fttmr010->is_aspeed) { writel(period, fttmr010->base + TIMER1_LOAD); - writel(0, fttmr010->base + TIMER1_MATCH1); } else { cr = 0xffffffff - (period - 1); writel(cr, fttmr010->base + TIMER1_COUNT); @@ -281,23 +295,21 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) } /* - * The Aspeed AST2400 moves bits around in the control register, - * otherwise it works the same. + * The Aspeed timers move bits around in the control register. */ if (is_aspeed) { fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | TIMER_1_CR_ASPEED_INT; - /* Downward not available */ - fttmr010->count_down = true; + fttmr010->is_aspeed = true; } else { fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; - } - /* - * Reset the interrupt mask and status - */ - writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); - writel(0, fttmr010->base + TIMER_INTR_STATE); + /* + * Reset the interrupt mask and status + */ + writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); + writel(0, fttmr010->base + TIMER_INTR_STATE); + } /* * Enable timer 1 count up, timer 2 count up, except on Aspeed, @@ -306,9 +318,8 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) if (is_aspeed) val = TIMER_2_CR_ASPEED_ENABLE; else { - val = TIMER_2_CR_ENABLE; - if (!fttmr010->count_down) - val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN; + val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN | + TIMER_2_CR_UPDOWN; } writel(val, fttmr010->base + TIMER_CR); @@ -321,7 +332,7 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) writel(0, fttmr010->base + TIMER2_MATCH1); writel(0, fttmr010->base + TIMER2_MATCH2); - if (fttmr010->count_down) { + if (fttmr010->is_aspeed) { writel(~0, fttmr010->base + TIMER2_LOAD); clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, "FTTMR010-TIMER2", @@ -371,7 +382,7 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) #ifdef CONFIG_ARM /* Also use this timer for delays */ - if (fttmr010->count_down) + if (fttmr010->is_aspeed) fttmr010->delay_timer.read_current_timer = fttmr010_read_current_timer_down; else -- cgit v1.2.3 From 4f352d1fc5a8d3220e29766a26172eff34867014 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 7 Dec 2018 06:05:36 +0000 Subject: clocksource/drivers/timer-imx-tpm: Specify clock name for timer-of i.MX TPM needs "ipg" clock for register access and "per" clock for timer function, the driver gets "ipg" clock by searching the clock name, but timer-of initialization will get first clock in device tree TPM node since no clock name specified in of_clk, that means the "per" clock MUST be the first clock entry in device tree TPM node, this patch specifies clock name for of_clk to avoid this restriction, it makes TPM driver work properly with different sequence of clock entries in device tree TPM node. Signed-off-by: Anson Huang Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-imx-tpm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c index c3dd4d2f2a6e..c1d52d5264c2 100644 --- a/drivers/clocksource/timer-imx-tpm.c +++ b/drivers/clocksource/timer-imx-tpm.c @@ -139,6 +139,9 @@ static struct timer_of to_tpm = { .handler = tpm_timer_interrupt, .flags = IRQF_TIMER | IRQF_IRQPOLL, }, + .of_clk = { + .name = "per", + }, }; static int __init tpm_clocksource_init(void) -- cgit v1.2.3 From 92e0d143fdef1faa7560c93fb0d6cd6c61da88ee Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 4 Dec 2018 15:59:52 +0530 Subject: clocksource/drivers/riscv_timer: Provide the sched_clock Currently, we don't have a sched_clock registered for RISC-V systems. This means Linux time keeping will use jiffies (running at HZ) as the default sched_clock. To avoid this, we explicity provide sched_clock using RISC-V rdtime instruction (similar to riscv_timer clocksource). Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/riscv_timer.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c57b156f49a2..a4ae339e0101 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -599,7 +599,7 @@ config ATCPIT100_TIMER config RISCV_TIMER bool "Timer for the RISC-V platform" - depends on RISCV + depends on GENERIC_SCHED_CLOCK && RISCV default y select TIMER_PROBE select TIMER_OF diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c index 084e97dc10ed..431892200a08 100644 --- a/drivers/clocksource/riscv_timer.c +++ b/drivers/clocksource/riscv_timer.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,11 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) return get_cycles64(); } +static u64 riscv_sched_clock(void) +{ + return get_cycles64(); +} + static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { .name = "riscv_clocksource", .rating = 300, @@ -97,6 +103,9 @@ static int __init riscv_timer_init_dt(struct device_node *n) cs = per_cpu_ptr(&riscv_clocksource, cpuid); clocksource_register_hz(cs, riscv_timebase); + sched_clock_register(riscv_sched_clock, + BITS_PER_LONG, riscv_timebase); + error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, "clockevents/riscv/timer:starting", riscv_timer_starting_cpu, riscv_timer_dying_cpu); -- cgit v1.2.3 From 3d42b32b1d6bdee161f6d629fc850fdf0c0fb2a1 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Sun, 9 Dec 2018 17:34:04 +0100 Subject: clocksource/drivers/riscv: Change name riscv_timer to timer-riscv In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Reviewed-by: Palmer Dabbelt Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/riscv_timer.c | 118 -------------------------------------- drivers/clocksource/timer-riscv.c | 118 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 119 insertions(+), 119 deletions(-) delete mode 100644 drivers/clocksource/riscv_timer.c create mode 100644 drivers/clocksource/timer-riscv.c (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd9138104568..ddf697b29df9 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -78,6 +78,6 @@ obj-$(CONFIG_H8300_TPU) += h8300_tpu.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o -obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o +obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c deleted file mode 100644 index 431892200a08..000000000000 --- a/drivers/clocksource/riscv_timer.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012 Regents of the University of California - * Copyright (C) 2017 SiFive - */ -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * All RISC-V systems have a timer attached to every hart. These timers can be - * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup - * events. In order to abstract the architecture-specific timer reading and - * setting functions away from the clock event insertion code, we provide - * function pointers to the clockevent subsystem that perform two basic - * operations: rdtime() reads the timer on the current CPU, and - * next_event(delta) sets the next timer event to 'delta' cycles in the future. - * As the timers are inherently a per-cpu resource, these callbacks perform - * operations on the current hart. There is guaranteed to be exactly one timer - * per hart on all RISC-V systems. - */ - -static int riscv_clock_next_event(unsigned long delta, - struct clock_event_device *ce) -{ - csr_set(sie, SIE_STIE); - sbi_set_timer(get_cycles64() + delta); - return 0; -} - -static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { - .name = "riscv_timer_clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 100, - .set_next_event = riscv_clock_next_event, -}; - -/* - * It is guaranteed that all the timers across all the harts are synchronized - * within one tick of each other, so while this could technically go - * backwards when hopping between CPUs, practically it won't happen. - */ -static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) -{ - return get_cycles64(); -} - -static u64 riscv_sched_clock(void) -{ - return get_cycles64(); -} - -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { - .name = "riscv_clocksource", - .rating = 300, - .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .read = riscv_clocksource_rdtime, -}; - -static int riscv_timer_starting_cpu(unsigned int cpu) -{ - struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); - - ce->cpumask = cpumask_of(cpu); - clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); - - csr_set(sie, SIE_STIE); - return 0; -} - -static int riscv_timer_dying_cpu(unsigned int cpu) -{ - csr_clear(sie, SIE_STIE); - return 0; -} - -/* called directly from the low-level interrupt handler */ -void riscv_timer_interrupt(void) -{ - struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event); - - csr_clear(sie, SIE_STIE); - evdev->event_handler(evdev); -} - -static int __init riscv_timer_init_dt(struct device_node *n) -{ - int cpuid, hartid, error; - struct clocksource *cs; - - hartid = riscv_of_processor_hartid(n); - cpuid = riscv_hartid_to_cpuid(hartid); - - if (cpuid != smp_processor_id()) - return 0; - - cs = per_cpu_ptr(&riscv_clocksource, cpuid); - clocksource_register_hz(cs, riscv_timebase); - - sched_clock_register(riscv_sched_clock, - BITS_PER_LONG, riscv_timebase); - - error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, - "clockevents/riscv/timer:starting", - riscv_timer_starting_cpu, riscv_timer_dying_cpu); - if (error) - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); - return error; -} - -TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c new file mode 100644 index 000000000000..431892200a08 --- /dev/null +++ b/drivers/clocksource/timer-riscv.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * All RISC-V systems have a timer attached to every hart. These timers can be + * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup + * events. In order to abstract the architecture-specific timer reading and + * setting functions away from the clock event insertion code, we provide + * function pointers to the clockevent subsystem that perform two basic + * operations: rdtime() reads the timer on the current CPU, and + * next_event(delta) sets the next timer event to 'delta' cycles in the future. + * As the timers are inherently a per-cpu resource, these callbacks perform + * operations on the current hart. There is guaranteed to be exactly one timer + * per hart on all RISC-V systems. + */ + +static int riscv_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + csr_set(sie, SIE_STIE); + sbi_set_timer(get_cycles64() + delta); + return 0; +} + +static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = { + .name = "riscv_timer_clockevent", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 100, + .set_next_event = riscv_clock_next_event, +}; + +/* + * It is guaranteed that all the timers across all the harts are synchronized + * within one tick of each other, so while this could technically go + * backwards when hopping between CPUs, practically it won't happen. + */ +static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs) +{ + return get_cycles64(); +} + +static u64 riscv_sched_clock(void) +{ + return get_cycles64(); +} + +static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { + .name = "riscv_clocksource", + .rating = 300, + .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .read = riscv_clocksource_rdtime, +}; + +static int riscv_timer_starting_cpu(unsigned int cpu) +{ + struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); + + ce->cpumask = cpumask_of(cpu); + clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); + + csr_set(sie, SIE_STIE); + return 0; +} + +static int riscv_timer_dying_cpu(unsigned int cpu) +{ + csr_clear(sie, SIE_STIE); + return 0; +} + +/* called directly from the low-level interrupt handler */ +void riscv_timer_interrupt(void) +{ + struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event); + + csr_clear(sie, SIE_STIE); + evdev->event_handler(evdev); +} + +static int __init riscv_timer_init_dt(struct device_node *n) +{ + int cpuid, hartid, error; + struct clocksource *cs; + + hartid = riscv_of_processor_hartid(n); + cpuid = riscv_hartid_to_cpuid(hartid); + + if (cpuid != smp_processor_id()) + return 0; + + cs = per_cpu_ptr(&riscv_clocksource, cpuid); + clocksource_register_hz(cs, riscv_timebase); + + sched_clock_register(riscv_sched_clock, + BITS_PER_LONG, riscv_timebase); + + error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING, + "clockevents/riscv/timer:starting", + riscv_timer_starting_cpu, riscv_timer_dying_cpu); + if (error) + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", + error, cpuid); + return error; +} + +TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); -- cgit v1.2.3 From 2d3bc644dd161c6c3e92dac74a4112c0411d4698 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Sun, 9 Dec 2018 17:35:44 +0100 Subject: clocksource/drivers/rockchip: Change name rockchip_timer to timer-rockchip In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/rockchip_timer.c | 307 ----------------------------------- drivers/clocksource/timer-rockchip.c | 307 +++++++++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+), 308 deletions(-) delete mode 100644 drivers/clocksource/rockchip_timer.c create mode 100644 drivers/clocksource/timer-rockchip.c (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ddf697b29df9..9d0c0fa0d69b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -20,7 +20,7 @@ obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o -obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o +obj-$(CONFIG_ROCKCHIP_TIMER) += timer-rockchip.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o obj-$(CONFIG_ARMADA_370_XP_TIMER) += timer-armada-370-xp.o diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c deleted file mode 100644 index 33f370dbd0d6..000000000000 --- a/drivers/clocksource/rockchip_timer.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Rockchip timer support - * - * Copyright (C) Daniel Lezcano - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TIMER_NAME "rk_timer" - -#define TIMER_LOAD_COUNT0 0x00 -#define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CURRENT_VALUE0 0x08 -#define TIMER_CURRENT_VALUE1 0x0C -#define TIMER_CONTROL_REG3288 0x10 -#define TIMER_CONTROL_REG3399 0x1c -#define TIMER_INT_STATUS 0x18 - -#define TIMER_DISABLE 0x0 -#define TIMER_ENABLE 0x1 -#define TIMER_MODE_FREE_RUNNING (0 << 1) -#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1) -#define TIMER_INT_UNMASK (1 << 2) - -struct rk_timer { - void __iomem *base; - void __iomem *ctrl; - struct clk *clk; - struct clk *pclk; - u32 freq; - int irq; -}; - -struct rk_clkevt { - struct clock_event_device ce; - struct rk_timer timer; -}; - -static struct rk_clkevt *rk_clkevt; -static struct rk_timer *rk_clksrc; - -static inline struct rk_timer *rk_timer(struct clock_event_device *ce) -{ - return &container_of(ce, struct rk_clkevt, ce)->timer; -} - -static inline void rk_timer_disable(struct rk_timer *timer) -{ - writel_relaxed(TIMER_DISABLE, timer->ctrl); -} - -static inline void rk_timer_enable(struct rk_timer *timer, u32 flags) -{ - writel_relaxed(TIMER_ENABLE | flags, timer->ctrl); -} - -static void rk_timer_update_counter(unsigned long cycles, - struct rk_timer *timer) -{ - writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); - writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1); -} - -static void rk_timer_interrupt_clear(struct rk_timer *timer) -{ - writel_relaxed(1, timer->base + TIMER_INT_STATUS); -} - -static inline int rk_timer_set_next_event(unsigned long cycles, - struct clock_event_device *ce) -{ - struct rk_timer *timer = rk_timer(ce); - - rk_timer_disable(timer); - rk_timer_update_counter(cycles, timer); - rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT | - TIMER_INT_UNMASK); - return 0; -} - -static int rk_timer_shutdown(struct clock_event_device *ce) -{ - struct rk_timer *timer = rk_timer(ce); - - rk_timer_disable(timer); - return 0; -} - -static int rk_timer_set_periodic(struct clock_event_device *ce) -{ - struct rk_timer *timer = rk_timer(ce); - - rk_timer_disable(timer); - rk_timer_update_counter(timer->freq / HZ - 1, timer); - rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK); - return 0; -} - -static irqreturn_t rk_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *ce = dev_id; - struct rk_timer *timer = rk_timer(ce); - - rk_timer_interrupt_clear(timer); - - if (clockevent_state_oneshot(ce)) - rk_timer_disable(timer); - - ce->event_handler(ce); - - return IRQ_HANDLED; -} - -static u64 notrace rk_timer_sched_read(void) -{ - return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0); -} - -static int __init -rk_timer_probe(struct rk_timer *timer, struct device_node *np) -{ - struct clk *timer_clk; - struct clk *pclk; - int ret = -EINVAL, irq; - u32 ctrl_reg = TIMER_CONTROL_REG3288; - - timer->base = of_iomap(np, 0); - if (!timer->base) { - pr_err("Failed to get base address for '%s'\n", TIMER_NAME); - return -ENXIO; - } - - if (of_device_is_compatible(np, "rockchip,rk3399-timer")) - ctrl_reg = TIMER_CONTROL_REG3399; - - timer->ctrl = timer->base + ctrl_reg; - - pclk = of_clk_get_by_name(np, "pclk"); - if (IS_ERR(pclk)) { - ret = PTR_ERR(pclk); - pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); - goto out_unmap; - } - - ret = clk_prepare_enable(pclk); - if (ret) { - pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); - goto out_unmap; - } - timer->pclk = pclk; - - timer_clk = of_clk_get_by_name(np, "timer"); - if (IS_ERR(timer_clk)) { - ret = PTR_ERR(timer_clk); - pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME); - goto out_timer_clk; - } - - ret = clk_prepare_enable(timer_clk); - if (ret) { - pr_err("Failed to enable timer clock\n"); - goto out_timer_clk; - } - timer->clk = timer_clk; - - timer->freq = clk_get_rate(timer_clk); - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME); - goto out_irq; - } - timer->irq = irq; - - rk_timer_interrupt_clear(timer); - rk_timer_disable(timer); - return 0; - -out_irq: - clk_disable_unprepare(timer_clk); -out_timer_clk: - clk_disable_unprepare(pclk); -out_unmap: - iounmap(timer->base); - - return ret; -} - -static void __init rk_timer_cleanup(struct rk_timer *timer) -{ - clk_disable_unprepare(timer->clk); - clk_disable_unprepare(timer->pclk); - iounmap(timer->base); -} - -static int __init rk_clkevt_init(struct device_node *np) -{ - struct clock_event_device *ce; - int ret = -EINVAL; - - rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL); - if (!rk_clkevt) { - ret = -ENOMEM; - goto out; - } - - ret = rk_timer_probe(&rk_clkevt->timer, np); - if (ret) - goto out_probe; - - ce = &rk_clkevt->ce; - ce->name = TIMER_NAME; - ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_DYNIRQ; - ce->set_next_event = rk_timer_set_next_event; - ce->set_state_shutdown = rk_timer_shutdown; - ce->set_state_periodic = rk_timer_set_periodic; - ce->irq = rk_clkevt->timer.irq; - ce->cpumask = cpu_possible_mask; - ce->rating = 250; - - ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER, - TIMER_NAME, ce); - if (ret) { - pr_err("Failed to initialize '%s': %d\n", - TIMER_NAME, ret); - goto out_irq; - } - - clockevents_config_and_register(&rk_clkevt->ce, - rk_clkevt->timer.freq, 1, UINT_MAX); - return 0; - -out_irq: - rk_timer_cleanup(&rk_clkevt->timer); -out_probe: - kfree(rk_clkevt); -out: - /* Leave rk_clkevt not NULL to prevent future init */ - rk_clkevt = ERR_PTR(ret); - return ret; -} - -static int __init rk_clksrc_init(struct device_node *np) -{ - int ret = -EINVAL; - - rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL); - if (!rk_clksrc) { - ret = -ENOMEM; - goto out; - } - - ret = rk_timer_probe(rk_clksrc, np); - if (ret) - goto out_probe; - - rk_timer_update_counter(UINT_MAX, rk_clksrc); - rk_timer_enable(rk_clksrc, 0); - - ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0, - TIMER_NAME, rk_clksrc->freq, 250, 32, - clocksource_mmio_readl_down); - if (ret) { - pr_err("Failed to register clocksource\n"); - goto out_clocksource; - } - - sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq); - return 0; - -out_clocksource: - rk_timer_cleanup(rk_clksrc); -out_probe: - kfree(rk_clksrc); -out: - /* Leave rk_clksrc not NULL to prevent future init */ - rk_clksrc = ERR_PTR(ret); - return ret; -} - -static int __init rk_timer_init(struct device_node *np) -{ - if (!rk_clkevt) - return rk_clkevt_init(np); - - if (!rk_clksrc) - return rk_clksrc_init(np); - - pr_err("Too many timer definitions for '%s'\n", TIMER_NAME); - return -EINVAL; -} - -TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init); -TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init); diff --git a/drivers/clocksource/timer-rockchip.c b/drivers/clocksource/timer-rockchip.c new file mode 100644 index 000000000000..33f370dbd0d6 --- /dev/null +++ b/drivers/clocksource/timer-rockchip.c @@ -0,0 +1,307 @@ +/* + * Rockchip timer support + * + * Copyright (C) Daniel Lezcano + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TIMER_NAME "rk_timer" + +#define TIMER_LOAD_COUNT0 0x00 +#define TIMER_LOAD_COUNT1 0x04 +#define TIMER_CURRENT_VALUE0 0x08 +#define TIMER_CURRENT_VALUE1 0x0C +#define TIMER_CONTROL_REG3288 0x10 +#define TIMER_CONTROL_REG3399 0x1c +#define TIMER_INT_STATUS 0x18 + +#define TIMER_DISABLE 0x0 +#define TIMER_ENABLE 0x1 +#define TIMER_MODE_FREE_RUNNING (0 << 1) +#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1) +#define TIMER_INT_UNMASK (1 << 2) + +struct rk_timer { + void __iomem *base; + void __iomem *ctrl; + struct clk *clk; + struct clk *pclk; + u32 freq; + int irq; +}; + +struct rk_clkevt { + struct clock_event_device ce; + struct rk_timer timer; +}; + +static struct rk_clkevt *rk_clkevt; +static struct rk_timer *rk_clksrc; + +static inline struct rk_timer *rk_timer(struct clock_event_device *ce) +{ + return &container_of(ce, struct rk_clkevt, ce)->timer; +} + +static inline void rk_timer_disable(struct rk_timer *timer) +{ + writel_relaxed(TIMER_DISABLE, timer->ctrl); +} + +static inline void rk_timer_enable(struct rk_timer *timer, u32 flags) +{ + writel_relaxed(TIMER_ENABLE | flags, timer->ctrl); +} + +static void rk_timer_update_counter(unsigned long cycles, + struct rk_timer *timer) +{ + writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0); + writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1); +} + +static void rk_timer_interrupt_clear(struct rk_timer *timer) +{ + writel_relaxed(1, timer->base + TIMER_INT_STATUS); +} + +static inline int rk_timer_set_next_event(unsigned long cycles, + struct clock_event_device *ce) +{ + struct rk_timer *timer = rk_timer(ce); + + rk_timer_disable(timer); + rk_timer_update_counter(cycles, timer); + rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT | + TIMER_INT_UNMASK); + return 0; +} + +static int rk_timer_shutdown(struct clock_event_device *ce) +{ + struct rk_timer *timer = rk_timer(ce); + + rk_timer_disable(timer); + return 0; +} + +static int rk_timer_set_periodic(struct clock_event_device *ce) +{ + struct rk_timer *timer = rk_timer(ce); + + rk_timer_disable(timer); + rk_timer_update_counter(timer->freq / HZ - 1, timer); + rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK); + return 0; +} + +static irqreturn_t rk_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *ce = dev_id; + struct rk_timer *timer = rk_timer(ce); + + rk_timer_interrupt_clear(timer); + + if (clockevent_state_oneshot(ce)) + rk_timer_disable(timer); + + ce->event_handler(ce); + + return IRQ_HANDLED; +} + +static u64 notrace rk_timer_sched_read(void) +{ + return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0); +} + +static int __init +rk_timer_probe(struct rk_timer *timer, struct device_node *np) +{ + struct clk *timer_clk; + struct clk *pclk; + int ret = -EINVAL, irq; + u32 ctrl_reg = TIMER_CONTROL_REG3288; + + timer->base = of_iomap(np, 0); + if (!timer->base) { + pr_err("Failed to get base address for '%s'\n", TIMER_NAME); + return -ENXIO; + } + + if (of_device_is_compatible(np, "rockchip,rk3399-timer")) + ctrl_reg = TIMER_CONTROL_REG3399; + + timer->ctrl = timer->base + ctrl_reg; + + pclk = of_clk_get_by_name(np, "pclk"); + if (IS_ERR(pclk)) { + ret = PTR_ERR(pclk); + pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); + goto out_unmap; + } + + ret = clk_prepare_enable(pclk); + if (ret) { + pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); + goto out_unmap; + } + timer->pclk = pclk; + + timer_clk = of_clk_get_by_name(np, "timer"); + if (IS_ERR(timer_clk)) { + ret = PTR_ERR(timer_clk); + pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME); + goto out_timer_clk; + } + + ret = clk_prepare_enable(timer_clk); + if (ret) { + pr_err("Failed to enable timer clock\n"); + goto out_timer_clk; + } + timer->clk = timer_clk; + + timer->freq = clk_get_rate(timer_clk); + + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + ret = -EINVAL; + pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME); + goto out_irq; + } + timer->irq = irq; + + rk_timer_interrupt_clear(timer); + rk_timer_disable(timer); + return 0; + +out_irq: + clk_disable_unprepare(timer_clk); +out_timer_clk: + clk_disable_unprepare(pclk); +out_unmap: + iounmap(timer->base); + + return ret; +} + +static void __init rk_timer_cleanup(struct rk_timer *timer) +{ + clk_disable_unprepare(timer->clk); + clk_disable_unprepare(timer->pclk); + iounmap(timer->base); +} + +static int __init rk_clkevt_init(struct device_node *np) +{ + struct clock_event_device *ce; + int ret = -EINVAL; + + rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL); + if (!rk_clkevt) { + ret = -ENOMEM; + goto out; + } + + ret = rk_timer_probe(&rk_clkevt->timer, np); + if (ret) + goto out_probe; + + ce = &rk_clkevt->ce; + ce->name = TIMER_NAME; + ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ; + ce->set_next_event = rk_timer_set_next_event; + ce->set_state_shutdown = rk_timer_shutdown; + ce->set_state_periodic = rk_timer_set_periodic; + ce->irq = rk_clkevt->timer.irq; + ce->cpumask = cpu_possible_mask; + ce->rating = 250; + + ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER, + TIMER_NAME, ce); + if (ret) { + pr_err("Failed to initialize '%s': %d\n", + TIMER_NAME, ret); + goto out_irq; + } + + clockevents_config_and_register(&rk_clkevt->ce, + rk_clkevt->timer.freq, 1, UINT_MAX); + return 0; + +out_irq: + rk_timer_cleanup(&rk_clkevt->timer); +out_probe: + kfree(rk_clkevt); +out: + /* Leave rk_clkevt not NULL to prevent future init */ + rk_clkevt = ERR_PTR(ret); + return ret; +} + +static int __init rk_clksrc_init(struct device_node *np) +{ + int ret = -EINVAL; + + rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL); + if (!rk_clksrc) { + ret = -ENOMEM; + goto out; + } + + ret = rk_timer_probe(rk_clksrc, np); + if (ret) + goto out_probe; + + rk_timer_update_counter(UINT_MAX, rk_clksrc); + rk_timer_enable(rk_clksrc, 0); + + ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0, + TIMER_NAME, rk_clksrc->freq, 250, 32, + clocksource_mmio_readl_down); + if (ret) { + pr_err("Failed to register clocksource\n"); + goto out_clocksource; + } + + sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq); + return 0; + +out_clocksource: + rk_timer_cleanup(rk_clksrc); +out_probe: + kfree(rk_clksrc); +out: + /* Leave rk_clksrc not NULL to prevent future init */ + rk_clksrc = ERR_PTR(ret); + return ret; +} + +static int __init rk_timer_init(struct device_node *np) +{ + if (!rk_clkevt) + return rk_clkevt_init(np); + + if (!rk_clksrc) + return rk_clksrc_init(np); + + pr_err("Too many timer definitions for '%s'\n", TIMER_NAME); + return -EINVAL; +} + +TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init); +TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init); -- cgit v1.2.3 From f155ae2c35c9ea8ce52f3ac670ced0eb23eded19 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Sun, 9 Dec 2018 17:37:13 +0100 Subject: clocksource/drivers/tegra20: Change name tegra20_timer to timer-tegra20 In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/tegra20_timer.c | 263 ------------------------------------ drivers/clocksource/timer-tegra20.c | 263 ++++++++++++++++++++++++++++++++++++ 3 files changed, 264 insertions(+), 264 deletions(-) delete mode 100644 drivers/clocksource/tegra20_timer.c create mode 100644 drivers/clocksource/timer-tegra20.c (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 9d0c0fa0d69b..e02c1af0c716 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -35,7 +35,7 @@ obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o -obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o +obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c deleted file mode 100644 index 4293943f4e2b..000000000000 --- a/drivers/clocksource/tegra20_timer.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (C) 2010 Google, Inc. - * - * Author: - * Colin Cross - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 - -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c - -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 - -#define TIMER_PTV 0x0 -#define TIMER_PCR 0x4 - -static void __iomem *timer_reg_base; -static void __iomem *rtc_base; - -static struct timespec64 persistent_ts; -static u64 persistent_ms, last_persistent_ms; - -static struct delay_timer tegra_delay_timer; - -#define timer_writel(value, reg) \ - writel_relaxed(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - readl_relaxed(timer_reg_base + (reg)) - -static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) -{ - u32 reg; - - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); - - return 0; -} - -static inline void timer_shutdown(struct clock_event_device *evt) -{ - timer_writel(0, TIMER3_BASE + TIMER_PTV); -} - -static int tegra_timer_shutdown(struct clock_event_device *evt) -{ - timer_shutdown(evt); - return 0; -} - -static int tegra_timer_set_periodic(struct clock_event_device *evt) -{ - u32 reg = 0xC0000000 | ((1000000 / HZ) - 1); - - timer_shutdown(evt); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); - return 0; -} - -static struct clock_event_device tegra_clockevent = { - .name = "timer0", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, -}; - -static u64 notrace tegra_read_sched_clock(void) -{ - return timer_readl(TIMERUS_CNTR_1US); -} - -/* - * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static u64 tegra_rtc_read_ms(void) -{ - u32 ms = readl(rtc_base + RTC_MILLISECONDS); - u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); - return (u64)s * MSEC_PER_SEC + ms; -} - -/* - * tegra_read_persistent_clock64 - Return time from a persistent clock. - * - * Reads the time from a source which isn't disabled during PM, the - * 32k sync timer. Convert the cycles elapsed since last read into - * nsecs and adds to a monotonically increasing timespec64. - * Care must be taken that this funciton is not called while the - * tegra_rtc driver could be executing to avoid race conditions - * on the RTC shadow register - */ -static void tegra_read_persistent_clock64(struct timespec64 *ts) -{ - u64 delta; - - last_persistent_ms = persistent_ms; - persistent_ms = tegra_rtc_read_ms(); - delta = persistent_ms - last_persistent_ms; - - timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); - *ts = persistent_ts; -} - -static unsigned long tegra_delay_timer_read_counter_long(void) -{ - return readl(timer_reg_base + TIMERUS_CNTR_1US); -} - -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction tegra_timer_irq = { - .name = "timer0", - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_interrupt, - .dev_id = &tegra_clockevent, -}; - -static int __init tegra20_init_timer(struct device_node *np) -{ - struct clk *clk; - unsigned long rate; - int ret; - - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers\n"); - return -ENXIO; - } - - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - return -EINVAL; - } - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); - rate = 12000000; - } else { - clk_prepare_enable(clk); - rate = clk_get_rate(clk); - } - - switch (rate) { - case 12000000: - timer_writel(0x000b, TIMERUS_USEC_CFG); - break; - case 13000000: - timer_writel(0x000c, TIMERUS_USEC_CFG); - break; - case 19200000: - timer_writel(0x045f, TIMERUS_USEC_CFG); - break; - case 26000000: - timer_writel(0x0019, TIMERUS_USEC_CFG); - break; - default: - WARN(1, "Unknown clock rate"); - } - - sched_clock_register(tegra_read_sched_clock, 32, 1000000); - - ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, - clocksource_mmio_readl_up); - if (ret) { - pr_err("Failed to register clocksource\n"); - return ret; - } - - tegra_delay_timer.read_current_timer = - tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = 1000000; - register_current_timer_delay(&tegra_delay_timer); - - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); - if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); - return ret; - } - - tegra_clockevent.cpumask = cpu_possible_mask; - tegra_clockevent.irq = tegra_timer_irq.irq; - clockevents_config_and_register(&tegra_clockevent, 1000000, - 0x1, 0x1fffffff); - - return 0; -} -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); - -static int __init tegra20_init_rtc(struct device_node *np) -{ - struct clk *clk; - - rtc_base = of_iomap(np, 0); - if (!rtc_base) { - pr_err("Can't map RTC registers\n"); - return -ENXIO; - } - - /* - * rtc registers are used by read_persistent_clock, keep the rtc clock - * enabled - */ - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) - pr_warn("Unable to get rtc-tegra clock\n"); - else - clk_prepare_enable(clk); - - return register_persistent_clock(tegra_read_persistent_clock64); -} -TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c new file mode 100644 index 000000000000..4293943f4e2b --- /dev/null +++ b/drivers/clocksource/timer-tegra20.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 + +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c + +#define TIMER1_BASE 0x0 +#define TIMER2_BASE 0x8 +#define TIMER3_BASE 0x50 +#define TIMER4_BASE 0x58 + +#define TIMER_PTV 0x0 +#define TIMER_PCR 0x4 + +static void __iomem *timer_reg_base; +static void __iomem *rtc_base; + +static struct timespec64 persistent_ts; +static u64 persistent_ms, last_persistent_ms; + +static struct delay_timer tegra_delay_timer; + +#define timer_writel(value, reg) \ + writel_relaxed(value, timer_reg_base + (reg)) +#define timer_readl(reg) \ + readl_relaxed(timer_reg_base + (reg)) + +static int tegra_timer_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + u32 reg; + + reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); + timer_writel(reg, TIMER3_BASE + TIMER_PTV); + + return 0; +} + +static inline void timer_shutdown(struct clock_event_device *evt) +{ + timer_writel(0, TIMER3_BASE + TIMER_PTV); +} + +static int tegra_timer_shutdown(struct clock_event_device *evt) +{ + timer_shutdown(evt); + return 0; +} + +static int tegra_timer_set_periodic(struct clock_event_device *evt) +{ + u32 reg = 0xC0000000 | ((1000000 / HZ) - 1); + + timer_shutdown(evt); + timer_writel(reg, TIMER3_BASE + TIMER_PTV); + return 0; +} + +static struct clock_event_device tegra_clockevent = { + .name = "timer0", + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_DYNIRQ, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, +}; + +static u64 notrace tegra_read_sched_clock(void) +{ + return timer_readl(TIMERUS_CNTR_1US); +} + +/* + * tegra_rtc_read - Reads the Tegra RTC registers + * Care must be taken that this funciton is not called while the + * tegra_rtc driver could be executing to avoid race conditions + * on the RTC shadow register + */ +static u64 tegra_rtc_read_ms(void) +{ + u32 ms = readl(rtc_base + RTC_MILLISECONDS); + u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; +} + +/* + * tegra_read_persistent_clock64 - Return time from a persistent clock. + * + * Reads the time from a source which isn't disabled during PM, the + * 32k sync timer. Convert the cycles elapsed since last read into + * nsecs and adds to a monotonically increasing timespec64. + * Care must be taken that this funciton is not called while the + * tegra_rtc driver could be executing to avoid race conditions + * on the RTC shadow register + */ +static void tegra_read_persistent_clock64(struct timespec64 *ts) +{ + u64 delta; + + last_persistent_ms = persistent_ms; + persistent_ms = tegra_rtc_read_ms(); + delta = persistent_ms - last_persistent_ms; + + timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); + *ts = persistent_ts; +} + +static unsigned long tegra_delay_timer_read_counter_long(void) +{ + return readl(timer_reg_base + TIMERUS_CNTR_1US); +} + +static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static struct irqaction tegra_timer_irq = { + .name = "timer0", + .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, + .handler = tegra_timer_interrupt, + .dev_id = &tegra_clockevent, +}; + +static int __init tegra20_init_timer(struct device_node *np) +{ + struct clk *clk; + unsigned long rate; + int ret; + + timer_reg_base = of_iomap(np, 0); + if (!timer_reg_base) { + pr_err("Can't map timer registers\n"); + return -ENXIO; + } + + tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); + if (tegra_timer_irq.irq <= 0) { + pr_err("Failed to map timer IRQ\n"); + return -EINVAL; + } + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); + rate = 12000000; + } else { + clk_prepare_enable(clk); + rate = clk_get_rate(clk); + } + + switch (rate) { + case 12000000: + timer_writel(0x000b, TIMERUS_USEC_CFG); + break; + case 13000000: + timer_writel(0x000c, TIMERUS_USEC_CFG); + break; + case 19200000: + timer_writel(0x045f, TIMERUS_USEC_CFG); + break; + case 26000000: + timer_writel(0x0019, TIMERUS_USEC_CFG); + break; + default: + WARN(1, "Unknown clock rate"); + } + + sched_clock_register(tegra_read_sched_clock, 32, 1000000); + + ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, 300, 32, + clocksource_mmio_readl_up); + if (ret) { + pr_err("Failed to register clocksource\n"); + return ret; + } + + tegra_delay_timer.read_current_timer = + tegra_delay_timer_read_counter_long; + tegra_delay_timer.freq = 1000000; + register_current_timer_delay(&tegra_delay_timer); + + ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); + if (ret) { + pr_err("Failed to register timer IRQ: %d\n", ret); + return ret; + } + + tegra_clockevent.cpumask = cpu_possible_mask; + tegra_clockevent.irq = tegra_timer_irq.irq; + clockevents_config_and_register(&tegra_clockevent, 1000000, + 0x1, 0x1fffffff); + + return 0; +} +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); + +static int __init tegra20_init_rtc(struct device_node *np) +{ + struct clk *clk; + + rtc_base = of_iomap(np, 0); + if (!rtc_base) { + pr_err("Can't map RTC registers\n"); + return -ENXIO; + } + + /* + * rtc registers are used by read_persistent_clock, keep the rtc clock + * enabled + */ + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) + pr_warn("Unable to get rtc-tegra clock\n"); + else + clk_prepare_enable(clk); + + return register_persistent_clock(tegra_read_persistent_clock64); +} +TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); -- cgit v1.2.3 From 493d09b7a7f5b23f176b00f944ad77e9e0c84672 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Sun, 9 Dec 2018 17:38:54 +0100 Subject: clocksource/drivers/sun4i: Change name sun4i_timer to timer-sun4i In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/sun4i_timer.c | 220 -------------------------------------- drivers/clocksource/timer-sun4i.c | 220 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 221 insertions(+), 221 deletions(-) delete mode 100644 drivers/clocksource/sun4i_timer.c create mode 100644 drivers/clocksource/timer-sun4i.c (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index e02c1af0c716..37732cb5710c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -32,7 +32,7 @@ obj-$(CONFIG_MXS_TIMER) += mxs_timer.o obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_U300_TIMER) += timer-u300.o -obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o +obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c deleted file mode 100644 index 6e0180aaf784..000000000000 --- a/drivers/clocksource/sun4i_timer.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Allwinner A1X SoCs timer handling. - * - * Copyright (C) 2012 Maxime Ripard - * - * Maxime Ripard - * - * Based on code from - * Allwinner Technology Co., Ltd. - * Benn Huang - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "timer-of.h" - -#define TIMER_IRQ_EN_REG 0x00 -#define TIMER_IRQ_EN(val) BIT(val) -#define TIMER_IRQ_ST_REG 0x04 -#define TIMER_CTL_REG(val) (0x10 * val + 0x10) -#define TIMER_CTL_ENABLE BIT(0) -#define TIMER_CTL_RELOAD BIT(1) -#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2) -#define TIMER_CTL_CLK_SRC_OSC24M (1) -#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) -#define TIMER_CTL_ONESHOT BIT(7) -#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14) -#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18) - -#define TIMER_SYNC_TICKS 3 - -/* - * When we disable a timer, we need to wait at least for 2 cycles of - * the timer source clock. We will use for that the clocksource timer - * that is already setup and runs at the same frequency than the other - * timers, and we never will be disabled. - */ -static void sun4i_clkevt_sync(void __iomem *base) -{ - u32 old = readl(base + TIMER_CNTVAL_REG(1)); - - while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) - cpu_relax(); -} - -static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer) -{ - u32 val = readl(base + TIMER_CTL_REG(timer)); - writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer)); - sun4i_clkevt_sync(base); -} - -static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer, - unsigned long delay) -{ - writel(delay, base + TIMER_INTVAL_REG(timer)); -} - -static void sun4i_clkevt_time_start(void __iomem *base, u8 timer, - bool periodic) -{ - u32 val = readl(base + TIMER_CTL_REG(timer)); - - if (periodic) - val &= ~TIMER_CTL_ONESHOT; - else - val |= TIMER_CTL_ONESHOT; - - writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - base + TIMER_CTL_REG(timer)); -} - -static int sun4i_clkevt_shutdown(struct clock_event_device *evt) -{ - struct timer_of *to = to_timer_of(evt); - - sun4i_clkevt_time_stop(timer_of_base(to), 0); - - return 0; -} - -static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt) -{ - struct timer_of *to = to_timer_of(evt); - - sun4i_clkevt_time_stop(timer_of_base(to), 0); - sun4i_clkevt_time_start(timer_of_base(to), 0, false); - - return 0; -} - -static int sun4i_clkevt_set_periodic(struct clock_event_device *evt) -{ - struct timer_of *to = to_timer_of(evt); - - sun4i_clkevt_time_stop(timer_of_base(to), 0); - sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to)); - sun4i_clkevt_time_start(timer_of_base(to), 0, true); - - return 0; -} - -static int sun4i_clkevt_next_event(unsigned long evt, - struct clock_event_device *clkevt) -{ - struct timer_of *to = to_timer_of(clkevt); - - sun4i_clkevt_time_stop(timer_of_base(to), 0); - sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS); - sun4i_clkevt_time_start(timer_of_base(to), 0, false); - - return 0; -} - -static void sun4i_timer_clear_interrupt(void __iomem *base) -{ - writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG); -} - -static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - struct timer_of *to = to_timer_of(evt); - - sun4i_timer_clear_interrupt(timer_of_base(to)); - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct timer_of to = { - .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE, - - .clkevt = { - .name = "sun4i_tick", - .rating = 350, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = sun4i_clkevt_shutdown, - .set_state_periodic = sun4i_clkevt_set_periodic, - .set_state_oneshot = sun4i_clkevt_set_oneshot, - .tick_resume = sun4i_clkevt_shutdown, - .set_next_event = sun4i_clkevt_next_event, - .cpumask = cpu_possible_mask, - }, - - .of_irq = { - .handler = sun4i_timer_interrupt, - .flags = IRQF_TIMER | IRQF_IRQPOLL, - }, -}; - -static u64 notrace sun4i_timer_sched_read(void) -{ - return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1)); -} - -static int __init sun4i_timer_init(struct device_node *node) -{ - int ret; - u32 val; - - ret = timer_of_init(node, &to); - if (ret) - return ret; - - writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1)); - writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | - TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), - timer_of_base(&to) + TIMER_CTL_REG(1)); - - /* - * sched_clock_register does not have priorities, and on sun6i and - * later there is a better sched_clock registered by arm_arch_timer.c - */ - if (of_machine_is_compatible("allwinner,sun4i-a10") || - of_machine_is_compatible("allwinner,sun5i-a13") || - of_machine_is_compatible("allwinner,sun5i-a10s")) - sched_clock_register(sun4i_timer_sched_read, 32, - timer_of_rate(&to)); - - ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1), - node->name, timer_of_rate(&to), 350, 32, - clocksource_mmio_readl_down); - if (ret) { - pr_err("Failed to register clocksource\n"); - return ret; - } - - writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), - timer_of_base(&to) + TIMER_CTL_REG(0)); - - /* Make sure timer is stopped before playing with interrupts */ - sun4i_clkevt_time_stop(timer_of_base(&to), 0); - - /* clear timer0 interrupt */ - sun4i_timer_clear_interrupt(timer_of_base(&to)); - - clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), - TIMER_SYNC_TICKS, 0xffffffff); - - /* Enable timer0 interrupt */ - val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); - writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG); - - return ret; -} -TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", - sun4i_timer_init); diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c new file mode 100644 index 000000000000..6e0180aaf784 --- /dev/null +++ b/drivers/clocksource/timer-sun4i.c @@ -0,0 +1,220 @@ +/* + * Allwinner A1X SoCs timer handling. + * + * Copyright (C) 2012 Maxime Ripard + * + * Maxime Ripard + * + * Based on code from + * Allwinner Technology Co., Ltd. + * Benn Huang + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +#define TIMER_IRQ_EN_REG 0x00 +#define TIMER_IRQ_EN(val) BIT(val) +#define TIMER_IRQ_ST_REG 0x04 +#define TIMER_CTL_REG(val) (0x10 * val + 0x10) +#define TIMER_CTL_ENABLE BIT(0) +#define TIMER_CTL_RELOAD BIT(1) +#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2) +#define TIMER_CTL_CLK_SRC_OSC24M (1) +#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) +#define TIMER_CTL_ONESHOT BIT(7) +#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14) +#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18) + +#define TIMER_SYNC_TICKS 3 + +/* + * When we disable a timer, we need to wait at least for 2 cycles of + * the timer source clock. We will use for that the clocksource timer + * that is already setup and runs at the same frequency than the other + * timers, and we never will be disabled. + */ +static void sun4i_clkevt_sync(void __iomem *base) +{ + u32 old = readl(base + TIMER_CNTVAL_REG(1)); + + while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS) + cpu_relax(); +} + +static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer) +{ + u32 val = readl(base + TIMER_CTL_REG(timer)); + writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer)); + sun4i_clkevt_sync(base); +} + +static void sun4i_clkevt_time_setup(void __iomem *base, u8 timer, + unsigned long delay) +{ + writel(delay, base + TIMER_INTVAL_REG(timer)); +} + +static void sun4i_clkevt_time_start(void __iomem *base, u8 timer, + bool periodic) +{ + u32 val = readl(base + TIMER_CTL_REG(timer)); + + if (periodic) + val &= ~TIMER_CTL_ONESHOT; + else + val |= TIMER_CTL_ONESHOT; + + writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, + base + TIMER_CTL_REG(timer)); +} + +static int sun4i_clkevt_shutdown(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + sun4i_clkevt_time_stop(timer_of_base(to), 0); + + return 0; +} + +static int sun4i_clkevt_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + sun4i_clkevt_time_stop(timer_of_base(to), 0); + sun4i_clkevt_time_start(timer_of_base(to), 0, false); + + return 0; +} + +static int sun4i_clkevt_set_periodic(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + sun4i_clkevt_time_stop(timer_of_base(to), 0); + sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to)); + sun4i_clkevt_time_start(timer_of_base(to), 0, true); + + return 0; +} + +static int sun4i_clkevt_next_event(unsigned long evt, + struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + sun4i_clkevt_time_stop(timer_of_base(to), 0); + sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS); + sun4i_clkevt_time_start(timer_of_base(to), 0, false); + + return 0; +} + +static void sun4i_timer_clear_interrupt(void __iomem *base) +{ + writel(TIMER_IRQ_EN(0), base + TIMER_IRQ_ST_REG); +} + +static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); + + sun4i_timer_clear_interrupt(timer_of_base(to)); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE, + + .clkevt = { + .name = "sun4i_tick", + .rating = 350, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = sun4i_clkevt_shutdown, + .set_state_periodic = sun4i_clkevt_set_periodic, + .set_state_oneshot = sun4i_clkevt_set_oneshot, + .tick_resume = sun4i_clkevt_shutdown, + .set_next_event = sun4i_clkevt_next_event, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .handler = sun4i_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static u64 notrace sun4i_timer_sched_read(void) +{ + return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1)); +} + +static int __init sun4i_timer_init(struct device_node *node) +{ + int ret; + u32 val; + + ret = timer_of_init(node, &to); + if (ret) + return ret; + + writel(~0, timer_of_base(&to) + TIMER_INTVAL_REG(1)); + writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | + TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), + timer_of_base(&to) + TIMER_CTL_REG(1)); + + /* + * sched_clock_register does not have priorities, and on sun6i and + * later there is a better sched_clock registered by arm_arch_timer.c + */ + if (of_machine_is_compatible("allwinner,sun4i-a10") || + of_machine_is_compatible("allwinner,sun5i-a13") || + of_machine_is_compatible("allwinner,sun5i-a10s")) + sched_clock_register(sun4i_timer_sched_read, 32, + timer_of_rate(&to)); + + ret = clocksource_mmio_init(timer_of_base(&to) + TIMER_CNTVAL_REG(1), + node->name, timer_of_rate(&to), 350, 32, + clocksource_mmio_readl_down); + if (ret) { + pr_err("Failed to register clocksource\n"); + return ret; + } + + writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), + timer_of_base(&to) + TIMER_CTL_REG(0)); + + /* Make sure timer is stopped before playing with interrupts */ + sun4i_clkevt_time_stop(timer_of_base(&to), 0); + + /* clear timer0 interrupt */ + sun4i_timer_clear_interrupt(timer_of_base(&to)); + + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + TIMER_SYNC_TICKS, 0xffffffff); + + /* Enable timer0 interrupt */ + val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG); + writel(val | TIMER_IRQ_EN(0), timer_of_base(&to) + TIMER_IRQ_EN_REG); + + return ret; +} +TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer", + sun4i_timer_init); -- cgit v1.2.3 From adab4ec3c2341d0939a3a83b81320a934c64c3e2 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Sun, 9 Dec 2018 17:40:14 +0100 Subject: clocksource/drivers/meson6: Change name meson6_timer timer-meson6 In order to unify the names in this directory, let's rename the driver to be prefixed with timer-* Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/meson6_timer.c | 220 ------------------------------------- drivers/clocksource/timer-meson6.c | 220 +++++++++++++++++++++++++++++++++++++ 3 files changed, 221 insertions(+), 221 deletions(-) delete mode 100644 drivers/clocksource/meson6_timer.c create mode 100644 drivers/clocksource/timer-meson6.c (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 37732cb5710c..f475927d5140 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o -obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o +obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c deleted file mode 100644 index 84bd9479c3f8..000000000000 --- a/drivers/clocksource/meson6_timer.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Amlogic Meson6 SoCs timer handling. - * - * Copyright (C) 2014 Carlo Caione - * - * Based on code from Amlogic, Inc - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_ARM -#include -#endif - -#define MESON_ISA_TIMER_MUX 0x00 -#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) -#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) -#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17) -#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16) -#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15) -#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14) -#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13) -#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12) -#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8) -#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0 -#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1 -#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2 -#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3 -#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4 -#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6) -#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4) -#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2) -#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0) -#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0 -#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1 -#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0 -#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3 - -#define MESON_ISA_TIMERA 0x04 -#define MESON_ISA_TIMERB 0x08 -#define MESON_ISA_TIMERC 0x0c -#define MESON_ISA_TIMERD 0x10 -#define MESON_ISA_TIMERE 0x14 - -static void __iomem *timer_base; - -#ifdef CONFIG_ARM -static unsigned long meson6_read_current_timer(void) -{ - return readl_relaxed(timer_base + MESON_ISA_TIMERE); -} - -static struct delay_timer meson6_delay_timer = { - .read_current_timer = meson6_read_current_timer, - .freq = 1000 * 1000, -}; -#endif - -static u64 notrace meson6_timer_sched_read(void) -{ - return (u64)readl(timer_base + MESON_ISA_TIMERE); -} - -static void meson6_clkevt_time_stop(void) -{ - u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); - - writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN, - timer_base + MESON_ISA_TIMER_MUX); -} - -static void meson6_clkevt_time_setup(unsigned long delay) -{ - writel(delay, timer_base + MESON_ISA_TIMERA); -} - -static void meson6_clkevt_time_start(bool periodic) -{ - u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); - - if (periodic) - val |= MESON_ISA_TIMER_MUX_TIMERA_MODE; - else - val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE; - - writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN, - timer_base + MESON_ISA_TIMER_MUX); -} - -static int meson6_shutdown(struct clock_event_device *evt) -{ - meson6_clkevt_time_stop(); - return 0; -} - -static int meson6_set_oneshot(struct clock_event_device *evt) -{ - meson6_clkevt_time_stop(); - meson6_clkevt_time_start(false); - return 0; -} - -static int meson6_set_periodic(struct clock_event_device *evt) -{ - meson6_clkevt_time_stop(); - meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1); - meson6_clkevt_time_start(true); - return 0; -} - -static int meson6_clkevt_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - meson6_clkevt_time_stop(); - meson6_clkevt_time_setup(evt); - meson6_clkevt_time_start(false); - - return 0; -} - -static struct clock_event_device meson6_clockevent = { - .name = "meson6_tick", - .rating = 400, - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = meson6_shutdown, - .set_state_periodic = meson6_set_periodic, - .set_state_oneshot = meson6_set_oneshot, - .tick_resume = meson6_shutdown, - .set_next_event = meson6_clkevt_next_event, -}; - -static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction meson6_timer_irq = { - .name = "meson6_timer", - .flags = IRQF_TIMER | IRQF_IRQPOLL, - .handler = meson6_timer_interrupt, - .dev_id = &meson6_clockevent, -}; - -static int __init meson6_timer_init(struct device_node *node) -{ - u32 val; - int ret, irq; - - timer_base = of_io_request_and_map(node, 0, "meson6-timer"); - if (IS_ERR(timer_base)) { - pr_err("Can't map registers\n"); - return -ENXIO; - } - - irq = irq_of_parse_and_map(node, 0); - if (irq <= 0) { - pr_err("Can't parse IRQ\n"); - return -EINVAL; - } - - /* Set 1us for timer E */ - val = readl(timer_base + MESON_ISA_TIMER_MUX); - val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK; - val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK, - MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US); - writel(val, timer_base + MESON_ISA_TIMER_MUX); - - sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC); - clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name, - 1000 * 1000, 300, 32, clocksource_mmio_readl_up); - - /* Timer A base 1us */ - val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK; - val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK, - MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US); - writel(val, timer_base + MESON_ISA_TIMER_MUX); - - /* Stop the timer A */ - meson6_clkevt_time_stop(); - - ret = setup_irq(irq, &meson6_timer_irq); - if (ret) { - pr_warn("failed to setup irq %d\n", irq); - return ret; - } - - meson6_clockevent.cpumask = cpu_possible_mask; - meson6_clockevent.irq = irq; - - clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, - 1, 0xfffe); - -#ifdef CONFIG_ARM - /* Also use MESON_ISA_TIMERE for delays */ - register_current_timer_delay(&meson6_delay_timer); -#endif - - return 0; -} -TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer", - meson6_timer_init); diff --git a/drivers/clocksource/timer-meson6.c b/drivers/clocksource/timer-meson6.c new file mode 100644 index 000000000000..84bd9479c3f8 --- /dev/null +++ b/drivers/clocksource/timer-meson6.c @@ -0,0 +1,220 @@ +/* + * Amlogic Meson6 SoCs timer handling. + * + * Copyright (C) 2014 Carlo Caione + * + * Based on code from Amlogic, Inc + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARM +#include +#endif + +#define MESON_ISA_TIMER_MUX 0x00 +#define MESON_ISA_TIMER_MUX_TIMERD_EN BIT(19) +#define MESON_ISA_TIMER_MUX_TIMERC_EN BIT(18) +#define MESON_ISA_TIMER_MUX_TIMERB_EN BIT(17) +#define MESON_ISA_TIMER_MUX_TIMERA_EN BIT(16) +#define MESON_ISA_TIMER_MUX_TIMERD_MODE BIT(15) +#define MESON_ISA_TIMER_MUX_TIMERC_MODE BIT(14) +#define MESON_ISA_TIMER_MUX_TIMERB_MODE BIT(13) +#define MESON_ISA_TIMER_MUX_TIMERA_MODE BIT(12) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK GENMASK(10, 8) +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_SYSTEM_CLOCK 0x0 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_10US 0x2 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_100US 0x3 +#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1MS 0x4 +#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK GENMASK(7, 6) +#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK GENMASK(5, 4) +#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK GENMASK(3, 2) +#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK GENMASK(1, 0) +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_10US 0x1 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_100US 0x0 +#define MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1MS 0x3 + +#define MESON_ISA_TIMERA 0x04 +#define MESON_ISA_TIMERB 0x08 +#define MESON_ISA_TIMERC 0x0c +#define MESON_ISA_TIMERD 0x10 +#define MESON_ISA_TIMERE 0x14 + +static void __iomem *timer_base; + +#ifdef CONFIG_ARM +static unsigned long meson6_read_current_timer(void) +{ + return readl_relaxed(timer_base + MESON_ISA_TIMERE); +} + +static struct delay_timer meson6_delay_timer = { + .read_current_timer = meson6_read_current_timer, + .freq = 1000 * 1000, +}; +#endif + +static u64 notrace meson6_timer_sched_read(void) +{ + return (u64)readl(timer_base + MESON_ISA_TIMERE); +} + +static void meson6_clkevt_time_stop(void) +{ + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); + + writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); +} + +static void meson6_clkevt_time_setup(unsigned long delay) +{ + writel(delay, timer_base + MESON_ISA_TIMERA); +} + +static void meson6_clkevt_time_start(bool periodic) +{ + u32 val = readl(timer_base + MESON_ISA_TIMER_MUX); + + if (periodic) + val |= MESON_ISA_TIMER_MUX_TIMERA_MODE; + else + val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE; + + writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN, + timer_base + MESON_ISA_TIMER_MUX); +} + +static int meson6_shutdown(struct clock_event_device *evt) +{ + meson6_clkevt_time_stop(); + return 0; +} + +static int meson6_set_oneshot(struct clock_event_device *evt) +{ + meson6_clkevt_time_stop(); + meson6_clkevt_time_start(false); + return 0; +} + +static int meson6_set_periodic(struct clock_event_device *evt) +{ + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1); + meson6_clkevt_time_start(true); + return 0; +} + +static int meson6_clkevt_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + meson6_clkevt_time_stop(); + meson6_clkevt_time_setup(evt); + meson6_clkevt_time_start(false); + + return 0; +} + +static struct clock_event_device meson6_clockevent = { + .name = "meson6_tick", + .rating = 400, + .features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = meson6_shutdown, + .set_state_periodic = meson6_set_periodic, + .set_state_oneshot = meson6_set_oneshot, + .tick_resume = meson6_shutdown, + .set_next_event = meson6_clkevt_next_event, +}; + +static irqreturn_t meson6_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction meson6_timer_irq = { + .name = "meson6_timer", + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = meson6_timer_interrupt, + .dev_id = &meson6_clockevent, +}; + +static int __init meson6_timer_init(struct device_node *node) +{ + u32 val; + int ret, irq; + + timer_base = of_io_request_and_map(node, 0, "meson6-timer"); + if (IS_ERR(timer_base)) { + pr_err("Can't map registers\n"); + return -ENXIO; + } + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) { + pr_err("Can't parse IRQ\n"); + return -EINVAL; + } + + /* Set 1us for timer E */ + val = readl(timer_base + MESON_ISA_TIMER_MUX); + val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); + + sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC); + clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name, + 1000 * 1000, 300, 32, clocksource_mmio_readl_up); + + /* Timer A base 1us */ + val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK; + val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK, + MESON_ISA_TIMER_MUX_TIMERABCD_INPUT_CLOCK_1US); + writel(val, timer_base + MESON_ISA_TIMER_MUX); + + /* Stop the timer A */ + meson6_clkevt_time_stop(); + + ret = setup_irq(irq, &meson6_timer_irq); + if (ret) { + pr_warn("failed to setup irq %d\n", irq); + return ret; + } + + meson6_clockevent.cpumask = cpu_possible_mask; + meson6_clockevent.irq = irq; + + clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC, + 1, 0xfffe); + +#ifdef CONFIG_ARM + /* Also use MESON_ISA_TIMERE for delays */ + register_current_timer_delay(&meson6_delay_timer); +#endif + + return 0; +} +TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer", + meson6_timer_init); -- cgit v1.2.3 From 7f83a1327962b9b3712866db8cbafbdee239cce4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 10 Dec 2018 23:05:46 +0530 Subject: clocksource/drivers/rda: Add clock driver for RDA8810PL SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add clock driver for RDA Micro RDA8810PL SoC supporting OSTIMER and HWTIMER. RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). Each timer provides optional interrupt support. In this driver, OSTIMER is used for clockevents and HWTIMER is used for clocksource. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 8 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-rda.c | 195 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 204 insertions(+) create mode 100644 drivers/clocksource/timer-rda.c (limited to 'drivers/clocksource') diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a4ae339e0101..a9e26f6a81a1 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -105,6 +105,14 @@ config OWL_TIMER help Enables the support for the Actions Semi Owl timer driver. +config RDA_TIMER + bool "RDA timer driver" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + select TIMER_OF + help + Enables the support for the RDA Micro timer driver. + config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index f475927d5140..cdd210ff89ea 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o +obj-$(CONFIG_RDA_TIMER) += timer-rda.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/timer-rda.c b/drivers/clocksource/timer-rda.c new file mode 100644 index 000000000000..fd1199c189bf --- /dev/null +++ b/drivers/clocksource/timer-rda.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RDA8810PL SoC timer driver + * + * Copyright RDA Microelectronics Company Limited + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + * + * RDA8810PL has two independent timers: OSTIMER (56 bit) and HWTIMER (64 bit). + * Each timer provides optional interrupt support. In this driver, OSTIMER is + * used for clockevents and HWTIMER is used for clocksource. + */ + +#include +#include + +#include "timer-of.h" + +#define RDA_OSTIMER_LOADVAL_L 0x000 +#define RDA_OSTIMER_CTRL 0x004 +#define RDA_HWTIMER_LOCKVAL_L 0x024 +#define RDA_HWTIMER_LOCKVAL_H 0x028 +#define RDA_TIMER_IRQ_MASK_SET 0x02c +#define RDA_TIMER_IRQ_MASK_CLR 0x030 +#define RDA_TIMER_IRQ_CLR 0x034 + +#define RDA_OSTIMER_CTRL_ENABLE BIT(24) +#define RDA_OSTIMER_CTRL_REPEAT BIT(28) +#define RDA_OSTIMER_CTRL_LOAD BIT(30) + +#define RDA_TIMER_IRQ_MASK_OSTIMER BIT(0) + +#define RDA_TIMER_IRQ_CLR_OSTIMER BIT(0) + +static int rda_ostimer_start(void __iomem *base, bool periodic, u64 cycles) +{ + u32 ctrl, load_l; + + load_l = (u32)cycles; + ctrl = ((cycles >> 32) & 0xffffff); + ctrl |= RDA_OSTIMER_CTRL_LOAD | RDA_OSTIMER_CTRL_ENABLE; + if (periodic) + ctrl |= RDA_OSTIMER_CTRL_REPEAT; + + /* Enable ostimer interrupt first */ + writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER, + base + RDA_TIMER_IRQ_MASK_SET); + + /* Write low 32 bits first, high 24 bits are with ctrl */ + writel_relaxed(load_l, base + RDA_OSTIMER_LOADVAL_L); + writel_relaxed(ctrl, base + RDA_OSTIMER_CTRL); + + return 0; +} + +static int rda_ostimer_stop(void __iomem *base) +{ + /* Disable ostimer interrupt first */ + writel_relaxed(RDA_TIMER_IRQ_MASK_OSTIMER, + base + RDA_TIMER_IRQ_MASK_CLR); + + writel_relaxed(0, base + RDA_OSTIMER_CTRL); + + return 0; +} + +static int rda_ostimer_set_state_shutdown(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + rda_ostimer_stop(timer_of_base(to)); + + return 0; +} + +static int rda_ostimer_set_state_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + + rda_ostimer_stop(timer_of_base(to)); + + return 0; +} + +static int rda_ostimer_set_state_periodic(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long cycles_per_jiffy; + + rda_ostimer_stop(timer_of_base(to)); + + cycles_per_jiffy = ((unsigned long long)NSEC_PER_SEC / HZ * + evt->mult) >> evt->shift; + rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy); + + return 0; +} + +static int rda_ostimer_tick_resume(struct clock_event_device *evt) +{ + return 0; +} + +static int rda_ostimer_set_next_event(unsigned long evt, + struct clock_event_device *ev) +{ + struct timer_of *to = to_timer_of(ev); + + rda_ostimer_start(timer_of_base(to), false, evt); + + return 0; +} + +static irqreturn_t rda_ostimer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + struct timer_of *to = to_timer_of(evt); + + /* clear timer int */ + writel_relaxed(RDA_TIMER_IRQ_CLR_OSTIMER, + timer_of_base(to) + RDA_TIMER_IRQ_CLR); + + if (evt->event_handler) + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct timer_of rda_ostimer_of = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE, + + .clkevt = { + .name = "rda-ostimer", + .rating = 250, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ, + .set_state_shutdown = rda_ostimer_set_state_shutdown, + .set_state_oneshot = rda_ostimer_set_state_oneshot, + .set_state_periodic = rda_ostimer_set_state_periodic, + .tick_resume = rda_ostimer_tick_resume, + .set_next_event = rda_ostimer_set_next_event, + }, + + .of_base = { + .name = "rda-timer", + .index = 0, + }, + + .of_irq = { + .name = "ostimer", + .handler = rda_ostimer_interrupt, + .flags = IRQF_TIMER, + }, +}; + +static u64 rda_hwtimer_read(struct clocksource *cs) +{ + void __iomem *base = timer_of_base(&rda_ostimer_of); + u32 lo, hi; + + /* Always read low 32 bits first */ + do { + lo = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_L); + hi = readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H); + } while (hi != readl_relaxed(base + RDA_HWTIMER_LOCKVAL_H)); + + return ((u64)hi << 32) | lo; +} + +static struct clocksource rda_hwtimer_clocksource = { + .name = "rda-timer", + .rating = 400, + .read = rda_hwtimer_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init rda_timer_init(struct device_node *np) +{ + unsigned long rate = 2000000; + int ret; + + ret = timer_of_init(np, &rda_ostimer_of); + if (ret) + return ret; + + clocksource_register_hz(&rda_hwtimer_clocksource, rate); + + clockevents_config_and_register(&rda_ostimer_of.clkevt, rate, + 0x2, UINT_MAX); + + return 0; +} + +TIMER_OF_DECLARE(rda8810pl, "rda,8810pl-timer", rda_timer_init); -- cgit v1.2.3