From b1f247714acb2a78452ba555807764b2c1115a40 Mon Sep 17 00:00:00 2001 From: Wang Hai Date: Wed, 30 Jun 2021 09:58:23 +0800 Subject: clk: stm32mp1: fix missing spin_lock_init() The driver allocates the spinlock but not initialize it. Use spin_lock_init() on it to initialize it correctly. Fixes: c392df194a2d ("clk: stm32mp1: move RCC reset controller into RCC clock driver") Reported-by: Hulk Robot Signed-off-by: Wang Hai Link: https://lore.kernel.org/r/20210630015824.2555840-1-wanghai38@huawei.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-stm32mp1.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 6adc625e79cb..256575bd29b9 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -2263,6 +2263,7 @@ static int stm32_rcc_reset_init(struct device *dev, void __iomem *base, if (!reset_data) return -ENOMEM; + spin_lock_init(&reset_data->lock); reset_data->membase = base; reset_data->rcdev.owner = THIS_MODULE; reset_data->rcdev.ops = &stm32_reset_ops; -- cgit v1.2.3 From b424f73b6c017f907fd4018bd109d62b237f7875 Mon Sep 17 00:00:00 2001 From: Wang Hai Date: Wed, 30 Jun 2021 10:03:22 +0800 Subject: clk: lmk04832: fix return value check in lmk04832_probe() In case of error, the function devm_kzalloc() and devm_kcalloc() return NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Reported-by: Hulk Robot Signed-off-by: Wang Hai Link: https://lore.kernel.org/r/20210630020322.2555946-1-wanghai38@huawei.com Reviewed-by: Liam Beguin Signed-off-by: Stephen Boyd --- drivers/clk/clk-lmk04832.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c index c1095e733220..246095b1ab45 100644 --- a/drivers/clk/clk-lmk04832.c +++ b/drivers/clk/clk-lmk04832.c @@ -1425,23 +1425,23 @@ static int lmk04832_probe(struct spi_device *spi) lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, sizeof(struct lmk_dclk), GFP_KERNEL); - if (IS_ERR(lmk->dclk)) { - ret = PTR_ERR(lmk->dclk); + if (!lmk->dclk) { + ret = -ENOMEM; goto err_disable_oscin; } lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, sizeof(*lmk->clkout), GFP_KERNEL); - if (IS_ERR(lmk->clkout)) { - ret = PTR_ERR(lmk->clkout); + if (!lmk->clkout) { + ret = -ENOMEM; goto err_disable_oscin; } lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, info->num_channels), GFP_KERNEL); - if (IS_ERR(lmk->clk_data)) { - ret = PTR_ERR(lmk->clk_data); + if (!lmk->clk_data) { + ret = -ENOMEM; goto err_disable_oscin; } -- cgit v1.2.3 From 2cdee50eda9d87f4fabba3df00caa4cc873f30ab Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 29 Jun 2021 11:29:56 +0100 Subject: clk: lmk04832: Fix spelling mistakes in dev_err messages and comments There are handful of spelling mistakes in two dev_err error messages and comments. Fix them. Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20210629102956.17901-1-colin.king@canonical.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-lmk04832.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c index 246095b1ab45..c7a3a029fb1e 100644 --- a/drivers/clk/clk-lmk04832.c +++ b/drivers/clk/clk-lmk04832.c @@ -519,7 +519,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate, vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r); if (vco_rate < 0) { - dev_err(lmk->dev, "PLL2 parmeters out of range\n"); + dev_err(lmk->dev, "PLL2 parameters out of range\n"); return vco_rate; } @@ -550,7 +550,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r); if (vco_rate < 0) { - dev_err(lmk->dev, "failed to determine PLL2 parmeters\n"); + dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); return vco_rate; } @@ -573,7 +573,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, /* * PLL2_N registers must be programmed after other PLL2 dividers are - * programed to ensure proper VCO frequency calibration + * programmed to ensure proper VCO frequency calibration */ ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, FIELD_GET(0x030000, n)); @@ -1120,7 +1120,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; } - /* Enable Duty Cycle Corretion */ + /* Enable Duty Cycle Correction */ if (dclk_div == 1) { ret = regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), -- cgit v1.2.3 From faa0e307948594b4379a86fff7fb2409067aed6f Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Tue, 22 Jun 2021 15:45:02 +0900 Subject: clk: k210: Fix k210_clk_set_parent() In k210_clk_set_parent(), add missing writel() call to update the mux register of a clock to change its parent. This also fixes a compilation warning with clang when compiling with W=1. Fixes: c6ca7616f7d5 ("clk: Add RISC-V Canaan Kendryte K210 clock driver") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Link: https://lore.kernel.org/r/20210622064502.14841-1-damien.lemoal@wdc.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-k210.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c index 6c84abf5b2e3..67a7cb3503c3 100644 --- a/drivers/clk/clk-k210.c +++ b/drivers/clk/clk-k210.c @@ -722,6 +722,7 @@ static int k210_clk_set_parent(struct clk_hw *hw, u8 index) reg |= BIT(cfg->mux_bit); else reg &= ~BIT(cfg->mux_bit); + writel(reg, ksc->regs + cfg->mux_reg); spin_unlock_irqrestore(&ksc->clk_lock, flags); return 0; -- cgit v1.2.3 From bbd7a6cc382f4317b08ba71151b23abf76fc4c34 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 28 Jun 2021 00:39:57 +0200 Subject: clk: divider: Add re-usable determine_rate implementations These are useful when running on 32-bit systems to increase the upper supported frequency limit. clk_ops.round_rate returns a signed long which limits the maximum rate on 32-bit systems to 2^31 (or approx. 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. To avoid code-duplication switch over divider_{ro_,}round_rate_parent to use the new divider_{ro_,}determine_rate functions. Reviewed-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-divider.c | 75 +++++++++++++++++++++++++++++++++++--------- include/linux/clk-provider.h | 6 ++++ 2 files changed, 67 insertions(+), 14 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 344997203f0e..87ba4966b0e8 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -343,16 +343,63 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent, return bestdiv; } +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags) +{ + int div; + + div = clk_divider_bestdiv(hw, req->best_parent_hw, req->rate, + &req->best_parent_rate, table, width, flags); + + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} +EXPORT_SYMBOL_GPL(divider_determine_rate); + +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val) +{ + int div; + + div = _get_div(table, val, flags, width); + + /* Even a read-only clock can propagate a rate change */ + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { + if (!req->best_parent_hw) + return -EINVAL; + + req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw, + req->rate * div); + } + + req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); + + return 0; +} +EXPORT_SYMBOL_GPL(divider_ro_determine_rate); + long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags) { - int div; + struct clk_rate_request req = { + .rate = rate, + .best_parent_rate = *prate, + .best_parent_hw = parent, + }; + int ret; - div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags); + ret = divider_determine_rate(hw, &req, table, width, flags); + if (ret) + return ret; - return DIV_ROUND_UP_ULL((u64)*prate, div); + *prate = req.best_parent_rate; + + return req.rate; } EXPORT_SYMBOL_GPL(divider_round_rate_parent); @@ -361,23 +408,23 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val) { - int div; - - div = _get_div(table, val, flags, width); + struct clk_rate_request req = { + .rate = rate, + .best_parent_rate = *prate, + .best_parent_hw = parent, + }; + int ret; - /* Even a read-only clock can propagate a rate change */ - if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { - if (!parent) - return -EINVAL; + ret = divider_ro_determine_rate(hw, &req, table, width, flags, val); + if (ret) + return ret; - *prate = clk_hw_round_rate(parent, rate * div); - } + *prate = req.best_parent_rate; - return DIV_ROUND_UP_ULL((u64)*prate, div); + return req.rate; } EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); - static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 162a2e5546a3..d83b829305c0 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -629,6 +629,12 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val); +int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags); +int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req, + const struct clk_div_table *table, u8 width, + unsigned long flags, unsigned int val); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); -- cgit v1.2.3 From db400ac1444b756030249ed4a35e53a68e557b59 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 28 Jun 2021 00:39:58 +0200 Subject: clk: divider: Switch from .round_rate to .determine_rate by default .determine_rate is meant to replace .round_rate. The former comes with a benefit which is especially relevant on 32-bit systems: since .determine_rate uses an "unsigned long" (compared to a "signed long" which is used by .round_rate) the maximum value on 32-bit systems increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz). Switch to a .determine_rate implementation by default so 32-bit systems can benefit from the increased maximum value as well as so we have one fewer user of .round_rate. Reviewed-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210627223959.188139-3-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd --- drivers/clk/clk-divider.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 87ba4966b0e8..9e05e81116af 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -425,8 +425,8 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, } EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); -static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_divider *divider = to_clk_divider(hw); @@ -437,13 +437,13 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, val = clk_div_readl(divider) >> divider->shift; val &= clk_div_mask(divider->width); - return divider_ro_round_rate(hw, rate, prate, divider->table, - divider->width, divider->flags, - val); + return divider_ro_determine_rate(hw, req, divider->table, + divider->width, + divider->flags, val); } - return divider_round_rate(hw, rate, prate, divider->table, - divider->width, divider->flags); + return divider_determine_rate(hw, req, divider->table, divider->width, + divider->flags); } int divider_get_val(unsigned long rate, unsigned long parent_rate, @@ -500,14 +500,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops clk_divider_ops = { .recalc_rate = clk_divider_recalc_rate, - .round_rate = clk_divider_round_rate, + .determine_rate = clk_divider_determine_rate, .set_rate = clk_divider_set_rate, }; EXPORT_SYMBOL_GPL(clk_divider_ops); const struct clk_ops clk_divider_ro_ops = { .recalc_rate = clk_divider_recalc_rate, - .round_rate = clk_divider_round_rate, + .determine_rate = clk_divider_determine_rate, }; EXPORT_SYMBOL_GPL(clk_divider_ro_ops); -- cgit v1.2.3 From e4c5ef6b9584a861210cf92955b7c8b1727688b9 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 28 Jun 2021 00:39:59 +0200 Subject: clk: meson: regmap: switch to determine_rate for the dividers This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Reviewed-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20210627223959.188139-4-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd --- drivers/clk/meson/clk-regmap.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index dcd1757cc5df..8ad8977cf1c2 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -75,8 +75,8 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, div->width); } -static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_regmap_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct clk_regmap *clk = to_clk_regmap(hw); struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); @@ -87,18 +87,17 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, if (div->flags & CLK_DIVIDER_READ_ONLY) { ret = regmap_read(clk->map, div->offset, &val); if (ret) - /* Gives a hint that something is wrong */ - return 0; + return ret; val >>= div->shift; val &= clk_div_mask(div->width); - return divider_ro_round_rate(hw, rate, prate, div->table, - div->width, div->flags, val); + return divider_ro_determine_rate(hw, req, div->table, + div->width, div->flags, val); } - return divider_round_rate(hw, rate, prate, div->table, div->width, - div->flags); + return divider_determine_rate(hw, req, div->table, div->width, + div->flags); } static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -123,14 +122,14 @@ static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops clk_regmap_divider_ops = { .recalc_rate = clk_regmap_div_recalc_rate, - .round_rate = clk_regmap_div_round_rate, + .determine_rate = clk_regmap_div_determine_rate, .set_rate = clk_regmap_div_set_rate, }; EXPORT_SYMBOL_GPL(clk_regmap_divider_ops); const struct clk_ops clk_regmap_divider_ro_ops = { .recalc_rate = clk_regmap_div_recalc_rate, - .round_rate = clk_regmap_div_round_rate, + .determine_rate = clk_regmap_div_determine_rate, }; EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops); -- cgit v1.2.3 From 498cc50b3fa99b545532dc433d53d3c0b889cc98 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 30 Jun 2021 11:58:39 -0700 Subject: clk: hisilicon: hi3559a: Drop __init markings everywhere This driver is a platform driver. The probe function can be called after kernel init, and try to reference kernel memory that has been freed. Drop the __init markings everywhere here to avoid referencing initdata from non-init code. Fixes modpost warnings. Reported-by: kernel test robot Cc: Dongjiu Geng Fixes: 6c81966107dc ("clk: hisilicon: Add clock driver for hi3559A SoC") Link: https://lore.kernel.org/r/20210630185839.3680834-1-sboyd@kernel.org Signed-off-by: Stephen Boyd --- drivers/clk/hisilicon/clk-hi3559a.c | 39 ++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 20 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index b1f19c43b558..56012a3d0219 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -107,25 +107,25 @@ static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = { }; -static const char *fmc_mux_p[] __initconst = { +static const char *fmc_mux_p[] = { "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m" }; -static const char *mmc_mux_p[] __initconst = { +static const char *mmc_mux_p[] = { "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k" }; -static const char *sysapb_mux_p[] __initconst = { +static const char *sysapb_mux_p[] = { "24m", "50m", }; -static const char *sysbus_mux_p[] __initconst = { +static const char *sysbus_mux_p[] = { "24m", "300m" }; -static const char *uart_mux_p[] __initconst = { "50m", "24m", "3m" }; +static const char *uart_mux_p[] = { "50m", "24m", "3m" }; -static const char *a73_clksel_mux_p[] __initconst = { +static const char *a73_clksel_mux_p[] = { "24m", "apll", "1000m" }; @@ -136,7 +136,7 @@ static const u32 sysbus_mux_table[] = { 0, 1 }; static const u32 uart_mux_table[] = { 0, 1, 2 }; static const u32 a73_clksel_mux_table[] = { 0, 1, 2 }; -static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = { +static struct hisi_mux_clock hi3559av100_mux_clks_crg[] = { { HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p), CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, @@ -181,7 +181,7 @@ static struct hisi_mux_clock hi3559av100_mux_clks_crg[] __initdata = { }, }; -static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = { +static struct hisi_gate_clock hi3559av100_gate_clks[] = { { HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT, 0x170, 1, 0, @@ -336,7 +336,7 @@ static struct hisi_gate_clock hi3559av100_gate_clks[] __initdata = { }, }; -static struct hi3559av100_pll_clock hi3559av100_pll_clks[] __initdata = { +static struct hi3559av100_pll_clock hi3559av100_pll_clks[] = { { HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3, 0x4, 0, 12, 12, 6 @@ -502,7 +502,7 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, } } -static __init struct hisi_clock_data *hi3559av100_clk_register( +static struct hisi_clock_data *hi3559av100_clk_register( struct platform_device *pdev) { struct hisi_clock_data *clk_data; @@ -549,7 +549,7 @@ unregister_fixed_rate: return ERR_PTR(ret); } -static __init void hi3559av100_clk_unregister(struct platform_device *pdev) +static void hi3559av100_clk_unregister(struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); @@ -568,8 +568,7 @@ static const struct hisi_crg_funcs hi3559av100_crg_funcs = { .unregister_clks = hi3559av100_clk_unregister, }; -static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] - __initdata = { +static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] = { { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, }, { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, }, { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, }, @@ -587,16 +586,16 @@ static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] /* shub mux clk */ static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3}; -static const char *shub_source_clk_mux_p[] __initconst = { +static const char *shub_source_clk_mux_p[] = { "clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL" }; static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3}; -static const char *shub_uart_source_clk_mux_p[] __initconst = { +static const char *shub_uart_source_clk_mux_p[] = { "clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M" }; -static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = { +static struct hisi_mux_clock hi3559av100_shub_mux_clks[] = { { HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p, ARRAY_SIZE(shub_source_clk_mux_p), @@ -615,7 +614,7 @@ static struct hisi_mux_clock hi3559av100_shub_mux_clks[] __initdata = { static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}}; static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}}; -static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = { +static struct hisi_divider_clock hi3559av100_shub_div_clks[] = { { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2, CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table, }, @@ -625,7 +624,7 @@ static struct hisi_divider_clock hi3559av100_shub_div_clks[] __initdata = { }; /* shub gate clk */ -static struct hisi_gate_clock hi3559av100_shub_gate_clks[] __initdata = { +static struct hisi_gate_clock hi3559av100_shub_gate_clks[] = { { HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk", 0, 0x20, 1, 0, @@ -697,7 +696,7 @@ static int hi3559av100_shub_default_clk_set(void) return 0; } -static __init struct hisi_clock_data *hi3559av100_shub_clk_register( +static struct hisi_clock_data *hi3559av100_shub_clk_register( struct platform_device *pdev) { struct hisi_clock_data *clk_data = NULL; @@ -751,7 +750,7 @@ unregister_fixed_rate: return ERR_PTR(ret); } -static __init void hi3559av100_shub_clk_unregister(struct platform_device *pdev) +static void hi3559av100_shub_clk_unregister(struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); -- cgit v1.2.3 From 783d08bd02f5d33d6e9e7fea62b727e2b6fe6462 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 1 Jul 2021 18:10:58 -0700 Subject: Revert "clk: divider: Switch from .round_rate to .determine_rate by default" This reverts commit db400ac1444b756030249ed4a35e53a68e557b59. We have drivers that are still using the .round_rate ops from here. We could implement both determine_rate and round_rate for these divider ops, but for now let's just kick out the commit that tried to change it and convert various drivers properly. Reported-by: Guenter Roeck Fixes: db400ac1444b ("clk: divider: Switch from .round_rate to .determine_rate by default") Cc: Jerome Brunet Cc: Martin Blumenstingl Link: https://lore.kernel.org/r/20210702011058.77284-1-sboyd@kernel.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-divider.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 9e05e81116af..87ba4966b0e8 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -425,8 +425,8 @@ long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, } EXPORT_SYMBOL_GPL(divider_ro_round_rate_parent); -static int clk_divider_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) +static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) { struct clk_divider *divider = to_clk_divider(hw); @@ -437,13 +437,13 @@ static int clk_divider_determine_rate(struct clk_hw *hw, val = clk_div_readl(divider) >> divider->shift; val &= clk_div_mask(divider->width); - return divider_ro_determine_rate(hw, req, divider->table, - divider->width, - divider->flags, val); + return divider_ro_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags, + val); } - return divider_determine_rate(hw, req, divider->table, divider->width, - divider->flags); + return divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); } int divider_get_val(unsigned long rate, unsigned long parent_rate, @@ -500,14 +500,14 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops clk_divider_ops = { .recalc_rate = clk_divider_recalc_rate, - .determine_rate = clk_divider_determine_rate, + .round_rate = clk_divider_round_rate, .set_rate = clk_divider_set_rate, }; EXPORT_SYMBOL_GPL(clk_divider_ops); const struct clk_ops clk_divider_ro_ops = { .recalc_rate = clk_divider_recalc_rate, - .determine_rate = clk_divider_determine_rate, + .round_rate = clk_divider_round_rate, }; EXPORT_SYMBOL_GPL(clk_divider_ro_ops); -- cgit v1.2.3