From a115f6362cee01813c66e10e397b25f2a06aecfb Mon Sep 17 00:00:00 2001 From: ABE Hiroshige Date: Thu, 14 Dec 2017 22:50:55 +0900 Subject: clk: renesas: r8a7796: Add FDP clock This patch adds FDP1-0 clock to the R8A7796 SoC. Signed-off-by: ABE Hiroshige Signed-off-by: Takeshi Kihara [geert: s/fdp0/fdp1-0/] Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index b3767472088a..41e29734126b 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -115,6 +115,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { + DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), -- cgit v1.2.3