From 59a43fa2487bf8ac67a758c4e653ce3db16f86a9 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 21 Dec 2021 14:24:23 +0900 Subject: clk: renesas: r8a779f0: Add SYS-DMAC clocks Add SYS-DMAC clocks on r8a779f0. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211221052423.597283-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index e6ec02c2c2a8..8cc7457564db 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -119,6 +119,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), + DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), + DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), }; /* -- cgit v1.2.3 From d843e61e0ea50ecf2fc9276c828ea3867867fd89 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Sat, 25 Dec 2021 22:39:57 +0300 Subject: clk: renesas: r8a7799[05]: Add MLP clocks Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs. Similar to other R-Car Gen3 SoC, exact information on the parents of MLP clocks on E3 and D3 is not available. However, since the parents of these clocks are not anyhow software-controllable, the only harm from this is inexact information exported via debugfs. So just keep the parent set in the same way as with other Gen3 SoCs. Signed-off-by: Nikita Yushchenko Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index faf60f7adc8d..d34d97baab35 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -200,6 +200,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { DEF_MOD("du0", 724, R8A77990_CLK_S1D1), DEF_MOD("lvds", 727, R8A77990_CLK_S2D1), + DEF_MOD("mlp", 802, R8A77990_CLK_S2D1), DEF_MOD("vin5", 806, R8A77990_CLK_S1D2), DEF_MOD("vin4", 807, R8A77990_CLK_S1D2), DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2), diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 7713cfd99c1d..525eef197fd9 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -160,6 +160,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { DEF_MOD("du1", 723, R8A77995_CLK_S1D1), DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), + DEF_MOD("mlp", 802, R8A77995_CLK_S2D1), DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), -- cgit v1.2.3 From b289cdecc7c3e25e001cde260c882e4d9a8b0772 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Dec 2021 09:32:23 +0000 Subject: clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600 MHz, but with current multiplier and divider values this resulted to 1596 MHz. This patch updates the multiplier and divider values for PLL2 and PLL3 so that we get the exact (1600 MHz) values. Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC") Suggested-by: Biju Das Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a07g044-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 79042bf46fe8..46359afef0d4 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -88,8 +88,8 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), - DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), - DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), -- cgit v1.2.3 From 9b621b6adff533468798404acca062c46da141af Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 11 Jan 2022 17:22:27 +0100 Subject: clk: renesas: r8a779a0: Add CANFD module clock Adds "canfd0" to mod clocks. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220111162231.10390-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 1c09d4ebe90f..fadd8a1718c6 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -136,6 +136,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), + DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD), DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), -- cgit v1.2.3 From 2a8b539433e111c4de364237627ef219d2f6350a Mon Sep 17 00:00:00 2001 From: Adam Wujek Date: Fri, 3 Dec 2021 14:12:07 +0000 Subject: clk: si5341: fix reported clk_rate when output divider is 2 SI5341_OUT_CFG_RDIV_FORCE2 shall be checked first to distinguish whether a divider for a given output is set to 2 (SI5341_OUT_CFG_RDIV_FORCE2 is set) or the output is disabled (SI5341_OUT_CFG_RDIV_FORCE2 not set, SI5341_OUT_R_REG is set 0). Before the change, divider set to 2 (SI5341_OUT_R_REG set to 0) was interpreted as output is disabled. Signed-off-by: Adam Wujek Link: https://lore.kernel.org/r/20211203141125.2447520-1-dev_public@wujek.eu Reviewed-by: Robert Hancock Signed-off-by: Stephen Boyd --- drivers/clk/clk-si5341.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c index f7b41366666e..4de098b6b0d4 100644 --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c @@ -798,6 +798,15 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, u32 r_divider; u8 r[3]; + err = regmap_read(output->data->regmap, + SI5341_OUT_CONFIG(output), &val); + if (err < 0) + return err; + + /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */ + if (val & SI5341_OUT_CFG_RDIV_FORCE2) + return parent_rate / 2; + err = regmap_bulk_read(output->data->regmap, SI5341_OUT_R_REG(output), r, 3); if (err < 0) @@ -814,13 +823,6 @@ static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw, r_divider += 1; r_divider <<= 1; - err = regmap_read(output->data->regmap, - SI5341_OUT_CONFIG(output), &val); - if (err < 0) - return err; - - if (val & SI5341_OUT_CFG_RDIV_FORCE2) - r_divider = 2; return parent_rate / r_divider; } -- cgit v1.2.3 From 982c59537523942e53c3c8039bd29dfab594d713 Mon Sep 17 00:00:00 2001 From: Qing Wang Date: Thu, 14 Oct 2021 23:45:28 -0700 Subject: clk-si5341: replace snprintf in show functions with sysfs_emit coccicheck complains about the use of snprintf() in sysfs show functions. Fix the following coccicheck warning: drivers/clk/clk-si5341.c:1471: WARNING: use scnprintf or sprintf. drivers/clk/clk-si5341.c:1486: WARNING: use scnprintf or sprintf. drivers/clk/clk-si5341.c:1501: WARNING: use scnprintf or sprintf. drivers/clk/clk-si5341.c:1516: WARNING: use scnprintf or sprintf. Use sysfs_emit instead of scnprintf or sprintf makes more sense. Signed-off-by: Qing Wang Link: https://lore.kernel.org/r/1634280331-4150-1-git-send-email-wangqing@vivo.com Reviewed-by: Robert Hancock Signed-off-by: Stephen Boyd --- drivers/clk/clk-si5341.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c index 4de098b6b0d4..071f5a1c8a1c 100644 --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c @@ -1470,7 +1470,7 @@ static ssize_t input_present_show(struct device *dev, if (res < 0) return res; res = !(status & SI5341_STATUS_LOSREF); - return snprintf(buf, PAGE_SIZE, "%d\n", res); + return sysfs_emit(buf, "%d\n", res); } static DEVICE_ATTR_RO(input_present); @@ -1485,7 +1485,7 @@ static ssize_t input_present_sticky_show(struct device *dev, if (res < 0) return res; res = !(status & SI5341_STATUS_LOSREF); - return snprintf(buf, PAGE_SIZE, "%d\n", res); + return sysfs_emit(buf, "%d\n", res); } static DEVICE_ATTR_RO(input_present_sticky); @@ -1500,7 +1500,7 @@ static ssize_t pll_locked_show(struct device *dev, if (res < 0) return res; res = !(status & SI5341_STATUS_LOL); - return snprintf(buf, PAGE_SIZE, "%d\n", res); + return sysfs_emit(buf, "%d\n", res); } static DEVICE_ATTR_RO(pll_locked); @@ -1515,7 +1515,7 @@ static ssize_t pll_locked_sticky_show(struct device *dev, if (res < 0) return res; res = !(status & SI5341_STATUS_LOL); - return snprintf(buf, PAGE_SIZE, "%d\n", res); + return sysfs_emit(buf, "%d\n", res); } static DEVICE_ATTR_RO(pll_locked_sticky); -- cgit v1.2.3 From 7a688c91d3fd54c53e7a9edd6052cdae98dd99d8 Mon Sep 17 00:00:00 2001 From: José Expósito Date: Sat, 15 Jan 2022 19:30:59 +0100 Subject: clk: mediatek: Fix memory leaks on probe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Handle the error branches to free memory where required. Addresses-Coverity-ID: 1491825 ("Resource leak") Signed-off-by: José Expósito Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220115183059.GA10809@elementary Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8192.c | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index cbc7c6dbe0f4..79ddb3cc0b98 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1236,9 +1236,17 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); if (r) - return r; + goto free_clk_data; + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto free_clk_data; + + return r; - return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } static int clk_mt8192_peri_probe(struct platform_device *pdev) @@ -1253,9 +1261,17 @@ static int clk_mt8192_peri_probe(struct platform_device *pdev) r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); if (r) - return r; + goto free_clk_data; + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto free_clk_data; - return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + return r; + +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } static int clk_mt8192_apmixed_probe(struct platform_device *pdev) @@ -1271,9 +1287,17 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); if (r) - return r; + goto free_clk_data; - return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto free_clk_data; + + return r; + +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } static const struct of_device_id of_match_clk_mt8192[] = { -- cgit v1.2.3 From ea2be22f3d37b1e77fbfe46cd6536eab667107ec Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Tue, 11 Jan 2022 14:20:50 +0000 Subject: clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT Make AUDIOPINCK accessible via phandle to select it as peripheral clock parent using assigned-clock-parents in DT where available. Signed-off-by: Zixun LI Reviewed-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220111142051.37957-1-admin@hifiphile.com Signed-off-by: Stephen Boyd --- drivers/clk/at91/sama5d2.c | 4 +++- include/dt-bindings/clock/at91.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index d027294a0089..f479e39e3bb2 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -168,7 +168,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1, + sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPINCK + 1, nck(sama5d2_systemck), nck(sama5d2_periph32ck), nck(sama5d2_gck), 3); @@ -216,6 +216,8 @@ static void __init sama5d2_pmc_setup(struct device_node *np) if (IS_ERR(hw)) goto err_free; + sama5d2_pmc->chws[PMC_AUDIOPINCK] = hw; + hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", "audiopll_fracck"); if (IS_ERR(hw)) diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 98e1b2ab6403..573cf8c25eb4 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -24,6 +24,7 @@ #define PMC_PLLACK 7 #define PMC_PLLBCK 8 #define PMC_AUDIOPLLCK 9 +#define PMC_AUDIOPINCK 10 /* SAMA7G5 */ #define PMC_CPUPLL (PMC_MAIN + 1) -- cgit v1.2.3 From a5ab04af49434aef532bf6cd4baa08a13665d608 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 11 Jan 2022 14:53:10 +0200 Subject: clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT MCK1 feeds the External Bus Interface (EBI). EBI's clock rate is used to translate EBI's timmings to SMC timings, thus we need to handle MCK1 in the EBI driver. Allow MCK1 to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20220111125310.902856-1-tudor.ambarus@microchip.com Reviewed-by: Claudiu Beznea Signed-off-by: Stephen Boyd --- drivers/clk/at91/sama7g5.c | 8 +++++++- include/dt-bindings/clock/at91.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 369dfafabbca..e43458673afb 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -302,6 +302,7 @@ static const struct { * @ep_count: extra parents count * @ep_mux_table: mux table for extra parents * @id: clock id + * @eid: export index in sama7g5->chws[] array * @c: true if clock is critical and cannot be disabled */ static const struct { @@ -311,6 +312,7 @@ static const struct { u8 ep_count; u8 ep_mux_table[4]; u8 id; + u8 eid; u8 c; } sama7g5_mckx[] = { { .n = "mck1", @@ -319,6 +321,7 @@ static const struct { .ep_mux_table = { 5, }, .ep_count = 1, .ep_chg_id = INT_MIN, + .eid = PMC_MCK1, .c = 1, }, { .n = "mck2", @@ -913,7 +916,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) if (IS_ERR(regmap)) return; - sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, + sama7g5_pmc = pmc_data_allocate(PMC_MCK1 + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); @@ -1027,6 +1030,9 @@ static void __init sama7g5_pmc_setup(struct device_node *np) goto err_free; alloc_mem[alloc_mem_size++] = mux_table; + + if (sama7g5_mckx[i].eid) + sama7g5_pmc->chws[sama7g5_mckx[i].eid] = hw; } hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal"); diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 573cf8c25eb4..3e3972a814c1 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -36,6 +36,7 @@ #define PMC_AUDIOIOPLL (PMC_MAIN + 7) #define PMC_ETHPLL (PMC_MAIN + 8) #define PMC_CPU (PMC_MAIN + 9) +#define PMC_MCK1 (PMC_MAIN + 10) #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ -- cgit v1.2.3 From e33b88b6d7c212de866296dda6a19738c5a978a8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:54 +0100 Subject: clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock The ETHCK_K are modeled as composite clock of MUX and GATE, however per STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet, ETHPTPDIV divider is attached past the ETHCK_K mux, and ETH_CLK/eth_clk_fb clock are output past ETHCKEN gate. Therefore, in case ETH_CLK/eth_clk_fb are not in use AND PTP clock are in use, ETHCKEN gate can be turned off. Current driver does not permit that, fix it. This patch converts ETHCK_K from composite clock into a ETHCKEN gate, ETHPTP_K from composite clock into ETHPTPDIV divider, and adds another NO_ID clock "ck_ker_eth" which models the ETHSRC mux and is parent clock to both ETHCK_K and ETHPTP_K. Therefore, all references to ETHCK_K and ETHPTP_K remain functional as before. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20220118202958.1840431-1-marex@denx.de Tested-by: Johann Neuhauser Acked-by: Gabriel Fernandez Signed-off-by: Stephen Boyd --- drivers/clk/clk-stm32mp1.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 863274aa50e3..23a34ab459a3 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -2008,7 +2008,6 @@ static const struct clock_config stm32mp1_clock_cfg[] = { KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI), KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1), KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO), - KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK), /* Particulary Kernel Clocks (no mux or no gate) */ MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM), @@ -2017,11 +2016,16 @@ static const struct clock_config stm32mp1_clock_cfg[] = { MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU), MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12), - COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE | + COMPOSITE(NO_ID, "ck_ker_eth", eth_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT, _NO_GATE, _MMUX(M_ETHCK), - _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), + _NO_DIV), + + MGATE_MP1(ETHCK_K, "ethck_k", "ck_ker_eth", 0, G_ETHCK), + + DIV(ETHPTP_K, "ethptp_k", "ck_ker_eth", CLK_OPS_PARENT_ENABLE | + CLK_SET_RATE_NO_REPARENT, RCC_ETHCKSELR, 4, 4, 0), /* RTC clock */ COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE, -- cgit v1.2.3 From e9ed1ef18a37a97899dca8d5b2693d5c218bb774 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 Jan 2022 21:29:55 +0100 Subject: clk: stm32mp1: Add parent_data to ETHRX clock Pass parent_data to ETHRX clock with new fw_name = "ETH_RX_CLK/ETH_REF_CLK". By default, this change has no impact on the operation of the clock driver. However, due to the fw_name, it permits DT to override ETHRX clock parent, which might be needed in case the ETHRX clock are supplied by external clock source. Example of MCO2 supplying clock to ETH_RX_CLK via external pad-to-pad wire: &rcc { clocks = <&rcc CK_MCO2>; clock-names = "ETH_RX_CLK/ETH_REF_CLK"; }; Note that while this patch permits to implement this rare usecase, the issue with ethernet RX and TX input clock modeling on MP1 is far more complex and requires more core plumbing. [1] STM32MP1 Reference Manual RM0436 Rev 3, Page 574, Figure 83. Peripheral clock distribution for Ethernet https://www.st.com/resource/en/reference_manual/dm00327659-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20220118202958.1840431-2-marex@denx.de Tested-by: Johann Neuhauser Acked-by: Gabriel Fernandez Signed-off-by: Stephen Boyd --- drivers/clk/clk-stm32mp1.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 23a34ab459a3..7ad2e6203bae 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -155,6 +155,10 @@ static const char * const eth_src[] = { "pll4_p", "pll3_q" }; +const struct clk_parent_data ethrx_src[] = { + { .name = "ethck_k", .fw_name = "ETH_RX_CLK/ETH_REF_CLK" }, +}; + static const char * const rng_src[] = { "ck_csi", "pll4_r", "ck_lse", "ck_lsi" }; @@ -317,6 +321,7 @@ struct clock_config { const char *name; const char *parent_name; const char * const *parent_names; + const struct clk_parent_data *parent_data; int num_parents; unsigned long flags; void *cfg; @@ -576,6 +581,7 @@ static struct clk_hw * clk_stm32_register_gate_ops(struct device *dev, const char *name, const char *parent_name, + const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *base, const struct stm32_gate_cfg *cfg, @@ -586,7 +592,10 @@ clk_stm32_register_gate_ops(struct device *dev, int ret; init.name = name; - init.parent_names = &parent_name; + if (parent_name) + init.parent_names = &parent_name; + if (parent_data) + init.parent_data = parent_data; init.num_parents = 1; init.flags = flags; @@ -611,6 +620,7 @@ clk_stm32_register_gate_ops(struct device *dev, static struct clk_hw * clk_stm32_register_composite(struct device *dev, const char *name, const char * const *parent_names, + const struct clk_parent_data *parent_data, int num_parents, void __iomem *base, const struct stm32_composite_cfg *cfg, unsigned long flags, spinlock_t *lock) @@ -1135,6 +1145,7 @@ _clk_stm32_register_gate(struct device *dev, return clk_stm32_register_gate_ops(dev, cfg->name, cfg->parent_name, + cfg->parent_data, cfg->flags, base, cfg->cfg, @@ -1148,8 +1159,8 @@ _clk_stm32_register_composite(struct device *dev, const struct clock_config *cfg) { return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, - cfg->num_parents, base, cfg->cfg, - cfg->flags, lock); + cfg->parent_data, cfg->num_parents, + base, cfg->cfg, cfg->flags, lock); } #define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\ @@ -1258,6 +1269,16 @@ _clk_stm32_register_composite(struct device *dev, .func = _clk_stm32_register_gate,\ } +#define STM32_GATE_PDATA(_id, _name, _parent, _flags, _gate)\ +{\ + .id = _id,\ + .name = _name,\ + .parent_data = _parent,\ + .flags = _flags,\ + .cfg = (struct stm32_gate_cfg *) {_gate},\ + .func = _clk_stm32_register_gate,\ +} + #define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\ (&(struct stm32_gate_cfg) {\ &(struct gate_cfg) {\ @@ -1291,6 +1312,10 @@ _clk_stm32_register_composite(struct device *dev, STM32_GATE(_id, _name, _parent, _flags,\ _STM32_MGATE(_mgate)) +#define MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate)\ + STM32_GATE_PDATA(_id, _name, _parent, _flags,\ + _STM32_MGATE(_mgate)) + #define _STM32_DIV(_div_offset, _div_shift, _div_width,\ _div_flags, _div_table, _ops)\ .div = &(struct stm32_div_cfg) {\ @@ -1354,6 +1379,9 @@ _clk_stm32_register_composite(struct device *dev, #define PCLK(_id, _name, _parent, _flags, _mgate)\ MGATE_MP1(_id, _name, _parent, _flags, _mgate) +#define PCLK_PDATA(_id, _name, _parent, _flags, _mgate)\ + MGATE_MP1_PDATA(_id, _name, _parent, _flags, _mgate) + #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\ CLK_SET_RATE_NO_REPARENT | _flags,\ @@ -1951,7 +1979,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = { PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA), PCLK(GPU, "gpu", "ck_axi", 0, G_GPU), PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX), - PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX), + PCLK_PDATA(ETHRX, "ethrx", ethrx_src, 0, G_ETHRX), PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC), PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC), PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI), -- cgit v1.2.3 From 4917394e0c765e89787ed8e296a0706cac51440d Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Wed, 19 Jan 2022 12:54:34 +0100 Subject: clk: zynqmp: replace warn_once with pr_debug for failed clock ops The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek Signed-off-by: Stephen Boyd --- drivers/clk/zynqmp/clk-gate-zynqmp.c | 12 ++++++------ drivers/clk/zynqmp/clk-mux-zynqmp.c | 8 ++++---- drivers/clk/zynqmp/divider.c | 12 ++++++------ drivers/clk/zynqmp/pll.c | 32 ++++++++++++++++---------------- 4 files changed, 32 insertions(+), 32 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c index 565ed67a0430..b89e55737198 100644 --- a/drivers/clk/zynqmp/clk-gate-zynqmp.c +++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c @@ -41,8 +41,8 @@ static int zynqmp_clk_gate_enable(struct clk_hw *hw) ret = zynqmp_pm_clock_enable(clk_id); if (ret) - pr_warn_once("%s() clock enabled failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n", + __func__, clk_name, clk_id, ret); return ret; } @@ -61,8 +61,8 @@ static void zynqmp_clk_gate_disable(struct clk_hw *hw) ret = zynqmp_pm_clock_disable(clk_id); if (ret) - pr_warn_once("%s() clock disable failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n", + __func__, clk_name, clk_id, ret); } /** @@ -80,8 +80,8 @@ static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw) ret = zynqmp_pm_clock_getstate(clk_id, &state); if (ret) { - pr_warn_once("%s() clock get state failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() clock get state failed for %s, ret = %d\n", + __func__, clk_name, ret); return -EIO; } diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 17afce594f28..60359333f26d 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -51,8 +51,8 @@ static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) ret = zynqmp_pm_clock_getparent(clk_id, &val); if (ret) { - pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() getparent failed for clock: %s, ret = %d\n", + __func__, clk_name, ret); /* * clk_core_get_parent_by_index() takes num_parents as incorrect * index which is exactly what I want to return here @@ -80,8 +80,8 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) ret = zynqmp_pm_clock_setparent(clk_id, index); if (ret) - pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() set parent failed for clock: %s, ret = %d\n", + __func__, clk_name, ret); return ret; } diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index cb49281f9cf9..422ea79907dd 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -89,8 +89,8 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, ret = zynqmp_pm_clock_getdivider(clk_id, &div); if (ret) - pr_warn_once("%s() get divider failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() get divider failed for %s, ret = %d\n", + __func__, clk_name, ret); if (div_type == TYPE_DIV1) value = div & 0xFFFF; @@ -177,8 +177,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); if (ret) - pr_warn_once("%s() get divider failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() get divider failed for %s, ret = %d\n", + __func__, clk_name, ret); if (div_type == TYPE_DIV1) bestdiv = bestdiv & 0xFFFF; else @@ -244,8 +244,8 @@ static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, ret = zynqmp_pm_clock_setdivider(clk_id, div); if (ret) - pr_warn_once("%s() set divider failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() set divider failed for %s, ret = %d\n", + __func__, clk_name, ret); return ret; } diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index 036e4ff64a2f..91a6b4cc910e 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -56,8 +56,8 @@ static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw) ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload); if (ret) { - pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() PLL get frac mode failed for %s, ret = %d\n", + __func__, clk_name, ret); return PLL_MODE_ERROR; } @@ -84,8 +84,8 @@ static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on) ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode); if (ret) - pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n", + __func__, clk_name, ret); else clk->set_pll_mode = true; } @@ -145,8 +145,8 @@ static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw, ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); if (ret) { - pr_warn_once("%s() get divider failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() get divider failed for %s, ret = %d\n", + __func__, clk_name, ret); return 0ul; } @@ -200,8 +200,8 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, WARN(1, "More than allowed devices are using the %s, which is forbidden\n", clk_name); else if (ret) - pr_warn_once("%s() set divider failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() set divider failed for %s, ret = %d\n", + __func__, clk_name, ret); zynqmp_pm_set_pll_frac_data(clk_id, f); return rate + frac; @@ -211,8 +211,8 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate, fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv); if (ret) - pr_warn_once("%s() set divider failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() set divider failed for %s, ret = %d\n", + __func__, clk_name, ret); return parent_rate * fbdiv; } @@ -233,8 +233,8 @@ static int zynqmp_pll_is_enabled(struct clk_hw *hw) ret = zynqmp_pm_clock_getstate(clk_id, &state); if (ret) { - pr_warn_once("%s() clock get state failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() clock get state failed for %s, ret = %d\n", + __func__, clk_name, ret); return -EIO; } @@ -265,8 +265,8 @@ static int zynqmp_pll_enable(struct clk_hw *hw) ret = zynqmp_pm_clock_enable(clk_id); if (ret) - pr_warn_once("%s() clock enable failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() clock enable failed for %s, ret = %d\n", + __func__, clk_name, ret); return ret; } @@ -287,8 +287,8 @@ static void zynqmp_pll_disable(struct clk_hw *hw) ret = zynqmp_pm_clock_disable(clk_id); if (ret) - pr_warn_once("%s() clock disable failed for %s, ret = %d\n", - __func__, clk_name, ret); + pr_debug("%s() clock disable failed for %s, ret = %d\n", + __func__, clk_name, ret); } static const struct clk_ops zynqmp_pll_ops = { -- cgit v1.2.3 From a992acbb219a74fb025f8c2d65760fe05e775c7b Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 20 Jan 2022 09:59:02 -0800 Subject: clk: gate: Add some kunit test suites Test various parts of the clk gate implementation with the kunit testing framework. Reviewed-by: Brendan Higgins Acked-by: Daniel Latypov Cc: Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20220120175902.2165958-1-sboyd@kernel.org --- drivers/clk/.kunitconfig | 3 + drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-gate_test.c | 464 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 476 insertions(+) create mode 100644 drivers/clk/.kunitconfig create mode 100644 drivers/clk/clk-gate_test.c (limited to 'drivers/clk') diff --git a/drivers/clk/.kunitconfig b/drivers/clk/.kunitconfig new file mode 100644 index 000000000000..3754fdb9485a --- /dev/null +++ b/drivers/clk/.kunitconfig @@ -0,0 +1,3 @@ +CONFIG_KUNIT=y +CONFIG_COMMON_CLK=y +CONFIG_CLK_GATE_KUNIT_TEST=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..3cdf33470a75 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -428,4 +428,12 @@ source "drivers/clk/x86/Kconfig" source "drivers/clk/xilinx/Kconfig" source "drivers/clk/zynqmp/Kconfig" +# Kunit test cases +config CLK_GATE_KUNIT_TEST + tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Kunit test for the basic clk gate type. + endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..6a98291350b6 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o obj-$(CONFIG_COMMON_CLK) += clk-gate.o +obj-$(CONFIG_CLK_GATE_KUNIT_TEST) += clk-gate_test.o obj-$(CONFIG_COMMON_CLK) += clk-multiplier.o obj-$(CONFIG_COMMON_CLK) += clk-mux.o obj-$(CONFIG_COMMON_CLK) += clk-composite.o diff --git a/drivers/clk/clk-gate_test.c b/drivers/clk/clk-gate_test.c new file mode 100644 index 000000000000..e136aaad48bf --- /dev/null +++ b/drivers/clk/clk-gate_test.c @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Kunit test for clk gate basic type + */ +#include +#include +#include + +#include + +static void clk_gate_register_test_dev(struct kunit *test) +{ + struct clk_hw *ret; + struct platform_device *pdev; + + pdev = platform_device_register_simple("test_gate_device", -1, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, pdev); + + ret = clk_hw_register_gate(&pdev->dev, "test_gate", NULL, 0, NULL, + 0, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ret); + KUNIT_EXPECT_STREQ(test, "test_gate", clk_hw_get_name(ret)); + KUNIT_EXPECT_EQ(test, 0UL, clk_hw_get_flags(ret)); + + clk_hw_unregister_gate(ret); + platform_device_put(pdev); +} + +static void clk_gate_register_test_parent_names(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *ret; + + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 1000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + + ret = clk_hw_register_gate(NULL, "test_gate", "test_parent", 0, NULL, + 0, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ret); + KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); + + clk_hw_unregister_gate(ret); + clk_hw_unregister_fixed_rate(parent); +} + +static void clk_gate_register_test_parent_data(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *ret; + struct clk_parent_data pdata = { }; + + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 1000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + pdata.hw = parent; + + ret = clk_hw_register_gate_parent_data(NULL, "test_gate", &pdata, 0, + NULL, 0, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ret); + KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); + + clk_hw_unregister_gate(ret); + clk_hw_unregister_fixed_rate(parent); +} + +static void clk_gate_register_test_parent_data_legacy(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *ret; + struct clk_parent_data pdata = { }; + + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 1000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + pdata.name = "test_parent"; + + ret = clk_hw_register_gate_parent_data(NULL, "test_gate", &pdata, 0, + NULL, 0, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ret); + KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); + + clk_hw_unregister_gate(ret); + clk_hw_unregister_fixed_rate(parent); +} + +static void clk_gate_register_test_parent_hw(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *ret; + + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 1000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + + ret = clk_hw_register_gate_parent_hw(NULL, "test_gate", parent, 0, NULL, + 0, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ret); + KUNIT_EXPECT_PTR_EQ(test, parent, clk_hw_get_parent(ret)); + + clk_hw_unregister_gate(ret); + clk_hw_unregister_fixed_rate(parent); +} + +static void clk_gate_register_test_hiword_invalid(struct kunit *test) +{ + struct clk_hw *ret; + + ret = clk_hw_register_gate(NULL, "test_gate", NULL, 0, NULL, + 20, CLK_GATE_HIWORD_MASK, NULL); + + KUNIT_EXPECT_TRUE(test, IS_ERR(ret)); +} + +static struct kunit_case clk_gate_register_test_cases[] = { + KUNIT_CASE(clk_gate_register_test_dev), + KUNIT_CASE(clk_gate_register_test_parent_names), + KUNIT_CASE(clk_gate_register_test_parent_data), + KUNIT_CASE(clk_gate_register_test_parent_data_legacy), + KUNIT_CASE(clk_gate_register_test_parent_hw), + KUNIT_CASE(clk_gate_register_test_hiword_invalid), + {} +}; + +static struct kunit_suite clk_gate_register_test_suite = { + .name = "clk-gate-register-test", + .test_cases = clk_gate_register_test_cases, +}; + +struct clk_gate_test_context { + void __iomem *fake_mem; + struct clk_hw *hw; + struct clk_hw *parent; + u32 fake_reg; /* Keep at end, KASAN can detect out of bounds */ +}; + +static struct clk_gate_test_context *clk_gate_test_alloc_ctx(struct kunit *test) +{ + struct clk_gate_test_context *ctx; + + test->priv = ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + ctx->fake_mem = (void __force __iomem *)&ctx->fake_reg; + + return ctx; +} + +static void clk_gate_test_parent_rate(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + unsigned long prate = clk_hw_get_rate(parent); + unsigned long rate = clk_hw_get_rate(hw); + + KUNIT_EXPECT_EQ(test, prate, rate); +} + +static void clk_gate_test_enable(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + struct clk *clk = hw->clk; + u32 enable_val = BIT(5); + + KUNIT_ASSERT_EQ(test, clk_prepare_enable(clk), 0); + + KUNIT_EXPECT_EQ(test, enable_val, ctx->fake_reg); + KUNIT_EXPECT_TRUE(test, clk_hw_is_enabled(hw)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_prepared(hw)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_enabled(parent)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_prepared(parent)); +} + +static void clk_gate_test_disable(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + struct clk *clk = hw->clk; + u32 enable_val = BIT(5); + u32 disable_val = 0; + + KUNIT_ASSERT_EQ(test, clk_prepare_enable(clk), 0); + KUNIT_ASSERT_EQ(test, enable_val, ctx->fake_reg); + + clk_disable_unprepare(clk); + KUNIT_EXPECT_EQ(test, disable_val, ctx->fake_reg); + KUNIT_EXPECT_FALSE(test, clk_hw_is_enabled(hw)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_prepared(hw)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_enabled(parent)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_prepared(parent)); +} + +static struct kunit_case clk_gate_test_cases[] = { + KUNIT_CASE(clk_gate_test_parent_rate), + KUNIT_CASE(clk_gate_test_enable), + KUNIT_CASE(clk_gate_test_disable), + {} +}; + +static int clk_gate_test_init(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 2000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + + hw = clk_hw_register_gate_parent_hw(NULL, "test_gate", parent, 0, + ctx->fake_mem, 5, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + ctx->hw = hw; + ctx->parent = parent; + + return 0; +} + +static void clk_gate_test_exit(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + + clk_hw_unregister_gate(ctx->hw); + clk_hw_unregister_fixed_rate(ctx->parent); +} + +static struct kunit_suite clk_gate_test_suite = { + .name = "clk-gate-test", + .init = clk_gate_test_init, + .exit = clk_gate_test_exit, + .test_cases = clk_gate_test_cases, +}; + +static void clk_gate_test_invert_enable(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + struct clk *clk = hw->clk; + u32 enable_val = 0; + + KUNIT_ASSERT_EQ(test, clk_prepare_enable(clk), 0); + + KUNIT_EXPECT_EQ(test, enable_val, ctx->fake_reg); + KUNIT_EXPECT_TRUE(test, clk_hw_is_enabled(hw)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_prepared(hw)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_enabled(parent)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_prepared(parent)); +} + +static void clk_gate_test_invert_disable(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + struct clk *clk = hw->clk; + u32 enable_val = 0; + u32 disable_val = BIT(15); + + KUNIT_ASSERT_EQ(test, clk_prepare_enable(clk), 0); + KUNIT_ASSERT_EQ(test, enable_val, ctx->fake_reg); + + clk_disable_unprepare(clk); + KUNIT_EXPECT_EQ(test, disable_val, ctx->fake_reg); + KUNIT_EXPECT_FALSE(test, clk_hw_is_enabled(hw)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_prepared(hw)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_enabled(parent)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_prepared(parent)); +} + +static struct kunit_case clk_gate_test_invert_cases[] = { + KUNIT_CASE(clk_gate_test_invert_enable), + KUNIT_CASE(clk_gate_test_invert_disable), + {} +}; + +static int clk_gate_test_invert_init(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 2000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + + ctx->fake_reg = BIT(15); /* Default to off */ + hw = clk_hw_register_gate_parent_hw(NULL, "test_gate", parent, 0, + ctx->fake_mem, 15, + CLK_GATE_SET_TO_DISABLE, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + ctx->hw = hw; + ctx->parent = parent; + + return 0; +} + +static struct kunit_suite clk_gate_test_invert_suite = { + .name = "clk-gate-invert-test", + .init = clk_gate_test_invert_init, + .exit = clk_gate_test_exit, + .test_cases = clk_gate_test_invert_cases, +}; + +static void clk_gate_test_hiword_enable(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + struct clk *clk = hw->clk; + u32 enable_val = BIT(9) | BIT(9 + 16); + + KUNIT_ASSERT_EQ(test, clk_prepare_enable(clk), 0); + + KUNIT_EXPECT_EQ(test, enable_val, ctx->fake_reg); + KUNIT_EXPECT_TRUE(test, clk_hw_is_enabled(hw)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_prepared(hw)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_enabled(parent)); + KUNIT_EXPECT_TRUE(test, clk_hw_is_prepared(parent)); +} + +static void clk_gate_test_hiword_disable(struct kunit *test) +{ + struct clk_gate_test_context *ctx = test->priv; + struct clk_hw *parent = ctx->parent; + struct clk_hw *hw = ctx->hw; + struct clk *clk = hw->clk; + u32 enable_val = BIT(9) | BIT(9 + 16); + u32 disable_val = BIT(9 + 16); + + KUNIT_ASSERT_EQ(test, clk_prepare_enable(clk), 0); + KUNIT_ASSERT_EQ(test, enable_val, ctx->fake_reg); + + clk_disable_unprepare(clk); + KUNIT_EXPECT_EQ(test, disable_val, ctx->fake_reg); + KUNIT_EXPECT_FALSE(test, clk_hw_is_enabled(hw)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_prepared(hw)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_enabled(parent)); + KUNIT_EXPECT_FALSE(test, clk_hw_is_prepared(parent)); +} + +static struct kunit_case clk_gate_test_hiword_cases[] = { + KUNIT_CASE(clk_gate_test_hiword_enable), + KUNIT_CASE(clk_gate_test_hiword_disable), + {} +}; + +static int clk_gate_test_hiword_init(struct kunit *test) +{ + struct clk_hw *parent; + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + parent = clk_hw_register_fixed_rate(NULL, "test_parent", NULL, 0, + 2000000); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent); + + hw = clk_hw_register_gate_parent_hw(NULL, "test_gate", parent, 0, + ctx->fake_mem, 9, + CLK_GATE_HIWORD_MASK, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + + ctx->hw = hw; + ctx->parent = parent; + + return 0; +} + +static struct kunit_suite clk_gate_test_hiword_suite = { + .name = "clk-gate-hiword-test", + .init = clk_gate_test_hiword_init, + .exit = clk_gate_test_exit, + .test_cases = clk_gate_test_hiword_cases, +}; + +static void clk_gate_test_is_enabled(struct kunit *test) +{ + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + ctx->fake_reg = BIT(7); + hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 7, + 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + KUNIT_ASSERT_TRUE(test, clk_hw_is_enabled(hw)); + + clk_hw_unregister_gate(hw); +} + +static void clk_gate_test_is_disabled(struct kunit *test) +{ + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + ctx->fake_reg = BIT(4); + hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 7, + 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + KUNIT_ASSERT_FALSE(test, clk_hw_is_enabled(hw)); + + clk_hw_unregister_gate(hw); +} + +static void clk_gate_test_is_enabled_inverted(struct kunit *test) +{ + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + ctx->fake_reg = BIT(31); + hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 2, + CLK_GATE_SET_TO_DISABLE, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + KUNIT_ASSERT_TRUE(test, clk_hw_is_enabled(hw)); + + clk_hw_unregister_gate(hw); +} + +static void clk_gate_test_is_disabled_inverted(struct kunit *test) +{ + struct clk_hw *hw; + struct clk_gate_test_context *ctx; + + ctx = clk_gate_test_alloc_ctx(test); + ctx->fake_reg = BIT(29); + hw = clk_hw_register_gate(NULL, "test_gate", NULL, 0, ctx->fake_mem, 29, + CLK_GATE_SET_TO_DISABLE, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, hw); + KUNIT_ASSERT_FALSE(test, clk_hw_is_enabled(hw)); + + clk_hw_unregister_gate(hw); +} + +static struct kunit_case clk_gate_test_enabled_cases[] = { + KUNIT_CASE(clk_gate_test_is_enabled), + KUNIT_CASE(clk_gate_test_is_disabled), + KUNIT_CASE(clk_gate_test_is_enabled_inverted), + KUNIT_CASE(clk_gate_test_is_disabled_inverted), + {} +}; + +static struct kunit_suite clk_gate_test_enabled_suite = { + .name = "clk-gate-is_enabled-test", + .test_cases = clk_gate_test_enabled_cases, +}; + +kunit_test_suites( + &clk_gate_register_test_suite, + &clk_gate_test_suite, + &clk_gate_test_invert_suite, + &clk_gate_test_hiword_suite, + &clk_gate_test_enabled_suite +); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From a6e11bb24ebd40a05a33ac1985d8643eb7217a40 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 25 Jan 2022 10:33:32 +0100 Subject: clk: cs2000-cp: Make aux output function controllable The aux output pin can be configured to output either of the two clock inputs, the generated clock or the pll lock status. Allow access to this feature through a new optional device-tree property. Signed-off-by: Daniel Mack Link: https://lore.kernel.org/r/20220125093336.226787-6-daniel@zonque.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-cs2000-cp.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 92bc4aca0f95..db7290621cef 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -39,6 +39,8 @@ /* DEVICE_CFG1 */ #define RSEL(x) (((x) & 0x3) << 3) #define RSEL_MASK RSEL(0x3) +#define AUXOUTSRC(x) (((x) & 0x3) << 1) +#define AUXOUTSRC_MASK AUXOUTSRC(0x3) #define ENDEV1 (0x1) /* DEVICE_CFG2 */ @@ -421,12 +423,19 @@ static int cs2000_clk_register(struct cs2000_priv *priv) struct clk_init_data init; const char *name = np->name; static const char *parent_names[CLK_MAX]; + u32 aux_out = 0; int ch = 0; /* it uses ch0 only at this point */ int rate; int ret; of_property_read_string(np, "clock-output-names", &name); + of_property_read_u32(np, "cirrus,aux-output-source", &aux_out); + ret = cs2000_bset(priv, DEVICE_CFG1, + AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); + if (ret < 0) + return ret; + /* * set default rate as 1/1. * otherwise .set_rate which setup ratio -- cgit v1.2.3 From da1eb4e8b4df2942614478289c89a2031d0488b1 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 25 Jan 2022 10:33:33 +0100 Subject: clk: cs2000-cp: add support for dynamic mode The CS2000 chip features two input clocks, REF_CLK and CLK_IN. In static mode, the output clock (CLK_OUT) is directly derived from REF_CLK, and CLK_IN is ignored. In dynamic mode, CLK_IN is used by the digital PLL. In dynamic mode, a low-frequency ratio configuration that uses a higher multiplier factor. Until now, only the static mode and high-frequency divider rations of the hardware was supported by the driver. This patch adds support for dynamic mode and both ratios: * Parse a new OF property 'cirrus,dynamic-mode' to determine the mode * In dynamic mode, present CLK_IN as parent clock, else use REF_CLK * The low-frequency ratio mode is automatically selected, depending on the mode of operation and the given input and output rates Signed-off-by: Daniel Mack Link: https://lore.kernel.org/r/20220125093336.226787-7-daniel@zonque.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-cs2000-cp.c | 111 +++++++++++++++++++++++++++++--------------- 1 file changed, 74 insertions(+), 37 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index db7290621cef..bd030e156d65 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -49,7 +49,7 @@ #define LOCKCLK_MASK LOCKCLK(0x3) #define FRACNSRC_MASK (1 << 0) #define FRACNSRC_STATIC (0 << 0) -#define FRACNSRC_DYNAMIC (1 << 1) +#define FRACNSRC_DYNAMIC (1 << 0) /* GLOBAL_CFG */ #define ENDEV2 (0x1) @@ -79,6 +79,9 @@ struct cs2000_priv { struct clk *clk_in; struct clk *ref_clk; + bool dynamic_mode; + bool lf_ratio; + /* suspend/resume */ unsigned long saved_rate; unsigned long saved_parent_rate; @@ -134,17 +137,11 @@ static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable) if (ret < 0) return ret; - /* FIXME: for Static ratio mode */ - ret = cs2000_bset(priv, FUNC_CFG2, LFRATIO_MASK, - LFRATIO_12_20); - if (ret < 0) - return ret; - return 0; } -static int cs2000_clk_in_bound_rate(struct cs2000_priv *priv, - u32 rate_in) +static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv, + u32 rate_in) { u32 val; @@ -191,35 +188,37 @@ static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable) (AUXOUTDIS | CLKOUTDIS)); } -static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out) +static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio) { u64 ratio; + u32 multiplier = lf_ratio ? 12 : 20; /* - * ratio = rate_out / rate_in * 2^20 + * ratio = rate_out / rate_in * 2^multiplier * * To avoid over flow, rate_out is u64. * The result should be u32. */ - ratio = (u64)rate_out << 20; + ratio = (u64)rate_out << multiplier; do_div(ratio, rate_in); return ratio; } -static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in) +static unsigned long cs2000_ratio_to_rate(u32 ratio, u32 rate_in, bool lf_ratio) { u64 rate_out; + u32 multiplier = lf_ratio ? 12 : 20; /* - * ratio = rate_out / rate_in * 2^20 + * ratio = rate_out / rate_in * 2^multiplier * * To avoid over flow, rate_out is u64. * The result should be u32 or unsigned long. */ rate_out = (u64)ratio * rate_in; - return rate_out >> 20; + return rate_out >> multiplier; } static int cs2000_ratio_set(struct cs2000_priv *priv, @@ -232,7 +231,7 @@ static int cs2000_ratio_set(struct cs2000_priv *priv, if (CH_SIZE_ERR(ch)) return -EINVAL; - val = cs2000_rate_to_ratio(rate_in, rate_out); + val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio); for (i = 0; i < RATIO_REG_SIZE; i++) { ret = cs2000_write(priv, Ratio_Add(ch, i), @@ -265,22 +264,20 @@ static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch) static int cs2000_ratio_select(struct cs2000_priv *priv, int ch) { int ret; + u8 fracnsrc; if (CH_SIZE_ERR(ch)) return -EINVAL; - /* - * FIXME - * - * this driver supports static ratio mode only at this point. - */ ret = cs2000_bset(priv, DEVICE_CFG1, RSEL_MASK, RSEL(ch)); if (ret < 0) return ret; + fracnsrc = priv->dynamic_mode ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC; + ret = cs2000_bset(priv, DEVICE_CFG2, - (AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK), - (LOCKCLK(ch) | FRACNSRC_STATIC)); + AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK, + LOCKCLK(ch) | fracnsrc); if (ret < 0) return ret; @@ -296,17 +293,39 @@ static unsigned long cs2000_recalc_rate(struct clk_hw *hw, ratio = cs2000_ratio_get(priv, ch); - return cs2000_ratio_to_rate(ratio, parent_rate); + return cs2000_ratio_to_rate(ratio, parent_rate, priv->lf_ratio); } static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { + struct cs2000_priv *priv = hw_to_priv(hw); u32 ratio; - ratio = cs2000_rate_to_ratio(*parent_rate, rate); + ratio = cs2000_rate_to_ratio(*parent_rate, rate, priv->lf_ratio); + + return cs2000_ratio_to_rate(ratio, *parent_rate, priv->lf_ratio); +} + +static int cs2000_select_ratio_mode(struct cs2000_priv *priv, + unsigned long rate, + unsigned long parent_rate) +{ + /* + * From the datasheet: + * + * | It is recommended that the 12.20 High-Resolution format be + * | utilized whenever the desired ratio is less than 4096 since + * | the output frequency accuracy of the PLL is directly proportional + * | to the accuracy of the timing reference clock and the resolution + * | of the R_UD. + * + * This mode is only available in dynamic mode. + */ + priv->lf_ratio = priv->dynamic_mode && ((rate / parent_rate) > 4096); - return cs2000_ratio_to_rate(ratio, *parent_rate); + return cs2000_bset(priv, FUNC_CFG2, LFRATIO_MASK, + priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20); } static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, @@ -315,7 +334,7 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; - ret = cs2000_clk_in_bound_rate(priv, parent_rate); + ret = cs2000_select_ratio_mode(priv, rate, parent_rate); if (ret < 0) return ret; @@ -382,8 +401,13 @@ static void cs2000_disable(struct clk_hw *hw) static u8 cs2000_get_parent(struct clk_hw *hw) { - /* always return REF_CLK */ - return REF_CLK; + struct cs2000_priv *priv = hw_to_priv(hw); + + /* + * In dynamic mode, output rates are derived from CLK_IN. + * In static mode, CLK_IN is ignored, so we return REF_CLK instead. + */ + return priv->dynamic_mode ? CLK_IN : REF_CLK; } static const struct clk_ops cs2000_ops = { @@ -424,28 +448,41 @@ static int cs2000_clk_register(struct cs2000_priv *priv) const char *name = np->name; static const char *parent_names[CLK_MAX]; u32 aux_out = 0; + int ref_clk_rate; int ch = 0; /* it uses ch0 only at this point */ - int rate; int ret; of_property_read_string(np, "clock-output-names", &name); + priv->dynamic_mode = of_property_read_bool(np, "cirrus,dynamic-mode"); + dev_info(dev, "operating in %s mode\n", + priv->dynamic_mode ? "dynamic" : "static"); + of_property_read_u32(np, "cirrus,aux-output-source", &aux_out); ret = cs2000_bset(priv, DEVICE_CFG1, AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); if (ret < 0) return ret; - /* - * set default rate as 1/1. - * otherwise .set_rate which setup ratio - * is never called if user requests 1/1 rate - */ - rate = clk_get_rate(priv->ref_clk); - ret = __cs2000_set_rate(priv, ch, rate, rate); + ref_clk_rate = clk_get_rate(priv->ref_clk); + ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate); if (ret < 0) return ret; + if (priv->dynamic_mode) { + /* Default to low-frequency mode to allow for large ratios */ + priv->lf_ratio = true; + } else { + /* + * set default rate as 1/1. + * otherwise .set_rate which setup ratio + * is never called if user requests 1/1 rate + */ + ret = __cs2000_set_rate(priv, ch, ref_clk_rate, ref_clk_rate); + if (ret < 0) + return ret; + } + parent_names[CLK_IN] = __clk_get_name(priv->clk_in); parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); -- cgit v1.2.3 From b83688258605900413dd6c85ac9278eea3bda614 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 25 Jan 2022 10:33:34 +0100 Subject: clk: cs2000-cp: make clock skip setting configurable The clock skip function of this chip is not necessarily desirable in all hardware appliances. This patch makes the feature configurable through a device-tree property. Signed-off-by: Daniel Mack Link: https://lore.kernel.org/r/20220125093336.226787-8-daniel@zonque.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-cs2000-cp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index bd030e156d65..9f99e39b41f2 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -81,6 +81,7 @@ struct cs2000_priv { bool dynamic_mode; bool lf_ratio; + bool clk_skip; /* suspend/resume */ unsigned long saved_rate; @@ -133,7 +134,7 @@ static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable) return ret; ret = cs2000_bset(priv, FUNC_CFG1, CLKSKIPEN, - enable ? CLKSKIPEN : 0); + (enable && priv->clk_skip) ? CLKSKIPEN : 0); if (ret < 0) return ret; @@ -464,6 +465,8 @@ static int cs2000_clk_register(struct cs2000_priv *priv) if (ret < 0) return ret; + priv->clk_skip = of_property_read_bool(np, "cirrus,clock-skip"); + ref_clk_rate = clk_get_rate(priv->ref_clk); ret = cs2000_ref_clk_bound_rate(priv, ref_clk_rate); if (ret < 0) -- cgit v1.2.3 From 2f3d32fe9df80a65485c548a145916145fc99d68 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 25 Jan 2022 10:33:35 +0100 Subject: clk: cs2000-cp: freeze config during register fiddling Make sure to freeze the configuration of the chip during the programming of 32-bit registers. This avoids the processing of invalid intermediate states. Signed-off-by: Daniel Mack Link: https://lore.kernel.org/r/20220125093336.226787-9-daniel@zonque.org Signed-off-by: Stephen Boyd --- drivers/clk/clk-cs2000-cp.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 9f99e39b41f2..1baf0595ba59 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -52,6 +52,7 @@ #define FRACNSRC_DYNAMIC (1 << 0) /* GLOBAL_CFG */ +#define FREEZE (1 << 7) #define ENDEV2 (0x1) /* FUNC_CFG1 */ @@ -335,6 +336,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, FREEZE); + if (ret < 0) + return ret; + ret = cs2000_select_ratio_mode(priv, rate, parent_rate); if (ret < 0) return ret; @@ -347,6 +352,10 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, if (ret < 0) return ret; + ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, 0); + if (ret < 0) + return ret; + priv->saved_rate = rate; priv->saved_parent_rate = parent_rate; -- cgit v1.2.3 From 5edffb980519c3d59f93fdaff7249af83c3a3495 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 25 Jan 2022 10:33:36 +0100 Subject: clk: cs2000-cp: convert driver to regmap Regmap gives us caching, debugging infrastructure and other things for free and does away with open-coded bit-fiddling implementations. Signed-off-by: Daniel Mack Link: https://lore.kernel.org/r/20220125093336.226787-10-daniel@zonque.org Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 1 + drivers/clk/clk-cs2000-cp.c | 124 ++++++++++++++++++++++++-------------------- 2 files changed, 69 insertions(+), 56 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..87ff6e2263f9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -197,6 +197,7 @@ config COMMON_CLK_CDCE925 config COMMON_CLK_CS2000_CP tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier" depends on I2C + select REGMAP_I2C help If you say yes here you get support for the CS2000 clock multiplier. diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c index 1baf0595ba59..dc5040a84dcc 100644 --- a/drivers/clk/clk-cs2000-cp.c +++ b/drivers/clk/clk-cs2000-cp.c @@ -11,6 +11,7 @@ #include #include #include +#include #define CH_MAX 4 #define RATIO_REG_SIZE 4 @@ -74,11 +75,36 @@ #define REF_CLK 1 #define CLK_MAX 2 +static bool cs2000_readable_reg(struct device *dev, unsigned int reg) +{ + return reg > 0; +} + +static bool cs2000_writeable_reg(struct device *dev, unsigned int reg) +{ + return reg != DEVICE_ID; +} + +static bool cs2000_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg == DEVICE_CTRL; +} + +static const struct regmap_config cs2000_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = FUNC_CFG2, + .readable_reg = cs2000_readable_reg, + .writeable_reg = cs2000_writeable_reg, + .volatile_reg = cs2000_volatile_reg, +}; + struct cs2000_priv { struct clk_hw hw; struct i2c_client *client; struct clk *clk_in; struct clk *ref_clk; + struct regmap *regmap; bool dynamic_mode; bool lf_ratio; @@ -101,41 +127,22 @@ static const struct i2c_device_id cs2000_id[] = { }; MODULE_DEVICE_TABLE(i2c, cs2000_id); -#define cs2000_read(priv, addr) \ - i2c_smbus_read_byte_data(priv_to_client(priv), addr) -#define cs2000_write(priv, addr, val) \ - i2c_smbus_write_byte_data(priv_to_client(priv), addr, val) - -static int cs2000_bset(struct cs2000_priv *priv, u8 addr, u8 mask, u8 val) -{ - s32 data; - - data = cs2000_read(priv, addr); - if (data < 0) - return data; - - data &= ~mask; - data |= (val & mask); - - return cs2000_write(priv, addr, data); -} - static int cs2000_enable_dev_config(struct cs2000_priv *priv, bool enable) { int ret; - ret = cs2000_bset(priv, DEVICE_CFG1, ENDEV1, - enable ? ENDEV1 : 0); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, ENDEV1, + enable ? ENDEV1 : 0); if (ret < 0) return ret; - ret = cs2000_bset(priv, GLOBAL_CFG, ENDEV2, - enable ? ENDEV2 : 0); + ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, ENDEV2, + enable ? ENDEV2 : 0); if (ret < 0) return ret; - ret = cs2000_bset(priv, FUNC_CFG1, CLKSKIPEN, - (enable && priv->clk_skip) ? CLKSKIPEN : 0); + ret = regmap_update_bits(priv->regmap, FUNC_CFG1, CLKSKIPEN, + (enable && priv->clk_skip) ? CLKSKIPEN : 0); if (ret < 0) return ret; @@ -156,21 +163,21 @@ static int cs2000_ref_clk_bound_rate(struct cs2000_priv *priv, else return -EINVAL; - return cs2000_bset(priv, FUNC_CFG1, - REFCLKDIV_MASK, - REFCLKDIV(val)); + return regmap_update_bits(priv->regmap, FUNC_CFG1, + REFCLKDIV_MASK, + REFCLKDIV(val)); } static int cs2000_wait_pll_lock(struct cs2000_priv *priv) { struct device *dev = priv_to_dev(priv); - s32 val; - unsigned int i; + unsigned int i, val; + int ret; for (i = 0; i < 256; i++) { - val = cs2000_read(priv, DEVICE_CTRL); - if (val < 0) - return val; + ret = regmap_read(priv->regmap, DEVICE_CTRL, &val); + if (ret < 0) + return ret; if (!(val & PLL_UNLOCK)) return 0; udelay(1); @@ -184,10 +191,10 @@ static int cs2000_wait_pll_lock(struct cs2000_priv *priv) static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable) { /* enable both AUX_OUT, CLK_OUT */ - return cs2000_bset(priv, DEVICE_CTRL, - (AUXOUTDIS | CLKOUTDIS), - enable ? 0 : - (AUXOUTDIS | CLKOUTDIS)); + return regmap_update_bits(priv->regmap, DEVICE_CTRL, + (AUXOUTDIS | CLKOUTDIS), + enable ? 0 : + (AUXOUTDIS | CLKOUTDIS)); } static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out, bool lf_ratio) @@ -235,7 +242,7 @@ static int cs2000_ratio_set(struct cs2000_priv *priv, val = cs2000_rate_to_ratio(rate_in, rate_out, priv->lf_ratio); for (i = 0; i < RATIO_REG_SIZE; i++) { - ret = cs2000_write(priv, + ret = regmap_write(priv->regmap, Ratio_Add(ch, i), Ratio_Val(val, i)); if (ret < 0) @@ -247,14 +254,14 @@ static int cs2000_ratio_set(struct cs2000_priv *priv, static u32 cs2000_ratio_get(struct cs2000_priv *priv, int ch) { - s32 tmp; + unsigned int tmp, i; u32 val; - unsigned int i; + int ret; val = 0; for (i = 0; i < RATIO_REG_SIZE; i++) { - tmp = cs2000_read(priv, Ratio_Add(ch, i)); - if (tmp < 0) + ret = regmap_read(priv->regmap, Ratio_Add(ch, i), &tmp); + if (ret < 0) return 0; val |= Val_Ratio(tmp, i); @@ -271,15 +278,15 @@ static int cs2000_ratio_select(struct cs2000_priv *priv, int ch) if (CH_SIZE_ERR(ch)) return -EINVAL; - ret = cs2000_bset(priv, DEVICE_CFG1, RSEL_MASK, RSEL(ch)); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, RSEL_MASK, RSEL(ch)); if (ret < 0) return ret; fracnsrc = priv->dynamic_mode ? FRACNSRC_DYNAMIC : FRACNSRC_STATIC; - ret = cs2000_bset(priv, DEVICE_CFG2, - AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK, - LOCKCLK(ch) | fracnsrc); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG2, + AUTORMOD | LOCKCLK_MASK | FRACNSRC_MASK, + LOCKCLK(ch) | fracnsrc); if (ret < 0) return ret; @@ -326,8 +333,8 @@ static int cs2000_select_ratio_mode(struct cs2000_priv *priv, */ priv->lf_ratio = priv->dynamic_mode && ((rate / parent_rate) > 4096); - return cs2000_bset(priv, FUNC_CFG2, LFRATIO_MASK, - priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20); + return regmap_update_bits(priv->regmap, FUNC_CFG2, LFRATIO_MASK, + priv->lf_ratio ? LFRATIO_20_12 : LFRATIO_12_20); } static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, @@ -336,7 +343,7 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, { int ret; - ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, FREEZE); + ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, FREEZE); if (ret < 0) return ret; @@ -352,7 +359,7 @@ static int __cs2000_set_rate(struct cs2000_priv *priv, int ch, if (ret < 0) return ret; - ret = cs2000_bset(priv, GLOBAL_CFG, FREEZE, 0); + ret = regmap_update_bits(priv->regmap, GLOBAL_CFG, FREEZE, 0); if (ret < 0) return ret; @@ -469,8 +476,8 @@ static int cs2000_clk_register(struct cs2000_priv *priv) priv->dynamic_mode ? "dynamic" : "static"); of_property_read_u32(np, "cirrus,aux-output-source", &aux_out); - ret = cs2000_bset(priv, DEVICE_CFG1, - AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); + ret = regmap_update_bits(priv->regmap, DEVICE_CFG1, + AUXOUTSRC_MASK, AUXOUTSRC(aux_out)); if (ret < 0) return ret; @@ -522,12 +529,13 @@ static int cs2000_clk_register(struct cs2000_priv *priv) static int cs2000_version_print(struct cs2000_priv *priv) { struct device *dev = priv_to_dev(priv); - s32 val; const char *revision; + unsigned int val; + int ret; - val = cs2000_read(priv, DEVICE_ID); - if (val < 0) - return val; + ret = regmap_read(priv->regmap, DEVICE_ID, &val); + if (ret < 0) + return ret; /* CS2000 should be 0x0 */ if (val >> 3) @@ -576,6 +584,10 @@ static int cs2000_probe(struct i2c_client *client, priv->client = client; i2c_set_clientdata(client, priv); + priv->regmap = devm_regmap_init_i2c(client, &cs2000_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + ret = cs2000_clk_get(priv); if (ret < 0) return ret; -- cgit v1.2.3 From 7154b046d8f3a441474ced1688eb348d42f5f165 Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Tue, 11 Jan 2022 16:54:13 -0500 Subject: clk: imx: Add initial support for i.MXRT1050 clock driver Add clock driver support for i.MXRT1050. Signed-off-by: Jesse Taube Suggested-by: Giulio Benetti Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20220111215415.2075257-6-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa --- drivers/clk/imx/Kconfig | 7 ++ drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imxrt1050.c | 168 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 176 insertions(+) create mode 100644 drivers/clk/imx/clk-imxrt1050.c (limited to 'drivers/clk') diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index c08edbd04d22..45641b8bdc50 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -105,3 +105,10 @@ config CLK_IMX8ULP select MXC_CLK help Build the driver for i.MX8ULP CCM Clock Driver + +config CLK_IMXRT1050 + tristate "IMXRT1050 CCM Clock Driver" + depends on SOC_IMXRT + select MXC_CLK + help + Build the driver for i.MXRT1050 CCM Clock Driver diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b5e040026dfb..1e13c5cb37d9 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -46,4 +46,5 @@ obj-$(CONFIG_CLK_IMX6SX) += clk-imx6sx.o obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o +obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o obj-$(CONFIG_CLK_VF610) += clk-vf610.o diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c new file mode 100644 index 000000000000..9539d35588ee --- /dev/null +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 + * Author(s): + * Jesse Taube + * Giulio Benetti + */ +#include +#include +#include +#include +#include + +#include "clk.h" + +static const char * const pll_ref_sels[] = {"osc", "dummy", }; +static const char * const per_sels[] = {"ipg_pdof", "osc", }; +static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; +static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; +static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", }; +static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; +static const char *const pre_periph_sels[] = { + "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; +static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; +static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; +static const char *const lcdif_sels[] = { + "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m", + "pll2_pfd1_594m", "pll3_pfd1_664_62m", }; +static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; +static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; + +static struct clk_hw **hws; +static struct clk_hw_onecell_data *clk_hw_data; + +static int imxrt1050_clocks_probe(struct platform_device *pdev) +{ + void __iomem *ccm_base; + void __iomem *pll_base; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *anp; + int ret; + + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, + IMXRT1050_CLK_END), GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num = IMXRT1050_CLK_END; + hws = clk_hw_data->hws; + + hws[IMXRT1050_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc"); + + anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop"); + pll_base = of_iomap(anp, 0); + of_node_put(anp); + if (WARN_ON(!pll_base)) + return -ENOMEM; + + /* Anatop clocks */ + hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL); + + hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel", + pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel", + pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel", + pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel", + pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm", + "pll1_arm_ref_sel", pll_base + 0x0, 0x7f); + hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", + "pll2_sys_ref_sel", pll_base + 0x30, 0x1); + hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", + "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1); + hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5_video", + "pll5_video_ref_sel", pll_base + 0xa0, 0x7f); + + /* PLL bypass out */ + hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", pll_base + 0x0, 16, 1, + pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", pll_base + 0x30, 16, 1, + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", pll_base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); + hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", pll_base + 0xa0, 16, 1, + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); + + hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel", + "pll5_video", pll_base + 0xa0, 19, 2); + hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div", + "video_post_div_sel", pll_base + 0x170, 30, 2); + + hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); + + hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_sys", pll_base + 0x100, 0); + hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_sys", pll_base + 0x100, 1); + hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_sys", pll_base + 0x100, 2); + hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", pll_base + 0xf0, 1); + hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", pll_base + 0xf0, 3); + + /* CCM clocks */ + ccm_base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(ccm_base))) + return PTR_ERR(ccm_base); + + hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3); + hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2, + pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); + hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1, + periph_sels, ARRAY_SIZE(periph_sels)); + hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1, + usdhc_sels, ARRAY_SIZE(usdhc_sels)); + hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1, + usdhc_sels, ARRAY_SIZE(usdhc_sels)); + hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1, + lpuart_sels, ARRAY_SIZE(lpuart_sels)); + hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3, + lcdif_sels, ARRAY_SIZE(lcdif_sels)); + hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1, + per_sels, ARRAY_SIZE(per_sels)); + hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1, + semc_alt_sels, ARRAY_SIZE(semc_alt_sels)); + hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1, + semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL); + + hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3); + hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2); + hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per", "per_sel", ccm_base + 0x1C, 0, 5); + + hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", ccm_base + 0x24, 11, 3); + hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", ccm_base + 0x24, 16, 3); + hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf", "lpuart_sel", ccm_base + 0x24, 0, 6); + hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_sel", ccm_base + 0x38, 12, 3); + hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", ccm_base + 0x18, 23, 3); + + hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); + hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); + hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); + hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); + hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); + hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); + imx_check_clk_hws(hws, IMXRT1050_CLK_END); + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + dev_err(dev, "Failed to register clks for i.MXRT1050.\n"); + imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END); + } + return ret; +} +static const struct of_device_id imxrt1050_clk_of_match[] = { + { .compatible = "fsl,imxrt1050-ccm" }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match); + +static struct platform_driver imxrt1050_clk_driver = { + .probe = imxrt1050_clocks_probe, + .driver = { + .name = "imxrt1050-ccm", + .of_match_table = imxrt1050_clk_of_match, + }, +}; +module_platform_driver(imxrt1050_clk_driver); -- cgit v1.2.3 From 036a4b4b4dfa6c56806b71daf8589044ff7aeeaa Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 17 Dec 2021 15:25:33 +0200 Subject: clk: imx: Add imx8dxl clk driver Add files for imx8dxl clk driver which is based on imx8qxp clock driver. Signed-off-by: Jacky Bai Signed-off-by: Abel Vesa Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/1639747533-9778-1-git-send-email-abel.vesa@nxp.com --- drivers/clk/imx/Makefile | 3 +- drivers/clk/imx/clk-imx8dxl-rsrc.c | 66 ++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8qxp.c | 1 + drivers/clk/imx/clk-scu.h | 1 + 4 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/imx/clk-imx8dxl-rsrc.c (limited to 'drivers/clk') diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 1e13c5cb37d9..aa8f5204d7e1 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -28,7 +28,8 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \ - clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o + clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \ + clk-imx8dxl-rsrc.o clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o obj-$(CONFIG_CLK_IMX8ULP) += clk-imx8ulp.o diff --git a/drivers/clk/imx/clk-imx8dxl-rsrc.c b/drivers/clk/imx/clk-imx8dxl-rsrc.c new file mode 100644 index 000000000000..69b7aa34fff5 --- /dev/null +++ b/drivers/clk/imx/clk-imx8dxl-rsrc.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019~2020 NXP + */ + +#include + +#include "clk-scu.h" + +/* Keep sorted in the ascending order */ +static u32 imx8dxl_clk_scu_rsrc_table[] = { + IMX_SC_R_SPI_0, + IMX_SC_R_SPI_1, + IMX_SC_R_SPI_2, + IMX_SC_R_SPI_3, + IMX_SC_R_UART_0, + IMX_SC_R_UART_1, + IMX_SC_R_UART_2, + IMX_SC_R_UART_3, + IMX_SC_R_I2C_0, + IMX_SC_R_I2C_1, + IMX_SC_R_I2C_2, + IMX_SC_R_I2C_3, + IMX_SC_R_ADC_0, + IMX_SC_R_FTM_0, + IMX_SC_R_FTM_1, + IMX_SC_R_CAN_0, + IMX_SC_R_LCD_0, + IMX_SC_R_LCD_0_PWM_0, + IMX_SC_R_PWM_0, + IMX_SC_R_PWM_1, + IMX_SC_R_PWM_2, + IMX_SC_R_PWM_3, + IMX_SC_R_PWM_4, + IMX_SC_R_PWM_5, + IMX_SC_R_PWM_6, + IMX_SC_R_PWM_7, + IMX_SC_R_GPT_0, + IMX_SC_R_GPT_1, + IMX_SC_R_GPT_2, + IMX_SC_R_GPT_3, + IMX_SC_R_GPT_4, + IMX_SC_R_FSPI_0, + IMX_SC_R_FSPI_1, + IMX_SC_R_SDHC_0, + IMX_SC_R_SDHC_1, + IMX_SC_R_SDHC_2, + IMX_SC_R_ENET_0, + IMX_SC_R_ENET_1, + IMX_SC_R_MLB_0, + IMX_SC_R_USB_1, + IMX_SC_R_NAND, + IMX_SC_R_M4_0_I2C, + IMX_SC_R_M4_0_UART, + IMX_SC_R_ELCDIF_PLL, + IMX_SC_R_AUDIO_PLL_0, + IMX_SC_R_AUDIO_PLL_1, + IMX_SC_R_AUDIO_CLK_0, + IMX_SC_R_AUDIO_CLK_1, + IMX_SC_R_A35 +}; + +const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = { + .rsrc = imx8dxl_clk_scu_rsrc_table, + .num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table), +}; diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 40a2efb1329b..546a3703bfeb 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -295,6 +295,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) static const struct of_device_id imx8qxp_match[] = { { .compatible = "fsl,scu-clk", }, + { .compatible = "fsl,imx8dxl-clk", &imx_clk_scu_rsrc_imx8dxl, }, { .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, }, { .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, }, { /* sentinel */ } diff --git a/drivers/clk/imx/clk-scu.h b/drivers/clk/imx/clk-scu.h index 22156e93b85d..af7b697f51ca 100644 --- a/drivers/clk/imx/clk-scu.h +++ b/drivers/clk/imx/clk-scu.h @@ -21,6 +21,7 @@ struct imx_clk_scu_rsrc_table { extern struct list_head imx_scu_clks[]; extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops; +extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl; extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp; extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm; -- cgit v1.2.3 From 842f4cb7263953020f4e2f2f0005fc3e6fc56144 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 26 Jan 2022 15:55:33 +0100 Subject: clk: rockchip: Add more PLL rates for rk3568 This adds a few more PLL settings needed for some standard resolutions: 297MHz 3840x2160-30.00 241.5MHz 2560x1440-59.95 135MHz 1280x1024-75.02 119MHz 1680x1050-59.88 108MHz 1280x1024-60.02 78.75MHz 1024x768-75.03 Changes since v3: - new patch Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20220126145549.617165-12-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3568.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 69a9e8069a48..9d889fc46811 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), + RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), + RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), { /* sentinel */ }, }; -- cgit v1.2.3 From ff3187eabb5ce478d15b6ed62eb286756adefac3 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 26 Jan 2022 15:55:46 +0100 Subject: clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or cpll. gpll and cpll also drive many other clocks, so changing the dclk_vop[012] clocks could change these other clocks as well. Drop CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can only adjust the pixel clocks with the divider between the PLL and the dclk_vop[012] which means the user may have to adjust the PLL clock to a suitable rate using the assigned-clock-rate device tree property. Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20220126145549.617165-25-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3568.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 9d889fc46811..7687c62d1fa8 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1044,13 +1044,13 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKGATE_CON(20), 8, GFLAGS), GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, RK3568_CLKGATE_CON(20), 9, GFLAGS), - COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 10, GFLAGS), - COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 11, GFLAGS), - COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, + COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, RK3568_CLKGATE_CON(20), 12, GFLAGS), GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, -- cgit v1.2.3 From 6e69052f01d9131388cfcfaee929120118a267f4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 26 Jan 2022 15:55:47 +0100 Subject: clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the rk3568 we have this (simplified) situation: .--------. .-----. .---------. -| hpll |--.--| /n |----|dclk_vop0|- `--------´ | `-----´ `---------´ | .-----. .---------. `--| /m |----|dclk_vop1|- | `-----´ `---------´ | .---------. `-------------|hdmi_ref |- `---------´ For the HDMI to work the HDMI reference clock needs to be the same as the pixel clock which means the dividers have be set to one. The last patch removed the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not changed on pixel clock changes. In order to allow the HDMI controller to set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the HDMI reference clock. With this the flow becomes: 1) HDMI controller driver sets the rate to its pixel clock which means hpll is set to the pixel clock 2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change the hpll clock anymore this means only the divider is adjusted to the desired value of dividing by one. Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20220126145549.617165-26-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3568.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 7687c62d1fa8..63dfbeeeb06d 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), - MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, + MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), }; -- cgit v1.2.3 From a1bcf50a99dd1e40f0c6a963bd4f12547a89d4cd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 5 Feb 2022 08:40:06 +0000 Subject: clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a07g044-cpg.c | 426 ++++++++++++++++++++---------------- drivers/clk/renesas/rzg2l-cpg.c | 6 + drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 250 insertions(+), 191 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index be6e6ae7448c..c281f3af5716 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -34,6 +34,7 @@ config CLK_RENESAS select CLK_R8A779F0 if ARCH_R8A779F0 select CLK_R9A06G032 if ARCH_R9A06G032 select CLK_R9A07G044 if ARCH_R9A07G044 + select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -163,6 +164,10 @@ config CLK_R9A07G044 bool "RZ/G2L clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A07G054 + bool "RZ/V2L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP @@ -195,7 +200,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector config CLK_RZG2L - bool "Renesas RZ/G2L family clock support" if COMPILE_TEST + bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER # Generic diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 8b34db1a328c..d5e571699a30 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o +obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 46359afef0d4..bdfabb992a20 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -11,12 +11,13 @@ #include #include +#include #include "rzg2l-cpg.h" enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2, + LAST_DT_CORE_CLK = R9A07G054_CLK_DRP_A, /* External Input Clocks */ CLK_EXTAL, @@ -80,200 +81,222 @@ static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" }; -static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { - /* External Clock Inputs */ - DEF_INPUT("extal", CLK_EXTAL), +static const struct { + struct cpg_core_clk common[44]; +#ifdef CONFIG_CLK_R9A07G054 + struct cpg_core_clk drp[0]; +#endif +} core_clks __initconst = { + .common = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), - /* Internal Core Clocks */ - DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), - DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), - DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), - DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), - DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), - DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), - DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), + /* Internal Core Clocks */ + DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), + DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4), + DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3), - DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), - DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), + DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6), - DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), - DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), - DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), - DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), - DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2), + DEF_FIXED(".clk_533", CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), + DEF_FIXED(".clk_400", CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), + DEF_FIXED(".clk_266", CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), - DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), - DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), + DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), + DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), - DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), - DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), - DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), - DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), - DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, - sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), - DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, - DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), + DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), + DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), + DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, + sel_pll3_3, ARRAY_SIZE(sel_pll3_3), 0, CLK_MUX_READ_ONLY), + DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, + DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), - DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), - DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, - sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), + DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2), + DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2), + DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, + sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY), - /* Core output clk */ - DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), - DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, - dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), - DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), - DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, - DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), - DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, - DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), - DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), - DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), - DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, - sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), - DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), - DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), - DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, - sel_shdi, ARRAY_SIZE(sel_shdi)), - DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, - sel_shdi, ARRAY_SIZE(sel_shdi)), - DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), - DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), - DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, - CLK_DIVIDER_HIWORD_MASK), + /* Core output clk */ + DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), + DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, + dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), + DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), + DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, + DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), + DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, + DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), + DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), + DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), + DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, + sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, + sel_shdi, ARRAY_SIZE(sel_shdi)), + DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4), + DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4), + DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8, + CLK_DIVIDER_HIWORD_MASK), + }, +#ifdef CONFIG_CLK_R9A07G054 + .drp = { + }, +#endif }; -static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { - DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, - 0x514, 0), - DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, - 0x518, 0), - DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, - 0x518, 1), - DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, - 0x52c, 0), - DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, - 0x52c, 1), - DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, - 0x534, 0), - DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, - 0x534, 1), - DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, - 0x534, 2), - DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, - 0x548, 0), - DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, - 0x548, 1), - DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, - 0x548, 2), - DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, - 0x548, 3), - DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, - 0x548, 4), - DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, - 0x548, 5), - DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, - 0x550, 0), - DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, - 0x550, 1), - DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, - 0x554, 0), - DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, - 0x554, 1), - DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, - 0x554, 2), - DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, - 0x554, 3), - DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, - 0x554, 4), - DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, - 0x554, 5), - DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, - 0x554, 6), - DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, - 0x554, 7), - DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, - 0x558, 0), - DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, - 0x558, 1), - DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, - 0x558, 2), - DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, - 0x570, 0), - DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 1), - DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, - 0x570, 2), - DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 3), - DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, - 0x570, 4), - DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 5), - DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, - 0x570, 6), - DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, - 0x570, 7), - DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, - 0x578, 0), - DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, - 0x578, 1), - DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, - 0x578, 2), - DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, - 0x578, 3), - DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, - 0x57c, 0), - DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, - 0x57c, 0), - DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, - 0x57c, 1), - DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, - 0x57c, 1), - DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, - 0x580, 0), - DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, - 0x580, 1), - DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, - 0x580, 2), - DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, - 0x580, 3), - DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 0), - DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 1), - DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 2), - DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 3), - DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, - 0x584, 4), - DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, - 0x588, 0), - DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, - 0x588, 1), - DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, - 0x590, 0), - DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, - 0x590, 1), - DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, - 0x590, 2), - DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, - 0x594, 0), - DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, - 0x598, 0), - DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, - 0x5a8, 0), - DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, - 0x5a8, 1), - DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, - 0x5ac, 0), +static const struct { + struct rzg2l_mod_clk common[62]; +#ifdef CONFIG_CLK_R9A07G054 + struct rzg2l_mod_clk drp[0]; +#endif +} mod_clks = { + .common = { + DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, + 0x514, 0), + DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, + 0x518, 0), + DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, + 0x518, 1), + DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, + 0x52c, 0), + DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, + 0x52c, 1), + DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, + 0x534, 0), + DEF_MOD("ostm1_clk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, + 0x534, 1), + DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, + 0x534, 2), + DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, + 0x548, 0), + DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, + 0x548, 1), + DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, + 0x548, 2), + DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, + 0x548, 3), + DEF_MOD("wdt2_pclk", R9A07G044_WDT2_PCLK, R9A07G044_CLK_P0, + 0x548, 4), + DEF_MOD("wdt2_clk", R9A07G044_WDT2_CLK, R9A07G044_OSCCLK, + 0x548, 5), + DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, + 0x550, 0), + DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, + 0x550, 1), + DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, + 0x554, 0), + DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, + 0x554, 1), + DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, + 0x554, 2), + DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, + 0x554, 3), + DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, + 0x554, 4), + DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, + 0x554, 5), + DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, + 0x554, 6), + DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, + 0x554, 7), + DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, + 0x558, 0), + DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, + 0x558, 1), + DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, + 0x558, 2), + DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, + 0x570, 0), + DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 1), + DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, + 0x570, 2), + DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 3), + DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, + 0x570, 4), + DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 5), + DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, + 0x570, 6), + DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, + 0x570, 7), + DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, + 0x578, 0), + DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, + 0x578, 1), + DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, + 0x578, 2), + DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, + 0x578, 3), + DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, + 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, + 0x57c, 0), + DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, + 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, + 0x57c, 1), + DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, + 0x580, 0), + DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, + 0x580, 1), + DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, + 0x580, 2), + DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, + 0x580, 3), + DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 0), + DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 1), + DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 2), + DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 3), + DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, + 0x584, 4), + DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, + 0x588, 0), + DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, + 0x588, 1), + DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, + 0x590, 0), + DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, + 0x590, 1), + DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, + 0x590, 2), + DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, + 0x594, 0), + DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, + 0x598, 0), + DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, + 0x5a8, 0), + DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, + 0x5a8, 1), + DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, + 0x5ac, 0), + }, +#ifdef CONFIG_CLK_R9A07G054 + .drp = { + }, +#endif }; static struct rzg2l_reset r9a07g044_resets[] = { @@ -336,8 +359,8 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { const struct rzg2l_cpg_info r9a07g044_cpg_info = { /* Core Clocks */ - .core_clks = r9a07g044_core_clks, - .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks), + .core_clks = core_clks.common, + .num_core_clks = ARRAY_SIZE(core_clks.common), .last_dt_core_clk = LAST_DT_CORE_CLK, .num_total_core_clks = MOD_CLK_BASE, @@ -346,11 +369,34 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), /* Module Clocks */ - .mod_clks = r9a07g044_mod_clks, - .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks), + .mod_clks = mod_clks.common, + .num_mod_clks = ARRAY_SIZE(mod_clks.common), .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1, /* Resets */ .resets = r9a07g044_resets, - .num_resets = ARRAY_SIZE(r9a07g044_resets), + .num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ +}; + +#ifdef CONFIG_CLK_R9A07G054 +const struct rzg2l_cpg_info r9a07g054_cpg_info = { + /* Core Clocks */ + .core_clks = core_clks.common, + .num_core_clks = ARRAY_SIZE(core_clks.common) + ARRAY_SIZE(core_clks.drp), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a07g044_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = mod_clks.common, + .num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp), + .num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1, + + /* Resets */ + .resets = r9a07g044_resets, + .num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ }; +#endif diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index edd0abe34a37..486d0656c58a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = { .compatible = "renesas,r9a07g044-cpg", .data = &r9a07g044_cpg_info, }, +#endif +#ifdef CONFIG_CLK_R9A07G054 + { + .compatible = "renesas,r9a07g054-cpg", + .data = &r9a07g054_cpg_info, + }, #endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 5729d102034b..ce657beaf160 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -203,5 +203,6 @@ struct rzg2l_cpg_info { }; extern const struct rzg2l_cpg_info r9a07g044_cpg_info; +extern const struct rzg2l_cpg_info r9a07g054_cpg_info; #endif -- cgit v1.2.3 From bf8f5182b8f59309809b41c1d1730ed9ca6134b1 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 20 Dec 2021 12:41:19 +0100 Subject: clk: qcom: ipq8074: fix PCI-E clock oops Fix PCI-E clock related kernel oops that are caused by a missing clock parent. pcie0_rchng_clk_src has num_parents set to 2 but only one parent is actually set via parent_hws, it should also have "XO" defined. This will cause the kernel to panic on a NULL pointer in clk_core_get_parent_by_index(). So, to fix this utilize clk_parent_data to provide gcc_xo_gpll0 parent data. Since there is already an existing static const char * const gcc_xo_gpll0[] used to provide the same parents via parent_names convert those users to clk_parent_data as well. Without this earlycon is needed to even catch the OOPS as it will reset the board before serial is initialized with the following: [ 0.232279] Unable to handle kernel paging request at virtual address 0000a00000000000 [ 0.232322] Mem abort info: [ 0.239094] ESR = 0x96000004 [ 0.241778] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.244908] SET = 0, FnV = 0 [ 0.250377] EA = 0, S1PTW = 0 [ 0.253236] FSC = 0x04: level 0 translation fault [ 0.256277] Data abort info: [ 0.261141] ISV = 0, ISS = 0x00000004 [ 0.264262] CM = 0, WnR = 0 [ 0.267820] [0000a00000000000] address between user and kernel address ranges [ 0.270954] Internal error: Oops: 96000004 [#1] SMP [ 0.278067] Modules linked in: [ 0.282751] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.10 #0 [ 0.285882] Hardware name: Xiaomi AX3600 (DT) [ 0.292043] pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.296299] pc : clk_core_get_parent_by_index+0x68/0xec [ 0.303067] lr : __clk_register+0x1d8/0x820 [ 0.308273] sp : ffffffc01111b7d0 [ 0.312438] x29: ffffffc01111b7d0 x28: 0000000000000000 x27: 0000000000000040 [ 0.315919] x26: 0000000000000002 x25: 0000000000000000 x24: ffffff8000308800 [ 0.323037] x23: ffffff8000308850 x22: ffffff8000308880 x21: ffffff8000308828 [ 0.330155] x20: 0000000000000028 x19: ffffff8000309700 x18: 0000000000000020 [ 0.337272] x17: 000000005cc86990 x16: 0000000000000004 x15: ffffff80001d9d0a [ 0.344391] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000006 [ 0.351508] x11: 0000000000000003 x10: 0101010101010101 x9 : 0000000000000000 [ 0.358626] x8 : 7f7f7f7f7f7f7f7f x7 : 6468626f5e626266 x6 : 17000a3a403c1b06 [ 0.365744] x5 : 061b3c403a0a0017 x4 : 0000000000000000 x3 : 0000000000000001 [ 0.372863] x2 : 0000a00000000000 x1 : 0000000000000001 x0 : ffffff8000309700 [ 0.379982] Call trace: [ 0.387091] clk_core_get_parent_by_index+0x68/0xec [ 0.389351] __clk_register+0x1d8/0x820 [ 0.394210] devm_clk_hw_register+0x5c/0xe0 [ 0.398030] devm_clk_register_regmap+0x44/0x8c [ 0.402198] qcom_cc_really_probe+0x17c/0x1d0 [ 0.406711] qcom_cc_probe+0x34/0x44 [ 0.411224] gcc_ipq8074_probe+0x18/0x30 [ 0.414869] platform_probe+0x68/0xe0 [ 0.418776] really_probe.part.0+0x9c/0x30c [ 0.422336] __driver_probe_device+0x98/0x144 [ 0.426329] driver_probe_device+0x44/0x11c [ 0.430842] __device_attach_driver+0xb4/0x120 [ 0.434836] bus_for_each_drv+0x68/0xb0 [ 0.439349] __device_attach+0xb0/0x170 [ 0.443081] device_initial_probe+0x14/0x20 [ 0.446901] bus_probe_device+0x9c/0xa4 [ 0.451067] device_add+0x35c/0x834 [ 0.454886] of_device_add+0x54/0x64 [ 0.458360] of_platform_device_create_pdata+0xc0/0x100 [ 0.462181] of_platform_bus_create+0x114/0x370 [ 0.467128] of_platform_bus_create+0x15c/0x370 [ 0.471641] of_platform_populate+0x50/0xcc [ 0.476155] of_platform_default_populate_init+0xa8/0xc8 [ 0.480324] do_one_initcall+0x50/0x1b0 [ 0.485877] kernel_init_freeable+0x234/0x29c [ 0.489436] kernel_init+0x24/0x120 [ 0.493948] ret_from_fork+0x10/0x20 [ 0.497253] Code: d50323bf d65f03c0 f94002a2 b4000302 (f9400042) [ 0.501079] ---[ end trace 4ca7e1129da2abce ]--- Fixes: f0cfcf1a ("clk: qcom: ipq8074: Add missing clocks for pcie") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211220114119.465247-1-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 108fe27bee10..b09d99343e09 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -60,11 +60,6 @@ static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { { P_GPLL0_DIV2, 4 }, }; -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0", -}; - static const struct parent_map gcc_xo_gpll0_map[] = { { P_XO, 0 }, { P_GPLL0, 1 }, @@ -956,6 +951,11 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { }, }; +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, +}; + static const struct freq_tbl ftbl_pcie_axi_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(200000000, P_GPLL0, 4, 0, 0), @@ -969,7 +969,7 @@ static struct clk_rcg2 pcie0_axi_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie0_axi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -1016,7 +1016,7 @@ static struct clk_rcg2 pcie1_axi_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie1_axi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -1330,7 +1330,7 @@ static struct clk_rcg2 nss_ce_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "nss_ce_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, @@ -4329,8 +4329,7 @@ static struct clk_rcg2 pcie0_rchng_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie0_rchng_clk_src", - .parent_hws = (const struct clk_hw *[]) { - &gpll0.clkr.hw }, + .parent_data = gcc_xo_gpll0, .num_parents = 2, .ops = &clk_rcg2_ops, }, -- cgit v1.2.3 From cc517ea3333f586cb63d76f4e1e8ae3d2469b010 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Wed, 9 Feb 2022 19:45:08 +0100 Subject: clk: qcom: Add display clock controller driver for QCM2290 Add support for the display clock controller found in QCM2290 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). It's a porting of dispcc-scuba GPL-2.0 driver from CAF msm-4.19 kernel: https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/clk/qcom/dispcc-scuba.c?h=LE.UM.4.4.1.r3 Global clock name references (parent_names) have been replaced by parent_data and parent_hws. Clocks marked enable_safe_config have their clk_rcg2_ops moved to clk_rcg2_shared_ops. Signed-off-by: Loic Poulain Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1644432308-21099-2-git-send-email-loic.poulain@linaro.org --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-qcm2290.c | 555 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 565 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-qcm2290.c (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 42c874194d1a..f5b54bfc992f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -340,6 +340,15 @@ config QCM_GCC_2290 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC etc. +config QCM_DISPCC_2290 + tristate "QCM2290 Display Clock Controller" + select QCM_GCC_2290 + help + Support for the display clock controller on Qualcomm Technologies, Inc + QCM2290 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config QCS_GCC_404 tristate "QCS404 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 0d98ca9be67f..d96d6793fc7d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCM_GCC_2290) += gcc-qcm2290.o +obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c new file mode 100644 index 000000000000..96b149365912 --- /dev/null +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco spark_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +/* 768MHz configuration */ +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x28, + .alpha = 0x0, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055B, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = spark_vco, + .num_vco = ARRAY_SIZE(spark_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo_ao" }, + { .fw_name = "gcc_disp_gpll0_div_clk_src" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk_src" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "dsi1_phy_pll_out_dsiclk" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .fw_name = "sleep_clk" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x20a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + /* For set_rate and set_parent to succeed, parent(s) must be enabled */ + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x20bc, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x20c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x2074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x205c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + /* For set_rate and set_parent to succeed, parent(s) must be enabled */ + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x208c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { + F(32764, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_sleep_clk_src = { + .cmd_rcgr = 0x6050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .freq_tbl = ftbl_disp_cc_sleep_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_sleep_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x201c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x2020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x2024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x2010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x2018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_sleep_clk = { + .halt_reg = 0x6068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6068, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_sleep_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_sleep_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x3000, + .pd = { + .name = "mdss_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL, +}; + +static struct gdsc *disp_cc_qcm2290_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, +}; + +static struct clk_regmap *disp_cc_qcm2290_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, + [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, +}; + +static const struct regmap_config disp_cc_qcm2290_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_qcm2290_desc = { + .config = &disp_cc_qcm2290_regmap_config, + .clks = disp_cc_qcm2290_clocks, + .num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks), + .gdscs = disp_cc_qcm2290_gdscs, + .num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs), +}; + +static const struct of_device_id disp_cc_qcm2290_match_table[] = { + { .compatible = "qcom,qcm2290-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table); + +static int disp_cc_qcm2290_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + + /* Keep DISP_CC_XO_CLK always-ON */ + regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + + ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register DISP CC clocks\n"); + return ret; + } + + return ret; +} + +static struct platform_driver disp_cc_qcm2290_driver = { + .probe = disp_cc_qcm2290_probe, + .driver = { + .name = "dispcc-qcm2290", + .of_match_table = disp_cc_qcm2290_match_table, + }, +}; + +static int __init disp_cc_qcm2290_init(void) +{ + return platform_driver_register(&disp_cc_qcm2290_driver); +} +subsys_initcall(disp_cc_qcm2290_init); + +static void __exit disp_cc_qcm2290_exit(void) +{ + platform_driver_unregister(&disp_cc_qcm2290_driver); +} +module_exit(disp_cc_qcm2290_exit); + +MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 30ac9f356f50bee4e388789fc2717b264bf0609d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:00 +0300 Subject: clk: qcom: gpucc-sdm660: fix two clocks with parent_names Two clocks are still using parent_names, use parent_hws instead. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-2-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gpucc-sdm660.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 41bba96a08b3..d170353eccf6 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -204,8 +204,8 @@ static struct clk_branch gpucc_rbbmtimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_rbbmtimer_clk", - .parent_names = (const char *[]){ - "rbbmtimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &rbbmtimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -222,8 +222,8 @@ static struct clk_branch gpucc_rbcpr_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_rbcpr_clk", - .parent_names = (const char *[]){ - "rbcpr_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &rbcpr_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- cgit v1.2.3 From 6985fdc0c80c4fe576a196a12c8be11501f5c3f2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:01 +0300 Subject: clk: qcom: gpucc-sdm660: get rid of the test clock The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-3-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gpucc-sdm660.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index d170353eccf6..8271696d21b4 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -29,7 +29,6 @@ enum { P_GPU_XO, - P_CORE_BI_PLL_TEST_SE, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, P_GPU_PLL0_PLL_OUT_MAIN, -- cgit v1.2.3 From ba9b57dcac4f33bd836e64bbb9591d9adeb369d2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:02 +0300 Subject: clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-4-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gpucc-sdm660.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index 8271696d21b4..d6b38a0b063d 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -65,8 +65,8 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = { .num_vco = ARRAY_SIZE(gpu_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_pll0_pll_out_main", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpucc_cxo_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpucc_cxo_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -80,8 +80,8 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = { .num_vco = ARRAY_SIZE(gpu_vco), .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_pll1_pll_out_main", - .parent_data = &(const struct clk_parent_data){ - .hw = &gpucc_cxo_clk.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gpucc_cxo_clk.clkr.hw, }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -134,8 +134,8 @@ static struct clk_branch gpucc_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpucc_gfx3d_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gfx3d_clk_src.rcg.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &gfx3d_clk_src.rcg.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, -- cgit v1.2.3 From 3ca90171215619fa598a1dd8a3077cf01b8c74d1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:03 +0300 Subject: clk: qcom: camcc-sc7180: use ARRAY_SIZE instead of specifying num_parents Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-5-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sc7180.c | 50 ++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index ce73ee9037cb..f6e303976a0d 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -303,7 +303,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -324,7 +324,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .parent_data = cam_cc_parent_data_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), .ops = &clk_rcg2_shared_ops, }, }; @@ -338,7 +338,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .parent_data = cam_cc_parent_data_5, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), .ops = &clk_rcg2_shared_ops, }, }; @@ -359,7 +359,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -378,7 +378,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -392,7 +392,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -406,7 +406,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -420,7 +420,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -442,7 +442,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -465,7 +465,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -487,7 +487,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", .parent_data = cam_cc_parent_data_4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .ops = &clk_rcg2_shared_ops, }, }; @@ -509,7 +509,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -523,7 +523,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", .parent_data = cam_cc_parent_data_4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .ops = &clk_rcg2_shared_ops, }, }; @@ -537,7 +537,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -551,7 +551,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .parent_data = cam_cc_parent_data_4, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -566,7 +566,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", .parent_data = cam_cc_parent_data_3, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .ops = &clk_rcg2_shared_ops, }, }; @@ -589,7 +589,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -612,7 +612,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", .parent_data = cam_cc_parent_data_2, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .ops = &clk_rcg2_shared_ops, }, }; @@ -634,7 +634,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk_src", .parent_data = cam_cc_parent_data_6, - .num_parents = 5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), .ops = &clk_rcg2_shared_ops, }, }; @@ -655,7 +655,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -669,7 +669,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -683,7 +683,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -697,7 +697,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -711,7 +711,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk_src", .parent_data = cam_cc_parent_data_1, - .num_parents = 3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .ops = &clk_rcg2_shared_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .parent_data = cam_cc_parent_data_0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, .ops = &clk_rcg2_shared_ops, }, -- cgit v1.2.3 From 5d57a18f25698f039a3ecfe25efd3cf5cdf0349e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:04 +0300 Subject: clk: qcom: camcc-sc7180: get rid of the test clock The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-6-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sc7180.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index f6e303976a0d..3c15e551419f 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -29,7 +29,6 @@ enum { P_CAM_CC_PLL2_OUT_AUX, P_CAM_CC_PLL2_OUT_EARLY, P_CAM_CC_PLL3_OUT_MAIN, - P_CORE_BI_PLL_TEST_SE, }; static const struct pll_vco agera_vco[] = { @@ -187,26 +186,22 @@ static const struct parent_map cam_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll1.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_AUX, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll2_out_aux.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_2[] = { @@ -214,7 +209,6 @@ static const struct parent_map cam_cc_parent_map_2[] = { { P_CAM_CC_PLL2_OUT_EARLY, 4 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_2[] = { @@ -222,7 +216,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = { { .hw = &cam_cc_pll2_out_early.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_3[] = { @@ -231,7 +224,6 @@ static const struct parent_map cam_cc_parent_map_3[] = { { P_CAM_CC_PLL2_OUT_EARLY, 4 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_3[] = { @@ -240,33 +232,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = { { .hw = &cam_cc_pll2_out_early.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct parent_map cam_cc_parent_map_6[] = { @@ -274,7 +261,6 @@ static const struct parent_map cam_cc_parent_map_6[] = { { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL3_OUT_MAIN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data cam_cc_parent_data_6[] = { @@ -282,7 +268,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = { { .hw = &cam_cc_pll1.clkr.hw }, { .hw = &cam_cc_pll3.clkr.hw }, { .hw = &cam_cc_pll0.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { -- cgit v1.2.3 From f1697f36196e3aee1b7585610df494cef1a72393 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:05 +0300 Subject: clk: qcom: camcc-sc7180: use parent_hws instead of parent_data If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-7-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++++++-------------------- 1 file changed, 79 insertions(+), 77 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c index 3c15e551419f..e2b4804695f3 100644 --- a/drivers/clk/qcom/camcc-sc7180.c +++ b/drivers/clk/qcom/camcc-sc7180.c @@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_early", - .parent_names = (const char *[]){ "cam_cc_pll2" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_aux", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_pll2.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_bps_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cci_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_core_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_icp_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_ipe_0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_jpeg_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_lrme_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_lrme_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk0_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk1_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk2_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk3_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &cam_cc_mclk4_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- cgit v1.2.3 From cf4cd3dcb79a14c95474389cd6eb6fd8c18a121b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:06 +0300 Subject: clk: qcom: camcc-sdm845: use ARRAY_SIZE instead of specifying num_parents Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-8-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sdm845.c | 50 ++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index 1b2cefef7431..97024e466dcd 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -190,7 +190,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -213,7 +213,7 @@ static struct clk_rcg2 cam_cc_cci_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -233,7 +233,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -254,7 +254,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -269,7 +269,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -284,7 +284,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -299,7 +299,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -324,7 +324,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -347,7 +347,7 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -370,7 +370,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -394,7 +394,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -417,7 +417,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -431,7 +431,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -446,7 +446,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -460,7 +460,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -475,7 +475,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -500,7 +500,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -515,7 +515,7 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -530,7 +530,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -555,7 +555,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -578,7 +578,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -593,7 +593,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -608,7 +608,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -623,7 +623,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -647,7 +647,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .parent_names = cam_cc_parent_names_0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, -- cgit v1.2.3 From 6b7ef45f7aa9f7cedd46920fe91160265a83b486 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:07 +0300 Subject: clk: qcom: camcc-sdm845: get rid of the test clock The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-9-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sdm845.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index 97024e466dcd..6210b0fb7eac 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -23,7 +23,6 @@ enum { P_CAM_CC_PLL1_OUT_EVEN, P_CAM_CC_PLL2_OUT_EVEN, P_CAM_CC_PLL3_OUT_EVEN, - P_CORE_BI_PLL_TEST_SE, }; static const struct parent_map cam_cc_parent_map_0[] = { @@ -32,7 +31,6 @@ static const struct parent_map cam_cc_parent_map_0[] = { { P_CAM_CC_PLL1_OUT_EVEN, 2 }, { P_CAM_CC_PLL3_OUT_EVEN, 5 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const cam_cc_parent_names_0[] = { @@ -41,7 +39,6 @@ static const char * const cam_cc_parent_names_0[] = { "cam_cc_pll1_out_even", "cam_cc_pll3_out_even", "cam_cc_pll0_out_even", - "core_bi_pll_test_se", }; static struct clk_alpha_pll cam_cc_pll0 = { -- cgit v1.2.3 From b4e2d27ec748dd4591aaf39a894983138c92e2e2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:08 +0300 Subject: clk: qcom: camcc-sdm845: move clock parent tables down Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-10-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sdm845.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index 6210b0fb7eac..fd01ea53a07f 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -25,22 +25,6 @@ enum { P_CAM_CC_PLL3_OUT_EVEN, }; -static const struct parent_map cam_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL2_OUT_EVEN, 1 }, - { P_CAM_CC_PLL1_OUT_EVEN, 2 }, - { P_CAM_CC_PLL3_OUT_EVEN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, -}; - -static const char * const cam_cc_parent_names_0[] = { - "bi_tcxo", - "cam_cc_pll2_out_even", - "cam_cc_pll1_out_even", - "cam_cc_pll3_out_even", - "cam_cc_pll0_out_even", -}; - static struct clk_alpha_pll cam_cc_pll0 = { .offset = 0x0, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], @@ -159,6 +143,22 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { }, }; +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 1 }, + { P_CAM_CC_PLL1_OUT_EVEN, 2 }, + { P_CAM_CC_PLL3_OUT_EVEN, 5 }, + { P_CAM_CC_PLL0_OUT_EVEN, 6 }, +}; + +static const char * const cam_cc_parent_names_0[] = { + "bi_tcxo", + "cam_cc_pll2_out_even", + "cam_cc_pll1_out_even", + "cam_cc_pll3_out_even", + "cam_cc_pll0_out_even", +}; + static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), -- cgit v1.2.3 From 0cc3bd80610cc04642c8dd5cd1d54bd975229d02 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:09 +0300 Subject: clk: qcom: camcc-sdm845: convert to parent_hws/_data Convert the clock driver to specify parent hws/data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-11-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/camcc-sdm845.c | 300 +++++++++++++++++++++------------------- 1 file changed, 158 insertions(+), 142 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c index fd01ea53a07f..be3f95326965 100644 --- a/drivers/clk/qcom/camcc-sdm845.c +++ b/drivers/clk/qcom/camcc-sdm845.c @@ -31,7 +31,9 @@ static struct clk_alpha_pll cam_cc_pll0 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -53,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0_out_even", - .parent_names = (const char *[]){ "cam_cc_pll0" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -65,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -81,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1_out_even", - .parent_names = (const char *[]){ "cam_cc_pll1" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll1.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -93,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -109,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2_out_even", - .parent_names = (const char *[]){ "cam_cc_pll2" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll2.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -121,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3", - .parent_names = (const char *[]){ "bi_tcxo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", .name = "bi_tcxo", + }, .num_parents = 1, .ops = &clk_alpha_pll_fabia_ops, }, @@ -137,7 +151,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3_out_even", - .parent_names = (const char *[]){ "cam_cc_pll3" }, + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_pll3.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_fabia_ops, }, @@ -151,12 +167,12 @@ static const struct parent_map cam_cc_parent_map_0[] = { { P_CAM_CC_PLL0_OUT_EVEN, 6 }, }; -static const char * const cam_cc_parent_names_0[] = { - "bi_tcxo", - "cam_cc_pll2_out_even", - "cam_cc_pll1_out_even", - "cam_cc_pll3_out_even", - "cam_cc_pll0_out_even", +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, + { .hw = &cam_cc_pll2_out_even.clkr.hw }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, }; static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { @@ -186,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { .freq_tbl = ftbl_cam_cc_bps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -209,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = { .freq_tbl = ftbl_cam_cc_cci_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -229,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -250,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -265,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -280,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -295,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -320,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -343,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = { .freq_tbl = ftbl_cam_cc_fd_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -366,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { .freq_tbl = ftbl_cam_cc_icp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -390,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -413,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -427,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -442,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -456,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -471,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .ops = &clk_rcg2_shared_ops, }, }; @@ -496,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -511,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = { .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -526,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { .freq_tbl = ftbl_cam_cc_bps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -551,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { .freq_tbl = ftbl_cam_cc_lrme_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_shared_ops, }, @@ -574,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -589,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -604,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -619,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -643,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, @@ -658,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -676,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -707,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", - .parent_names = (const char *[]){ - "cam_cc_bps_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -751,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_clk", - .parent_names = (const char *[]){ - "cam_cc_cci_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cci_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -769,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -787,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi0phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -805,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi1phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -823,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi2phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -841,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi3phytimer_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -859,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -877,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -895,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -913,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -931,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_clk", - .parent_names = (const char *[]){ - "cam_cc_fd_core_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fd_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -949,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_fd_core_uar_clk", - .parent_names = (const char *[]){ - "cam_cc_fd_core_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fd_core_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -992,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", - .parent_names = (const char *[]){ - "cam_cc_icp_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1049,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1067,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1085,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_csid_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1103,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1133,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1151,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1169,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_csid_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1187,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -1204,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_lite_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1222,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1240,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_lite_csid_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1258,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1276,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1307,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_0_clk", - .parent_names = (const char *[]){ - "cam_cc_ipe_0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1325,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1343,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1374,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_1_clk", - .parent_names = (const char *[]){ - "cam_cc_ipe_1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_ipe_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1392,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", - .parent_names = (const char *[]){ - "cam_cc_jpeg_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1410,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_lrme_clk", - .parent_names = (const char *[]){ - "cam_cc_lrme_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_lrme_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1428,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk0_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1446,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk1_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1464,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk2_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1482,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk3_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- cgit v1.2.3 From 38d40dd3ed38e81dbab3c07d5edcb3ad740ca75a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:10 +0300 Subject: clk: qcom: videocc-sc7180: use parent_hws instead of parent_data If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-12-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/videocc-sc7180.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index ed57bbb19f88..5b9b54f616b8 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -99,8 +99,8 @@ static struct clk_branch video_cc_vcodec0_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_vcodec0_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_venus_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -143,8 +143,8 @@ static struct clk_branch video_cc_venus_ctl_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_cc_venus_ctl_core_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &video_cc_venus_clk_src.clkr.hw, + .parent_hws = (const struct clk_hw*[]){ + &video_cc_venus_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, -- cgit v1.2.3 From ed96df3d461eeb2c40cb06ca5fd51644d0f4a2c0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:11 +0300 Subject: clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-13-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++++++--------------------- 1 file changed, 61 insertions(+), 61 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 9b1674b28d45..d95814025c65 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -290,7 +290,7 @@ static struct clk_rcg2 system_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, - .num_parents = 7, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -310,7 +310,7 @@ static struct clk_rcg2 config_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "config_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -332,7 +332,7 @@ static struct clk_rcg2 periph_noc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "periph_noc_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -353,7 +353,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -371,7 +371,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -389,7 +389,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_names = gcc_xo_sleep_clk, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -408,7 +408,7 @@ static struct clk_rcg2 usb20_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_master_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -421,7 +421,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", .parent_names = gcc_xo_gpll0_gpll0_early_div, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -447,7 +447,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_floor_ops, }, }; @@ -467,7 +467,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -492,7 +492,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, }; @@ -506,7 +506,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc3_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, }; @@ -530,7 +530,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, }; @@ -555,7 +555,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -574,7 +574,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -634,7 +634,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -675,7 +675,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -716,7 +716,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -757,7 +757,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -798,7 +798,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -812,7 +812,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -839,7 +839,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -880,7 +880,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -921,7 +921,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -962,7 +962,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart4_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1003,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart5_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1044,7 +1044,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1058,7 +1058,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart6_apps_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1076,7 +1076,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1095,7 +1095,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", .parent_names = gcc_xo_gpll0_aud_ref_clk, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), .ops = &clk_rcg2_ops, }, }; @@ -1107,7 +1107,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sleep_clk_src", .parent_names = gcc_sleep_clk, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -1120,7 +1120,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1132,7 +1132,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1153,7 +1153,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1167,7 +1167,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1181,7 +1181,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1200,7 +1200,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_aux_clk_src", .parent_names = gcc_xo_sleep_clk, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -1221,7 +1221,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1241,7 +1241,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_clk_src", .parent_names = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1262,7 +1262,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; -- cgit v1.2.3 From b554a687b4971ae137e92ee3feddc38e85a38d60 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:12 +0300 Subject: clk: qcom: gcc-msm8996: drop unsupported clock sources In preparation of updating the msm8996 gcc driver, drop all unsupported GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3). Downstream kernel also does not provide support for these GPLL sources, so it is safe to drop them. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8996.c | 55 +++++------------------------------------- 1 file changed, 6 insertions(+), 49 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index d95814025c65..4c85b3935a81 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -27,15 +27,10 @@ enum { P_XO, P_GPLL0, - P_GPLL2, - P_GPLL3, - P_GPLL1, - P_GPLL2_EARLY, P_GPLL0_EARLY_DIV, P_SLEEP_CLK, P_GPLL4, P_AUD_REF_CLK, - P_GPLL1_EARLY_DIV }; static const struct parent_map gcc_sleep_clk_map[] = { @@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { "gpll0_early_div" }; -static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL1_EARLY_DIV, 3 }, - { P_GPLL1, 4 }, - { P_GPLL4, 5 }, - { P_GPLL0_EARLY_DIV, 6 } -}; - -static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll1_early_div", - "gpll1", - "gpll4", - "gpll0_early_div" -}; - -static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL2, 2 }, - { P_GPLL3, 3 }, - { P_GPLL1, 4 }, - { P_GPLL2_EARLY, 5 }, - { P_GPLL0_EARLY_DIV, 6 } -}; - -static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll2", - "gpll3", - "gpll1", - "gpll2_early", - "gpll0_early_div" -}; - static struct clk_fixed_factor xo = { .mult = 1, .div = 1, @@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = { static struct clk_rcg2 system_noc_clk_src = { .cmd_rcgr = 0x0401c, .hid_width = 5, - .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map, + .parent_map = gcc_xo_gpll0_gpll0_early_div_map, .freq_tbl = ftbl_system_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", - .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, - .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), + .parent_names = gcc_xo_gpll0_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; @@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { static struct clk_rcg2 qspi_ser_clk_src = { .cmd_rcgr = 0x8b00c, .hid_width = 5, - .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map, + .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map, .freq_tbl = ftbl_qspi_ser_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", - .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, - .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), + .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, }; -- cgit v1.2.3 From 1a2789cff03ccdeb70084157387f4a7bf4d2099f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:13 +0300 Subject: clk: qcom: gcc-msm8996: move clock parent tables down Move clock parent tables down, after the GPLL declrataions, so that we can use gpll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-15-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++++++--------------------- 1 file changed, 92 insertions(+), 92 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 4c85b3935a81..8531f2f3665f 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -33,98 +33,6 @@ enum { P_AUD_REF_CLK, }; -static const struct parent_map gcc_sleep_clk_map[] = { - { P_SLEEP_CLK, 5 } -}; - -static const char * const gcc_sleep_clk[] = { - "sleep_clk" -}; - -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 } -}; - -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0" -}; - -static const struct parent_map gcc_xo_sleep_clk_map[] = { - { P_XO, 0 }, - { P_SLEEP_CLK, 5 } -}; - -static const char * const gcc_xo_sleep_clk[] = { - "xo", - "sleep_clk" -}; - -static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL0_EARLY_DIV, 6 } -}; - -static const char * const gcc_xo_gpll0_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll0_early_div" -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 } -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0", - "gpll4" -}; - -static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_AUD_REF_CLK, 2 } -}; - -static const char * const gcc_xo_gpll0_aud_ref_clk[] = { - "xo", - "gpll0", - "aud_ref_clk" -}; - -static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_EARLY_DIV, 6 } -}; - -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { - "xo", - "gpll0", - "sleep_clk", - "gpll0_early_div" -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 }, - { P_GPLL0_EARLY_DIV, 6 } -}; - -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll4", - "gpll0_early_div" -}; - static struct clk_fixed_factor xo = { .mult = 1, .div = 1, @@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = { }, }; +static const struct parent_map gcc_sleep_clk_map[] = { + { P_SLEEP_CLK, 5 } +}; + +static const char * const gcc_sleep_clk[] = { + "sleep_clk" +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 } +}; + +static const char * const gcc_xo_gpll0[] = { + "xo", + "gpll0" +}; + +static const struct parent_map gcc_xo_sleep_clk_map[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 5 } +}; + +static const char * const gcc_xo_sleep_clk[] = { + "xo", + "sleep_clk" +}; + +static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_EARLY_DIV, 6 } +}; + +static const char * const gcc_xo_gpll0_gpll0_early_div[] = { + "xo", + "gpll0", + "gpll0_early_div" +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 } +}; + +static const char * const gcc_xo_gpll0_gpll4[] = { + "xo", + "gpll0", + "gpll4" +}; + +static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_AUD_REF_CLK, 2 } +}; + +static const char * const gcc_xo_gpll0_aud_ref_clk[] = { + "xo", + "gpll0", + "aud_ref_clk" +}; + +static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_EARLY_DIV, 6 } +}; + +static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { + "xo", + "gpll0", + "sleep_clk", + "gpll0_early_div" +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 }, + { P_GPLL0_EARLY_DIV, 6 } +}; + +static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { + "xo", + "gpll0", + "gpll4", + "gpll0_early_div" +}; + static const struct freq_tbl ftbl_system_noc_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), -- cgit v1.2.3 From b3867679d460d67aaef5aa76e4512197a5375514 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:14 +0300 Subject: clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-16-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++++++++------------- 1 file changed, 463 insertions(+), 215 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 8531f2f3665f..6b36024583b4 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = { .div = 1, .hw.init = &(struct clk_init_data){ .name = "xo", - .parent_names = (const char *[]){ "xo_board" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo", .name = "xo_board", + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_early", - .parent_names = (const char *[]){ "xo" }, + .parent_hws = (const struct clk_hw*[]){ + &xo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_early_div", - .parent_names = (const char *[]){ "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", - .parent_names = (const char *[]){ "gpll0_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_gpll0_div_clk", - .parent_names = (const char *[]){ "gpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_gpll0_div_clk", - .parent_names = (const char *[]){ "gpll0" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll0.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops @@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4_early", - .parent_names = (const char *[]){ "xo" }, + .parent_hws = (const struct clk_hw*[]){ + &xo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = { .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", - .parent_names = (const char *[]){ "gpll4_early" }, + .parent_hws = (const struct clk_hw*[]){ + &gpll4_early.clkr.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ops, }, @@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = { { P_SLEEP_CLK, 5 } }; -static const char * const gcc_sleep_clk[] = { - "sleep_clk" +static const struct clk_parent_data gcc_sleep_clk[] = { + { .fw_name = "sleep_clk", .name = "sleep_clk" } }; static const struct parent_map gcc_xo_gpll0_map[] = { @@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = { { P_GPLL0, 1 } }; -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0" +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw } }; static const struct parent_map gcc_xo_sleep_clk_map[] = { @@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = { { P_SLEEP_CLK, 5 } }; -static const char * const gcc_xo_sleep_clk[] = { - "xo", - "sleep_clk" +static const struct clk_parent_data gcc_xo_sleep_clk[] = { + { .hw = &xo.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" } }; static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { @@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { { P_GPLL0_EARLY_DIV, 6 } }; -static const char * const gcc_xo_gpll0_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll0_early_div" +static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_early_div.hw } }; static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { @@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { { P_GPLL4, 5 } }; -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0", - "gpll4" +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw } }; static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { @@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { { P_AUD_REF_CLK, 2 } }; -static const char * const gcc_xo_gpll0_aud_ref_clk[] = { - "xo", - "gpll0", - "aud_ref_clk" +static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" } }; static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { @@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { { P_GPLL0_EARLY_DIV, 6 } }; -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { - "xo", - "gpll0", - "sleep_clk", - "gpll0_early_div" +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, + { .hw = &gpll0_early_div.hw } }; static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { @@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { { P_GPLL0_EARLY_DIV, 6 } }; -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = { - "xo", - "gpll0", - "gpll4", - "gpll0_early_div" +static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { + { .hw = &xo.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0_early_div.hw } }; static const struct freq_tbl ftbl_system_noc_clk_src[] = { @@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = { .freq_tbl = ftbl_system_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "system_noc_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = { .freq_tbl = ftbl_config_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "config_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = { .freq_tbl = ftbl_periph_noc_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "periph_noc_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .freq_tbl = ftbl_usb30_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .freq_tbl = ftbl_usb3_phy_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_xo_sleep_clk, + .parent_data = gcc_xo_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, @@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = { .freq_tbl = ftbl_usb20_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_master_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .freq_tbl = ftbl_sdcc1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_floor_ops, }, @@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .freq_tbl = ftbl_sdcc1_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4, + .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, @@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc3_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll4, + .parent_data = gcc_xo_gpll0_gpll4, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), .ops = &clk_rcg2_floor_ops, }, @@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { .freq_tbl = ftbl_sdcc4_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_floor_ops, }, @@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = { .freq_tbl = ftbl_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { .freq_tbl = ftbl_tsif_ref_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk_src", - .parent_names = gcc_xo_gpll0_aud_ref_clk, + .parent_data = gcc_xo_gpll0_aud_ref_clk, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk), .ops = &clk_rcg2_ops, }, @@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = { .parent_map = gcc_sleep_clk_map, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_sleep_clk_src", - .parent_names = gcc_sleep_clk, + .parent_data = gcc_sleep_clk, .num_parents = ARRAY_SIZE(gcc_sleep_clk), .ops = &clk_rcg2_ops, }, @@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = { .freq_tbl = ftbl_usb30_mock_utmi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_rbcpr_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = { .parent_map = gcc_xo_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "hmss_gpll0_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div, + .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = { .freq_tbl = ftbl_pcie_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_aux_clk_src", - .parent_names = gcc_xo_sleep_clk, + .parent_data = gcc_xo_sleep_clk, .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk), .ops = &clk_rcg2_ops, }, @@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { .freq_tbl = ftbl_ufs_axi_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_axi_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = { .freq_tbl = ftbl_ufs_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_clk_src", - .parent_names = gcc_xo_gpll0, + .parent_data = gcc_xo_gpll0, .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, @@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = { .freq_tbl = ftbl_qspi_ser_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "qspi_ser_clk_src", - .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, + .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div, .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), .ops = &clk_rcg2_ops, }, @@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_axi_clk", - .parent_names = (const char *[]){ "usb30_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_ufs_axi_clk", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_periph_noc_usb20_ahb_clk", - .parent_names = (const char *[]){ "usb20_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb20_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mmss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .ops = &clk_branch2_ops, @@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ "usb30_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_mock_utmi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ "usb3_phy_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb3_phy_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_pipe_clk", - .parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_master_clk", - .parent_names = (const char *[]){ "usb20_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb20_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb20_mock_utmi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_phy_cfg_ahb2phy_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ "sdcc1_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc1_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc1_ice_core_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ "sdcc2_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc2_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_apps_clk", - .parent_names = (const char *[]){ "sdcc3_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc3_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc3_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_apps_clk", - .parent_names = (const char *[]){ "sdcc4_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdcc4_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc4_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = { .enable_mask = BIT(16), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart1_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup2_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart2_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup3_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart3_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart3_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup4_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart4_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart4_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup5_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup5_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart5_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart5_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_spi_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup6_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup6_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart6_apps_clk", - .parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp1_uart6_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_sleep_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup1_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup1_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart1_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup2_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup2_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart2_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup3_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup3_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart3_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart3_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup4_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart4_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart4_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup5_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup5_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup5_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart5_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart5_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_spi_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup6_spi_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup6_i2c_apps_clk", - .parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_qup6_i2c_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart6_apps_clk", - .parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &blsp2_uart6_apps_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ "pdm2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pdm2_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = { .enable_mask = BIT(13), .hw.init = &(struct clk_init_data){ .name = "gcc_prng_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_tsif_inactivity_timers_clk", - .parent_names = (const char *[]){ "gcc_sleep_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gcc_sleep_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "gcc_boot_rom_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hmss_rbcpr_clk", - .parent_names = (const char *[]){ "hmss_rbcpr_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &hmss_rbcpr_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ "gp1_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp1_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ "gp2_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp2_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ "gp3_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp3_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_slv_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_mstr_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_names = (const char *[]){ "pcie_0_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_slv_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_mstr_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk", - .parent_names = (const char *[]){ "pcie_1_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_slv_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_mstr_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_2_pipe_clk", - .parent_names = (const char *[]){ "pcie_2_pipe_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_aux_clk", - .parent_names = (const char *[]){ "pcie_aux_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_aux_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_axi_clk", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = { .div = 16, .hw.init = &(struct clk_init_data){ .name = "ufs_tx_cfg_clk_src", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, @@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_cfg_clk", - .parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_tx_cfg_clk_src.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = { .div = 16, .hw.init = &(struct clk_init_data){ .name = "ufs_rx_cfg_clk_src", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, @@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_cfg_clk", - .parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_rx_cfg_clk_src.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_tx_symbol_0_clk", - .parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_0_clk", - .parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_rx_symbol_1_clk", - .parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src", + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "ufs_ice_core_postdiv_clk_src", - .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_ice_core_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, @@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_unipro_core_clk", - .parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_ice_core_postdiv_clk_src.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_ice_core_clk", - .parent_names = (const char *[]){ "ufs_ice_core_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_ice_core_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre0_snoc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre0_cnoc_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_smmu_aggre0_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_smmu_aggre0_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, .ops = &clk_branch2_ops, @@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre2_ufs_axi_clk", - .parent_names = (const char *[]){ "ufs_axi_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &ufs_axi_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre2_usb3_axi_clk", - .parent_names = (const char *[]){ "usb30_master_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_dcc_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_ahb_clk", - .parent_names = (const char *[]){ "periph_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &periph_noc_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_qspi_ser_clk", - .parent_names = (const char *[]){ "qspi_ser_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &qspi_ser_clk_src.clkr.hw, + }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, @@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_cfg_ahb_clk", - .parent_names = (const char *[]){ "config_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &config_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_mnoc_bimc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_snoc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", - .parent_names = (const char *[]){ "system_noc_clk_src" }, + .parent_hws = (const struct clk_hw*[]){ + &system_noc_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch2_ops, }, -- cgit v1.2.3 From fb4701307ce7d4d651ce3bbc064485d04b5714aa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 28 Dec 2021 07:54:15 +0300 Subject: clk: qcom: gcc-msm8996: start getting rid of xo clk The "xo" fixed_factor clock is a leftover/hack from a time when we couldn't make rpmhcc the root of all clocks. It is going to be removed once all users of this clock are converted to use clocks specified through the DTS. Replace internal usage of the xo clock with the cxo (RPM_SMD_BB_CLK1) parent, specifying xo_board as a fallback. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211228045415.20543-17-dmitry.baryshkov@linaro.org --- drivers/clk/qcom/gcc-msm8996.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 6b36024583b4..e16163706735 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -54,8 +54,8 @@ static struct clk_alpha_pll gpll0_early = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_early", - .parent_hws = (const struct clk_hw*[]){ - &xo.hw, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo", .name = "xo_board", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -131,8 +131,8 @@ static struct clk_alpha_pll gpll4_early = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gpll4_early", - .parent_hws = (const struct clk_hw*[]){ - &xo.hw, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo", .name = "xo_board", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -167,7 +167,7 @@ static const struct parent_map gcc_xo_gpll0_map[] = { }; static const struct clk_parent_data gcc_xo_gpll0[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .hw = &gpll0.clkr.hw } }; @@ -177,7 +177,7 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = { }; static const struct clk_parent_data gcc_xo_sleep_clk[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .fw_name = "sleep_clk", .name = "sleep_clk" } }; @@ -188,7 +188,7 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = { }; static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll0_early_div.hw } }; @@ -200,7 +200,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { }; static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw } }; @@ -212,7 +212,7 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = { }; static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .hw = &gpll0.clkr.hw }, { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" } }; @@ -225,7 +225,7 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = { }; static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .hw = &gpll0.clkr.hw }, { .fw_name = "sleep_clk", .name = "sleep_clk" }, { .hw = &gpll0_early_div.hw } @@ -239,7 +239,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = { }; static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { - { .hw = &xo.hw }, + { .fw_name = "cxo", .name = "xo_board" }, { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &gpll0_early_div.hw } -- cgit v1.2.3 From e6db8c8be7ad3b4ed42e3b06564047e3a4c42345 Mon Sep 17 00:00:00 2001 From: Bartosz Dudziak Date: Mon, 7 Feb 2022 19:54:11 +0100 Subject: clk: qcom: Add MSM8226 Multimedia Clock Controller support Modify the existing MSM8974 multimedia clock controller driver to support the MMCC found on MSM8226 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Bartosz Dudziak Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220207185411.19118-3-bartosz.dudziak@snejp.pl --- drivers/clk/qcom/mmcc-msm8974.c | 206 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 201 insertions(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index a1552b6771bc..f74662925a58 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -257,6 +257,18 @@ static struct clk_rcg2 mmss_ahb_clk_src = { }, }; +static struct freq_tbl ftbl_mmss_axi_clk_msm8226[] = { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0, 16, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(75000000, P_GPLL0, 8, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(150000000, P_GPLL0, 4, 0, 0), + F(200000000, P_MMPLL0, 4, 0, 0), + F(266666666, P_MMPLL0, 3, 0, 0), + { } +}; + static struct freq_tbl ftbl_mmss_axi_clk[] = { F( 19200000, P_XO, 1, 0, 0), F( 37500000, P_GPLL0, 16, 0, 0), @@ -364,6 +376,23 @@ static struct clk_rcg2 csi3_clk_src = { }, }; +static struct freq_tbl ftbl_camss_vfe_vfe0_clk_msm8226[] = { + F(37500000, P_GPLL0, 16, 0, 0), + F(50000000, P_GPLL0, 12, 0, 0), + F(60000000, P_GPLL0, 10, 0, 0), + F(80000000, P_GPLL0, 7.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(109090000, P_GPLL0, 5.5, 0, 0), + F(133330000, P_GPLL0, 4.5, 0, 0), + F(150000000, P_GPLL0, 4, 0, 0), + F(200000000, P_GPLL0, 3, 0, 0), + F(228570000, P_MMPLL0, 3.5, 0, 0), + F(266670000, P_MMPLL0, 3, 0, 0), + F(320000000, P_MMPLL0, 2.5, 0, 0), + F(400000000, P_MMPLL0, 2, 0, 0), + { } +}; + static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { F(37500000, P_GPLL0, 16, 0, 0), F(50000000, P_GPLL0, 12, 0, 0), @@ -407,6 +436,18 @@ static struct clk_rcg2 vfe1_clk_src = { }, }; +static struct freq_tbl ftbl_mdss_mdp_clk_msm8226[] = { + F(37500000, P_GPLL0, 16, 0, 0), + F(60000000, P_GPLL0, 10, 0, 0), + F(75000000, P_GPLL0, 8, 0, 0), + F(92310000, P_GPLL0, 6.5, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(133330000, P_MMPLL0, 6, 0, 0), + F(177780000, P_MMPLL0, 4.5, 0, 0), + F(200000000, P_MMPLL0, 4, 0, 0), + { } +}; + static struct freq_tbl ftbl_mdss_mdp_clk[] = { F(37500000, P_GPLL0, 16, 0, 0), F(60000000, P_GPLL0, 10, 0, 0), @@ -513,6 +554,14 @@ static struct clk_rcg2 pclk1_clk_src = { }, }; +static struct freq_tbl ftbl_venus0_vcodec0_clk_msm8226[] = { + F(66700000, P_GPLL0, 9, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + F(133330000, P_MMPLL0, 6, 0, 0), + F(160000000, P_MMPLL0, 5, 0, 0), + { } +}; + static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { F(50000000, P_GPLL0, 12, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), @@ -593,6 +642,13 @@ static struct clk_rcg2 camss_gp1_clk_src = { }, }; +static struct freq_tbl ftbl_camss_mclk0_3_clk_msm8226[] = { + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0, 5, 1, 5), + F(66670000, P_GPLL0, 9, 0, 0), + { } +}; + static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { F(4800000, P_XO, 4, 0, 0), F(6000000, P_GPLL0, 10, 1, 10), @@ -705,6 +761,15 @@ static struct clk_rcg2 csi2phytimer_clk_src = { }, }; +static struct freq_tbl ftbl_camss_vfe_cpp_clk_msm8226[] = { + F(133330000, P_GPLL0, 4.5, 0, 0), + F(150000000, P_GPLL0, 4, 0, 0), + F(266670000, P_MMPLL0, 3, 0, 0), + F(320000000, P_MMPLL0, 2.5, 0, 0), + F(400000000, P_MMPLL0, 2, 0, 0), + { } +}; + static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { F(133330000, P_GPLL0, 4.5, 0, 0), F(266670000, P_MMPLL0, 3, 0, 0), @@ -2366,6 +2431,116 @@ static struct gdsc oxilicx_gdsc = { .pwrsts = PWRSTS_OFF_ON, }; +static struct clk_regmap *mmcc_msm8226_clocks[] = { + [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, + [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, + [MMPLL0] = &mmpll0.clkr, + [MMPLL0_VOTE] = &mmpll0_vote, + [MMPLL1] = &mmpll1.clkr, + [MMPLL1_VOTE] = &mmpll1_vote, + [CSI0_CLK_SRC] = &csi0_clk_src.clkr, + [CSI1_CLK_SRC] = &csi1_clk_src.clkr, + [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, + [MDP_CLK_SRC] = &mdp_clk_src.clkr, + [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, + [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, + [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, + [CCI_CLK_SRC] = &cci_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, + [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, + [CPP_CLK_SRC] = &cpp_clk_src.clkr, + [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, + [ESC0_CLK_SRC] = &esc0_clk_src.clkr, + [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, + [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, + [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, + [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, + [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, + [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, + [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, + [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, + [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, + [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, + [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, + [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, + [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, + [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, + [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, + [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, + [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, + [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, + [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, + [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, + [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, + [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, + [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, + [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, + [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, + [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, + [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, + [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, + [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, + [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, + [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, + [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, + [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, + [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, + [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, + [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, + [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, + [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, + [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, + [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, + [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, + [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, + [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, + [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, + [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, + [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, + [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, + [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, + [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr, + [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, + [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, + [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, +}; + +static const struct qcom_reset_map mmcc_msm8226_resets[] = { + [SPDM_RESET] = { 0x0200 }, + [SPDM_RM_RESET] = { 0x0300 }, + [VENUS0_RESET] = { 0x1020 }, + [MDSS_RESET] = { 0x2300 }, +}; + +static struct gdsc *mmcc_msm8226_gdscs[] = { + [VENUS0_GDSC] = &venus0_gdsc, + [MDSS_GDSC] = &mdss_gdsc, + [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, + [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, +}; + +static const struct regmap_config mmcc_msm8226_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5104, + .fast_io = true, +}; + +static const struct qcom_cc_desc mmcc_msm8226_desc = { + .config = &mmcc_msm8226_regmap_config, + .clks = mmcc_msm8226_clocks, + .num_clks = ARRAY_SIZE(mmcc_msm8226_clocks), + .resets = mmcc_msm8226_resets, + .num_resets = ARRAY_SIZE(mmcc_msm8226_resets), + .gdscs = mmcc_msm8226_gdscs, + .num_gdscs = ARRAY_SIZE(mmcc_msm8226_gdscs), +}; + static struct clk_regmap *mmcc_msm8974_clocks[] = { [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, @@ -2569,23 +2744,44 @@ static const struct qcom_cc_desc mmcc_msm8974_desc = { }; static const struct of_device_id mmcc_msm8974_match_table[] = { - { .compatible = "qcom,mmcc-msm8974" }, + { .compatible = "qcom,mmcc-msm8226", .data = &mmcc_msm8226_desc }, + { .compatible = "qcom,mmcc-msm8974", .data = &mmcc_msm8974_desc }, { } }; MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); +static void msm8226_clock_override(void) +{ + mmss_axi_clk_src.freq_tbl = ftbl_mmss_axi_clk_msm8226; + vfe0_clk_src.freq_tbl = ftbl_camss_vfe_vfe0_clk_msm8226; + mdp_clk_src.freq_tbl = ftbl_mdss_mdp_clk_msm8226; + vcodec0_clk_src.freq_tbl = ftbl_venus0_vcodec0_clk_msm8226; + mclk0_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226; + mclk1_clk_src.freq_tbl = ftbl_camss_mclk0_3_clk_msm8226; + cpp_clk_src.freq_tbl = ftbl_camss_vfe_cpp_clk_msm8226; +} + static int mmcc_msm8974_probe(struct platform_device *pdev) { struct regmap *regmap; + const struct qcom_cc_desc *desc; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; - regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc); + regmap = qcom_cc_map(pdev, desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); - clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); - clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); + if (desc == &mmcc_msm8974_desc) { + clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); + clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); + } else { + msm8226_clock_override(); + } - return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); + return qcom_cc_really_probe(pdev, desc, regmap); } static struct platform_driver mmcc_msm8974_driver = { -- cgit v1.2.3 From 2403d6f1b1dac1b7864cd8b9b4a0f7350c63e770 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:04 +0800 Subject: clk: mediatek: Use %pe to print errors If %pe is used to print errors, a string representation of the error would be printed instead of a number as with %ld. Also, all the sites printing errors are deriving the error code from a pointer. Using %pe is more straightforward. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-2-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-apmixed.c | 2 +- drivers/clk/mediatek/clk-cpumux.c | 6 ++---- drivers/clk/mediatek/clk-mtk.c | 18 ++++++------------ drivers/clk/mediatek/clk-mux.c | 6 ++---- drivers/clk/mediatek/clk-pll.c | 3 +-- drivers/clk/mediatek/reset.c | 3 +-- 6 files changed, 13 insertions(+), 25 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-apmixed.c b/drivers/clk/mediatek/clk-apmixed.c index caa9119413f1..a29339cc26c4 100644 --- a/drivers/clk/mediatek/clk-apmixed.c +++ b/drivers/clk/mediatek/clk-apmixed.c @@ -92,7 +92,7 @@ struct clk * __init mtk_clk_register_ref2usb_tx(const char *name, clk = clk_register(NULL, &tx->hw); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", name, clk); kfree(tx); } diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index e188018bc906..cab5095416b6 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -87,8 +87,7 @@ int mtk_clk_register_cpumuxes(struct device_node *node, regmap = device_node_to_regmap(node); if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %ld\n", node, - PTR_ERR(regmap)); + pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); return PTR_ERR(regmap); } @@ -97,8 +96,7 @@ int mtk_clk_register_cpumuxes(struct device_node *node, clk = mtk_clk_register_cpumux(mux, regmap); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - mux->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", mux->name, clk); continue; } diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 8d5791b3f460..519a461cbb6f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -70,8 +70,7 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, rc->rate); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - rc->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", rc->name, clk); continue; } @@ -97,8 +96,7 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, CLK_SET_RATE_PARENT, ff->mult, ff->div); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - ff->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", ff->name, clk); continue; } @@ -122,8 +120,7 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, regmap = device_node_to_regmap(node); if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %ld\n", node, - PTR_ERR(regmap)); + pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); return PTR_ERR(regmap); } @@ -141,8 +138,7 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, gate->shift, gate->ops, gate->flags, dev); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - gate->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", gate->name, clk); continue; } @@ -264,8 +260,7 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs, clk = mtk_clk_register_composite(mc, base, lock); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - mc->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", mc->name, clk); continue; } @@ -293,8 +288,7 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, mcd->div_width, mcd->clk_divider_flags, lock); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - mcd->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", mcd->name, clk); continue; } diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 6d3a50eb7d6f..89f23e111d91 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -175,8 +175,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, regmap = device_node_to_regmap(node); if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %ld\n", node, - PTR_ERR(regmap)); + pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); return PTR_ERR(regmap); } @@ -187,8 +186,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, clk = mtk_clk_register_mux(mux, regmap, lock); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - mux->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", mux->name, clk); continue; } diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 60d7ffa0b924..f04f724e12e5 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -378,8 +378,7 @@ void mtk_clk_register_plls(struct device_node *node, clk = mtk_clk_register_pll(pll, base); if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %ld\n", - pll->name, PTR_ERR(clk)); + pr_err("Failed to register clk %s: %pe\n", pll->name, clk); continue; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index ffe464ce7ff8..bcec4b89f449 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -100,8 +100,7 @@ static void mtk_register_reset_controller_common(struct device_node *np, regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %ld\n", np, - PTR_ERR(regmap)); + pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); return; } -- cgit v1.2.3 From 19b8d43887f52e65c38fb828c0976656b6302337 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:05 +0800 Subject: clk: mediatek: gate: Consolidate gate type clk related code Right now some bits of the gate type clk code are in clk-gate.[ch], but other bits are in clk-mtk.[ch]. This is different from the cpumux and mux type clks, for which all of the code are found in the same files. Move the functions that register multiple clks from a given list, mtk_clk_register_gates_with_dev() and mtk_clk_register_gates(), to clk-gate.[ch] to consolidate all the code for the gate type clks. This commit only moves code with minor whitespace fixups to correct the code style. Further improvements, such as internalizing various functions and structures will be done in later commits. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-3-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-gate.c | 53 ++++++++++++++++++++++++++++++++++++++++- drivers/clk/mediatek/clk-gate.h | 25 +++++++++++++++++++ drivers/clk/mediatek/clk-mtk.c | 51 --------------------------------------- drivers/clk/mediatek/clk-mtk.h | 25 ------------------- 4 files changed, 77 insertions(+), 77 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 5d88b428565b..54921768bfba 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -11,9 +11,9 @@ #include #include #include +#include #include -#include "clk-mtk.h" #include "clk-gate.h" static u32 mtk_get_clockgating(struct clk_hw *hw) @@ -182,4 +182,55 @@ struct clk *mtk_clk_register_gate( } EXPORT_SYMBOL_GPL(mtk_clk_register_gate); +int mtk_clk_register_gates_with_dev(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data, + struct device *dev) +{ + int i; + struct clk *clk; + struct regmap *regmap; + + if (!clk_data) + return -ENOMEM; + + regmap = device_node_to_regmap(node); + if (IS_ERR(regmap)) { + pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); + return PTR_ERR(regmap); + } + + for (i = 0; i < num; i++) { + const struct mtk_gate *gate = &clks[i]; + + if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) + continue; + + clk = mtk_clk_register_gate(gate->name, gate->parent_name, + regmap, + gate->regs->set_ofs, + gate->regs->clr_ofs, + gate->regs->sta_ofs, + gate->shift, gate->ops, + gate->flags, dev); + + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %pe\n", gate->name, clk); + continue; + } + + clk_data->clks[gate->id] = clk; + } + + return 0; +} + +int mtk_clk_register_gates(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data) +{ + return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); +} +EXPORT_SYMBOL_GPL(mtk_clk_register_gates); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index 3c3329ec54b7..432b571d23b3 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -43,6 +43,22 @@ struct clk *mtk_clk_register_gate( unsigned long flags, struct device *dev); +struct mtk_gate_regs { + u32 sta_ofs; + u32 clr_ofs; + u32 set_ofs; +}; + +struct mtk_gate { + int id; + const char *name; + const char *parent_name; + const struct mtk_gate_regs *regs; + int shift; + const struct clk_ops *ops; + unsigned long flags; +}; + #define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ _ops, _flags) { \ .id = _id, \ @@ -57,4 +73,13 @@ struct clk *mtk_clk_register_gate( #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0) +int mtk_clk_register_gates(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data); + +int mtk_clk_register_gates_with_dev(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data, + struct device *dev); + #endif /* __DRV_CLK_GATE_H */ diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 519a461cbb6f..0c5db3c71fdd 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -106,57 +106,6 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, } EXPORT_SYMBOL_GPL(mtk_clk_register_factors); -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, - int num, struct clk_onecell_data *clk_data, - struct device *dev) -{ - int i; - struct clk *clk; - struct regmap *regmap; - - if (!clk_data) - return -ENOMEM; - - regmap = device_node_to_regmap(node); - if (IS_ERR(regmap)) { - pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); - return PTR_ERR(regmap); - } - - for (i = 0; i < num; i++) { - const struct mtk_gate *gate = &clks[i]; - - if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) - continue; - - clk = mtk_clk_register_gate(gate->name, gate->parent_name, - regmap, - gate->regs->set_ofs, - gate->regs->clr_ofs, - gate->regs->sta_ofs, - gate->shift, gate->ops, gate->flags, dev); - - if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %pe\n", gate->name, clk); - continue; - } - - clk_data->clks[gate->id] = clk; - } - - return 0; -} - -int mtk_clk_register_gates(struct device_node *node, - const struct mtk_gate *clks, - int num, struct clk_onecell_data *clk_data) -{ - return mtk_clk_register_gates_with_dev(node, - clks, num, clk_data, NULL); -} -EXPORT_SYMBOL_GPL(mtk_clk_register_gates); - struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 0ff289d93452..bdec7dc5e07a 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -150,31 +150,6 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); -struct mtk_gate_regs { - u32 sta_ofs; - u32 clr_ofs; - u32 set_ofs; -}; - -struct mtk_gate { - int id; - const char *name; - const char *parent_name; - const struct mtk_gate_regs *regs; - int shift; - const struct clk_ops *ops; - unsigned long flags; -}; - -int mtk_clk_register_gates(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_onecell_data *clk_data); - -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, - int num, struct clk_onecell_data *clk_data, - struct device *dev); - struct mtk_clk_divider { int id; const char *name; -- cgit v1.2.3 From ee488dc918bcb1140ad1ebb4459c702c9b53444b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:06 +0800 Subject: clk: mediatek: gate: Internalize clk implementation struct mtk_clk_gate and mtk_clk_register_gate() are not used outside of the gate clk library. Only the API that handles a list of clks is used by the individual platform clk drivers. Internalize the parts that aren't used outside of the implementation. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-4-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-gate.c | 35 +++++++++++++++++++++++------------ drivers/clk/mediatek/clk-gate.h | 31 ++----------------------------- 2 files changed, 25 insertions(+), 41 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 54921768bfba..e51cfd8c653c 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -11,11 +11,28 @@ #include #include #include +#include +#include #include #include +#include #include "clk-gate.h" +struct mtk_clk_gate { + struct clk_hw hw; + struct regmap *regmap; + int set_ofs; + int clr_ofs; + int sta_ofs; + u8 bit; +}; + +static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw) +{ + return container_of(hw, struct mtk_clk_gate, hw); +} + static u32 mtk_get_clockgating(struct clk_hw *hw) { struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); @@ -140,17 +157,12 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = { }; EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); -struct clk *mtk_clk_register_gate( - const char *name, - const char *parent_name, - struct regmap *regmap, - int set_ofs, - int clr_ofs, - int sta_ofs, - u8 bit, - const struct clk_ops *ops, - unsigned long flags, - struct device *dev) +static struct clk *mtk_clk_register_gate(const char *name, + const char *parent_name, + struct regmap *regmap, int set_ofs, + int clr_ofs, int sta_ofs, u8 bit, + const struct clk_ops *ops, + unsigned long flags, struct device *dev) { struct mtk_clk_gate *cg; struct clk *clk; @@ -180,7 +192,6 @@ struct clk *mtk_clk_register_gate( return clk; } -EXPORT_SYMBOL_GPL(mtk_clk_register_gate); int mtk_clk_register_gates_with_dev(struct device_node *node, const struct mtk_gate *clks, int num, diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index 432b571d23b3..3d75521ba20c 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -7,42 +7,15 @@ #ifndef __DRV_CLK_GATE_H #define __DRV_CLK_GATE_H -#include #include - -struct clk; - -struct mtk_clk_gate { - struct clk_hw hw; - struct regmap *regmap; - int set_ofs; - int clr_ofs; - int sta_ofs; - u8 bit; -}; - -static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw) -{ - return container_of(hw, struct mtk_clk_gate, hw); -} +#include +#include extern const struct clk_ops mtk_clk_gate_ops_setclr; extern const struct clk_ops mtk_clk_gate_ops_setclr_inv; extern const struct clk_ops mtk_clk_gate_ops_no_setclr; extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv; -struct clk *mtk_clk_register_gate( - const char *name, - const char *parent_name, - struct regmap *regmap, - int set_ofs, - int clr_ofs, - int sta_ofs, - u8 bit, - const struct clk_ops *ops, - unsigned long flags, - struct device *dev); - struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; -- cgit v1.2.3 From 44dd1414cf76d3e9f4073a3f9ff9b116dc9e79e9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:07 +0800 Subject: clk: mediatek: gate: Implement unregister API The gate clk type within the MediaTek clk driver library only has a register function, and no corresponding unregister function. This means there is no way for its users to properly implement cleanup and removal. Add a matching unregister function for the gate type clk. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-5-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-gate.c | 35 +++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-gate.h | 3 +++ 2 files changed, 38 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index e51cfd8c653c..ed1ad5535d41 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -193,6 +193,21 @@ static struct clk *mtk_clk_register_gate(const char *name, return clk; } +static void mtk_clk_unregister_gate(struct clk *clk) +{ + struct mtk_clk_gate *cg; + struct clk_hw *hw; + + hw = __clk_get_hw(clk); + if (!hw) + return; + + cg = to_mtk_clk_gate(hw); + + clk_unregister(clk); + kfree(cg); +} + int mtk_clk_register_gates_with_dev(struct device_node *node, const struct mtk_gate *clks, int num, struct clk_onecell_data *clk_data, @@ -244,4 +259,24 @@ int mtk_clk_register_gates(struct device_node *node, } EXPORT_SYMBOL_GPL(mtk_clk_register_gates); +void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + if (!clk_data) + return; + + for (i = num; i > 0; i--) { + const struct mtk_gate *gate = &clks[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[gate->id])) + continue; + + mtk_clk_unregister_gate(clk_data->clks[gate->id]); + clk_data->clks[gate->id] = ERR_PTR(-ENOENT); + } +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index 3d75521ba20c..344adffb6578 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -55,4 +55,7 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, struct clk_onecell_data *clk_data, struct device *dev); +void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, + struct clk_onecell_data *clk_data); + #endif /* __DRV_CLK_GATE_H */ -- cgit v1.2.3 From 625afe4f05e111b883b95d1b345fd21c94e64cfa Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:08 +0800 Subject: clk: mediatek: gate: Clean up included headers Some included headers aren't actually used anywhere, while other headers with the declaration of functions and structures aren't directly included. Get rid of the unused ones, and add the ones that should be included directly. On the header side, replace headers that are included purely for data structure definitions with forward declarations. This decreases the amount of preprocessing and compilation effort required for each inclusion. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-6-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-gate.c | 11 +++-------- drivers/clk/mediatek/clk-gate.h | 10 +++++++--- 2 files changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index ed1ad5535d41..e8881ae1489a 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -4,18 +4,13 @@ * Author: James Liao */ -#include -#include - -#include -#include -#include -#include #include -#include #include #include +#include #include +#include +#include #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index 344adffb6578..6b5738826a22 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -7,9 +7,13 @@ #ifndef __DRV_CLK_GATE_H #define __DRV_CLK_GATE_H -#include -#include -#include +#include + +struct clk; +struct clk_onecell_data; +struct clk_ops; +struct device; +struct device_node; extern const struct clk_ops mtk_clk_gate_ops_setclr; extern const struct clk_ops mtk_clk_gate_ops_setclr_inv; -- cgit v1.2.3 From 89ceb2064ecba333bcf206dc15e4e057d04e132d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:09 +0800 Subject: clk: mediatek: cpumux: Implement unregister API The cpumux clk type within the MediaTek clk driver library only has a register function, and no corresponding unregister function. This means there is no way for its users to properly implement cleanup and removal. Add a matching unregister function for the cpumux type clk. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-7-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-cpumux.c | 31 +++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-cpumux.h | 3 +++ 2 files changed, 34 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index cab5095416b6..99a819e3673f 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -77,6 +77,21 @@ mtk_clk_register_cpumux(const struct mtk_composite *mux, return clk; } +static void mtk_clk_unregister_cpumux(struct clk *clk) +{ + struct mtk_clk_cpumux *cpumux; + struct clk_hw *hw; + + hw = __clk_get_hw(clk); + if (!hw) + return; + + cpumux = to_mtk_clk_cpumux(hw); + + clk_unregister(clk); + kfree(cpumux); +} + int mtk_clk_register_cpumuxes(struct device_node *node, const struct mtk_composite *clks, int num, struct clk_onecell_data *clk_data) @@ -106,4 +121,20 @@ int mtk_clk_register_cpumuxes(struct device_node *node, return 0; } +void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + for (i = num; i > 0; i--) { + const struct mtk_composite *mux = &clks[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) + continue; + + mtk_clk_unregister_cpumux(clk_data->clks[mux->id]); + clk_data->clks[mux->id] = ERR_PTR(-ENOENT); + } +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h index 2aaf1afd4e5f..fda7770fd803 100644 --- a/drivers/clk/mediatek/clk-cpumux.h +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -19,4 +19,7 @@ int mtk_clk_register_cpumuxes(struct device_node *node, const struct mtk_composite *clks, int num, struct clk_onecell_data *clk_data); +void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num, + struct clk_onecell_data *clk_data); + #endif /* __DRV_CLK_CPUMUX_H */ -- cgit v1.2.3 From 759284426a22a1f66a175b56e6b79fa663b8f7d4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:10 +0800 Subject: clk: mediatek: cpumux: Internalize struct mtk_clk_cpumux struct mtk_clk_cpumux is an implementation detail of the cpumux clk type, and is not used outside of the implementation. Internalize the definition to minimize leakage of details and shrink the header file. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-8-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-cpumux.c | 8 ++++++++ drivers/clk/mediatek/clk-cpumux.h | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index 99a819e3673f..344c6399b22f 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -12,6 +12,14 @@ #include "clk-mtk.h" #include "clk-cpumux.h" +struct mtk_clk_cpumux { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 mask; + u8 shift; +}; + static inline struct mtk_clk_cpumux *to_mtk_clk_cpumux(struct clk_hw *_hw) { return container_of(_hw, struct mtk_clk_cpumux, hw); diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h index fda7770fd803..a538f2bbef0d 100644 --- a/drivers/clk/mediatek/clk-cpumux.h +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -7,14 +7,6 @@ #ifndef __DRV_CLK_CPUMUX_H #define __DRV_CLK_CPUMUX_H -struct mtk_clk_cpumux { - struct clk_hw hw; - struct regmap *regmap; - u32 reg; - u32 mask; - u8 shift; -}; - int mtk_clk_register_cpumuxes(struct device_node *node, const struct mtk_composite *clks, int num, struct clk_onecell_data *clk_data); -- cgit v1.2.3 From 02f0d762319c22dd7f97d9dd491d651189332279 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:11 +0800 Subject: clk: mediatek: cpumux: Clean up included headers Some headers with the declaration of functions and structures aren't directly included. Explicitly include them so that future changes to other headers would not result in an unexpected build break. On the header side, add forward declarations for any data structures whose pointers are used in function signatures. No headers are required. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-9-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-cpumux.c | 3 +++ drivers/clk/mediatek/clk-cpumux.h | 4 ++++ 2 files changed, 7 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index 344c6399b22f..658aee789f44 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -5,8 +5,11 @@ */ #include +#include +#include #include #include +#include #include #include "clk-mtk.h" diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h index a538f2bbef0d..b07e89f7c283 100644 --- a/drivers/clk/mediatek/clk-cpumux.h +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -7,6 +7,10 @@ #ifndef __DRV_CLK_CPUMUX_H #define __DRV_CLK_CPUMUX_H +struct clk_onecell_data; +struct device_node; +struct mtk_composite; + int mtk_clk_register_cpumuxes(struct device_node *node, const struct mtk_composite *clks, int num, struct clk_onecell_data *clk_data); -- cgit v1.2.3 From 0b4b0387ddf6ab2b29d16147973fcf12ba0a0441 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:12 +0800 Subject: clk: mediatek: mux: Implement unregister API The mux clk type within the MediaTek clk driver library only has a register function, and no corresponding unregister function. This means there is no way for its users to properly implement cleanup and removal. Add a matching unregister function for the mux type clk. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-10-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mux.c | 35 +++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 3 +++ 2 files changed, 38 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 89f23e111d91..6f0c22a699c3 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -164,6 +164,21 @@ static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux, return clk; } +static void mtk_clk_unregister_mux(struct clk *clk) +{ + struct mtk_clk_mux *mux; + struct clk_hw *hw; + + hw = __clk_get_hw(clk); + if (!hw) + return; + + mux = to_mtk_clk_mux(hw); + + clk_unregister(clk); + kfree(mux); +} + int mtk_clk_register_muxes(const struct mtk_mux *muxes, int num, struct device_node *node, spinlock_t *lock, @@ -198,4 +213,24 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, } EXPORT_SYMBOL_GPL(mtk_clk_register_muxes); +void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + if (!clk_data) + return; + + for (i = num; i > 0; i--) { + const struct mtk_mux *mux = &muxes[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) + continue; + + mtk_clk_unregister_mux(clk_data->clks[mux->id]); + clk_data->clks[mux->id] = ERR_PTR(-ENOENT); + } +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 27841d649118..cb2ac4f04c58 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -88,4 +88,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, spinlock_t *lock, struct clk_onecell_data *clk_data); +void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, + struct clk_onecell_data *clk_data); + #endif /* __DRV_CLK_MTK_MUX_H */ -- cgit v1.2.3 From 7b375737e47eaf6c715a3cf1d6d7089b4d295b0d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:13 +0800 Subject: clk: mediatek: mux: Internalize struct mtk_clk_mux struct mtk_clk_mux is an implementation detail of the mux clk type, and is not used outside of the implementation. Internalize the definition to minimize leakage of details and shrink the header file. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-11-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mux.c | 8 ++++++++ drivers/clk/mediatek/clk-mux.h | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 6f0c22a699c3..2d4d8dc0120a 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -13,6 +13,14 @@ #include "clk-mtk.h" #include "clk-mux.h" +struct mtk_clk_mux { + struct clk_hw hw; + struct regmap *regmap; + const struct mtk_mux *data; + spinlock_t *lock; + bool reparent; +}; + static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw) { return container_of(hw, struct mtk_clk_mux, hw); diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index cb2ac4f04c58..38a2b6014b08 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -9,14 +9,6 @@ #include -struct mtk_clk_mux { - struct clk_hw hw; - struct regmap *regmap; - const struct mtk_mux *data; - spinlock_t *lock; - bool reparent; -}; - struct mtk_mux { int id; const char *name; -- cgit v1.2.3 From dc46de49264e3b57f3b64927512bcd49a2c745ad Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:14 +0800 Subject: clk: mediatek: mux: Clean up included headers Some included headers aren't actually used anywhere, while other headers with the declaration of functions and structures aren't directly included. Get rid of the unused ones, and add the ones that should be included directly. On the header side, replace headers that are included purely for data structure definitions with forward declarations. This decreases the amount of preprocessing and compilation effort required for each inclusion. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-12-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mux.c | 11 +++++++---- drivers/clk/mediatek/clk-mux.h | 8 +++++++- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 2d4d8dc0120a..01af6a52711a 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -4,13 +4,16 @@ * Author: Owen Chen */ -#include -#include -#include +#include +#include +#include +#include #include #include +#include +#include +#include -#include "clk-mtk.h" #include "clk-mux.h" struct mtk_clk_mux { diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 38a2b6014b08..903a3c937959 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -7,7 +7,13 @@ #ifndef __DRV_CLK_MTK_MUX_H #define __DRV_CLK_MTK_MUX_H -#include +#include +#include + +struct clk; +struct clk_onecell_data; +struct clk_ops; +struct device_node; struct mtk_mux { int id; -- cgit v1.2.3 From 39691fb67b6a4f09f839650b09f3eb33fd7d4d91 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:15 +0800 Subject: clk: mediatek: pll: Split definitions into separate header file When the PLL type clk was implemented in the MediaTek clk driver library, the data structure definitions and function declaration were put in the common header file. Since it is its own type of clk, and not all platform clk drivers utilize it, having the definitions in the common header results in wasted cycles during compilation. Split out the related definitions and declarations into its own header file, and include that only in the platform clk drivers that need it. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-13-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt2701.c | 5 ++- drivers/clk/mediatek/clk-mt2712.c | 3 +- drivers/clk/mediatek/clk-mt6765.c | 3 +- drivers/clk/mediatek/clk-mt6779.c | 3 +- drivers/clk/mediatek/clk-mt6797.c | 3 +- drivers/clk/mediatek/clk-mt7622.c | 5 ++- drivers/clk/mediatek/clk-mt7629.c | 5 ++- drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +- drivers/clk/mediatek/clk-mt8135.c | 3 +- drivers/clk/mediatek/clk-mt8167.c | 3 +- drivers/clk/mediatek/clk-mt8173.c | 5 ++- drivers/clk/mediatek/clk-mt8183.c | 3 +- drivers/clk/mediatek/clk-mt8192.c | 3 +- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 1 + drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 1 + drivers/clk/mediatek/clk-mt8516.c | 3 +- drivers/clk/mediatek/clk-mtk.h | 39 -------------------- drivers/clk/mediatek/clk-pll.c | 1 + drivers/clk/mediatek/clk-pll.h | 55 ++++++++++++++++++++++++++++ 19 files changed, 91 insertions(+), 57 deletions(-) create mode 100644 drivers/clk/mediatek/clk-pll.h (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 695be0f77427..1eb3e4563c3f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -10,9 +10,10 @@ #include #include -#include "clk-mtk.h" -#include "clk-gate.h" #include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index a3bd9a107209..ff72b9ab945b 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -13,8 +13,9 @@ #include #include -#include "clk-mtk.h" #include "clk-gate.h" +#include "clk-pll.h" +#include "clk-mtk.h" #include diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c index d77ea5aff292..24829ca3bd1f 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -12,9 +12,10 @@ #include #include -#include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mtk.h" #include "clk-mux.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9825385c9f94..7b61664da18f 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -10,9 +10,10 @@ #include #include +#include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-gate.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index 428eb24ffec5..02259e81625a 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -9,8 +9,9 @@ #include #include -#include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index ef5947e15c75..0e1fb30a1e98 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -11,9 +11,10 @@ #include #include -#include "clk-mtk.h" -#include "clk-gate.h" #include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include #include /* for consumer */ diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index a0ee079670c7..c0e023bf31eb 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -12,9 +12,10 @@ #include #include -#include "clk-mtk.h" -#include "clk-gate.h" #include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt7986-apmixed.c b/drivers/clk/mediatek/clk-mt7986-apmixed.c index 98ec3887585f..21d4c82e782a 100644 --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c @@ -10,9 +10,11 @@ #include #include #include -#include "clk-mtk.h" + #include "clk-gate.h" +#include "clk-mtk.h" #include "clk-mux.h" +#include "clk-pll.h" #include #include diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 9b4b645aea99..09ad272d51f1 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -11,8 +11,9 @@ #include #include -#include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" static DEFINE_SPINLOCK(mt8135_clk_lock); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index e5ea10e31799..812b33a57530 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -12,8 +12,9 @@ #include #include -#include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 8f898ac476c0..46b7655feeaa 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -8,9 +8,10 @@ #include #include -#include "clk-mtk.h" -#include "clk-gate.h" #include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 5046852eb0fd..68496554dd3d 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -11,9 +11,10 @@ #include #include +#include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-gate.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 79ddb3cc0b98..ab27cd66b866 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -12,9 +12,10 @@ #include #include +#include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" -#include "clk-gate.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 6156ceeed71e..5b1b7dc447eb 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -5,6 +5,7 @@ #include "clk-gate.h" #include "clk-mtk.h" +#include "clk-pll.h" #include #include diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c index f1c84186346e..db449ff877d7 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -4,6 +4,7 @@ // Author: Chun-Jie Chen #include "clk-mtk.h" +#include "clk-pll.h" #include #include diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index 9d4261ecc760..a37143f920ce 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -11,8 +11,9 @@ #include #include -#include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mtk.h" +#include "clk-pll.h" #include diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bdec7dc5e07a..168220f85489 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -179,45 +179,6 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); void mtk_free_clk_data(struct clk_onecell_data *clk_data); -#define HAVE_RST_BAR BIT(0) -#define PLL_AO BIT(1) - -struct mtk_pll_div_table { - u32 div; - unsigned long freq; -}; - -struct mtk_pll_data { - int id; - const char *name; - u32 reg; - u32 pwr_reg; - u32 en_mask; - u32 pd_reg; - u32 tuner_reg; - u32 tuner_en_reg; - u8 tuner_en_bit; - int pd_shift; - unsigned int flags; - const struct clk_ops *ops; - u32 rst_bar_mask; - unsigned long fmin; - unsigned long fmax; - int pcwbits; - int pcwibits; - u32 pcw_reg; - int pcw_shift; - u32 pcw_chg_reg; - const struct mtk_pll_div_table *div_table; - const char *parent_name; - u32 en_reg; - u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ -}; - -void mtk_clk_register_plls(struct device_node *node, - const struct mtk_pll_data *plls, int num_plls, - struct clk_onecell_data *clk_data); - struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f04f724e12e5..64f59554bc9b 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -13,6 +13,7 @@ #include #include "clk-mtk.h" +#include "clk-pll.h" #define REG_CON0 0 #define REG_CON1 4 diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h new file mode 100644 index 000000000000..d01b0c38311d --- /dev/null +++ b/drivers/clk/mediatek/clk-pll.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao + */ + +#ifndef __DRV_CLK_MTK_PLL_H +#define __DRV_CLK_MTK_PLL_H + +#include + +struct clk_ops; +struct clk_onecell_data; +struct device_node; + +struct mtk_pll_div_table { + u32 div; + unsigned long freq; +}; + +#define HAVE_RST_BAR BIT(0) +#define PLL_AO BIT(1) + +struct mtk_pll_data { + int id; + const char *name; + u32 reg; + u32 pwr_reg; + u32 en_mask; + u32 pd_reg; + u32 tuner_reg; + u32 tuner_en_reg; + u8 tuner_en_bit; + int pd_shift; + unsigned int flags; + const struct clk_ops *ops; + u32 rst_bar_mask; + unsigned long fmin; + unsigned long fmax; + int pcwbits; + int pcwibits; + u32 pcw_reg; + int pcw_shift; + u32 pcw_chg_reg; + const struct mtk_pll_div_table *div_table; + const char *parent_name; + u32 en_reg; + u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ +}; + +void mtk_clk_register_plls(struct device_node *node, + const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data); + +#endif /* __DRV_CLK_MTK_PLL_H */ -- cgit v1.2.3 From 6dd199064dd86127030b5bc59d4058370b6c8310 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:16 +0800 Subject: clk: mediatek: pll: Implement unregister API The PLL clk type within the MediaTek clk driver library only has a register function, and no corresponding unregister function. This means there is no way for its users to properly implement cleanup and removal. Add a matching unregister function for the PLL type clk. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-14-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-pll.c | 55 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-pll.h | 2 ++ 2 files changed, 57 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 64f59554bc9b..b54e33b75d4e 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -360,6 +360,21 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, return clk; } +static void mtk_clk_unregister_pll(struct clk *clk) +{ + struct clk_hw *hw; + struct mtk_clk_pll *pll; + + hw = __clk_get_hw(clk); + if (!hw) + return; + + pll = to_mtk_clk_pll(hw); + + clk_unregister(clk); + kfree(pll); +} + void mtk_clk_register_plls(struct device_node *node, const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) { @@ -388,4 +403,44 @@ void mtk_clk_register_plls(struct device_node *node, } EXPORT_SYMBOL_GPL(mtk_clk_register_plls); +static __iomem void *mtk_clk_pll_get_base(struct clk *clk, + const struct mtk_pll_data *data) +{ + struct clk_hw *hw = __clk_get_hw(clk); + struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); + + return pll->base_addr - data->reg; +} + +void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data) +{ + __iomem void *base = NULL; + int i; + + if (!clk_data) + return; + + for (i = num_plls; i > 0; i--) { + const struct mtk_pll_data *pll = &plls[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[pll->id])) + continue; + + /* + * This is quite ugly but unfortunately the clks don't have + * any device tied to them, so there's no place to store the + * pointer to the I/O region base address. We have to fetch + * it from one of the registered clks. + */ + base = mtk_clk_pll_get_base(clk_data->clks[pll->id], pll); + + mtk_clk_unregister_pll(clk_data->clks[pll->id]); + clk_data->clks[pll->id] = ERR_PTR(-ENOENT); + } + + iounmap(base); +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index d01b0c38311d..a889b1e472e7 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -51,5 +51,7 @@ struct mtk_pll_data { void mtk_clk_register_plls(struct device_node *node, const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data); +void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data); #endif /* __DRV_CLK_MTK_PLL_H */ -- cgit v1.2.3 From 10174b5077566b6754f87e02bd5260b5430ce711 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:17 +0800 Subject: clk: mediatek: pll: Clean up included headers Some included headers aren't actually used anywhere, while other headers with the declaration of functions and structures aren't directly included. Get rid of the unused ones, and add the ones that should be included directly. Also, copy the MHZ macro from clk-mtk.h, and drop clk-mtk.h from the included headers. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-15-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-pll.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index b54e33b75d4e..8439d37e354d 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -4,17 +4,19 @@ * Author: James Liao */ -#include -#include +#include +#include +#include +#include #include #include +#include #include -#include -#include -#include "clk-mtk.h" #include "clk-pll.h" +#define MHZ (1000 * 1000) + #define REG_CON0 0 #define REG_CON1 4 -- cgit v1.2.3 From 34c9d45418bca1a90ed24eb54f082746a261a325 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:18 +0800 Subject: clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API mtk_clk_register_fixed_clks(), as the name suggests, is used to register a given list of fixed rate clks. However it is lacking a counterpart unregister API. Implement said unregister API so that the various clock platform drivers can utilize it to do proper unregistration, cleanup and removal. In the header file, the register function's declaration is also reformatted to fit code style guidelines. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-16-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 20 ++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 6 ++++-- 2 files changed, 24 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 0c5db3c71fdd..7c0d5706eed7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -80,6 +80,26 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, } EXPORT_SYMBOL_GPL(mtk_clk_register_fixed_clks); +void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + if (!clk_data) + return; + + for (i = num; i > 0; i--) { + const struct mtk_fixed_clk *rc = &clks[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[rc->id])) + continue; + + clk_unregister_fixed_rate(clk_data->clks[rc->id]); + clk_data->clks[rc->id] = ERR_PTR(-ENOENT); + } +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_fixed_clks); + void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, struct clk_onecell_data *clk_data) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 168220f85489..cc7f920eabb4 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -34,8 +34,10 @@ struct mtk_fixed_clk { .rate = _rate, \ } -void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, - int num, struct clk_onecell_data *clk_data); +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, + struct clk_onecell_data *clk_data); +void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, + struct clk_onecell_data *clk_data); struct mtk_fixed_factor { int id; -- cgit v1.2.3 From 1c6d6b69baae1bb31605eea9d954e2c9a93c673c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:19 +0800 Subject: clk: mediatek: Implement mtk_clk_unregister_factors() API mtk_clk_register_factors(), as the name suggests, is used to register a given list of fixed factor clks. However it is lacking a counterpart unregister API. Implement said unregister API so that the various clock platform drivers can utilize it to do proper unregistration, cleanup and removal. In the header file, the register function's declaration is also reformatted to fit code style guidelines. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-17-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 20 ++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 6 ++++-- 2 files changed, 24 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 7c0d5706eed7..b267b2f04b84 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -126,6 +126,26 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, } EXPORT_SYMBOL_GPL(mtk_clk_register_factors); +void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + if (!clk_data) + return; + + for (i = num; i > 0; i--) { + const struct mtk_fixed_factor *ff = &clks[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[ff->id])) + continue; + + clk_unregister_fixed_factor(clk_data->clks[ff->id]); + clk_data->clks[ff->id] = ERR_PTR(-ENOENT); + } +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors); + struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index cc7f920eabb4..4db1a97c1250 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -55,8 +55,10 @@ struct mtk_fixed_factor { .div = _div, \ } -void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, - int num, struct clk_onecell_data *clk_data); +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, + struct clk_onecell_data *clk_data); +void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, + struct clk_onecell_data *clk_data); struct mtk_composite { int id; -- cgit v1.2.3 From b87385eb5a8ed25dd944c05608bead1733bbde1b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:20 +0800 Subject: clk: mediatek: Implement mtk_clk_unregister_divider_clks() API mtk_clk_register_divider_clks(), as the name suggests, is used to register a given list of divider clks. However it is lacking a counterpart unregister API. Implement said unregister API so that the various clock platform drivers can utilize it to do proper unregistration, cleanup and removal. In the header file, the register function's declaration is also reformatted to fit code style guidelines. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-18-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 19 +++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 8 +++++--- 2 files changed, 24 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b267b2f04b84..3a6dfe445e63 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -286,6 +286,25 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, } } +void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + if (!clk_data) + return; + + for (i = num; i > 0; i--) { + const struct mtk_clk_divider *mcd = &mcds[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[mcd->id])) + continue; + + clk_unregister_divider(clk_data->clks[mcd->id]); + clk_data->clks[mcd->id] = ERR_PTR(-ENOENT); + } +} + int mtk_clk_simple_probe(struct platform_device *pdev) { const struct mtk_clk_desc *mcd; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 4db1a97c1250..e3ae22fb0334 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -176,9 +176,11 @@ struct mtk_clk_divider { .div_width = _width, \ } -void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, - int num, void __iomem *base, spinlock_t *lock, - struct clk_onecell_data *clk_data); +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, + void __iomem *base, spinlock_t *lock, + struct clk_onecell_data *clk_data); +void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, + struct clk_onecell_data *clk_data); struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); void mtk_free_clk_data(struct clk_onecell_data *clk_data); -- cgit v1.2.3 From cb50864f6cee9c69573d135226b972b9b9abab26 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:21 +0800 Subject: clk: mediatek: Implement mtk_clk_unregister_composites() API mtk_clk_register_composites(), as the name suggests, is used to register a given list of composite clks. However it is lacking a counterpart unregister API. Implement said unregister API so that the various clock platform drivers can utilize it to do proper unregistration, cleanup and removal. In the header file, the register function's declaration is also reformatted to fit code style guidelines. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Link: https://lore.kernel.org/r/20220208124034.414635-19-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 46 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 2 ++ 2 files changed, 48 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 3a6dfe445e63..869e6ae55c82 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -233,6 +233,32 @@ err_out: return ERR_PTR(ret); } +static void mtk_clk_unregister_composite(struct clk *clk) +{ + struct clk_hw *hw; + struct clk_composite *composite; + struct clk_mux *mux = NULL; + struct clk_gate *gate = NULL; + struct clk_divider *div = NULL; + + hw = __clk_get_hw(clk); + if (!hw) + return; + + composite = to_clk_composite(hw); + if (composite->mux_hw) + mux = to_clk_mux(composite->mux_hw); + if (composite->gate_hw) + gate = to_clk_gate(composite->gate_hw); + if (composite->rate_hw) + div = to_clk_divider(composite->rate_hw); + + clk_unregister_composite(clk); + kfree(div); + kfree(gate); + kfree(mux); +} + void mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data) @@ -259,6 +285,26 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs, } EXPORT_SYMBOL_GPL(mtk_clk_register_composites); +void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, + struct clk_onecell_data *clk_data) +{ + int i; + + if (!clk_data) + return; + + for (i = num; i > 0; i--) { + const struct mtk_composite *mc = &mcs[i - 1]; + + if (IS_ERR_OR_NULL(clk_data->clks[mc->id])) + continue; + + mtk_clk_unregister_composite(clk_data->clks[mc->id]); + clk_data->clks[mc->id] = ERR_PTR(-ENOENT); + } +} +EXPORT_SYMBOL_GPL(mtk_clk_unregister_composites); + void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index e3ae22fb0334..3c3a934f53cd 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -153,6 +153,8 @@ struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, struct clk_onecell_data *clk_data); +void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, + struct clk_onecell_data *clk_data); struct mtk_clk_divider { int id; -- cgit v1.2.3 From 2204d96b1919126a7929da891fb6baa5fab8a945 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:22 +0800 Subject: clk: mediatek: Add mtk_clk_simple_remove() In commit c58cd0e40ffa ("clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers"), a generic probe function was added to simplify clk drivers that only needed to support clk gates. However due to the lack of unregister APIs, a corresponding remove function was not added. Now that the unregister APIs have been implemented, add aforementioned remove function to make it complete. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-20-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 15 +++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 1 + 2 files changed, 16 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 869e6ae55c82..f108786caeda 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -374,6 +374,8 @@ int mtk_clk_simple_probe(struct platform_device *pdev) if (r) goto free_data; + platform_set_drvdata(pdev, clk_data); + return r; free_data: @@ -381,4 +383,17 @@ free_data: return r; } +int mtk_clk_simple_remove(struct platform_device *pdev) +{ + const struct mtk_clk_desc *mcd = of_device_get_match_data(&pdev->dev); + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); + mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 3c3a934f53cd..4fa658f5d934 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -202,5 +202,6 @@ struct mtk_clk_desc { }; int mtk_clk_simple_probe(struct platform_device *pdev); +int mtk_clk_simple_remove(struct platform_device *pdev); #endif /* __DRV_CLK_MTK_H */ -- cgit v1.2.3 From c42a2888e0db3bb53e5a2df5ac5fd82991583595 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:23 +0800 Subject: clk: mediatek: mtk: Clean up included headers Some included headers aren't actually used anywhere, while other headers with the declaration of functions and structures aren't directly included. Get rid of the unused ones, and add the ones that should be included directly. On the header side, replace headers that are included purely for data structure definitions with forward declarations. This decreases the amount of preprocessing and compilation effort required for each inclusion. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-21-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 13 ++++++------- drivers/clk/mediatek/clk-mtk.h | 12 ++++++------ 2 files changed, 12 insertions(+), 13 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index f108786caeda..5618c84e4e08 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -4,17 +4,16 @@ * Author: James Liao */ -#include -#include +#include +#include #include #include -#include -#include -#include -#include #include -#include +#include +#include #include +#include +#include #include "clk-mtk.h" #include "clk-gate.h" diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 4fa658f5d934..7f902581a115 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -7,19 +7,19 @@ #ifndef __DRV_CLK_MTK_H #define __DRV_CLK_MTK_H -#include -#include #include -#include - -struct clk; -struct clk_onecell_data; +#include +#include +#include +#include #define MAX_MUX_GATE_BIT 31 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) #define MHZ (1000 * 1000) +struct platform_device; + struct mtk_fixed_clk { int id; const char *name; -- cgit v1.2.3 From 4e94ea5432f58d1454d4ac9478a6dec951c077d2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:24 +0800 Subject: clk: mediatek: cpumux: Implement error handling in register API The cpumux clk type registration function does not stop or return errors if any clk failed to be registered, nor does it implement an error handling path. This may result in a partially working device if any step failed. Make the register function return proper error codes, and bail out if errors occur. Proper cleanup, i.e. unregister any clks that were successfully registered, is done in the new error path. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-22-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-cpumux.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index 658aee789f44..499c60432280 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -123,13 +123,26 @@ int mtk_clk_register_cpumuxes(struct device_node *node, clk = mtk_clk_register_cpumux(mux, regmap); if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", mux->name, clk); - continue; + goto err; } clk_data->clks[mux->id] = clk; } return 0; + +err: + while (--i >= 0) { + const struct mtk_composite *mux = &clks[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) + continue; + + mtk_clk_unregister_cpumux(clk_data->clks[mux->id]); + clk_data->clks[mux->id] = ERR_PTR(-ENOENT); + } + + return PTR_ERR(clk); } void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num, -- cgit v1.2.3 From e938a13409884ed91ca35f3a09c71618800a797c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:25 +0800 Subject: clk: mediatek: gate: Implement error handling in register API The gate clk type registration function does not stop or return errors if any clk failed to be registered, nor does it implement an error handling path. This may result in a partially working device if any step failed. Make the register function return proper error codes, and bail out if errors occur. Proper cleanup, i.e. unregister any clks that were successfully registered, is done in the new error path. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-23-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-gate.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index e8881ae1489a..631ff170b7b9 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -237,13 +237,26 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", gate->name, clk); - continue; + goto err; } clk_data->clks[gate->id] = clk; } return 0; + +err: + while (--i >= 0) { + const struct mtk_gate *gate = &clks[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[gate->id])) + continue; + + mtk_clk_unregister_gate(clk_data->clks[gate->id]); + clk_data->clks[gate->id] = ERR_PTR(-ENOENT); + } + + return PTR_ERR(clk); } int mtk_clk_register_gates(struct device_node *node, -- cgit v1.2.3 From 203ce39ed50bed0fac716c7a811a67b1fcfde8d5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:26 +0800 Subject: clk: mediatek: mux: Reverse check for existing clk to reduce nesting level The clk registration code here currently does: if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) { ... do clk registration ... } This extra level of nesting wastes screen real estate. Reduce the nesting level by reversing the conditional shown above. Other than that, functionality is not changed. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-24-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mux.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 01af6a52711a..70aa42144632 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -208,16 +208,17 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, for (i = 0; i < num; i++) { const struct mtk_mux *mux = &muxes[i]; - if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) { - clk = mtk_clk_register_mux(mux, regmap, lock); + if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) + continue; - if (IS_ERR(clk)) { - pr_err("Failed to register clk %s: %pe\n", mux->name, clk); - continue; - } + clk = mtk_clk_register_mux(mux, regmap, lock); - clk_data->clks[mux->id] = clk; + if (IS_ERR(clk)) { + pr_err("Failed to register clk %s: %pe\n", mux->name, clk); + continue; } + + clk_data->clks[mux->id] = clk; } return 0; -- cgit v1.2.3 From eb7b7a7de99396ba0b92a24e79339f635d195bfb Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:27 +0800 Subject: clk: mediatek: mux: Implement error handling in register API The mux clk type registration function does not stop or return errors if any clk failed to be registered, nor does it implement an error handling path. This may result in a partially working device if any step failed. Make the register function return proper error codes, and bail out if errors occur. Proper cleanup, i.e. unregister any clks that were successfully registered, is done in the new error path. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-25-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mux.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 70aa42144632..f51e67650f03 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -215,13 +215,26 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", mux->name, clk); - continue; + goto err; } clk_data->clks[mux->id] = clk; } return 0; + +err: + while (--i >= 0) { + const struct mtk_mux *mux = &muxes[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[mux->id])) + continue; + + mtk_clk_unregister_mux(clk_data->clks[mux->id]); + clk_data->clks[mux->id] = ERR_PTR(-ENOENT); + } + + return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(mtk_clk_register_muxes); -- cgit v1.2.3 From 6ae34f2b7b8211a8d33a8b68dd5410f50e95bf0e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:28 +0800 Subject: clk: mediatek: pll: Implement error handling in register API The pll clk type registration function does not stop or return errors if any clk failed to be registered, nor does it implement an error handling path. This may result in a partially working device if any step failed. Make the register function return proper error codes, and bail out if errors occur. Proper cleanup, i.e. unregister any clks that were successfully registered, and unmap the I/O space, is done in the new error path. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-26-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-pll.c | 23 +++++++++++++++++++---- drivers/clk/mediatek/clk-pll.h | 6 +++--- 2 files changed, 22 insertions(+), 7 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 8439d37e354d..817a80293bfc 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -377,8 +377,9 @@ static void mtk_clk_unregister_pll(struct clk *clk) kfree(pll); } -void mtk_clk_register_plls(struct device_node *node, - const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) +int mtk_clk_register_plls(struct device_node *node, + const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data) { void __iomem *base; int i; @@ -387,7 +388,7 @@ void mtk_clk_register_plls(struct device_node *node, base = of_iomap(node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); - return; + return -EINVAL; } for (i = 0; i < num_plls; i++) { @@ -397,11 +398,25 @@ void mtk_clk_register_plls(struct device_node *node, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", pll->name, clk); - continue; + goto err; } clk_data->clks[pll->id] = clk; } + + return 0; + +err: + while (--i >= 0) { + const struct mtk_pll_data *pll = &plls[i]; + + mtk_clk_unregister_pll(clk_data->clks[pll->id]); + clk_data->clks[pll->id] = ERR_PTR(-ENOENT); + } + + iounmap(base); + + return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(mtk_clk_register_plls); diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h index a889b1e472e7..bf06e44caef9 100644 --- a/drivers/clk/mediatek/clk-pll.h +++ b/drivers/clk/mediatek/clk-pll.h @@ -48,9 +48,9 @@ struct mtk_pll_data { u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ }; -void mtk_clk_register_plls(struct device_node *node, - const struct mtk_pll_data *plls, int num_plls, - struct clk_onecell_data *clk_data); +int mtk_clk_register_plls(struct device_node *node, + const struct mtk_pll_data *plls, int num_plls, + struct clk_onecell_data *clk_data); void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data); -- cgit v1.2.3 From 3c3ba2ab0226f9a4f4312a5db2dd402ec42392ca Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:29 +0800 Subject: clk: mediatek: mtk: Implement error handling in register APIs The remaining clk registration functions do not stop or return errors if any clk failed to be registered, nor do they implement error handling paths. This may result in a partially working device if any step fails. Make the register functions return proper error codes, and bail out if errors occur. Proper cleanup, i.e. unregister any clks that were successfully registered, is done in the new error path. This also makes the |struct clk_data *| argument mandatory, as it is used to track the list of clks registered. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-27-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 118 ++++++++++++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mtk.h | 20 +++---- 2 files changed, 103 insertions(+), 35 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 5618c84e4e08..8f15e9de742e 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -53,16 +53,19 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data) kfree(clk_data); } -void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, - int num, struct clk_onecell_data *clk_data) +int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, + struct clk_onecell_data *clk_data) { int i; struct clk *clk; + if (!clk_data) + return -ENOMEM; + for (i = 0; i < num; i++) { const struct mtk_fixed_clk *rc = &clks[i]; - if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[rc->id])) continue; clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0, @@ -70,12 +73,26 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", rc->name, clk); - continue; + goto err; } - if (clk_data) - clk_data->clks[rc->id] = clk; + clk_data->clks[rc->id] = clk; } + + return 0; + +err: + while (--i >= 0) { + const struct mtk_fixed_clk *rc = &clks[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[rc->id])) + continue; + + clk_unregister_fixed_rate(clk_data->clks[rc->id]); + clk_data->clks[rc->id] = ERR_PTR(-ENOENT); + } + + return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(mtk_clk_register_fixed_clks); @@ -99,16 +116,19 @@ void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_fixed_clks); -void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, - int num, struct clk_onecell_data *clk_data) +int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, + struct clk_onecell_data *clk_data) { int i; struct clk *clk; + if (!clk_data) + return -ENOMEM; + for (i = 0; i < num; i++) { const struct mtk_fixed_factor *ff = &clks[i]; - if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[ff->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[ff->id])) continue; clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name, @@ -116,12 +136,26 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", ff->name, clk); - continue; + goto err; } - if (clk_data) - clk_data->clks[ff->id] = clk; + clk_data->clks[ff->id] = clk; + } + + return 0; + +err: + while (--i >= 0) { + const struct mtk_fixed_factor *ff = &clks[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[ff->id])) + continue; + + clk_unregister_fixed_factor(clk_data->clks[ff->id]); + clk_data->clks[ff->id] = ERR_PTR(-ENOENT); } + + return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(mtk_clk_register_factors); @@ -258,13 +292,16 @@ static void mtk_clk_unregister_composite(struct clk *clk) kfree(mux); } -void mtk_clk_register_composites(const struct mtk_composite *mcs, - int num, void __iomem *base, spinlock_t *lock, - struct clk_onecell_data *clk_data) +int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, + void __iomem *base, spinlock_t *lock, + struct clk_onecell_data *clk_data) { struct clk *clk; int i; + if (!clk_data) + return -ENOMEM; + for (i = 0; i < num; i++) { const struct mtk_composite *mc = &mcs[i]; @@ -275,12 +312,26 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", mc->name, clk); - continue; + goto err; } - if (clk_data) - clk_data->clks[mc->id] = clk; + clk_data->clks[mc->id] = clk; + } + + return 0; + +err: + while (--i >= 0) { + const struct mtk_composite *mc = &mcs[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[mcs->id])) + continue; + + mtk_clk_unregister_composite(clk_data->clks[mc->id]); + clk_data->clks[mc->id] = ERR_PTR(-ENOENT); } + + return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(mtk_clk_register_composites); @@ -304,17 +355,20 @@ void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_composites); -void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, - int num, void __iomem *base, spinlock_t *lock, - struct clk_onecell_data *clk_data) +int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, + void __iomem *base, spinlock_t *lock, + struct clk_onecell_data *clk_data) { struct clk *clk; int i; + if (!clk_data) + return -ENOMEM; + for (i = 0; i < num; i++) { const struct mtk_clk_divider *mcd = &mcds[i]; - if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[mcd->id])) continue; clk = clk_register_divider(NULL, mcd->name, mcd->parent_name, @@ -323,12 +377,26 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", mcd->name, clk); - continue; + goto err; } - if (clk_data) - clk_data->clks[mcd->id] = clk; + clk_data->clks[mcd->id] = clk; + } + + return 0; + +err: + while (--i >= 0) { + const struct mtk_clk_divider *mcd = &mcds[i]; + + if (IS_ERR_OR_NULL(clk_data->clks[mcd->id])) + continue; + + mtk_clk_unregister_composite(clk_data->clks[mcd->id]); + clk_data->clks[mcd->id] = ERR_PTR(-ENOENT); } + + return PTR_ERR(clk); } void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 7f902581a115..bf6565aa7319 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -34,8 +34,8 @@ struct mtk_fixed_clk { .rate = _rate, \ } -void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, - struct clk_onecell_data *clk_data); +int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, + struct clk_onecell_data *clk_data); void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, struct clk_onecell_data *clk_data); @@ -55,8 +55,8 @@ struct mtk_fixed_factor { .div = _div, \ } -void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, - struct clk_onecell_data *clk_data); +int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, + struct clk_onecell_data *clk_data); void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, struct clk_onecell_data *clk_data); @@ -150,9 +150,9 @@ struct mtk_composite { struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock); -void mtk_clk_register_composites(const struct mtk_composite *mcs, - int num, void __iomem *base, spinlock_t *lock, - struct clk_onecell_data *clk_data); +int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, + void __iomem *base, spinlock_t *lock, + struct clk_onecell_data *clk_data); void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, struct clk_onecell_data *clk_data); @@ -178,9 +178,9 @@ struct mtk_clk_divider { .div_width = _width, \ } -void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, - void __iomem *base, spinlock_t *lock, - struct clk_onecell_data *clk_data); +int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, + void __iomem *base, spinlock_t *lock, + struct clk_onecell_data *clk_data); void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, struct clk_onecell_data *clk_data); -- cgit v1.2.3 From 2d18b7e31aa804dc6c0e43545ae5b028802e6f86 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:30 +0800 Subject: clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path Until now the mediatek clk driver library did not have any way to unregister clks, and so all drivers did not do proper cleanup in their error paths. Now that the library does have APIs to unregister clks, use them in the error path of mtk_clk_simple_probe() to do proper cleanup. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-28-wenst@chromium.org Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 8f15e9de742e..0e027be0d5fc 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -439,12 +439,14 @@ int mtk_clk_simple_probe(struct platform_device *pdev) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_data; + goto unregister_clks; platform_set_drvdata(pdev, clk_data); return r; +unregister_clks: + mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); free_data: mtk_free_clk_data(clk_data); return r; -- cgit v1.2.3 From cd3a77a085f5449696aed6f8f350241d4be509e8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:31 +0800 Subject: clk: mediatek: mt8195: Hook up mtk_clk_simple_remove() Various small clock controllers only have clock gates, and utilize mtk_clk_simple_probe() as their driver probe function. Now that we have a matching remove function, hook it up for the relevant drivers. This was done with the following command: sed -i -e '/mtk_clk_simple_probe/a \ .remove = mtk_clk_simple_remove,' drivers/clk/mediatek/clk-mt8195-*.c Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Link: https://lore.kernel.org/r/20220208124034.414635-29-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chun-Jie Chen Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8195-cam.c | 1 + drivers/clk/mediatek/clk-mt8195-ccu.c | 1 + drivers/clk/mediatek/clk-mt8195-img.c | 1 + drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c | 1 + drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 + drivers/clk/mediatek/clk-mt8195-ipe.c | 1 + drivers/clk/mediatek/clk-mt8195-mfg.c | 1 + drivers/clk/mediatek/clk-mt8195-peri_ao.c | 1 + drivers/clk/mediatek/clk-mt8195-scp_adsp.c | 1 + drivers/clk/mediatek/clk-mt8195-vdec.c | 1 + drivers/clk/mediatek/clk-mt8195-venc.c | 1 + drivers/clk/mediatek/clk-mt8195-vpp0.c | 1 + drivers/clk/mediatek/clk-mt8195-vpp1.c | 1 + drivers/clk/mediatek/clk-mt8195-wpe.c | 1 + 14 files changed, 14 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mt8195-cam.c b/drivers/clk/mediatek/clk-mt8195-cam.c index 3d261fc3848e..e4d00fe6e757 100644 --- a/drivers/clk/mediatek/clk-mt8195-cam.c +++ b/drivers/clk/mediatek/clk-mt8195-cam.c @@ -134,6 +134,7 @@ static const struct of_device_id of_match_clk_mt8195_cam[] = { static struct platform_driver clk_mt8195_cam_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-cam", .of_match_table = of_match_clk_mt8195_cam, diff --git a/drivers/clk/mediatek/clk-mt8195-ccu.c b/drivers/clk/mediatek/clk-mt8195-ccu.c index f846f1d73605..4e326b6301ba 100644 --- a/drivers/clk/mediatek/clk-mt8195-ccu.c +++ b/drivers/clk/mediatek/clk-mt8195-ccu.c @@ -42,6 +42,7 @@ static const struct of_device_id of_match_clk_mt8195_ccu[] = { static struct platform_driver clk_mt8195_ccu_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-ccu", .of_match_table = of_match_clk_mt8195_ccu, diff --git a/drivers/clk/mediatek/clk-mt8195-img.c b/drivers/clk/mediatek/clk-mt8195-img.c index 22b52a8f15fe..12f5c436d075 100644 --- a/drivers/clk/mediatek/clk-mt8195-img.c +++ b/drivers/clk/mediatek/clk-mt8195-img.c @@ -88,6 +88,7 @@ static const struct of_device_id of_match_clk_mt8195_img[] = { static struct platform_driver clk_mt8195_img_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-img", .of_match_table = of_match_clk_mt8195_img, diff --git a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c index 4ab312eb26a5..fbc809d05072 100644 --- a/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c +++ b/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c @@ -58,6 +58,7 @@ static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = { static struct platform_driver clk_mt8195_imp_iic_wrap_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-imp_iic_wrap", .of_match_table = of_match_clk_mt8195_imp_iic_wrap, diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/mediatek/clk-mt8195-infra_ao.c index 5f9b69967459..8ebe3b9415c4 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -198,6 +198,7 @@ static const struct of_device_id of_match_clk_mt8195_infra_ao[] = { static struct platform_driver clk_mt8195_infra_ao_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-infra_ao", .of_match_table = of_match_clk_mt8195_infra_ao, diff --git a/drivers/clk/mediatek/clk-mt8195-ipe.c b/drivers/clk/mediatek/clk-mt8195-ipe.c index fc1d42b6ac84..b0d745cf7752 100644 --- a/drivers/clk/mediatek/clk-mt8195-ipe.c +++ b/drivers/clk/mediatek/clk-mt8195-ipe.c @@ -43,6 +43,7 @@ static const struct of_device_id of_match_clk_mt8195_ipe[] = { static struct platform_driver clk_mt8195_ipe_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-ipe", .of_match_table = of_match_clk_mt8195_ipe, diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c index aca6d9c0837c..9411c556a5a9 100644 --- a/drivers/clk/mediatek/clk-mt8195-mfg.c +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8195_mfg[] = { static struct platform_driver clk_mt8195_mfg_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-mfg", .of_match_table = of_match_clk_mt8195_mfg, diff --git a/drivers/clk/mediatek/clk-mt8195-peri_ao.c b/drivers/clk/mediatek/clk-mt8195-peri_ao.c index 907a92b22de8..2f6b3bb657db 100644 --- a/drivers/clk/mediatek/clk-mt8195-peri_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-peri_ao.c @@ -54,6 +54,7 @@ static const struct of_device_id of_match_clk_mt8195_peri_ao[] = { static struct platform_driver clk_mt8195_peri_ao_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-peri_ao", .of_match_table = of_match_clk_mt8195_peri_ao, diff --git a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c index 26b4846c5894..e16c383f631b 100644 --- a/drivers/clk/mediatek/clk-mt8195-scp_adsp.c +++ b/drivers/clk/mediatek/clk-mt8195-scp_adsp.c @@ -39,6 +39,7 @@ static const struct of_device_id of_match_clk_mt8195_scp_adsp[] = { static struct platform_driver clk_mt8195_scp_adsp_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-scp_adsp", .of_match_table = of_match_clk_mt8195_scp_adsp, diff --git a/drivers/clk/mediatek/clk-mt8195-vdec.c b/drivers/clk/mediatek/clk-mt8195-vdec.c index a1df04f42a90..a1446b666385 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdec.c +++ b/drivers/clk/mediatek/clk-mt8195-vdec.c @@ -96,6 +96,7 @@ static const struct of_device_id of_match_clk_mt8195_vdec[] = { static struct platform_driver clk_mt8195_vdec_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-vdec", .of_match_table = of_match_clk_mt8195_vdec, diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c index 7339851a0856..622f57804f96 100644 --- a/drivers/clk/mediatek/clk-mt8195-venc.c +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -61,6 +61,7 @@ static const struct of_device_id of_match_clk_mt8195_venc[] = { static struct platform_driver clk_mt8195_venc_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-venc", .of_match_table = of_match_clk_mt8195_venc, diff --git a/drivers/clk/mediatek/clk-mt8195-vpp0.c b/drivers/clk/mediatek/clk-mt8195-vpp0.c index c3241466a8d0..bf2939c3a023 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp0.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp0.c @@ -102,6 +102,7 @@ static const struct of_device_id of_match_clk_mt8195_vpp0[] = { static struct platform_driver clk_mt8195_vpp0_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-vpp0", .of_match_table = of_match_clk_mt8195_vpp0, diff --git a/drivers/clk/mediatek/clk-mt8195-vpp1.c b/drivers/clk/mediatek/clk-mt8195-vpp1.c index ce0b9a40a179..ffd52c762890 100644 --- a/drivers/clk/mediatek/clk-mt8195-vpp1.c +++ b/drivers/clk/mediatek/clk-mt8195-vpp1.c @@ -100,6 +100,7 @@ static const struct of_device_id of_match_clk_mt8195_vpp1[] = { static struct platform_driver clk_mt8195_vpp1_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-vpp1", .of_match_table = of_match_clk_mt8195_vpp1, diff --git a/drivers/clk/mediatek/clk-mt8195-wpe.c b/drivers/clk/mediatek/clk-mt8195-wpe.c index 274d60838d8e..b483fab10e18 100644 --- a/drivers/clk/mediatek/clk-mt8195-wpe.c +++ b/drivers/clk/mediatek/clk-mt8195-wpe.c @@ -135,6 +135,7 @@ static const struct of_device_id of_match_clk_mt8195_wpe[] = { static struct platform_driver clk_mt8195_wpe_drv = { .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8195-wpe", .of_match_table = of_match_clk_mt8195_wpe, -- cgit v1.2.3 From f3e690b00b86d2b2182b70433993fb038515f086 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:32 +0800 Subject: clk: mediatek: mt8195: Implement error handling in probe functions Until now the mediatek clk driver library did not have any way to unregister clks, and so all drivers did not do proper cleanup in their error paths. Now that the library does have APIs to unregister clks, use them in the error path of the probe functions for the mt8195 clk drivers to do proper cleanup. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220208124034.414635-30-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 13 ++++++-- drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 9 +++-- drivers/clk/mediatek/clk-mt8195-topckgen.c | 49 +++++++++++++++++++++------- drivers/clk/mediatek/clk-mt8195-vdo0.c | 4 ++- drivers/clk/mediatek/clk-mt8195-vdo1.c | 4 ++- 5 files changed, 61 insertions(+), 18 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 5b1b7dc447eb..d0fdb5a4a921 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -120,17 +120,24 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); if (r) goto free_apmixed_data; + r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + if (r) + goto unregister_plls; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_apmixed_data; + goto unregister_gates; return r; +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); free_apmixed_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c index db449ff877d7..f489b57e325e 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -66,13 +66,18 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data); - r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + r = mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data); if (r) goto free_apusys_pll_data; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) + goto unregister_plls; + return r; +unregister_plls: + mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data); free_apusys_pll_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 3e2aba9c40bb..3631f49a5e5a 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1239,25 +1239,52 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev) goto free_top_data; } - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, - &mt8195_clk_lock, top_clk_data); - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8195_clk_lock, top_clk_data); - mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt8195_clk_lock, top_clk_data); - r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); + r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + top_clk_data); if (r) goto free_top_data; + r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); + if (r) + goto unregister_fixed_clks; + + r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, + &mt8195_clk_lock, top_clk_data); + if (r) + goto unregister_factors; + + r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, + &mt8195_clk_lock, top_clk_data); + if (r) + goto unregister_muxes; + + r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, + &mt8195_clk_lock, top_clk_data); + if (r) + goto unregister_composite_muxes; + + r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); + if (r) + goto unregister_composite_divs; + r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); if (r) - goto free_top_data; + goto unregister_gates; return r; +unregister_gates: + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); +unregister_composite_divs: + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data); +unregister_composite_muxes: + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data); +unregister_muxes: + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); free_top_data: mtk_free_clk_data(top_clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index f7ff7618c714..af34eb564b1d 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -105,10 +105,12 @@ static int clk_mt8195_vdo0_probe(struct platform_device *pdev) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_vdo0_data; + goto unregister_gates; return r; +unregister_gates: + mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); free_vdo0_data: mtk_free_clk_data(clk_data); return r; diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 03df8eae8838..6b502bbc730c 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -122,10 +122,12 @@ static int clk_mt8195_vdo1_probe(struct platform_device *pdev) r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) - goto free_vdo1_data; + goto unregister_gates; return r; +unregister_gates: + mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); free_vdo1_data: mtk_free_clk_data(clk_data); return r; -- cgit v1.2.3 From cf8a482afc286dde5eaf4a08d12b63590c599764 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:33 +0800 Subject: clk: mediatek: mt8195: Implement remove functions Until now the mediatek clk driver library did not have any way to unregister clks, and so none of the drivers implemented remove functions. Now that the library does have APIs to unregister clks, use them to implement remove functions for the mt8195 clk drivers. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Link: https://lore.kernel.org/r/20220208124034.414635-31-wenst@chromium.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 16 ++++++++++++++++ drivers/clk/mediatek/clk-mt8195-apusys_pll.c | 15 +++++++++++++++ drivers/clk/mediatek/clk-mt8195-topckgen.c | 20 ++++++++++++++++++++ drivers/clk/mediatek/clk-mt8195-vdo0.c | 16 ++++++++++++++++ drivers/clk/mediatek/clk-mt8195-vdo1.c | 16 ++++++++++++++++ 5 files changed, 83 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index d0fdb5a4a921..eecc7035a56a 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -132,6 +132,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev) if (r) goto unregister_gates; + platform_set_drvdata(pdev, clk_data); + return r; unregister_gates: @@ -143,8 +145,22 @@ free_apmixed_data: return r; } +static int clk_mt8195_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + static struct platform_driver clk_mt8195_apmixed_drv = { .probe = clk_mt8195_apmixed_probe, + .remove = clk_mt8195_apmixed_remove, .driver = { .name = "clk-mt8195-apmixed", .of_match_table = of_match_clk_mt8195_apmixed, diff --git a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c index f489b57e325e..8cd88dfc3283 100644 --- a/drivers/clk/mediatek/clk-mt8195-apusys_pll.c +++ b/drivers/clk/mediatek/clk-mt8195-apusys_pll.c @@ -74,6 +74,8 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev) if (r) goto unregister_plls; + platform_set_drvdata(pdev, clk_data); + return r; unregister_plls: @@ -83,6 +85,18 @@ free_apusys_pll_data: return r; } +static int clk_mt8195_apusys_pll_remove(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); + mtk_clk_unregister_plls(apusys_plls, ARRAY_SIZE(apusys_plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = { { .compatible = "mediatek,mt8195-apusys_pll", }, {} @@ -90,6 +104,7 @@ static const struct of_device_id of_match_clk_mt8195_apusys_pll[] = { static struct platform_driver clk_mt8195_apusys_pll_drv = { .probe = clk_mt8195_apusys_pll_probe, + .remove = clk_mt8195_apusys_pll_remove, .driver = { .name = "clk-mt8195-apusys_pll", .of_match_table = of_match_clk_mt8195_apusys_pll, diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 3631f49a5e5a..b602fcd7f1d1 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1271,6 +1271,8 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev) if (r) goto unregister_gates; + platform_set_drvdata(pdev, top_clk_data); + return r; unregister_gates: @@ -1290,8 +1292,26 @@ free_top_data: return r; } +static int clk_mt8195_topck_remove(struct platform_device *pdev) +{ + struct clk_onecell_data *top_clk_data = platform_get_drvdata(pdev); + struct device_node *node = pdev->dev.of_node; + + of_clk_del_provider(node); + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data); + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data); + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data); + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); + mtk_free_clk_data(top_clk_data); + + return 0; +} + static struct platform_driver clk_mt8195_topck_drv = { .probe = clk_mt8195_topck_probe, + .remove = clk_mt8195_topck_remove, .driver = { .name = "clk-mt8195-topck", .of_match_table = of_match_clk_mt8195_topck, diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index af34eb564b1d..3bc7ed19d550 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -107,6 +107,8 @@ static int clk_mt8195_vdo0_probe(struct platform_device *pdev) if (r) goto unregister_gates; + platform_set_drvdata(pdev, clk_data); + return r; unregister_gates: @@ -116,8 +118,22 @@ free_vdo0_data: return r; } +static int clk_mt8195_vdo0_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + static struct platform_driver clk_mt8195_vdo0_drv = { .probe = clk_mt8195_vdo0_probe, + .remove = clk_mt8195_vdo0_remove, .driver = { .name = "clk-mt8195-vdo0", }, diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 6b502bbc730c..90c738a85ff1 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -124,6 +124,8 @@ static int clk_mt8195_vdo1_probe(struct platform_device *pdev) if (r) goto unregister_gates; + platform_set_drvdata(pdev, clk_data); + return r; unregister_gates: @@ -133,8 +135,22 @@ free_vdo1_data: return r; } +static int clk_mt8195_vdo1_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; + struct clk_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + static struct platform_driver clk_mt8195_vdo1_drv = { .probe = clk_mt8195_vdo1_probe, + .remove = clk_mt8195_vdo1_remove, .driver = { .name = "clk-mt8195-vdo1", }, -- cgit v1.2.3 From d54bb86b89556712d92154a386b421012fecf79e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 8 Feb 2022 20:40:34 +0800 Subject: clk: mediatek: Warn if clk IDs are duplicated The Mediatek clk driver library handles duplicate clock IDs in two different ways: either ignoring the duplicate entry, or overwriting the old clk. Either way may cause unexpected behavior, and the latter also causes an orphan clk that cannot be cleaned up. Align the behavior so that later duplicate entries are ignored, and a warning printed. The warning will also aid in making the issue noticeable. Signed-off-by: Chen-Yu Tsai Reviewed-by: Miles Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220208124034.414635-32-wenst@chromium.org Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-cpumux.c | 6 ++++++ drivers/clk/mediatek/clk-gate.c | 5 ++++- drivers/clk/mediatek/clk-mtk.c | 18 ++++++++++++++---- drivers/clk/mediatek/clk-mux.c | 5 ++++- drivers/clk/mediatek/clk-pll.c | 6 ++++++ 5 files changed, 34 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c index 499c60432280..c11b3fae622e 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -120,6 +120,12 @@ int mtk_clk_register_cpumuxes(struct device_node *node, for (i = 0; i < num; i++) { const struct mtk_composite *mux = &clks[i]; + if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) { + pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", + node, mux->id); + continue; + } + clk = mtk_clk_register_cpumux(mux, regmap); if (IS_ERR(clk)) { pr_err("Failed to register clk %s: %pe\n", mux->name, clk); diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 631ff170b7b9..da52023f8455 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -224,8 +224,11 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, for (i = 0; i < num; i++) { const struct mtk_gate *gate = &clks[i]; - if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) { + pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", + node, gate->id); continue; + } clk = mtk_clk_register_gate(gate->name, gate->parent_name, regmap, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 0e027be0d5fc..b4063261cf56 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -65,8 +65,10 @@ int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, for (i = 0; i < num; i++) { const struct mtk_fixed_clk *rc = &clks[i]; - if (!IS_ERR_OR_NULL(clk_data->clks[rc->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[rc->id])) { + pr_warn("Trying to register duplicate clock ID: %d\n", rc->id); continue; + } clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0, rc->rate); @@ -128,8 +130,10 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, for (i = 0; i < num; i++) { const struct mtk_fixed_factor *ff = &clks[i]; - if (!IS_ERR_OR_NULL(clk_data->clks[ff->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[ff->id])) { + pr_warn("Trying to register duplicate clock ID: %d\n", ff->id); continue; + } clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name, CLK_SET_RATE_PARENT, ff->mult, ff->div); @@ -305,8 +309,11 @@ int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, for (i = 0; i < num; i++) { const struct mtk_composite *mc = &mcs[i]; - if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mc->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[mc->id])) { + pr_warn("Trying to register duplicate clock ID: %d\n", + mc->id); continue; + } clk = mtk_clk_register_composite(mc, base, lock); @@ -368,8 +375,11 @@ int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, for (i = 0; i < num; i++) { const struct mtk_clk_divider *mcd = &mcds[i]; - if (!IS_ERR_OR_NULL(clk_data->clks[mcd->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[mcd->id])) { + pr_warn("Trying to register duplicate clock ID: %d\n", + mcd->id); continue; + } clk = clk_register_divider(NULL, mcd->name, mcd->parent_name, mcd->flags, base + mcd->div_reg, mcd->div_shift, diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index f51e67650f03..21ad5a4afd65 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -208,8 +208,11 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, for (i = 0; i < num; i++) { const struct mtk_mux *mux = &muxes[i]; - if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) + if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) { + pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", + node, mux->id); continue; + } clk = mtk_clk_register_mux(mux, regmap, lock); diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 817a80293bfc..ccaa2085ab4d 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -394,6 +394,12 @@ int mtk_clk_register_plls(struct device_node *node, for (i = 0; i < num_plls; i++) { const struct mtk_pll_data *pll = &plls[i]; + if (!IS_ERR_OR_NULL(clk_data->clks[pll->id])) { + pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", + node, pll->id); + continue; + } + clk = mtk_clk_register_pll(pll, base); if (IS_ERR(clk)) { -- cgit v1.2.3 From b191fe39a5ff2334b60ef4588ec15a0abd88f6a4 Mon Sep 17 00:00:00 2001 From: Wang Qing Date: Mon, 14 Feb 2022 17:55:39 -0800 Subject: clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it Use the helper function time_is_{before,after}_jiffies() to improve code readability. Signed-off-by: Wang Qing Link: https://lore.kernel.org/r/1644890154-64915-3-git-send-email-wangqing@vivo.com Signed-off-by: Stephen Boyd --- drivers/clk/mvebu/armada-37xx-periph.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c index 32ac6b6b7530..e3777ca65912 100644 --- a/drivers/clk/mvebu/armada-37xx-periph.c +++ b/drivers/clk/mvebu/armada-37xx-periph.c @@ -25,6 +25,7 @@ #include #include #include +#include #define TBG_SEL 0x0 #define DIV_SEL0 0x4 @@ -541,7 +542,7 @@ static void clk_pm_cpu_set_rate_wa(struct clk_pm_cpu *pm_cpu, * We are going to L0 with rate >= 1GHz. Check whether we have been at * L1 for long enough time. If not, go to L1 for 20ms. */ - if (pm_cpu->l1_expiration && jiffies >= pm_cpu->l1_expiration) + if (pm_cpu->l1_expiration && time_is_before_eq_jiffies(pm_cpu->l1_expiration)) goto invalidate_l1_exp; regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD, -- cgit v1.2.3 From 39d1e443173a58a6a3452bb931907ce0fb4061e3 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Fri, 11 Feb 2022 11:13:11 +0200 Subject: clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock The IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock derives from the media_mipi_phy1_ref clock and is gated by the shared media clock gate. Its identifier is defined in dt-bindings/clock/imx8mp-clock.h but its definition is missing from the driver. Add it. Signed-off-by: Laurent Pinchart Reviewed-by: Paul Elder Link: https://lore.kernel.org/r/20220211091311.28146-1-laurent.pinchart@ideasonboard.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index c990ad37882b..f23b92906d3b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -694,6 +694,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] = imx_clk_hw_gate2_shared2("media_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media); hws[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0); -- cgit v1.2.3 From 691419f90f7fb8a6f247b477cb539644e11431da Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 7 Jan 2022 15:34:36 +0100 Subject: clk: renesas: r8a779f0: Fix RSW2 clock divider According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note 22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated from CPGMA1"), the RSwitch2 and PCI Express clock is generated from PLL5 by dividing by two, followed by the RSW2 divider. As PLL5 runs at 3200 MHz, and RSW2 is fixed to 320 MHz, the RSW2 divider must be 5. Correct the parent and the fixed divider. Fixes: 24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/d6a406f31e6f02f892e0253f4e8a9a2f68fd652e.1641566003.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 8cc7457564db..4100078406d6 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -103,7 +103,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { DEF_FIXED("s0d12_hsc", R8A779F0_CLK_S0D12_HSC, CLK_S0, 12, 1), DEF_FIXED("cl16m_hsc", R8A779F0_CLK_CL16M_HSC, CLK_S0, 48, 1), DEF_FIXED("s0d2_cc", R8A779F0_CLK_S0D2_CC, CLK_S0, 2, 1), - DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5, 2, 1), + DEF_FIXED("rsw2", R8A779F0_CLK_RSW2, CLK_PLL5_DIV2, 5, 1), DEF_FIXED("cbfusa", R8A779F0_CLK_CBFUSA, CLK_EXTAL, 2, 1), DEF_FIXED("cpex", R8A779F0_CLK_CPEX, CLK_EXTAL, 2, 1), -- cgit v1.2.3 From 78789705581dcb2138302de11dce2ee2642e758e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Jan 2022 18:09:01 +0100 Subject: clk: renesas: r8a779f0: Add WDT clock Add the module clock used by the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to ensure uninterrupted watchdog operation. Signed-off-by: Geert Uytterhoeven Acked-by: Guenter Roeck Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/8d9b280065a663f2cf31db7b21a010aa781a0af1.1642525158.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 4100078406d6..e48c5af73414 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -121,6 +121,11 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), + DEF_MOD("wdt", 907, R8A779F0_CLK_R), +}; + +static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { + MOD_CLK_ID(907), /* WDT */ }; /* @@ -177,6 +182,10 @@ const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), .num_hw_mod_clks = 28 * 32, + /* Critical Module Clocks */ + .crit_mod_clks = r8a779f0_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks), + /* Callbacks */ .init = r8a779f0_cpg_mssr_init, .cpg_clk_register = rcar_gen4_cpg_clk_register, -- cgit v1.2.3 From 5447d32c55592610969fa7e825a591c4104f0134 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 15:34:28 +0100 Subject: clk: renesas: r8a779f0: Add I2C clocks Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/e4dcee5f6f521dccd7ac7f2fb6c86cfe4a24d032.1643898820.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index e48c5af73414..123c1b01550d 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -115,6 +115,12 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { + DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER), + DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER), + DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER), + DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER), + DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER), + DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER), DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), -- cgit v1.2.3 From 73421f2a48e6bd1d1024a09aedbc9c662cb88e77 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Feb 2022 16:35:56 +0100 Subject: clk: renesas: r8a779f0: Add PFC clock Add the module clock used by the Pin Function (PFC/GPIO) controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/4ef3d3dfe714ad75112e4886efea0b66e40a33bc.1645457502.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 123c1b01550d..76b441965037 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), + DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M), }; static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { -- cgit v1.2.3 From 9f565399ad0739dbdeac868e40e86e80f54dc77b Mon Sep 17 00:00:00 2001 From: "Minghao Chi (CGEL ZTE)" Date: Mon, 21 Feb 2022 02:01:03 +0000 Subject: clk/rockchip: Use of_device_get_match_data() Use of_device_get_match_data() to simplify the code. Reported-by: Zeal Robot Signed-off-by: Minghao Chi (CGEL ZTE) Link: https://lore.kernel.org/r/20220221020103.1925026-1-chi.minghao@zte.com.cn Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3568.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 63dfbeeeb06d..606ae6cd918b 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1703,14 +1703,12 @@ static const struct of_device_id clk_rk3568_match_table[] = { static int __init clk_rk3568_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - const struct of_device_id *match; const struct clk_rk3568_inits *init_data; - match = of_match_device(clk_rk3568_match_table, &pdev->dev); - if (!match || !match->data) + init_data = (struct clk_rk3568_inits *)of_device_get_match_data(&pdev->dev); + if (!init_data) return -EINVAL; - init_data = match->data; if (init_data->inits) init_data->inits(np); -- cgit v1.2.3 From 10b74af310735860510a533433b1d3ab2e05a138 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 31 Jan 2022 17:32:24 +0100 Subject: clk: rockchip: re-add rational best approximation algorithm to the fractional divider In commit 4e7cf74fa3b2 ("clk: fractional-divider: Export approximation algorithm to the CCF users"), the code handling the rational best approximation algorithm was replaced by a call to the core clk_fractional_divider_general_approximation function which did the same thing back then. However, in commit 82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag"), this common code was made conditional on CLK_FRAC_DIVIDER_POWER_OF_TWO_PS flag which was not added back to the rockchip clock driver. This broke the ltk050h3146w-a2 MIPI DSI display present on a PX30-based downstream board. Let's add the flag to the fractional divider flags so that the original and intended behavior is brought back to the rockchip clock drivers. Fixes: 82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag") Cc: stable@vger.kernel.org Cc: Quentin Schulz Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20220131163224.708002-1-quentin.schulz@theobroma-systems.com Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index b7be7e11b0df..bb8a844309bf 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -180,6 +180,7 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate, unsigned long *m, unsigned long *n) { + struct clk_fractional_divider *fd = to_clk_fd(hw); unsigned long p_rate, p_parent_rate; struct clk_hw *p_parent; @@ -190,6 +191,8 @@ static void rockchip_fractional_approximation(struct clk_hw *hw, *parent_rate = p_parent_rate; } + fd->flags |= CLK_FRAC_DIVIDER_POWER_OF_TWO_PS; + clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n); } -- cgit v1.2.3 From b77d8306d84f83d1da68028a68c91da9c867b6f6 Mon Sep 17 00:00:00 2001 From: Dirk Buchwalder Date: Thu, 10 Feb 2022 18:31:00 +0100 Subject: clk: qcom: ipq8074: Use floor ops for SDCC1 clock Use floor ops on SDCC1 APPS clock in order to round down selected clock frequency and avoid overclocking SD/eMMC cards. For example, currently HS200 cards were failling tuning as they were actually being clocked at 384MHz instead of 192MHz. This caused some boards to disable 1.8V I/O and force the eMMC into the standard HS mode (50MHz) and that appeared to work despite the eMMC being overclocked to 96Mhz in that case. There was a previous commit to use floor ops on SDCC clocks, but it looks to have only covered SDCC2 clock. Fixes: 9607f6224b39 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by: Dirk Buchwalder Signed-off-by: Robert Marko Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220210173100.505128-1-robimarko@gmail.com --- drivers/clk/qcom/gcc-ipq8074.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index b09d99343e09..541016db3c4b 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -1074,7 +1074,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .name = "sdcc1_apps_clk_src", .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, .num_parents = 4, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_floor_ops, }, }; -- cgit v1.2.3 From 809b482896742b30bcdaf2e2b2860acd1b0aa75d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 22 Feb 2022 20:45:16 -0800 Subject: clk: qcom: rpmhcc: add sc8280xp support to the RPMh clock controller The Qualcomm SC8280XP platform exposes 5 clocks through the RPMh clock controller. Add these, and the relates active-only variants, to the RPMh clock controller driver. Signed-off-by: Bjorn Andersson Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20220223044516.3776637-2-bjorn.andersson@linaro.org --- drivers/clk/qcom/clk-rpmh.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 74e57c84f60a..aed907982344 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -512,6 +512,23 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = { .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), }; +DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2); + +static struct clk_hw *sc8280xp_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_LN_BB_CLK3] = &sc8280xp_ln_bb_clk3.hw, + [RPMH_LN_BB_CLK3_A] = &sc8280xp_ln_bb_clk3_ao.hw, + [RPMH_IPA_CLK] = &sdm845_ipa.hw, + [RPMH_PKA_CLK] = &sm8350_pka.hw, + [RPMH_HWKM_CLK] = &sm8350_hwkm.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { + .clks = sc8280xp_rpmh_clocks, + .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), +}; + /* Resource name must match resource id present in cmd-db */ DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4); @@ -691,6 +708,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, + { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, -- cgit v1.2.3 From 703da2aed99c7882486defedb78d5e1cc7f47cf7 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:07 +0100 Subject: clk: nxp: Remove unused variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GCC warns: > ../drivers/clk/nxp/clk-lpc18xx-cgu.c: In function ‘lpc18xx_pll1_recalc_rate’: > ../drivers/clk/nxp/clk-lpc18xx-cgu.c:460:13: warning: variable ‘stat’ set but not used [-Wunused-but-set-variable] > 460 | u32 stat, ctrl; > | ^~~~ Get rid of the (apparently) useless read from the PLL1_STAT register and the declaration of stat. Reported-by: kernel test robot Fixes: b04e0b8fd5443 ("clk: add lpc18xx cgu clk driver") Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-2-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/nxp/clk-lpc18xx-cgu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c index 8b686da5577b..349eebf69ed9 100644 --- a/drivers/clk/nxp/clk-lpc18xx-cgu.c +++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c @@ -457,9 +457,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw, struct lpc18xx_pll *pll = to_lpc_pll(hw); u16 msel, nsel, psel; bool direct, fbsel; - u32 stat, ctrl; + u32 ctrl; - stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT); ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false; -- cgit v1.2.3 From 2eb3b3f0e87084a365321a61c9230fb16d94f1ec Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:08 +0100 Subject: clk: nxp: Declare mux table parameter as const u32 * MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit lpc18xx_fill_parent_names's "id" parameter isn't used for writing, so let's make it const. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-3-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/nxp/clk-lpc18xx-cgu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c index 349eebf69ed9..c23ac463ab0f 100644 --- a/drivers/clk/nxp/clk-lpc18xx-cgu.c +++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c @@ -522,7 +522,7 @@ static struct lpc18xx_cgu_pll_clk lpc18xx_cgu_src_clk_plls[] = { LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops), }; -static void lpc18xx_fill_parent_names(const char **parent, u32 *id, int size) +static void lpc18xx_fill_parent_names(const char **parent, const u32 *id, int size) { int i; -- cgit v1.2.3 From 891b7023010cc0d62d814619b1893745d7613f7f Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:09 +0100 Subject: clk: mux: Declare u32 *table parameter as const MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The elements of the table are never modified in clk-mux.c. To make this clear to clock drivers, declare the parameter as const u32 *table. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-4-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/clk-mux.c | 10 +++++----- include/linux/clk-provider.h | 12 ++++++------ 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 20582aae7a35..214045f6e989 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -40,7 +40,7 @@ static inline void clk_mux_writel(struct clk_mux *mux, u32 val) writel(val, mux->reg); } -int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, +int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, unsigned int val) { int num_parents = clk_hw_get_num_parents(hw); @@ -67,7 +67,7 @@ int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, } EXPORT_SYMBOL_GPL(clk_mux_val_to_index); -unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index) +unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index) { unsigned int val = index; @@ -152,7 +152,7 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, const struct clk_hw **parent_hws, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock) + u8 clk_mux_flags, const u32 *table, spinlock_t *lock) { struct clk_mux *mux; struct clk_hw *hw; @@ -218,7 +218,7 @@ struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node const struct clk_hw **parent_hws, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock) + u8 clk_mux_flags, const u32 *table, spinlock_t *lock) { struct clk_hw **ptr, *hw; @@ -244,7 +244,7 @@ EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock) + u8 clk_mux_flags, const u32 *table, spinlock_t *lock) { struct clk_hw *hw; diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..27be57528874 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -888,7 +888,7 @@ void clk_hw_unregister_divider(struct clk_hw *hw); struct clk_mux { struct clk_hw hw; void __iomem *reg; - u32 *table; + const u32 *table; u32 mask; u8 shift; u8 flags; @@ -913,18 +913,18 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, const struct clk_hw **parent_hws, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock); + u8 clk_mux_flags, const u32 *table, spinlock_t *lock); struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np, const char *name, u8 num_parents, const char * const *parent_names, const struct clk_hw **parent_hws, const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock); + u8 clk_mux_flags, const u32 *table, spinlock_t *lock); struct clk *clk_register_mux_table(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table, spinlock_t *lock); + u8 clk_mux_flags, const u32 *table, spinlock_t *lock); #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \ shift, width, clk_mux_flags, lock) \ @@ -962,9 +962,9 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name, (shift), BIT((width)) - 1, (clk_mux_flags), \ NULL, (lock)) -int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, +int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags, unsigned int val); -unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); +unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index); void clk_unregister_mux(struct clk *clk); void clk_hw_unregister_mux(struct clk_hw *hw); -- cgit v1.2.3 From 08edf70457b375d2f09aaee5ba07777046293d93 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:10 +0100 Subject: clk: hisilicon: Remove unnecessary cast of mux table to u32 * MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that clk_register_mux_table takes a const u32 *, we don't need the cast anymore. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-5-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/hisilicon/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 9361fba7cd4c..54d9fdc93599 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -162,7 +162,7 @@ int hisi_clk_register_mux(const struct hisi_mux_clock *clks, clks[i].num_parents, clks[i].flags, base + clks[i].offset, clks[i].shift, mask, clks[i].mux_flags, - (u32 *)clks[i].table, &hisi_clk_lock); + clks[i].table, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); -- cgit v1.2.3 From 8a8e164b1de0edaf94afd27a74b2e06ef1117060 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:11 +0100 Subject: clk: mmp: Declare mux tables as const u32[] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that clk_register_mux_table takes a const u32 *, we can declare the mux tables as const u32[]. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-6-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/mmp/clk-of-mmp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index 0839fb2049e9..50a780274ba0 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -317,9 +317,9 @@ static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"}; static DEFINE_SPINLOCK(gpu_lock); static const char * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"}; -static u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1040 }; +static const u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1040 }; static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"}; -static u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 }; +static const u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 }; static const char * const mmp3_gpu_bus_parent_names[] = {"pll1_4", "pll1_6", "pll1_2", "pll2_2"}; static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"}; -- cgit v1.2.3 From eac03cb010a9f5df37550b6082a6a8ba5e8b84dc Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:12 +0100 Subject: clk: qcom: Declare mux table as const u32[] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that clk_register_mux_table takes a const u32 *, we can declare the mux tables as const u32[]. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-7-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/qcom/kpss-xcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c index 4fec1f9142b8..88d4b33ac0cc 100644 --- a/drivers/clk/qcom/kpss-xcc.c +++ b/drivers/clk/qcom/kpss-xcc.c @@ -17,7 +17,7 @@ static const char *aux_parents[] = { "pxo", }; -static unsigned int aux_parent_map[] = { +static const u32 aux_parent_map[] = { 3, 0, }; -- cgit v1.2.3 From fa6ffe65cce5e596a411f6a878f9ad6588f3b8a7 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 5 Feb 2022 11:36:13 +0100 Subject: clk: pistachio: Declare mux table as const u32[] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that clk_register_mux_table takes a const u32 *, we can declare the mux table as const u32[]. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220205103613.1216218-8-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/pistachio/clk-pistachio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/pistachio/clk-pistachio.c b/drivers/clk/pistachio/clk-pistachio.c index 76f492c7e917..2a6d583237dc 100644 --- a/drivers/clk/pistachio/clk-pistachio.c +++ b/drivers/clk/pistachio/clk-pistachio.c @@ -154,7 +154,7 @@ static struct pistachio_pll pistachio_plls[] __initdata = { PNAME(mux_debug) = { "mips_pll_mux", "rpu_v_pll_mux", "rpu_l_pll_mux", "sys_pll_mux", "wifi_pll_mux", "bt_pll_mux" }; -static u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 }; +static const u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 }; static unsigned int pistachio_critical_clks_core[] __initdata = { CLK_MIPS -- cgit v1.2.3 From 75061a6ff49ba3482c6319ded0c26e6a526b0967 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 17 Feb 2022 14:05:53 -0800 Subject: clk: Mark 'all_lists' as const This list array doesn't change at runtime. Mark it const to move to RO memory. Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20220217220554.2711696-2-sboyd@kernel.org --- drivers/clk/clk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..16384e9437f5 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -37,7 +37,7 @@ static HLIST_HEAD(clk_root_list); static HLIST_HEAD(clk_orphan_list); static LIST_HEAD(clk_notifier_list); -static struct hlist_head *all_lists[] = { +static const struct hlist_head *all_lists[] = { &clk_root_list, &clk_orphan_list, NULL, @@ -4095,7 +4095,7 @@ static void clk_core_evict_parent_cache_subtree(struct clk_core *root, /* Remove this clk from all parent caches */ static void clk_core_evict_parent_cache(struct clk_core *core) { - struct hlist_head **lists; + const struct hlist_head **lists; struct clk_core *root; lockdep_assert_held(&prepare_lock); -- cgit v1.2.3 From 8df64183b8b71c751cf81c3d7655227fbea837b2 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 17 Feb 2022 14:05:54 -0800 Subject: clk: Mark clk_core_evict_parent_cache_subtree() 'target' const Clarify that the 'target' clk isn't being modified, instead it's being searched for. Mark it const so the function can't modify it. Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20220217220554.2711696-3-sboyd@kernel.org --- drivers/clk/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 16384e9437f5..d15997ea3930 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -4079,7 +4079,7 @@ static const struct clk_ops clk_nodrv_ops = { }; static void clk_core_evict_parent_cache_subtree(struct clk_core *root, - struct clk_core *target) + const struct clk_core *target) { int i; struct clk_core *child; -- cgit v1.2.3 From eccac77ede3946c90143447cdc785dc16aec4b24 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 27 Jan 2022 16:10:52 +0200 Subject: clk: imx7d: Remove audio_mclk_root_clk The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790), but according to the reference manual, there is no such gate. The CCGR121 belongs to ECSPI2 and it is not shared. Fixes: 8f6d8094b215b57 ("ARM: imx: add imx7d clk tree support") Reported-by: David Wolfe Signed-off-by: Abel Vesa Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20220127141052.1900174-2-abel.vesa@nxp.com --- drivers/clk/imx/clk-imx7d.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index c4e0f1c07192..3f6fd7ef2a68 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -849,7 +849,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) hws[IMX7D_WDOG4_ROOT_CLK] = imx_clk_hw_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); hws[IMX7D_KPP_ROOT_CLK] = imx_clk_hw_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0); hws[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_hw_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); - hws[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_hw_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); hws[IMX7D_WRCLK_ROOT_CLK] = imx_clk_hw_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); hws[IMX7D_USB_CTRL_CLK] = imx_clk_hw_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0); hws[IMX7D_USB_PHY1_CLK] = imx_clk_hw_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); -- cgit v1.2.3 From 135efc3a76d127691afaf1864e4ab627bf09d53d Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 28 Feb 2022 10:50:14 +0300 Subject: clk: imx: off by one in imx_lpcg_parse_clks_from_dt() The > needs to be >= to prevent an off by one access. Fixes: d5f1e6a2bb61 ("clk: imx: imx8qxp-lpcg: add parsing clocks from device tree") Reported-by: kernel test robot Signed-off-by: Dan Carpenter Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220228075014.GD13685@kili Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index b23758083ce5..5e31a6a24b3a 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -248,7 +248,7 @@ static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev, for (i = 0; i < count; i++) { idx = bit_offset[i] / 4; - if (idx > IMX_LPCG_MAX_CLKS) { + if (idx >= IMX_LPCG_MAX_CLKS) { dev_warn(&pdev->dev, "invalid bit offset of clock %d\n", i); ret = -EINVAL; -- cgit v1.2.3 From 11994196178d9038d659c2b9468d7c219b708a37 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 28 Feb 2022 10:09:06 +0800 Subject: clk: imx: add i.MX93 composite clk i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by: Abel Vesa Reviewed-by: Stephen Boyd Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220228020908.2810346-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-composite-93.c | 93 ++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 9 ++++ 3 files changed, 103 insertions(+) create mode 100644 drivers/clk/imx/clk-composite-93.c (limited to 'drivers/clk') diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index aa8f5204d7e1..36c04922d789 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -4,6 +4,7 @@ mxc-clk-objs += clk.o mxc-clk-objs += clk-busy.o mxc-clk-objs += clk-composite-7ulp.o mxc-clk-objs += clk-composite-8m.o +mxc-clk-objs += clk-composite-93.o mxc-clk-objs += clk-cpu.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c new file mode 100644 index 000000000000..b44619aa5ca5 --- /dev/null +++ b/drivers/clk/imx/clk-composite-93.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + * Peng Fan + */ + +#include +#include +#include +#include +#include + +#include "clk.h" + +#define CCM_DIV_SHIFT 0 +#define CCM_DIV_WIDTH 8 +#define CCM_MUX_SHIFT 8 +#define CCM_MUX_MASK 3 +#define CCM_OFF_SHIFT 24 + +#define AUTHEN_OFFSET 0x30 +#define TZ_NS_SHIFT 9 +#define TZ_NS_MASK BIT(9) + +struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; + struct clk_hw *div_hw, *gate_hw; + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + bool clk_ro = false; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux_hw = &mux->hw; + mux->reg = reg; + mux->shift = CCM_MUX_SHIFT; + mux->mask = CCM_MUX_MASK; + mux->lock = &imx_ccm_lock; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div_hw = &div->hw; + div->reg = reg; + div->shift = CCM_DIV_SHIFT; + div->width = CCM_DIV_WIDTH; + div->lock = &imx_ccm_lock; + div->flags = CLK_DIVIDER_ROUND_CLOSEST; + + if (!(readl(reg + AUTHEN_OFFSET) & TZ_NS_MASK)) + clk_ro = true; + + if (clk_ro) { + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ro_ops, div_hw, + &clk_divider_ro_ops, NULL, NULL, flags); + } else { + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = CCM_OFF_SHIFT; + gate->lock = &imx_ccm_lock; + gate->flags = CLK_GATE_SET_TO_DISABLE; + + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ops, div_hw, + &clk_divider_ops, gate_hw, + &clk_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); + } + + if (IS_ERR(hw)) + goto fail; + + return hw; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(hw); +} +EXPORT_SYMBOL_GPL(imx93_clk_composite_flags); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 7d220a01de1f..63eb7c53b123 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -419,6 +419,15 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, IMX_COMPOSITE_FW_MANAGED, \ IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE) +struct clk_hw *imx93_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, + void __iomem *reg, + unsigned long flags); +#define imx93_clk_composite(name, parent_names, num_parents, reg) \ + imx93_clk_composite_flags(name, parent_names, num_parents, reg, \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, -- cgit v1.2.3 From 1b26cb8a77a49d8f8b5b723ef1db4cd6d2434dfc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 28 Feb 2022 10:09:07 +0800 Subject: clk: imx: support fracn gppll This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of feedback divider dynamically. This fracn gppll is used in i.MX93. Reviewed-by: Abel Vesa Reviewed-by: Sascha Hauer Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-fracn-gppll.c | 323 ++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 21 +++ 3 files changed, 345 insertions(+) create mode 100644 drivers/clk/imx/clk-fracn-gppll.c (limited to 'drivers/clk') diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 36c04922d789..60c8a4bb7574 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -5,6 +5,7 @@ mxc-clk-objs += clk-busy.o mxc-clk-objs += clk-composite-7ulp.o mxc-clk-objs += clk-composite-8m.o mxc-clk-objs += clk-composite-93.o +mxc-clk-objs += clk-fracn-gppll.o mxc-clk-objs += clk-cpu.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c new file mode 100644 index 000000000000..71c102d950ab --- /dev/null +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define PLL_CTRL 0x0 +#define CLKMUX_BYPASS BIT(2) +#define CLKMUX_EN BIT(1) +#define POWERUP_MASK BIT(0) + +#define PLL_ANA_PRG 0x10 +#define PLL_SPREAD_SPECTRUM 0x30 + +#define PLL_NUMERATOR 0x40 +#define PLL_MFN_MASK GENMASK(31, 2) + +#define PLL_DENOMINATOR 0x50 +#define PLL_MFD_MASK GENMASK(29, 0) + +#define PLL_DIV 0x60 +#define PLL_MFI_MASK GENMASK(24, 16) +#define PLL_RDIV_MASK GENMASK(15, 13) +#define PLL_ODIV_MASK GENMASK(7, 0) + +#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10) + +#define PLL_STATUS 0xF0 +#define LOCK_STATUS BIT(0) + +#define DFS_STATUS 0xF4 + +#define LOCK_TIMEOUT_US 200 + +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ + { \ + .rate = (_rate), \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .mfd = (_mfd), \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + } + +struct clk_fracn_gppll { + struct clk_hw hw; + void __iomem *base; + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; +}; + +/* + * Fvco = Fref * (MFI + MFN / MFD) + * Fout = Fvco / (rdiv * odiv) + */ +static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { + PLL_FRACN_GP(650000000U, 81, 0, 0, 0, 3), + PLL_FRACN_GP(594000000U, 198, 0, 0, 0, 8), + PLL_FRACN_GP(560000000U, 70, 0, 0, 0, 3), + PLL_FRACN_GP(400000000U, 50, 0, 0, 0, 3), + PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) +}; + +struct imx_fracn_gppll_clk imx_fracn_gppll = { + .rate_table = fracn_tbl, + .rate_count = ARRAY_SIZE(fracn_tbl), +}; +EXPORT_SYMBOL_GPL(imx_fracn_gppll); + +static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw) +{ + return container_of(hw, struct clk_fracn_gppll, hw); +} + +static const struct imx_fracn_gppll_rate_table * +imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate) +{ + const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; + int i; + + for (i = 0; i < pll->rate_count; i++) + if (rate == rate_table[i].rate) + return &rate_table[i]; + + return NULL; +} + +static long clk_fracn_gppll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); + const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; + int i; + + /* Assuming rate_table is in descending order */ + for (i = 0; i < pll->rate_count; i++) + if (rate >= rate_table[i].rate) + return rate_table[i].rate; + + /* return minimum supported value */ + return rate_table[pll->rate_count - 1].rate; +} + +static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); + const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; + u32 pll_numerator, pll_denominator, pll_div; + u32 mfi, mfn, mfd, rdiv, odiv; + u64 fvco = parent_rate; + long rate = 0; + int i; + + pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR); + mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator); + + pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR); + mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator); + + pll_div = readl_relaxed(pll->base + PLL_DIV); + mfi = FIELD_GET(PLL_MFI_MASK, pll_div); + + rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); + rdiv = rdiv + 1; + odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); + switch (odiv) { + case 0: + odiv = 2; + break; + case 1: + odiv = 3; + break; + default: + break; + } + + /* + * Sometimes, the recalculated rate has deviation due to + * the frac part. So find the accurate pll rate from the table + * first, if no match rate in the table, use the rate calculated + * from the equation below. + */ + for (i = 0; i < pll->rate_count; i++) { + if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi && + rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv && + rate_table[i].odiv == odiv) + rate = rate_table[i].rate; + } + + if (rate) + return (unsigned long)rate; + + /* Fvco = Fref * (MFI + MFN / MFD) */ + fvco = fvco * mfi * mfd + fvco * mfn; + do_div(fvco, mfd * rdiv * odiv); + + return (unsigned long)fvco; +} + +static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll) +{ + u32 val; + + return readl_poll_timeout(pll->base + PLL_STATUS, val, + val & LOCK_STATUS, 0, LOCK_TIMEOUT_US); +} + +static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); + const struct imx_fracn_gppll_rate_table *rate; + u32 tmp, pll_div, ana_mfn; + int ret; + + rate = imx_get_pll_settings(pll, drate); + + /* Disable output */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~CLKMUX_EN; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Power Down */ + tmp &= ~POWERUP_MASK; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Disable BYPASS */ + tmp &= ~CLKMUX_BYPASS; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | + FIELD_PREP(PLL_MFI_MASK, rate->mfi); + writel_relaxed(pll_div, pll->base + PLL_DIV); + writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR); + writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR); + + /* Wait for 5us according to fracn mode pll doc */ + udelay(5); + + /* Enable Powerup */ + tmp |= POWERUP_MASK; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Wait Lock */ + ret = clk_fracn_gppll_wait_lock(pll); + if (ret) + return ret; + + /* Enable output */ + tmp |= CLKMUX_EN; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + ana_mfn = readl_relaxed(pll->base + PLL_STATUS); + ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn); + + WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n"); + + return 0; +} + +static int clk_fracn_gppll_prepare(struct clk_hw *hw) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); + u32 val; + int ret; + + val = readl_relaxed(pll->base + PLL_CTRL); + if (val & POWERUP_MASK) + return 0; + + val |= CLKMUX_BYPASS; + writel_relaxed(val, pll->base + PLL_CTRL); + + val |= POWERUP_MASK; + writel_relaxed(val, pll->base + PLL_CTRL); + + val |= CLKMUX_EN; + writel_relaxed(val, pll->base + PLL_CTRL); + + ret = clk_fracn_gppll_wait_lock(pll); + if (ret) + return ret; + + val &= ~CLKMUX_BYPASS; + writel_relaxed(val, pll->base + PLL_CTRL); + + return 0; +} + +static int clk_fracn_gppll_is_prepared(struct clk_hw *hw) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CTRL); + + return (val & POWERUP_MASK) ? 1 : 0; +} + +static void clk_fracn_gppll_unprepare(struct clk_hw *hw) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); + u32 val; + + val = readl_relaxed(pll->base + PLL_CTRL); + val &= ~POWERUP_MASK; + writel_relaxed(val, pll->base + PLL_CTRL); +} + +static const struct clk_ops clk_fracn_gppll_ops = { + .prepare = clk_fracn_gppll_prepare, + .unprepare = clk_fracn_gppll_unprepare, + .is_prepared = clk_fracn_gppll_is_prepared, + .recalc_rate = clk_fracn_gppll_recalc_rate, + .round_rate = clk_fracn_gppll_round_rate, + .set_rate = clk_fracn_gppll_set_rate, +}; + +struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk) +{ + struct clk_fracn_gppll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = pll_clk->flags; + init.parent_names = &parent_name; + init.num_parents = 1; + init.ops = &clk_fracn_gppll_ops; + + pll->base = base; + pll->hw.init = &init; + pll->rate_table = pll_clk->rate_table; + pll->rate_count = pll_clk->rate_count; + + hw = &pll->hw; + + ret = clk_hw_register(NULL, hw); + if (ret) { + pr_err("%s: failed to register pll %s %d\n", __func__, name, ret); + kfree(pll); + return ERR_PTR(ret); + } + + return hw; +} +EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 63eb7c53b123..a7cbbcd1a3f4 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -72,6 +72,27 @@ extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; +/* NOTE: Rate table should be kept sorted in descending order. */ +struct imx_fracn_gppll_rate_table { + unsigned int rate; + unsigned int mfi; + unsigned int mfn; + unsigned int mfd; + unsigned int rdiv; + unsigned int odiv; +}; + +struct imx_fracn_gppll_clk { + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; + int flags; +}; + +struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); + +extern struct imx_fracn_gppll_clk imx_fracn_gppll; + #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) -- cgit v1.2.3 From 24defbe194b650218680fcd9dec8cd103537b531 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 28 Feb 2022 10:09:08 +0800 Subject: clk: imx: add i.MX93 clk Add i.MX93 clk driver. i.MX93 clk hardware design is different compared with i.MX8M. It supports 4 sources for each clk root and the sources are separated into a few groups, low speed/fast io/audio and etc. Reviewed-by: Abel Vesa Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220228020908.2810346-6-peng.fan@oss.nxp.com [abel.vesa@nxp.com: Added missing module license and description] Signed-off-by: Abel Vesa --- drivers/clk/imx/Kconfig | 6 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx93.c | 341 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/clk/imx/clk-imx93.c (limited to 'drivers/clk') diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index 45641b8bdc50..cc464a42d646 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -106,6 +106,12 @@ config CLK_IMX8ULP help Build the driver for i.MX8ULP CCM Clock Driver +config CLK_IMX93 + tristate "IMX93 CCM Clock Driver" + depends on ARCH_MXC || COMPILE_TEST + help + Build the driver for i.MX93 CCM Clock Driver + config CLK_IMXRT1050 tristate "IMXRT1050 CCM Clock Driver" depends on SOC_IMXRT diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 60c8a4bb7574..88b9b9285d22 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o +obj-$(CONFIG_CLK_IMX93) += clk-imx93.o + obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \ clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o \ diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c new file mode 100644 index 000000000000..edcc87661d1f --- /dev/null +++ b/drivers/clk/imx/clk-imx93.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +enum clk_sel { + LOW_SPEED_IO_SEL, + NON_IO_SEL, + FAST_SEL, + AUDIO_SEL, + VIDEO_SEL, + TPM_SEL, + CKO1_SEL, + CKO2_SEL, + MISC_SEL, + MAX_SEL +}; + +static const char *parent_names[MAX_SEL][4] = { + {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, + {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, + {"osc_24m", "sys_pll_pfd0", "sys_pll_pfd1", "sys_pll_pfd2"}, + {"osc_24m", "audio_pll", "video_pll", "clk_ext1"}, + {"osc_24m", "audio_pll", "video_pll", "sys_pll_pfd0"}, + {"osc_24m", "sys_pll_pfd0", "audio_pll", "clk_ext1"}, + {"osc_24m", "sys_pll_pfd0", "sys_pll_pfd1", "audio_pll"}, + {"osc_24m", "sys_pll_pfd0", "sys_pll_pfd1", "video_pll"}, + {"osc_24m", "audio_pll", "video_pll", "sys_pll_pfd2"}, +}; + +static const struct imx93_clk_root { + u32 clk; + char *name; + u32 off; + enum clk_sel sel; + unsigned long flags; +} root_array[] = { + /* a55/m33/bus critical clk for system run */ + { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_A55, "a55_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPIT1, "lpit1_root", 0x0600, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPIT2, "lpit2_root", 0x0680, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_TPM1, "tpm1_root", 0x0800, TPM_SEL, }, + { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, + { IMX93_CLK_TPM3, "tpm3_root", 0x0900, TPM_SEL, }, + { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, }, + { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, }, + { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, }, + { IMX93_CLK_FLEXSPI1, "flexspi1_root", 0x0b00, FAST_SEL, }, + { IMX93_CLK_CAN1, "can1_root", 0x0b80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_CAN2, "can2_root", 0x0c00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART1, "lpuart1_root", 0x0c80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART2, "lpuart2_root", 0x0d00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART3, "lpuart3_root", 0x0d80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART4, "lpuart4_root", 0x0e00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART5, "lpuart5_root", 0x0e80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART6, "lpuart6_root", 0x0f00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART7, "lpuart7_root", 0x0f80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART8, "lpuart8_root", 0x1000, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C1, "lpi2c1_root", 0x1080, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C2, "lpi2c2_root", 0x1100, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C3, "lpi2c3_root", 0x1180, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C4, "lpi2c4_root", 0x1200, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C5, "lpi2c5_root", 0x1280, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C6, "lpi2c6_root", 0x1300, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C7, "lpi2c7_root", 0x1380, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C8, "lpi2c8_root", 0x1400, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI1, "lpspi1_root", 0x1480, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI2, "lpspi2_root", 0x1500, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI3, "lpspi3_root", 0x1580, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI4, "lpspi4_root", 0x1600, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI5, "lpspi5_root", 0x1680, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI6, "lpspi6_root", 0x1700, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI7, "lpspi7_root", 0x1780, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI8, "lpspi8_root", 0x1800, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C1, "i3c1_root", 0x1880, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C2, "i3c2_root", 0x1900, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_USDHC1, "usdhc1_root", 0x1980, FAST_SEL, }, + { IMX93_CLK_USDHC2, "usdhc2_root", 0x1a00, FAST_SEL, }, + { IMX93_CLK_USDHC3, "usdhc3_root", 0x1a80, FAST_SEL, }, + { IMX93_CLK_SAI1, "sai1_root", 0x1b00, AUDIO_SEL, }, + { IMX93_CLK_SAI2, "sai2_root", 0x1b80, AUDIO_SEL, }, + { IMX93_CLK_SAI3, "sai3_root", 0x1c00, AUDIO_SEL, }, + { IMX93_CLK_CCM_CKO1, "ccm_cko1_root", 0x1c80, CKO1_SEL, }, + { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, }, + { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, }, + { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, }, + { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, + { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, }, + { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, }, + { IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, }, + { IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, }, + { IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, }, + { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, }, + { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, }, + { IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, }, + { IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_TSTMR2, "tstmr2_root", 0x2880, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_MQS1, "mqs1_root", 0x2900, AUDIO_SEL, }, + { IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, }, + { IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, }, + { IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, }, + { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, }, + { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, }, + { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, } +}; + +static const struct imx93_clk_ccgr { + u32 clk; + char *name; + char *parent_name; + u32 off; + unsigned long flags; +} ccgr_array[] = { + { IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, }, + /* M33 critical clk for system run */ + { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, + { IMX93_CLK_ADC1_GATE, "adc1", "osc_24m", 0x82c0, }, + { IMX93_CLK_WDOG1_GATE, "wdog1", "osc_24m", 0x8300, }, + { IMX93_CLK_WDOG2_GATE, "wdog2", "osc_24m", 0x8340, }, + { IMX93_CLK_WDOG3_GATE, "wdog3", "osc_24m", 0x8380, }, + { IMX93_CLK_WDOG4_GATE, "wdog4", "osc_24m", 0x83c0, }, + { IMX93_CLK_WDOG5_GATE, "wdog5", "osc_24m", 0x8400, }, + { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, + { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, + { IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, }, + { IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, }, + { IMX93_CLK_EDMA1_GATE, "edma1", "wakeup_axi_root", 0x8540, }, + { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, + { IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, }, + { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, + { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, + { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, + { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, + { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, + { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, + { IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, }, + { IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, }, + { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, + { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, + { IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, }, + { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, + { IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, }, + { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, + { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, + { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, + { IMX93_CLK_CAN1_GATE, "can1", "can1_root", 0x8c80, }, + { IMX93_CLK_CAN2_GATE, "can2", "can2_root", 0x8cc0, }, + { IMX93_CLK_LPUART1_GATE, "lpuart1", "lpuart1_root", 0x8d00, }, + { IMX93_CLK_LPUART2_GATE, "lpuart2", "lpuart2_root", 0x8d40, }, + { IMX93_CLK_LPUART3_GATE, "lpuart3", "lpuart3_root", 0x8d80, }, + { IMX93_CLK_LPUART4_GATE, "lpuart4", "lpuart4_root", 0x8dc0, }, + { IMX93_CLK_LPUART5_GATE, "lpuart5", "lpuart5_root", 0x8e00, }, + { IMX93_CLK_LPUART6_GATE, "lpuart6", "lpuart6_root", 0x8e40, }, + { IMX93_CLK_LPUART7_GATE, "lpuart7", "lpuart7_root", 0x8e80, }, + { IMX93_CLK_LPUART8_GATE, "lpuart8", "lpuart8_root", 0x8ec0, }, + { IMX93_CLK_LPI2C1_GATE, "lpi2c1", "lpi2c1_root", 0x8f00, }, + { IMX93_CLK_LPI2C2_GATE, "lpi2c2", "lpi2c2_root", 0x8f40, }, + { IMX93_CLK_LPI2C3_GATE, "lpi2c3", "lpi2c3_root", 0x8f80, }, + { IMX93_CLK_LPI2C4_GATE, "lpi2c4", "lpi2c4_root", 0x8fc0, }, + { IMX93_CLK_LPI2C5_GATE, "lpi2c5", "lpi2c5_root", 0x9000, }, + { IMX93_CLK_LPI2C6_GATE, "lpi2c6", "lpi2c6_root", 0x9040, }, + { IMX93_CLK_LPI2C7_GATE, "lpi2c7", "lpi2c7_root", 0x9080, }, + { IMX93_CLK_LPI2C8_GATE, "lpi2c8", "lpi2c8_root", 0x90c0, }, + { IMX93_CLK_LPSPI1_GATE, "lpspi1", "lpspi1_root", 0x9100, }, + { IMX93_CLK_LPSPI2_GATE, "lpspi2", "lpspi2_root", 0x9140, }, + { IMX93_CLK_LPSPI3_GATE, "lpspi3", "lpspi3_root", 0x9180, }, + { IMX93_CLK_LPSPI4_GATE, "lpspi4", "lpspi4_root", 0x91c0, }, + { IMX93_CLK_LPSPI5_GATE, "lpspi5", "lpspi5_root", 0x9200, }, + { IMX93_CLK_LPSPI6_GATE, "lpspi6", "lpspi6_root", 0x9240, }, + { IMX93_CLK_LPSPI7_GATE, "lpspi7", "lpspi7_root", 0x9280, }, + { IMX93_CLK_LPSPI8_GATE, "lpspi8", "lpspi8_root", 0x92c0, }, + { IMX93_CLK_I3C1_GATE, "i3c1", "i3c1_root", 0x9300, }, + { IMX93_CLK_I3C2_GATE, "i3c2", "i3c2_root", 0x9340, }, + { IMX93_CLK_USDHC1_GATE, "usdhc1", "usdhc1_root", 0x9380, }, + { IMX93_CLK_USDHC2_GATE, "usdhc2", "usdhc2_root", 0x93c0, }, + { IMX93_CLK_USDHC3_GATE, "usdhc3", "usdhc3_root", 0x9400, }, + { IMX93_CLK_SAI1_GATE, "sai1", "sai1_root", 0x9440, }, + { IMX93_CLK_SAI2_GATE, "sai2", "sai2_root", 0x9480, }, + { IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, }, + { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, }, + { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, }, + { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, }, + { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, + { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, + { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, + { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_apb_root", 0x9700, }, + { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, + { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, + { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, }, + { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, }, + { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, + { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, + { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, + { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, + { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, }, + { IMX93_CLK_ENET1_GATE, "enet1", "enet_root", 0x9e00, }, + { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, + { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, }, + { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, + { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, + { IMX93_CLK_TMC_GATE, "tmc", "osc_24m", 0x9f40, }, + { IMX93_CLK_PMRO_GATE, "pmro", "osc_24m", 0x9f80, } +}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **clks; + +static int imx93_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct imx93_clk_root *root; + const struct imx93_clk_ccgr *ccgr; + void __iomem *base = NULL; + int i, ret; + + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, + IMX93_CLK_END), GFP_KERNEL); + if (!clk_hw_data) + return -ENOMEM; + + clk_hw_data->num = IMX93_CLK_END; + clks = clk_hw_data->hws; + + clks[IMX93_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + clks[IMX93_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); + clks[IMX93_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); + clks[IMX93_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); + + clks[IMX93_CLK_SYS_PLL_PFD0] = imx_clk_hw_fixed("sys_pll_pfd0", 1000000000); + clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2", + "sys_pll_pfd0", 1, 2); + clks[IMX93_CLK_SYS_PLL_PFD1] = imx_clk_hw_fixed("sys_pll_pfd1", 800000000); + clks[IMX93_CLK_SYS_PLL_PFD1_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd1_div2", + "sys_pll_pfd1", 1, 2); + clks[IMX93_CLK_SYS_PLL_PFD2] = imx_clk_hw_fixed("sys_pll_pfd2", 625000000); + clks[IMX93_CLK_SYS_PLL_PFD2_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd2_div2", + "sys_pll_pfd2", 1, 2); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop"); + base = of_iomap(np, 0); + of_node_put(np); + if (WARN_ON(!base)) + return -ENOMEM; + + clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", base + 0x1200, + &imx_fracn_gppll); + clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", base + 0x1400, + &imx_fracn_gppll); + + np = dev->of_node; + base = devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + + for (i = 0; i < ARRAY_SIZE(root_array); i++) { + root = &root_array[i]; + clks[root->clk] = imx93_clk_composite_flags(root->name, + parent_names[root->sel], + 4, base + root->off, + root->flags); + } + + for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) { + ccgr = &ccgr_array[i]; + clks[ccgr->clk] = imx_clk_hw_gate4_flags(ccgr->name, + ccgr->parent_name, + base + ccgr->off, 0, + ccgr->flags); + } + + imx_check_clk_hws(clks, IMX93_CLK_END); + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + dev_err(dev, "failed to register clks for i.MX93\n"); + goto unregister_hws; + } + + return 0; + +unregister_hws: + imx_unregister_hw_clocks(clks, IMX93_CLK_END); + + return ret; +} + +static const struct of_device_id imx93_clk_of_match[] = { + { .compatible = "fsl,imx93-ccm" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx93_clk_of_match); + +static struct platform_driver imx93_clk_driver = { + .probe = imx93_clocks_probe, + .driver = { + .name = "imx93-ccm", + .suppress_bind_attrs = true, + .of_match_table = of_match_ptr(imx93_clk_of_match), + }, +}; +module_platform_driver(imx93_clk_driver); + +MODULE_DESCRIPTION("NXP i.MX93 clock driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From d25cbd3e392730f459f1fbf5f959c16b460a59ca Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 25 Feb 2022 16:17:31 +0800 Subject: clk: imx8mm: remove SYS PLL 1/2 clock gates Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220225081733.2294166-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mm.c | 49 +++++++++++++++----------------------------- 1 file changed, 16 insertions(+), 33 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index e92621fa8b9c..e8cbe181ec06 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -366,45 +366,28 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); /* SYS PLL1 fixed output */ - hws[IMX8MM_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27); - hws[IMX8MM_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25); - hws[IMX8MM_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23); - hws[IMX8MM_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21); - hws[IMX8MM_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19); - hws[IMX8MM_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17); - hws[IMX8MM_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15); - hws[IMX8MM_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13); hws[IMX8MM_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20); - hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10); - hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8); - hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6); - hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5); - hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4); - hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3); - hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2); + hws[IMX8MM_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MM_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MM_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MM_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MM_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MM_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MM_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MM_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); hws[IMX8MM_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); /* SYS PLL2 fixed output */ - hws[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27); - hws[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25); - hws[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23); - hws[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21); - hws[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19); - hws[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17); - hws[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15); - hws[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13); hws[IMX8MM_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - - hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20); - hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10); - hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8); - hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6); - hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5); - hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4); - hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3); - hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2); + hws[IMX8MM_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MM_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MM_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MM_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MM_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MM_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MM_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); -- cgit v1.2.3 From 38ce00adc16319544c8c56edd36324d2c1b98a50 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 25 Feb 2022 16:17:32 +0800 Subject: clk: imx8mn: remove SYS PLL 1/2 clock gates Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220225081733.2294166-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mn.c | 50 ++++++++++++++------------------------------ 1 file changed, 16 insertions(+), 34 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 021355a24708..92fcbab4f5be 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -364,45 +364,27 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); /* SYS PLL1 fixed output */ - hws[IMX8MN_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27); - hws[IMX8MN_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25); - hws[IMX8MN_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23); - hws[IMX8MN_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21); - hws[IMX8MN_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19); - hws[IMX8MN_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17); - hws[IMX8MN_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15); - hws[IMX8MN_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13); hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11); - - hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20); - hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10); - hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8); - hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6); - hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5); - hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4); - hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3); - hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2); + hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); /* SYS PLL2 fixed output */ - hws[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27); - hws[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25); - hws[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23); - hws[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21); - hws[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19); - hws[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17); - hws[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15); - hws[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13); hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11); - - hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20); - hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10); - hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8); - hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6); - hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5); - hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4); - hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3); - hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2); + hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); -- cgit v1.2.3 From d097cc045b64948ca3048ced4a43cc74eaf641a5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 25 Feb 2022 16:17:33 +0800 Subject: clk: imx8mp: remove SYS PLL 1/2 clock gates Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220225081733.2294166-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx8mp.c | 48 +++++++++++++++----------------------------- 1 file changed, 16 insertions(+), 32 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index f23b92906d3b..18f5b7c3ca9d 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -480,44 +480,28 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11); hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11); - hws[IMX8MP_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1_bypass", anatop_base + 0x94, 27); - hws[IMX8MP_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1_bypass", anatop_base + 0x94, 25); - hws[IMX8MP_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1_bypass", anatop_base + 0x94, 23); - hws[IMX8MP_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1_bypass", anatop_base + 0x94, 21); - hws[IMX8MP_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1_bypass", anatop_base + 0x94, 19); - hws[IMX8MP_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1_bypass", anatop_base + 0x94, 17); - hws[IMX8MP_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1_bypass", anatop_base + 0x94, 15); - hws[IMX8MP_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1_bypass", anatop_base + 0x94, 13); hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11); - hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20); - hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10); - hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8); - hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6); - hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5); - hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4); - hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3); - hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2); + hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MP_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MP_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MP_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MP_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MP_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MP_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MP_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); hws[IMX8MP_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); - hws[IMX8MP_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2_bypass", anatop_base + 0x104, 27); - hws[IMX8MP_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2_bypass", anatop_base + 0x104, 25); - hws[IMX8MP_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2_bypass", anatop_base + 0x104, 23); - hws[IMX8MP_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2_bypass", anatop_base + 0x104, 21); - hws[IMX8MP_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2_bypass", anatop_base + 0x104, 19); - hws[IMX8MP_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2_bypass", anatop_base + 0x104, 17); - hws[IMX8MP_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2_bypass", anatop_base + 0x104, 15); - hws[IMX8MP_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2_bypass", anatop_base + 0x104, 13); hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11); - hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20); - hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10); - hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8); - hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6); - hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5); - hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4); - hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3); - hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2); + hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MP_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MP_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MP_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MP_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000); -- cgit v1.2.3 From 485b4ff57c2777c15bfe2e6e6a204200b040e131 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:49 +0100 Subject: clk: imx: pll14xx: Use register defines consistently The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CTL to DIV_CTL0 because that's the name in the reference manual. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-2-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 49 ++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 24 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 2b5ed86b9dbb..cae64d750672 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -15,7 +15,8 @@ #include "clk.h" #define GNRL_CTL 0x0 -#define DIV_CTL 0x4 +#define DIV_CTL0 0x4 +#define DIV_CTL1 0x8 #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -122,7 +123,7 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u32 mdiv, pdiv, sdiv, pll_div; u64 fvco = parent_rate; - pll_div = readl_relaxed(pll->base + 4); + pll_div = readl_relaxed(pll->base + DIV_CTL0); mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; @@ -141,8 +142,8 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, short int kdiv; u64 fvco = parent_rate; - pll_div_ctl0 = readl_relaxed(pll->base + 4); - pll_div_ctl1 = readl_relaxed(pll->base + 8); + pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; @@ -172,7 +173,7 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { u32 val; - return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0, + return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0, LOCK_TIMEOUT_US); } @@ -191,32 +192,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + 4); + tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel_relaxed(tmp, pll->base + 4); + writel_relaxed(tmp, pll->base + DIV_CTL0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl_relaxed(pll->base); + tmp = readl_relaxed(pll->base + GNRL_CTL); tmp |= LOCK_SEL_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable RST */ tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base); + writel(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel_relaxed(div_val, pll->base + 0x4); + writel_relaxed(div_val, pll->base + DIV_CTL0); /* * According to SPEC, t3 - t2 need to be greater than @@ -228,7 +229,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -237,7 +238,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); return 0; } @@ -257,32 +258,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + 4); + tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~(SDIV_MASK) << SDIV_SHIFT; tmp |= rate->sdiv << SDIV_SHIFT; - writel_relaxed(tmp, pll->base + 4); + writel_relaxed(tmp, pll->base + DIV_CTL0); tmp = rate->kdiv << KDIV_SHIFT; - writel_relaxed(tmp, pll->base + 8); + writel_relaxed(tmp, pll->base + DIV_CTL1); return 0; } /* Enable RST */ - tmp = readl_relaxed(pll->base); + tmp = readl_relaxed(pll->base + GNRL_CTL); tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | (rate->sdiv << SDIV_SHIFT); - writel_relaxed(div_val, pll->base + 0x4); - writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8); + writel_relaxed(div_val, pll->base + DIV_CTL0); + writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than @@ -294,7 +295,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -303,7 +304,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base); + writel_relaxed(tmp, pll->base + GNRL_CTL); return 0; } -- cgit v1.2.3 From d77461a616b659bd88dc153e3a86dba5bf78aa8a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:50 +0100 Subject: clk: imx: pll14xx: Drop wrong shifting The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK already contains the shifted value, so shifting it again is wrong. No functional change though as SDIV_SHIFT is zero. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-3-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index cae64d750672..b295d8a04900 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -195,7 +195,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { - tmp &= ~(SDIV_MASK) << SDIV_SHIFT; + tmp &= ~SDIV_MASK; tmp |= rate->sdiv << SDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL0); @@ -261,7 +261,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, tmp = readl_relaxed(pll->base + DIV_CTL0); if (!clk_pll14xx_mp_change(rate, tmp)) { - tmp &= ~(SDIV_MASK) << SDIV_SHIFT; + tmp &= ~SDIV_MASK; tmp |= rate->sdiv << SDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL0); -- cgit v1.2.3 From 58f4980ccbecf633df1fcb113e2a9f04842eccc6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:51 +0100 Subject: clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP Linux has these marvelous FIELD_GET/FIELD_PREP macros for easy access to bitfields in registers. Use them and remove the now unused *_SHIFT defines. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-4-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index b295d8a04900..fabb380b8730 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -3,6 +3,7 @@ * Copyright 2017-2018 NXP. */ +#include #include #include #include @@ -22,13 +23,9 @@ #define CLKE_MASK BIT(11) #define RST_MASK BIT(9) #define BYPASS_MASK BIT(4) -#define MDIV_SHIFT 12 #define MDIV_MASK GENMASK(21, 12) -#define PDIV_SHIFT 4 #define PDIV_MASK GENMASK(9, 4) -#define SDIV_SHIFT 0 #define SDIV_MASK GENMASK(2, 0) -#define KDIV_SHIFT 0 #define KDIV_MASK GENMASK(15, 0) #define LOCK_TIMEOUT_US 10000 @@ -124,9 +121,9 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u64 fvco = parent_rate; pll_div = readl_relaxed(pll->base + DIV_CTL0); - mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; - pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; - sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; + mdiv = FIELD_GET(MDIV_MASK, pll_div); + pdiv = FIELD_GET(PDIV_MASK, pll_div); + sdiv = FIELD_GET(SDIV_MASK, pll_div); fvco *= mdiv; do_div(fvco, pdiv << sdiv); @@ -144,10 +141,10 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); - mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; - pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; - sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; - kdiv = pll_div_ctl1 & KDIV_MASK; + mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); + pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); + sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); + kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ fvco *= (mdiv * 65536 + kdiv); @@ -163,8 +160,8 @@ static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *ra { u32 old_mdiv, old_pdiv; - old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; - old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; + old_mdiv = FIELD_GET(MDIV_MASK, pll_div); + old_pdiv = FIELD_GET(PDIV_MASK, pll_div); return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; } @@ -196,7 +193,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= rate->sdiv << SDIV_SHIFT; + tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(tmp, pll->base + DIV_CTL0); return 0; @@ -215,8 +212,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel(tmp, pll->base + GNRL_CTL); - div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | - (rate->sdiv << SDIV_SHIFT); + div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(div_val, pll->base + DIV_CTL0); /* @@ -262,10 +259,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= rate->sdiv << SDIV_SHIFT; + tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(tmp, pll->base + DIV_CTL0); - tmp = rate->kdiv << KDIV_SHIFT; + tmp = FIELD_PREP(KDIV_MASK, rate->kdiv); writel_relaxed(tmp, pll->base + DIV_CTL1); return 0; @@ -280,10 +277,11 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel_relaxed(tmp, pll->base + GNRL_CTL); - div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | - (rate->sdiv << SDIV_SHIFT); + div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | + FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); writel_relaxed(div_val, pll->base + DIV_CTL0); - writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); + writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than -- cgit v1.2.3 From 53990cf9d5b489fc0ec08e5c4df7139fc311a824 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:52 +0100 Subject: clk: imx: pll14xx: consolidate rate calculation The PLL driver has support for two different PLLs: The pll1416x and the pll1443x. The latter has support for an additional kdiv value. recalc_rate can be the same calculation when kdiv is assumed to be zero for the PLL which doesn't support that value. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-5-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 59 +++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 33 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index fabb380b8730..ebd5d888fea6 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -97,6 +97,20 @@ static const struct imx_pll14xx_rate_table *imx_get_pll_settings( return NULL; } +static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, + int sdiv, int kdiv, unsigned long prate) +{ + u64 fvco = prate; + + /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ + fvco *= (mdiv * 65536 + kdiv); + pdiv *= 65536; + + do_div(fvco, pdiv << sdiv); + + return fvco; +} + static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { @@ -113,46 +127,25 @@ static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, return rate_table[i - 1].rate; } -static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pll14xx *pll = to_clk_pll14xx(hw); - u32 mdiv, pdiv, sdiv, pll_div; - u64 fvco = parent_rate; - - pll_div = readl_relaxed(pll->base + DIV_CTL0); - mdiv = FIELD_GET(MDIV_MASK, pll_div); - pdiv = FIELD_GET(PDIV_MASK, pll_div); - sdiv = FIELD_GET(SDIV_MASK, pll_div); - - fvco *= mdiv; - do_div(fvco, pdiv << sdiv); - - return fvco; -} - -static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, +static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); - u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; - short int kdiv; - u64 fvco = parent_rate; + u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); - /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ - fvco *= (mdiv * 65536 + kdiv); - pdiv *= 65536; - - do_div(fvco, pdiv << sdiv); + if (pll->type == PLL_1443X) { + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); + } else { + kdiv = 0; + } - return fvco; + return pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, parent_rate); } static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate, @@ -363,20 +356,20 @@ static const struct clk_ops clk_pll1416x_ops = { .prepare = clk_pll14xx_prepare, .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, - .recalc_rate = clk_pll1416x_recalc_rate, + .recalc_rate = clk_pll14xx_recalc_rate, .round_rate = clk_pll14xx_round_rate, .set_rate = clk_pll1416x_set_rate, }; static const struct clk_ops clk_pll1416x_min_ops = { - .recalc_rate = clk_pll1416x_recalc_rate, + .recalc_rate = clk_pll14xx_recalc_rate, }; static const struct clk_ops clk_pll1443x_ops = { .prepare = clk_pll14xx_prepare, .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, - .recalc_rate = clk_pll1443x_recalc_rate, + .recalc_rate = clk_pll14xx_recalc_rate, .round_rate = clk_pll14xx_round_rate, .set_rate = clk_pll1443x_set_rate, }; -- cgit v1.2.3 From 052d03a043afebb8e26ec17de52e8cdc8b217ef9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:53 +0100 Subject: clk: imx: pll14xx: name variables after usage In clk_pll1443x_set_rate() 'tmp' is used for the content of different registers which makes it a bit hard to follow. Use different variables named after the registers to make it clearer. No functional change intended. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-6-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index ebd5d888fea6..b464e1155e25 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -238,7 +238,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, { struct clk_pll14xx *pll = to_clk_pll14xx(hw); const struct imx_pll14xx_rate_table *rate; - u32 tmp, div_val; + u32 gnrl_ctl, div_ctl0; int ret; rate = imx_get_pll_settings(pll, drate); @@ -248,32 +248,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + DIV_CTL0); + div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); - if (!clk_pll14xx_mp_change(rate, tmp)) { - tmp &= ~SDIV_MASK; - tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(tmp, pll->base + DIV_CTL0); + if (!clk_pll14xx_mp_change(rate, div_ctl0)) { + div_ctl0 &= ~SDIV_MASK; + div_ctl0 |= FIELD_PREP(SDIV_MASK, rate->sdiv); + writel_relaxed(div_ctl0, pll->base + DIV_CTL0); - tmp = FIELD_PREP(KDIV_MASK, rate->kdiv); - writel_relaxed(tmp, pll->base + DIV_CTL1); + writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), + pll->base + DIV_CTL1); return 0; } /* Enable RST */ - tmp = readl_relaxed(pll->base + GNRL_CTL); - tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL); + gnrl_ctl &= ~RST_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); /* Enable BYPASS */ - tmp |= BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl |= BYPASS_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); - div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | - FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_val, pll->base + DIV_CTL0); + div_ctl0 = FIELD_PREP(MDIV_MASK, rate->mdiv) | + FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); + writel_relaxed(div_ctl0, pll->base + DIV_CTL0); writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); /* @@ -285,8 +285,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, udelay(3); /* Disable RST */ - tmp |= RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl |= RST_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -294,8 +294,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return ret; /* Bypass */ - tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + gnrl_ctl &= ~BYPASS_MASK; + writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); return 0; } -- cgit v1.2.3 From 5ff50031cb8852bfcf587d003ba6bad3c2336852 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:54 +0100 Subject: clk: imx: pll14xx: explicitly return lowest rate clk_pll14xx_round_rate() returns the lowest rate by indexing into the rate table with the variable i. i is actually pll->rate_count as this is the value we come out of the loop with. Use pll->rate_count explicitly to make it a bit more clear what is being done. While at it fix a typo in the comment. No functional change. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-7-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index b464e1155e25..af4c979e70a6 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -118,13 +118,13 @@ static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; int i; - /* Assumming rate_table is in descending order */ + /* Assuming rate_table is in descending order */ for (i = 0; i < pll->rate_count; i++) if (rate >= rate_table[i].rate) return rate_table[i].rate; /* return minimum supported value */ - return rate_table[i - 1].rate; + return rate_table[pll->rate_count - 1].rate; } static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, -- cgit v1.2.3 From 80cbc80612a01461a257f2c2eb9976cbadfb7be2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:55 +0100 Subject: clk: imx: pll14xx: Add pr_fmt Print all messages from within the pll14xx driver with a common prefix using pr_fmt. No need to print function names anymore, so drop them from the messages. Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-8-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index af4c979e70a6..646e0ce7d624 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -3,6 +3,8 @@ * Copyright 2017-2018 NXP. */ +#define pr_fmt(fmt) "pll14xx: " fmt + #include #include #include @@ -177,8 +179,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, rate = imx_get_pll_settings(pll, drate); if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, clk_hw_get_name(hw)); + pr_err("Invalid rate %lu for pll clk %s\n", drate, + clk_hw_get_name(hw)); return -EINVAL; } @@ -404,8 +406,7 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, init.ops = &clk_pll1443x_ops; break; default: - pr_err("%s: Unknown pll type for pll clk %s\n", - __func__, name); + pr_err("Unknown pll type for pll clk %s\n", name); kfree(pll); return ERR_PTR(-EINVAL); } @@ -424,8 +425,7 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, ret = clk_hw_register(dev, hw); if (ret) { - pr_err("%s: failed to register pll %s %d\n", - __func__, name, ret); + pr_err("failed to register pll %s %d\n", name, ret); kfree(pll); return ERR_PTR(ret); } -- cgit v1.2.3 From b09c68dc57c9d44071d83bb935b733f53ea2b2b4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 4 Mar 2022 13:52:56 +0100 Subject: clk: imx: pll14xx: Support dynamic rates The pll1443x PLL so far only supports rates from a rate table passed during initialization. Calculating PLL settings dynamically helps audio applications to get their desired rates, so support for this is added in this patch. The strategy to get to the PLL setting for a rate is: - First try to only adjust kdiv which specifies the fractional part of the PLL. This setting can be changed without glitches on the output and is therefore preferred - When that isn't possible then the rate table is searched for suitable rates, so for standard rates the same settings are used as without this patch - As a last resort the best settings are calculated dynamically The code in this patch is based on patches from Adrian Alonso and Mads Bligaard Nielsen Signed-off-by: Sascha Hauer Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20220304125256.2125023-9-s.hauer@pengutronix.de Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-pll14xx.c | 143 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 126 insertions(+), 17 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 646e0ce7d624..1d0f79e9c346 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -29,6 +29,8 @@ #define PDIV_MASK GENMASK(9, 4) #define SDIV_MASK GENMASK(2, 0) #define KDIV_MASK GENMASK(15, 0) +#define KDIV_MIN SHRT_MIN +#define KDIV_MAX SHRT_MAX #define LOCK_TIMEOUT_US 10000 @@ -113,7 +115,106 @@ static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, return fvco; } -static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, +static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, + unsigned long rate, unsigned long prate) +{ + long kdiv; + + /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */ + kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); + + return clamp_t(short, kdiv, KDIV_MIN, KDIV_MAX); +} + +static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, + unsigned long prate, struct imx_pll14xx_rate_table *t) +{ + u32 pll_div_ctl0, pll_div_ctl1; + int mdiv, pdiv, sdiv, kdiv; + long fvco, rate_min, rate_max, dist, best = LONG_MAX; + const struct imx_pll14xx_rate_table *tt; + + /* + * Fractional PLL constrains: + * + * a) 6MHz <= prate <= 25MHz + * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz) + * c) 64 <= m <= 1023 + * d) 0 <= s <= 6 + * e) -32768 <= k <= 32767 + * + * fvco = (m * 65536 + k) * prate / (p * 65536) + */ + + /* First try if we can get the desired rate from one of the static entries */ + tt = imx_get_pll_settings(pll, rate); + if (tt) { + pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n", + clk_hw_get_name(&pll->hw), prate, rate); + t->rate = tt->rate; + t->mdiv = tt->mdiv; + t->pdiv = tt->pdiv; + t->sdiv = tt->sdiv; + t->kdiv = tt->kdiv; + return; + } + + pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); + pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); + sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); + pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + + /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */ + rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); + rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate); + + if (rate >= rate_min && rate <= rate_max) { + kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); + pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n", + clk_hw_get_name(&pll->hw), prate, rate, + FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv); + fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); + t->rate = (unsigned int)fvco; + t->mdiv = mdiv; + t->pdiv = pdiv; + t->sdiv = sdiv; + t->kdiv = kdiv; + return; + } + + /* Finally calculate best values */ + for (pdiv = 1; pdiv <= 7; pdiv++) { + for (sdiv = 0; sdiv <= 6; sdiv++) { + /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */ + mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate); + mdiv = clamp(mdiv, 64, 1023); + + kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); + fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); + + /* best match */ + dist = abs((long)rate - (long)fvco); + if (dist < best) { + best = dist; + t->rate = (unsigned int)fvco; + t->mdiv = mdiv; + t->pdiv = pdiv; + t->sdiv = sdiv; + t->kdiv = kdiv; + + if (!dist) + goto found; + } + } + } +found: + pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n", + clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv, + t->mdiv, t->kdiv); +} + +static long clk_pll1416x_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); @@ -129,6 +230,17 @@ static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate, return rate_table[pll->rate_count - 1].rate; } +static long clk_pll1443x_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct imx_pll14xx_rate_table t; + + imx_pll14xx_calc_settings(pll, rate, *prate, &t); + + return t.rate; +} + static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -239,25 +351,21 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); - const struct imx_pll14xx_rate_table *rate; + struct imx_pll14xx_rate_table rate; u32 gnrl_ctl, div_ctl0; int ret; - rate = imx_get_pll_settings(pll, drate); - if (!rate) { - pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, clk_hw_get_name(hw)); - return -EINVAL; - } + imx_pll14xx_calc_settings(pll, drate, prate, &rate); div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); - if (!clk_pll14xx_mp_change(rate, div_ctl0)) { + if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { + /* only sdiv and/or kdiv changed - no need to RESET PLL */ div_ctl0 &= ~SDIV_MASK; - div_ctl0 |= FIELD_PREP(SDIV_MASK, rate->sdiv); + div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); writel_relaxed(div_ctl0, pll->base + DIV_CTL0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), + writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); return 0; @@ -272,11 +380,12 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, gnrl_ctl |= BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); - div_ctl0 = FIELD_PREP(MDIV_MASK, rate->mdiv) | - FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); + div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | + FIELD_PREP(PDIV_MASK, rate.pdiv) | + FIELD_PREP(SDIV_MASK, rate.sdiv); writel_relaxed(div_ctl0, pll->base + DIV_CTL0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); + + writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than @@ -359,7 +468,7 @@ static const struct clk_ops clk_pll1416x_ops = { .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, .recalc_rate = clk_pll14xx_recalc_rate, - .round_rate = clk_pll14xx_round_rate, + .round_rate = clk_pll1416x_round_rate, .set_rate = clk_pll1416x_set_rate, }; @@ -372,7 +481,7 @@ static const struct clk_ops clk_pll1443x_ops = { .unprepare = clk_pll14xx_unprepare, .is_prepared = clk_pll14xx_is_prepared, .recalc_rate = clk_pll14xx_recalc_rate, - .round_rate = clk_pll14xx_round_rate, + .round_rate = clk_pll1443x_round_rate, .set_rate = clk_pll1443x_set_rate, }; -- cgit v1.2.3 From 1a944729d8635fa59638f24e8727d5ccaa0c8c19 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 4 Mar 2022 20:26:16 +0200 Subject: clk: at91: sama7g5: fix parents of PDMCs' GCLK Audio PLL can be used as parent by the GCLKs of PDMCs. Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") Signed-off-by: Codrin Ciubotariu Reviewed-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com --- drivers/clk/at91/sama7g5.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index e43458673afb..9a213ba9e58b 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -699,16 +699,16 @@ static const struct { { .n = "pdmc0_gclk", .id = 68, .r = { .max = 50000000 }, - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, { .n = "pdmc1_gclk", .id = 69, .r = { .max = 50000000, }, - .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, - .pp_mux_table = { 5, 8, }, + .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, + .pp_mux_table = { 5, 9, }, .pp_count = 2, .pp_chg_id = INT_MIN, }, -- cgit v1.2.3 From 8e842f02af7e2f6225d52d78cd25b465a98d344b Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 3 Feb 2022 13:02:02 +0200 Subject: clk: at91: clk-master: remove dead code Commit facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master clock") removed the master clock's prescaler from clock tree of SAMA7G5 as it has been discovered that there is a hardware bug when trying to change it at run-time (bug is described in description of commit facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master clock")). This was previously changed at CPUFreq driver request. Thus, with commit facb87ad7560 ("clk: at91: sama7g5: remove prescaler part of master clock") there is no need of code that handles run-time changes of master clock's prescaler, thus remove this code. Signed-off-by: Claudiu Beznea Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com --- drivers/clk/at91/at91rm9200.c | 3 +- drivers/clk/at91/at91sam9260.c | 3 +- drivers/clk/at91/at91sam9g45.c | 3 +- drivers/clk/at91/at91sam9n12.c | 3 +- drivers/clk/at91/at91sam9rl.c | 3 +- drivers/clk/at91/at91sam9x5.c | 3 +- drivers/clk/at91/clk-master.c | 117 +++-------------------------------------- drivers/clk/at91/dt-compat.c | 3 +- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sam9x60.c | 3 +- drivers/clk/at91/sama5d2.c | 3 +- drivers/clk/at91/sama5d3.c | 3 +- drivers/clk/at91/sama5d4.c | 3 +- 13 files changed, 18 insertions(+), 134 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index fff4fdda974f..b174f727a8ef 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -143,8 +143,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) parent_names, &at91rm9200_master_layout, &rm9200_mck_characteristics, - &rm9200_mck_lock, CLK_SET_RATE_GATE, - INT_MIN); + &rm9200_mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index 79802f864ee5..11550e50cd9f 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -419,8 +419,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, parent_names, &at91rm9200_master_layout, data->mck_characteristics, - &at91sam9260_mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &at91sam9260_mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index 7ed984f8058c..8c9344451f46 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -154,8 +154,7 @@ static void __init at91sam9g45_pmc_setup(struct device_node *np) parent_names, &at91rm9200_master_layout, &mck_characteristics, - &at91sam9g45_mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &at91sam9g45_mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 63cc58944b00..0bb19400d199 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -181,8 +181,7 @@ static void __init at91sam9n12_pmc_setup(struct device_node *np) parent_names, &at91sam9x5_master_layout, &mck_characteristics, - &at91sam9n12_mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &at91sam9n12_mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index 4d4faf6c61d8..b992137bab02 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -123,8 +123,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np) parent_names, &at91rm9200_master_layout, &sam9rl_mck_characteristics, - &sam9rl_mck_lock, CLK_SET_RATE_GATE, - INT_MIN); + &sam9rl_mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index bd8007b4f3e0..3857db2e144b 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -201,8 +201,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np, hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index b2d0a7f4f7f9..164e2959c7cf 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -374,85 +374,6 @@ static void clk_sama7g5_master_best_diff(struct clk_rate_request *req, } } -static int clk_master_pres_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - struct clk_master *master = to_clk_master(hw); - struct clk_rate_request req_parent = *req; - const struct clk_master_characteristics *characteristics = - master->characteristics; - struct clk_hw *parent; - long best_rate = LONG_MIN, best_diff = LONG_MIN; - u32 pres; - int i; - - if (master->chg_pid < 0) - return -EOPNOTSUPP; - - parent = clk_hw_get_parent_by_index(hw, master->chg_pid); - if (!parent) - return -EOPNOTSUPP; - - for (i = 0; i <= MASTER_PRES_MAX; i++) { - if (characteristics->have_div3_pres && i == MASTER_PRES_MAX) - pres = 3; - else - pres = 1 << i; - - req_parent.rate = req->rate * pres; - if (__clk_determine_rate(parent, &req_parent)) - continue; - - clk_sama7g5_master_best_diff(req, parent, req_parent.rate, - &best_diff, &best_rate, pres); - if (!best_diff) - break; - } - - return 0; -} - -static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_master *master = to_clk_master(hw); - unsigned long flags; - unsigned int pres, mckr, tmp; - int ret; - - pres = DIV_ROUND_CLOSEST(parent_rate, rate); - if (pres > MASTER_PRES_MAX) - return -EINVAL; - - else if (pres == 3) - pres = MASTER_PRES_MAX; - else if (pres) - pres = ffs(pres) - 1; - - spin_lock_irqsave(master->lock, flags); - ret = regmap_read(master->regmap, master->layout->offset, &mckr); - if (ret) - goto unlock; - - mckr &= master->layout->mask; - tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK; - if (pres == tmp) - goto unlock; - - mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift); - mckr |= (pres << master->layout->pres_shift); - ret = regmap_write(master->regmap, master->layout->offset, mckr); - if (ret) - goto unlock; - - while (!clk_master_ready(master)) - cpu_relax(); -unlock: - spin_unlock_irqrestore(master->lock, flags); - - return ret; -} - static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -539,13 +460,6 @@ static void clk_master_pres_restore_context(struct clk_hw *hw) pr_warn("MCKR PRES was not configured properly by firmware!\n"); } -static void clk_master_pres_restore_context_chg(struct clk_hw *hw) -{ - struct clk_master *master = to_clk_master(hw); - - clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate); -} - static const struct clk_ops master_pres_ops = { .prepare = clk_master_prepare, .is_prepared = clk_master_is_prepared, @@ -555,25 +469,13 @@ static const struct clk_ops master_pres_ops = { .restore_context = clk_master_pres_restore_context, }; -static const struct clk_ops master_pres_ops_chg = { - .prepare = clk_master_prepare, - .is_prepared = clk_master_is_prepared, - .determine_rate = clk_master_pres_determine_rate, - .recalc_rate = clk_master_pres_recalc_rate, - .get_parent = clk_master_pres_get_parent, - .set_rate = clk_master_pres_set_rate, - .save_context = clk_master_pres_save_context, - .restore_context = clk_master_pres_restore_context_chg, -}; - static struct clk_hw * __init at91_clk_register_master_internal(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, - const struct clk_ops *ops, spinlock_t *lock, u32 flags, - int chg_pid) + const struct clk_ops *ops, spinlock_t *lock, u32 flags) { struct clk_master *master; struct clk_init_data init; @@ -599,7 +501,6 @@ at91_clk_register_master_internal(struct regmap *regmap, master->layout = layout; master->characteristics = characteristics; master->regmap = regmap; - master->chg_pid = chg_pid; master->lock = lock; if (ops == &master_div_ops_chg) { @@ -628,19 +529,13 @@ at91_clk_register_master_pres(struct regmap *regmap, const char **parent_names, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, - spinlock_t *lock, u32 flags, int chg_pid) + spinlock_t *lock) { - const struct clk_ops *ops; - - if (flags & CLK_SET_RATE_GATE) - ops = &master_pres_ops; - else - ops = &master_pres_ops_chg; - return at91_clk_register_master_internal(regmap, name, num_parents, parent_names, layout, - characteristics, ops, - lock, flags, chg_pid); + characteristics, + &master_pres_ops, + lock, CLK_SET_RATE_GATE); } struct clk_hw * __init @@ -661,7 +556,7 @@ at91_clk_register_master_div(struct regmap *regmap, hw = at91_clk_register_master_internal(regmap, name, 1, &parent_name, layout, characteristics, ops, - lock, flags, -EINVAL); + lock, flags); if (!IS_ERR(hw) && safe_div) { master_div = to_clk_master(hw); diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index ca2dbb65b9df..8ca8bcacf66d 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -392,8 +392,7 @@ of_at91_clk_master_setup(struct device_node *np, hw = at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, parent_names, layout, - characteristics, &mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + characteristics, &mck_lock); if (IS_ERR(hw)) goto out_free_characteristics; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 3a1bf6194c28..efe4975bddc3 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -175,7 +175,7 @@ at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, - spinlock_t *lock, u32 flags, int chg_pid); + spinlock_t *lock); struct clk_hw * __init at91_clk_register_master_div(struct regmap *regmap, const char *name, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 5c264185f261..9ea4ce501bad 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -271,8 +271,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np) parent_names[2] = "pllack_divck"; hw = at91_clk_register_master_pres(regmap, "masterck_pres", 3, parent_names, &sam9x60_master_layout, - &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index f479e39e3bb2..cfd0f5e23b99 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -242,8 +242,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np) hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 339d0f382ff0..7e93c6edf305 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -175,8 +175,7 @@ static void __init sama5d3_pmc_setup(struct device_node *np) hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 4af75b1e39e9..1a14a9bce308 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -190,8 +190,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np) hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, parent_names, &at91sam9x5_master_layout, - &mck_characteristics, &mck_lock, - CLK_SET_RATE_GATE, INT_MIN); + &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; -- cgit v1.2.3 From 837519775f1d3945e3d4019641f7120d58325059 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 22 Feb 2022 02:15:29 +0100 Subject: clk: qcom: Add display clock controller driver for SM6350 Add support for the display clock controller found on SM6350. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220222011534.3502-2-konrad.dybcio@somainline.org --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-sm6350.c | 797 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 807 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-sm6350.c (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index f5b54bfc992f..dc246e473888 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -598,6 +598,15 @@ config SM_DISPCC_8250 Say Y if you want to support display devices and functionality such as splash screen. +config SM_DISPCC_6350 + tristate "SM6350 Display Clock Controller" + depends on SM_GCC_6350 + help + Support for the display clock controller on Qualcomm Technologies, Inc + SM6350 devices. + Say Y if you want to support display devices and functionality such as + splash screen. + config SM_GCC_6115 tristate "SM6115 and SM4250 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index d96d6793fc7d..82fe72028976 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o +obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c new file mode 100644 index 000000000000..0c3c2e26ede9 --- /dev/null +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_EVEN, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_GCC_DISP_GPLL0_CLK, +}; + +static struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x3a, + .alpha = 0x5555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002067, + .test_ctl_val = 0x40000000, + .test_ctl_hi_val = 0x00000002, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00004805, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dp_phy_pll_link_clk" }, + { .fw_name = "dp_phy_pll_vco_div_clk" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk" }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, + { P_DISP_CC_PLL0_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk" }, + { .hw = &disp_cc_pll0.clkr.hw }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GCC_DISP_GPLL0_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "gcc_disp_gpll0_clk" }, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk" }, +}; + +static const struct parent_map disp_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_6[] = { + { .fw_name = "bi_tcxo" }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0), + F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x115c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x10c4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x10dc, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x1144, + .mnd_width = 0, + .hid_width = 5, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x1114, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x10f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x112c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x10e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0), + F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0), + F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x107c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x1064, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x1094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x10ac, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_6, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_6, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { + .reg = 0x1110, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_dp_link_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x104c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x104c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x102c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x102c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x1030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x1048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x1040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x1038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x103c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x103c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x1044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x1034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x1010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x1020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x100c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x1018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { + .halt_reg = 0x200c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_vsync_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x1028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_sleep_clk = { + .halt_reg = 0x5004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_xo_clk = { + .halt_reg = 0x5008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x1004, + .pd = { + .name = "mdss_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *disp_cc_sm6350_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = + &disp_cc_mdss_dp_link_div_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, + [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, +}; + +static struct gdsc *disp_cc_sm6350_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, +}; + +static const struct regmap_config disp_cc_sm6350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_sm6350_desc = { + .config = &disp_cc_sm6350_regmap_config, + .clks = disp_cc_sm6350_clocks, + .num_clks = ARRAY_SIZE(disp_cc_sm6350_clocks), + .gdscs = disp_cc_sm6350_gdscs, + .num_gdscs = ARRAY_SIZE(disp_cc_sm6350_gdscs), +}; + +static const struct of_device_id disp_cc_sm6350_match_table[] = { + { .compatible = "qcom,sm6350-dispcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_sm6350_match_table); + +static int disp_cc_sm6350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &disp_cc_sm6350_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + + return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap); +} + +static struct platform_driver disp_cc_sm6350_driver = { + .probe = disp_cc_sm6350_probe, + .driver = { + .name = "disp_cc-sm6350", + .of_match_table = disp_cc_sm6350_match_table, + }, +}; + +static int __init disp_cc_sm6350_init(void) +{ + return platform_driver_register(&disp_cc_sm6350_driver); +} +subsys_initcall(disp_cc_sm6350_init); + +static void __exit disp_cc_sm6350_exit(void) +{ + platform_driver_unregister(&disp_cc_sm6350_driver); +} +module_exit(disp_cc_sm6350_exit); + +MODULE_DESCRIPTION("QTI DISP_CC SM6350 Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 013804a727a0482bc6661e15dfababde5f856550 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 22 Feb 2022 02:15:31 +0100 Subject: clk: qcom: Add GPU clock controller driver for SM6350 Add support for the GPU clock controller found on SM6350. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220222011534.3502-4-konrad.dybcio@somainline.org --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6350.c | 521 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 530 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6350.c (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index dc246e473888..229a9aa190c4 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -660,6 +660,14 @@ config SM_GCC_8450 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6350 + tristate "SM6350 Graphics Clock Controller" + select SM_GCC_6350 + help + Support for the graphics clock controller on SM6350 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_8150 tristate "SM8150 Graphics Clock Controller" select SM_GCC_8150 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 82fe72028976..fca999afc760 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o +obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c new file mode 100644 index 000000000000..ef15185a99c3 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "reset.h" +#include "gdsc.h" + +#define CX_GMU_CBCR_SLEEP_MASK 0xF +#define CX_GMU_CBCR_SLEEP_SHIFT 4 +#define CX_GMU_CBCR_WAKE_MASK 0xF +#define CX_GMU_CBCR_WAKE_SHIFT 8 + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, + P_GPU_CC_PLL1_OUT_EVEN, + P_GPU_CC_PLL1_OUT_MAIN, + P_GPU_CC_PLL1_OUT_ODD, + P_CRC_DIV, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 506MHz Configuration*/ +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x1A, + .alpha = 0x5AAA, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002067, + .test_ctl_val = 0x40000000, + .test_ctl_hi_val = 0x00000002, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00004805, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static struct clk_fixed_factor crc_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "crc_div", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, +}; + +/* 514MHz Configuration*/ +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x1A, + .alpha = 0xC555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002067, + .test_ctl_val = 0x40000000, + .test_ctl_hi_val = 0x00000002, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00004805, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = fabia_vco, + .num_vco = ARRAY_SIZE(fabia_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk" }, + { .fw_name = "gcc_gpu_gpll0_div_clk" }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CRC_DIV, 1 }, + { P_GPU_CC_PLL0_OUT_ODD, 2 }, + { P_GPU_CC_PLL1_OUT_EVEN, 3 }, + { P_GPU_CC_PLL1_OUT_ODD, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &crc_div.hw }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(253000000, P_CRC_DIV, 1, 0, 0), + F(355000000, P_CRC_DIV, 1, 0, 0), + F(430000000, P_CRC_DIV, 1, 0, 0), + F(565000000, P_CRC_DIV, 1, 0, 0), + F(650000000, P_CRC_DIV, 1, 0, 0), + F(800000000, P_CRC_DIV, 1, 0, 0), + F(825000000, P_CRC_DIV, 1, 0, 0), + F(850000000, P_CRC_DIV, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_acd_ahb_clk = { + .halt_reg = 0x1168, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1168, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_acd_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_acd_cxo_clk = { + .halt_reg = 0x1164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1164, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_acd_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = { + .halt_reg = 0x10a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_slv_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_vsense_clk = { + .halt_reg = 0x1058, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_vsense_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | POLL_CFG_GDSCR, +}; + +static struct clk_hw *gpu_cc_sm6350_hws[] = { + [GPU_CC_CRC_DIV] = &crc_div.hw, +}; + +static struct clk_regmap *gpu_cc_sm6350_clocks[] = { + [GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr, + [GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr, + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, +}; + +static struct gdsc *gpu_cc_sm6350_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6350_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8008, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6350_desc = { + .config = &gpu_cc_sm6350_regmap_config, + .clk_hws = gpu_cc_sm6350_hws, + .num_clk_hws = ARRAY_SIZE(gpu_cc_sm6350_hws), + .clks = gpu_cc_sm6350_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6350_clocks), + .gdscs = gpu_cc_sm6350_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm6350_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6350_match_table[] = { + { .compatible = "qcom,sm6350-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6350_match_table); + +static int gpu_cc_sm6350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + unsigned int value, mask; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6350_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Configure gpu_cc_cx_gmu_clk with recommended wakeup/sleep settings */ + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; + value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; + regmap_update_bits(regmap, 0x1098, mask, value); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6350_driver = { + .probe = gpu_cc_sm6350_probe, + .driver = { + .name = "sm6350-gpucc", + .of_match_table = gpu_cc_sm6350_match_table, + }, +}; + +static int __init gpu_cc_sm6350_init(void) +{ + return platform_driver_register(&gpu_cc_sm6350_driver); +} +core_initcall(gpu_cc_sm6350_init); + +static void __exit gpu_cc_sm6350_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm6350_driver); +} +module_exit(gpu_cc_sm6350_exit); + +MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From af44e3276bf8f79bed480764c6a6296be73e073f Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 22 Feb 2022 10:26:22 +0530 Subject: clk: qcom: Add A7 PLL support for SDX65 Update A7 PLL Kconfig to reflect support for SDX65. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645505785-2271-3-git-send-email-quic_rohiagar@quicinc.com --- drivers/clk/qcom/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 229a9aa190c4..a4ede4a4143d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -29,11 +29,11 @@ config QCOM_A53PLL devices. config QCOM_A7PLL - tristate "SDX55 A7 PLL" + tristate "A7 PLL driver for SDX55 and SDX65" help - Support for the A7 PLL on SDX55 devices. It provides the CPU with + Support for the A7 PLL on SDX55 and SDX65 devices. It provides the CPU with frequencies above 1GHz. - Say Y if you want to support higher CPU frequencies on SDX55 + Say Y if you want to support higher CPU frequencies on SDX55 and SDX65 devices. config QCOM_CLK_APCS_MSM8916 -- cgit v1.2.3 From 2081df368ef325bd7f659e395620090ab2d8d1c0 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Tue, 22 Feb 2022 10:26:25 +0530 Subject: clk: qcom: Add SDX65 APCS clock controller support Update APCS Kconfig to reflect support for SDX65 APCS clock controller. Signed-off-by: Rohit Agarwal Reviewed-by: Stephen Boyd Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645505785-2271-6-git-send-email-quic_rohiagar@quicinc.com --- drivers/clk/qcom/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a4ede4a4143d..204438ceabf3 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996 drivers for dynamic power management. config QCOM_CLK_APCS_SDX55 - tristate "SDX55 APCS Clock Controller" + tristate "SDX55 and SDX65 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST help - Support for the APCS Clock Controller on SDX55 platform. The + Support for the APCS Clock Controller on SDX55, SDX65 platforms. The APCS is managing the mux and divider which feeds the CPUs. Say Y if you want to support CPU frequency scaling on devices - such as SDX55. + such as SDX55, SDX65. config QCOM_CLK_RPM tristate "RPM based Clock Controller" -- cgit v1.2.3 From e95e825333eda345d812b461301dad50021d5487 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:24 +0100 Subject: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by: Ansuel Smith Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-5-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index d6b7adb4be38..34cddf461dba 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -291,13 +291,13 @@ static const char * const gcc_pxo_pll3[] = { "pll3", }; -static const struct parent_map gcc_pxo_pll8_pll0[] = { +static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PXO, 0 }, { P_PLL8, 3 }, { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0_map[] = { +static const char * const gcc_pxo_pll8_pll0[] = { "pxo", "pll8_vote", "pll0_vote", @@ -1993,7 +1993,7 @@ static struct clk_rcg usb30_master_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_master, .clkr = { @@ -2001,7 +2001,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2063,7 +2063,7 @@ static struct clk_rcg usb30_utmi_clk = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb30_utmi, .clkr = { @@ -2071,7 +2071,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2133,7 +2133,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2141,7 +2141,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2197,7 +2197,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { }, .s = { .src_sel_shift = 0, - .parent_map = gcc_pxo_pll8_pll0, + .parent_map = gcc_pxo_pll8_pll0_map, }, .freq_tbl = clk_tbl_usb, .clkr = { @@ -2205,7 +2205,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0_map, + .parent_names = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, -- cgit v1.2.3 From cb02866f9a740fb9fb8ff19698a69290da4057e5 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:25 +0100 Subject: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by: Ansuel Smith Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-6-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 286 +++++++++++++++++++++++++---------------- 1 file changed, 173 insertions(+), 113 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 34cddf461dba..aacd0ada0dd3 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -25,6 +25,10 @@ #include "clk-hfpll.h" #include "reset.h" +static const struct clk_parent_data gcc_pxo[] = { + { .fw_name = "pxo", .name = "pxo" }, +}; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -35,7 +39,7 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_hws = (const struct clk_hw*[]){ + &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -62,7 +68,7 @@ static struct clk_pll pll3 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll3", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -89,7 +95,7 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]){ + &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = { static struct clk_hfpll hfpll0 = { .d = &hfpll0_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll0", .ops = &clk_ops_hfpll, @@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = { static struct clk_hfpll hfpll1 = { .d = &hfpll1_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll1", .ops = &clk_ops_hfpll, @@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = { static struct clk_hfpll hfpll_l2 = { .d = &hfpll_l2_data, .clkr.hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .name = "hfpll_l2", .ops = &clk_ops_hfpll, @@ -194,7 +202,7 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_hws = (const struct clk_hw*[]){ + &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -238,7 +248,7 @@ static struct clk_pll pll18 = { .freq_tbl = pll18_freq_tbl, .clkr.hw.init = &(struct clk_init_data){ .name = "pll18", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = { { P_PLL8, 3 } }; -static const char * const gcc_pxo_pll8[] = { - "pxo", - "pll8_vote", +static const struct clk_parent_data gcc_pxo_pll8[] = { + { .fw_name = "pxo", .name = "pxo" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_cxo_map[] = { @@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = { { P_CXO, 5 } }; -static const char * const gcc_pxo_pll8_cxo[] = { - "pxo", - "pll8_vote", - "cxo", +static const struct clk_parent_data gcc_pxo_pll8_cxo[] = { + { .fw_name = "pxo", .name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .fw_name = "cxo", .name = "cxo" }, }; static const struct parent_map gcc_pxo_pll3_map[] = { @@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = { { P_PLL3, 6 } }; -static const char * const gcc_pxo_pll3[] = { - "pxo", - "pll3", +static const struct clk_parent_data gcc_pxo_pll3[] = { + { .fw_name = "pxo", .name = "pxo" }, + { .hw = &pll3.clkr.hw }, }; static const struct parent_map gcc_pxo_pll8_pll0_map[] = { @@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = { { P_PLL0, 2 } }; -static const char * const gcc_pxo_pll8_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", +static const struct clk_parent_data gcc_pxo_pll8_pll0[] = { + { .fw_name = "pxo", .name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, }; static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { @@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = { { P_PLL18, 1 } }; -static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = { - "pxo", - "pll8_vote", - "pll0_vote", - "pll14", - "pll18", +static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { + { .fw_name = "pxo", .name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_clk", - .parent_names = (const char *[]){ - "gsbi6_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_clk", - .parent_names = (const char *[]){ - "gsbi7_uart_src", + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_clk", - .parent_names = (const char *[]){ "gsbi6_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi6_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_clk", - .parent_names = (const char *[]){ "gsbi7_qup_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gsbi7_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_pxo_pll8_cxo, + .parent_data = gcc_pxo_pll8_cxo, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]){ + &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]){ + &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc3_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc3_clk", - .parent_names = (const char *[]){ "sdc3_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sdc3_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", - .parent_names = gcc_pxo_pll8, + .parent_data = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, }, @@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "tsif_ref_clk", - .parent_names = (const char *[]){ "tsif_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &tsif_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src_clk", - .parent_names = (const char *[]){ "pcie_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src_clk", - .parent_names = (const char *[]){ "pcie1_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie1_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src_clk", - .parent_names = (const char *[]){ "pcie2_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &pcie2_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", - .parent_names = gcc_pxo_pll3, + .parent_data = gcc_pxo_pll3, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_rxoob_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_pmalive_clk", - .parent_names = (const char *[]){ "sata_ref_src" }, + .parent_hws = (const struct clk_hw*[]){ + &sata_ref_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "sata_phy_ref_clk", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = gcc_pxo, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_branch_clk", - .parent_names = (const char *[]){ "usb30_master_ref_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_master_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_0_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb30_1_utmi_clk_ctl", - .parent_names = (const char *[]){ "usb30_utmi_clk", }, + .parent_hws = (const struct clk_hw*[]){ + &usb30_utmi_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]){ + &usb_hs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", - .parent_names = gcc_pxo_pll8_pll0, + .parent_data = gcc_pxo_pll8_pll0, .num_parents = 3, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "usb_fs1_sys_clk", - .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, + .parent_hws = (const struct clk_hw*[]){ + &usb_fs1_xcvr_clk_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core1_clk", - .parent_names = (const char *[]){ - "gmac_core1_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core1_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core2_clk", - .parent_names = (const char *[]){ - "gmac_core2_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core2_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core3_clk", - .parent_names = (const char *[]){ - "gmac_core3_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core3_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "gmac_core4_clk", - .parent_names = (const char *[]){ - "gmac_core4_src", + .parent_hws = (const struct clk_hw*[]){ + &gmac_core4_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, }, @@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = { .enable_mask = BIT(6) | BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_tcm_clk", - .parent_names = (const char *[]){ - "nss_tcm_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_tcm_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, @@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", - .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, + .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, -- cgit v1.2.3 From a6aedd6532131bc81d47bbf63385dfcf2a0e9faa Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:26 +0100 Subject: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by: Ansuel Smith Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++++++--------------------- 1 file changed, 34 insertions(+), 34 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index aacd0ada0dd3..ef285d3853aa 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -373,7 +373,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -424,7 +424,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -475,7 +475,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -526,7 +526,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -577,7 +577,7 @@ static struct clk_rcg gsbi6_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -628,7 +628,7 @@ static struct clk_rcg gsbi7_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_uart_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -692,7 +692,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -743,7 +743,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -794,7 +794,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -845,7 +845,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -896,7 +896,7 @@ static struct clk_rcg gsbi6_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi6_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -947,7 +947,7 @@ static struct clk_rcg gsbi7_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi7_qup_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1099,7 +1099,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -1150,7 +1150,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1201,7 +1201,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_data = gcc_pxo_pll8_cxo, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1257,7 +1257,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -1321,7 +1321,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1371,7 +1371,7 @@ static struct clk_rcg sdc3_src = { .hw.init = &(struct clk_init_data){ .name = "sdc3_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1456,7 +1456,7 @@ static struct clk_rcg tsif_ref_src = { .hw.init = &(struct clk_init_data){ .name = "tsif_ref_src", .parent_data = gcc_pxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1620,7 +1620,7 @@ static struct clk_rcg pcie_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1714,7 +1714,7 @@ static struct clk_rcg pcie1_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie1_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1808,7 +1808,7 @@ static struct clk_rcg pcie2_ref_src = { .hw.init = &(struct clk_init_data){ .name = "pcie2_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1907,7 +1907,7 @@ static struct clk_rcg sata_ref_src = { .hw.init = &(struct clk_init_data){ .name = "sata_ref_src", .parent_data = gcc_pxo_pll3, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2048,7 +2048,7 @@ static struct clk_rcg usb30_master_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb30_master_ref_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2122,7 +2122,7 @@ static struct clk_rcg usb30_utmi_clk = { .hw.init = &(struct clk_init_data){ .name = "usb30_utmi_clk", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2196,7 +2196,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2262,7 +2262,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = { .hw.init = &(struct clk_init_data){ .name = "usb_fs1_xcvr_src", .parent_data = gcc_pxo_pll8_pll0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -2398,7 +2398,7 @@ static struct clk_dyn_rcg gmac_core1_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core1_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2470,7 +2470,7 @@ static struct clk_dyn_rcg gmac_core2_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core2_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2542,7 +2542,7 @@ static struct clk_dyn_rcg gmac_core3_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core3_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2614,7 +2614,7 @@ static struct clk_dyn_rcg gmac_core4_src = { .hw.init = &(struct clk_init_data){ .name = "gmac_core4_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2674,7 +2674,7 @@ static struct clk_dyn_rcg nss_tcm_src = { .hw.init = &(struct clk_init_data){ .name = "nss_tcm_src", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, }, }, @@ -2752,7 +2752,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core1_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, @@ -2805,7 +2805,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .hw.init = &(struct clk_init_data){ .name = "ubi32_core2_src_clk", .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), .ops = &clk_dyn_rcg_ops, .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, }, -- cgit v1.2.3 From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:27 +0100 Subject: clk: qcom: gcc-ipq806x: add additional freq nss cores Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be clocked to 800MHz. Add these missing freq to the gcc driver. Set the freq_tbl for the ubi32_cores to the correct values based on the machine compatible. Signed-off-by: Ansuel Smith Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-8-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index ef285d3853aa..f49fc8b753a8 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = { static struct pll_freq_tbl pll18_freq_tbl[] = { NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625), + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625), NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625), + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625), }; static struct clk_pll pll18 = { @@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = { }, }; -static const struct freq_tbl clk_tbl_nss[] = { +static const struct freq_tbl clk_tbl_nss_ipq8064[] = { { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, @@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss[] = { { } }; +static const struct freq_tbl clk_tbl_nss_ipq8065[] = { + { 110000000, P_PLL18, 1, 1, 5 }, + { 275000000, P_PLL18, 2, 0, 0 }, + { 600000000, P_PLL18, 1, 0, 0 }, + { 800000000, P_PLL18, 1, 0, 0 }, + { } +}; + static struct clk_dyn_rcg ubi32_core1_src_clk = { .ns_reg[0] = 0x3d2c, .ns_reg[1] = 0x3d30, @@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = { .pre_div_width = 2, }, .mux_sel_bit = 0, - .freq_tbl = clk_tbl_nss, + /* nss freq table is selected based on the SoC compatible */ .clkr = { .enable_reg = 0x3d20, .enable_mask = BIT(1), @@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { .pre_div_width = 2, }, .mux_sel_bit = 0, - .freq_tbl = clk_tbl_nss, + /* nss freq table is selected based on the SoC compatible */ .clkr = { .enable_reg = 0x3d40, .enable_mask = BIT(1), @@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) if (ret) return ret; + if (of_machine_is_compatible("qcom,ipq8065")) { + ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065; + ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065; + } else { + ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064; + ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064; + } + ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc); if (ret) return ret; -- cgit v1.2.3 From 28aa450d38e521de45be951df052d2c49a17fae2 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:28 +0100 Subject: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Some clocks are used by other devices present on the SoC. For example the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to reject any regulator change command. These clock should never be disabled. Signed-off-by: Ansuel Smith Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-9-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index f49fc8b753a8..983d07586930 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = { .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), .ops = &clk_rcg_ops, - .flags = CLK_SET_PARENT_GATE, + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED, }, }, }; @@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = { }, .num_parents = 1, .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }, }; @@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_h_clk", .ops = &clk_branch_ops, + .flags = CLK_IGNORE_UNUSED, }, }, }; -- cgit v1.2.3 From 33958ad3fc02aeb06a4634e59689a9559d968e1f Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:29 +0100 Subject: clk: qcom: clk-rcg: add clk_rcg_floor_ops ops Add clk_rcg_floor_ops for clock that can't provide a stable freq and require to use a floor freq to provide the requested frequency. Signed-off-by: Ansuel Smith Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-10-ansuelsmth@gmail.com --- drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++ drivers/clk/qcom/clk-rcg.h | 1 + 2 files changed, 25 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index a9d181d6be21..88845baa7f84 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate, return __clk_rcg_set_rate(rcg, f); } +static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_rcg *rcg = to_clk_rcg(hw); + const struct freq_tbl *f; + + f = qcom_find_freq_floor(rcg->freq_tbl, rate); + if (!f) + return -EINVAL; + + return __clk_rcg_set_rate(rcg, f); +} + static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { @@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = { }; EXPORT_SYMBOL_GPL(clk_rcg_ops); +const struct clk_ops clk_rcg_floor_ops = { + .enable = clk_enable_regmap, + .disable = clk_disable_regmap, + .get_parent = clk_rcg_get_parent, + .set_parent = clk_rcg_set_parent, + .recalc_rate = clk_rcg_recalc_rate, + .determine_rate = clk_rcg_determine_rate, + .set_rate = clk_rcg_set_floor_rate, +}; +EXPORT_SYMBOL_GPL(clk_rcg_floor_ops); + const struct clk_ops clk_rcg_bypass_ops = { .enable = clk_enable_regmap, .disable = clk_disable_regmap, diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 99efcc7f8d88..00cea508d49e 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -86,6 +86,7 @@ struct clk_rcg { }; extern const struct clk_ops clk_rcg_ops; +extern const struct clk_ops clk_rcg_floor_ops; extern const struct clk_ops clk_rcg_bypass_ops; extern const struct clk_ops clk_rcg_bypass2_ops; extern const struct clk_ops clk_rcg_pixel_ops; -- cgit v1.2.3 From 7e726f34c782b2ca28a29ca9870e34e4319d65bc Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:30 +0100 Subject: clk: qcom: gcc-ipq806x: add additional freq for sdc table Add additional freq supported for the sdc table. The ops are changed to the floor_ops to handle a freq request of 52kHz where we need to provide a freq of 51.2kHz instead for stability reason. Signed-off-by: Ansuel Smith Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-11-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 983d07586930..f3d56519eee5 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = { { 20210000, P_PLL8, 1, 1, 19 }, { 24000000, P_PLL8, 4, 1, 4 }, { 48000000, P_PLL8, 4, 1, 2 }, + { 51200000, P_PLL8, 1, 2, 15 }, { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 }, @@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = { .name = "sdc1_src", .parent_data = gcc_pxo_pll8, .num_parents = ARRAY_SIZE(gcc_pxo_pll8), - .ops = &clk_rcg_ops, + .ops = &clk_rcg_floor_ops, }, } }; -- cgit v1.2.3 From b293510f3961b90dcab59965f57779be93ceda7c Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:32 +0100 Subject: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Add missing CryptoEngine clocks and pll11 required clock. Signed-off-by: Ansuel Smith Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-13-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 244 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index f3d56519eee5..711a8b421e8b 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -256,6 +256,24 @@ static struct clk_pll pll18 = { }, }; +static struct clk_pll pll11 = { + .l_reg = 0x3184, + .m_reg = 0x3188, + .n_reg = 0x318c, + .config_reg = 0x3194, + .mode_reg = 0x3180, + .status_reg = 0x3198, + .status_bit = 16, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pll11", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "pxo", + }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + enum { P_PXO, P_PLL8, @@ -264,6 +282,7 @@ enum { P_CXO, P_PLL14, P_PLL18, + P_PLL11, }; static const struct parent_map gcc_pxo_pll8_map[] = { @@ -331,6 +350,44 @@ static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = { { .hw = &pll18.clkr.hw }, }; +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL8, 4 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll8_vote.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = { + { P_PXO, 0 }, + { P_PLL3, 6 }, + { P_PLL0, 2 }, + { P_PLL14, 5 }, + { P_PLL18, 1 }, + { P_PLL11, 3 }, +}; + +static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = { + { .fw_name = "pxo" }, + { .hw = &pll3.clkr.hw }, + { .hw = &pll0_vote.hw }, + { .hw = &pll14.clkr.hw }, + { .hw = &pll18.clkr.hw }, + { .hw = &pll11.clkr.hw }, + +}; + static struct freq_tbl clk_tbl_gsbi_uart[] = { { 1843200, P_PLL8, 2, 6, 625 }, { 3686400, P_PLL8, 2, 12, 625 }, @@ -2824,6 +2881,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = { }, }; +static const struct freq_tbl clk_tbl_ce5_core[] = { + { 150000000, P_PLL3, 8, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_core_src = { + .ns_reg[0] = 0x36C4, + .ns_reg[1] = 0x36C8, + .bank_reg = 0x36C0, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_core, + .clkr = { + .enable_reg = 0x36C0, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_src", + .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_core_clk = { + .halt_reg = 0x2FDC, + .halt_bit = 5, + .hwcg_reg = 0x36CC, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x36CC, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_core_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_core_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_a_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_a_clk_src = { + .ns_reg[0] = 0x3d84, + .ns_reg[1] = 0x3d88, + .bank_reg = 0x3d80, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_a_clk, + .clkr = { + .enable_reg = 0x3d80, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_a_clk = { + .halt_reg = 0x3c20, + .halt_bit = 12, + .hwcg_reg = 0x3d8c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3d8c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_a_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_a_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + +static const struct freq_tbl clk_tbl_ce5_h_clk[] = { + { 160000000, P_PLL0, 5, 1, 1 }, + { 213200000, P_PLL11, 5, 1, 1 }, + { } +}; + +static struct clk_dyn_rcg ce5_h_clk_src = { + .ns_reg[0] = 0x3c64, + .ns_reg[1] = 0x3c68, + .bank_reg = 0x3c60, + .s[0] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .s[1] = { + .src_sel_shift = 0, + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map, + }, + .p[0] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .p[1] = { + .pre_div_shift = 3, + .pre_div_width = 4, + }, + .mux_sel_bit = 0, + .freq_tbl = clk_tbl_ce5_h_clk, + .clkr = { + .enable_reg = 0x3c60, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk_src", + .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11, + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11), + .ops = &clk_dyn_rcg_ops, + }, + }, +}; + +static struct clk_branch ce5_h_clk = { + .halt_reg = 0x3c20, + .halt_bit = 11, + .hwcg_reg = 0x3c6c, + .hwcg_bit = 6, + .clkr = { + .enable_reg = 0x3c6c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "ce5_h_clk", + .parent_hws = (const struct clk_hw*[]){ + &ce5_h_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch_ops, + .flags = CLK_SET_RATE_PARENT, + }, + }, +}; + static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -2831,6 +3068,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, + [PLL11] = &pll11.clkr, [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, @@ -2945,6 +3183,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr, + [CE5_A_CLK] = &ce5_a_clk.clkr, + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr, + [CE5_H_CLK] = &ce5_h_clk.clkr, + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr, + [CE5_CORE_CLK] = &ce5_core_clk.clkr, }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -- cgit v1.2.3 From 4f865bdcb44fb18951de94be5c2ec37a891a8d03 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 26 Feb 2022 14:52:34 +0100 Subject: clk: qcom: gcc-ipq806x: add CryptoEngine resets Add missing CryptoEngine resets. Signed-off-by: Ansuel Smith Reviewed-by: Stephen Boyd Tested-by: Jonathan McDowell Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226135235.10051-15-ansuelsmth@gmail.com --- drivers/clk/qcom/gcc-ipq806x.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c index 711a8b421e8b..718de17a1e60 100644 --- a/drivers/clk/qcom/gcc-ipq806x.c +++ b/drivers/clk/qcom/gcc-ipq806x.c @@ -3320,6 +3320,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = { [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, + [CRYPTO_ENG1_RESET] = { 0x3e00, 0}, + [CRYPTO_ENG2_RESET] = { 0x3e04, 0}, + [CRYPTO_ENG3_RESET] = { 0x3e08, 0}, + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0}, + [CRYPTO_AHB_RESET] = { 0x3e10, 0}, [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 }, [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 }, [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 }, -- cgit v1.2.3 From f804360bb3a50decbed6e2761247964dca72c080 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 26 Feb 2022 22:41:25 +0100 Subject: clk: qcom: smd: Add missing RPM clocks for msm8992/4 XO and MSS_CFG were omitted when first adding the clocks for these SoCs. Add them, and while at it, move the XO clock to the top of the definition list, as ideally everyone should start using it sooner or later.. Fixes: b4297844995f ("clk: qcom: smd: Add support for MSM8992/4 rpm clocks") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226214126.21209-2-konrad.dybcio@somainline.org --- drivers/clk/qcom/clk-smd-rpm.c | 13 +++++++++++-- include/linux/soc/qcom/smd-rpm.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index ea28e45ca371..418f017e933f 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -413,6 +413,7 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .recalc_rate = clk_smd_rpm_recalc_rate, }; +DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); @@ -604,7 +605,11 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000); DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); +DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, + QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); static struct clk_smd_rpm *msm8992_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, @@ -637,6 +642,8 @@ static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, @@ -661,6 +668,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); static struct clk_smd_rpm *msm8994_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, @@ -693,6 +702,8 @@ static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, @@ -857,8 +868,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .num_clks = ARRAY_SIZE(msm8998_clks), }; -DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, - 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000); diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 860dd8cdf9f3..82c9d489833a 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -40,6 +40,7 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_AGGR_CLK 0x72676761 #define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768 #define QCOM_SMD_RPM_PKA_CLK 0x616b70 +#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, -- cgit v1.2.3 From 89f0f1a4601562481b57f61988da7fdb62dfce82 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 26 Feb 2022 22:41:26 +0100 Subject: clk: qcom: smd: Add missing MSM8998 RPM clocks Add missing RPM-provided clocks on msm8998 and reorder the definitions where needed. Tested-by: Jami Kettunen Signed-off-by: Konrad Dybcio Tested-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226214126.21209-3-konrad.dybcio@somainline.org --- drivers/clk/qcom/clk-smd-rpm.c | 40 +++++++++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 13 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 418f017e933f..afc6dc930011 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -816,15 +816,18 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, - 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000); + static struct clk_smd_rpm *msm8998_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, @@ -837,12 +840,22 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -855,10 +868,14 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3, [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a, + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin, [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin, }; @@ -868,9 +885,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .num_clks = ARRAY_SIZE(msm8998_clks), }; -DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000); - static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -900,16 +914,16 @@ static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin, - [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a, + [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, + [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { @@ -1011,8 +1025,8 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, -- cgit v1.2.3 From 58922910add18583d5273c2edcdb9fd7bf4eca02 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sun, 27 Feb 2022 23:25:35 +0530 Subject: clk: qcom: clk-rcg2: Update logic to calculate D value for RCG The display pixel clock has a requirement on certain newer platforms to support M/N as (2/3) and the final D value calculated results in underflow errors. As the current implementation does not check for D value is within the accepted range for a given M & N value. Update the logic to calculate the final D value based on the range. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org --- drivers/clk/qcom/clk-rcg2.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index e1b1b426fae4..b831975a9606 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { - u32 cfg, mask; + u32 cfg, mask, d_val, not2d_val, n_minus_m; struct clk_hw *hw = &rcg->clkr.hw; int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); @@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (ret) return ret; + /* Calculate 2d value */ + d_val = f->n; + + n_minus_m = f->n - f->m; + n_minus_m *= 2; + + d_val = clamp_t(u32, d_val, f->m, n_minus_m); + not2d_val = ~d_val & mask; + ret = regmap_update_bits(rcg->clkr.regmap, - RCG_D_OFFSET(rcg), mask, ~f->n); + RCG_D_OFFSET(rcg), mask, not2d_val); if (ret) return ret; } -- cgit v1.2.3 From b527358cb4cd58a8279c9062b0786f1fab628fdc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sun, 27 Feb 2022 23:25:36 +0530 Subject: clk: qcom: clk-rcg2: Update the frac table for pixel clock Support the new numerator and denominator for pixel clock on SM8350 and support rgb101010, RGB888 use cases on SM8450. Fixes: 99cbd064b059f ("clk: qcom: Support display RCG clocks") Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220227175536.3131-2-tdas@codeaurora.org --- drivers/clk/qcom/clk-rcg2.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index b831975a9606..f675fd969c4d 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -729,6 +729,7 @@ static const struct frac_entry frac_table_pixel[] = { { 2, 9 }, { 4, 9 }, { 1, 1 }, + { 2, 3 }, { } }; -- cgit v1.2.3 From 2dc63e768ce2fbf24cb49c858f549596bb30a0a0 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 3 Mar 2022 02:00:41 +0530 Subject: clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 Add the PCIe0 and PCIe1 GDSC defines & driver structures for SM8150. Cc: Stephen Boyd Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302203045.184500-4-bhupesh.sharma@linaro.org --- drivers/clk/qcom/gcc-sm8150.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 ++ 2 files changed, 22 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 245794485719..7e478dc2cefe 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3448,6 +3448,24 @@ static struct clk_branch gcc_video_xo_clk = { }, }; +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x6b004, + .pd = { + .name = "pcie_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x8d004, + .pd = { + .name = "pcie_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + static struct gdsc usb30_prim_gdsc = { .gdscr = 0xf004, .pd = { @@ -3714,6 +3732,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { }; static struct gdsc *gcc_sm8150_gdscs[] = { + [PCIE_0_GDSC] = &pcie_0_gdsc, + [PCIE_1_GDSC] = &pcie_1_gdsc, [USB30_PRIM_GDSC] = &usb30_prim_gdsc, [USB30_SEC_GDSC] = &usb30_sec_gdsc, }; diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 3e1a91876610..ae9c16410420 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -241,6 +241,8 @@ #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 /* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 -- cgit v1.2.3 From 2fb605a1a529d366513fd223b4ee7c75db2db7e8 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 3 Mar 2022 13:51:39 +0530 Subject: clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 Add the UFS_CARD and UFS_PHY GDSC defines & driver structures for SM8150. Cc: Stephen Boyd Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220303082140.240745-2-bhupesh.sharma@linaro.org --- drivers/clk/qcom/gcc-sm8150.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 2 ++ 2 files changed, 22 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 7e478dc2cefe..1ba2714d387c 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3466,6 +3466,24 @@ static struct gdsc pcie_1_gdsc = { .flags = POLL_CFG_GDSCR, }; +static struct gdsc ufs_card_gdsc = { + .gdscr = 0x75004, + .pd = { + .name = "ufs_card_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + +static struct gdsc ufs_phy_gdsc = { + .gdscr = 0x77004, + .pd = { + .name = "ufs_phy_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + static struct gdsc usb30_prim_gdsc = { .gdscr = 0xf004, .pd = { @@ -3734,6 +3752,8 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { static struct gdsc *gcc_sm8150_gdscs[] = { [PCIE_0_GDSC] = &pcie_0_gdsc, [PCIE_1_GDSC] = &pcie_1_gdsc, + [UFS_CARD_GDSC] = &ufs_card_gdsc, + [UFS_PHY_GDSC] = &ufs_phy_gdsc, [USB30_PRIM_GDSC] = &usb30_prim_gdsc, [USB30_SEC_GDSC] = &usb30_sec_gdsc, }; diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index ae9c16410420..d70ab54c44c7 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -243,6 +243,8 @@ /* GCC GDSCRs */ #define PCIE_0_GDSC 0 #define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 -- cgit v1.2.3 From fb0c4f9d72937670f38e7031d9aaf6589a00f454 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 3 Mar 2022 14:18:20 +0530 Subject: clk: qcom: gcc: sm8150: Fix some identation issues Fix identation issues with usb30 gdsc structs in gcc-sm8150. Cc: Stephen Boyd Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220303084824.284946-3-bhupesh.sharma@linaro.org --- drivers/clk/qcom/gcc-sm8150.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 1ba2714d387c..f510b8462509 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3485,21 +3485,21 @@ static struct gdsc ufs_phy_gdsc = { }; static struct gdsc usb30_prim_gdsc = { - .gdscr = 0xf004, - .pd = { - .name = "usb30_prim_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .gdscr = 0xf004, + .pd = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, }; static struct gdsc usb30_sec_gdsc = { - .gdscr = 0x10004, - .pd = { - .name = "usb30_sec_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR, + .gdscr = 0x10004, + .pd = { + .name = "usb30_sec_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, }; static struct clk_regmap *gcc_sm8150_clocks[] = { -- cgit v1.2.3 From d1a16e345578332c31aa4fb7b76e2e38249861ad Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 3 Mar 2022 14:18:21 +0530 Subject: clk: qcom: gcc: Add emac GDSC support for SM8150 Add the EMAC GDSC defines and driver structures for SM8150. Cc: Stephen Boyd Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220303084824.284946-4-bhupesh.sharma@linaro.org --- drivers/clk/qcom/gcc-sm8150.c | 10 ++++++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 1 + 2 files changed, 11 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index f510b8462509..09cf827addab 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -3484,6 +3484,15 @@ static struct gdsc ufs_phy_gdsc = { .flags = POLL_CFG_GDSCR, }; +static struct gdsc emac_gdsc = { + .gdscr = 0x6004, + .pd = { + .name = "emac_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + static struct gdsc usb30_prim_gdsc = { .gdscr = 0xf004, .pd = { @@ -3750,6 +3759,7 @@ static const struct qcom_reset_map gcc_sm8150_resets[] = { }; static struct gdsc *gcc_sm8150_gdscs[] = { + [EMAC_GDSC] = &emac_gdsc, [PCIE_0_GDSC] = &pcie_0_gdsc, [PCIE_1_GDSC] = &pcie_1_gdsc, [UFS_CARD_GDSC] = &ufs_card_gdsc, diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index d70ab54c44c7..dfefd5e8bf6e 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -247,5 +247,6 @@ #define UFS_PHY_GDSC 3 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 +#define EMAC_GDSC 6 #endif -- cgit v1.2.3 From 620f512528389929d9af795f82c63e52a589b53c Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Thu, 3 Mar 2022 14:18:10 +0100 Subject: clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig In order to keep at least the list of `CONFIG_SM_` drivers sorted alphabetically, SDX_GCC_65 should have been moved one line up. This in turn makes it easier and cleaner to add the followup SM_DISPCC_6125 driver in the right place, right before SM_DISPCC_8250. Fixes: d79afa201328 ("clk: qcom: Add SDX65 GCC support") Signed-off-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220303131812.302302-2-marijn.suijten@somainline.org --- drivers/clk/qcom/Kconfig | 14 +++++++------- drivers/clk/qcom/Makefile | 2 +- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 204438ceabf3..ffeafa362906 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -574,13 +574,6 @@ config SDX_GCC_55 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. -config SM_CAMCC_8250 - tristate "SM8250 Camera Clock Controller" - select SM_GCC_8250 - help - Support for the camera clock controller on SM8250 devices. - Say Y if you want to support camera devices and camera functionality. - config SDX_GCC_65 tristate "SDX65 Global Clock Controller" select QCOM_GDSC @@ -589,6 +582,13 @@ config SDX_GCC_65 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_CAMCC_8250 + tristate "SM8250 Camera Clock Controller" + select SM_GCC_8250 + help + Support for the camera clock controller on SM8250 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_DISPCC_8250 tristate "SM8150 and SM8250 Display Clock Controller" depends on SM_GCC_8150 || SM_GCC_8250 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index fca999afc760..04440c31f325 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -84,8 +84,8 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o -obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o +obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o -- cgit v1.2.3 From 6e87c8f074075e10c5352d3256879b4e6dd6cb81 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Thu, 3 Mar 2022 14:18:12 +0100 Subject: clk: qcom: Add display clock controller driver for SM6125 Add support for the display clock controller found on SM6125 based devices. This allows display drivers to probe and control their clocks. Signed-off-by: Martin Botka Signed-off-by: Marijn Suijten Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc-sm6125.c | 709 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 719 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-sm6125.c (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ffeafa362906..d01436be6d7a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -589,6 +589,15 @@ config SM_CAMCC_8250 Support for the camera clock controller on SM8250 devices. Say Y if you want to support camera devices and camera functionality. +config SM_DISPCC_6125 + tristate "SM6125 Display Clock Controller" + depends on SM_GCC_6125 + help + Support for the display clock controller on Qualcomm Technologies, Inc + SM6125 devices. + Say Y if you want to support display devices and functionality such as + splash screen + config SM_DISPCC_8250 tristate "SM8150 and SM8250 Display Clock Controller" depends on SM_GCC_8150 || SM_GCC_8250 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 04440c31f325..671cf5821af1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o +obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c new file mode 100644 index 000000000000..b921456a2e0d --- /dev/null +++ b/drivers/clk/qcom/dispcc-sm6125.c @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" + +enum { + P_BI_TCXO, + P_DISP_CC_PLL0_OUT_MAIN, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, +}; + +static struct pll_vco disp_cc_pll_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = disp_cc_pll_vco, + .num_vco = ARRAY_SIZE(disp_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +/* 768MHz configuration */ +static const struct alpha_pll_config disp_cc_pll0_config = { + .l = 0x28, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = BIT(0), + .config_ctl_val = 0x4001055b, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dp_phy_pll_link_clk" }, + { .fw_name = "dp_phy_pll_vco_div_clk" }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk" }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_div_clk_src" }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 4 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "gcc_disp_gpll0_div_clk_src" }, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "dsi1_phy_pll_out_dsiclk" }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x20bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x213c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { + F( 180000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + F( 360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x210c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { + F( 162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F( 270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F( 540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x20f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x2124, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x20d8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x2074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x205c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_pixel_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x208c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x20a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x2024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x2028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x2040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x2038, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2038, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x2030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x203c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x202c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x202c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x2008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x2018, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x2018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x2010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x2020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_xo_clk = { + .halt_reg = 0x604c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x604c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_xo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x3000, + .pd = { + .name = "mdss_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL, +}; + +static struct clk_regmap *disp_cc_sm6125_clocks[] = { + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, + [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, + [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, + [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, +}; + +static struct gdsc *disp_cc_sm6125_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, +}; + +static const struct regmap_config disp_cc_sm6125_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_sm6125_desc = { + .config = &disp_cc_sm6125_regmap_config, + .clks = disp_cc_sm6125_clocks, + .num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks), + .gdscs = disp_cc_sm6125_gdscs, + .num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs), +}; + +static const struct of_device_id disp_cc_sm6125_match_table[] = { + { .compatible = "qcom,dispcc-sm6125" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_sm6125_match_table); + +static int disp_cc_sm6125_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &disp_cc_sm6125_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); + + return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap); +} + +static struct platform_driver disp_cc_sm6125_driver = { + .probe = disp_cc_sm6125_probe, + .driver = { + .name = "disp_cc-sm6125", + .of_match_table = disp_cc_sm6125_match_table, + }, +}; + +static int __init disp_cc_sm6125_init(void) +{ + return platform_driver_register(&disp_cc_sm6125_driver); +} +subsys_initcall(disp_cc_sm6125_init); + +static void __exit disp_cc_sm6125_exit(void) +{ + platform_driver_unregister(&disp_cc_sm6125_driver); +} +module_exit(disp_cc_sm6125_exit); + +MODULE_DESCRIPTION("QTI DISPCC SM6125 Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 3e6054d043c01e0d47a51cddc814f8d3409fc355 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 3 Mar 2022 09:05:08 +0000 Subject: clk: imx: remove redundant re-assignment of pll->base There are two identical assignments of pll->base to the same value, the second assignment is redundant and can be removed. Cleans up cppcheck warning: drivers/clk/imx/clk-sscg-pll.c:528:12: style: Variable 'pll->base' is reassigned a value before the old one has been used. [redundantAssignment] Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20220303090508.1125175-1-colin.i.king@gmail.com Signed-off-by: Stephen Boyd --- drivers/clk/imx/clk-sscg-pll.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/clk-sscg-pll.c b/drivers/clk/imx/clk-sscg-pll.c index 9d6cdff0537f..81f304fae908 100644 --- a/drivers/clk/imx/clk-sscg-pll.c +++ b/drivers/clk/imx/clk-sscg-pll.c @@ -525,7 +525,6 @@ struct clk_hw *imx_clk_hw_sscg_pll(const char *name, init.parent_names = parent_names; init.num_parents = num_parents; - pll->base = base; pll->hw.init = &init; hw = &pll->hw; -- cgit v1.2.3 From 40dda3532f903107a063cd6ec1f15e10dd0eccc5 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 26 Jan 2022 18:39:47 +0100 Subject: clk: starfive: jh7100: Don't round divisor up twice The problem is best illustrated by an example. Suppose a consumer wants a 4MHz clock rate from a divider with a 10MHz parent. It would then call clk_round_rate(clk, 4000000) which would call into our determine_rate() callback that correctly rounds up and finds that a divisor of 3 gives the highest possible frequency below the requested 4MHz and returns 10000000 / 3 = 3333333Hz. However the consumer would then call clk_set_rate(clk, 3333333) but since 3333333 doesn't divide 10000000 evenly our set_rate() callback would again round the divisor up and set it to 4 which results in an unnecessarily low rate of 2.5MHz. Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback. Fixes: 4210be668a09 ("clk: starfive: Add JH7100 clock generator driver") Signed-off-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20220126173953.1016706-2-kernel@esmil.dk Signed-off-by: Stephen Boyd --- drivers/clk/starfive/clk-starfive-jh7100.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index 25d31afa0f87..db6a4dc203af 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -399,22 +399,13 @@ static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw, return div ? parent_rate / div : 0; } -static unsigned long jh7100_clk_bestdiv(struct jh7100_clk *clk, - unsigned long rate, unsigned long parent) -{ - unsigned long max = clk->max_div; - unsigned long div = DIV_ROUND_UP(parent, rate); - - return min(div, max); -} - static int jh7100_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct jh7100_clk *clk = jh7100_clk_from(hw); unsigned long parent = req->best_parent_rate; unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); - unsigned long div = jh7100_clk_bestdiv(clk, rate, parent); + unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); unsigned long result = parent / div; /* @@ -442,7 +433,8 @@ static int jh7100_clk_set_rate(struct clk_hw *hw, unsigned long parent_rate) { struct jh7100_clk *clk = jh7100_clk_from(hw); - unsigned long div = jh7100_clk_bestdiv(clk, rate, parent_rate); + unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), + 1UL, (unsigned long)clk->max_div); jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); return 0; -- cgit v1.2.3 From 73bfc8d745a98744088cb30517399222674455b1 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 26 Jan 2022 18:39:48 +0100 Subject: clk: starfive: jh7100: Handle audio_div clock properly It turns out the audio_div clock is a fractional divider where the lowest byte of the ctrl register is the integer part of the divider and the 2nd byte is the number of 100th added to the divider. The children of this clock is used by the audio peripherals for their sample rate clock, so round to the closest possible rate rather than always rounding down like regular dividers. Fixes: 4210be668a09 ("clk: starfive: Add JH7100 clock generator driver") Signed-off-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20220126173953.1016706-3-kernel@esmil.dk Signed-off-by: Stephen Boyd --- drivers/clk/starfive/clk-starfive-jh7100.c | 68 +++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index db6a4dc203af..4b59338b5d7d 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -32,6 +32,13 @@ #define JH7100_CLK_MUX_MASK GENMASK(27, 24) #define JH7100_CLK_MUX_SHIFT 24 #define JH7100_CLK_DIV_MASK GENMASK(23, 0) +#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) +#define JH7100_CLK_FRAC_SHIFT 8 +#define JH7100_CLK_INT_MASK GENMASK(7, 0) + +/* fractional divider min/max */ +#define JH7100_CLK_FRAC_MIN 100UL +#define JH7100_CLK_FRAC_MAX 25599UL /* clock data */ #define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ @@ -55,6 +62,13 @@ .parents = { [0] = _parent }, \ } +#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = JH7100_CLK_FRAC_MAX, \ + .parents = { [0] = _parent }, \ +} + #define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ .name = _name, \ .flags = 0, \ @@ -225,7 +239,7 @@ static const struct { JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, JH7100_CLK_OSC_SYS, JH7100_CLK_USBPHY_PLLDIV25M), - JH7100__DIV(JH7100_CLK_AUDIO_DIV, "audio_div", 131072, JH7100_CLK_AUDIO_ROOT), + JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), @@ -440,6 +454,49 @@ static int jh7100_clk_set_rate(struct clk_hw *hw, return 0; } +static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + u32 reg = jh7100_clk_reg_get(clk); + unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) + + ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT); + + return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; +} + +static int jh7100_clk_frac_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long parent100 = 100 * req->best_parent_rate; + unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); + unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate), + JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); + unsigned long result = parent100 / div100; + + /* clamp the result as in jh7100_clk_determine_rate() above */ + if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX) + result = parent100 / (div100 + 1); + if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN) + result = parent100 / (div100 - 1); + + req->rate = result; + return 0; +} + +static int jh7100_clk_frac_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct jh7100_clk *clk = jh7100_clk_from(hw); + unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate), + JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); + u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100); + + jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value); + return 0; +} + static u8 jh7100_clk_get_parent(struct clk_hw *hw) { struct jh7100_clk *clk = jh7100_clk_from(hw); @@ -526,6 +583,13 @@ static const struct clk_ops jh7100_clk_div_ops = { .debug_init = jh7100_clk_debug_init, }; +static const struct clk_ops jh7100_clk_fdiv_ops = { + .recalc_rate = jh7100_clk_frac_recalc_rate, + .determine_rate = jh7100_clk_frac_determine_rate, + .set_rate = jh7100_clk_frac_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + static const struct clk_ops jh7100_clk_gdiv_ops = { .enable = jh7100_clk_enable, .disable = jh7100_clk_disable, @@ -564,6 +628,8 @@ static const struct clk_ops *__init jh7100_clk_ops(u32 max) if (max & JH7100_CLK_DIV_MASK) { if (max & JH7100_CLK_ENABLE) return &jh7100_clk_gdiv_ops; + if (max == JH7100_CLK_FRAC_MAX) + return &jh7100_clk_fdiv_ops; return &jh7100_clk_div_ops; } -- cgit v1.2.3 From 26ad971faa07951179ae6d39f91b6622da4d020c Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 26 Jan 2022 18:39:51 +0100 Subject: clk: starfive: jh7100: Make hw clock implementation reusable The JH7100 has additional audio and video clocks at different memory ranges, but they use the same register layout. Add a header and export the starfive_jh7100_clk_ops function so the clock implementation can be reused by drivers handling these clocks. Signed-off-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20220126173953.1016706-6-kernel@esmil.dk Signed-off-by: Stephen Boyd --- drivers/clk/starfive/clk-starfive-jh7100.c | 96 +++-------------------------- drivers/clk/starfive/clk-starfive-jh7100.h | 97 ++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 89 deletions(-) create mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h (limited to 'drivers/clk') diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index 4b59338b5d7d..a6708f9ebf4c 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -20,83 +20,15 @@ #include +#include "clk-starfive-jh7100.h" + /* external clocks */ #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0) #define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1) #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2) #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) -/* register fields */ -#define JH7100_CLK_ENABLE BIT(31) -#define JH7100_CLK_INVERT BIT(30) -#define JH7100_CLK_MUX_MASK GENMASK(27, 24) -#define JH7100_CLK_MUX_SHIFT 24 -#define JH7100_CLK_DIV_MASK GENMASK(23, 0) -#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) -#define JH7100_CLK_FRAC_SHIFT 8 -#define JH7100_CLK_INT_MASK GENMASK(7, 0) - -/* fractional divider min/max */ -#define JH7100_CLK_FRAC_MIN 100UL -#define JH7100_CLK_FRAC_MAX 25599UL - -/* clock data */ -#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ - .name = _name, \ - .flags = CLK_SET_RATE_PARENT | (_flags), \ - .max = JH7100_CLK_ENABLE, \ - .parents = { [0] = _parent }, \ -} - -#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ - .name = _name, \ - .flags = 0, \ - .max = _max, \ - .parents = { [0] = _parent }, \ -} - -#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ - .name = _name, \ - .flags = _flags, \ - .max = JH7100_CLK_ENABLE | (_max), \ - .parents = { [0] = _parent }, \ -} - -#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ - .name = _name, \ - .flags = 0, \ - .max = JH7100_CLK_FRAC_MAX, \ - .parents = { [0] = _parent }, \ -} - -#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ - .name = _name, \ - .flags = 0, \ - .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ - .parents = { __VA_ARGS__ }, \ -} - -#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ - .name = _name, \ - .flags = _flags, \ - .max = JH7100_CLK_ENABLE | \ - (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ - .parents = { __VA_ARGS__ }, \ -} - -#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ - .name = _name, \ - .flags = CLK_SET_RATE_PARENT, \ - .max = JH7100_CLK_INVERT, \ - .parents = { [0] = _parent }, \ -} - -static const struct { - const char *name; - unsigned long flags; - u32 max; - u8 parents[4]; -} jh7100_clk_data[] __initconst = { +static const struct jh7100_clk_data jh7100_clk_data[] __initconst = { JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, JH7100_CLK_OSC_SYS, JH7100_CLK_PLL0_OUT, @@ -337,21 +269,6 @@ static const struct { JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), }; -struct jh7100_clk { - struct clk_hw hw; - unsigned int idx; - unsigned int max_div; -}; - -struct jh7100_clk_priv { - /* protect clk enable and set rate/parent from happening at the same time */ - spinlock_t rmw_lock; - struct device *dev; - void __iomem *base; - struct clk_hw *pll[3]; - struct jh7100_clk reg[JH7100_CLK_PLL0_OUT]; -}; - static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) { return container_of(hw, struct jh7100_clk, hw); @@ -623,7 +540,7 @@ static const struct clk_ops jh7100_clk_inv_ops = { .debug_init = jh7100_clk_debug_init, }; -static const struct clk_ops *__init jh7100_clk_ops(u32 max) +const struct clk_ops *starfive_jh7100_clk_ops(u32 max) { if (max & JH7100_CLK_DIV_MASK) { if (max & JH7100_CLK_ENABLE) @@ -644,6 +561,7 @@ static const struct clk_ops *__init jh7100_clk_ops(u32 max) return &jh7100_clk_inv_ops; } +EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops); static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) { @@ -665,7 +583,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) unsigned int idx; int ret; - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL); if (!priv) return -ENOMEM; @@ -695,7 +613,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7100_clk_data[idx].name, - .ops = jh7100_clk_ops(max), + .ops = starfive_jh7100_clk_ops(max), .parent_data = parents, .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, .flags = jh7100_clk_data[idx].flags, diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h new file mode 100644 index 000000000000..8eccd8c0a746 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7100.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CLK_STARFIVE_JH7100_H +#define __CLK_STARFIVE_JH7100_H + +#include +#include + +/* register fields */ +#define JH7100_CLK_ENABLE BIT(31) +#define JH7100_CLK_INVERT BIT(30) +#define JH7100_CLK_MUX_MASK GENMASK(27, 24) +#define JH7100_CLK_MUX_SHIFT 24 +#define JH7100_CLK_DIV_MASK GENMASK(23, 0) +#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) +#define JH7100_CLK_FRAC_SHIFT 8 +#define JH7100_CLK_INT_MASK GENMASK(7, 0) + +/* fractional divider min/max */ +#define JH7100_CLK_FRAC_MIN 100UL +#define JH7100_CLK_FRAC_MAX 25599UL + +/* clock data */ +struct jh7100_clk_data { + const char *name; + unsigned long flags; + u32 max; + u8 parents[4]; +}; + +#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT | (_flags), \ + .max = JH7100_CLK_ENABLE, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = _max, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | (_max), \ + .parents = { [0] = _parent }, \ +} + +#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = JH7100_CLK_FRAC_MAX, \ + .parents = { [0] = _parent }, \ +} + +#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | \ + (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT, \ + .max = JH7100_CLK_INVERT, \ + .parents = { [0] = _parent }, \ +} + +struct jh7100_clk { + struct clk_hw hw; + unsigned int idx; + unsigned int max_div; +}; + +struct jh7100_clk_priv { + /* protect clk enable and set rate/parent from happening at the same time */ + spinlock_t rmw_lock; + struct device *dev; + void __iomem *base; + struct clk_hw *pll[3]; + struct jh7100_clk reg[]; +}; + +const struct clk_ops *starfive_jh7100_clk_ops(u32 max); + +#endif -- cgit v1.2.3 From 8c373f8c793cc1bb8f708433dcb8343ba078bd17 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 26 Jan 2022 18:39:52 +0100 Subject: clk: starfive: jh7100: Support more clock types Unlike the system clocks there are audio clocks that combine both multiplexer/divider and gate/multiplexer/divider, so add support for that. Signed-off-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20220126173953.1016706-7-kernel@esmil.dk Signed-off-by: Stephen Boyd --- drivers/clk/starfive/clk-starfive-jh7100.c | 26 ++++++++++++++++++++++++++ drivers/clk/starfive/clk-starfive-jh7100.h | 15 +++++++++++++++ 2 files changed, 41 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index a6708f9ebf4c..691aeebc7092 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -534,6 +534,27 @@ static const struct clk_ops jh7100_clk_gmux_ops = { .debug_init = jh7100_clk_debug_init, }; +static const struct clk_ops jh7100_clk_mdiv_ops = { + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + +static const struct clk_ops jh7100_clk_gmd_ops = { + .enable = jh7100_clk_enable, + .disable = jh7100_clk_disable, + .is_enabled = jh7100_clk_is_enabled, + .recalc_rate = jh7100_clk_recalc_rate, + .determine_rate = jh7100_clk_determine_rate, + .get_parent = jh7100_clk_get_parent, + .set_parent = jh7100_clk_set_parent, + .set_rate = jh7100_clk_set_rate, + .debug_init = jh7100_clk_debug_init, +}; + static const struct clk_ops jh7100_clk_inv_ops = { .get_phase = jh7100_clk_get_phase, .set_phase = jh7100_clk_set_phase, @@ -543,6 +564,11 @@ static const struct clk_ops jh7100_clk_inv_ops = { const struct clk_ops *starfive_jh7100_clk_ops(u32 max) { if (max & JH7100_CLK_DIV_MASK) { + if (max & JH7100_CLK_MUX_MASK) { + if (max & JH7100_CLK_ENABLE) + return &jh7100_clk_gmd_ops; + return &jh7100_clk_mdiv_ops; + } if (max & JH7100_CLK_ENABLE) return &jh7100_clk_gdiv_ops; if (max == JH7100_CLK_FRAC_MAX) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h index 8eccd8c0a746..f116be5740a5 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.h +++ b/drivers/clk/starfive/clk-starfive-jh7100.h @@ -70,6 +70,21 @@ struct jh7100_clk_data { .parents = { __VA_ARGS__ }, \ } +#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ +} + +#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \ + .name = _name, \ + .flags = _flags, \ + .max = JH7100_CLK_ENABLE | \ + (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ +} + #define JH7100__INV(_idx, _name, _parent) [_idx] = { \ .name = _name, \ .flags = CLK_SET_RATE_PARENT, \ -- cgit v1.2.3 From 3028181ea3b8e2054d62dc013318c44f93333248 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Wed, 26 Jan 2022 18:39:53 +0100 Subject: clk: starfive: Add JH7100 audio clock driver Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20220126173953.1016706-8-kernel@esmil.dk Signed-off-by: Stephen Boyd --- MAINTAINERS | 8 +- drivers/clk/starfive/Kconfig | 8 ++ drivers/clk/starfive/Makefile | 1 + drivers/clk/starfive/clk-starfive-jh7100-audio.c | 170 +++++++++++++++++++++++ 4 files changed, 183 insertions(+), 4 deletions(-) create mode 100644 drivers/clk/starfive/clk-starfive-jh7100-audio.c (limited to 'drivers/clk') diff --git a/MAINTAINERS b/MAINTAINERS index ea3e6c914384..19a855f3fdca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18376,12 +18376,12 @@ M: Ion Badulescu S: Odd Fixes F: drivers/net/ethernet/adaptec/starfire* -STARFIVE JH7100 CLOCK DRIVER +STARFIVE JH7100 CLOCK DRIVERS M: Emil Renner Berthing S: Maintained -F: Documentation/devicetree/bindings/clock/starfive,jh7100-clkgen.yaml -F: drivers/clk/starfive/clk-starfive-jh7100.c -F: include/dt-bindings/clock/starfive-jh7100.h +F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml +F: drivers/clk/starfive/clk-starfive-jh7100* +F: include/dt-bindings/clock/starfive-jh7100*.h STARFIVE JH7100 PINCTRL DRIVER M: Emil Renner Berthing diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index c0fa9d5e641f..003bd2d56ce7 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -7,3 +7,11 @@ config CLK_STARFIVE_JH7100 help Say yes here to support the clock controller on the StarFive JH7100 SoC. + +config CLK_STARFIVE_JH7100_AUDIO + tristate "StarFive JH7100 audio clock support" + depends on CLK_STARFIVE_JH7100 + default m if SOC_STARFIVE + help + Say Y or M here to support the audio clocks on the StarFive JH7100 + SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index 09759cc73530..0fa8ecb9ec1c 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 # StarFive Clock obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o +obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c new file mode 100644 index 000000000000..8473a65e219b --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JH7100 Audio Clock Driver + * + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-starfive-jh7100.h" + +/* external clocks */ +#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0) +#define JH7100_AUDCLK_AUDIO_12288 (JH7100_AUDCLK_END + 1) +#define JH7100_AUDCLK_DOM7AHB_BUS (JH7100_AUDCLK_END + 2) +#define JH7100_AUDCLK_I2SADC_BCLK_IOPAD (JH7100_AUDCLK_END + 3) +#define JH7100_AUDCLK_I2SADC_LRCLK_IOPAD (JH7100_AUDCLK_END + 4) +#define JH7100_AUDCLK_I2SDAC_BCLK_IOPAD (JH7100_AUDCLK_END + 5) +#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6) +#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7) + +static const struct jh7100_clk_data jh7100_audclk_data[] = { + JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, + JH7100_AUDCLK_ADC_MCLK, + JH7100_AUDCLK_I2SADC_BCLK_IOPAD), + JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), + JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, + JH7100_AUDCLK_I2SADC_BCLK_N, + JH7100_AUDCLK_I2SADC_LRCLK_IOPAD, + JH7100_AUDCLK_I2SADC_BCLK), + JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, + JH7100_AUDCLK_DAC_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), + JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), + JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, + JH7100_AUDCLK_I2S1_BCLK_N, + JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD), + JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), + JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), + JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), + JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), + JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), + JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), + JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), + JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, + JH7100_AUDCLK_VAD_INTMEM, + JH7100_AUDCLK_AUDIO_12288), +}; + +static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data) +{ + struct jh7100_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7100_AUDCLK_END) + return &priv->reg[idx].hw; + + return ERR_PTR(-EINVAL); +} + +static int jh7100_audclk_probe(struct platform_device *pdev) +{ + struct jh7100_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + for (idx = 0; idx < JH7100_AUDCLK_END; idx++) { + u32 max = jh7100_audclk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7100_audclk_data[idx].name, + .ops = starfive_jh7100_clk_ops(max), + .parent_data = parents, + .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, + .flags = jh7100_audclk_data[idx].flags, + }; + struct jh7100_clk *clk = &priv->reg[idx]; + unsigned int i; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jh7100_audclk_data[idx].parents[i]; + + if (pidx < JH7100_AUDCLK_END) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx == JH7100_AUDCLK_AUDIO_SRC) + parents[i].fw_name = "audio_src"; + else if (pidx == JH7100_AUDCLK_AUDIO_12288) + parents[i].fw_name = "audio_12288"; + else if (pidx == JH7100_AUDCLK_DOM7AHB_BUS) + parents[i].fw_name = "dom7ahb_bus"; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & JH7100_CLK_DIV_MASK; + + ret = devm_clk_hw_register(priv->dev, &clk->hw); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(priv->dev, jh7100_audclk_get, priv); +} + +static const struct of_device_id jh7100_audclk_match[] = { + { .compatible = "starfive,jh7100-audclk" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7100_audclk_match); + +static struct platform_driver jh7100_audclk_driver = { + .probe = jh7100_audclk_probe, + .driver = { + .name = "clk-starfive-jh7100-audio", + .of_match_table = jh7100_audclk_match, + }, +}; +module_platform_driver(jh7100_audclk_driver); + +MODULE_AUTHOR("Emil Renner Berthing"); +MODULE_DESCRIPTION("StarFive JH7100 audio clock driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 78ab3a9a3d57193f7080422aea30bf5905608b7d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:42 +0200 Subject: clk: ti: Constify clkctrl_name We can constify clkctrl_name in preparation for making use of the clock-output-names property. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-2-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/clkctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 864c484bde1b..0049828db0e9 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -505,7 +505,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) struct omap_clkctrl_clk *clkctrl_clk = NULL; const __be32 *addrp; bool legacy_naming; - char *clkctrl_name; + const char *clkctrl_name; u32 addr; int ret; char *c; -- cgit v1.2.3 From 80864594ff2ad002e2755daf97d46ff0c86faf1f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:43 +0200 Subject: clk: ti: Preserve node in ti_dt_clocks_register() In preparation for making use of the clock-output-names, we want to keep node around in ti_dt_clocks_register(). This change should not needed as a fix currently. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-3-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/clk.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 3da33c786d77..29eafab4353e 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -131,7 +131,7 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) { struct ti_dt_clk *c; - struct device_node *node, *parent; + struct device_node *node, *parent, *child; struct clk *clk; struct of_phandle_args clkspec; char buf[64]; @@ -171,10 +171,13 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) node = of_find_node_by_name(NULL, buf); if (num_args && compat_mode) { parent = node; - node = of_get_child_by_name(parent, "clock"); - if (!node) - node = of_get_child_by_name(parent, "clk"); - of_node_put(parent); + child = of_get_child_by_name(parent, "clock"); + if (!child) + child = of_get_child_by_name(parent, "clk"); + if (child) { + of_node_put(parent); + node = child; + } } clkspec.np = node; -- cgit v1.2.3 From 274d679810dab8a7dd5042826979d6ef014007a5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:44 +0200 Subject: clk: ti: Optionally parse IO address from parent clock node If no reg property is specified for a TI clock, let's try to use the parent clock node IO address. This way we can avoid duplicate devicetree reg properties that cause warnings for unique_unit_address. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-4-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/clk.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 29eafab4353e..a0ddf16f0eca 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -274,6 +274,8 @@ int ti_clk_get_reg_addr(struct device_node *node, int index, for (i = 0; i < CLK_MAX_MEMMAPS; i++) { if (clocks_node_ptr[i] == node->parent) break; + if (clocks_node_ptr[i] == node->parent->parent) + break; } if (i == CLK_MAX_MEMMAPS) { @@ -284,8 +286,12 @@ int ti_clk_get_reg_addr(struct device_node *node, int index, reg->index = i; if (of_property_read_u32_index(node, "reg", index, &val)) { - pr_err("%pOFn must have reg[%d]!\n", node, index); - return -EINVAL; + if (of_property_read_u32_index(node->parent, "reg", + index, &val)) { + pr_err("%pOFn or parent must have reg[%d]!\n", + node, index); + return -EINVAL; + } } reg->offset = val; -- cgit v1.2.3 From 51f661ef9a106e908097262ff5034a85ce15b122 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:45 +0200 Subject: clk: ti: Add ti_find_clock_provider() to use clock-output-names Let's add ti_find_clock_provider() so we can use clock-output-names to name the clock provider instead of relying on non-standard devicetree node names. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-5-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/clk.c | 43 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index a0ddf16f0eca..6fcbd801e8f1 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -119,12 +119,51 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) return 0; } +/* + * Eventually we could standardize to using '_' for clk-*.c files to follow the + * TRM naming and leave out the tmp name here. + */ +static struct device_node *ti_find_clock_provider(struct device_node *from, + const char *name) +{ + struct device_node *np; + bool found = false; + const char *n; + char *tmp; + + tmp = kstrdup(name, GFP_KERNEL); + if (!tmp) + return NULL; + strreplace(tmp, '-', '_'); + + /* Node named "clock" with "clock-output-names" */ + for_each_of_allnodes_from(from, np) { + if (of_property_read_string_index(np, "clock-output-names", + 0, &n)) + continue; + + if (!strncmp(n, tmp, strlen(tmp))) { + found = true; + break; + } + } + of_node_put(from); + kfree(tmp); + + if (found) + return np; + + /* Fall back to using old node name base provider name */ + return of_find_node_by_name(from, name); +} + /** * ti_dt_clocks_register - register DT alias clocks during boot * @oclks: list of clocks to register * * Register alias or non-standard DT clock entries during boot. By - * default, DT clocks are found based on their node name. If any + * default, DT clocks are found based on their clock-output-names + * property, or the clock node name for legacy cases. If any * additional con-id / dev-id -> clock mapping is required, use this * function to list these. */ @@ -168,7 +207,7 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[]) if (num_args && clkctrl_nodes_missing) continue; - node = of_find_node_by_name(NULL, buf); + node = ti_find_clock_provider(NULL, buf); if (num_args && compat_mode) { parent = node; child = of_get_child_by_name(parent, "clock"); -- cgit v1.2.3 From d02747e9894c66940db6859c273ab3000c730a93 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:46 +0200 Subject: clk: ti: Use clock-output-names for clkctrl Use clock-output-names devicetree property for clkctrl clocks if available. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-6-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/clkctrl.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 0049828db0e9..535f35b21204 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -469,14 +469,32 @@ static void __init _clkctrl_add_provider(void *data, of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data); } -/* Get clock name based on compatible string for clkctrl */ -static char * __init clkctrl_get_name(struct device_node *np) +/* + * Get clock name based on "clock-output-names" property or the + * compatible property for clkctrl. + */ +static const char * __init clkctrl_get_name(struct device_node *np) { struct property *prop; const int prefix_len = 11; const char *compat; + const char *output; char *name; + if (!of_property_read_string_index(np, "clock-output-names", 0, + &output)) { + const char *end; + int len; + + len = strlen(output); + end = strstr(output, "_clkctrl"); + if (end) + len -= strlen(end); + name = kstrndup(output, len, GFP_KERNEL); + + return name; + } + of_property_for_each_string(np, "compatible", prop, compat) { if (!strncmp("ti,clkctrl-", compat, prefix_len)) { /* Two letter minimum name length for l3, l4 etc */ -- cgit v1.2.3 From 2c1593328d7f02fe49de5ad6b42c36296c9d6922 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:47 +0200 Subject: clk: ti: Add ti_dt_clk_name() helper to use clock-output-names Let's create the clock alias based on the clock-output-names property if available. Also the component clock drivers can use ti_dt_clk_name() in the following patches. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-7-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/clk.c | 20 +++++++++++++++++++- drivers/clk/ti/clock.h | 1 + 2 files changed, 20 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index 6fcbd801e8f1..3463579220b5 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -447,6 +447,24 @@ static const struct of_device_id simple_clk_match_table[] __initconst = { { } }; +/** + * ti_dt_clk_name - init clock name from first output name or node name + * @np: device node + * + * Use the first clock-output-name for the clock name if found. Fall back + * to legacy naming based on node name. + */ +const char *ti_dt_clk_name(struct device_node *np) +{ + const char *name; + + if (!of_property_read_string_index(np, "clock-output-names", 0, + &name)) + return name; + + return np->name; +} + /** * ti_clk_add_aliases - setup clock aliases * @@ -463,7 +481,7 @@ void __init ti_clk_add_aliases(void) clkspec.np = np; clk = of_clk_get_from_provider(&clkspec); - ti_clk_add_alias(NULL, clk, np->name); + ti_clk_add_alias(NULL, clk, ti_dt_clk_name(np)); } } diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index f1dd62de2bfc..938f34e290ed 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -214,6 +214,7 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, const char *con); struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, const char *con); +const char *ti_dt_clk_name(struct device_node *np); int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); void ti_clk_add_aliases(void); -- cgit v1.2.3 From 9e56a7d4263ca1c51d867e811cf2dd7e61b6469e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:48 +0200 Subject: clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name() Let's update the TI pll and clockdomain clocks to use ti_dt_clk_name() instead of devicetree node name if available. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-8-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/apll.c | 13 +++++++++---- drivers/clk/ti/clockdomain.c | 2 +- drivers/clk/ti/dpll.c | 8 +++++--- drivers/clk/ti/fapll.c | 11 +++++++---- 4 files changed, 22 insertions(+), 12 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c index ac5bc8857a51..e4db6b9a55c6 100644 --- a/drivers/clk/ti/apll.c +++ b/drivers/clk/ti/apll.c @@ -139,6 +139,7 @@ static void __init omap_clk_register_apll(void *user, struct clk_hw *hw = user; struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *ad = clk_hw->dpll_data; + const char *name; struct clk *clk; const struct clk_init_data *init = clk_hw->hw.init; @@ -166,7 +167,8 @@ static void __init omap_clk_register_apll(void *user, ad->clk_bypass = __clk_get_hw(clk); - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); + name = ti_dt_clk_name(node); + clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); kfree(init->parent_names); @@ -198,7 +200,7 @@ static void __init of_dra7_apll_setup(struct device_node *node) clk_hw->dpll_data = ad; clk_hw->hw.init = init; - init->name = node->name; + init->name = ti_dt_clk_name(node); init->ops = &apll_ck_ops; init->num_parents = of_clk_get_parent_count(node); @@ -347,6 +349,7 @@ static void __init of_omap2_apll_setup(struct device_node *node) struct dpll_data *ad = NULL; struct clk_hw_omap *clk_hw = NULL; struct clk_init_data *init = NULL; + const char *name; struct clk *clk; const char *parent_name; u32 val; @@ -362,7 +365,8 @@ static void __init of_omap2_apll_setup(struct device_node *node) clk_hw->dpll_data = ad; clk_hw->hw.init = init; init->ops = &omap2_apll_ops; - init->name = node->name; + name = ti_dt_clk_name(node); + init->name = name; clk_hw->ops = &omap2_apll_hwops; init->num_parents = of_clk_get_parent_count(node); @@ -403,7 +407,8 @@ static void __init of_omap2_apll_setup(struct device_node *node) if (ret) goto cleanup; - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); + name = ti_dt_clk_name(node); + clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); kfree(init); diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index 74831b2752b3..24179c907774 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -131,7 +131,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node) { struct clk *clk; struct clk_hw *clk_hw; - const char *clkdm_name = node->name; + const char *clkdm_name = ti_dt_clk_name(node); int i; unsigned int num_clks; diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index e9f9aee936ae..7c6dc8449b22 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -164,6 +164,7 @@ static void __init _register_dpll(void *user, struct clk_hw *hw = user; struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct dpll_data *dd = clk_hw->dpll_data; + const char *name; struct clk *clk; const struct clk_init_data *init = hw->init; @@ -193,7 +194,8 @@ static void __init _register_dpll(void *user, dd->clk_bypass = __clk_get_hw(clk); /* register the clock */ - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); + name = ti_dt_clk_name(node); + clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -227,7 +229,7 @@ static void _register_dpll_x2(struct device_node *node, struct clk *clk; struct clk_init_data init = { NULL }; struct clk_hw_omap *clk_hw; - const char *name = node->name; + const char *name = ti_dt_clk_name(node); const char *parent_name; parent_name = of_clk_get_parent_name(node, 0); @@ -304,7 +306,7 @@ static void __init of_ti_dpll_setup(struct device_node *node, clk_hw->ops = &clkhwops_omap3_dpll; clk_hw->hw.init = init; - init->name = node->name; + init->name = ti_dt_clk_name(node); init->ops = ops; init->num_parents = of_clk_get_parent_count(node); diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c index 8024c6d2b9e9..749c6b73abff 100644 --- a/drivers/clk/ti/fapll.c +++ b/drivers/clk/ti/fapll.c @@ -19,6 +19,8 @@ #include #include +#include "clock.h" + /* FAPLL Control Register PLL_CTRL */ #define FAPLL_MAIN_MULT_N_SHIFT 16 #define FAPLL_MAIN_DIV_P_SHIFT 8 @@ -542,6 +544,7 @@ static void __init ti_fapll_setup(struct device_node *node) struct clk_init_data *init = NULL; const char *parent_name[2]; struct clk *pll_clk; + const char *name; int i; fd = kzalloc(sizeof(*fd), GFP_KERNEL); @@ -559,7 +562,8 @@ static void __init ti_fapll_setup(struct device_node *node) goto free; init->ops = &ti_fapll_ops; - init->name = node->name; + name = ti_dt_clk_name(node); + init->name = name; init->num_parents = of_clk_get_parent_count(node); if (init->num_parents != 2) { @@ -591,7 +595,7 @@ static void __init ti_fapll_setup(struct device_node *node) if (fapll_is_ddr_pll(fd->base)) fd->bypass_bit_inverted = true; - fd->name = node->name; + fd->name = name; fd->hw.init = init; /* Register the parent PLL */ @@ -638,8 +642,7 @@ static void __init ti_fapll_setup(struct device_node *node) freq = NULL; } synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, - output_name, node->name, - pll_clk); + output_name, name, pll_clk); if (IS_ERR(synth_clk)) continue; -- cgit v1.2.3 From ed06099c5d0b329082cc19c58eace0b20bf7fe70 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Feb 2022 09:14:49 +0200 Subject: clk: ti: Update component clocks to use ti_dt_clk_name() Let's update all the TI component clocks to use ti_dt_clk_name() instead of devicetree node name if available. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220204071449.16762-9-tony@atomide.com Signed-off-by: Stephen Boyd --- drivers/clk/ti/autoidle.c | 2 +- drivers/clk/ti/clk-dra7-atl.c | 6 ++++-- drivers/clk/ti/composite.c | 6 ++++-- drivers/clk/ti/divider.c | 6 ++++-- drivers/clk/ti/fixed-factor.c | 2 +- drivers/clk/ti/gate.c | 4 +++- drivers/clk/ti/interface.c | 4 +++- drivers/clk/ti/mux.c | 4 +++- 8 files changed, 23 insertions(+), 11 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c index f6f8a409f148..d6e5f1511ace 100644 --- a/drivers/clk/ti/autoidle.c +++ b/drivers/clk/ti/autoidle.c @@ -205,7 +205,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node) return -ENOMEM; clk->shift = shift; - clk->name = node->name; + clk->name = ti_dt_clk_name(node); ret = ti_clk_get_reg_addr(node, 0, &clk->reg); if (ret) { kfree(clk); diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c index 8d4c08b034bd..aa0950c4f498 100644 --- a/drivers/clk/ti/clk-dra7-atl.c +++ b/drivers/clk/ti/clk-dra7-atl.c @@ -173,6 +173,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) struct dra7_atl_desc *clk_hw = NULL; struct clk_init_data init = { NULL }; const char **parent_names = NULL; + const char *name; struct clk *clk; clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); @@ -183,7 +184,8 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) clk_hw->hw.init = &init; clk_hw->divider = 1; - init.name = node->name; + name = ti_dt_clk_name(node); + init.name = name; init.ops = &atl_clk_ops; init.flags = CLK_IGNORE_UNUSED; init.num_parents = of_clk_get_parent_count(node); @@ -203,7 +205,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node) init.parent_names = parent_names; - clk = ti_clk_register(NULL, &clk_hw->hw, node->name); + clk = ti_clk_register(NULL, &clk_hw->hw, name); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index eaa43575cfa5..8d60319be368 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -125,6 +125,7 @@ static void __init _register_composite(void *user, struct component_clk *comp; int num_parents = 0; const char **parent_names = NULL; + const char *name; int i; int ret; @@ -172,7 +173,8 @@ static void __init _register_composite(void *user, goto cleanup; } - clk = clk_register_composite(NULL, node->name, + name = ti_dt_clk_name(node); + clk = clk_register_composite(NULL, name, parent_names, num_parents, _get_hw(cclk, CLK_COMPONENT_TYPE_MUX), &ti_clk_mux_ops, @@ -182,7 +184,7 @@ static void __init _register_composite(void *user, &ti_composite_gate_ops, 0); if (!IS_ERR(clk)) { - ret = ti_clk_add_alias(NULL, clk, node->name); + ret = ti_clk_add_alias(NULL, clk, name); if (ret) { clk_unregister(clk); goto cleanup; diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 28080df92f72..9fbea0997b43 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -320,10 +320,12 @@ static struct clk *_register_divider(struct device_node *node, struct clk *clk; struct clk_init_data init; const char *parent_name; + const char *name; parent_name = of_clk_get_parent_name(node, 0); - init.name = node->name; + name = ti_dt_clk_name(node); + init.name = name; init.ops = &ti_clk_divider_ops; init.flags = flags; init.parent_names = (parent_name ? &parent_name : NULL); @@ -332,7 +334,7 @@ static struct clk *_register_divider(struct device_node *node, div->hw.init = &init; /* register the clock */ - clk = ti_clk_register(NULL, &div->hw, node->name); + clk = ti_clk_register(NULL, &div->hw, name); if (IS_ERR(clk)) kfree(div); diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c index 7cbe896db071..8cb00d0af966 100644 --- a/drivers/clk/ti/fixed-factor.c +++ b/drivers/clk/ti/fixed-factor.c @@ -36,7 +36,7 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) { struct clk *clk; - const char *clk_name = node->name; + const char *clk_name = ti_dt_clk_name(node); const char *parent_name; u32 div, mult; u32 flags = 0; diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index b1d0fdb40a75..0033de9beb4c 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -138,6 +138,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, struct clk *clk; const char *parent_name; struct clk_omap_reg reg; + const char *name; u8 enable_bit = 0; u32 val; u32 flags = 0; @@ -164,7 +165,8 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node, if (of_property_read_bool(node, "ti,set-bit-to-disable")) clk_gate_flags |= INVERT_ENABLE; - clk = _register_gate(NULL, node->name, parent_name, flags, ®, + name = ti_dt_clk_name(node); + clk = _register_gate(NULL, name, parent_name, flags, ®, enable_bit, clk_gate_flags, ops, hw_ops); if (!IS_ERR(clk)) diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c index 83e34429d3b1..dd2b455183a9 100644 --- a/drivers/clk/ti/interface.c +++ b/drivers/clk/ti/interface.c @@ -72,6 +72,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node, const char *parent_name; struct clk_omap_reg reg; u8 enable_bit = 0; + const char *name; u32 val; if (ti_clk_get_reg_addr(node, 0, ®)) @@ -86,7 +87,8 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node, return; } - clk = _register_interface(NULL, node->name, parent_name, ®, + name = ti_dt_clk_name(node); + clk = _register_interface(NULL, name, parent_name, ®, enable_bit, ops); if (!IS_ERR(clk)) diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 0069e7cf3ebc..15de513d2d81 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -176,6 +176,7 @@ static void of_mux_clk_setup(struct device_node *node) struct clk_omap_reg reg; unsigned int num_parents; const char **parent_names; + const char *name; u8 clk_mux_flags = 0; u32 mask = 0; u32 shift = 0; @@ -213,7 +214,8 @@ static void of_mux_clk_setup(struct device_node *node) mask = (1 << fls(mask)) - 1; - clk = _register_mux(NULL, node->name, parent_names, num_parents, + name = ti_dt_clk_name(node); + clk = _register_mux(NULL, name, parent_names, num_parents, flags, ®, shift, mask, latch, clk_mux_flags, NULL); -- cgit v1.2.3 From d8a441e53e2434b1401e52dfd66b05263e442edc Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 18 Feb 2022 01:09:17 +0100 Subject: clk: actions: Terminate clk_div_table with sentinel element MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order that the end of a clk_div_table can be detected, it must be terminated with a sentinel element (.div = 0). In owl-s900.s, the { 0, 8 } element was probably meant to be just that, so this patch changes { 0, 8 } to { 0, 0 }. Fixes: d47317ca4ade1 ("clk: actions: Add S700 SoC clock support") Fixes: d85d20053e195 ("clk: actions: Add S900 SoC clock support") Signed-off-by: Jonathan Neuschäfer Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20220218000922.134857-2-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/actions/owl-s700.c | 1 + drivers/clk/actions/owl-s900.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c index a2f34d13fb54..6ea7da1d6d75 100644 --- a/drivers/clk/actions/owl-s700.c +++ b/drivers/clk/actions/owl-s700.c @@ -162,6 +162,7 @@ static struct clk_div_table hdmia_div_table[] = { static struct clk_div_table rmii_div_table[] = { {0, 4}, {1, 10}, + {0, 0} }; /* divider clocks */ diff --git a/drivers/clk/actions/owl-s900.c b/drivers/clk/actions/owl-s900.c index 790890978424..5144ada2c7e1 100644 --- a/drivers/clk/actions/owl-s900.c +++ b/drivers/clk/actions/owl-s900.c @@ -140,7 +140,7 @@ static struct clk_div_table rmii_ref_div_table[] = { static struct clk_div_table usb3_mac_div_table[] = { { 1, 2 }, { 2, 3 }, { 3, 4 }, - { 0, 8 }, + { 0, 0 } }; static struct clk_div_table i2s_div_table[] = { -- cgit v1.2.3 From 3eb00f89162e80083dfcaa842468b510462cfeaa Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 18 Feb 2022 01:09:18 +0100 Subject: clk: loongson1: Terminate clk_div_table with sentinel element MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order that the end of a clk_div_table can be detected, it must be terminated with a sentinel element (.div = 0). Fixes: b4626a7f4892 ("CLK: Add Loongson1C clock support") Signed-off-by: Jonathan Neuschäfer Reviewed-by: Philippe Mathieu-Daudé Link: https://lore.kernel.org/r/20220218000922.134857-3-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/loongson1/clk-loongson1c.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/loongson1/clk-loongson1c.c b/drivers/clk/loongson1/clk-loongson1c.c index 703f87622cf5..1ebf740380ef 100644 --- a/drivers/clk/loongson1/clk-loongson1c.c +++ b/drivers/clk/loongson1/clk-loongson1c.c @@ -37,6 +37,7 @@ static const struct clk_div_table ahb_div_table[] = { [1] = { .val = 1, .div = 4 }, [2] = { .val = 2, .div = 3 }, [3] = { .val = 3, .div = 3 }, + [4] = { /* sentinel */ } }; void __init ls1x_clk_init(void) -- cgit v1.2.3 From 113b261bdf2b4fd34e7769a147a7acd0a4d9137f Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 18 Feb 2022 01:09:19 +0100 Subject: clk: hisilicon: Terminate clk_div_table with sentinel element MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order that the end of a clk_div_table can be detected, it must be terminated with a sentinel element (.div = 0). Fixes: 6c81966107dc0 ("clk: hisilicon: Add clock driver for hi3559A SoC") Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220218000922.134857-4-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/hisilicon/clk-hi3559a.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index 56012a3d0219..9ea1a80acbe8 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -611,8 +611,8 @@ static struct hisi_mux_clock hi3559av100_shub_mux_clks[] = { /* shub div clk */ -static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}}; -static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}}; +static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}, {/*sentinel*/}}; +static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}, {/*sentinel*/}}; static struct hisi_divider_clock hi3559av100_shub_div_clks[] = { { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2, -- cgit v1.2.3 From 8bed4ed5aa3431085d9d27afc35d684856460eda Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 18 Feb 2022 01:09:20 +0100 Subject: clk: clps711x: Terminate clk_div_table with sentinel element MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order that the end of a clk_div_table can be detected, it must be terminated with a sentinel element (.div = 0). Fixes: 631c53478973d ("clk: Add CLPS711X clk driver") Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220218000922.134857-5-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/clk-clps711x.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-clps711x.c b/drivers/clk/clk-clps711x.c index a2c6486ef170..f8417ee2961a 100644 --- a/drivers/clk/clk-clps711x.c +++ b/drivers/clk/clk-clps711x.c @@ -28,11 +28,13 @@ static const struct clk_div_table spi_div_table[] = { { .val = 1, .div = 8, }, { .val = 2, .div = 2, }, { .val = 3, .div = 1, }, + { /* sentinel */ } }; static const struct clk_div_table timer_div_table[] = { { .val = 0, .div = 256, }, { .val = 1, .div = 1, }, + { /* sentinel */ } }; struct clps711x_clk { -- cgit v1.2.3 From 1fdfd517ce79740016f8ea4afc3fdc8e13f2653c Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 18 Feb 2022 01:09:21 +0100 Subject: clk: actions: Make sentinel elements more obvious MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sentinel elements of various tables in drivers/clk/actions can be a bit hard to recognize. Make them easier to see by changing the style from { 0, 0 } to { /* sentinel */ }. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220218000922.134857-6-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd --- drivers/clk/actions/owl-s500.c | 16 ++++++++-------- drivers/clk/actions/owl-s700.c | 18 ++++++++++-------- drivers/clk/actions/owl-s900.c | 26 +++++++++++++------------- 3 files changed, 31 insertions(+), 29 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c index 57d06e183dff..c69a7e2f0645 100644 --- a/drivers/clk/actions/owl-s500.c +++ b/drivers/clk/actions/owl-s500.c @@ -95,7 +95,7 @@ static const struct clk_pll_table clk_audio_pll_table[] = { { 0, 45158400 }, { 1, 49152000 }, - { 0, 0 }, + { /* sentinel */ } }; /* pll clocks */ @@ -138,46 +138,46 @@ static struct clk_factor_table sd_factor_table[] = { { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 }, { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 }, { 280, 1, 25 * 128 }, - { 0, 0, 0 }, + { /* sentinel */ } }; static struct clk_factor_table de_factor_table[] = { { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, { 8, 1, 12 }, - { 0, 0, 0 }, + { /* sentinel */ } }; static struct clk_factor_table hde_factor_table[] = { { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, - { 0, 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table rmii_ref_div_table[] = { { 0, 4 }, { 1, 10 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table std12rate_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table i2s_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, { 8, 24 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table nand_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 }, { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 }, - { 0, 0 }, + { /* sentinel */ } }; /* mux clock */ diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c index 6ea7da1d6d75..3e48105602aa 100644 --- a/drivers/clk/actions/owl-s700.c +++ b/drivers/clk/actions/owl-s700.c @@ -73,7 +73,7 @@ static struct clk_pll_table clk_audio_pll_table[] = { {0, 45158400}, {1, 49152000}, - {0, 0}, + { /* sentinel */ } }; static struct clk_pll_table clk_cvbs_pll_table[] = { @@ -82,7 +82,8 @@ static struct clk_pll_table clk_cvbs_pll_table[] = { {33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000}, {36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000}, {39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000}, - {42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0}, + {42, 44 * 12000000}, {43, 45 * 12000000}, + { /* sentinel */ } }; /* pll clocks */ @@ -137,7 +138,7 @@ static struct clk_factor_table sd_factor_table[] = { {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128}, {280, 1, 25 * 128}, {281, 1, 26 * 128}, - {0, 0}, + { /* sentinel */ } }; static struct clk_factor_table lcd_factor_table[] = { @@ -150,19 +151,19 @@ static struct clk_factor_table lcd_factor_table[] = { {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7}, {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7}, {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7}, - {0, 0}, + { /* sentinel */ } }; static struct clk_div_table hdmia_div_table[] = { {0, 1}, {1, 2}, {2, 3}, {3, 4}, {4, 6}, {5, 8}, {6, 12}, {7, 16}, {8, 24}, - {0, 0}, + { /* sentinel */ } }; static struct clk_div_table rmii_div_table[] = { {0, 4}, {1, 10}, - {0, 0} + { /* sentinel */ } }; /* divider clocks */ @@ -179,13 +180,14 @@ static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, static struct clk_factor_table de_factor_table[] = { {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5}, {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8}, - {8, 1, 12}, {0, 0, 0}, + {8, 1, 12}, + { /* sentinel */ } }; static struct clk_factor_table hde_factor_table[] = { {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5}, {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8}, - {0, 0, 0}, + { /* sentinel */ } }; /* gate clocks */ diff --git a/drivers/clk/actions/owl-s900.c b/drivers/clk/actions/owl-s900.c index 5144ada2c7e1..7dc6e07fb60e 100644 --- a/drivers/clk/actions/owl-s900.c +++ b/drivers/clk/actions/owl-s900.c @@ -73,12 +73,12 @@ static struct clk_pll_table clk_audio_pll_table[] = { { 0, 45158400 }, { 1, 49152000 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_pll_table clk_edp_pll_table[] = { { 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 }, - { 0, 0 }, + { /* sentinel */ } }; /* pll clocks */ @@ -120,41 +120,41 @@ static struct clk_div_table nand_div_table[] = { { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 }, { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 }, { 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table apb_div_table[] = { { 1, 2 }, { 2, 3 }, { 3, 4 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table eth_mac_div_table[] = { { 0, 2 }, { 1, 4 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table rmii_ref_div_table[] = { { 0, 4 }, { 1, 10 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table usb3_mac_div_table[] = { { 1, 2 }, { 2, 3 }, { 3, 4 }, - { 0, 0 } + { /* sentinel */ } }; static struct clk_div_table i2s_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, { 8, 24 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_div_table hdmia_div_table[] = { { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 }, { 8, 24 }, - { 0, 0 }, + { /* sentinel */ } }; /* divider clocks */ @@ -185,24 +185,24 @@ static struct clk_factor_table sd_factor_table[] = { { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 }, { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 }, - { 0, 0 }, + { /* sentinel */ } }; static struct clk_factor_table dmm_factor_table[] = { { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 }, - { 0, 0, 0 }, + { /* sentinel */ } }; static struct clk_factor_table noc_factor_table[] = { { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 }, - { 0, 0, 0 }, + { /* sentinel */ } }; static struct clk_factor_table bisp_factor_table[] = { { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 }, { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 }, - { 0, 0, 0 }, + { /* sentinel */ } }; /* factor clocks */ -- cgit v1.2.3 From 6f3cf24864ac113b053e485d7a7b000ee3786d1d Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Thu, 17 Feb 2022 09:34:53 -0800 Subject: clk: socfpga: cleanup spdx tags Replace tabs with spaces in SPDX tag Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20220217173453.3262672-1-trix@redhat.com Acked-by: Dinh Nguyen Signed-off-by: Stephen Boyd --- drivers/clk/socfpga/clk-periph-s10.c | 2 +- drivers/clk/socfpga/clk-pll-s10.c | 2 +- drivers/clk/socfpga/clk-s10.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index cbabde2b476b..f5c1ca42b668 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017, Intel Corporation */ diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index e444e4a0ee53..1d82737befd3 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017, Intel Corporation */ diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c index 4e508a844b3d..9b2e0275fbf7 100644 --- a/drivers/clk/socfpga/clk-s10.c +++ b/drivers/clk/socfpga/clk-s10.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017, Intel Corporation */ -- cgit v1.2.3 From 7c55e8efd290438e9bd95f6c3e14d3fa4f71b323 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Tue, 22 Feb 2022 11:51:53 -0800 Subject: clk: cleanup comments For spdx Space instead of tab before spdx tag Removed repeated works the, to, two Replacements much much to a much 'to to' to 'to do' aready to already Comunications to Communications freqency to frequency Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20220222195153.3817625-1-trix@redhat.com Signed-off-by: Stephen Boyd --- drivers/clk/at91/sckc.c | 2 +- drivers/clk/axis/clk-artpec6.c | 2 +- drivers/clk/bcm/clk-iproc.h | 2 +- drivers/clk/bcm/clk-kona-setup.c | 2 +- drivers/clk/clk-fractional-divider.c | 2 +- drivers/clk/clk-si5341.c | 2 +- drivers/clk/meson/meson8b.c | 2 +- drivers/clk/mmp/pwr-island.c | 2 +- drivers/clk/socfpga/clk-gate-s10.c | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 2d65770d8665..fdc9b669f8a7 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -535,7 +535,7 @@ static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw) /* * Assume that if it has already been selected (for example by the - * bootloader), enough time has aready passed. + * bootloader), enough time has already passed. */ if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) { osc->prepared = true; diff --git a/drivers/clk/axis/clk-artpec6.c b/drivers/clk/axis/clk-artpec6.c index f95959ff85ac..a3f349d4624d 100644 --- a/drivers/clk/axis/clk-artpec6.c +++ b/drivers/clk/axis/clk-artpec6.c @@ -2,7 +2,7 @@ /* * ARTPEC-6 clock initialization * - * Copyright 2015-2016 Axis Comunications AB. + * Copyright 2015-2016 Axis Communications AB. */ #include diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h index a48ddd3e0b28..d7e5b94bed45 100644 --- a/drivers/clk/bcm/clk-iproc.h +++ b/drivers/clk/bcm/clk-iproc.h @@ -89,7 +89,7 @@ * Parameters for VCO frequency configuration * * VCO frequency = - * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv) + * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency / pdiv) */ struct iproc_pll_vco_param { unsigned long rate; diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c index e65eeef9cbaf..5dd65164c8b1 100644 --- a/drivers/clk/bcm/clk-kona-setup.c +++ b/drivers/clk/bcm/clk-kona-setup.c @@ -510,7 +510,7 @@ static bool kona_clk_valid(struct kona_clk *bcm_clk) * placeholders for non-supported clocks. Keep track of the * position of each clock name in the original array. * - * Allocates an array of pointers to to hold the names of all + * Allocates an array of pointers to hold the names of all * non-null entries in the original array, and returns a pointer to * that array in *names. This will be used for registering the * clock with the common clock code. On successful return, diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 4274540327ce..8efa5142ff8c 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -34,7 +34,7 @@ * and assume that the IP, that needs m and n, has also its own * prescaler, which is capable to divide by 2^scale. In this way * we get the denominator to satisfy the desired range (2) and - * at the same time much much better result of m and n than simple + * at the same time a much better result of m and n than simple * saturated values. */ diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c index f7b41366666e..4baeb7378a4b 100644 --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c @@ -655,7 +655,7 @@ static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw, f = synth->data->freq_vco; f *= n_den >> 4; - /* Now we need to to 64-bit division: f/n_num */ + /* Now we need to do 64-bit division: f/n_num */ /* And compensate for the 4 bits we dropped */ f = div64_u64(f, (n_num >> 4)); diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index cd0f5bae24d4..8f3b7a94a667 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2232,7 +2232,7 @@ static struct clk_regmap meson8b_vpu_1 = { }; /* - * The VPU clock has two two identical clock trees (vpu_0 and vpu_1) + * The VPU clock has two identical clock trees (vpu_0 and vpu_1) * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can * actually manage this glitch-free mux because it does top-to-bottom * updates the each clock tree and switches to the "inactive" one when diff --git a/drivers/clk/mmp/pwr-island.c b/drivers/clk/mmp/pwr-island.c index ab57c0e995c1..edaa2433a472 100644 --- a/drivers/clk/mmp/pwr-island.c +++ b/drivers/clk/mmp/pwr-island.c @@ -76,7 +76,7 @@ static int mmp_pm_domain_power_off(struct generic_pm_domain *genpd) if (pm_domain->lock) spin_lock_irqsave(pm_domain->lock, flags); - /* Turn off and isolate the the power island. */ + /* Turn off and isolate the power island. */ val = readl(pm_domain->reg); val &= ~pm_domain->power_on; val &= ~0x100; diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c index 32567795765f..3930d922efb4 100644 --- a/drivers/clk/socfpga/clk-gate-s10.c +++ b/drivers/clk/socfpga/clk-gate-s10.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017, Intel Corporation */ -- cgit v1.2.3 From 0c1b56df451716ba207bbf59f303473643eee4fd Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:23 +0100 Subject: clk: Fix clk_hw_get_clk() when dev is NULL Any registered clk_core structure can have a NULL pointer in its dev field. While never actually documented, this is evidenced by the wide usage of clk_register and clk_hw_register with a NULL device pointer, and the fact that the core of_clk_hw_register() function also passes a NULL device pointer. A call to clk_hw_get_clk() on a clk_hw struct whose clk_core is in that case will result in a NULL pointer derefence when it calls dev_name() on that NULL device pointer. Add a test for this case and use NULL as the dev_id if the device pointer is NULL. Fixes: 30d6f8c15d2c ("clk: add api to get clk consumer from clk_hw") Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-2-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 8de6a22498e7..fff5edb89d6d 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3773,8 +3773,9 @@ struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw, struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id) { struct device *dev = hw->core->dev; + const char *name = dev ? dev_name(dev) : NULL; - return clk_hw_create_clk(dev, hw, dev_name(dev), con_id); + return clk_hw_create_clk(dev, hw, name, con_id); } EXPORT_SYMBOL(clk_hw_get_clk); -- cgit v1.2.3 From 723d0530d9d778cdceab4ebd0d0efc2d3a021c3c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:24 +0100 Subject: clk: Introduce Kunit Tests for the framework Let's test various parts of the rate-related clock API with the kunit testing framework. Cc: kunit-dev@googlegroups.com Tested-by: Daniel Latypov Suggested-by: Stephen Boyd Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-3-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/.kunitconfig | 1 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk_test.c | 787 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 796 insertions(+) create mode 100644 drivers/clk/clk_test.c (limited to 'drivers/clk') diff --git a/drivers/clk/.kunitconfig b/drivers/clk/.kunitconfig index 3754fdb9485a..cdbc7d7deba9 100644 --- a/drivers/clk/.kunitconfig +++ b/drivers/clk/.kunitconfig @@ -1,3 +1,4 @@ CONFIG_KUNIT=y CONFIG_COMMON_CLK=y +CONFIG_CLK_KUNIT_TEST=y CONFIG_CLK_GATE_KUNIT_TEST=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3cdf33470a75..2ef6eca297ff 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -429,6 +429,13 @@ source "drivers/clk/xilinx/Kconfig" source "drivers/clk/zynqmp/Kconfig" # Kunit test cases +config CLK_KUNIT_TEST + tristate "Basic Clock Framework Kunit Tests" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Kunit tests for the common clock framework. + config CLK_GATE_KUNIT_TEST tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS depends on KUNIT diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 6a98291350b6..8f9b1daba411 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -2,6 +2,7 @@ # common clock types obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o +obj-$(CONFIG_CLK_KUNIT_TEST) += clk_test.o obj-$(CONFIG_COMMON_CLK) += clk-divider.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c new file mode 100644 index 000000000000..edef47506c62 --- /dev/null +++ b/drivers/clk/clk_test.c @@ -0,0 +1,787 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Kunit test for clk rate management + */ +#include +#include + +/* Needed for clk_hw_get_clk() */ +#include "clk.h" + +#include + +#define DUMMY_CLOCK_INIT_RATE (42 * 1000 * 1000) +#define DUMMY_CLOCK_RATE_1 (142 * 1000 * 1000) +#define DUMMY_CLOCK_RATE_2 (242 * 1000 * 1000) + +struct clk_dummy_context { + struct clk_hw hw; + unsigned long rate; +}; + +static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy_context *ctx = + container_of(hw, struct clk_dummy_context, hw); + + return ctx->rate; +} + +static int clk_dummy_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + /* Just return the same rate without modifying it */ + return 0; +} + +static int clk_dummy_maximize_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + /* + * If there's a maximum set, always run the clock at the maximum + * allowed. + */ + if (req->max_rate < ULONG_MAX) + req->rate = req->max_rate; + + return 0; +} + +static int clk_dummy_minimize_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + /* + * If there's a minimum set, always run the clock at the minimum + * allowed. + */ + if (req->min_rate > 0) + req->rate = req->min_rate; + + return 0; +} + +static int clk_dummy_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dummy_context *ctx = + container_of(hw, struct clk_dummy_context, hw); + + ctx->rate = rate; + return 0; +} + +static const struct clk_ops clk_dummy_rate_ops = { + .recalc_rate = clk_dummy_recalc_rate, + .determine_rate = clk_dummy_determine_rate, + .set_rate = clk_dummy_set_rate, +}; + +static const struct clk_ops clk_dummy_maximize_rate_ops = { + .recalc_rate = clk_dummy_recalc_rate, + .determine_rate = clk_dummy_maximize_rate, + .set_rate = clk_dummy_set_rate, +}; + +static const struct clk_ops clk_dummy_minimize_rate_ops = { + .recalc_rate = clk_dummy_recalc_rate, + .determine_rate = clk_dummy_minimize_rate, + .set_rate = clk_dummy_set_rate, +}; + +static int clk_test_init_with_ops(struct kunit *test, const struct clk_ops *ops) +{ + struct clk_dummy_context *ctx; + struct clk_init_data init = { }; + int ret; + + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + ctx->rate = DUMMY_CLOCK_INIT_RATE; + test->priv = ctx; + + init.name = "test_dummy_rate"; + init.ops = ops; + ctx->hw.init = &init; + + ret = clk_hw_register(NULL, &ctx->hw); + if (ret) + return ret; + + return 0; +} + +static int clk_test_init(struct kunit *test) +{ + return clk_test_init_with_ops(test, &clk_dummy_rate_ops); +} + +static int clk_maximize_test_init(struct kunit *test) +{ + return clk_test_init_with_ops(test, &clk_dummy_maximize_rate_ops); +} + +static int clk_minimize_test_init(struct kunit *test) +{ + return clk_test_init_with_ops(test, &clk_dummy_minimize_rate_ops); +} + +static void clk_test_exit(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + + clk_hw_unregister(&ctx->hw); +} + +/* + * Test that the actual rate matches what is returned by clk_get_rate() + */ +static void clk_test_get_rate(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, ctx->rate); +} + +/* + * Test that, after a call to clk_set_rate(), the rate returned by + * clk_get_rate() matches. + * + * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't + * modify the requested rate, which is our case in clk_dummy_rate_ops. + */ +static void clk_test_set_get_rate(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); +} + +/* + * Test that, after several calls to clk_set_rate(), the rate returned + * by clk_get_rate() matches the last one. + * + * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't + * modify the requested rate, which is our case in clk_dummy_rate_ops. + */ +static void clk_test_set_set_get_rate(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); +} + +/* + * Test that clk_round_rate and clk_set_rate are consitent and will + * return the same frequency. + */ +static void clk_test_round_set_get_rate(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rounded_rate, set_rate; + + rounded_rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1); + KUNIT_ASSERT_GT(test, rounded_rate, 0); + KUNIT_EXPECT_EQ(test, rounded_rate, DUMMY_CLOCK_RATE_1); + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1), + 0); + + set_rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, set_rate, 0); + KUNIT_EXPECT_EQ(test, rounded_rate, set_rate); +} + +static struct kunit_case clk_test_cases[] = { + KUNIT_CASE(clk_test_get_rate), + KUNIT_CASE(clk_test_set_get_rate), + KUNIT_CASE(clk_test_set_set_get_rate), + KUNIT_CASE(clk_test_round_set_get_rate), + {} +}; + +static struct kunit_suite clk_test_suite = { + .name = "clk-test", + .init = clk_test_init, + .exit = clk_test_exit, + .test_cases = clk_test_cases, +}; + +/* + * Test that clk_set_rate_range won't return an error for a valid range + * and that it will make sure the rate of the clock is within the + * boundaries. + */ +static void clk_range_test_set_range(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1); + KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2); +} + +/* + * Test that calling clk_set_rate_range with a minimum rate higher than + * the maximum rate returns an error. + */ +static void clk_range_test_set_range_invalid(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + + KUNIT_EXPECT_LT(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1 + 1000, + DUMMY_CLOCK_RATE_1), + 0); +} + +/* + * Test that users can't set multiple, disjoints, range that would be + * impossible to meet. + */ +static void clk_range_test_multiple_disjoints_range(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *user1, *user2; + + user1 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1); + + user2 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user1, 1000, 2000), + 0); + + KUNIT_EXPECT_LT(test, + clk_set_rate_range(user2, 3000, 4000), + 0); + + clk_put(user2); + clk_put(user1); +} + +/* + * Test that if our clock has some boundaries and we try to round a rate + * lower than the minimum, the returned rate won't be affected by the + * boundaries. + */ +static void clk_range_test_set_range_round_rate_lower(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1 - 1000); +} + +/* + * Test that if our clock has some boundaries and we try to set a rate + * lower than the minimum, we'll get an error. + */ +static void clk_range_test_set_range_set_rate_lower(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + KUNIT_ASSERT_LT(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1 - 1000), + 0); +} + +/* + * Test that if our clock has some boundaries and we try to round and + * set a rate lower than the minimum, the values won't be consistent + * between clk_round_rate() and clk_set_rate(). + */ +static void clk_range_test_set_range_set_round_rate_consistent_lower(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + long rounded; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rounded = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000); + KUNIT_ASSERT_GT(test, rounded, 0); + + KUNIT_EXPECT_LT(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1 - 1000), + 0); + + KUNIT_EXPECT_NE(test, rounded, clk_get_rate(clk)); +} + +/* + * Test that if our clock has some boundaries and we try to round a rate + * higher than the maximum, the returned rate won't be affected by the + * boundaries. + */ +static void clk_range_test_set_range_round_rate_higher(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2 + 1000); +} + +/* + * Test that if our clock has some boundaries and we try to set a rate + * lower than the maximum, we'll get an error. + */ +static void clk_range_test_set_range_set_rate_higher(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + KUNIT_ASSERT_LT(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), + 0); +} + +/* + * Test that if our clock has some boundaries and we try to round and + * set a rate higher than the maximum, the values won't be consistent + * between clk_round_rate() and clk_set_rate(). + */ +static void clk_range_test_set_range_set_round_rate_consistent_higher(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + long rounded; + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rounded = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000); + KUNIT_ASSERT_GT(test, rounded, 0); + + KUNIT_EXPECT_LT(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), + 0); + + KUNIT_EXPECT_NE(test, rounded, clk_get_rate(clk)); +} + +/* + * Test that if our clock has a rate lower than the minimum set by a + * call to clk_set_rate_range(), the rate will be raised to match the + * new minimum. + * + * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't + * modify the requested rate, which is our case in clk_dummy_rate_ops. + */ +static void clk_range_test_set_range_get_rate_raised(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1 - 1000), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); +} + +/* + * Test that if our clock has a rate higher than the maximum set by a + * call to clk_set_rate_range(), the rate will be lowered to match the + * new maximum. + * + * This assumes that clk_ops.determine_rate or clk_ops.round_rate won't + * modify the requested rate, which is our case in clk_dummy_rate_ops. + */ +static void clk_range_test_set_range_get_rate_lowered(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); +} + +static struct kunit_case clk_range_test_cases[] = { + KUNIT_CASE(clk_range_test_set_range), + KUNIT_CASE(clk_range_test_set_range_invalid), + KUNIT_CASE(clk_range_test_multiple_disjoints_range), + KUNIT_CASE(clk_range_test_set_range_round_rate_lower), + KUNIT_CASE(clk_range_test_set_range_set_rate_lower), + KUNIT_CASE(clk_range_test_set_range_set_round_rate_consistent_lower), + KUNIT_CASE(clk_range_test_set_range_round_rate_higher), + KUNIT_CASE(clk_range_test_set_range_set_rate_higher), + KUNIT_CASE(clk_range_test_set_range_set_round_rate_consistent_higher), + KUNIT_CASE(clk_range_test_set_range_get_rate_raised), + KUNIT_CASE(clk_range_test_set_range_get_rate_lowered), + {} +}; + +static struct kunit_suite clk_range_test_suite = { + .name = "clk-range-test", + .init = clk_test_init, + .exit = clk_test_exit, + .test_cases = clk_range_test_cases, +}; + +/* + * Test that if: + * - we have several subsequent calls to clk_set_rate_range(); + * - and we have a round_rate ops that always return the maximum + * frequency allowed; + * + * The clock will run at the minimum of all maximum boundaries + * requested, even if those boundaries aren't there anymore. + */ +static void clk_range_test_set_range_rate_maximized(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2 - 1000), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2 - 1000); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2 - 1000); +} + +/* + * Test that if: + * - we have several subsequent calls to clk_set_rate_range(), across + * multiple users; + * - and we have a round_rate ops that always return the maximum + * frequency allowed; + * + * The clock will run at the minimum of all maximum boundaries + * requested, even if those boundaries aren't there anymore. + */ +static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + struct clk *user1, *user2; + unsigned long rate; + + user1 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1); + + user2 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user1, + 0, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user2, + 0, + DUMMY_CLOCK_RATE_1), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user2, 0, ULONG_MAX), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + clk_put(user2); + clk_put(user1); +} + +static struct kunit_case clk_range_maximize_test_cases[] = { + KUNIT_CASE(clk_range_test_set_range_rate_maximized), + KUNIT_CASE(clk_range_test_multiple_set_range_rate_maximized), + {} +}; + +static struct kunit_suite clk_range_maximize_test_suite = { + .name = "clk-range-maximize-test", + .init = clk_maximize_test_init, + .exit = clk_test_exit, + .test_cases = clk_range_maximize_test_cases, +}; + +/* + * Test that if: + * - we have several subsequent calls to clk_set_rate_range() + * - and we have a round_rate ops that always return the minimum + * frequency allowed; + * + * The clock will run at the maximum of all minimum boundaries + * requested, even if those boundaries aren't there anymore. + */ +static void clk_range_test_set_range_rate_minimized(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate; + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_1 - 1000), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1 + 1000, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1 + 1000); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + DUMMY_CLOCK_RATE_1, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1 + 1000); +} + +/* + * Test that if: + * - we have several subsequent calls to clk_set_rate_range(), across + * multiple users; + * - and we have a round_rate ops that always return the minimum + * frequency allowed; + * + * The clock will run at the maximum of all minimum boundaries + * requested, even if those boundaries aren't there anymore. + */ +static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + struct clk *user1, *user2; + unsigned long rate; + + user1 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1); + + user2 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user1, + DUMMY_CLOCK_RATE_1, + ULONG_MAX), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user2, + DUMMY_CLOCK_RATE_2, + ULONG_MAX), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user2, 0, ULONG_MAX), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + clk_put(user2); + clk_put(user1); +} + +static struct kunit_case clk_range_minimize_test_cases[] = { + KUNIT_CASE(clk_range_test_set_range_rate_minimized), + KUNIT_CASE(clk_range_test_multiple_set_range_rate_minimized), + {} +}; + +static struct kunit_suite clk_range_minimize_test_suite = { + .name = "clk-range-minimize-test", + .init = clk_minimize_test_init, + .exit = clk_test_exit, + .test_cases = clk_range_minimize_test_cases, +}; + +kunit_test_suites( + &clk_test_suite, + &clk_range_test_suite, + &clk_range_maximize_test_suite, + &clk_range_minimize_test_suite +); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 10c46f2ea914202482d19cf80dcc9c321c9ff59b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:25 +0100 Subject: clk: Enforce that disjoints limits are invalid If we were to have two users of the same clock, doing something like: clk_set_rate_range(user1, 1000, 2000); clk_set_rate_range(user2, 3000, 4000); The second call would fail with -EINVAL, preventing from getting in a situation where we end up with impossible limits. However, this is never explicitly checked against and enforced, and works by relying on an undocumented behaviour of clk_set_rate(). Indeed, on the first clk_set_rate_range will make sure the current clock rate is within the new range, so it will be between 1000 and 2000Hz. On the second clk_set_rate_range(), it will consider (rightfully), that our current clock is outside of the 3000-4000Hz range, and will call clk_core_set_rate_nolock() to set it to 3000Hz. clk_core_set_rate_nolock() will then call clk_calc_new_rates() that will eventually check that our rate 3000Hz rate is outside the min 3000Hz max 2000Hz range, will bail out, the error will propagate and we'll eventually return -EINVAL. This solely relies on the fact that clk_calc_new_rates(), and in particular clk_core_determine_round_nolock(), won't modify the new rate allowing the error to be reported. That assumption won't be true for all drivers, and most importantly we'll break that assumption in a later patch. It can also be argued that we shouldn't even reach the point where we're calling clk_core_set_rate_nolock(). Let's make an explicit check for disjoints range before we're doing anything. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-4-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index fff5edb89d6d..112911138a7b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -632,6 +632,24 @@ static void clk_core_get_boundaries(struct clk_core *core, *max_rate = min(*max_rate, clk_user->max_rate); } +static bool clk_core_check_boundaries(struct clk_core *core, + unsigned long min_rate, + unsigned long max_rate) +{ + struct clk *user; + + lockdep_assert_held(&prepare_lock); + + if (min_rate > core->max_rate || max_rate < core->min_rate) + return false; + + hlist_for_each_entry(user, &core->clks, clks_node) + if (min_rate > user->max_rate || max_rate < user->min_rate) + return false; + + return true; +} + void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate) { @@ -2348,6 +2366,11 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) clk->min_rate = min; clk->max_rate = max; + if (!clk_core_check_boundaries(clk->core, min, max)) { + ret = -EINVAL; + goto out; + } + rate = clk_core_get_rate_nolock(clk->core); if (rate < min || rate > max) { /* @@ -2376,6 +2399,7 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) } } +out: if (clk->exclusive_count) clk_core_rate_protect(clk->core); -- cgit v1.2.3 From 948fb0969eae856f9b65d8c9b98042afed08454f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:26 +0100 Subject: clk: Always clamp the rounded rate The current core while setting the min and max rate properly in the clk_request structure will not make sure that the requested rate is within these boundaries, leaving it to each and every driver to make sure it is. It's not clear if this was on purpose or not, but this introduces some inconsistencies within the API. For example, a user setting a range and then calling clk_round_rate() with a value outside of that range will get the same value back (ignoring any driver adjustements), effectively ignoring the range that was just set. Another one, arguably worse, is that it also makes clk_round_rate() and clk_set_rate() behave differently if there's a range and the rate being used for both is outside that range. As we have seen, the rate will be returned unchanged by clk_round_rate(), but clk_set_rate() will error out returning -EINVAL. Let's make sure the framework will always clamp the rate to the current range found on the clock, which will fix both these inconsistencies. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-5-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 2 ++ drivers/clk/clk_test.c | 50 ++++++++++++++++++++++++++++++++------------------ 2 files changed, 34 insertions(+), 18 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 112911138a7b..6c4e10209568 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1348,6 +1348,8 @@ static int clk_core_determine_round_nolock(struct clk_core *core, if (!core) return 0; + req->rate = clamp(req->rate, req->min_rate, req->max_rate); + /* * At this point, core protection will be disabled * - if the provider is not protected at all diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index edef47506c62..bc8d856f0ee8 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -310,8 +310,7 @@ static void clk_range_test_multiple_disjoints_range(struct kunit *test) /* * Test that if our clock has some boundaries and we try to round a rate - * lower than the minimum, the returned rate won't be affected by the - * boundaries. + * lower than the minimum, the returned rate will be within range. */ static void clk_range_test_set_range_round_rate_lower(struct kunit *test) { @@ -328,18 +327,20 @@ static void clk_range_test_set_range_round_rate_lower(struct kunit *test) rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000); KUNIT_ASSERT_GT(test, rate, 0); - KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1 - 1000); + KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1); + KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2); } /* * Test that if our clock has some boundaries and we try to set a rate - * lower than the minimum, we'll get an error. + * higher than the maximum, the new rate will be within range. */ static void clk_range_test_set_range_set_rate_lower(struct kunit *test) { struct clk_dummy_context *ctx = test->priv; struct clk_hw *hw = &ctx->hw; struct clk *clk = hw->clk; + unsigned long rate; KUNIT_ASSERT_EQ(test, clk_set_rate_range(clk, @@ -347,15 +348,21 @@ static void clk_range_test_set_range_set_rate_lower(struct kunit *test) DUMMY_CLOCK_RATE_2), 0); - KUNIT_ASSERT_LT(test, + KUNIT_ASSERT_EQ(test, clk_set_rate(clk, DUMMY_CLOCK_RATE_1 - 1000), 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1); + KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2); } /* * Test that if our clock has some boundaries and we try to round and - * set a rate lower than the minimum, the values won't be consistent - * between clk_round_rate() and clk_set_rate(). + * set a rate lower than the minimum, the rate returned by + * clk_round_rate() will be consistent with the new rate set by + * clk_set_rate(). */ static void clk_range_test_set_range_set_round_rate_consistent_lower(struct kunit *test) { @@ -373,17 +380,16 @@ static void clk_range_test_set_range_set_round_rate_consistent_lower(struct kuni rounded = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000); KUNIT_ASSERT_GT(test, rounded, 0); - KUNIT_EXPECT_LT(test, + KUNIT_ASSERT_EQ(test, clk_set_rate(clk, DUMMY_CLOCK_RATE_1 - 1000), 0); - KUNIT_EXPECT_NE(test, rounded, clk_get_rate(clk)); + KUNIT_EXPECT_EQ(test, rounded, clk_get_rate(clk)); } /* * Test that if our clock has some boundaries and we try to round a rate - * higher than the maximum, the returned rate won't be affected by the - * boundaries. + * higher than the maximum, the returned rate will be within range. */ static void clk_range_test_set_range_round_rate_higher(struct kunit *test) { @@ -400,18 +406,20 @@ static void clk_range_test_set_range_round_rate_higher(struct kunit *test) rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000); KUNIT_ASSERT_GT(test, rate, 0); - KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2 + 1000); + KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1); + KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2); } /* * Test that if our clock has some boundaries and we try to set a rate - * lower than the maximum, we'll get an error. + * higher than the maximum, the new rate will be within range. */ static void clk_range_test_set_range_set_rate_higher(struct kunit *test) { struct clk_dummy_context *ctx = test->priv; struct clk_hw *hw = &ctx->hw; struct clk *clk = hw->clk; + unsigned long rate; KUNIT_ASSERT_EQ(test, clk_set_rate_range(clk, @@ -419,15 +427,21 @@ static void clk_range_test_set_range_set_rate_higher(struct kunit *test) DUMMY_CLOCK_RATE_2), 0); - KUNIT_ASSERT_LT(test, + KUNIT_ASSERT_EQ(test, clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1); + KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2); } /* * Test that if our clock has some boundaries and we try to round and - * set a rate higher than the maximum, the values won't be consistent - * between clk_round_rate() and clk_set_rate(). + * set a rate higher than the maximum, the rate returned by + * clk_round_rate() will be consistent with the new rate set by + * clk_set_rate(). */ static void clk_range_test_set_range_set_round_rate_consistent_higher(struct kunit *test) { @@ -445,11 +459,11 @@ static void clk_range_test_set_range_set_round_rate_consistent_higher(struct kun rounded = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000); KUNIT_ASSERT_GT(test, rounded, 0); - KUNIT_EXPECT_LT(test, + KUNIT_ASSERT_EQ(test, clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), 0); - KUNIT_EXPECT_NE(test, rounded, clk_get_rate(clk)); + KUNIT_EXPECT_EQ(test, rounded, clk_get_rate(clk)); } /* -- cgit v1.2.3 From a9b269310ad9abb2f206fe814fd3afcadddce3aa Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:27 +0100 Subject: clk: Use clamp instead of open-coding our own The code in clk_set_rate_range() will, if the current rate is outside of the new range, force it to the minimum or maximum. Since it's running under the condition that the rate is either lower than the minimum, or higher than the maximum, this is equivalent to using clamp, while being less readable. Let's switch to using clamp instead. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-6-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 6c4e10209568..c15ee5070f52 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2388,11 +2388,7 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) * this corner case when determining the rate */ - if (rate < min) - rate = min; - else - rate = max; - + rate = clamp(clk->core->req_rate, min, max); ret = clk_core_set_rate_nolock(clk->core, rate); if (ret) { /* rollback the changes */ -- cgit v1.2.3 From c80ac50cbb378a4029129a596251747386e3c8e9 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:28 +0100 Subject: clk: Always set the rate on clk_set_range_rate When we change a clock minimum or maximum using clk_set_rate_range(), clk_set_min_rate() or clk_set_max_rate(), the current code will only trigger a new rate change if the rate is outside of the new boundaries. However, a clock driver might want to always keep the clock rate to one of its boundary, for example the minimum to keep the power consumption as low as possible. Since they don't always get called though, clock providers don't have the opportunity to implement this behaviour. Let's trigger a clk_set_rate() on the previous requested rate every time clk_set_rate_range() is called. That way, providers that care about the new boundaries have a chance to adjust the rate, while providers that don't care about those new boundaries will return the same rate than before, which will be ignored by clk_set_rate() and won't result in a new rate change. Suggested-by: Stephen Boyd Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-7-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 45 +++++++++++++++++++++-------------------- drivers/clk/clk_test.c | 54 ++++++++++++++++++++++---------------------------- 2 files changed, 47 insertions(+), 52 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index c15ee5070f52..9bc8bf434b94 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2373,28 +2373,29 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) goto out; } - rate = clk_core_get_rate_nolock(clk->core); - if (rate < min || rate > max) { - /* - * FIXME: - * We are in bit of trouble here, current rate is outside the - * the requested range. We are going try to request appropriate - * range boundary but there is a catch. It may fail for the - * usual reason (clock broken, clock protected, etc) but also - * because: - * - round_rate() was not favorable and fell on the wrong - * side of the boundary - * - the determine_rate() callback does not really check for - * this corner case when determining the rate - */ - - rate = clamp(clk->core->req_rate, min, max); - ret = clk_core_set_rate_nolock(clk->core, rate); - if (ret) { - /* rollback the changes */ - clk->min_rate = old_min; - clk->max_rate = old_max; - } + /* + * Since the boundaries have been changed, let's give the + * opportunity to the provider to adjust the clock rate based on + * the new boundaries. + * + * We also need to handle the case where the clock is currently + * outside of the boundaries. Clamping the last requested rate + * to the current minimum and maximum will also handle this. + * + * FIXME: + * There is a catch. It may fail for the usual reason (clock + * broken, clock protected, etc) but also because: + * - round_rate() was not favorable and fell on the wrong + * side of the boundary + * - the determine_rate() callback does not really check for + * this corner case when determining the rate + */ + rate = clamp(clk->core->req_rate, min, max); + ret = clk_core_set_rate_nolock(clk->core, rate); + if (ret) { + /* rollback the changes */ + clk->min_rate = old_min; + clk->max_rate = old_max; } out: diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index bc8d856f0ee8..8924a5ac56d8 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -549,13 +549,12 @@ static struct kunit_suite clk_range_test_suite = { }; /* - * Test that if: - * - we have several subsequent calls to clk_set_rate_range(); - * - and we have a round_rate ops that always return the maximum - * frequency allowed; + * Test that if we have several subsequent calls to + * clk_set_rate_range(), the core will reevaluate whether a new rate is + * needed each and every time. * - * The clock will run at the minimum of all maximum boundaries - * requested, even if those boundaries aren't there anymore. + * With clk_dummy_maximize_rate_ops, this means that the rate will + * trail along the maximum as it evolves. */ static void clk_range_test_set_range_rate_maximized(struct kunit *test) { @@ -596,18 +595,16 @@ static void clk_range_test_set_range_rate_maximized(struct kunit *test) rate = clk_get_rate(clk); KUNIT_ASSERT_GT(test, rate, 0); - KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2 - 1000); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); } /* - * Test that if: - * - we have several subsequent calls to clk_set_rate_range(), across - * multiple users; - * - and we have a round_rate ops that always return the maximum - * frequency allowed; + * Test that if we have several subsequent calls to + * clk_set_rate_range(), across multiple users, the core will reevaluate + * whether a new rate is needed each and every time. * - * The clock will run at the minimum of all maximum boundaries - * requested, even if those boundaries aren't there anymore. + * With clk_dummy_maximize_rate_ops, this means that the rate will + * trail along the maximum as it evolves. */ static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test) { @@ -653,7 +650,7 @@ static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test) rate = clk_get_rate(clk); KUNIT_ASSERT_GT(test, rate, 0); - KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); clk_put(user2); clk_put(user1); @@ -673,13 +670,12 @@ static struct kunit_suite clk_range_maximize_test_suite = { }; /* - * Test that if: - * - we have several subsequent calls to clk_set_rate_range() - * - and we have a round_rate ops that always return the minimum - * frequency allowed; + * Test that if we have several subsequent calls to + * clk_set_rate_range(), the core will reevaluate whether a new rate is + * needed each and every time. * - * The clock will run at the maximum of all minimum boundaries - * requested, even if those boundaries aren't there anymore. + * With clk_dummy_minimize_rate_ops, this means that the rate will + * trail along the minimum as it evolves. */ static void clk_range_test_set_range_rate_minimized(struct kunit *test) { @@ -720,18 +716,16 @@ static void clk_range_test_set_range_rate_minimized(struct kunit *test) rate = clk_get_rate(clk); KUNIT_ASSERT_GT(test, rate, 0); - KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1 + 1000); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); } /* - * Test that if: - * - we have several subsequent calls to clk_set_rate_range(), across - * multiple users; - * - and we have a round_rate ops that always return the minimum - * frequency allowed; + * Test that if we have several subsequent calls to + * clk_set_rate_range(), across multiple users, the core will reevaluate + * whether a new rate is needed each and every time. * - * The clock will run at the maximum of all minimum boundaries - * requested, even if those boundaries aren't there anymore. + * With clk_dummy_minimize_rate_ops, this means that the rate will + * trail along the minimum as it evolves. */ static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test) { @@ -773,7 +767,7 @@ static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test) rate = clk_get_rate(clk); KUNIT_ASSERT_GT(test, rate, 0); - KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); clk_put(user2); clk_put(user1); -- cgit v1.2.3 From c97448437847bd76116b3a077e44808e946bb1ae Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:29 +0100 Subject: clk: Add clk_drop_range In order to reset the range on a clock, we need to call clk_set_rate_range with a minimum of 0 and a maximum of ULONG_MAX. Since it's fairly inconvenient, let's introduce a clk_drop_range() function that will do just this. Suggested-by: Stephen Boyd Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-8-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk_test.c | 4 ++-- include/linux/clk.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 8924a5ac56d8..48f95d1784c8 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -645,7 +645,7 @@ static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test) KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); KUNIT_ASSERT_EQ(test, - clk_set_rate_range(user2, 0, ULONG_MAX), + clk_drop_range(user2), 0); rate = clk_get_rate(clk); @@ -762,7 +762,7 @@ static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test) KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); KUNIT_ASSERT_EQ(test, - clk_set_rate_range(user2, 0, ULONG_MAX), + clk_drop_range(user2), 0); rate = clk_get_rate(clk); diff --git a/include/linux/clk.h b/include/linux/clk.h index 266e8de3cb51..39faa54efe88 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -986,6 +986,17 @@ static inline void clk_bulk_disable_unprepare(int num_clks, clk_bulk_unprepare(num_clks, clks); } +/** + * clk_drop_range - Reset any range set on that clock + * @clk: clock source + * + * Returns success (0) or negative errno. + */ +static inline int clk_drop_range(struct clk *clk) +{ + return clk_set_rate_range(clk, 0, ULONG_MAX); +} + /** * clk_get_optional - lookup and obtain a reference to an optional clock * producer. -- cgit v1.2.3 From 12c90f3f27bb3ad0dd3fad1550fec87091aa3329 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:30 +0100 Subject: clk: bcm: rpi: Add variant structure We only export a bunch of firmware clocks, and some of them require special treatment. This has been do so far using some tests on the clock id in various places, but this is fairly hard to extend and doesn't scale very well. Since we'll need some more cases in the next patches, let's switch to a variant structure that defines the behaviour we need to have for a given clock. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-9-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-raspberrypi.c | 64 ++++++++++++++++++++++++++++----------- 1 file changed, 47 insertions(+), 17 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c index dd3b71eafabf..f7185d421085 100644 --- a/drivers/clk/bcm/clk-raspberrypi.c +++ b/drivers/clk/bcm/clk-raspberrypi.c @@ -56,6 +56,8 @@ static char *rpi_firmware_clk_names[] = { #define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0) #define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1) +struct raspberrypi_clk_variant; + struct raspberrypi_clk { struct device *dev; struct rpi_firmware *firmware; @@ -66,10 +68,36 @@ struct raspberrypi_clk_data { struct clk_hw hw; unsigned int id; + struct raspberrypi_clk_variant *variant; struct raspberrypi_clk *rpi; }; +struct raspberrypi_clk_variant { + bool export; + char *clkdev; +}; + +static struct raspberrypi_clk_variant +raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = { + [RPI_FIRMWARE_ARM_CLK_ID] = { + .export = true, + .clkdev = "cpu0", + }, + [RPI_FIRMWARE_CORE_CLK_ID] = { + .export = true, + }, + [RPI_FIRMWARE_M2MC_CLK_ID] = { + .export = true, + }, + [RPI_FIRMWARE_V3D_CLK_ID] = { + .export = true, + }, + [RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = { + .export = true, + }, +}; + /* * Structure of the message passed to Raspberry Pi's firmware in order to * change clock rates. The 'disable_turbo' option is only available to the ARM @@ -183,7 +211,8 @@ static const struct clk_ops raspberrypi_firmware_clk_ops = { static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi, unsigned int parent, - unsigned int id) + unsigned int id, + struct raspberrypi_clk_variant *variant) { struct raspberrypi_clk_data *data; struct clk_init_data init = {}; @@ -195,6 +224,7 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi, return ERR_PTR(-ENOMEM); data->rpi = rpi; data->id = id; + data->variant = variant; init.name = devm_kasprintf(rpi->dev, GFP_KERNEL, "fw-clk-%s", @@ -228,9 +258,9 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi, clk_hw_set_rate_range(&data->hw, min_rate, max_rate); - if (id == RPI_FIRMWARE_ARM_CLK_ID) { + if (variant->clkdev) { ret = devm_clk_hw_register_clkdev(rpi->dev, &data->hw, - NULL, "cpu0"); + NULL, variant->clkdev); if (ret) { dev_err(rpi->dev, "Failed to initialize clkdev\n"); return ERR_PTR(ret); @@ -264,27 +294,27 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi, return ret; while (clks->id) { - struct clk_hw *hw; - - switch (clks->id) { - case RPI_FIRMWARE_ARM_CLK_ID: - case RPI_FIRMWARE_CORE_CLK_ID: - case RPI_FIRMWARE_M2MC_CLK_ID: - case RPI_FIRMWARE_V3D_CLK_ID: - case RPI_FIRMWARE_PIXEL_BVB_CLK_ID: + struct raspberrypi_clk_variant *variant; + + if (clks->id > RPI_FIRMWARE_NUM_CLK_ID) { + dev_err(rpi->dev, "Unknown clock id: %u", clks->id); + return -EINVAL; + } + + variant = &raspberrypi_clk_variants[clks->id]; + if (variant->export) { + struct clk_hw *hw; + hw = raspberrypi_clk_register(rpi, clks->parent, - clks->id); + clks->id, variant); if (IS_ERR(hw)) return PTR_ERR(hw); data->hws[clks->id] = hw; data->num = clks->id + 1; - fallthrough; - - default: - clks++; - break; } + + clks++; } return 0; -- cgit v1.2.3 From 542acfec4e313c001f9b82332f4fa2848ec7bf58 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:31 +0100 Subject: clk: bcm: rpi: Set a default minimum rate The M2MC clock provides the state machine clock for both HDMI controllers. However, if no HDMI monitor is plugged in at boot, its clock rate will be left at 0 by the firmware and will make any register access end up in a CPU stall, even though the clock was enabled. We had some code in the HDMI controller to deal with this before, but it makes more sense to have it in the clock driver. Move it there. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-10-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-raspberrypi.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c index f7185d421085..c879f2e9a4a7 100644 --- a/drivers/clk/bcm/clk-raspberrypi.c +++ b/drivers/clk/bcm/clk-raspberrypi.c @@ -76,6 +76,7 @@ struct raspberrypi_clk_data { struct raspberrypi_clk_variant { bool export; char *clkdev; + unsigned long min_rate; }; static struct raspberrypi_clk_variant @@ -89,6 +90,18 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = { }, [RPI_FIRMWARE_M2MC_CLK_ID] = { .export = true, + + /* + * If we boot without any cable connected to any of the + * HDMI connector, the firmware will skip the HSM + * initialization and leave it with a rate of 0, + * resulting in a bus lockup when we're accessing the + * registers even if it's enabled. + * + * Let's put a sensible default so that we don't end up + * in this situation. + */ + .min_rate = 120000000, }, [RPI_FIRMWARE_V3D_CLK_ID] = { .export = true, @@ -267,6 +280,19 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi, } } + if (variant->min_rate) { + unsigned long rate; + + clk_hw_set_rate_range(&data->hw, variant->min_rate, max_rate); + + rate = raspberrypi_fw_get_rate(&data->hw, 0); + if (rate < variant->min_rate) { + ret = raspberrypi_fw_set_rate(&data->hw, variant->min_rate, 0); + if (ret) + return ERR_PTR(ret); + } + } + return &data->hw; } -- cgit v1.2.3 From e9d6cea2af1cf8d84287ff2287b6cd776f7475d2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Feb 2022 15:35:32 +0100 Subject: clk: bcm: rpi: Run some clocks at the minimum rate allowed The core clock and M2MC clocks are shared between some devices (Unicam controllers and the HVS, and the HDMI controllers, respectively) that will have various, varying, requirements depending on their current work load. Since those loads can require a fairly high clock rate in extreme conditions (up to ~600MHz), we can end up running those clocks at their maximum frequency even though we no longer require such a high rate. Fortunately, those devices don't require an exact rate but a minimum rate, and all the drivers are using clk_set_min_rate. Thus, we can just rely on the fact that the clk_request minimum (which is the aggregated minimum of all the clock users) is what we want at all times. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220225143534.405820-11-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-raspberrypi.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c index c879f2e9a4a7..9d09621549b9 100644 --- a/drivers/clk/bcm/clk-raspberrypi.c +++ b/drivers/clk/bcm/clk-raspberrypi.c @@ -77,6 +77,7 @@ struct raspberrypi_clk_variant { bool export; char *clkdev; unsigned long min_rate; + bool minimize; }; static struct raspberrypi_clk_variant @@ -87,6 +88,18 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = { }, [RPI_FIRMWARE_CORE_CLK_ID] = { .export = true, + + /* + * The clock is shared between the HVS and the CSI + * controllers, on the BCM2711 and will change depending + * on the pixels composited on the HVS and the capture + * resolution on Unicam. + * + * Since the rate can get quite large, and we need to + * coordinate between both driver instances, let's + * always use the minimum the drivers will let us. + */ + .minimize = true, }, [RPI_FIRMWARE_M2MC_CLK_ID] = { .export = true, @@ -102,6 +115,16 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = { * in this situation. */ .min_rate = 120000000, + + /* + * The clock is shared between the two HDMI controllers + * on the BCM2711 and will change depending on the + * resolution output on each. Since the rate can get + * quite large, and we need to coordinate between both + * driver instances, let's always use the minimum the + * drivers will let us. + */ + .minimize = true, }, [RPI_FIRMWARE_V3D_CLK_ID] = { .export = true, @@ -206,12 +229,26 @@ static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate, static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { + struct raspberrypi_clk_data *data = + container_of(hw, struct raspberrypi_clk_data, hw); + struct raspberrypi_clk_variant *variant = data->variant; + /* * The firmware will do the rounding but that isn't part of * the interface with the firmware, so we just do our best * here. */ + req->rate = clamp(req->rate, req->min_rate, req->max_rate); + + /* + * We want to aggressively reduce the clock rate here, so let's + * just ignore the requested rate and return the bare minimum + * rate we can get away with. + */ + if (variant->minimize && req->min_rate > 0) + req->rate = req->min_rate; + return 0; } -- cgit v1.2.3 From 6d6ef58c2470da85a99119f74d34216c8074b9f0 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Wed, 12 Jan 2022 10:45:01 +0000 Subject: clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver The reference taken by 'of_find_device_by_node()' must be released when not needed anymore. Add the corresponding 'put_device()' in the error handling path. Fixes: 2db04f16b589 ("clk: tegra: Add EMC clock driver") Signed-off-by: Miaoqian Lin Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20220112104501.30655-1-linmq006@gmail.com Signed-off-by: Stephen Boyd --- drivers/clk/tegra/clk-tegra124-emc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/tegra/clk-tegra124-emc.c b/drivers/clk/tegra/clk-tegra124-emc.c index 74c1d894cca8..219c80653dbd 100644 --- a/drivers/clk/tegra/clk-tegra124-emc.c +++ b/drivers/clk/tegra/clk-tegra124-emc.c @@ -198,6 +198,7 @@ static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra) tegra->emc = platform_get_drvdata(pdev); if (!tegra->emc) { + put_device(&pdev->dev); pr_err("%s: cannot find EMC driver\n", __func__); return NULL; } -- cgit v1.2.3 From 09e3b18ca5def4680b65d60159e595dbbcf7743f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 22 Feb 2022 15:07:32 +0100 Subject: clk: bcm2835: Remove unused variable Since commit 8ca011ef4af4 ("clk: bcm-2835: Remove rounding up the dividers"), the rem variable is still set but no longer used. Remove it. Fixes: 8ca011ef4af4 ("clk: bcm-2835: Remove rounding up the dividers") Reported-by: kernel test robot Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220222140732.253819-1-maxime@cerno.tech Reviewed-by: Florian Fainelli Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-bcm2835.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 3667b4d731e7..3ad20e75fd23 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -939,10 +939,8 @@ static u32 bcm2835_clock_choose_div(struct clk_hw *hw, u32 unused_frac_mask = GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; - u64 rem; u32 div, mindiv, maxdiv; - rem = do_div(temp, rate); div = temp; div &= ~unused_frac_mask; -- cgit v1.2.3 From cde8e3ae3d374bf7826d87bcb6b28fb334dcaf82 Mon Sep 17 00:00:00 2001 From: "Minghao Chi (CGEL ZTE)" Date: Thu, 3 Mar 2022 01:48:56 +0000 Subject: clk: Use of_device_get_match_data() Use of_device_get_match_data() to simplify the code. Reported-by: Zeal Robot Signed-off-by: Minghao Chi (CGEL ZTE) Link: https://lore.kernel.org/r/20220303014856.2059307-1-chi.minghao@zte.com.cn Acked-by: Neil Armstrong Signed-off-by: Stephen Boyd --- drivers/clk/clk-oxnas.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-oxnas.c b/drivers/clk/clk-oxnas.c index 78d5ea669fea..cda5e258355b 100644 --- a/drivers/clk/clk-oxnas.c +++ b/drivers/clk/clk-oxnas.c @@ -209,15 +209,11 @@ static int oxnas_stdclk_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct oxnas_stdclk_data *data; - const struct of_device_id *id; struct regmap *regmap; int ret; int i; - id = of_match_device(oxnas_stdclk_dt_ids, &pdev->dev); - if (!id) - return -ENODEV; - data = id->data; + data = of_device_get_match_data(&pdev->dev); regmap = syscon_node_to_regmap(of_get_parent(np)); if (IS_ERR(regmap)) { -- cgit v1.2.3 From 7cd5c56054f8340218b65bd6e4cc04614a4ab89c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 24 Feb 2022 16:29:17 +0100 Subject: clk: COMMON_CLK_LAN966X should depend on SOC_LAN966 The LAN966x Generic Clock Controller is only present on Microchip LAN966x SoCs. Hence add a dependency on SOC_LAN966, to prevent asking the user about this driver when configuring a kernel without LAN966x SoC support. Fixes: 54104ee023333e3b ("clk: lan966x: Add lan966x SoC clock driver") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/eb102eae05e5667b9bd342a0c387f7f262d24bda.1645716471.git.geert+renesas@glider.be Reviewed-by: Horatiu Vultur Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..042092d00413 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -231,6 +231,7 @@ config COMMON_CLK_GEMINI config COMMON_CLK_LAN966X bool "Generic Clock Controller driver for LAN966X SoC" + depends on SOC_LAN966 || COMPILE_TEST help This driver provides support for Generic Clock Controller(GCK) on LAN966X SoC. GCK generates and supplies clock to various peripherals -- cgit v1.2.3 From ca85a66710a8a1f6b0719397225c3e9ee0abb692 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 9 Mar 2022 15:55:18 +0900 Subject: clk: uniphier: Fix fixed-rate initialization Fixed-rate clocks in UniPhier don't have any parent clocks, however, initial data "init.flags" isn't initialized, so it might be determined that there is a parent clock for fixed-rate clock. This sets init.flags to zero as initialization. Cc: Fixes: 734d82f4a678 ("clk: uniphier: add core support code for UniPhier clock driver") Signed-off-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/1646808918-30899-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd --- drivers/clk/uniphier/clk-uniphier-fixed-rate.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-rate.c b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c index 5319cd380480..3bc55ab75314 100644 --- a/drivers/clk/uniphier/clk-uniphier-fixed-rate.c +++ b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c @@ -24,6 +24,7 @@ struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev, init.name = name; init.ops = &clk_fixed_rate_ops; + init.flags = 0; init.parent_names = NULL; init.num_parents = 0; -- cgit v1.2.3 From 635e5e73370e7a5974c09b86cccd96e562bfeee8 Mon Sep 17 00:00:00 2001 From: Daire McNamara Date: Tue, 22 Feb 2022 12:11:44 +0000 Subject: clk: microchip: Add driver for Microchip PolarFire SoC Add support for clock configuration on Microchip PolarFire SoC Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Co-developed-by: Padmarao Begari Signed-off-by: Padmarao Begari Signed-off-by: Daire McNamara Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Link: https://lore.kernel.org/r/20220222121143.3316880-2-conor.dooley@microchip.com Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 4 +- drivers/clk/Makefile | 2 +- drivers/clk/microchip/Kconfig | 10 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk-mpfs.c | 381 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 394 insertions(+), 4 deletions(-) create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/clk-mpfs.c (limited to 'drivers/clk') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..678a865021e2 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -330,9 +330,6 @@ config COMMON_CLK_PXA help Support for the Marvell PXA SoC. -config COMMON_CLK_PIC32 - def_bool COMMON_CLK && MACH_PIC32 - config COMMON_CLK_OXNAS bool "Clock driver for the OXNAS SoC Family" depends on ARCH_OXNAS || COMPILE_TEST @@ -407,6 +404,7 @@ source "drivers/clk/keystone/Kconfig" source "drivers/clk/mediatek/Kconfig" source "drivers/clk/meson/Kconfig" source "drivers/clk/mstar/Kconfig" +source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..61271926b16b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -91,7 +91,7 @@ obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ obj-$(CONFIG_MACH_LOONGSON32) += loongson1/ obj-y += mediatek/ obj-$(CONFIG_ARCH_MESON) += meson/ -obj-$(CONFIG_MACH_PIC32) += microchip/ +obj-y += microchip/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig new file mode 100644 index 000000000000..a5a99873c4f5 --- /dev/null +++ b/drivers/clk/microchip/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +config COMMON_CLK_PIC32 + def_bool COMMON_CLK && MACH_PIC32 + +config MCHP_CLK_MPFS + bool "Clk driver for PolarFire SoC" + depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST + help + Supports Clock Configuration for PolarFire SoC diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile index f34b247e870f..5fa6dcf30a9a 100644 --- a/drivers/clk/microchip/Makefile +++ b/drivers/clk/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o +obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c new file mode 100644 index 000000000000..aa1561b773d6 --- /dev/null +++ b/drivers/clk/microchip/clk-mpfs.c @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Daire McNamara, + * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include + +/* address offset of control registers */ +#define REG_CLOCK_CONFIG_CR 0x08u +#define REG_SUBBLK_CLOCK_CR 0x84u +#define REG_SUBBLK_RESET_CR 0x88u + +struct mpfs_clock_data { + void __iomem *base; + struct clk_hw_onecell_data hw_data; +}; + +struct mpfs_cfg_clock { + const struct clk_div_table *table; + unsigned int id; + u8 shift; + u8 width; +}; + +struct mpfs_cfg_hw_clock { + struct mpfs_cfg_clock cfg; + void __iomem *sys_base; + struct clk_hw hw; + struct clk_init_data init; +}; + +#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) + +struct mpfs_periph_clock { + unsigned int id; + u8 shift; +}; + +struct mpfs_periph_hw_clock { + struct mpfs_periph_clock periph; + void __iomem *sys_base; + struct clk_hw hw; +}; + +#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) + +/* + * mpfs_clk_lock prevents anything else from writing to the + * mpfs clk block while a software locked register is being written. + */ +static DEFINE_SPINLOCK(mpfs_clk_lock); + +static const struct clk_parent_data mpfs_cfg_parent[] = { + { .index = 0 }, +}; + +static const struct clk_div_table mpfs_div_cpu_axi_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 0, 0 } +}; + +static const struct clk_div_table mpfs_div_ahb_table[] = { + { 1, 2 }, { 2, 4}, { 3, 8 }, + { 0, 0 } +}; + +static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + u32 val; + + val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; + val &= clk_div_mask(cfg->width); + + return prate / (1u << val); +} + +static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; + + return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); +} + +static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); + struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + unsigned long flags; + u32 val; + int divider_setting; + + divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + val = readl_relaxed(base_addr + REG_CLOCK_CONFIG_CR); + val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); + val |= divider_setting << cfg->shift; + writel_relaxed(val, base_addr + REG_CLOCK_CONFIG_CR); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + +static const struct clk_ops mpfs_clk_cfg_ops = { + .recalc_rate = mpfs_cfg_clk_recalc_rate, + .round_rate = mpfs_cfg_clk_round_rate, + .set_rate = mpfs_cfg_clk_set_rate, +}; + +#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags) { \ + .cfg.id = _id, \ + .cfg.shift = _shift, \ + .cfg.width = _width, \ + .cfg.table = _table, \ + .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_cfg_ops, \ + _flags), \ +} + +static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { + CLK_CFG(CLK_CPU, "clk_cpu", mpfs_cfg_parent, 0, 2, mpfs_div_cpu_axi_table, 0), + CLK_CFG(CLK_AXI, "clk_axi", mpfs_cfg_parent, 2, 2, mpfs_div_cpu_axi_table, 0), + CLK_CFG(CLK_AHB, "clk_ahb", mpfs_cfg_parent, 4, 2, mpfs_div_ahb_table, 0), +}; + +static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, + void __iomem *sys_base) +{ + cfg_hw->sys_base = sys_base; + + return devm_clk_hw_register(dev, &cfg_hw->hw); +} + +static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, + unsigned int num_clks, struct mpfs_clock_data *data) +{ + void __iomem *sys_base = data->base; + unsigned int i, id; + int ret; + + for (i = 0; i < num_clks; i++) { + struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; + + ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); + if (ret) + return dev_err_probe(dev, ret, "failed to register clock id: %d\n", + cfg_hw->cfg.id); + + id = cfg_hws[i].cfg.id; + data->hw_data.hws[id] = &cfg_hw->hw; + } + + return 0; +} + +static int mpfs_periph_clk_enable(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + unsigned long flags; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); + val = reg & ~(1u << periph->shift); + writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg | (1u << periph->shift); + writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + +static void mpfs_periph_clk_disable(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + unsigned long flags; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); + val = reg | (1u << periph->shift); + writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg & ~(1u << periph->shift); + writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); +} + +static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) +{ + struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); + struct mpfs_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg; + + reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); + if ((reg & (1u << periph->shift)) == 0u) { + reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + if (reg & (1u << periph->shift)) + return 1; + } + + return 0; +} + +static const struct clk_ops mpfs_periph_clk_ops = { + .enable = mpfs_periph_clk_enable, + .disable = mpfs_periph_clk_disable, + .is_enabled = mpfs_periph_clk_is_enabled, +}; + +#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ + .periph.id = _id, \ + .periph.shift = _shift, \ + .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ + _flags), \ +} + +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw) + +/* + * Critical clocks: + * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt + * trap handler + * - CLK_MMUART0: reserved by the hss + * - CLK_DDRC: provides clock to the ddr subsystem + * - CLK_FICx: these provide clocks for sections of the fpga fabric, disabling them would + * cause the fabric to go into reset + */ + +static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { + CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0), + CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0), + CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0), + CLK_PERIPH(CLK_TIMER, "clk_periph_timer", PARENT_CLK(AHB), 4, 0), + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0), + CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0), + CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0), + CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0), + CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0), + CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0), + CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0), + CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0), + CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0), + CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0), + CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0), + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, 0), + CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0), + CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0), + CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0), + CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0), + CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", PARENT_CLK(AHB), 24, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", PARENT_CLK(AHB), 25, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", PARENT_CLK(AHB), 26, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", PARENT_CLK(AHB), 27, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", PARENT_CLK(AHB), 28, 0), + CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), +}; + +static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, + void __iomem *sys_base) +{ + periph_hw->sys_base = sys_base; + + return devm_clk_hw_register(dev, &periph_hw->hw); +} + +static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, + int num_clks, struct mpfs_clock_data *data) +{ + void __iomem *sys_base = data->base; + unsigned int i, id; + int ret; + + for (i = 0; i < num_clks; i++) { + struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; + + ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); + if (ret) + return dev_err_probe(dev, ret, "failed to register clock id: %d\n", + periph_hw->periph.id); + + id = periph_hws[i].periph.id; + data->hw_data.hws[id] = &periph_hw->hw; + } + + return 0; +} + +static int mpfs_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_clock_data *clk_data; + unsigned int num_clks; + int ret; + + /* CLK_RESERVED is not part of cfg_clks nor periph_clks, so add 1 */ + num_clks = ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1; + + clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(clk_data->base)) + return PTR_ERR(clk_data->base); + + clk_data->hw_data.num = num_clks; + + ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); + if (ret) + return ret; + + ret = mpfs_clk_register_periphs(dev, mpfs_periph_clks, ARRAY_SIZE(mpfs_periph_clks), + clk_data); + if (ret) + return ret; + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); + if (ret) + return ret; + + return ret; +} + +static const struct of_device_id mpfs_clk_of_match_table[] = { + { .compatible = "microchip,mpfs-clkcfg", }, + {} +}; +MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); + +static struct platform_driver mpfs_clk_driver = { + .probe = mpfs_clk_probe, + .driver = { + .name = "microchip-mpfs-clkcfg", + .of_match_table = mpfs_clk_of_match_table, + }, +}; + +static int __init clk_mpfs_init(void) +{ + return platform_driver_register(&mpfs_clk_driver); +} +core_initcall(clk_mpfs_init); + +static void __exit clk_mpfs_exit(void) +{ + platform_driver_unregister(&mpfs_clk_driver); +} +module_exit(clk_mpfs_exit); + +MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 6641057d5dba87338780cf3e0d0ae8389ef1125c Mon Sep 17 00:00:00 2001 From: Martin Povišer Date: Tue, 8 Feb 2022 19:34:10 +0100 Subject: clk: clk-apple-nco: Add driver for Apple NCO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a common clock driver for NCO blocks found on Apple SoCs where they are typically the generators of audio clocks. Signed-off-by: Martin Povišer Link: https://lore.kernel.org/r/20220208183411.61090-3-povik+lin@cutebit.org Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 9 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-apple-nco.c | 334 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 344 insertions(+) create mode 100644 drivers/clk/clk-apple-nco.c (limited to 'drivers/clk') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..af4d037e18e3 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -59,6 +59,15 @@ config LMK04832 Say yes here to build support for Texas Instruments' LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs +config COMMON_CLK_APPLE_NCO + bool "Clock driver for Apple SoC NCOs" + depends on ARCH_APPLE || COMPILE_TEST + default ARCH_APPLE + help + This driver supports NCO (Numerically Controlled Oscillator) blocks + found on Apple SoCs such as t8103 (M1). The blocks are typically + generators of audio clocks. + config COMMON_CLK_MAX77686 tristate "Clock driver for Maxim 77620/77686/77802 MFD" depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..e95e702bdaeb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ endif # hardware specific clock types # please keep this section sorted lexicographically by file path name +obj-$(CONFIG_COMMON_CLK_APPLE_NCO) += clk-apple-nco.o obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o diff --git a/drivers/clk/clk-apple-nco.c b/drivers/clk/clk-apple-nco.c new file mode 100644 index 000000000000..208ee2945209 --- /dev/null +++ b/drivers/clk/clk-apple-nco.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Driver for an SoC block (Numerically Controlled Oscillator) + * found on t8103 (M1) and other Apple chips + * + * Copyright (C) The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NCO_CHANNEL_STRIDE 0x4000 +#define NCO_CHANNEL_REGSIZE 20 + +#define REG_CTRL 0 +#define CTRL_ENABLE BIT(31) +#define REG_DIV 4 +#define DIV_FINE GENMASK(1, 0) +#define DIV_COARSE GENMASK(12, 2) +#define REG_INC1 8 +#define REG_INC2 12 +#define REG_ACCINIT 16 + +/* + * Theory of operation (postulated) + * + * The REG_DIV register indirectly expresses a base integer divisor, roughly + * corresponding to twice the desired ratio of input to output clock. This + * base divisor is adjusted on a cycle-by-cycle basis based on the state of a + * 32-bit phase accumulator to achieve a desired precise clock ratio over the + * long term. + * + * Specifically an output clock cycle is produced after (REG_DIV divisor)/2 + * or (REG_DIV divisor + 1)/2 input cycles, the latter taking effect when top + * bit of the 32-bit accumulator is set. The accumulator is incremented each + * produced output cycle, by the value from either REG_INC1 or REG_INC2, which + * of the two is selected depending again on the accumulator's current top bit. + * + * Because the NCO hardware implements counting of input clock cycles in part + * in a Galois linear-feedback shift register, the higher bits of divisor + * are programmed into REG_DIV by picking an appropriate LFSR state. See + * applnco_compute_tables/applnco_div_translate for details on this. + */ + +#define LFSR_POLY 0xa01 +#define LFSR_INIT 0x7ff +#define LFSR_LEN 11 +#define LFSR_PERIOD ((1 << LFSR_LEN) - 1) +#define LFSR_TBLSIZE (1 << LFSR_LEN) + +/* The minimal attainable coarse divisor (first value in table) */ +#define COARSE_DIV_OFFSET 2 + +struct applnco_tables { + u16 fwd[LFSR_TBLSIZE]; + u16 inv[LFSR_TBLSIZE]; +}; + +struct applnco_channel { + void __iomem *base; + struct applnco_tables *tbl; + struct clk_hw hw; + + spinlock_t lock; +}; + +#define to_applnco_channel(_hw) container_of(_hw, struct applnco_channel, hw) + +static void applnco_enable_nolock(struct clk_hw *hw) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + u32 val; + + val = readl_relaxed(chan->base + REG_CTRL); + writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL); +} + +static void applnco_disable_nolock(struct clk_hw *hw) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + u32 val; + + val = readl_relaxed(chan->base + REG_CTRL); + writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL); +} + +static int applnco_is_enabled(struct clk_hw *hw) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + + return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0; +} + +static void applnco_compute_tables(struct applnco_tables *tbl) +{ + int i; + u32 state = LFSR_INIT; + + /* + * Go through the states of a Galois LFSR and build + * a coarse divisor translation table. + */ + for (i = LFSR_PERIOD; i > 0; i--) { + if (state & 1) + state = (state >> 1) ^ (LFSR_POLY >> 1); + else + state = (state >> 1); + tbl->fwd[i] = state; + tbl->inv[state] = i; + } + + /* Zero value is special-cased */ + tbl->fwd[0] = 0; + tbl->inv[0] = 0; +} + +static bool applnco_div_out_of_range(unsigned int div) +{ + unsigned int coarse = div / 4; + + return coarse < COARSE_DIV_OFFSET || + coarse >= COARSE_DIV_OFFSET + LFSR_TBLSIZE; +} + +static u32 applnco_div_translate(struct applnco_tables *tbl, unsigned int div) +{ + unsigned int coarse = div / 4; + + if (WARN_ON(applnco_div_out_of_range(div))) + return 0; + + return FIELD_PREP(DIV_COARSE, tbl->fwd[coarse - COARSE_DIV_OFFSET]) | + FIELD_PREP(DIV_FINE, div % 4); +} + +static unsigned int applnco_div_translate_inv(struct applnco_tables *tbl, u32 regval) +{ + unsigned int coarse, fine; + + coarse = tbl->inv[FIELD_GET(DIV_COARSE, regval)] + COARSE_DIV_OFFSET; + fine = FIELD_GET(DIV_FINE, regval); + + return coarse * 4 + fine; +} + +static int applnco_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + unsigned long flags; + u32 div, inc1, inc2; + bool was_enabled; + + div = 2 * parent_rate / rate; + inc1 = 2 * parent_rate - div * rate; + inc2 = inc1 - rate; + + if (applnco_div_out_of_range(div)) + return -EINVAL; + + div = applnco_div_translate(chan->tbl, div); + + spin_lock_irqsave(&chan->lock, flags); + was_enabled = applnco_is_enabled(hw); + applnco_disable_nolock(hw); + + writel_relaxed(div, chan->base + REG_DIV); + writel_relaxed(inc1, chan->base + REG_INC1); + writel_relaxed(inc2, chan->base + REG_INC2); + + /* Presumably a neutral initial value for accumulator */ + writel_relaxed(1 << 31, chan->base + REG_ACCINIT); + + if (was_enabled) + applnco_enable_nolock(hw); + spin_unlock_irqrestore(&chan->lock, flags); + + return 0; +} + +static unsigned long applnco_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + u32 div, inc1, inc2, incbase; + + div = applnco_div_translate_inv(chan->tbl, + readl_relaxed(chan->base + REG_DIV)); + + inc1 = readl_relaxed(chan->base + REG_INC1); + inc2 = readl_relaxed(chan->base + REG_INC2); + + /* + * We don't support wraparound of accumulator + * nor the edge case of both increments being zero + */ + if (inc1 >= (1 << 31) || inc2 < (1 << 31) || (inc1 == 0 && inc2 == 0)) + return 0; + + /* Scale both sides of division by incbase to maintain precision */ + incbase = inc1 - inc2; + + return div64_u64(((u64) parent_rate) * 2 * incbase, + ((u64) div) * incbase + inc1); +} + +static long applnco_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long lo = *parent_rate / (COARSE_DIV_OFFSET + LFSR_TBLSIZE) + 1; + unsigned long hi = *parent_rate / COARSE_DIV_OFFSET; + + return clamp(rate, lo, hi); +} + +static int applnco_enable(struct clk_hw *hw) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + applnco_enable_nolock(hw); + spin_unlock_irqrestore(&chan->lock, flags); + + return 0; +} + +static void applnco_disable(struct clk_hw *hw) +{ + struct applnco_channel *chan = to_applnco_channel(hw); + unsigned long flags; + + spin_lock_irqsave(&chan->lock, flags); + applnco_disable_nolock(hw); + spin_unlock_irqrestore(&chan->lock, flags); +} + +static const struct clk_ops applnco_ops = { + .set_rate = applnco_set_rate, + .recalc_rate = applnco_recalc_rate, + .round_rate = applnco_round_rate, + .enable = applnco_enable, + .disable = applnco_disable, + .is_enabled = applnco_is_enabled, +}; + +static int applnco_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init; + struct clk_hw_onecell_data *onecell_data; + void __iomem *base; + struct resource *res; + struct applnco_tables *tbl; + unsigned int nchannels; + int ret, i; + + base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + return PTR_ERR(base); + + if (resource_size(res) < NCO_CHANNEL_REGSIZE) + return -EINVAL; + nchannels = (resource_size(res) - NCO_CHANNEL_REGSIZE) + / NCO_CHANNEL_STRIDE + 1; + + onecell_data = devm_kzalloc(&pdev->dev, struct_size(onecell_data, hws, + nchannels), GFP_KERNEL); + if (!onecell_data) + return -ENOMEM; + onecell_data->num = nchannels; + + tbl = devm_kzalloc(&pdev->dev, sizeof(*tbl), GFP_KERNEL); + if (!tbl) + return -ENOMEM; + applnco_compute_tables(tbl); + + for (i = 0; i < nchannels; i++) { + struct applnco_channel *chan; + + chan = devm_kzalloc(&pdev->dev, sizeof(*chan), GFP_KERNEL); + if (!chan) + return -ENOMEM; + chan->base = base + NCO_CHANNEL_STRIDE * i; + chan->tbl = tbl; + spin_lock_init(&chan->lock); + + memset(&init, 0, sizeof(init)); + init.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%s-%d", np->name, i); + init.ops = &applnco_ops; + init.parent_data = &pdata; + init.num_parents = 1; + init.flags = 0; + + chan->hw.init = &init; + ret = devm_clk_hw_register(&pdev->dev, &chan->hw); + if (ret) + return ret; + + onecell_data->hws[i] = &chan->hw; + } + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + onecell_data); +} + +static const struct of_device_id applnco_ids[] = { + { .compatible = "apple,nco" }, + { } +}; +MODULE_DEVICE_TABLE(of, applnco_ids) + +static struct platform_driver applnco_driver = { + .driver = { + .name = "apple-nco", + .of_match_table = applnco_ids, + }, + .probe = applnco_probe, +}; +module_platform_driver(applnco_driver); + +MODULE_AUTHOR("Martin Povišer "); +MODULE_DESCRIPTION("Clock driver for NCO blocks on Apple SoCs"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 236541ace29edbc88ae4e81f3e4524f8e1d3fdf4 Mon Sep 17 00:00:00 2001 From: Martin Povišer Date: Sat, 12 Mar 2022 14:57:22 +0100 Subject: clk: clk-apple-nco: Allow and fix module building MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer Link: https://lore.kernel.org/r/20220312135722.20770-1-povik+lin@cutebit.org Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 2 +- drivers/clk/clk-apple-nco.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index af4d037e18e3..65e2f8c04f32 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -60,7 +60,7 @@ config LMK04832 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs config COMMON_CLK_APPLE_NCO - bool "Clock driver for Apple SoC NCOs" + tristate "Clock driver for Apple SoC NCOs" depends on ARCH_APPLE || COMPILE_TEST default ARCH_APPLE help diff --git a/drivers/clk/clk-apple-nco.c b/drivers/clk/clk-apple-nco.c index 208ee2945209..39472a51530a 100644 --- a/drivers/clk/clk-apple-nco.c +++ b/drivers/clk/clk-apple-nco.c @@ -318,7 +318,7 @@ static const struct of_device_id applnco_ids[] = { { .compatible = "apple,nco" }, { } }; -MODULE_DEVICE_TABLE(of, applnco_ids) +MODULE_DEVICE_TABLE(of, applnco_ids); static struct platform_driver applnco_driver = { .driver = { -- cgit v1.2.3 From 8850c3eae2c7a68ed901432a456ea70bbfef65a4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 10:56:16 +0200 Subject: clk: ti: Drop legacy compatibility clocks for am3 We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220203085618.16043-2-tony@atomide.com Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- drivers/clk/ti/Makefile | 3 +- drivers/clk/ti/clk-33xx-compat.c | 218 --------------------------------------- drivers/clk/ti/clk-33xx.c | 5 +- drivers/clk/ti/clkctrl.c | 8 +- include/dt-bindings/clock/am3.h | 93 ----------------- 5 files changed, 4 insertions(+), 323 deletions(-) delete mode 100644 drivers/clk/ti/clk-33xx-compat.c (limited to 'drivers/clk') diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index 5ca1e39dd88a..b9f54c7b50fd 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -6,8 +6,7 @@ clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ clkt_dpll.o clkt_iclk.o clkt_dflt.o \ clkctrl.o -obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \ - clk-33xx-compat.o +obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ diff --git a/drivers/clk/ti/clk-33xx-compat.c b/drivers/clk/ti/clk-33xx-compat.c deleted file mode 100644 index 3e07f127912a..000000000000 --- a/drivers/clk/ti/clk-33xx-compat.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * AM33XX Clock init - * - * Copyright (C) 2013 Texas Instruments, Inc - * Tero Kristo (t-kristo@ti.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "clock.h" - -static const char * const am3_gpio1_dbclk_parents[] __initconst = { - "l4_per_cm:clk:0138:0", - NULL, -}; - -static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = { - { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = { - { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = { - { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = { - { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, - { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" }, - { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" }, - { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" }, - { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, - { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, - { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, - { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, - { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, - { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, - { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, - { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, - { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, - { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, - { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, - { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, - { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, - { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, - { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, - { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, - { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, - { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" }, - { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" }, - { 0 }, -}; - -static const char * const am3_gpio0_dbclk_parents[] __initconst = { - "gpio0_dbclk_mux_ck", - NULL, -}; - -static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = { - { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL }, - { 0 }, -}; - -static const char * const am3_dbg_sysclk_ck_parents[] __initconst = { - "sys_clkin_ck", - NULL, -}; - -static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = { - "l4_wkup_cm:clk:0010:19", - "l4_wkup_cm:clk:0010:30", - NULL, -}; - -static const char * const am3_trace_clk_div_ck_parents[] __initconst = { - "l4_wkup_cm:clk:0010:20", - NULL, -}; - -static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = { - .max_div = 64, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const char * const am3_stm_clk_div_ck_parents[] __initconst = { - "l4_wkup_cm:clk:0010:22", - NULL, -}; - -static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = { - .max_div = 64, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const char * const am3_dbg_clka_ck_parents[] __initconst = { - "dpll_core_m4_ck", - NULL, -}; - -static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = { - { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL }, - { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, - { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL }, - { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data }, - { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data }, - { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = { - { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, - { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, - { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" }, - { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" }, - { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" }, - { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, - { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" }, - { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" }, - { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" }, - { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" }, - { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" }, - { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = { - { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = { - { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = { - { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = { - { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, - { 0 }, -}; - -const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = { - { 0x44e00014, am3_l4_per_clkctrl_regs }, - { 0x44e00404, am3_l4_wkup_clkctrl_regs }, - { 0x44e00604, am3_mpu_clkctrl_regs }, - { 0x44e00800, am3_l4_rtc_clkctrl_regs }, - { 0x44e00904, am3_gfx_l3_clkctrl_regs }, - { 0x44e00a20, am3_l4_cefuse_clkctrl_regs }, - { 0 }, -}; - -struct ti_dt_clk am33xx_compat_clks[] = { - DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"), - DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), - DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"), - DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"), - DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"), - DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"), - DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"), - DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"), - DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"), - DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"), - DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"), - DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"), - DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"), - { .node_name = NULL }, -}; diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index f2c22120aaa7..b4d142adede4 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -279,10 +279,7 @@ int __init am33xx_dt_clk_init(void) { struct clk *clk1, *clk2; - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - ti_dt_clocks_register(am33xx_compat_clks); - else - ti_dt_clocks_register(am33xx_clks); + ti_dt_clocks_register(am33xx_clks); omap2_clk_disable_autoidle_all(); diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 535f35b21204..b2778252716f 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -560,12 +560,8 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) soc_mask = CLKF_SOC_DRA76; #endif #ifdef CONFIG_SOC_AM33XX - if (of_machine_is_compatible("ti,am33xx")) { - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - data = am3_clkctrl_compat_data; - else - data = am3_clkctrl_data; - } + if (of_machine_is_compatible("ti,am33xx")) + data = am3_clkctrl_data; #endif #ifdef CONFIG_SOC_AM43XX if (of_machine_is_compatible("ti,am4372")) { diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h index 894951541276..dfbad5c87933 100644 --- a/include/dt-bindings/clock/am3.h +++ b/include/dt-bindings/clock/am3.h @@ -8,99 +8,6 @@ #define AM3_CLKCTRL_OFFSET 0x0 #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - /* l4ls clocks */ #define AM3_L4LS_CLKCTRL_OFFSET 0x38 #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) -- cgit v1.2.3 From e65eb2efc6175392f0e97f515e6e5b179e181cd8 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 10:56:17 +0200 Subject: clk: ti: Drop legacy compatibility clocks for am4 We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Cc: devicetree@vger.kernel.org Cc: Rob Herring Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220203085618.16043-3-tony@atomide.com Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- drivers/clk/ti/Makefile | 3 +- drivers/clk/ti/clk-43xx-compat.c | 225 --------------------------------------- drivers/clk/ti/clk-43xx.c | 5 +- drivers/clk/ti/clkctrl.c | 16 +-- drivers/clk/ti/clock.h | 3 - include/dt-bindings/clock/am4.h | 98 ----------------- 6 files changed, 6 insertions(+), 344 deletions(-) delete mode 100644 drivers/clk/ti/clk-43xx-compat.c (limited to 'drivers/clk') diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index b9f54c7b50fd..eb20c1e9bb95 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -18,8 +18,7 @@ obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ clk-dra7-atl.o dpll3xxx.o \ dpll44xx.o clk-7xx-compat.o -obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \ - clk-43xx-compat.o +obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o endif # CONFIG_ARCH_OMAP2PLUS diff --git a/drivers/clk/ti/clk-43xx-compat.c b/drivers/clk/ti/clk-43xx-compat.c deleted file mode 100644 index 513039843392..000000000000 --- a/drivers/clk/ti/clk-43xx-compat.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * AM43XX Clock init - * - * Copyright (C) 2013 Texas Instruments, Inc - * Tero Kristo (t-kristo@ti.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#include "clock.h" - -static const char * const am4_synctimer_32kclk_parents[] __initconst = { - "mux_synctimer32k_ck", - NULL, -}; - -static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL }, - { 0 }, -}; - -static const char * const am4_gpio0_dbclk_parents[] __initconst = { - "gpio0_dbclk_mux_ck", - NULL, -}; - -static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = { - { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" }, - { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, - { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" }, - { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" }, - { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" }, - { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" }, - { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, - { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" }, - { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" }, - { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" }, - { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, - { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = { - { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = { - { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = { - { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" }, - { 0 }, -}; - -static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = { - "dpll_per_clkdcoldo", - NULL, -}; - -static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL }, - { 0 }, -}; - -static const char * const am4_gpio1_dbclk_parents[] __initconst = { - "clkdiv32k_ick", - NULL, -}; - -static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = { - { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = { - { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" }, - { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, - { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" }, - { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" }, - { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" }, - { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, - { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" }, - { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" }, - { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" }, - { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, - { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, - { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" }, - { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" }, - { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" }, - { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" }, - { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" }, - { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, - { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" }, - { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" }, - { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" }, - { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" }, - { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" }, - { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" }, - { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" }, - { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" }, - { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" }, - { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" }, - { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" }, - { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" }, - { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" }, - { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" }, - { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" }, - { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk", "dss_clkdm" }, - { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" }, - { 0 }, -}; - -const struct omap_clkctrl_data am4_clkctrl_compat_data[] __initconst = { - { 0x44df2820, am4_l4_wkup_clkctrl_regs }, - { 0x44df8320, am4_mpu_clkctrl_regs }, - { 0x44df8420, am4_gfx_l3_clkctrl_regs }, - { 0x44df8520, am4_l4_rtc_clkctrl_regs }, - { 0x44df8820, am4_l4_per_clkctrl_regs }, - { 0 }, -}; - -const struct omap_clkctrl_data am438x_clkctrl_compat_data[] __initconst = { - { 0x44df2820, am4_l4_wkup_clkctrl_regs }, - { 0x44df8320, am4_mpu_clkctrl_regs }, - { 0x44df8420, am4_gfx_l3_clkctrl_regs }, - { 0x44df8820, am4_l4_per_clkctrl_regs }, - { 0 }, -}; - -struct ti_dt_clk am43xx_compat_clks[] = { - DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"), - DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), - DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"), - DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"), - DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"), - DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"), - DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"), - DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"), - DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"), - DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"), - DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"), - { .node_name = NULL }, -}; diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c index 6e97a541cfd3..2ff4ff3d95d5 100644 --- a/drivers/clk/ti/clk-43xx.c +++ b/drivers/clk/ti/clk-43xx.c @@ -282,10 +282,7 @@ int __init am43xx_dt_clk_init(void) { struct clk *clk1, *clk2; - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - ti_dt_clocks_register(am43xx_compat_clks); - else - ti_dt_clocks_register(am43xx_clks); + ti_dt_clocks_register(am43xx_clks); omap2_clk_disable_autoidle_all(); diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index b2778252716f..cccdb868cf4b 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -564,19 +564,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) data = am3_clkctrl_data; #endif #ifdef CONFIG_SOC_AM43XX - if (of_machine_is_compatible("ti,am4372")) { - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - data = am4_clkctrl_compat_data; - else - data = am4_clkctrl_data; - } + if (of_machine_is_compatible("ti,am4372")) + data = am4_clkctrl_data; - if (of_machine_is_compatible("ti,am438x")) { - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - data = am438x_clkctrl_compat_data; - else - data = am438x_clkctrl_data; - } + if (of_machine_is_compatible("ti,am438x")) + data = am438x_clkctrl_data; #endif #ifdef CONFIG_SOC_TI81XX if (of_machine_is_compatible("ti,dm814")) diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 938f34e290ed..c841d2d28111 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -201,10 +201,7 @@ extern const struct omap_clkctrl_data am3_clkctrl_data[]; extern const struct omap_clkctrl_data am3_clkctrl_compat_data[]; extern struct ti_dt_clk am33xx_compat_clks[]; extern const struct omap_clkctrl_data am4_clkctrl_data[]; -extern const struct omap_clkctrl_data am4_clkctrl_compat_data[]; -extern struct ti_dt_clk am43xx_compat_clks[]; extern const struct omap_clkctrl_data am438x_clkctrl_data[]; -extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[]; extern const struct omap_clkctrl_data dm814_clkctrl_data[]; extern const struct omap_clkctrl_data dm816_clkctrl_data[]; diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h index 4be6c5961f34..a65b082e9cff 100644 --- a/include/dt-bindings/clock/am4.h +++ b/include/dt-bindings/clock/am4.h @@ -8,104 +8,6 @@ #define AM4_CLKCTRL_OFFSET 0x20 #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_wkup clocks */ -#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) -#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) -#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228) -#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230) -#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328) -#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338) -#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340) -#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348) -#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350) -#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358) -#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360) -#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368) - -/* mpu clocks */ -#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* gfx_l3 clocks */ -#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_rtc clocks */ -#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) - -/* l4_per clocks */ -#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) -#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) -#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) -#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) -#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) -#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) -#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68) -#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70) -#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) -#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) -#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) -#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) -#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) -#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220) -#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238) -#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240) -#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248) -#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258) -#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260) -#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268) -#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320) -#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420) -#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428) -#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430) -#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438) -#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440) -#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448) -#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450) -#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458) -#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460) -#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468) -#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478) -#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480) -#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488) -#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490) -#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498) -#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0) -#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8) -#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0) -#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8) -#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0) -#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8) -#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0) -#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500) -#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508) -#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510) -#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518) -#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520) -#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528) -#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530) -#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538) -#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540) -#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548) -#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550) -#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558) -#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560) -#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568) -#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570) -#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578) -#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580) -#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588) -#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590) -#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598) -#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0) -#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8) -#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0) -#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720) -#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) -#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) - -/* XXX: Compatibility part end. */ - /* l3s_tsc clocks */ #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 #define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) -- cgit v1.2.3 From 579cdf58b7e50fa0650324667d240ecf45c7d12f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 3 Feb 2022 10:56:18 +0200 Subject: clk: ti: Drop legacy compatibility clocks for dra7 We no longer have users for the compatibility clocks and we can drop them. These are old duplicate clocks for what we using. Depends-on: 31aa7056bbec ("ARM: dts: Don't use legacy clock defines for dra7 clkctrl") Depends-on: 9206a3af4fc0 ("clk: ti: Move dra7 clock devices out of the legacy section") Cc: devicetree@vger.kernel.org Cc: Rob Herring Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20220203085618.16043-4-tony@atomide.com Acked-by: Rob Herring Signed-off-by: Stephen Boyd --- drivers/clk/ti/Makefile | 3 +- drivers/clk/ti/clk-7xx-compat.c | 820 --------------------------------------- drivers/clk/ti/clk-7xx.c | 5 +- drivers/clk/ti/clkctrl.c | 9 +- include/dt-bindings/clock/dra7.h | 168 -------- 5 files changed, 5 insertions(+), 1000 deletions(-) delete mode 100644 drivers/clk/ti/clk-7xx-compat.c (limited to 'drivers/clk') diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile index eb20c1e9bb95..2c6315cfd5c6 100644 --- a/drivers/clk/ti/Makefile +++ b/drivers/clk/ti/Makefile @@ -17,7 +17,8 @@ obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ clk-dra7-atl.o dpll3xxx.o \ - dpll44xx.o clk-7xx-compat.o + dpll44xx.o + obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o endif # CONFIG_ARCH_OMAP2PLUS diff --git a/drivers/clk/ti/clk-7xx-compat.c b/drivers/clk/ti/clk-7xx-compat.c deleted file mode 100644 index ddf7c8277946..000000000000 --- a/drivers/clk/ti/clk-7xx-compat.c +++ /dev/null @@ -1,820 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * DRA7 Clock init - * - * Copyright (C) 2013 Texas Instruments, Inc. - * - * Tero Kristo (t-kristo@ti.com) - */ - -#include -#include -#include -#include -#include -#include - -#include "clock.h" - -#define DRA7_DPLL_GMAC_DEFFREQ 1000000000 -#define DRA7_DPLL_USB_DEFFREQ 960000000 - -static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = { - { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, - { 0 }, -}; - -static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = { - "per_abe_x1_gfclk2_div", - "video1_clk2_div", - "video2_clk2_div", - "hdmi_clk2_div", - NULL, -}; - -static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = { - "abe_24m_fclk", - "abe_sys_clk_div", - "func_24m_clk", - "atl_clkin3_ck", - "atl_clkin2_ck", - "atl_clkin1_ck", - "atl_clkin0_ck", - "sys_clkin2", - "ref_clkin0_ck", - "ref_clkin1_ck", - "ref_clkin2_ck", - "ref_clkin3_ck", - "mlb_clk", - "mlbp_clk", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = { - "timer_sys_clk_div", - "sys_32k_ck", - "sys_clkin2", - "ref_clkin0_ck", - "ref_clkin1_ck", - "ref_clkin2_ck", - "ref_clkin3_ck", - "abe_giclk_div", - "video1_div_clk", - "video2_div_clk", - "hdmi_div_clk", - "clkoutmux0_clk_mux", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = { - "func_48m_fclk", - "dpll_per_m2x2_ck", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = { - { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" }, - { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" }, - { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" }, - { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" }, - { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" }, - { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, - { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = { - { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = { - { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, - { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = { - { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = { - { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = { - { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { 0 }, -}; - -static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = { - "sys_32k_ck", - "video1_clkin_ck", - "video2_clkin_ck", - "hdmi_clkin_ck", - NULL, -}; - -static const char * const dra7_atl_gfclk_mux_parents[] __initconst = { - "l3_iclk_div", - "dpll_abe_m2_ck", - "atl_cm:clk:0000:24", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL }, - { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = { - { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = { - { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = { - { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, - { 0 }, -}; - -static const char * const dra7_dss_dss_clk_parents[] __initconst = { - "dpll_per_h12x2_ck", - NULL, -}; - -static const char * const dra7_dss_48mhz_clk_parents[] __initconst = { - "func_48m_fclk", - NULL, -}; - -static const char * const dra7_dss_hdmi_clk_parents[] __initconst = { - "hdmi_dpll_clk_mux", - NULL, -}; - -static const char * const dra7_dss_32khz_clk_parents[] __initconst = { - "sys_32k_ck", - NULL, -}; - -static const char * const dra7_dss_video1_clk_parents[] __initconst = { - "video1_dpll_clk_mux", - NULL, -}; - -static const char * const dra7_dss_video2_clk_parents[] __initconst = { - "video2_dpll_clk_mux", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL }, - { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL }, - { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL }, - { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL }, - { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = { - { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, - { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" }, - { 0 }, -}; - -static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = { - "func_128m_clk", - "dpll_per_m2x2_ck", - NULL, -}; - -static const char * const dra7_mmc1_fclk_div_parents[] __initconst = { - "l3init_cm:clk:0008:24", - NULL, -}; - -static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = { - .max_div = 4, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, - { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data }, - { 0 }, -}; - -static const char * const dra7_mmc2_fclk_div_parents[] __initconst = { - "l3init_cm:clk:0010:24", - NULL, -}; - -static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = { - .max_div = 4, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL }, - { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data }, - { 0 }, -}; - -static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = { - "l3init_960m_gfclk", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_sata_ref_clk_parents[] __initconst = { - "sys_clkin1", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = { - "apll_pcie_ck", - NULL, -}; - -static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = { - "optfclk_pciephy_div", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, - { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL }, - { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = { - "dpll_gmac_h11x2_ck", - "rmii_clk_ck", - NULL, -}; - -static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = { - "video1_clkin_ck", - "video2_clkin_ck", - "dpll_abe_m2_ck", - "hdmi_clkin_ck", - "l3_iclk_div", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL }, - { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = { - { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, - { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, - { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, - { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, - { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" }, - { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, - { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, - { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" }, - { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" }, - { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, - { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, - { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, - { 0 }, -}; - -static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = { - "timer_sys_clk_div", - "sys_32k_ck", - "sys_clkin2", - "ref_clkin0_ck", - "ref_clkin1_ck", - "ref_clkin2_ck", - "ref_clkin3_ck", - "abe_giclk_div", - "video1_div_clk", - "video2_div_clk", - "hdmi_div_clk", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = { - "l4per_cm:clk:0120:24", - NULL, -}; - -static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = { - .max_div = 4, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data }, - { 0 }, -}; - -static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = { - "l4per_cm:clk:0128:24", - NULL, -}; - -static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = { - .max_div = 4, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = { - "func_128m_clk", - "dpll_per_h13x2_ck", - NULL, -}; - -static const char * const dra7_qspi_gfclk_div_parents[] __initconst = { - "l4per_cm:clk:0138:24", - NULL, -}; - -static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = { - .max_div = 4, - .flags = CLK_DIVIDER_POWER_OF_TWO, -}; - -static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL }, - { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = { - { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL }, - { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = { - { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" }, - { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" }, - { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, - { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, - { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" }, - { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" }, - { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" }, - { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" }, - { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" }, - { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, - { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, - { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, - { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, - { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, - { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, - { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" }, - { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" }, - { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" }, - { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" }, - { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" }, - { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, - { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, - { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, - { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, - { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" }, - { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" }, - { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" }, - { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" }, - { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" }, - { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" }, - { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" }, - { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" }, - { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" }, - { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" }, - { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" }, - { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" }, - { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" }, - { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" }, - { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" }, - { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, - { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, - { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, - { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" }, - { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" }, - { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" }, - { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" }, - { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" }, - { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" }, - { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" }, - { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = { - { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL }, - { 0 }, -}; - -static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = { - "sys_clkin1", - "sys_clkin2", - NULL, -}; - -static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = { - { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL }, - { 0 }, -}; - -static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = { - { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, - { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, - { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, - { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, - { DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" }, - { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, - { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" }, - { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" }, - { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"}, - { 0 }, -}; - -const struct omap_clkctrl_data dra7_clkctrl_compat_data[] __initconst = { - { 0x4a005320, dra7_mpu_clkctrl_regs }, - { 0x4a005540, dra7_ipu_clkctrl_regs }, - { 0x4a005740, dra7_rtc_clkctrl_regs }, - { 0x4a008620, dra7_coreaon_clkctrl_regs }, - { 0x4a008720, dra7_l3main1_clkctrl_regs }, - { 0x4a008a20, dra7_dma_clkctrl_regs }, - { 0x4a008b20, dra7_emif_clkctrl_regs }, - { 0x4a008c00, dra7_atl_clkctrl_regs }, - { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, - { 0x4a008e20, dra7_l3instr_clkctrl_regs }, - { 0x4a009120, dra7_dss_clkctrl_regs }, - { 0x4a009320, dra7_l3init_clkctrl_regs }, - { 0x4a009700, dra7_l4per_clkctrl_regs }, - { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, - { 0 }, -}; - -struct ti_dt_clk dra7xx_compat_clks[] = { - DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), - DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), - DT_CLK(NULL, "sys_clkin", "sys_clkin1"), - DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"), - DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"), - DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"), - DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), - DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), - DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), - DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"), - DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"), - DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"), - DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"), - DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), - DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"), - DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"), - DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"), - DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"), - DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"), - DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"), - DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"), - DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"), - DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"), - DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"), - DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"), - DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"), - DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"), - DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"), - DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"), - DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"), - DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"), - DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"), - DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"), - DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"), - DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"), - DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"), - DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"), - DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"), - DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"), - DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"), - DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"), - DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), - DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"), - DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"), - DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), - DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"), - DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"), - DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"), - DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"), - DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"), - DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"), - DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"), - DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"), - DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"), - DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"), - DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"), - DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"), - DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"), - DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"), - DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"), - DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), - DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"), - DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"), - DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"), - DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"), - DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"), - DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"), - DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), - DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"), - DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"), - DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"), - DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"), - DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"), - DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"), - DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"), - DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"), - DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"), - DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"), - DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"), - DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"), - DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"), - DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"), - DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"), - DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"), - DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"), - DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"), - DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"), - DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"), - { .node_name = NULL }, -}; diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 8b9118ccd4cd..0f099441543f 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -946,10 +946,7 @@ int __init dra7xx_dt_clk_init(void) int rc; struct clk *dpll_ck, *hdcp_ck; - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - ti_dt_clocks_register(dra7xx_compat_clks); - else - ti_dt_clocks_register(dra7xx_clks); + ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index cccdb868cf4b..792137a06069 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -545,13 +545,8 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) data = omap5_clkctrl_data; #endif #ifdef CONFIG_SOC_DRA7XX - if (of_machine_is_compatible("ti,dra7")) { - if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) - data = dra7_clkctrl_compat_data; - else - data = dra7_clkctrl_data; - } - + if (of_machine_is_compatible("ti,dra7")) + data = dra7_clkctrl_data; if (of_machine_is_compatible("ti,dra72")) soc_mask = CLKF_SOC_DRA72; if (of_machine_is_compatible("ti,dra74")) diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 29ff6b895848..8a903c78c5a5 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -8,174 +8,6 @@ #define DRA7_CLKCTRL_OFFSET 0x20 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* mpu clocks */ -#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define _DRA7_IPU_CLKCTRL_OFFSET 0x40 -#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) -#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) -#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) -#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) -#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) -#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) -#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) -#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) - -/* rtc clocks */ -#define DRA7_RTC_CLKCTRL_OFFSET 0x40 -#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) -#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) - -/* vip clocks */ -#define DRA7_VIP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_VIP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_VIP3_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* vpe clocks */ -#define DRA7_VPE_CLKCTRL_OFFSET 0x60 -#define DRA7_VPE_CLKCTRL_INDEX(offset) ((offset) - DRA7_VPE_CLKCTRL_OFFSET) -#define DRA7_VPE_CLKCTRL DRA7_VPE_CLKCTRL_INDEX(0x64) - -/* coreaon clocks */ -#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) - -/* l3main1 clocks */ -#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) - -/* dma clocks */ -#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) - -/* atl clocks */ -#define DRA7_ATL_CLKCTRL_OFFSET 0x0 -#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) -#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) - -/* l4cfg clocks */ -#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) -#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) -#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) -#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) -#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) -#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) -#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) -#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* l3instr clocks */ -#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) - -/* l3init clocks */ -#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) -#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) -#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) -#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) -#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) -#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) -#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) - -/* l4per clocks */ -#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 -#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) -#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) -#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) -#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) -#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) -#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) -#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) -#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) -#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) -#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) -#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) -#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) -#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) -#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) -#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) -#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) -#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) -#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) -#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) -#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) -#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) -#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) -#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) -#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) -#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) -#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) -#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) -#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) -#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) -#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) -#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) -#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) -#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) -#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) -#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) -#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) -#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) -#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) -#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) -#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) -#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) -#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) -#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) -#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) -#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) -#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) -#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) -#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) -#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) -#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) -#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) -#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) -#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) -#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) -#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) -#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) - -/* wkupaon clocks */ -#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) -#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) -#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) -#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) -#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) -#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) - -/* XXX: Compatibility part end. */ - /* mpu clocks */ #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) -- cgit v1.2.3 From 7a74e1e49622698fbf106fdc98da55f9e6634c14 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 15 Mar 2022 10:24:46 +0200 Subject: clk: imx: Select MXC_CLK for i.MX93 clock driver Most of the i.MX clock generic API is built by selecting MXC_CLK. Without it, the i.MX93 clock driver will fail to build: aarch64-linux-gnu-ld: drivers/clk/imx/clk-imx93.o: in function `imx93_clocks_probe': clk-imx93.c:(.text+0xa8): undefined reference to `imx_obtain_fixed_clk_hw' So fix this by selecting MXC_CLK for the CLK_IMX93. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Abel Vesa Reported-by: kernel test robot Link: https://lore.kernel.org/r/20220315082446.3120850-1-abel.vesa@nxp.com Reviewed-by: Peng Fan Signed-off-by: Stephen Boyd --- drivers/clk/imx/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index cc464a42d646..25785ec9c276 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -109,6 +109,7 @@ config CLK_IMX8ULP config CLK_IMX93 tristate "IMX93 CCM Clock Driver" depends on ARCH_MXC || COMPILE_TEST + select MXC_CLK help Build the driver for i.MX93 CCM Clock Driver -- cgit v1.2.3 From 6a6c2389ddf74c2b204a6900745d7a77abfc22f3 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 14 Mar 2022 12:53:38 +0100 Subject: clk: ti: clkctrl: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/20220314115354.144023-15-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd --- drivers/clk/ti/clkctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 864c484bde1b..170cdf9ea8f6 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -603,7 +603,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) /* * The code below can be removed when all clkctrl nodes use domain - * specific compatible proprerty and standard clock node naming + * specific compatible property and standard clock node naming */ if (legacy_naming) { provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent); -- cgit v1.2.3 From bb7f4b8c1e5c184d8a39c25ce40a73ef6ecba365 Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 14 Mar 2022 12:53:39 +0100 Subject: clk: qcom: sm6125-gcc: fix typos in comments Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/20220314115354.144023-16-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-sm6125.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c index 431b55bb0d2f..cf3af88d4021 100644 --- a/drivers/clk/qcom/gcc-sm6125.c +++ b/drivers/clk/qcom/gcc-sm6125.c @@ -4151,7 +4151,7 @@ static int gcc_sm6125_probe(struct platform_device *pdev) /* * Enable DUAL_EDGE mode for MCLK RCGs - * This is requierd to enable MND divider mode + * This is required to enable MND divider mode */ regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000); regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000); -- cgit v1.2.3 From e83da8e2a1c323021ecb57f9a738f08fdd7879f1 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Fri, 4 Mar 2022 18:03:17 +0800 Subject: clk: sifive: duplicate the macro definitions for the time being This is a temporary patch in whole patch set. We are going to change the macro name in dt-binding, in order to avoid breaking the driver build and git bisect, add these macro definitions for the time being, and we will remove them later. Signed-off-by: Zong Li Link: https://lore.kernel.org/r/8cfd57f01cfb59adb716eb13ca0c8250c246dcb2.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd --- drivers/clk/sifive/fu540-prci.c | 6 +++++- drivers/clk/sifive/fu740-prci.c | 11 ++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 29bab915003c..9e13119066eb 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -20,9 +20,13 @@ #include -#include "fu540-prci.h" #include "sifive-prci.h" +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 53f6e00a03b9..7141a22d90e3 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -8,9 +8,18 @@ #include -#include "fu540-prci.h" #include "sifive-prci.h" +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_DVFSCOREPLL 3 +#define PRCI_CLK_HFPCLKPLL 4 +#define PRCI_CLK_CLTXPLL 5 +#define PRCI_CLK_TLCLK 6 +#define PRCI_CLK_PCLK 7 +#define PRCI_CLK_PCIE_AUX 8 + /* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { -- cgit v1.2.3 From 24a4a29f755e457d5485c5d9a1006be560ae48ce Mon Sep 17 00:00:00 2001 From: Zong Li Date: Fri, 4 Mar 2022 18:03:20 +0800 Subject: clk: sifive: Add SoCs prefix in each SoCs-dependent data This patch is prerequisite for moving SoCs C files into SoCs header files. Currently, fu540-prci.c and fu740-prci.c use same names for several macro definitions and variables, it would cause redefinition error when we trying to include all stuff in sifive-prci.c. In this patch, we also remove the temporary macro definitions which are added by previous patch. Signed-off-by: Zong Li Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/7728ef662c59449ce954b1b62c6ad5241e07adfb.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd --- drivers/clk/sifive/fu540-prci.c | 29 +++++++++------------ drivers/clk/sifive/fu740-prci.c | 56 +++++++++++++++++------------------------ 2 files changed, 35 insertions(+), 50 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 9e13119066eb..672c782ad604 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * Copyright (C) 2018-2019 Wesley Terpstra * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2022 Zong Li * * The FU540 PRCI implements clock and reset control for the SiFive * FU540-C000 chip. This driver assumes that it has sole control @@ -22,26 +22,21 @@ #include "sifive-prci.h" -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - /* PRCI integration data for each WRPLL instance */ -static struct __prci_wrpll_data __prci_corepll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_coreclksel_use_hfclk, .disable_bypass = sifive_prci_coreclksel_use_corepll, }; -static struct __prci_wrpll_data __prci_ddrpll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_gemgxlpll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, }; @@ -67,25 +62,25 @@ static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &__prci_corepll_data, + .pwd = &sifive_fu540_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd = &__prci_ddrpll_data, + .pwd = &sifive_fu540_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &__prci_gemgxlpll_data, + .pwd = &sifive_fu540_prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 7141a22d90e3..f27d1a42d946 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 SiFive, Inc. - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2022 SiFive, Inc. + * Copyright (C) 2020-2022 Zong Li */ #include @@ -10,50 +10,40 @@ #include "sifive-prci.h" -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_DVFSCOREPLL 3 -#define PRCI_CLK_HFPCLKPLL 4 -#define PRCI_CLK_CLTXPLL 5 -#define PRCI_CLK_TLCLK 6 -#define PRCI_CLK_PCLK 7 -#define PRCI_CLK_PCIE_AUX 8 - /* PRCI integration data for each WRPLL instance */ -static struct __prci_wrpll_data __prci_corepll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_coreclksel_use_hfclk, .disable_bypass = sifive_prci_coreclksel_use_final_corepll, }; -static struct __prci_wrpll_data __prci_ddrpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_gemgxlpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_dvfscorepll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_corepllsel_use_corepll, .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, }; -static struct __prci_wrpll_data __prci_hfpclkpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, }; -static struct __prci_wrpll_data __prci_cltxpll_data = { +static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, }; @@ -89,53 +79,53 @@ static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] = { - [PRCI_CLK_COREPLL] = { + [FU740_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_corepll_data, + .pwd = &sifive_fu740_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU740_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd = &__prci_ddrpll_data, + .pwd = &sifive_fu740_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU740_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_gemgxlpll_data, + .pwd = &sifive_fu740_prci_gemgxlpll_data, }, - [PRCI_CLK_DVFSCOREPLL] = { + [FU740_PRCI_CLK_DVFSCOREPLL] = { .name = "dvfscorepll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_dvfscorepll_data, + .pwd = &sifive_fu740_prci_dvfscorepll_data, }, - [PRCI_CLK_HFPCLKPLL] = { + [FU740_PRCI_CLK_HFPCLKPLL] = { .name = "hfpclkpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_hfpclkpll_data, + .pwd = &sifive_fu740_prci_hfpclkpll_data, }, - [PRCI_CLK_CLTXPLL] = { + [FU740_PRCI_CLK_CLTXPLL] = { .name = "cltxpll", .parent_name = "hfclk", .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &__prci_cltxpll_data, + .pwd = &sifive_fu740_prci_cltxpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU740_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu740_prci_tlclksel_clk_ops, }, - [PRCI_CLK_PCLK] = { + [FU740_PRCI_CLK_PCLK] = { .name = "pclk", .parent_name = "hfpclkpll", .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, - [PRCI_CLK_PCIE_AUX] = { + [FU740_PRCI_CLK_PCIE_AUX] = { .name = "pcie_aux", .parent_name = "hfclk", .ops = &sifive_fu740_prci_pcie_aux_clk_ops, -- cgit v1.2.3 From 5e916932df639bc2eeecc96c3a1f2cce496f1a93 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Fri, 4 Mar 2022 18:03:21 +0800 Subject: clk: sifive: Move all stuff into SoCs header files from C files Improve PRCI driver to reduce the complexity, we remove the SoCs C files by putting all stuff in each SoCs header files, and include these SoCs-specific header files in core of PRCI. It can also avoid the W=1 kernel build warnings about variable defined but not used [-Wunused-const-variable=], like commit 487dc7bb6a0c ("clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used") does. Signed-off-by: Zong Li Suggested-by: Lee Jones Reviewed-by: Lee Jones Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/a3c7ec5c46c1d8be455d1c347db4855bb56cec53.1646388139.git.zong.li@sifive.com Signed-off-by: Stephen Boyd --- drivers/clk/sifive/Makefile | 2 +- drivers/clk/sifive/fu540-prci.c | 88 -------------------------- drivers/clk/sifive/fu540-prci.h | 91 +++++++++++++++++++++++++-- drivers/clk/sifive/fu740-prci.c | 133 --------------------------------------- drivers/clk/sifive/fu740-prci.h | 130 ++++++++++++++++++++++++++++++++++++-- drivers/clk/sifive/sifive-prci.c | 5 -- 6 files changed, 214 insertions(+), 235 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.c delete mode 100644 drivers/clk/sifive/fu740-prci.c (limited to 'drivers/clk') diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 7b06fc04e6b3..efdf01f1c8d5 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o +obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c deleted file mode 100644 index 672c782ad604..000000000000 --- a/drivers/clk/sifive/fu540-prci.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018-2022 SiFive, Inc. - * Copyright (C) 2018-2019 Wesley Terpstra - * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020-2022 Zong Li - * - * The FU540 PRCI implements clock and reset control for the SiFive - * FU540-C000 chip. This driver assumes that it has sole control - * over all PRCI resources. - * - * This driver is based on the PRCI driver written by Wesley Terpstra: - * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 - * - * References: - * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" - */ - -#include - -#include - -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { - .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_coreclksel_use_hfclk, - .disable_bypass = sifive_prci_coreclksel_use_corepll, -}; - -static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { - .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { - .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = { - .set_rate = sifive_prci_wrpll_set_rate, - .round_rate = sifive_prci_wrpll_round_rate, - .recalc_rate = sifive_prci_wrpll_recalc_rate, - .enable = sifive_prci_clock_enable, - .disable = sifive_prci_clock_disable, - .is_enabled = sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = { - .recalc_rate = sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { - .recalc_rate = sifive_prci_tlclksel_recalc_rate, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] = { - [FU540_PRCI_CLK_COREPLL] = { - .name = "corepll", - .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &sifive_fu540_prci_corepll_data, - }, - [FU540_PRCI_CLK_DDRPLL] = { - .name = "ddrpll", - .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd = &sifive_fu540_prci_ddrpll_data, - }, - [FU540_PRCI_CLK_GEMGXLPLL] = { - .name = "gemgxlpll", - .parent_name = "hfclk", - .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &sifive_fu540_prci_gemgxlpll_data, - }, - [FU540_PRCI_CLK_TLCLK] = { - .name = "tlclk", - .parent_name = "corepll", - .ops = &sifive_fu540_prci_tlclksel_clk_ops, - }, -}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h index c220677dc010..e0173324f3c5 100644 --- a/drivers/clk/sifive/fu540-prci.h +++ b/drivers/clk/sifive/fu540-prci.h @@ -1,16 +1,99 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 SiFive, Inc. - * Zong Li + * Copyright (C) 2018-2021 SiFive, Inc. + * Copyright (C) 2018-2019 Wesley Terpstra + * Copyright (C) 2018-2019 Paul Walmsley + * Copyright (C) 2020-2021 Zong Li + * + * The FU540 PRCI implements clock and reset control for the SiFive + * FU540-C000 chip. This driver assumes that it has sole control + * over all PRCI resources. + * + * This driver is based on the PRCI driver written by Wesley Terpstra: + * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 + * + * References: + * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ #ifndef __SIFIVE_CLK_FU540_PRCI_H #define __SIFIVE_CLK_FU540_PRCI_H + +#include + +#include + #include "sifive-prci.h" -#define NUM_CLOCK_FU540 4 +/* PRCI integration data for each WRPLL instance */ + +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_coreclksel_use_hfclk, + .disable_bypass = sifive_prci_coreclksel_use_corepll, +}; + +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = { + .set_rate = sifive_prci_wrpll_set_rate, + .round_rate = sifive_prci_wrpll_round_rate, + .recalc_rate = sifive_prci_wrpll_recalc_rate, + .enable = sifive_prci_clock_enable, + .disable = sifive_prci_clock_disable, + .is_enabled = sifive_clk_is_enabled, +}; + +static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = { + .recalc_rate = sifive_prci_wrpll_recalc_rate, +}; + +static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { + .recalc_rate = sifive_prci_tlclksel_recalc_rate, +}; + +/* List of clock controls provided by the PRCI */ +static struct __prci_clock __prci_init_clocks_fu540[] = { + [FU540_PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", + .ops = &sifive_fu540_prci_wrpll_clk_ops, + .pwd = &sifive_fu540_prci_corepll_data, + }, + [FU540_PRCI_CLK_DDRPLL] = { + .name = "ddrpll", + .parent_name = "hfclk", + .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, + .pwd = &sifive_fu540_prci_ddrpll_data, + }, + [FU540_PRCI_CLK_GEMGXLPLL] = { + .name = "gemgxlpll", + .parent_name = "hfclk", + .ops = &sifive_fu540_prci_wrpll_clk_ops, + .pwd = &sifive_fu540_prci_gemgxlpll_data, + }, + [FU540_PRCI_CLK_TLCLK] = { + .name = "tlclk", + .parent_name = "corepll", + .ops = &sifive_fu540_prci_tlclksel_clk_ops, + }, +}; -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; +static const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; #endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c deleted file mode 100644 index f27d1a42d946..000000000000 --- a/drivers/clk/sifive/fu740-prci.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2022 SiFive, Inc. - * Copyright (C) 2020-2022 Zong Li - */ - -#include - -#include - -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { - .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_coreclksel_use_hfclk, - .disable_bypass = sifive_prci_coreclksel_use_final_corepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { - .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { - .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { - .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_corepllsel_use_corepll, - .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { - .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, - .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, - .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { - .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, - .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = { - .set_rate = sifive_prci_wrpll_set_rate, - .round_rate = sifive_prci_wrpll_round_rate, - .recalc_rate = sifive_prci_wrpll_recalc_rate, - .enable = sifive_prci_clock_enable, - .disable = sifive_prci_clock_disable, - .is_enabled = sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = { - .recalc_rate = sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = { - .recalc_rate = sifive_prci_tlclksel_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { - .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { - .enable = sifive_prci_pcie_aux_clock_enable, - .disable = sifive_prci_pcie_aux_clock_disable, - .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { - [FU740_PRCI_CLK_COREPLL] = { - .name = "corepll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_corepll_data, - }, - [FU740_PRCI_CLK_DDRPLL] = { - .name = "ddrpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd = &sifive_fu740_prci_ddrpll_data, - }, - [FU740_PRCI_CLK_GEMGXLPLL] = { - .name = "gemgxlpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_gemgxlpll_data, - }, - [FU740_PRCI_CLK_DVFSCOREPLL] = { - .name = "dvfscorepll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_dvfscorepll_data, - }, - [FU740_PRCI_CLK_HFPCLKPLL] = { - .name = "hfpclkpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_hfpclkpll_data, - }, - [FU740_PRCI_CLK_CLTXPLL] = { - .name = "cltxpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_cltxpll_data, - }, - [FU740_PRCI_CLK_TLCLK] = { - .name = "tlclk", - .parent_name = "corepll", - .ops = &sifive_fu740_prci_tlclksel_clk_ops, - }, - [FU740_PRCI_CLK_PCLK] = { - .name = "pclk", - .parent_name = "hfpclkpll", - .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, - }, - [FU740_PRCI_CLK_PCIE_AUX] = { - .name = "pcie_aux", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_pcie_aux_clk_ops, - }, -}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h index 511a0bf7ba2b..f31cd30fc395 100644 --- a/drivers/clk/sifive/fu740-prci.h +++ b/drivers/clk/sifive/fu740-prci.h @@ -1,17 +1,139 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 SiFive, Inc. - * Zong Li + * Copyright (C) 2020-2021 SiFive, Inc. + * Copyright (C) 2020-2021 Zong Li */ #ifndef __SIFIVE_CLK_FU740_PRCI_H #define __SIFIVE_CLK_FU740_PRCI_H +#include + +#include + #include "sifive-prci.h" -#define NUM_CLOCK_FU740 9 +/* PRCI integration data for each WRPLL instance */ + +static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_coreclksel_use_hfclk, + .disable_bypass = sifive_prci_coreclksel_use_final_corepll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { + .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_corepllsel_use_corepll, + .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { + .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, + .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, + .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { + .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, + .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = { + .set_rate = sifive_prci_wrpll_set_rate, + .round_rate = sifive_prci_wrpll_round_rate, + .recalc_rate = sifive_prci_wrpll_recalc_rate, + .enable = sifive_prci_clock_enable, + .disable = sifive_prci_clock_disable, + .is_enabled = sifive_clk_is_enabled, +}; -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; +static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = { + .recalc_rate = sifive_prci_wrpll_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = { + .recalc_rate = sifive_prci_tlclksel_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { + .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { + .enable = sifive_prci_pcie_aux_clock_enable, + .disable = sifive_prci_pcie_aux_clock_disable, + .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, +}; + +/* List of clock controls provided by the PRCI */ +static struct __prci_clock __prci_init_clocks_fu740[] = { + [FU740_PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_corepll_data, + }, + [FU740_PRCI_CLK_DDRPLL] = { + .name = "ddrpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, + .pwd = &sifive_fu740_prci_ddrpll_data, + }, + [FU740_PRCI_CLK_GEMGXLPLL] = { + .name = "gemgxlpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_gemgxlpll_data, + }, + [FU740_PRCI_CLK_DVFSCOREPLL] = { + .name = "dvfscorepll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_dvfscorepll_data, + }, + [FU740_PRCI_CLK_HFPCLKPLL] = { + .name = "hfpclkpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_hfpclkpll_data, + }, + [FU740_PRCI_CLK_CLTXPLL] = { + .name = "cltxpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &sifive_fu740_prci_cltxpll_data, + }, + [FU740_PRCI_CLK_TLCLK] = { + .name = "tlclk", + .parent_name = "corepll", + .ops = &sifive_fu740_prci_tlclksel_clk_ops, + }, + [FU740_PRCI_CLK_PCLK] = { + .name = "pclk", + .parent_name = "hfpclkpll", + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, + }, + [FU740_PRCI_CLK_PCIE_AUX] = { + .name = "pcie_aux", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_pcie_aux_clk_ops, + }, +}; static const struct prci_clk_desc prci_clk_fu740 = { .clks = __prci_init_clocks_fu740, diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index 80a288c59e56..916d2fc28b9c 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -12,11 +12,6 @@ #include "fu540-prci.h" #include "fu740-prci.h" -static const struct prci_clk_desc prci_clk_fu540 = { - .clks = __prci_init_clocks_fu540, - .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), -}; - /* * Private functions */ -- cgit v1.2.3 From c5601e0720ce1a3ad895f94a5838530edde01ed3 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 16 Mar 2022 11:35:33 +0300 Subject: clk: visconti: prevent array overflow in visconti_clk_register_gates() This code was using -1 to represent that there was no reset function. Unfortunately, the -1 was stored in u8 so the if (clks[i].rs_id >= 0) condition was always true. This lead to an out of bounds access in visconti_clk_register_gates(). Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20220316083533.GA30941@kili Acked-by: Nobuhiro Iwamatsu Signed-off-by: Stephen Boyd --- drivers/clk/visconti/clkc-tmpv770x.c | 2 +- drivers/clk/visconti/clkc.c | 2 +- drivers/clk/visconti/clkc.h | 3 +++ 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/visconti/clkc-tmpv770x.c b/drivers/clk/visconti/clkc-tmpv770x.c index c2b2f41a85a4..6c753b2cb558 100644 --- a/drivers/clk/visconti/clkc-tmpv770x.c +++ b/drivers/clk/visconti/clkc-tmpv770x.c @@ -176,7 +176,7 @@ static const struct visconti_clk_gate_table clk_gate_tables[] = { { TMPV770X_CLK_WRCK, "wrck", clks_parent_data, ARRAY_SIZE(clks_parent_data), 0, 0x68, 0x168, 9, 32, - -1, }, /* No reset */ + NO_RESET, }, { TMPV770X_CLK_PICKMON, "pickmon", clks_parent_data, ARRAY_SIZE(clks_parent_data), 0, 0x10, 0x110, 8, 4, diff --git a/drivers/clk/visconti/clkc.c b/drivers/clk/visconti/clkc.c index 56a8a4ffebca..d0b193b5d0b3 100644 --- a/drivers/clk/visconti/clkc.c +++ b/drivers/clk/visconti/clkc.c @@ -147,7 +147,7 @@ int visconti_clk_register_gates(struct visconti_clk_provider *ctx, if (!dev_name) return -ENOMEM; - if (clks[i].rs_id >= 0) { + if (clks[i].rs_id != NO_RESET) { rson_offset = reset[clks[i].rs_id].rson_offset; rsoff_offset = reset[clks[i].rs_id].rsoff_offset; rs_idx = reset[clks[i].rs_id].rs_idx; diff --git a/drivers/clk/visconti/clkc.h b/drivers/clk/visconti/clkc.h index 09ed82ff64e4..8756a1ec42ef 100644 --- a/drivers/clk/visconti/clkc.h +++ b/drivers/clk/visconti/clkc.h @@ -73,4 +73,7 @@ int visconti_clk_register_gates(struct visconti_clk_provider *data, int num_gate, const struct visconti_reset_data *reset, spinlock_t *lock); + +#define NO_RESET 0xFF + #endif /* _VISCONTI_CLKC_H_ */ -- cgit v1.2.3 From 0c125f87a84097c182c481be7497af9f816e5db5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Feb 2022 05:07:22 +0100 Subject: clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() Add an API for a fixed factor clk that uses an index for the parent instead of a string name. This allows us to move drivers away from the string based method of describing parents and use the DT/firmware based method instead. Signed-off-by: Marek Vasut Cc: Michael Turquette Cc: Rob Herring Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220226040723.143705-2-marex@denx.de [sboyd@kernel.org: Expose a new API instead of internal function] Signed-off-by: Stephen Boyd --- drivers/clk/clk-fixed-factor.c | 22 ++++++++++++++++++++++ include/linux/clk-provider.h | 3 +++ 2 files changed, 25 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 4e4b6d367612..54942d758ee6 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -131,6 +131,28 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, return hw; } +/** + * devm_clk_hw_register_fixed_factor_index - Register a fixed factor clock with + * parent from DT index + * @dev: device that is registering this clock + * @name: name of this clock + * @index: index of phandle in @dev 'clocks' property + * @flags: fixed factor flags + * @mult: multiplier + * @div: divider + * + * Return: Pointer to fixed factor clk_hw structure that was registered or + * an error pointer. + */ +struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, + const char *name, unsigned int index, unsigned long flags, + unsigned int mult, unsigned int div) +{ + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, index, + flags, mult, div, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); + struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2faa6f7aa8a8..b7a7923f6bbb 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1003,6 +1003,9 @@ void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, + const char *name, unsigned int index, unsigned long flags, + unsigned int mult, unsigned int div); /** * struct clk_fractional_divider - adjustable fractional divider clock * -- cgit v1.2.3 From 892e0ddea1aa6f70b68cb2dd8e16bf271e20e72f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 26 Feb 2022 05:07:23 +0100 Subject: clk: rs9: Add Renesas 9-series PCIe clock generator driver Add driver for Renesas 9-series PCIe clock generators. This driver is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. The driver is capable of configuring per-chip spread spectrum mode and output amplitude, as well as per-output slew rate. Signed-off-by: Marek Vasut Cc: Michael Turquette Cc: Rob Herring Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220226040723.143705-3-marex@denx.de [sboyd@kernel.org: Use non-underscore API for fixed factor] Signed-off-by: Stephen Boyd --- drivers/clk/Kconfig | 9 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-renesas-pcie.c | 322 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 332 insertions(+) create mode 100644 drivers/clk/clk-renesas-pcie.c (limited to 'drivers/clk') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index ad4256d54361..fb390e7fa641 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -340,6 +340,15 @@ config COMMON_CLK_OXNAS help Support for the OXNAS SoC Family clocks. +config COMMON_CLK_RS9_PCIE + tristate "Clock driver for Renesas 9-series PCIe clock generators" + depends on I2C + depends on OF + select REGMAP_I2C + help + This driver supports the Renesas 9-series PCIe clock generator + models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ. + config COMMON_CLK_VC5 tristate "Clock driver for IDT VersaClock 5,6 devices" depends on I2C diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630472..cfa671325feb 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o +obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c new file mode 100644 index 000000000000..59d9cf0053eb --- /dev/null +++ b/drivers/clk/clk-renesas-pcie.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for Renesas 9-series PCIe clock generator driver + * + * The following series can be supported: + * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ + * Currently supported: + * - 9FGV0241 + * + * Copyright (C) 2022 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include + +#define RS9_REG_OE 0x0 +#define RS9_REG_OE_DIF_OE(n) BIT((n) + 1) +#define RS9_REG_SS 0x1 +#define RS9_REG_SS_AMP_0V6 0x0 +#define RS9_REG_SS_AMP_0V7 0x1 +#define RS9_REG_SS_AMP_0V8 0x2 +#define RS9_REG_SS_AMP_0V9 0x3 +#define RS9_REG_SS_AMP_MASK 0x3 +#define RS9_REG_SS_SSC_100 0 +#define RS9_REG_SS_SSC_M025 (1 << 3) +#define RS9_REG_SS_SSC_M050 (3 << 3) +#define RS9_REG_SS_SSC_MASK (3 << 3) +#define RS9_REG_SS_SSC_LOCK BIT(5) +#define RS9_REG_SR 0x2 +#define RS9_REG_SR_2V0_DIF(n) 0 +#define RS9_REG_SR_3V0_DIF(n) BIT((n) + 1) +#define RS9_REG_SR_DIF_MASK(n) BIT((n) + 1) +#define RS9_REG_REF 0x3 +#define RS9_REG_REF_OE BIT(4) +#define RS9_REG_REF_OD BIT(5) +#define RS9_REG_REF_SR_SLOWEST 0 +#define RS9_REG_REF_SR_SLOW (1 << 6) +#define RS9_REG_REF_SR_FAST (2 << 6) +#define RS9_REG_REF_SR_FASTER (3 << 6) +#define RS9_REG_VID 0x5 +#define RS9_REG_DID 0x6 +#define RS9_REG_BCP 0x7 + +/* Supported Renesas 9-series models. */ +enum rs9_model { + RENESAS_9FGV0241, +}; + +/* Structure to describe features of a particular 9-series model */ +struct rs9_chip_info { + const enum rs9_model model; + unsigned int num_clks; +}; + +struct rs9_driver_data { + struct i2c_client *client; + struct regmap *regmap; + const struct rs9_chip_info *chip_info; + struct clk *pin_xin; + struct clk_hw *clk_dif[2]; + u8 pll_amplitude; + u8 pll_ssc; + u8 clk_dif_sr; +}; + +/* + * Renesas 9-series i2c regmap + */ +static const struct regmap_range rs9_readable_ranges[] = { + regmap_reg_range(RS9_REG_OE, RS9_REG_REF), + regmap_reg_range(RS9_REG_VID, RS9_REG_BCP), +}; + +static const struct regmap_access_table rs9_readable_table = { + .yes_ranges = rs9_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges), +}; + +static const struct regmap_range rs9_writeable_ranges[] = { + regmap_reg_range(RS9_REG_OE, RS9_REG_REF), + regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP), +}; + +static const struct regmap_access_table rs9_writeable_table = { + .yes_ranges = rs9_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges), +}; + +static const struct regmap_config rs9_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_FLAT, + .max_register = 0x8, + .rd_table = &rs9_readable_table, + .wr_table = &rs9_writeable_table, +}; + +static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx) +{ + struct i2c_client *client = rs9->client; + unsigned char name[5] = "DIF0"; + struct device_node *np; + int ret; + u32 sr; + + /* Set defaults */ + rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); + rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); + + snprintf(name, 5, "DIF%d", idx); + np = of_get_child_by_name(client->dev.of_node, name); + if (!np) + return 0; + + /* Output clock slew rate */ + ret = of_property_read_u32(np, "renesas,slew-rate", &sr); + of_node_put(np); + if (!ret) { + if (sr == 2000000) { /* 2V/ns */ + rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); + rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx); + } else if (sr == 3000000) { /* 3V/ns (default) */ + rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); + rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); + } else + ret = dev_err_probe(&client->dev, -EINVAL, + "Invalid renesas,slew-rate value\n"); + } + + return ret; +} + +static int rs9_get_common_config(struct rs9_driver_data *rs9) +{ + struct i2c_client *client = rs9->client; + struct device_node *np = client->dev.of_node; + unsigned int amp, ssc; + int ret; + + /* Set defaults */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; + rs9->pll_ssc = RS9_REG_SS_SSC_100; + + /* Output clock amplitude */ + ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt", + &); + if (!ret) { + if (amp == 600000) /* 0.6V */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V6; + else if (amp == 700000) /* 0.7V (default) */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V7; + else if (amp == 800000) /* 0.8V */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V8; + else if (amp == 900000) /* 0.9V */ + rs9->pll_amplitude = RS9_REG_SS_AMP_0V9; + else + return dev_err_probe(&client->dev, -EINVAL, + "Invalid renesas,out-amplitude-microvolt value\n"); + } + + /* Output clock spread spectrum */ + ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); + if (!ret) { + if (ssc == 100000) /* 100% ... no spread (default) */ + rs9->pll_ssc = RS9_REG_SS_SSC_100; + else if (ssc == 99750) /* -0.25% ... down spread */ + rs9->pll_ssc = RS9_REG_SS_SSC_M025; + else if (ssc == 99500) /* -0.50% ... down spread */ + rs9->pll_ssc = RS9_REG_SS_SSC_M050; + else + return dev_err_probe(&client->dev, -EINVAL, + "Invalid renesas,out-spread-spectrum value\n"); + } + + return 0; +} + +static void rs9_update_config(struct rs9_driver_data *rs9) +{ + int i; + + /* If amplitude is non-default, update it. */ + if (rs9->pll_amplitude != RS9_REG_SS_AMP_0V7) { + regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK, + rs9->pll_amplitude); + } + + /* If SSC is non-default, update it. */ + if (rs9->pll_ssc != RS9_REG_SS_SSC_100) { + regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK, + rs9->pll_ssc); + } + + for (i = 0; i < rs9->chip_info->num_clks; i++) { + if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)) + continue; + + regmap_update_bits(rs9->regmap, RS9_REG_SR, RS9_REG_SR_3V0_DIF(i), + rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)); + } +} + +static struct clk_hw * +rs9_of_clk_get(struct of_phandle_args *clkspec, void *data) +{ + struct rs9_driver_data *rs9 = data; + unsigned int idx = clkspec->args[0]; + + return rs9->clk_dif[idx]; +} + +static int rs9_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + unsigned char name[5] = "DIF0"; + struct rs9_driver_data *rs9; + struct clk_hw *hw; + int i, ret; + + rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL); + if (!rs9) + return -ENOMEM; + + i2c_set_clientdata(client, rs9); + rs9->client = client; + rs9->chip_info = device_get_match_data(&client->dev); + if (!rs9->chip_info) + return -EINVAL; + + /* Fetch common configuration from DT (if specified) */ + ret = rs9_get_common_config(rs9); + if (ret) + return ret; + + /* Fetch DIFx output configuration from DT (if specified) */ + for (i = 0; i < rs9->chip_info->num_clks; i++) { + ret = rs9_get_output_config(rs9, i); + if (ret) + return ret; + } + + rs9->regmap = devm_regmap_init_i2c(client, &rs9_regmap_config); + if (IS_ERR(rs9->regmap)) + return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap), + "Failed to allocate register map\n"); + + /* Register clock */ + for (i = 0; i < rs9->chip_info->num_clks; i++) { + snprintf(name, 5, "DIF%d", i); + hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name, + 0, 0, 4, 1); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + rs9->clk_dif[i] = hw; + } + + ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9); + if (!ret) + rs9_update_config(rs9); + + return ret; +} + +static int __maybe_unused rs9_suspend(struct device *dev) +{ + struct rs9_driver_data *rs9 = dev_get_drvdata(dev); + + regcache_cache_only(rs9->regmap, true); + regcache_mark_dirty(rs9->regmap); + + return 0; +} + +static int __maybe_unused rs9_resume(struct device *dev) +{ + struct rs9_driver_data *rs9 = dev_get_drvdata(dev); + int ret; + + regcache_cache_only(rs9->regmap, false); + ret = regcache_sync(rs9->regmap); + if (ret) + dev_err(dev, "Failed to restore register map: %d\n", ret); + return ret; +} + +static const struct rs9_chip_info renesas_9fgv0241_info = { + .model = RENESAS_9FGV0241, + .num_clks = 2, +}; + +static const struct i2c_device_id rs9_id[] = { + { "9fgv0241", .driver_data = RENESAS_9FGV0241 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, rs9_id); + +static const struct of_device_id clk_rs9_of_match[] = { + { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rs9_of_match); + +static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume); + +static struct i2c_driver rs9_driver = { + .driver = { + .name = "clk-renesas-pcie-9series", + .pm = &rs9_pm_ops, + .of_match_table = clk_rs9_of_match, + }, + .probe = rs9_probe, + .id_table = rs9_id, +}; +module_i2c_driver(rs9_driver); + +MODULE_AUTHOR("Marek Vasut "); +MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 71021db1c532c2545ae53b9ee85b37b7154f51d4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:49:40 +0100 Subject: clk: qcom: gcc-msm8994: Fix gpll4 width The gpll4 postdiv is actually a div4, so make sure that Linux is aware of this. This fixes the following error messages: mmc1: Card appears overclocked; req 200000000 Hz, actual 343999999 Hz mmc1: Card appears overclocked; req 400000000 Hz, actual 687999999 Hz Fixes: aec89f78cf01 ("clk: qcom: Add support for msm8994 global clock controller") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20220319174940.341137-1-konrad.dybcio@somainline.org Tested-by: Petr Vorel Reviewed-by: Petr Vorel Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8994.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c index 71aa630fa4bd..bd027d5df8b4 100644 --- a/drivers/clk/qcom/gcc-msm8994.c +++ b/drivers/clk/qcom/gcc-msm8994.c @@ -77,6 +77,7 @@ static struct clk_alpha_pll gpll4_early = { static struct clk_alpha_pll_postdiv gpll4 = { .offset = 0x1dc0, + .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", -- cgit v1.2.3 From 5f7e2af00807f2117650e711a58b7f0e986ce1df Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Mar 2022 17:11:42 +0100 Subject: clk: Initialize orphan req_rate When registering a clock that doesn't have a recalc_rate implementation, and doesn't have its parent registered yet, we initialize the clk_core rate and 'req_rate' fields to 0. The rate field is later updated when the parent is registered in clk_core_reparent_orphans_nolock() using __clk_recalc_rates(), but the 'req_rate' field is never updated. This leads to an issue in clk_set_rate_range() and clk_put(), since those functions will call clk_set_rate() with the content of 'req_rate' to provide drivers with the opportunity to change the rate based on the new boundaries. In this case, we would call clk_set_rate() with a rate of 0, effectively enforcing the minimum allowed for this clock whenever we would call one of those two functions, even though the actual rate might be within range. Let's fix this by setting 'req_rate' in clk_core_reparent_orphans_nolock() with the rate field content just updated by the call to __clk_recalc_rates(). Fixes: 1c8e600440c7 ("clk: Add rate constraints to clocks") Reported-by: Dmitry Osipenko Tested-by: Dmitry Osipenko # T30 Nexus7 Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220325161144.1901695-2-maxime@cerno.tech [sboyd@kernel.org: Reword comment] Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 9bc8bf434b94..ad1595c13c9f 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3479,6 +3479,19 @@ static void clk_core_reparent_orphans_nolock(void) __clk_set_parent_after(orphan, parent, NULL); __clk_recalc_accuracies(orphan); __clk_recalc_rates(orphan, 0); + + /* + * __clk_init_parent() will set the initial req_rate to + * 0 if the clock doesn't have clk_ops::recalc_rate and + * is an orphan when it's registered. + * + * 'req_rate' is used by clk_set_rate_range() and + * clk_put() to trigger a clk_set_rate() call whenever + * the boundaries are modified. Let's make sure + * 'req_rate' is set to something non-zero so that + * clk_set_rate_range() doesn't drop the frequency. + */ + orphan->req_rate = orphan->rate; } } } -- cgit v1.2.3 From 481f541ced8fcf9af87bedf6f87c2023de22bf6e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Mar 2022 17:11:43 +0100 Subject: clk: test: Test clk_set_rate_range on orphan mux A bug recently affected the Tegra30 where calling clk_set_rate_range() on a clock would make it change its rate to the minimum. This was due to the clock in question being a mux that was orphan at registration, which lead to the clk_core req_rate being 0, and the clk_set_rate_range() function then calling clk_set_rate() with req_rate, effectively making that clock running at the minimum rate allowed, even though the initial rate was within that range. Make a test suite to create a mux initially orphan, and then make sure that if our clock rate was initially within a given range, then enforcing that range won't affect it. Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220325161144.1901695-3-maxime@cerno.tech Signed-off-by: Stephen Boyd --- drivers/clk/clk_test.c | 105 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) (limited to 'drivers/clk') diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 48f95d1784c8..6731a822f4e3 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -72,6 +72,19 @@ static int clk_dummy_set_rate(struct clk_hw *hw, return 0; } +static int clk_dummy_single_set_parent(struct clk_hw *hw, u8 index) +{ + if (index >= clk_hw_get_num_parents(hw)) + return -EINVAL; + + return 0; +} + +static u8 clk_dummy_single_get_parent(struct clk_hw *hw) +{ + return 0; +} + static const struct clk_ops clk_dummy_rate_ops = { .recalc_rate = clk_dummy_recalc_rate, .determine_rate = clk_dummy_determine_rate, @@ -90,6 +103,11 @@ static const struct clk_ops clk_dummy_minimize_rate_ops = { .set_rate = clk_dummy_set_rate, }; +static const struct clk_ops clk_dummy_single_parent_ops = { + .set_parent = clk_dummy_single_set_parent, + .get_parent = clk_dummy_single_get_parent, +}; + static int clk_test_init_with_ops(struct kunit *test, const struct clk_ops *ops) { struct clk_dummy_context *ctx; @@ -239,6 +257,92 @@ static struct kunit_suite clk_test_suite = { .test_cases = clk_test_cases, }; +struct clk_single_parent_ctx { + struct clk_dummy_context parent_ctx; + struct clk_hw hw; +}; + +static int clk_orphan_transparent_single_parent_mux_test_init(struct kunit *test) +{ + struct clk_single_parent_ctx *ctx; + struct clk_init_data init = { }; + const char * const parents[] = { "orphan_parent" }; + int ret; + + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv = ctx; + + init.name = "test_orphan_dummy_parent"; + init.ops = &clk_dummy_single_parent_ops; + init.parent_names = parents; + init.num_parents = ARRAY_SIZE(parents); + init.flags = CLK_SET_RATE_PARENT; + ctx->hw.init = &init; + + ret = clk_hw_register(NULL, &ctx->hw); + if (ret) + return ret; + + memset(&init, 0, sizeof(init)); + init.name = "orphan_parent"; + init.ops = &clk_dummy_rate_ops; + ctx->parent_ctx.hw.init = &init; + ctx->parent_ctx.rate = DUMMY_CLOCK_INIT_RATE; + + ret = clk_hw_register(NULL, &ctx->parent_ctx.hw); + if (ret) + return ret; + + return 0; +} + +static void clk_orphan_transparent_single_parent_mux_test_exit(struct kunit *test) +{ + struct clk_single_parent_ctx *ctx = test->priv; + + clk_hw_unregister(&ctx->hw); + clk_hw_unregister(&ctx->parent_ctx.hw); +} + +/* + * Test that a mux-only clock, with an initial rate within a range, + * will still have the same rate after the range has been enforced. + */ +static void clk_test_orphan_transparent_parent_mux_set_range(struct kunit *test) +{ + struct clk_single_parent_ctx *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + unsigned long rate, new_rate; + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(clk, + ctx->parent_ctx.rate - 1000, + ctx->parent_ctx.rate + 1000), + 0); + + new_rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, new_rate, 0); + KUNIT_EXPECT_EQ(test, rate, new_rate); +} + +static struct kunit_case clk_orphan_transparent_single_parent_mux_test_cases[] = { + KUNIT_CASE(clk_test_orphan_transparent_parent_mux_set_range), + {} +}; + +static struct kunit_suite clk_orphan_transparent_single_parent_test_suite = { + .name = "clk-orphan-transparent-single-parent-test", + .init = clk_orphan_transparent_single_parent_mux_test_init, + .exit = clk_orphan_transparent_single_parent_mux_test_exit, + .test_cases = clk_orphan_transparent_single_parent_mux_test_cases, +}; + /* * Test that clk_set_rate_range won't return an error for a valid range * and that it will make sure the rate of the clock is within the @@ -788,6 +892,7 @@ static struct kunit_suite clk_range_minimize_test_suite = { kunit_test_suites( &clk_test_suite, + &clk_orphan_transparent_single_parent_test_suite, &clk_range_test_suite, &clk_range_maximize_test_suite, &clk_range_minimize_test_suite -- cgit v1.2.3 From 7dabfa2bc4803eed83d6f22bd6f045495f40636b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 25 Mar 2022 17:11:44 +0100 Subject: clk: Drop the rate range on clk_put() When clk_put() is called we don't make another clk_set_rate() call to re-evaluate the rate boundaries. This is unlike clk_set_rate_range() that evaluates the rate again each time it is called. However, clk_put() is essentially equivalent to clk_set_rate_range() since after clk_put() completes the consumer's boundaries shouldn't be enforced anymore. Let's add a call to clk_set_rate_range() in clk_put() to make sure those rate boundaries are dropped and the clock provider drivers can react. Also add a few tests to make sure this case is covered. Fixes: c80ac50cbb37 ("clk: Always set the rate on clk_set_range_rate") Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20220325161144.1901695-4-maxime@cerno.tech [sboyd@kernel.org: Reword commit text] Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 42 ++++++++++++------- drivers/clk/clk_test.c | 108 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+), 14 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ad1595c13c9f..32a9eaf35c6b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2332,19 +2332,15 @@ int clk_set_rate_exclusive(struct clk *clk, unsigned long rate) } EXPORT_SYMBOL_GPL(clk_set_rate_exclusive); -/** - * clk_set_rate_range - set a rate range for a clock source - * @clk: clock source - * @min: desired minimum clock rate in Hz, inclusive - * @max: desired maximum clock rate in Hz, inclusive - * - * Returns success (0) or negative errno. - */ -int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) +static int clk_set_rate_range_nolock(struct clk *clk, + unsigned long min, + unsigned long max) { int ret = 0; unsigned long old_min, old_max, rate; + lockdep_assert_held(&prepare_lock); + if (!clk) return 0; @@ -2357,8 +2353,6 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) return -EINVAL; } - clk_prepare_lock(); - if (clk->exclusive_count) clk_core_rate_unprotect(clk->core); @@ -2402,6 +2396,28 @@ out: if (clk->exclusive_count) clk_core_rate_protect(clk->core); + return ret; +} + +/** + * clk_set_rate_range - set a rate range for a clock source + * @clk: clock source + * @min: desired minimum clock rate in Hz, inclusive + * @max: desired maximum clock rate in Hz, inclusive + * + * Return: 0 for success or negative errno on failure. + */ +int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) +{ + int ret; + + if (!clk) + return 0; + + clk_prepare_lock(); + + ret = clk_set_rate_range_nolock(clk, min, max); + clk_prepare_unlock(); return ret; @@ -4403,9 +4419,7 @@ void __clk_put(struct clk *clk) } hlist_del(&clk->clks_node); - if (clk->min_rate > clk->core->req_rate || - clk->max_rate < clk->core->req_rate) - clk_core_set_rate_nolock(clk->core, clk->core->req_rate); + clk_set_rate_range_nolock(clk, 0, ULONG_MAX); owner = clk->core->owner; kref_put(&clk->core->ref, __clk_release); diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 6731a822f4e3..fd2339cc5898 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -760,9 +760,65 @@ static void clk_range_test_multiple_set_range_rate_maximized(struct kunit *test) clk_put(user1); } +/* + * Test that if we have several subsequent calls to + * clk_set_rate_range(), across multiple users, the core will reevaluate + * whether a new rate is needed, including when a user drop its clock. + * + * With clk_dummy_maximize_rate_ops, this means that the rate will + * trail along the maximum as it evolves. + */ +static void clk_range_test_multiple_set_range_rate_put_maximized(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + struct clk *user1, *user2; + unsigned long rate; + + user1 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1); + + user2 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate(clk, DUMMY_CLOCK_RATE_2 + 1000), + 0); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user1, + 0, + DUMMY_CLOCK_RATE_2), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user2, + 0, + DUMMY_CLOCK_RATE_1), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + clk_put(user2); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + clk_put(user1); +} + static struct kunit_case clk_range_maximize_test_cases[] = { KUNIT_CASE(clk_range_test_set_range_rate_maximized), KUNIT_CASE(clk_range_test_multiple_set_range_rate_maximized), + KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_maximized), {} }; @@ -877,9 +933,61 @@ static void clk_range_test_multiple_set_range_rate_minimized(struct kunit *test) clk_put(user1); } +/* + * Test that if we have several subsequent calls to + * clk_set_rate_range(), across multiple users, the core will reevaluate + * whether a new rate is needed, including when a user drop its clock. + * + * With clk_dummy_minimize_rate_ops, this means that the rate will + * trail along the minimum as it evolves. + */ +static void clk_range_test_multiple_set_range_rate_put_minimized(struct kunit *test) +{ + struct clk_dummy_context *ctx = test->priv; + struct clk_hw *hw = &ctx->hw; + struct clk *clk = hw->clk; + struct clk *user1, *user2; + unsigned long rate; + + user1 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user1); + + user2 = clk_hw_get_clk(hw, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, user2); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user1, + DUMMY_CLOCK_RATE_1, + ULONG_MAX), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + KUNIT_ASSERT_EQ(test, + clk_set_rate_range(user2, + DUMMY_CLOCK_RATE_2, + ULONG_MAX), + 0); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_2); + + clk_put(user2); + + rate = clk_get_rate(clk); + KUNIT_ASSERT_GT(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, DUMMY_CLOCK_RATE_1); + + clk_put(user1); +} + static struct kunit_case clk_range_minimize_test_cases[] = { KUNIT_CASE(clk_range_test_set_range_rate_minimized), KUNIT_CASE(clk_range_test_multiple_set_range_rate_minimized), + KUNIT_CASE(clk_range_test_multiple_set_range_rate_put_minimized), {} }; -- cgit v1.2.3 From d583804c97c5ae7a7eba9c44982adcb106c2d160 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Tue, 22 Feb 2022 18:39:02 +0530 Subject: clk: zynq: trivial warning fix Fix the below warning WARNING: Missing a blank line after declarations + int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], Signed-off-by: Shubhrajyoti Datta Link: https://lore.kernel.org/r/20220222130903.17235-2-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd --- drivers/clk/zynq/clkc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 204b83d911b9..434511dcf5cb 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np) /* Peripheral clocks */ for (i = fclk0; i <= fclk3; i++) { int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), periph_parents, enable); -- cgit v1.2.3 From a6aa462c3efc144808b0cf8a0fe993d4fe2c079a Mon Sep 17 00:00:00 2001 From: Shubhrajyoti Datta Date: Tue, 22 Feb 2022 18:39:03 +0530 Subject: clk: zynq: Update the parameters to zynq_clk_register_periph_clk In case there are only one gate or the two_gate is 0 the clk1 clock passed is not used. We are passing 0 which is arm_pll. Pass a invalid clock instead. Signed-off-by: Shubhrajyoti Datta Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd --- drivers/clk/zynq/clkc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 434511dcf5cb..7bdeaff2bfd6 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -355,14 +355,14 @@ static void __init zynq_clk_setup(struct device_node *np) periph_parents, enable); } - zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, - SLCR_LQSPI_CLK_CTRL, periph_parents, 0); + zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL, + SLCR_LQSPI_CLK_CTRL, periph_parents, 0); - zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, - SLCR_SMC_CLK_CTRL, periph_parents, 0); + zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL, + SLCR_SMC_CLK_CTRL, periph_parents, 0); - zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, - SLCR_PCAP_CLK_CTRL, periph_parents, 0); + zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL, + SLCR_PCAP_CLK_CTRL, periph_parents, 0); zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, -- cgit v1.2.3