From 7149c1becddf49022fe0aad2fa395377cd8f753e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 24 Mar 2017 16:33:07 +0800 Subject: clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code We ignore the d1 and d2 dividers in the audio PLL, and force them to 1 (register value 0) at probe time. However the comment preceding the audio PLL definition says we enforce the default value, which is not the same. Fix the preceding comment to match what we do in code. Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c index 51f6d495de5b..8936ef87652c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c +++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c @@ -70,8 +70,7 @@ static struct ccu_mult pll_c1cpux_clk = { /* * The Audio PLL has d1, d2 dividers in addition to the usual N, M * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz - * and 24.576 MHz, ignore them for now. Enforce the default for them, - * which is d1 = 0, d2 = 1. + * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0. */ #define SUN9I_A80_PLL_AUDIO_REG 0x008 -- cgit v1.2.3