From 9ea49fff04917255ad3dbc2231587a8e8ec0a389 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Dec 2012 16:42:29 +0000 Subject: clk: ux500: Ensure the FMSC clock is obtainable The FMSC clock is traditionally used for NAND flash devices when used on the ux500 series platforms. This patch makes it searchable during a clock-name search. Acked-by: Mike Turquette Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/clk/ux500/u8500_clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk') diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 6b889a0e90b3..a60180228628 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -324,7 +324,7 @@ void u8500_clk_init(void) clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0); - clk_register_clkdev(clk, NULL, "fsmc"); + clk_register_clkdev(clk, "fsmc", NULL); clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, BIT(1), 0); -- cgit v1.2.3 From 1e6b6801405ec578c8607e9dabcc4e946ea64f4c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 19 Dec 2012 16:48:02 +0000 Subject: clk: ux500: Provide an alias for the SMSC911x Ethernet chip In the case of some of the ux500 platforms, an Ethernet chip is placed on an extended bus which is traditionally used as a NAND flash chip placeholder. The p3_pclk0 clock is used to control it, so we are required to provide and easy way to access it from the SMSC911x driver. We do this using an alias provided by this patch. Acked-by: Mike Turquette Acked-by: Ulf Hansson Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/clk/ux500/u8500_clk.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk') diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index a60180228628..9d9add1e816d 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -325,6 +325,7 @@ void u8500_clk_init(void) clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0); clk_register_clkdev(clk, "fsmc", NULL); + clk_register_clkdev(clk, NULL, "smsc911x"); clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, BIT(1), 0); -- cgit v1.2.3 From bf161d2163f7b8bf4823829dbc1a14111760187e Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Fri, 8 Feb 2013 14:44:09 +0200 Subject: clk: tegra: No 7.1 super clk dividers on Tegra20 Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver Signed-off-by: Stephen Warren --- drivers/clk/tegra/clk-tegra20.c | 36 ++---------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 143ce1f899ad..fa3173e3b331 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -711,8 +711,8 @@ static void tegra20_pll_init(void) } static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", - "pll_p_cclk", "pll_p_out4_cclk", - "pll_p_out3_cclk", "clk_d", "pll_x" }; + "pll_p", "pll_p_out4", + "pll_p_out3", "clk_d", "pll_x" }; static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", "pll_p_out3", "pll_p_out2", "clk_d", "clk_32k", "pll_m_out1" }; @@ -721,38 +721,6 @@ static void tegra20_super_clk_init(void) { struct clk *clk; - /* - * DIV_U71 dividers for CCLK, these dividers are used only - * if parent clock is fixed rate. - */ - - /* - * Clock input to cclk divided from pll_p using - * U71 divider of cclk. - */ - clk = tegra_clk_register_divider("pll_p_cclk", "pll_p", - clk_base + SUPER_CCLK_DIVIDER, 0, - TEGRA_DIVIDER_INT, 16, 8, 1, NULL); - clk_register_clkdev(clk, "pll_p_cclk", NULL); - - /* - * Clock input to cclk divided from pll_p_out3 using - * U71 divider of cclk. - */ - clk = tegra_clk_register_divider("pll_p_out3_cclk", "pll_p_out3", - clk_base + SUPER_CCLK_DIVIDER, 0, - TEGRA_DIVIDER_INT, 16, 8, 1, NULL); - clk_register_clkdev(clk, "pll_p_out3_cclk", NULL); - - /* - * Clock input to cclk divided from pll_p_out4 using - * U71 divider of cclk. - */ - clk = tegra_clk_register_divider("pll_p_out4_cclk", "pll_p_out4", - clk_base + SUPER_CCLK_DIVIDER, 0, - TEGRA_DIVIDER_INT, 16, 8, 1, NULL); - clk_register_clkdev(clk, "pll_p_out4_cclk", NULL); - /* CCLK */ clk = tegra_clk_register_super_mux("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, -- cgit v1.2.3