From 08441a966219aee513cf802ca8de170c6655c61a Mon Sep 17 00:00:00 2001 From: Robert Yang Date: Tue, 25 Sep 2018 17:49:40 -0400 Subject: clk: tegra: Return the exact clock rate from clk_round_rate The current behavior is that clk_round_rate would return the same clock rate passed to it for valid PLL configurations. This change will return the exact rate the PLL will provide in accordance with clk API. Signed-off-by: Robert Yang Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Stephen Boyd --- drivers/clk/tegra/clk-pll.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 830d1c87fa7c..b50b7460014b 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -590,12 +590,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, cfg->n = cfg->output_rate / cfreq; cfg->cpcon = OUT_OF_TABLE_CPCON; - if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || - (1 << p_div) > divp_max(pll) - || cfg->output_rate > pll->params->vco_max) { + if (cfg->m == 0 || cfg->m > divm_max(pll) || + cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || + cfg->output_rate > pll->params->vco_max) { return -EINVAL; } + cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); cfg->output_rate >>= p_div; if (pll->params->pdiv_tohw) { -- cgit v1.2.3