From a89bd29a53d99f6106f5dca386c174a84abceb04 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 26 Jan 2021 12:45:26 +0000 Subject: clk: tegra: clk-tegra30: Remove unused variable 'reg' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/clk/tegra/clk-tegra30.c: In function ‘tegra30_enable_cpu_clock’: drivers/clk/tegra/clk-tegra30.c:1107:15: warning: variable ‘reg’ set but not used [-Wunused-but-set-variable] Cc: Peter De Schrijver Cc: Prashant Gaikwad Cc: Michael Turquette Cc: Stephen Boyd Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-clk@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20210126124540.3320214-8-lee.jones@linaro.org Signed-off-by: Stephen Boyd --- drivers/clk/tegra/clk-tegra30.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/clk/tegra') diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 37244a7e68c2..f72882f433ad 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1104,12 +1104,9 @@ static void tegra30_cpu_out_of_reset(u32 cpu) static void tegra30_enable_cpu_clock(u32 cpu) { - unsigned int reg; - writel(CPU_CLOCK(cpu), clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); - reg = readl(clk_base + - TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); + readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); } static void tegra30_disable_cpu_clock(u32 cpu) -- cgit v1.2.3 From b565eb81276a975bd2d9d28755df1468ef7854e8 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 26 Jan 2021 12:45:28 +0000 Subject: clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param Fixes the following W=1 kernel build warning(s): drivers/clk/tegra/cvb.c:106: warning: Function parameter or member 'align' not described in 'tegra_cvb_add_opp_table' Cc: Peter De Schrijver Cc: Prashant Gaikwad Cc: Michael Turquette Cc: Stephen Boyd Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-clk@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20210126124540.3320214-10-lee.jones@linaro.org Signed-off-by: Stephen Boyd --- drivers/clk/tegra/cvb.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/tegra') diff --git a/drivers/clk/tegra/cvb.c b/drivers/clk/tegra/cvb.c index 21115c4e5d3a..a7fdc7622913 100644 --- a/drivers/clk/tegra/cvb.c +++ b/drivers/clk/tegra/cvb.c @@ -86,6 +86,7 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table, * @dev: the struct device * for which the OPP table is built * @tables: array of CVB tables * @count: size of the previously mentioned array + * @align: parameters of the regulator step and offset * @process_id: process id of the HW module * @speedo_id: speedo id of the HW module * @speedo_value: speedo value of the HW module -- cgit v1.2.3