From 98c4b3661b5aee0e583d17d6304f6489c0f41155 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 20 Apr 2015 15:05:33 +0200 Subject: clk: tegra: Add dpaux1 clock This clock is of the same type as dpaux and is added to feed into the second DPAUX block used in conjunction with SOR1. Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-id.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/tegra/clk-id.h') diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index 62ea38187b71..fe6c6afcfa60 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -71,6 +71,7 @@ enum clk_id { tegra_clk_disp2_8, tegra_clk_dp2, tegra_clk_dpaux, + tegra_clk_dpaux1, tegra_clk_dsialp, tegra_clk_dsia_mux, tegra_clk_dsiblp, -- cgit v1.2.3