From 14d87cda8dc6d35b2a6cbbc1e1a5f6df4d9645ae Mon Sep 17 00:00:00 2001 From: Rahul Sharma Date: Thu, 29 Aug 2013 11:07:07 +0530 Subject: clk/exynos5420: fix the order of parents of hdmi mux Listing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10. Signed-off-by: Rahul Sharma Acked-by: Tomasz Figa Signed-off-by: Mike Turquette --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clk/samsung') diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 4e0c13e88569..522c033f5257 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -286,7 +286,7 @@ PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; -PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" }; +PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; -- cgit v1.2.3