From 787fe096fe42829f3091888835562ffce4d23bff Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Mon, 25 Mar 2019 17:35:55 +0100 Subject: clk: renesas: r8a77990: Add Z2 clock Adds support for R-Car E3 (r8a77990) Z2 clock. Signed-off-by: Takeshi Kihara [simon: reworked changelog; rebased] Signed-off-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/renesas') diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 9a278c75c918..99f602cb30a5 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), -- cgit v1.2.3