From e6988f2f53ef0a686909702358e21ee0c62bfbca Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: 5772: Replace private irq flow handler

That handler lacks the minimal checks for action being zero etc. Keep
the weird flow - ack before handling - intact and call into
handle_simple_irq which does the right thing.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
LKML-Reference: <20110202212552.413849952@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5272/intc.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
index 3cf681c177aa..2833909abfe8 100644
--- a/arch/m68knommu/platform/5272/intc.c
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -137,11 +137,8 @@ static int intc_irq_set_type(unsigned int irq, unsigned int type)
  */
 static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
 {
-	kstat_incr_irqs_this_cpu(irq, desc);
-	desc->status |= IRQ_INPROGRESS;
 	desc->chip->ack(irq);
-	handle_IRQ_event(irq, desc->action);
-	desc->status &= ~IRQ_INPROGRESS;
+	handle_simple_irq(irq, desc);
 }
 
 static struct irq_chip intc_irq_chip = {
-- 
cgit v1.2.3


From c2ff7c716a609dcc3b7f899a9052a6f6a93645b5 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Convert coldfire intc irq_chip to new

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/coldfire/intc.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index 60d2fcbe182b..d648081a63f6 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -111,28 +111,28 @@ void mcf_autovector(int irq)
 #endif
 }
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_mask(struct irq_data *d)
 {
-	if (mcf_irq2imr[irq])
-		mcf_setimr(mcf_irq2imr[irq]);
+	if (mcf_irq2imr[d->irq])
+		mcf_setimr(mcf_irq2imr[d->irq]);
 }
 
-static void intc_irq_unmask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *d)
 {
-	if (mcf_irq2imr[irq])
-		mcf_clrimr(mcf_irq2imr[irq]);
+	if (mcf_irq2imr[d->irq])
+		mcf_clrimr(mcf_irq2imr[d->irq]);
 }
 
-static int intc_irq_set_type(unsigned int irq, unsigned int type)
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
 {
 	return 0;
 }
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
-	.mask		= intc_irq_mask,
-	.unmask		= intc_irq_unmask,
-	.set_type	= intc_irq_set_type,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+	.irq_set_type	= intc_irq_set_type,
 };
 
 void __init init_IRQ(void)
-- 
cgit v1.2.3


From 0bc0f3aa1498e7ec0bb54f32b839e82319cb5fc1 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Convert coldfire intc-2 irq_chip to new

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/coldfire/intc-2.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 85daa2b3001a..71e07fb69302 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -43,8 +43,10 @@ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
 #define NR_VECS	64
 #endif
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_mask(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
 		unsigned long imraddr;
 		u32 val, imrbit;
@@ -64,8 +66,10 @@ static void intc_irq_mask(unsigned int irq)
 	}
 }
 
-static void intc_irq_unmask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
 		unsigned long intaddr, imraddr, icraddr;
 		u32 val, imrbit;
@@ -93,16 +97,16 @@ static void intc_irq_unmask(unsigned int irq)
 	}
 }
 
-static int intc_irq_set_type(unsigned int irq, unsigned int type)
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
 {
 	return 0;
 }
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
-	.mask		= intc_irq_mask,
-	.unmask		= intc_irq_unmask,
-	.set_type	= intc_irq_set_type,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+	.irq_set_type	= intc_irq_set_type,
 };
 
 void __init init_IRQ(void)
-- 
cgit v1.2.3


From f80c353ce8670b1ef336bc1dd74429763cbd7358 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Convert coldfire intc-simr irq_chip to new

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/coldfire/intc-simr.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index bb7048636140..69a3b679730b 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -20,8 +20,10 @@
 #include <asm/mcfsim.h>
 #include <asm/traps.h>
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_mask(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	if (irq >= MCFINT_VECBASE) {
 		if (irq < MCFINT_VECBASE + 64)
 			__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
@@ -30,8 +32,10 @@ static void intc_irq_mask(unsigned int irq)
 	}
 }
 
-static void intc_irq_unmask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	if (irq >= MCFINT_VECBASE) {
 		if (irq < MCFINT_VECBASE + 64)
 			__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
@@ -40,8 +44,10 @@ static void intc_irq_unmask(unsigned int irq)
 	}
 }
 
-static int intc_irq_set_type(unsigned int irq, unsigned int type)
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
 {
+	unsigned int irq = d->irq;
+
 	if (irq >= MCFINT_VECBASE) {
 		if (irq < MCFINT_VECBASE + 64)
 			__raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
@@ -53,9 +59,9 @@ static int intc_irq_set_type(unsigned int irq, unsigned int type)
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
-	.mask		= intc_irq_mask,
-	.unmask		= intc_irq_unmask,
-	.set_type	= intc_irq_set_type,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+	.irq_set_type	= intc_irq_set_type,
 };
 
 void __init init_IRQ(void)
-- 
cgit v1.2.3


From 39a17940abc4d069cbb33865e967dcc7ef1bf452 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Convert 68328 ints irq_chip to new functions

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/68328/ints.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index 2a3af193ccd3..e5631831a200 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -135,20 +135,20 @@ void process_int(int vec, struct pt_regs *fp)
 	}
 }
 
-static void intc_irq_unmask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *d)
 {
-	IMR &= ~(1<<irq);
+	IMR &= ~(1 << d->irq);
 }
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_mask(struct irq_data *d)
 {
-	IMR |= (1<<irq);
+	IMR |= (1 << d->irq);
 }
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "M68K-INTC",
-	.mask		= intc_irq_mask,
-	.unmask		= intc_irq_unmask,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
 };
 
 /*
-- 
cgit v1.2.3


From be497ddfd0d8a0aa3a84c41bb84bf10d2cb7cb7d Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Convert 68360 ints irq_chip to new functions

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/68360/ints.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c
index a29041c1a8a0..8de3feb568c6 100644
--- a/arch/m68knommu/platform/68360/ints.c
+++ b/arch/m68knommu/platform/68360/ints.c
@@ -37,26 +37,26 @@ extern void *_ramvec[];
 /* The number of spurious interrupts */
 volatile unsigned int num_spurious;
 
-static void intc_irq_unmask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *d)
 {
-	pquicc->intr_cimr |= (1 << irq);
+	pquicc->intr_cimr |= (1 << d->irq);
 }
 
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_mask(struct irq_data *d)
 {
-	pquicc->intr_cimr &= ~(1 << irq);
+	pquicc->intr_cimr &= ~(1 << d->irq);
 }
 
-static void intc_irq_ack(unsigned int irq)
+static void intc_irq_ack(struct irq_data *d)
 {
-	pquicc->intr_cisr = (1 << irq);
+	pquicc->intr_cisr = (1 << d->irq);
 }
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "M68K-INTC",
-	.mask		= intc_irq_mask,
-	.unmask		= intc_irq_unmask,
-	.ack		= intc_irq_ack,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+	.irq_ack	= intc_irq_ack,
 };
 
 /*
-- 
cgit v1.2.3


From 2730158ab2dd5c5df863da8135c07bb10acac60f Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:28 +0000
Subject: m68knommu: Convert 5272 intc irq_chip to new functions

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5272/intc.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
index 2833909abfe8..969ff0a467c6 100644
--- a/arch/m68knommu/platform/5272/intc.c
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -78,8 +78,10 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
  * an interrupt on this irq (for the external irqs). So this mask function
  * is also an ack_mask function.
  */
-static void intc_irq_mask(unsigned int irq)
+static void intc_irq_mask(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
 		u32 v;
 		irq -= MCFINT_VECBASE;
@@ -88,8 +90,10 @@ static void intc_irq_mask(unsigned int irq)
 	}
 }
 
-static void intc_irq_unmask(unsigned int irq)
+static void intc_irq_unmask(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
 		u32 v;
 		irq -= MCFINT_VECBASE;
@@ -98,8 +102,10 @@ static void intc_irq_unmask(unsigned int irq)
 	}
 }
 
-static void intc_irq_ack(unsigned int irq)
+static void intc_irq_ack(struct irq_data *d)
 {
+	unsigned int irq = d->irq;
+
 	/* Only external interrupts are acked */
 	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
 		irq -= MCFINT_VECBASE;
@@ -113,8 +119,10 @@ static void intc_irq_ack(unsigned int irq)
 	}
 }
 
-static int intc_irq_set_type(unsigned int irq, unsigned int type)
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
 {
+	unsigned int irq = d->irq;
+
 	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
 		irq -= MCFINT_VECBASE;
 		if (intc_irqmap[irq].ack) {
@@ -137,17 +145,17 @@ static int intc_irq_set_type(unsigned int irq, unsigned int type)
  */
 static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
 {
-	desc->chip->ack(irq);
+	get_irq_desc_chip(desc)->irq_ack(&desc->irq_data);
 	handle_simple_irq(irq, desc);
 }
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
-	.mask		= intc_irq_mask,
-	.unmask		= intc_irq_unmask,
-	.mask_ack	= intc_irq_mask,
-	.ack		= intc_irq_ack,
-	.set_type	= intc_irq_set_type,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+	.irq_mask_ack	= intc_irq_mask,
+	.irq_ack	= intc_irq_ack,
+	.irq_set_type	= intc_irq_set_type,
 };
 
 void __init init_IRQ(void)
-- 
cgit v1.2.3


From e474563ebac1ece056024e2395673e6df04f6a7c Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Convert 5249 intc irq_chip to new functions

/me idly wonders what sets the handlers for this chip.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5249/intc2.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c
index c5151f846591..8f4b63e17366 100644
--- a/arch/m68knommu/platform/5249/intc2.c
+++ b/arch/m68knommu/platform/5249/intc2.c
@@ -17,32 +17,32 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 
-static void intc2_irq_gpio_mask(unsigned int irq)
+static void intc2_irq_gpio_mask(struct irq_data *d)
 {
 	u32 imr;
 	imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
-	imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0));
+	imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
 	writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
 }
 
-static void intc2_irq_gpio_unmask(unsigned int irq)
+static void intc2_irq_gpio_unmask(struct irq_data *d)
 {
 	u32 imr;
 	imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
-	imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0));
+	imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
 	writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
 }
 
-static void intc2_irq_gpio_ack(unsigned int irq)
+static void intc2_irq_gpio_ack(struct irq_data *d)
 {
-	writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
+	writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
 }
 
 static struct irq_chip intc2_irq_gpio_chip = {
 	.name		= "CF-INTC2",
-	.mask		= intc2_irq_gpio_mask,
-	.unmask		= intc2_irq_gpio_unmask,
-	.ack		= intc2_irq_gpio_ack,
+	.irq_mask	= intc2_irq_gpio_mask,
+	.irq_unmask	= intc2_irq_gpio_unmask,
+	.irq_ack	= intc2_irq_gpio_ack,
 };
 
 static int __init mcf_intc2_init(void)
@@ -51,7 +51,7 @@ static int __init mcf_intc2_init(void)
 
 	/* GPIO interrupt sources */
 	for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
-		irq_desc[irq].chip = &intc2_irq_gpio_chip;
+		set_irq_chip(irq, &intc2_irq_gpio_chip);
 		set_irq_handler(irq, handle_edge_irq);
 	}
 
-- 
cgit v1.2.3


From 5a7d29805ec26cda22904b4503bec010f5724f58 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Use proper irq_desc accessors in

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/kernel/irq.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c
index c9cac36d4422..c7dd48f37bee 100644
--- a/arch/m68knommu/kernel/irq.c
+++ b/arch/m68knommu/kernel/irq.c
@@ -38,11 +38,13 @@ int show_interrupts(struct seq_file *p, void *v)
 		seq_puts(p, "           CPU0\n");
 
 	if (irq < NR_IRQS) {
-		ap = irq_desc[irq].action;
+		struct irq_desc *desc = irq_to_desc(irq);
+
+		ap = desc->action;
 		if (ap) {
 			seq_printf(p, "%3d: ", irq);
 			seq_printf(p, "%10u ", kstat_irqs(irq));
-			seq_printf(p, "%14s  ", irq_desc[irq].chip->name);
+			seq_printf(p, "%14s  ", get_irq_desc_chip(desc)->name);
 
 			seq_printf(p, "%s", ap->name);
 			for (ap = ap->next; ap; ap = ap->next)
-- 
cgit v1.2.3


From d3ff2c22a5e5d0bb485f4474b67e0a0f2c426c65 Mon Sep 17 00:00:00 2001
From: Thomas Gleixner <tglx@linutronix.de>
Date: Sun, 6 Feb 2011 23:39:14 +0000
Subject: m68knommu: Select GENERIC_HARDIRQS_NO_DEPRECATED

All chips converted and proper accessor functions used.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'arch')

diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 8b9dacaa0f6e..04c7d348fbe7 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -3,6 +3,7 @@ config M68K
 	default y
 	select HAVE_IDE
 	select HAVE_GENERIC_HARDIRQS
+	select GENERIC_HARDIRQS_NO_DEPRECATED
 
 config MMU
 	bool
-- 
cgit v1.2.3


From f2ba710d17ae221e21a7cccddbbf5257fd93e9fa Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sat, 5 Mar 2011 21:43:50 +1000
Subject: m68knommu: move ColdFire 5249 MBAR2 definition

The MBAR2 register is only used on the ColdFire 5249 part, so move its
definition out of the common coldfire.h and into the 5249 support header.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h | 1 -
 arch/m68k/include/asm/m5249sim.h | 5 +++++
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 213028cbe110..d70cf0f1c40a 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -31,7 +31,6 @@
  *	This is generally setup by the boards start up code.
  */
 #define	MCF_MBAR	0x10000000
-#define	MCF_MBAR2	0x80000000
 #if defined(CONFIG_M54xx)
 #define	MCF_IPSBAR	MCF_MBAR
 #elif defined(CONFIG_M520x)
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 4908b118f2fd..6698b0581040 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -16,6 +16,11 @@
 
 #include <asm/m52xxacr.h>
 
+/*
+ *	The 5249 has a second MBAR region, define its address.
+ */
+#define	MCF_MBAR2		0x80000000
+
 /*
  *	Define the 5249 SIM register set addresses.
  */
-- 
cgit v1.2.3


From 254eef7464f0704290af4b91021f512eb4c98d59 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sat, 5 Mar 2011 22:17:17 +1000
Subject: m68knommu: remove kludge seting of MCF_IPSBAR for ColdFire 54xx

The ColdFire 54xx family shares the same interrupt controller used
on the 523x, 527x and 528x ColdFire parts, but it isn't offset
relative to the IPSBAR register. The 54xx doesn't have an IPSBAR
register.

By including the base address of the peripheral registers in the register
definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid
having to define a fake IPSBAR for the 54xx. And this makes the register
address definitions of these more consistent, the majority of the other
register address defines include the peripheral base address already.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h          |  4 +---
 arch/m68k/include/asm/m523xsim.h          |  5 +++--
 arch/m68k/include/asm/m527xsim.h          |  5 +++--
 arch/m68k/include/asm/m528xsim.h          |  5 +++--
 arch/m68k/include/asm/m54xxsim.h          |  3 ++-
 arch/m68knommu/platform/coldfire/intc-2.c | 14 ++++++--------
 6 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index d70cf0f1c40a..91676454731b 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -31,9 +31,7 @@
  *	This is generally setup by the boards start up code.
  */
 #define	MCF_MBAR	0x10000000
-#if defined(CONFIG_M54xx)
-#define	MCF_IPSBAR	MCF_MBAR
-#elif defined(CONFIG_M520x)
+#if defined(CONFIG_M520x)
 #define	MCF_IPSBAR	0xFC000000
 #else
 #define	MCF_IPSBAR	0x40000000
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 4ad7a00257a8..9701ed34d234 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -19,8 +19,9 @@
 /*
  *	Define the 523x SIM register set addresses.
  */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
+#define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
+#define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 0 */
+
 #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
 #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
 #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index e8042e8bc003..3712f611bd5e 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -19,8 +19,9 @@
 /*
  *	Define the 5270/5271 SIM register set addresses.
  */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 1 */
+#define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
+#define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 1 */
+
 #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
 #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
 #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a6d2f4d9aaa0..a918545f6a5a 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -19,8 +19,9 @@
 /*
  *	Define the 5280/5282 SIM register set addresses.
  */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
+#define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
+#define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 0 */
+
 #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
 #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
 #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 462ae5328441..cc5d94d215b4 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -15,7 +15,8 @@
 /*
  *      Interrupt Controller Registers
  */
-#define MCFICM_INTC0		0x0700		/* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0		(MCF_MBAR + 0x700) 	/* Base for Interrupt Ctrl 0 */
+
 #define MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
 #define MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
 #define MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 71e07fb69302..ec869c8e8890 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -52,11 +52,10 @@ static void intc_irq_mask(struct irq_data *d)
 		u32 val, imrbit;
 
 		irq -= MCFINT_VECBASE;
-		imraddr = MCF_IPSBAR;
 #ifdef MCFICM_INTC1
-		imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+		imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
 #else
-		imraddr += MCFICM_INTC0;
+		imraddr = MCFICM_INTC0;
 #endif
 		imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
 		imrbit = 0x1 << (irq & 0x1f);
@@ -75,11 +74,10 @@ static void intc_irq_unmask(struct irq_data *d)
 		u32 val, imrbit;
 
 		irq -= MCFINT_VECBASE;
-		intaddr = MCF_IPSBAR;
 #ifdef MCFICM_INTC1
-		intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+		intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
 #else
-		intaddr += MCFICM_INTC0;
+		intaddr = MCFICM_INTC0;
 #endif
 		imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
 		icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
@@ -116,9 +114,9 @@ void __init init_IRQ(void)
 	init_vectors();
 
 	/* Mask all interrupt sources */
-	__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
+	__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
 #ifdef MCFICM_INTC1
-	__raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
+	__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
 #endif
 
 	for (irq = 0; (irq < NR_IRQS); irq++) {
-- 
cgit v1.2.3


From cdfc243e7df1b3abba2c6aa35eba89f59b46219e Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sat, 5 Mar 2011 22:48:52 +1000
Subject: m68knommu: remove bogus definition of MBAR for ColdFire 532x family

Remove the bogus definition of the MBAR register for the ColdFire 532x
family. It doesn't have an MBAR register, its peripheral registers are
at fixed addresses and are not relative to a settable base.

All the code that relyed on this definition existing has been cleaned
up. The register address definitions now include the base as required.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 91676454731b..8daea2cf202e 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -41,9 +41,6 @@
     defined(CONFIG_M520x)
 #undef MCF_MBAR
 #define	MCF_MBAR	MCF_IPSBAR
-#elif defined(CONFIG_M532x)
-#undef MCF_MBAR
-#define MCF_MBAR	0x00000000
 #endif
 
 /****************************************************************************/
-- 
cgit v1.2.3


From f317c71a2f3dcdae26055e6dd390d06c5efe5795 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sat, 5 Mar 2011 23:32:35 +1000
Subject: m68knommu: move ColdFire PIT timer base addresses

The PIT hardware timer module used in some ColdFire CPU's is not always
addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and
5208 have fixed peripheral addresses. So lets not define the register
addresses of the PIT relative to an IPSBAR definition. Move the base
address definitions into the per-part headers. This is a lot more consistent
since all the other peripheral base addresses are defined in the per-part
header files already.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m520xsim.h       |  6 ++++++
 arch/m68k/include/asm/m523xsim.h       |  9 ++++++++-
 arch/m68k/include/asm/m527xsim.h       | 11 ++++++++---
 arch/m68k/include/asm/m528xsim.h       |  8 ++++++++
 arch/m68k/include/asm/mcfpit.h         | 16 +---------------
 arch/m68knommu/platform/coldfire/pit.c |  2 +-
 6 files changed, 32 insertions(+), 20 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 88ed8239fe4e..afc21ad78f43 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -133,6 +133,12 @@
 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
 
+/*
+ *  PIT timer module.
+ */
+#define	MCFPIT_BASE1		0xFC080000	/* Base address of TIMER1 */
+#define	MCFPIT_BASE2		0xFC084000	/* Base address of TIMER2 */
+
 /*
  *  UART module.
  */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 9701ed34d234..6be94f6831ae 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -119,9 +119,16 @@
 #define MCFGPIO_PCLRR_ETPU	(MCF_IPSBAR + 0x10003C)
 
 /*
- * EPort
+ * PIT timer base addresses.
  */
+#define	MCFPIT_BASE1		(MCF_IPSBAR + 0x150000)
+#define	MCFPIT_BASE2		(MCF_IPSBAR + 0x160000)
+#define	MCFPIT_BASE3		(MCF_IPSBAR + 0x170000)
+#define	MCFPIT_BASE4		(MCF_IPSBAR + 0x180000)
 
+/*
+ * EPort
+ */
 #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
 #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 3712f611bd5e..cb7df04ad0c4 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -232,15 +232,20 @@
 #endif
 
 /*
- * EPort
+ * PIT timer base addresses.
  */
+#define	MCFPIT_BASE1		(MCF_IPSBAR + 0x150000)
+#define	MCFPIT_BASE2		(MCF_IPSBAR + 0x160000)
+#define	MCFPIT_BASE3		(MCF_IPSBAR + 0x170000)
+#define	MCFPIT_BASE4		(MCF_IPSBAR + 0x180000)
 
+/*
+ * EPort
+ */
 #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
 #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
 
-
-
 /*
  *	GPIO pins setups to enable the UARTs.
  */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index a918545f6a5a..014098a7de89 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -163,6 +163,14 @@
 #define MCFGPIO_PTDPAR		(MCF_IPSBAR + 0x0010005B)
 #define MCFGPIO_PUAPAR		(MCF_IPSBAR + 0x0010005C)
 
+/*
+ * PIT timer base addresses.
+ */
+#define	MCFPIT_BASE1		(MCF_IPSBAR + 0x00150000)
+#define	MCFPIT_BASE2		(MCF_IPSBAR + 0x00160000)
+#define	MCFPIT_BASE3		(MCF_IPSBAR + 0x00170000)
+#define	MCFPIT_BASE4		(MCF_IPSBAR + 0x00180000)
+
 /*
  * 	Edge Port registers
  */
diff --git a/arch/m68k/include/asm/mcfpit.h b/arch/m68k/include/asm/mcfpit.h
index f570cf64fd29..9fd321ca0725 100644
--- a/arch/m68k/include/asm/mcfpit.h
+++ b/arch/m68k/include/asm/mcfpit.h
@@ -11,22 +11,8 @@
 #define	mcfpit_h
 /****************************************************************************/
 
-
-/*
- *	Get address specific defines for the 5270/5271, 5280/5282, and 5208.
- */
-#if defined(CONFIG_M520x)
-#define	MCFPIT_BASE1		0x00080000	/* Base address of TIMER1 */
-#define	MCFPIT_BASE2		0x00084000	/* Base address of TIMER2 */
-#else
-#define	MCFPIT_BASE1		0x00150000	/* Base address of TIMER1 */
-#define	MCFPIT_BASE2		0x00160000	/* Base address of TIMER2 */
-#define	MCFPIT_BASE3		0x00170000	/* Base address of TIMER3 */
-#define	MCFPIT_BASE4		0x00180000	/* Base address of TIMER4 */
-#endif
-
 /*
- *	Define the PIT timer register set addresses.
+ *	Define the PIT timer register address offsets.
  */
 #define	MCFPIT_PCSR		0x0		/* PIT control register */
 #define	MCFPIT_PMR		0x2		/* PIT modulus register */
diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c
index aebea19abd78..c2b980926bec 100644
--- a/arch/m68knommu/platform/coldfire/pit.c
+++ b/arch/m68knommu/platform/coldfire/pit.c
@@ -31,7 +31,7 @@
  *	By default use timer1 as the system clock timer.
  */
 #define	FREQ	((MCF_CLK / 2) / 64)
-#define	TA(a)	(MCF_IPSBAR + MCFPIT_BASE1 + (a))
+#define	TA(a)	(MCFPIT_BASE1 + (a))
 #define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
 
 static u32 pit_cnt;
-- 
cgit v1.2.3


From 571f0608e1a53d6d405c385cc9c11b7902b35b7f Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sat, 5 Mar 2011 23:50:37 +1000
Subject: m68knommu: remove MBAR and IPSBAR hacks for the ColdFire 520x CPUs

The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses.
They do not use the setable peripheral address registers like the MBAR
and IPSBAR used on many other ColdFire parts. Don't use fake values
of MBAR and IPSBAR when using peripheral addresses for them, there
is no need to.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h        |  7 +-----
 arch/m68k/include/asm/m520xsim.h        | 40 +++++++++++++++++++--------------
 arch/m68knommu/platform/520x/config.c   | 36 ++++++++++++++---------------
 arch/m68knommu/platform/coldfire/head.S |  4 ++--
 4 files changed, 44 insertions(+), 43 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 8daea2cf202e..c7dce7e55686 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -31,14 +31,9 @@
  *	This is generally setup by the boards start up code.
  */
 #define	MCF_MBAR	0x10000000
-#if defined(CONFIG_M520x)
-#define	MCF_IPSBAR	0xFC000000
-#else
 #define	MCF_IPSBAR	0x40000000
-#endif
 
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x)
+#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
 #undef MCF_MBAR
 #define	MCF_MBAR	MCF_IPSBAR
 #endif
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index afc21ad78f43..87f8ce73b318 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -19,7 +19,7 @@
 /*
  *  Define the 520x SIM register set addresses.
  */
-#define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
+#define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */
 #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
 #define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
 #define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
@@ -35,9 +35,9 @@
  *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
  *  The 520x family only has a single INTC unit.
  */
-#define MCFINTC0_SIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
-#define MCFINTC0_CIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
-#define	MCFINTC0_ICR0       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
+#define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)
+#define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)
+#define	MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)
 #define MCFINTC1_SIMR       (0)
 #define MCFINTC1_CIMR       (0)
 #define	MCFINTC1_ICR0       (0)
@@ -52,12 +52,12 @@
 /*
  *  SDRAM configuration registers.
  */
-#define MCFSIM_SDMR         0x000a8000	/* SDRAM Mode/Extended Mode Register */
-#define MCFSIM_SDCR         0x000a8004	/* SDRAM Control Register */
-#define MCFSIM_SDCFG1       0x000a8008	/* SDRAM Configuration Register 1 */
-#define MCFSIM_SDCFG2       0x000a800c	/* SDRAM Configuration Register 2 */
-#define MCFSIM_SDCS0        0x000a8110	/* SDRAM Chip Select 0 Configuration */
-#define MCFSIM_SDCS1        0x000a8114	/* SDRAM Chip Select 1 Configuration */
+#define MCFSIM_SDMR         0xFC0a8000	/* SDRAM Mode/Extended Mode Register */
+#define MCFSIM_SDCR         0xFC0a8004	/* SDRAM Control Register */
+#define MCFSIM_SDCFG1       0xFC0a8008	/* SDRAM Configuration Register 1 */
+#define MCFSIM_SDCFG2       0xFC0a800c	/* SDRAM Configuration Register 2 */
+#define MCFSIM_SDCS0        0xFC0a8110	/* SDRAM Chip Select 0 Configuration */
+#define MCFSIM_SDCS1        0xFC0a8114	/* SDRAM Chip Select 1 Configuration */
 
 /*
  * EPORT and GPIO registers.
@@ -119,10 +119,10 @@
 #define MCFGPIO_IRQ_MAX			8
 #define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
 
-#define MCF_GPIO_PAR_UART                   (0xA4036)
-#define MCF_GPIO_PAR_FECI2C                 (0xA4033)
-#define MCF_GPIO_PAR_QSPI                   (0xA4034)
-#define MCF_GPIO_PAR_FEC                    (0xA4038)
+#define MCF_GPIO_PAR_UART		0xFC0A4036
+#define MCF_GPIO_PAR_FECI2C		0xFC0A4033
+#define MCF_GPIO_PAR_QSPI		0xFC0A4034
+#define MCF_GPIO_PAR_FEC		0xFC0A4038
 
 #define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
 #define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
@@ -142,9 +142,15 @@
 /*
  *  UART module.
  */
-#define MCFUART_BASE1		0x60000		/* Base address of UART1 */
-#define MCFUART_BASE2		0x64000		/* Base address of UART2 */
-#define MCFUART_BASE3		0x68000		/* Base address of UART2 */
+#define MCFUART_BASE1		0xFC060000	/* Base address of UART1 */
+#define MCFUART_BASE2		0xFC064000	/* Base address of UART2 */
+#define MCFUART_BASE3		0xFC068000	/* Base address of UART2 */
+
+/*
+ *  FEC module.
+ */
+#define	MCFFEC_BASE		0xFC030000	/* Base of FEC ethernet */
+#define	MCFFEC_SIZE		0x800		/* Register set size */
 
 /*
  *  Reset Controll Unit.
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 71d2ba474c63..621238f1a219 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -27,15 +27,15 @@
 
 static struct mcf_platform_uart m520x_uart_platform[] = {
 	{
-		.mapbase	= MCF_MBAR + MCFUART_BASE1,
+		.mapbase	= MCFUART_BASE1,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
+		.mapbase 	= MCFUART_BASE2,
 		.irq		= MCFINT_VECBASE + MCFINT_UART1,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE3,
+		.mapbase 	= MCFUART_BASE3,
 		.irq		= MCFINT_VECBASE + MCFINT_UART2,
 	},
 	{ },
@@ -49,8 +49,8 @@ static struct platform_device m520x_uart = {
 
 static struct resource m520x_fec_resources[] = {
 	{
-		.start		= MCF_MBAR + 0x30000,
-		.end		= MCF_MBAR + 0x30000 + 0x7ff,
+		.start		= MCFFEC_BASE,
+		.end		= MCFFEC_BASE + MCFFEC_SIZE - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
@@ -208,11 +208,11 @@ static void __init m520x_qspi_init(void)
 {
 	u16 par;
 	/* setup Port QS for QSPI with gpio CS control */
-	writeb(0x3f, MCF_IPSBAR + MCF_GPIO_PAR_QSPI);
+	writeb(0x3f, MCF_GPIO_PAR_QSPI);
 	/* make U1CTS and U2RTS gpio for cs_control */
-	par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+	par = readw(MCF_GPIO_PAR_UART);
 	par &= 0x00ff;
-	writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+	writew(par, MCF_GPIO_PAR_UART);
 }
 #endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
 
@@ -234,23 +234,23 @@ static void __init m520x_uart_init_line(int line, int irq)
 
 	switch (line) {
 	case 0:
-		par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+		par = readw(MCF_GPIO_PAR_UART);
 		par |= MCF_GPIO_PAR_UART_PAR_UTXD0 |
 		       MCF_GPIO_PAR_UART_PAR_URXD0;
-		writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+		writew(par, MCF_GPIO_PAR_UART);
 		break;
 	case 1:
-		par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
+		par = readw(MCF_GPIO_PAR_UART);
 		par |= MCF_GPIO_PAR_UART_PAR_UTXD1 |
 		       MCF_GPIO_PAR_UART_PAR_URXD1;
-		writew(par, MCF_IPSBAR + MCF_GPIO_PAR_UART);
+		writew(par, MCF_GPIO_PAR_UART);
 		break;
 	case 2:
-		par2 = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
+		par2 = readb(MCF_GPIO_PAR_FECI2C);
 		par2 &= ~0x0F;
 		par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
 			MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
-		writeb(par2, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
+		writeb(par2, MCF_GPIO_PAR_FECI2C);
 		break;
 	}
 }
@@ -271,11 +271,11 @@ static void __init m520x_fec_init(void)
 	u8 v;
 
 	/* Set multi-function pins to ethernet mode */
-	v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
-	writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
+	v = readb(MCF_GPIO_PAR_FEC);
+	writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
 
-	v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
-	writeb(v | 0x0f, MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
+	v = readb(MCF_GPIO_PAR_FECI2C);
+	writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
 }
 
 /***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index d5977909ae5f..7967e8ab9fae 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -68,14 +68,14 @@
 #elif defined(CONFIG_M520x)
 .macro GET_MEM_SIZE
 	clrl	%d0
-	movel	MCF_MBAR+MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
+	movel	MCFSIM_SDCS0, %d2	/* Get SDRAM chip select 0 config */
 	andl	#0x1f, %d2		/* Get only the chip select size */
 	beq	3f			/* Check if it is enabled */
 	addql	#1, %d2			/* Form exponent */
 	moveql	#1, %d0
 	lsll	%d2, %d0		/* 2 ^ exponent */
 3:
-	movel	MCF_MBAR+MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
+	movel	MCFSIM_SDCS1, %d2	/* Get SDRAM chip select 1 config */
 	andl	#0x1f, %d2		/* Get only the chip select size */
 	beq	4f			/* Check if it is enabled */
 	addql	#1, %d2			/* Form exponent */
-- 
cgit v1.2.3


From b62384afddbe7173b08420c67e6cbb22aa1ba709 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 00:05:29 +1000
Subject: m68knommu: remove use of MBAR value for ColdFire 523x peripheral
 addressing

The ColdFire 523x family of CPUs does not have an MBAR register, so don't
define its peripheral addresses relative to one. Its internal peripherals
are relative to the IPSBAR register, so make sure to use that.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m523xsim.h      | 15 ++++++++++++---
 arch/m68knommu/platform/523x/config.c | 10 +++++-----
 2 files changed, 17 insertions(+), 8 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 6be94f6831ae..6e5c17a4bcb5 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -58,10 +58,19 @@
 /*
  *  UART module.
  */
-#define MCFUART_BASE1		0x200           /* Base address of UART1 */
-#define MCFUART_BASE2		0x240           /* Base address of UART2 */
-#define MCFUART_BASE3		0x280           /* Base address of UART3 */
+#define MCFUART_BASE1		(MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2		(MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3		(MCF_IPSBAR + 0x280)
 
+/*
+ *  FEC ethernet module.
+ */
+#define	MCFFEC_BASE		(MCF_IPSBAR + 0x1000)
+#define	MCFFEC_SIZE		0x800
+
+/*
+ *  GPIO module.
+ */
 #define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)
 #define MCFGPIO_PODR_DATAH	(MCF_IPSBAR + 0x100001)
 #define MCFGPIO_PODR_DATAL	(MCF_IPSBAR + 0x100002)
diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c
index 8980f6d7715a..418a76feb1e3 100644
--- a/arch/m68knommu/platform/523x/config.c
+++ b/arch/m68knommu/platform/523x/config.c
@@ -28,15 +28,15 @@
 
 static struct mcf_platform_uart m523x_uart_platform[] = {
 	{
-		.mapbase	= MCF_MBAR + MCFUART_BASE1,
+		.mapbase	= MCFUART_BASE1,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
+		.mapbase 	= MCFUART_BASE2,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0 + 1,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE3,
+		.mapbase 	= MCFUART_BASE3,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0 + 2,
 	},
 	{ },
@@ -50,8 +50,8 @@ static struct platform_device m523x_uart = {
 
 static struct resource m523x_fec_resources[] = {
 	{
-		.start		= MCF_MBAR + 0x1000,
-		.end		= MCF_MBAR + 0x1000 + 0x7ff,
+		.start		= MCFFEC_BASE,
+		.end		= MCFFEC_BASE + MCFFEC_SIZE - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
-- 
cgit v1.2.3


From 9a6b0c73afa702eee1803e664eae1b951faf895c Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 00:13:17 +1000
Subject: m68knommu: remove use of MBAR value for ColdFire 527x peripheral
 addressing

The ColdFire 527x family of CPUs does not have an MBAR register, so don't
define its peripheral addresses relative to one. Its internal peripherals
are relative to the IPSBAR register, so make sure to use that.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m527xsim.h      | 14 +++++++++++---
 arch/m68knommu/platform/527x/config.c | 14 +++++++-------
 2 files changed, 18 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index cb7df04ad0c4..d299552ab5b0 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -63,9 +63,17 @@
 /*
  *	UART module.
  */
-#define MCFUART_BASE1		0x200           /* Base address of UART1 */
-#define MCFUART_BASE2		0x240           /* Base address of UART2 */
-#define MCFUART_BASE3		0x280           /* Base address of UART3 */
+#define MCFUART_BASE1		(MCF_IPSBAR + 0x200)
+#define MCFUART_BASE2		(MCF_IPSBAR + 0x240)
+#define MCFUART_BASE3		(MCF_IPSBAR + 0x280)
+
+/*
+ *	FEC ethernet module.
+ */
+#define	MCFFEC_BASE0		(MCF_IPSBAR + 0x1000)
+#define	MCFFEC_SIZE0		0x800
+#define	MCFFEC_BASE1		(MCF_IPSBAR + 0x1800)
+#define	MCFFEC_SIZE1		0x800
 
 #ifdef CONFIG_M5271
 #define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index 3d9c35c98b98..fa359593b613 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -28,15 +28,15 @@
 
 static struct mcf_platform_uart m527x_uart_platform[] = {
 	{
-		.mapbase	= MCF_MBAR + MCFUART_BASE1,
+		.mapbase	= MCFUART_BASE1,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
+		.mapbase 	= MCFUART_BASE2,
 		.irq		= MCFINT_VECBASE + MCFINT_UART1,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE3,
+		.mapbase 	= MCFUART_BASE3,
 		.irq		= MCFINT_VECBASE + MCFINT_UART2,
 	},
 	{ },
@@ -50,8 +50,8 @@ static struct platform_device m527x_uart = {
 
 static struct resource m527x_fec0_resources[] = {
 	{
-		.start		= MCF_MBAR + 0x1000,
-		.end		= MCF_MBAR + 0x1000 + 0x7ff,
+		.start		= MCFFEC_BASE0,
+		.end		= MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
@@ -73,8 +73,8 @@ static struct resource m527x_fec0_resources[] = {
 
 static struct resource m527x_fec1_resources[] = {
 	{
-		.start		= MCF_MBAR + 0x1800,
-		.end		= MCF_MBAR + 0x1800 + 0x7ff,
+		.start		= MCFFEC_BASE1,
+		.end		= MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
-- 
cgit v1.2.3


From a0ba4332a2cb110d6ef7695e64887396ab7d09d6 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 00:20:01 +1000
Subject: m68knommu: remove use of MBAR value for ColdFire 528x peripheral
 addressing

The ColdFire 528x family of CPUs does not have an MBAR register, so don't
define its peripheral addresses relative to one. Its internal peripherals
are relative to the IPSBAR register, so make sure to use that.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m528xsim.h      | 12 +++++++++---
 arch/m68knommu/platform/528x/config.c | 14 +++++++-------
 2 files changed, 16 insertions(+), 10 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 014098a7de89..d7c92419f2b5 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -49,9 +49,15 @@
 /*
  *	UART module.
  */
-#define MCFUART_BASE1		0x200           /* Base address of UART1 */
-#define MCFUART_BASE2		0x240           /* Base address of UART2 */
-#define MCFUART_BASE3		0x280           /* Base address of UART3 */
+#define	MCFUART_BASE1		(MCF_IPSBAR + 0x00000200)
+#define	MCFUART_BASE2		(MCF_IPSBAR + 0x00000240)
+#define	MCFUART_BASE3		(MCF_IPSBAR + 0x00000280)
+
+/*
+ *	FEC ethernet module.
+ */
+#define	MCFFEC_BASE		(MCF_IPSBAR + 0x00001000)
+#define	MCFFEC_SIZE		0x800
 
 /*
  * 	GPIO registers
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index 76b743343bfa..ac39fc661219 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -29,15 +29,15 @@
 
 static struct mcf_platform_uart m528x_uart_platform[] = {
 	{
-		.mapbase	= MCF_MBAR + MCFUART_BASE1,
+		.mapbase	= MCFUART_BASE1,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE2,
+		.mapbase 	= MCFUART_BASE2,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0 + 1,
 	},
 	{
-		.mapbase 	= MCF_MBAR + MCFUART_BASE3,
+		.mapbase 	= MCFUART_BASE3,
 		.irq		= MCFINT_VECBASE + MCFINT_UART0 + 2,
 	},
 	{ },
@@ -51,8 +51,8 @@ static struct platform_device m528x_uart = {
 
 static struct resource m528x_fec_resources[] = {
 	{
-		.start		= MCF_MBAR + 0x1000,
-		.end		= MCF_MBAR + 0x1000 + 0x7ff,
+		.start		= MCFFEC_BASE,
+		.end		= MCFFEC_BASE + MCFFEC_SIZE - 1,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
@@ -227,9 +227,9 @@ static void __init m528x_uart_init_line(int line, int irq)
 
 	/* make sure PUAPAR is set for UART0 and UART1 */
 	if (line < 2) {
-		port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR);
+		port = readb(MCF5282_GPIO_PUAPAR);
 		port |= (0x03 << (line * 2));
-		writeb(port, MCF_MBAR + MCF5282_GPIO_PUAPAR);
+		writeb(port, MCF5282_GPIO_PUAPAR);
 	}
 }
 
-- 
cgit v1.2.3


From babc08b7e953cd23e10d175d546309dedadaabea Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 00:54:36 +1000
Subject: m68knommu: move ColdFire DMA register addresses to per-cpu headers

The base addresses of the ColdFire DMA unit registers belong with
all the other address definitions in the per-cpu headers. The current
definitions assume they are relative to an MBAR register. Not all
ColdFire CPUs have an MBAR register. A clean address define can only
be acheived in the per-cpu headers along with all the other chips
peripheral base addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m5206sim.h       |  3 +++
 arch/m68k/include/asm/m523xsim.h       |  9 +++++++++
 arch/m68k/include/asm/m5249sim.h       |  8 ++++++++
 arch/m68k/include/asm/m5272sim.h       |  2 ++
 arch/m68k/include/asm/m527xsim.h       |  8 ++++++++
 arch/m68k/include/asm/m528xsim.h       |  8 ++++++++
 arch/m68k/include/asm/m5307sim.h       |  8 ++++++++
 arch/m68k/include/asm/m5407sim.h       |  8 ++++++++
 arch/m68k/include/asm/mcfdma.h         | 23 -----------------------
 arch/m68knommu/platform/coldfire/dma.c |  8 ++++----
 10 files changed, 58 insertions(+), 27 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 561b03b5ddf8..6fb656f18455 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -92,6 +92,9 @@
 #define	MCFSIM_PADDR		(MCF_MBAR + 0x1c5)	/* Parallel Direction (r/w) */
 #define	MCFSIM_PADAT		(MCF_MBAR + 0x1c9)	/* Parallel Port Value (r/w) */
 
+#define	MCFDMA_BASE0		(MCF_MBAR + 0x200)	/* Base address DMA 0 */
+#define	MCFDMA_BASE1		(MCF_MBAR + 0x240)	/* Base address DMA 1 */
+
 #if defined(CONFIG_NETtel)
 #define	MCFUART_BASE1		0x180		/* Base address of UART1 */
 #define	MCFUART_BASE2		0x140		/* Base address of UART2 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 6e5c17a4bcb5..89067bd04150 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -160,5 +160,14 @@
 */
 #define	MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
 #define	MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
+
+/*
+ * DMA unit base addresses.
+ */
+#define	MCFDMA_BASE0		(MCF_IPSBAR + 0x100)
+#define	MCFDMA_BASE1		(MCF_IPSBAR + 0x140)
+#define	MCFDMA_BASE2		(MCF_IPSBAR + 0x180)
+#define	MCFDMA_BASE3		(MCF_IPSBAR + 0x1C0)
+
 /****************************************************************************/
 #endif	/* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 6698b0581040..aefb83ef8392 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -72,6 +72,14 @@
 #define MCFUART_BASE1		0x1c0           /* Base address of UART1 */
 #define MCFUART_BASE2		0x200           /* Base address of UART2 */
 
+/*
+ *	DMA unit base addresses.
+ */
+#define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
+#define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
+#define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
+#define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
+
 /*
  *	Some symbol defines for the above...
  */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index b7cc50abc831..3b43fee72573 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -80,6 +80,8 @@
 #define	MCFSIM_PCDAT		(MCF_MBAR + 0x96) /* Port C Data (r/w) */
 #define	MCFSIM_PDCNT		(MCF_MBAR + 0x98) /* Port D Control (r/w) */
 
+#define	MCFDMA_BASE0		(MCF_MBAR + 0xe0) /* Base address DMA 0 */
+
 /*
  *	Define system peripheral IRQ usage.
  */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index d299552ab5b0..04b8c103095d 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -60,6 +60,14 @@
 #define	MCFSIM_DMR1		0x5c		/* SDRAM address mask 1 */
 #endif
 
+/*
+ *	DMA unit base addresses.
+ */
+#define	MCFDMA_BASE0		(MCF_IPSBAR + 0x100)
+#define	MCFDMA_BASE1		(MCF_IPSBAR + 0x140)
+#define	MCFDMA_BASE2		(MCF_IPSBAR + 0x180)
+#define	MCFDMA_BASE3		(MCF_IPSBAR + 0x1C0)
+
 /*
  *	UART module.
  */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index d7c92419f2b5..87c0cce59057 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -46,6 +46,14 @@
 #define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */
 #define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */
 
+/*
+ *	DMA unit base addresses.
+ */
+#define	MCFDMA_BASE0		(MCF_IPSBAR + 0x00000100)
+#define	MCFDMA_BASE1		(MCF_IPSBAR + 0x00000140)
+#define	MCFDMA_BASE2		(MCF_IPSBAR + 0x00000180)
+#define	MCFDMA_BASE3		(MCF_IPSBAR + 0x000001C0)
+
 /*
  *	UART module.
  */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 0bf57397e7a9..39285769c0e2 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -98,6 +98,14 @@
 #define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
 #define	MCFSIM_PADAT		(MCF_MBAR + 0x248)
 
+/*
+ *  DMA unit base addresses.
+ */
+#define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
+#define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
+#define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
+#define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
+
 /*
  *  UART module.
  */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 75f5c28a551d..70181727326f 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -84,6 +84,14 @@
 #define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
 #define	MCFSIM_PADAT		(MCF_MBAR + 0x248)
 
+/*
+ *	DMA unit base addresses.
+ */
+#define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
+#define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
+#define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
+#define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
+
 /*
  * Generic GPIO support
  */
diff --git a/arch/m68k/include/asm/mcfdma.h b/arch/m68k/include/asm/mcfdma.h
index 705c52c79cd8..10bc7e391c14 100644
--- a/arch/m68k/include/asm/mcfdma.h
+++ b/arch/m68k/include/asm/mcfdma.h
@@ -11,29 +11,6 @@
 #define	mcfdma_h
 /****************************************************************************/
 
-
-/*
- *	Get address specific defines for this Coldfire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define	MCFDMA_BASE0		0x200		/* Base address of DMA 0 */
-#define	MCFDMA_BASE1		0x240		/* Base address of DMA 1 */
-#elif defined(CONFIG_M5272)
-#define	MCFDMA_BASE0		0x0e0		/* Base address of DMA 0 */
-#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-/* These are relative to the IPSBAR, not MBAR */
-#define	MCFDMA_BASE0		0x100		/* Base address of DMA 0 */
-#define	MCFDMA_BASE1		0x140		/* Base address of DMA 1 */
-#define	MCFDMA_BASE2		0x180		/* Base address of DMA 2 */
-#define	MCFDMA_BASE3		0x1C0		/* Base address of DMA 3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define	MCFDMA_BASE0		0x300		/* Base address of DMA 0 */
-#define	MCFDMA_BASE1		0x340		/* Base address of DMA 1 */
-#define	MCFDMA_BASE2		0x380		/* Base address of DMA 2 */
-#define	MCFDMA_BASE3		0x3C0		/* Base address of DMA 3 */
-#endif
-
-
 #if !defined(CONFIG_M5272)
 
 /*
diff --git a/arch/m68knommu/platform/coldfire/dma.c b/arch/m68knommu/platform/coldfire/dma.c
index 2b30cf1b8f77..e88b95e2cc62 100644
--- a/arch/m68knommu/platform/coldfire/dma.c
+++ b/arch/m68knommu/platform/coldfire/dma.c
@@ -21,16 +21,16 @@
  */
 unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
 #ifdef MCFDMA_BASE0
-	MCF_MBAR + MCFDMA_BASE0,
+	MCFDMA_BASE0,
 #endif
 #ifdef MCFDMA_BASE1
-	MCF_MBAR + MCFDMA_BASE1,
+	MCFDMA_BASE1,
 #endif
 #ifdef MCFDMA_BASE2
-	MCF_MBAR + MCFDMA_BASE2,
+	MCFDMA_BASE2,
 #endif
 #ifdef MCFDMA_BASE3
-	MCF_MBAR + MCFDMA_BASE3,
+	MCFDMA_BASE3,
 #endif
 };
 
-- 
cgit v1.2.3


From 58f0ac98f386d2b335e5852e8feec828c43a0e13 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:57:14 +1000
Subject: m68knommu: remove use of MBAR in old-style ColdFire timer

Not all ColdFire CPUs that use the old style timer hardware module use
an MBAR set peripheral region. Move the TIMER base address defines to the
per-CPU header files where we can set it correctly based on how the
peripherals are mapped - instead of using a fake MBAR for some platforms.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m5206sim.h          |  3 +++
 arch/m68k/include/asm/m5249sim.h          |  8 +++++++-
 arch/m68k/include/asm/m5272sim.h          |  5 +++++
 arch/m68k/include/asm/m5307sim.h          |  6 ++++++
 arch/m68k/include/asm/m532xsim.h          |  8 ++++++++
 arch/m68k/include/asm/m5407sim.h          |  6 ++++++
 arch/m68k/include/asm/mcftimer.h          | 23 -----------------------
 arch/m68knommu/platform/coldfire/timers.c |  4 ++--
 8 files changed, 37 insertions(+), 26 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 6fb656f18455..7b58da5050a0 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -89,6 +89,9 @@
 #define	MCFSIM_PAR		0xcb		/* Pin Assignment reg (r/w) */
 #endif
 
+#define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */
+#define	MCFTIMER_BASE2		(MCF_MBAR + 0x120)	/* Base of TIMER2 */
+
 #define	MCFSIM_PADDR		(MCF_MBAR + 0x1c5)	/* Parallel Direction (r/w) */
 #define	MCFSIM_PADAT		(MCF_MBAR + 0x1c9)	/* Parallel Port Value (r/w) */
 
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index aefb83ef8392..c318ce786f93 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -19,7 +19,7 @@
 /*
  *	The 5249 has a second MBAR region, define its address.
  */
-#define	MCF_MBAR2		0x80000000
+#define MCF_MBAR2		0x80000000
 
 /*
  *	Define the 5249 SIM register set addresses.
@@ -66,6 +66,12 @@
 #define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
 #define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
 
+/*
+ *	Timer module.
+ */
+#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
+#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
+
 /*
  *	UART module.
  */
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 3b43fee72573..57ca4de1f911 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -82,6 +82,11 @@
 
 #define	MCFDMA_BASE0		(MCF_MBAR + 0xe0) /* Base address DMA 0 */
 
+#define	MCFTIMER_BASE1		(MCF_MBAR + 0x200) /* Base address TIMER1 */
+#define	MCFTIMER_BASE2		(MCF_MBAR + 0x220) /* Base address TIMER2 */
+#define	MCFTIMER_BASE3		(MCF_MBAR + 0x240) /* Base address TIMER4 */
+#define	MCFTIMER_BASE4		(MCF_MBAR + 0x260) /* Base address TIMER3 */
+
 /*
  *	Define system peripheral IRQ usage.
  */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 39285769c0e2..c3846fcfa5d1 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -95,6 +95,12 @@
 #define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
 #define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
 
+/*
+ *  Timer module.
+ */
+#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
+#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
+
 #define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
 #define	MCFSIM_PADAT		(MCF_MBAR + 0x248)
 
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index e6470f8ca324..0dea126f3fcf 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -85,6 +85,14 @@
 #define MCFUART_BASE2		0xFC064000	/* Base address of UART2 */
 #define MCFUART_BASE3		0xFC068000	/* Base address of UART3 */
 
+/*
+ *  Timer module.
+ */
+#define MCFTIMER_BASE1		0xFC070000	/* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0xFC074000	/* Base address of TIMER2 */
+#define MCFTIMER_BASE3		0xFC078000	/* Base address of TIMER3 */
+#define MCFTIMER_BASE4		0xFC07C000	/* Base address of TIMER4 */
+
 /*********************************************************************
  *
  * Reset Controller Module
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 70181727326f..43272584dc09 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -78,6 +78,12 @@
 #define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
 #define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
 
+/*
+ *	Timer module.
+ */
+#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
+#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
+
 #define MCFUART_BASE1		0x1c0           /* Base address of UART1 */
 #define MCFUART_BASE2		0x200           /* Base address of UART2 */
 
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 0f90f6d2227a..92b276fe8240 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -12,29 +12,6 @@
 #define	mcftimer_h
 /****************************************************************************/
 
-
-/*
- *	Get address specific defines for this ColdFire member.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
-#define	MCFTIMER_BASE1		0x100		/* Base address of TIMER1 */
-#define	MCFTIMER_BASE2		0x120		/* Base address of TIMER2 */
-#elif defined(CONFIG_M5272)
-#define MCFTIMER_BASE1		0x200           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x220           /* Base address of TIMER2 */
-#define MCFTIMER_BASE3		0x240           /* Base address of TIMER4 */
-#define MCFTIMER_BASE4		0x260           /* Base address of TIMER3 */
-#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
-#define MCFTIMER_BASE1		0x140           /* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0x180           /* Base address of TIMER2 */
-#elif defined(CONFIG_M532x)
-#define MCFTIMER_BASE1		0xfc070000	/* Base address of TIMER1 */
-#define MCFTIMER_BASE2		0xfc074000	/* Base address of TIMER2 */
-#define MCFTIMER_BASE3		0xfc078000	/* Base address of TIMER3 */
-#define MCFTIMER_BASE4		0xfc07c000	/* Base address of TIMER4 */
-#endif
-
-
 /*
  *	Define the TIMER register set addresses.
  */
diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c
index 2304d736c701..60242f65fea9 100644
--- a/arch/m68knommu/platform/coldfire/timers.c
+++ b/arch/m68knommu/platform/coldfire/timers.c
@@ -28,7 +28,7 @@
  *	By default use timer1 as the system clock timer.
  */
 #define	FREQ	(MCF_BUSCLK / 16)
-#define	TA(a)	(MCF_MBAR + MCFTIMER_BASE1 + (a))
+#define	TA(a)	(MCFTIMER_BASE1 + (a))
 
 /*
  *	These provide the underlying interrupt vector support.
@@ -126,7 +126,7 @@ void hw_timer_init(void)
 /*
  *	By default use timer2 as the profiler clock timer.
  */
-#define	PA(a)	(MCF_MBAR + MCFTIMER_BASE2 + (a))
+#define	PA(a)	(MCFTIMER_BASE2 + (a))
 
 /*
  *	Choose a reasonably fast profile timer. Make it an odd value to
-- 
cgit v1.2.3


From 6a92e1982d5c538d1cfafbe4b0cb16d49306854f Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 23:01:46 +1000
Subject: m68knommu: clean up use of MBAR for DRAM registers on ColdFire start

In some of the RAM size autodetection code on ColdFire CPU startup
we reference DRAM registers relative to the MBAR register. Not all of
the supported ColdFire CPUs have an MBAR, and currently this works
because we fake an MBAR address on those registers. In an effort to
clean this up, and eventually remove the fake MBAR setting make the
DRAM register address definitions actually contain the MBAR (or IPSBAR
as appropriate) value as required.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m5206sim.h        | 16 ++++++++--------
 arch/m68k/include/asm/m523xsim.h        | 10 +++++-----
 arch/m68k/include/asm/m5249sim.h        | 10 +++++-----
 arch/m68k/include/asm/m527xsim.h        | 26 +++++++++++++-------------
 arch/m68k/include/asm/m528xsim.h        | 10 +++++-----
 arch/m68k/include/asm/m5307sim.h        | 10 +++++-----
 arch/m68k/include/asm/m5407sim.h        | 10 +++++-----
 arch/m68knommu/platform/coldfire/head.S |  6 +++---
 8 files changed, 49 insertions(+), 49 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 7b58da5050a0..dfd6d3f73584 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -48,14 +48,14 @@
 #define	MCFSIM_SWIVR		0x42		/* SW Watchdog intr reg (r/w) */
 #define	MCFSIM_SWSR		0x43		/* SW Watchdog service (r/w) */
 
-#define	MCFSIM_DCRR		0x46		/* DRAM Refresh reg (r/w) */
-#define	MCFSIM_DCTR		0x4a		/* DRAM Timing reg (r/w) */
-#define	MCFSIM_DAR0		0x4c		/* DRAM 0 Address reg(r/w) */
-#define	MCFSIM_DMR0		0x50		/* DRAM 0 Mask reg (r/w) */
-#define	MCFSIM_DCR0		0x57		/* DRAM 0 Control reg (r/w) */
-#define	MCFSIM_DAR1		0x58		/* DRAM 1 Address reg (r/w) */
-#define	MCFSIM_DMR1		0x5c		/* DRAM 1 Mask reg (r/w) */
-#define	MCFSIM_DCR1		0x63		/* DRAM 1 Control reg (r/w) */
+#define	MCFSIM_DCRR		(MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
+#define	MCFSIM_DCTR		(MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
+#define	MCFSIM_DAR0		(MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
+#define	MCFSIM_DMR0		(MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
+#define	MCFSIM_DCR0		(MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
+#define	MCFSIM_DAR1		(MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
+#define	MCFSIM_DMR1		(MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
+#define	MCFSIM_DCR1		(MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
 
 #define	MCFSIM_CSAR0		0x64		/* CS 0 Address 0 reg (r/w) */
 #define	MCFSIM_CSMR0		0x68		/* CS 0 Mask 0 reg (r/w) */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 89067bd04150..3f3dbf01a109 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -40,11 +40,11 @@
 /*
  *	SDRAM configuration registers.
  */
-#define	MCFSIM_DCR		0x44		/* SDRAM control */
-#define	MCFSIM_DACR0		0x48		/* SDRAM base address 0 */
-#define	MCFSIM_DMR0		0x4c		/* SDRAM address mask 0 */
-#define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */
-#define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */
+#define	MCFSIM_DCR		(MCF_IPSBAR + 0x44)	/* Control */
+#define	MCFSIM_DACR0		(MCF_IPSBAR + 0x48)	/* Base address 0 */
+#define	MCFSIM_DMR0		(MCF_IPSBAR + 0x4c)	/* Address mask 0 */
+#define	MCFSIM_DACR1		(MCF_IPSBAR + 0x50)	/* Base address 1 */
+#define	MCFSIM_DMR1		(MCF_IPSBAR + 0x54)	/* Address mask 1 */
 
 /*
  *  Reset Controll Unit (relative to IPSBAR).
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index c318ce786f93..33b0b4df07ca 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -60,11 +60,11 @@
 #define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */
 #define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */
 
-#define MCFSIM_DCR		0x100		/* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0		0x108		/* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0		0x10c		/* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
+#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
+#define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
 
 /*
  *	Timer module.
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 04b8c103095d..838fb2b1e88b 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -43,21 +43,21 @@
  *	SDRAM configuration registers.
  */
 #ifdef CONFIG_M5271
-#define	MCFSIM_DCR		0x40		/* SDRAM control */
-#define	MCFSIM_DACR0		0x48		/* SDRAM base address 0 */
-#define	MCFSIM_DMR0		0x4c		/* SDRAM address mask 0 */
-#define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */
-#define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */
+#define	MCFSIM_DCR		(MCF_IPSBAR + 0x40)	/* Control */
+#define	MCFSIM_DACR0		(MCF_IPSBAR + 0x48)	/* Base address 0 */
+#define	MCFSIM_DMR0		(MCF_IPSBAR + 0x4c)	/* Address mask 0 */
+#define	MCFSIM_DACR1		(MCF_IPSBAR + 0x50)	/* Base address 1 */
+#define	MCFSIM_DMR1		(MCF_IPSBAR + 0x54)	/* Address mask 1 */
 #endif
 #ifdef CONFIG_M5275
-#define	MCFSIM_DMR		0x40		/* SDRAM mode */
-#define	MCFSIM_DCR		0x44		/* SDRAM control */
-#define	MCFSIM_DCFG1		0x48		/* SDRAM configuration 1 */
-#define	MCFSIM_DCFG2		0x4c		/* SDRAM configuration 2 */
-#define	MCFSIM_DBAR0		0x50		/* SDRAM base address 0 */
-#define	MCFSIM_DMR0		0x54		/* SDRAM address mask 0 */
-#define	MCFSIM_DBAR1		0x58		/* SDRAM base address 1 */
-#define	MCFSIM_DMR1		0x5c		/* SDRAM address mask 1 */
+#define	MCFSIM_DMR		(MCF_IPSBAR + 0x40)	/* Mode */
+#define	MCFSIM_DCR		(MCF_IPSBAR + 0x44)	/* Control */
+#define	MCFSIM_DCFG1		(MCF_IPSBAR + 0x48)	/* Configuration 1 */
+#define	MCFSIM_DCFG2		(MCF_IPSBAR + 0x4c)	/* Configuration 2 */
+#define	MCFSIM_DBAR0		(MCF_IPSBAR + 0x50)	/* Base address 0 */
+#define	MCFSIM_DMR0		(MCF_IPSBAR + 0x54)	/* Address mask 0 */
+#define	MCFSIM_DBAR1		(MCF_IPSBAR + 0x58)	/* Base address 1 */
+#define	MCFSIM_DMR1		(MCF_IPSBAR + 0x5c)	/* Address mask 1 */
 #endif
 
 /*
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 87c0cce59057..47324f2258a7 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -40,11 +40,11 @@
 /*
  *	SDRAM configuration registers.
  */
-#define	MCFSIM_DCR		0x44		/* SDRAM control */
-#define	MCFSIM_DACR0		0x48		/* SDRAM base address 0 */
-#define	MCFSIM_DMR0		0x4c		/* SDRAM address mask 0 */
-#define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */
-#define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */
+#define	MCFSIM_DCR		(MCF_IPSBAR + 0x00000044) /* Control */
+#define	MCFSIM_DACR0		(MCF_IPSBAR + 0x00000048) /* Base address 0 */
+#define	MCFSIM_DMR0		(MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
+#define	MCFSIM_DACR1		(MCF_IPSBAR + 0x00000050) /* Base address 1 */
+#define	MCFSIM_DMR1		(MCF_IPSBAR + 0x00000054) /* Address mask 1 */
 
 /*
  *	DMA unit base addresses.
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index c3846fcfa5d1..e4365f2e5c29 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -89,11 +89,11 @@
 #define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */
 #endif /* CONFIG_OLDMASK */
 
-#define MCFSIM_DCR		0x100		/* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0		0x108		/* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0		0x10c		/* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
+#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM Addr/Ctrl 0 */
+#define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM Mask 0 */
+#define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM Addr/Ctrl 1 */
+#define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM Mask 1 */
 
 /*
  *  Timer module.
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 43272584dc09..c1eba01d26b0 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -72,11 +72,11 @@
 #define MCFSIM_CSMR7		0xd8		/* CS 7 Mask reg (r/w) */
 #define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */
 
-#define MCFSIM_DCR		0x100		/* DRAM Control reg (r/w) */
-#define MCFSIM_DACR0		0x108		/* DRAM 0 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR0		0x10c		/* DRAM 0 Mask reg (r/w) */
-#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
-#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
+#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
+#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
+#define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
+#define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
 
 /*
  *	Timer module.
diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S
index 7967e8ab9fae..129bff4956b5 100644
--- a/arch/m68knommu/platform/coldfire/head.S
+++ b/arch/m68knommu/platform/coldfire/head.S
@@ -41,17 +41,17 @@
  *	DRAM controller is quite different.
  */
 .macro GET_MEM_SIZE
-	movel	MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
+	movel	MCFSIM_DMR0,%d0		/* get mask for 1st bank */
 	btst	#0,%d0			/* check if region enabled */
 	beq	1f
 	andl	#0xfffc0000,%d0
 	beq	1f
 	addl	#0x00040000,%d0		/* convert mask to size */
 1:
-	movel	MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
+	movel	MCFSIM_DMR1,%d1		/* get mask for 2nd bank */
 	btst	#0,%d1			/* check if region enabled */
 	beq	2f
-	andl	#0xfffc0000, %d1
+	andl	#0xfffc0000,%d1
 	beq	2f
 	addl	#0x00040000,%d1
 	addl	%d1,%d0			/* total mem size in d0 */
-- 
cgit v1.2.3


From b195c47924ba3ff7434ab49412e5b2dab0a973fa Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 01:01:31 +1000
Subject: m68knommu: clean up definitions of ColdFire peripheral base registers

Different ColdFire CPUs have different ways of defining where their
internal peripheral registers sit in their address space. Some use an
MBAR register, some use and IPSBAR register, some have a fixed mapping.

Now that most of the peripheral address definitions have been cleaned up
we can clean up the setting of the MBAR and IPSBAR defines to limit them
to just where they are needed (and where they actually exist).

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index c7dce7e55686..f06a0a439129 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -27,15 +27,20 @@
 #endif
 
 /*
- *	Define the processor support peripherals base address.
+ *	Define the processor internal peripherals base address.
+ *
+ *	The majority of ColdFire parts use an MBAR register to set
+ *	the base address. Some have an IPSBAR register instead, and it
+ *	has slightly different rules on its size and alignment. Some
+ *	parts have fixed addresses and the internal peripherals cannot
+ *	be relocated in the address space.
+ *
  *	This is generally setup by the boards start up code.
  */
-#define	MCF_MBAR	0x10000000
-#define	MCF_IPSBAR	0x40000000
-
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-#undef MCF_MBAR
-#define	MCF_MBAR	MCF_IPSBAR
+#define	MCF_IPSBAR	0x40000000
+#else
+#define	MCF_MBAR	0x10000000
 #endif
 
 /****************************************************************************/
-- 
cgit v1.2.3


From d4852a34e46679f0a36b7c8803eace2b9002cddc Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 21:53:28 +1000
Subject: m68knommu: make ColdFire internal peripheral region configurable

Most ColdFire CPUs have an internal peripheral set that can be mapped at
a user selectable address. Different ColdFire parts either use an MBAR
register of an IPSBAR register to map the peripheral region. Most boards
use the Freescale default mappings - but not all.

Make the setting of the MBAR or IPSBAR register configurable. And only make
the selection available on the appropriate ColdFire CPU types.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h | 15 +++++++++------
 arch/m68knommu/Kconfig           | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 49 insertions(+), 6 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index f06a0a439129..98d1d25101f2 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -33,14 +33,17 @@
  *	the base address. Some have an IPSBAR register instead, and it
  *	has slightly different rules on its size and alignment. Some
  *	parts have fixed addresses and the internal peripherals cannot
- *	be relocated in the address space.
+ *	be relocated in the CPU address space.
  *
- *	This is generally setup by the boards start up code.
+ *	The value of MBAR or IPSBAR is config time selectable, we no
+ *	longer hard define it here. No MBAR or IPSBAR will be defined if
+ *	this part has a fixed peripheral address map.
  */
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
-#define	MCF_IPSBAR	0x40000000
-#else
-#define	MCF_MBAR	0x10000000
+#ifdef CONFIG_MBAR
+#define	MCF_MBAR	CONFIG_MBAR
+#endif
+#ifdef CONFIG_IPSBAR
+#define	MCF_IPSBAR	CONFIG_IPSBAR
 #endif
 
 /****************************************************************************/
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 04c7d348fbe7..b597ce07142b 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -79,6 +79,12 @@ config HAVE_CACHE_SPLIT
 config HAVE_CACHE_CB
 	bool
 
+config HAVE_MBAR
+	bool
+
+config HAVE_IPSBAR
+	bool
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -112,12 +118,14 @@ config M68360
 config M5206
 	bool "MCF5206"
 	select COLDFIRE_SW_A7
+	select HAVE_MBAR
 	help
 	  Motorola ColdFire 5206 processor support.
 
 config M5206e
 	bool "MCF5206e"
 	select COLDFIRE_SW_A7
+	select HAVE_MBAR
 	help
 	  Motorola ColdFire 5206e processor support.
 
@@ -132,30 +140,35 @@ config M523x
 	bool "MCF523x"
 	select GENERIC_CLOCKEVENTS
 	select HAVE_CACHE_SPLIT
+	select HAVE_IPSBAR
 	help
 	  Freescale Coldfire 5230/1/2/4/5 processor support
 
 config M5249
 	bool "MCF5249"
 	select COLDFIRE_SW_A7
+	select HAVE_MBAR
 	help
 	  Motorola ColdFire 5249 processor support.
 
 config M5271
 	bool "MCF5271"
 	select HAVE_CACHE_SPLIT
+	select HAVE_IPSBAR
 	help
 	  Freescale (Motorola) ColdFire 5270/5271 processor support.
 
 config M5272
 	bool "MCF5272"
 	select COLDFIRE_SW_A7
+	select HAVE_MBAR
 	help
 	  Motorola ColdFire 5272 processor support.
 
 config M5275
 	bool "MCF5275"
 	select HAVE_CACHE_SPLIT
+	select HAVE_IPSBAR
 	help
 	  Freescale (Motorola) ColdFire 5274/5275 processor support.
 
@@ -163,6 +176,7 @@ config M528x
 	bool "MCF528x"
 	select GENERIC_CLOCKEVENTS
 	select HAVE_CACHE_SPLIT
+	select HAVE_IPSBAR
 	help
 	  Motorola ColdFire 5280/5282 processor support.
 
@@ -170,6 +184,7 @@ config M5307
 	bool "MCF5307"
 	select COLDFIRE_SW_A7
 	select HAVE_CACHE_CB
+	select HAVE_MBAR
 	help
 	  Motorola ColdFire 5307 processor support.
 
@@ -183,18 +198,21 @@ config M5407
 	bool "MCF5407"
 	select COLDFIRE_SW_A7
 	select HAVE_CACHE_CB
+	select HAVE_MBAR
 	help
 	  Motorola ColdFire 5407 processor support.
 
 config M547x
 	bool "MCF547x"
 	select HAVE_CACHE_CB
+	select HAVE_MBAR
 	help
 	  Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support.
 
 config M548x
 	bool "MCF548x"
 	select HAVE_CACHE_CB
+	select HAVE_MBAR
 	help
 	  Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
 
@@ -650,6 +668,28 @@ config VECTORBASE
 	  platforms this address is programmed into the VBR register, thus
 	  actually setting the address to use.
 
+config MBAR
+	hex "Address of the MBAR (internal peripherals)"
+	default "0x10000000"
+	depends on HAVE_MBAR
+	help
+	  Define the address of the internal system peripherals. This value
+	  is set in the processors MBAR register. This is generally setup by
+	  the boot loader, and will not be written by the kernel. By far most
+	  ColdFire boards use the default 0x10000000 value, so if unsure then
+	  use this.
+
+config IPSBAR
+	hex "Address of the IPSBAR (internal peripherals)"
+	default "0x40000000"
+	depends on HAVE_IPSBAR
+	help
+	  Define the address of the internal system peripherals. This value
+	  is set in the processors IPSBAR register. This is generally setup by
+	  the boot loader, and will not be written by the kernel. By far most
+	  ColdFire boards use the default 0x40000000 value, so if unsure then
+	  use this.
+
 config KERNELBASE
 	hex "Address of the base of kernel code"
 	default "0x400"
-- 
cgit v1.2.3


From 7badfabb3fcee4fc4a0fd7c0437706b91fef3fff Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Sun, 6 Mar 2011 23:20:19 +1000
Subject: m68knommu: add basic support for the ColdFire based FireBee board

The FireBee is a ColdFire 5475 based board. Add a configuration option
to support it, and the basic platform flash layout code.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/Kconfig                 |  6 +++
 arch/m68knommu/platform/54xx/Makefile  |  1 +
 arch/m68knommu/platform/54xx/firebee.c | 86 ++++++++++++++++++++++++++++++++++
 3 files changed, 93 insertions(+)
 create mode 100644 arch/m68knommu/platform/54xx/firebee.c

(limited to 'arch')

diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index b597ce07142b..2e6fe63b7a0f 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -519,6 +519,12 @@ config M5407C3
 	help
 	  Support for the Motorola M5407C3 board.
 
+config FIREBEE
+	bool "FireBee board support"
+	depends on M547x
+	help
+	  Support for the FireBee ColdFire 5475 based board.
+
 config CLEOPATRA
 	bool "Feith CLEOPATRA board support"
 	depends on (M5307 || M5407)
diff --git a/arch/m68knommu/platform/54xx/Makefile b/arch/m68knommu/platform/54xx/Makefile
index e6035e7a2d3f..6cfd090ec3cd 100644
--- a/arch/m68knommu/platform/54xx/Makefile
+++ b/arch/m68knommu/platform/54xx/Makefile
@@ -15,4 +15,5 @@
 asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
 
 obj-y := config.o
+obj-$(CONFIG_FIREBEE) += firebee.o
 
diff --git a/arch/m68knommu/platform/54xx/firebee.c b/arch/m68knommu/platform/54xx/firebee.c
new file mode 100644
index 000000000000..46d50534f981
--- /dev/null
+++ b/arch/m68knommu/platform/54xx/firebee.c
@@ -0,0 +1,86 @@
+/***************************************************************************/
+
+/*
+ *	firebee.c -- extra startup code support for the FireBee boards
+ *
+ *	Copyright (C) 2011, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+/***************************************************************************/
+
+/*
+ *	8MB of NOR flash fitted to the FireBee board.
+ */
+#define	FLASH_PHYS_ADDR		0xe0000000	/* Physical address of flash */
+#define	FLASH_PHYS_SIZE		0x00800000	/* Size of flash */
+
+#define	PART_BOOT_START		0x00000000	/* Start at bottom of flash */
+#define	PART_BOOT_SIZE		0x00040000	/* 256k in size */
+#define	PART_IMAGE_START	0x00040000	/* Start after boot loader */
+#define	PART_IMAGE_SIZE		0x006c0000	/* Most of flash */
+#define	PART_FPGA_START		0x00700000	/* Start at offset 7MB */
+#define	PART_FPGA_SIZE		0x00100000	/* 1MB in size */
+
+static struct mtd_partition firebee_flash_parts[] = {
+	{
+		.name	= "dBUG",
+		.offset	= PART_BOOT_START,
+		.size	= PART_BOOT_SIZE,
+	},
+	{
+		.name	= "FPGA",
+		.offset	= PART_FPGA_START,
+		.size	= PART_FPGA_SIZE,
+	},
+	{
+		.name	= "image",
+		.offset	= PART_IMAGE_START,
+		.size	= PART_IMAGE_SIZE,
+	},
+};
+
+static struct physmap_flash_data firebee_flash_data = {
+	.width		= 2,
+	.nr_parts	= ARRAY_SIZE(firebee_flash_parts),
+	.parts		= firebee_flash_parts,
+};
+
+static struct resource firebee_flash_resource = {
+	.start		= FLASH_PHYS_ADDR,
+	.end		= FLASH_PHYS_ADDR + FLASH_PHYS_SIZE,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device firebee_flash = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data = &firebee_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &firebee_flash_resource,
+};
+
+/***************************************************************************/
+
+static int __init init_firebee(void)
+{
+	platform_device_register(&firebee_flash);
+	return 0;
+}
+
+arch_initcall(init_firebee);
+
+/***************************************************************************/
-- 
cgit v1.2.3


From 49bc6deace5a0a774678212097474b27b27e44fb Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Mon, 7 Mar 2011 17:21:43 +1000
Subject: m68knommu: limit interrupts supported by ColdFire intc-2 driver

The intc-2 interrupt controller on some ColdFire CPUs has a set range of
interrupts its supports (64 through 128 or 192 depending on model). We
shouldn't be setting this handler for every possible interrupt from 0 to
255. Set more appropriate limits, and this means we can drop the interrupt
number check in the mask and unmask routines.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/coldfire/intc-2.c | 58 +++++++++++++------------------
 1 file changed, 25 insertions(+), 33 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index ec869c8e8890..4d172a7a6fbc 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -45,54 +45,46 @@ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
 
 static void intc_irq_mask(struct irq_data *d)
 {
-	unsigned int irq = d->irq;
+	unsigned int irq = d->irq - MCFINT_VECBASE;
+	unsigned long imraddr;
+	u32 val, imrbit;
 
-	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
-		unsigned long imraddr;
-		u32 val, imrbit;
-
-		irq -= MCFINT_VECBASE;
 #ifdef MCFICM_INTC1
-		imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+	imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
 #else
-		imraddr = MCFICM_INTC0;
+	imraddr = MCFICM_INTC0;
 #endif
-		imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
-		imrbit = 0x1 << (irq & 0x1f);
+	imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
+	imrbit = 0x1 << (irq & 0x1f);
 
-		val = __raw_readl(imraddr);
-		__raw_writel(val | imrbit, imraddr);
-	}
+	val = __raw_readl(imraddr);
+	__raw_writel(val | imrbit, imraddr);
 }
 
 static void intc_irq_unmask(struct irq_data *d)
 {
-	unsigned int irq = d->irq;
+	unsigned int irq = d->irq - MCFINT_VECBASE;
+	unsigned long intaddr, imraddr, icraddr;
+	u32 val, imrbit;
 
-	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
-		unsigned long intaddr, imraddr, icraddr;
-		u32 val, imrbit;
-
-		irq -= MCFINT_VECBASE;
 #ifdef MCFICM_INTC1
-		intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+	intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
 #else
-		intaddr = MCFICM_INTC0;
+	intaddr = MCFICM_INTC0;
 #endif
-		imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
-		icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
-		imrbit = 0x1 << (irq & 0x1f);
+	imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
+	icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
+	imrbit = 0x1 << (irq & 0x1f);
 
-		/* Don't set the "maskall" bit! */
-		if ((irq & 0x20) == 0)
-			imrbit |= 0x1;
+	/* Don't set the "maskall" bit! */
+	if ((irq & 0x20) == 0)
+		imrbit |= 0x1;
 
-		if (__raw_readb(icraddr) == 0)
-			__raw_writeb(intc_intpri--, icraddr);
+	if (__raw_readb(icraddr) == 0)
+		__raw_writeb(intc_intpri--, icraddr);
 
-		val = __raw_readl(imraddr);
-		__raw_writel(val & ~imrbit, imraddr);
-	}
+	val = __raw_readl(imraddr);
+	__raw_writel(val & ~imrbit, imraddr);
 }
 
 static int intc_irq_set_type(struct irq_data *d, unsigned int type)
@@ -119,7 +111,7 @@ void __init init_IRQ(void)
 	__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
 #endif
 
-	for (irq = 0; (irq < NR_IRQS); irq++) {
+	for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
 		set_irq_chip(irq, &intc_irq_chip);
 		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
 		set_irq_handler(irq, handle_level_irq);
-- 
cgit v1.2.3


From 6d0f33fa80ed530168161fd2f226a3e5cf27cf81 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Mon, 7 Mar 2011 17:42:28 +1000
Subject: m68knommu: move some init code out of unmask routine for ColdFire
 intc-2

Use a proper irq_startup() routine to intialize the interrupt priority
and level register in the ColdFire intc-2 controller code. We shouldn't
be checking if the priority/level has been set on every unmask operation.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/coldfire/intc-2.c | 47 +++++++++++++++++++++----------
 1 file changed, 32 insertions(+), 15 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 4d172a7a6fbc..66d4e47dd8d0 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -30,13 +30,6 @@
 #define MCFSIM_ICR_LEVEL(l)	((l)<<3)	/* Level l intr */
 #define MCFSIM_ICR_PRI(p)	(p)		/* Priority p intr */
 
-/*
- *	Each vector needs a unique priority and level associated with it.
- *	We don't really care so much what they are, we don't rely on the
- *	traditional priority interrupt scheme of the m68k/ColdFire.
- */
-static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
-
 #ifdef MCFICM_INTC1
 #define NR_VECS	128
 #else
@@ -64,25 +57,21 @@ static void intc_irq_mask(struct irq_data *d)
 static void intc_irq_unmask(struct irq_data *d)
 {
 	unsigned int irq = d->irq - MCFINT_VECBASE;
-	unsigned long intaddr, imraddr, icraddr;
+	unsigned long imraddr;
 	u32 val, imrbit;
 
 #ifdef MCFICM_INTC1
-	intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+	imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
 #else
-	intaddr = MCFICM_INTC0;
+	imraddr = MCFICM_INTC0;
 #endif
-	imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
-	icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
+	imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
 	imrbit = 0x1 << (irq & 0x1f);
 
 	/* Don't set the "maskall" bit! */
 	if ((irq & 0x20) == 0)
 		imrbit |= 0x1;
 
-	if (__raw_readb(icraddr) == 0)
-		__raw_writeb(intc_intpri--, icraddr);
-
 	val = __raw_readl(imraddr);
 	__raw_writel(val & ~imrbit, imraddr);
 }
@@ -92,8 +81,36 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
 	return 0;
 }
 
+/*
+ *	Each vector needs a unique priority and level associated with it.
+ *	We don't really care so much what they are, we don't rely on the
+ *	traditional priority interrupt scheme of the m68k/ColdFire. This
+ *	only needs to be set once for an interrupt, and we will never change
+ *	these values once we have set them.
+ */
+static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
+
+static unsigned int intc_irq_startup(struct irq_data *d)
+{
+	unsigned int irq = d->irq - MCFINT_VECBASE;
+	unsigned long icraddr;
+
+#ifdef MCFICM_INTC1
+	icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
+#else
+	icraddr = MCFICM_INTC0;
+#endif
+	icraddr += MCFINTC_ICR0 + (irq & 0x3f);
+	if (__raw_readb(icraddr) == 0)
+		__raw_writeb(intc_intpri--, icraddr);
+
+	intc_irq_unmask(d);
+	return 0;
+}
+
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
+	.irq_startup	= intc_irq_startup,
 	.irq_mask	= intc_irq_mask,
 	.irq_unmask	= intc_irq_unmask,
 	.irq_set_type	= intc_irq_set_type,
-- 
cgit v1.2.3


From 745c061f98720e7be201dd2d2277e524ecf45d1c Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Mon, 7 Mar 2011 23:00:04 +1000
Subject: m68knommu: limit interrupts supported by ColdFire intc-simr driver

The intc-simr interrupt controller on some ColdFire CPUs has a set range of
interrupts its supports (64 through 128 or 192 depending on model). We
shouldn't be setting this handler for every possible interrupt from 0 to
255. Set more appropriate limits, and this means we can drop the interrupt
number check in the mask and unmask routines.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/coldfire/intc-simr.c | 47 ++++++++++++++--------------
 1 file changed, 24 insertions(+), 23 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 69a3b679730b..8876f434c125 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -20,40 +20,40 @@
 #include <asm/mcfsim.h>
 #include <asm/traps.h>
 
+/*
+ *	There maybe one or two interrupt control units, each has 64
+ *	interrupts. If there is no second unit then MCFINTC1_* defines
+ *	will be 0 (and code for them optimized away).
+ */
+
 static void intc_irq_mask(struct irq_data *d)
 {
-	unsigned int irq = d->irq;
+	unsigned int irq = d->irq - MCFINT_VECBASE;
 
-	if (irq >= MCFINT_VECBASE) {
-		if (irq < MCFINT_VECBASE + 64)
-			__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
-		else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
-			__raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
-	}
+	if (MCFINTC1_SIMR && (irq > 64))
+		__raw_writeb(irq - 64, MCFINTC1_SIMR);
+	else
+		__raw_writeb(irq, MCFINTC0_SIMR);
 }
 
 static void intc_irq_unmask(struct irq_data *d)
 {
-	unsigned int irq = d->irq;
+	unsigned int irq = d->irq - MCFINT_VECBASE;
 
-	if (irq >= MCFINT_VECBASE) {
-		if (irq < MCFINT_VECBASE + 64)
-			__raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
-		else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
-			__raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
-	}
+	if (MCFINTC1_CIMR && (irq > 64))
+		__raw_writeb(irq - 64, MCFINTC1_CIMR);
+	else
+		__raw_writeb(irq, MCFINTC0_CIMR);
 }
 
 static int intc_irq_set_type(struct irq_data *d, unsigned int type)
 {
-	unsigned int irq = d->irq;
+	unsigned int irq = d->irq - MCFINT_VECBASE;
 
-	if (irq >= MCFINT_VECBASE) {
-		if (irq < MCFINT_VECBASE + 64)
-			__raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
-		else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
-			__raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
-	}
+	if (MCFINTC1_ICR0 && (irq > 64))
+		__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
+	else
+		__raw_writeb(5, MCFINTC0_ICR0 + irq);
 	return 0;
 }
 
@@ -66,7 +66,7 @@ static struct irq_chip intc_irq_chip = {
 
 void __init init_IRQ(void)
 {
-	int irq;
+	int irq, eirq;
 
 	init_vectors();
 
@@ -75,7 +75,8 @@ void __init init_IRQ(void)
 	if (MCFINTC1_SIMR)
 		__raw_writeb(0xff, MCFINTC1_SIMR);
 
-	for (irq = 0; (irq < NR_IRQS); irq++) {
+	eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
+	for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
 		set_irq_chip(irq, &intc_irq_chip);
 		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
 		set_irq_handler(irq, handle_level_irq);
-- 
cgit v1.2.3


From 62b323e263eb180a06daa4422ae12934024f4b5e Mon Sep 17 00:00:00 2001
From: Alexander Kurz <linux@kbdbabel.org>
Date: Sun, 20 Feb 2011 22:45:33 +0100
Subject: m68knommu: fixing compiler warnings

Signed-off-by: Alexander Kurz <linux@kbdbabel.org>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/528x/gpio.c | 210 ++++++++++++++++++------------------
 1 file changed, 105 insertions(+), 105 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68knommu/platform/528x/gpio.c
index eedaf0adbcd7..526db665d87e 100644
--- a/arch/m68knommu/platform/528x/gpio.c
+++ b/arch/m68knommu/platform/528x/gpio.c
@@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 1,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFEPORT_EPDDR,
-		.podr				= MCFEPORT_EPDR,
-		.ppdr				= MCFEPORT_EPPDR,
+		.pddr				= (void __iomem *)MCFEPORT_EPDDR,
+		.podr				= (void __iomem *)MCFEPORT_EPDR,
+		.ppdr				= (void __iomem *)MCFEPORT_EPPDR,
 	},
 	{
 		.gpio_chip			= {
@@ -49,9 +49,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 8,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPTA_GPTDDR,
-		.podr				= MCFGPTA_GPTPORT,
-		.ppdr				= MCFGPTB_GPTPORT,
+		.pddr				= (void __iomem *)MCFGPTA_GPTDDR,
+		.podr				= (void __iomem *)MCFGPTA_GPTPORT,
+		.ppdr				= (void __iomem *)MCFGPTB_GPTPORT,
 	},
 	{
 		.gpio_chip			= {
@@ -65,9 +65,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 16,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPTB_GPTDDR,
-		.podr				= MCFGPTB_GPTPORT,
-		.ppdr				= MCFGPTB_GPTPORT,
+		.pddr				= (void __iomem *)MCFGPTB_GPTDDR,
+		.podr				= (void __iomem *)MCFGPTB_GPTPORT,
+		.ppdr				= (void __iomem *)MCFGPTB_GPTPORT,
 	},
 	{
 		.gpio_chip			= {
@@ -81,9 +81,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 24,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFQADC_DDRQA,
-		.podr				= MCFQADC_PORTQA,
-		.ppdr				= MCFQADC_PORTQA,
+		.pddr				= (void __iomem *)MCFQADC_DDRQA,
+		.podr				= (void __iomem *)MCFQADC_PORTQA,
+		.ppdr				= (void __iomem *)MCFQADC_PORTQA,
 	},
 	{
 		.gpio_chip			= {
@@ -97,9 +97,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFQADC_DDRQB,
-		.podr				= MCFQADC_PORTQB,
-		.ppdr				= MCFQADC_PORTQB,
+		.pddr				= (void __iomem *)MCFQADC_DDRQB,
+		.podr				= (void __iomem *)MCFQADC_PORTQB,
+		.ppdr				= (void __iomem *)MCFQADC_PORTQB,
 	},
 	{
 		.gpio_chip			= {
@@ -113,11 +113,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 40,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRA,
-		.podr				= MCFGPIO_PORTA,
-		.ppdr				= MCFGPIO_PORTAP,
-		.setr				= MCFGPIO_SETA,
-		.clrr				= MCFGPIO_CLRA,
+		.pddr				= (void __iomem *)MCFGPIO_DDRA,
+		.podr				= (void __iomem *)MCFGPIO_PORTA,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTAP,
+		.setr				= (void __iomem *)MCFGPIO_SETA,
+		.clrr				= (void __iomem *)MCFGPIO_CLRA,
 	},
 	{
 		.gpio_chip			= {
@@ -131,11 +131,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 48,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRB,
-		.podr				= MCFGPIO_PORTB,
-		.ppdr				= MCFGPIO_PORTBP,
-		.setr				= MCFGPIO_SETB,
-		.clrr				= MCFGPIO_CLRB,
+		.pddr				= (void __iomem *)MCFGPIO_DDRB,
+		.podr				= (void __iomem *)MCFGPIO_PORTB,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTBP,
+		.setr				= (void __iomem *)MCFGPIO_SETB,
+		.clrr				= (void __iomem *)MCFGPIO_CLRB,
 	},
 	{
 		.gpio_chip			= {
@@ -149,11 +149,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 56,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRC,
-		.podr				= MCFGPIO_PORTC,
-		.ppdr				= MCFGPIO_PORTCP,
-		.setr				= MCFGPIO_SETC,
-		.clrr				= MCFGPIO_CLRC,
+		.pddr				= (void __iomem *)MCFGPIO_DDRC,
+		.podr				= (void __iomem *)MCFGPIO_PORTC,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTCP,
+		.setr				= (void __iomem *)MCFGPIO_SETC,
+		.clrr				= (void __iomem *)MCFGPIO_CLRC,
 	},
 	{
 		.gpio_chip			= {
@@ -167,11 +167,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 64,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRD,
-		.podr				= MCFGPIO_PORTD,
-		.ppdr				= MCFGPIO_PORTDP,
-		.setr				= MCFGPIO_SETD,
-		.clrr				= MCFGPIO_CLRD,
+		.pddr				= (void __iomem *)MCFGPIO_DDRD,
+		.podr				= (void __iomem *)MCFGPIO_PORTD,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTDP,
+		.setr				= (void __iomem *)MCFGPIO_SETD,
+		.clrr				= (void __iomem *)MCFGPIO_CLRD,
 	},
 	{
 		.gpio_chip			= {
@@ -185,11 +185,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 72,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRE,
-		.podr				= MCFGPIO_PORTE,
-		.ppdr				= MCFGPIO_PORTEP,
-		.setr				= MCFGPIO_SETE,
-		.clrr				= MCFGPIO_CLRE,
+		.pddr				= (void __iomem *)MCFGPIO_DDRE,
+		.podr				= (void __iomem *)MCFGPIO_PORTE,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTEP,
+		.setr				= (void __iomem *)MCFGPIO_SETE,
+		.clrr				= (void __iomem *)MCFGPIO_CLRE,
 	},
 	{
 		.gpio_chip			= {
@@ -203,11 +203,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 80,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRF,
-		.podr				= MCFGPIO_PORTF,
-		.ppdr				= MCFGPIO_PORTFP,
-		.setr				= MCFGPIO_SETF,
-		.clrr				= MCFGPIO_CLRF,
+		.pddr				= (void __iomem *)MCFGPIO_DDRF,
+		.podr				= (void __iomem *)MCFGPIO_PORTF,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTFP,
+		.setr				= (void __iomem *)MCFGPIO_SETF,
+		.clrr				= (void __iomem *)MCFGPIO_CLRF,
 	},
 	{
 		.gpio_chip			= {
@@ -221,11 +221,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 88,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRG,
-		.podr				= MCFGPIO_PORTG,
-		.ppdr				= MCFGPIO_PORTGP,
-		.setr				= MCFGPIO_SETG,
-		.clrr				= MCFGPIO_CLRG,
+		.pddr				= (void __iomem *)MCFGPIO_DDRG,
+		.podr				= (void __iomem *)MCFGPIO_PORTG,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTGP,
+		.setr				= (void __iomem *)MCFGPIO_SETG,
+		.clrr				= (void __iomem *)MCFGPIO_CLRG,
 	},
 	{
 		.gpio_chip			= {
@@ -239,11 +239,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 96,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRH,
-		.podr				= MCFGPIO_PORTH,
-		.ppdr				= MCFGPIO_PORTHP,
-		.setr				= MCFGPIO_SETH,
-		.clrr				= MCFGPIO_CLRH,
+		.pddr				= (void __iomem *)MCFGPIO_DDRH,
+		.podr				= (void __iomem *)MCFGPIO_PORTH,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTHP,
+		.setr				= (void __iomem *)MCFGPIO_SETH,
+		.clrr				= (void __iomem *)MCFGPIO_CLRH,
 	},
 	{
 		.gpio_chip			= {
@@ -257,11 +257,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 104,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRJ,
-		.podr				= MCFGPIO_PORTJ,
-		.ppdr				= MCFGPIO_PORTJP,
-		.setr				= MCFGPIO_SETJ,
-		.clrr				= MCFGPIO_CLRJ,
+		.pddr				= (void __iomem *)MCFGPIO_DDRJ,
+		.podr				= (void __iomem *)MCFGPIO_PORTJ,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTJP,
+		.setr				= (void __iomem *)MCFGPIO_SETJ,
+		.clrr				= (void __iomem *)MCFGPIO_CLRJ,
 	},
 	{
 		.gpio_chip			= {
@@ -275,11 +275,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 112,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDRDD,
-		.podr				= MCFGPIO_PORTDD,
-		.ppdr				= MCFGPIO_PORTDDP,
-		.setr				= MCFGPIO_SETDD,
-		.clrr				= MCFGPIO_CLRDD,
+		.pddr				= (void __iomem *)MCFGPIO_DDRDD,
+		.podr				= (void __iomem *)MCFGPIO_PORTDD,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTDDP,
+		.setr				= (void __iomem *)MCFGPIO_SETDD,
+		.clrr				= (void __iomem *)MCFGPIO_CLRDD,
 	},
 	{
 		.gpio_chip			= {
@@ -293,11 +293,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 120,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDREH,
-		.podr				= MCFGPIO_PORTEH,
-		.ppdr				= MCFGPIO_PORTEHP,
-		.setr				= MCFGPIO_SETEH,
-		.clrr				= MCFGPIO_CLREH,
+		.pddr				= (void __iomem *)MCFGPIO_DDREH,
+		.podr				= (void __iomem *)MCFGPIO_PORTEH,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTEHP,
+		.setr				= (void __iomem *)MCFGPIO_SETEH,
+		.clrr				= (void __iomem *)MCFGPIO_CLREH,
 	},
 	{
 		.gpio_chip			= {
@@ -311,11 +311,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 128,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_DDREL,
-		.podr				= MCFGPIO_PORTEL,
-		.ppdr				= MCFGPIO_PORTELP,
-		.setr				= MCFGPIO_SETEL,
-		.clrr				= MCFGPIO_CLREL,
+		.pddr				= (void __iomem *)MCFGPIO_DDREL,
+		.podr				= (void __iomem *)MCFGPIO_PORTEL,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTELP,
+		.setr				= (void __iomem *)MCFGPIO_SETEL,
+		.clrr				= (void __iomem *)MCFGPIO_CLREL,
 	},
 	{
 		.gpio_chip			= {
@@ -329,11 +329,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 136,
 			.ngpio			= 6,
 		},
-		.pddr				= MCFGPIO_DDRAS,
-		.podr				= MCFGPIO_PORTAS,
-		.ppdr				= MCFGPIO_PORTASP,
-		.setr				= MCFGPIO_SETAS,
-		.clrr				= MCFGPIO_CLRAS,
+		.pddr				= (void __iomem *)MCFGPIO_DDRAS,
+		.podr				= (void __iomem *)MCFGPIO_PORTAS,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTASP,
+		.setr				= (void __iomem *)MCFGPIO_SETAS,
+		.clrr				= (void __iomem *)MCFGPIO_CLRAS,
 	},
 	{
 		.gpio_chip			= {
@@ -347,11 +347,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 144,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFGPIO_DDRQS,
-		.podr				= MCFGPIO_PORTQS,
-		.ppdr				= MCFGPIO_PORTQSP,
-		.setr				= MCFGPIO_SETQS,
-		.clrr				= MCFGPIO_CLRQS,
+		.pddr				= (void __iomem *)MCFGPIO_DDRQS,
+		.podr				= (void __iomem *)MCFGPIO_PORTQS,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTQSP,
+		.setr				= (void __iomem *)MCFGPIO_SETQS,
+		.clrr				= (void __iomem *)MCFGPIO_CLRQS,
 	},
 	{
 		.gpio_chip			= {
@@ -365,11 +365,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 152,
 			.ngpio			= 6,
 		},
-		.pddr				= MCFGPIO_DDRSD,
-		.podr				= MCFGPIO_PORTSD,
-		.ppdr				= MCFGPIO_PORTSDP,
-		.setr				= MCFGPIO_SETSD,
-		.clrr				= MCFGPIO_CLRSD,
+		.pddr				= (void __iomem *)MCFGPIO_DDRSD,
+		.podr				= (void __iomem *)MCFGPIO_PORTSD,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTSDP,
+		.setr				= (void __iomem *)MCFGPIO_SETSD,
+		.clrr				= (void __iomem *)MCFGPIO_CLRSD,
 	},
 	{
 		.gpio_chip			= {
@@ -383,11 +383,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 160,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_DDRTC,
-		.podr				= MCFGPIO_PORTTC,
-		.ppdr				= MCFGPIO_PORTTCP,
-		.setr				= MCFGPIO_SETTC,
-		.clrr				= MCFGPIO_CLRTC,
+		.pddr				= (void __iomem *)MCFGPIO_DDRTC,
+		.podr				= (void __iomem *)MCFGPIO_PORTTC,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTTCP,
+		.setr				= (void __iomem *)MCFGPIO_SETTC,
+		.clrr				= (void __iomem *)MCFGPIO_CLRTC,
 	},
 	{
 		.gpio_chip			= {
@@ -401,11 +401,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 168,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_DDRTD,
-		.podr				= MCFGPIO_PORTTD,
-		.ppdr				= MCFGPIO_PORTTDP,
-		.setr				= MCFGPIO_SETTD,
-		.clrr				= MCFGPIO_CLRTD,
+		.pddr				= (void __iomem *)MCFGPIO_DDRTD,
+		.podr				= (void __iomem *)MCFGPIO_PORTTD,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTTDP,
+		.setr				= (void __iomem *)MCFGPIO_SETTD,
+		.clrr				= (void __iomem *)MCFGPIO_CLRTD,
 	},
 	{
 		.gpio_chip			= {
@@ -419,11 +419,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 176,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_DDRUA,
-		.podr				= MCFGPIO_PORTUA,
-		.ppdr				= MCFGPIO_PORTUAP,
-		.setr				= MCFGPIO_SETUA,
-		.clrr				= MCFGPIO_CLRUA,
+		.pddr				= (void __iomem *)MCFGPIO_DDRUA,
+		.podr				= (void __iomem *)MCFGPIO_PORTUA,
+		.ppdr				= (void __iomem *)MCFGPIO_PORTUAP,
+		.setr				= (void __iomem *)MCFGPIO_SETUA,
+		.clrr				= (void __iomem *)MCFGPIO_CLRUA,
 	},
 };
 
-- 
cgit v1.2.3


From 0bb724af29fa56c0be94a4abf2ed33dbd414ddc0 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 08:53:30 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 5206 targets

Fix these compiler warnings:

arch/m68knommu/platform/5206/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5206/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5206/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5206/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68knommu/platform/5206/gpio.c
index 60f779ce1651..b9ab4a120f28 100644
--- a/arch/m68knommu/platform/5206/gpio.c
+++ b/arch/m68knommu/platform/5206/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFSIM_PADDR,
-		.podr				= MCFSIM_PADAT,
-		.ppdr				= MCFSIM_PADAT,
+		.pddr				= (void __iomem *) MCFSIM_PADDR,
+		.podr				= (void __iomem *) MCFSIM_PADAT,
+		.ppdr				= (void __iomem *) MCFSIM_PADAT,
 	},
 };
 
-- 
cgit v1.2.3


From d5365ca5aa65a4988a8c713f0f902f367ae7cdb3 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 08:55:53 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 5206e targets

Fix these compiler warnings:

arch/m68knommu/platform/5206e/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast  CC      kernel/panic.o
arch/m68knommu/platform/5206e/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5206e/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5206e/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68knommu/platform/5206e/gpio.c
index 60f779ce1651..b9ab4a120f28 100644
--- a/arch/m68knommu/platform/5206e/gpio.c
+++ b/arch/m68knommu/platform/5206e/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFSIM_PADDR,
-		.podr				= MCFSIM_PADAT,
-		.ppdr				= MCFSIM_PADAT,
+		.pddr				= (void __iomem *) MCFSIM_PADDR,
+		.podr				= (void __iomem *) MCFSIM_PADAT,
+		.ppdr				= (void __iomem *) MCFSIM_PADAT,
 	},
 };
 
-- 
cgit v1.2.3


From 9516de490ee2131020153df19d0588b65d938ccb Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 08:59:35 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 520x targets

Fix these compiler warnings:

rch/m68knommu/platform/520x/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/520x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/520x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/520x/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/520x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast
...

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/520x/gpio.c | 96 ++++++++++++++++++-------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68knommu/platform/520x/gpio.c
index 15b5bb62a698..d757328563d1 100644
--- a/arch/m68knommu/platform/520x/gpio.c
+++ b/arch/m68knommu/platform/520x/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFEPORT_EPDDR,
-		.podr				= MCFEPORT_EPDR,
-		.ppdr				= MCFEPORT_EPPDR,
+		.pddr				= (void __iomem *) MCFEPORT_EPDDR,
+		.podr				= (void __iomem *) MCFEPORT_EPDR,
+		.ppdr				= (void __iomem *) MCFEPORT_EPPDR,
 	},
 	{
 		.gpio_chip			= {
@@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 8,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_BUSCTL,
-		.podr				= MCFGPIO_PODR_BUSCTL,
-		.ppdr				= MCFGPIO_PPDSDR_BUSCTL,
-		.setr				= MCFGPIO_PPDSDR_BUSCTL,
-		.clrr				= MCFGPIO_PCLRR_BUSCTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BUSCTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
 	},
 	{
 		.gpio_chip			= {
@@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 16,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_BE,
-		.podr				= MCFGPIO_PODR_BE,
-		.ppdr				= MCFGPIO_PPDSDR_BE,
-		.setr				= MCFGPIO_PPDSDR_BE,
-		.clrr				= MCFGPIO_PCLRR_BE,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BE,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BE,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BE,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BE,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BE,
 	},
 	{
 		.gpio_chip			= {
@@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 25,
 			.ngpio			= 3,
 		},
-		.pddr				= MCFGPIO_PDDR_CS,
-		.podr				= MCFGPIO_PODR_CS,
-		.ppdr				= MCFGPIO_PPDSDR_CS,
-		.setr				= MCFGPIO_PPDSDR_CS,
-		.clrr				= MCFGPIO_PCLRR_CS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_CS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_CS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_CS,
 	},
 	{
 		.gpio_chip			= {
@@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_FECI2C,
-		.podr				= MCFGPIO_PODR_FECI2C,
-		.ppdr				= MCFGPIO_PPDSDR_FECI2C,
-		.setr				= MCFGPIO_PPDSDR_FECI2C,
-		.clrr				= MCFGPIO_PCLRR_FECI2C,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECI2C,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECI2C,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECI2C,
 	},
 	{
 		.gpio_chip			= {
@@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 40,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_QSPI,
-		.podr				= MCFGPIO_PODR_QSPI,
-		.ppdr				= MCFGPIO_PPDSDR_QSPI,
-		.setr				= MCFGPIO_PPDSDR_QSPI,
-		.clrr				= MCFGPIO_PCLRR_QSPI,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_QSPI,
+		.podr				= (void __iomem *) MCFGPIO_PODR_QSPI,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_QSPI,
 	},
 	{
 		.gpio_chip			= {
@@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 48,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_TIMER,
-		.podr				= MCFGPIO_PODR_TIMER,
-		.ppdr				= MCFGPIO_PPDSDR_TIMER,
-		.setr				= MCFGPIO_PPDSDR_TIMER,
-		.clrr				= MCFGPIO_PCLRR_TIMER,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_TIMER,
+		.podr				= (void __iomem *) MCFGPIO_PODR_TIMER,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_TIMER,
 	},
 	{
 		.gpio_chip			= {
@@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 56,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_UART,
-		.podr				= MCFGPIO_PODR_UART,
-		.ppdr				= MCFGPIO_PPDSDR_UART,
-		.setr				= MCFGPIO_PPDSDR_UART,
-		.clrr				= MCFGPIO_PCLRR_UART,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UART,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UART,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UART,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UART,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UART,
 	},
 	{
 		.gpio_chip			= {
@@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 64,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FECH,
-		.podr				= MCFGPIO_PODR_FECH,
-		.ppdr				= MCFGPIO_PPDSDR_FECH,
-		.setr				= MCFGPIO_PPDSDR_FECH,
-		.clrr				= MCFGPIO_PCLRR_FECH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECH,
 	},
 	{
 		.gpio_chip			= {
@@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 72,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FECL,
-		.podr				= MCFGPIO_PODR_FECL,
-		.ppdr				= MCFGPIO_PPDSDR_FECL,
-		.setr				= MCFGPIO_PPDSDR_FECL,
-		.clrr				= MCFGPIO_PCLRR_FECL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECL,
 	},
 };
 
-- 
cgit v1.2.3


From 2836827d7b47d40283424ee90aaa2f7922d4558a Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:03:47 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 523x targets

Fix these compiler warnings:

arch/m68knommu/platform/523x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/523x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/523x/gpio.c:38:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/523x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/523x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast
...

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/523x/gpio.c | 136 ++++++++++++++++++------------------
 1 file changed, 68 insertions(+), 68 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c
index a8842dc27839..327ebf142c8e 100644
--- a/arch/m68knommu/platform/523x/gpio.c
+++ b/arch/m68knommu/platform/523x/gpio.c
@@ -33,9 +33,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 1,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFEPORT_EPDDR,
-		.podr				= MCFEPORT_EPDR,
-		.ppdr				= MCFEPORT_EPPDR,
+		.pddr				= (void __iomem *) MCFEPORT_EPDDR,
+		.podr				= (void __iomem *) MCFEPORT_EPDR,
+		.ppdr				= (void __iomem *) MCFEPORT_EPPDR,
 	},
 	{
 		.gpio_chip			= {
@@ -49,11 +49,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 13,
 			.ngpio			= 3,
 		},
-		.pddr				= MCFGPIO_PDDR_ADDR,
-		.podr				= MCFGPIO_PODR_ADDR,
-		.ppdr				= MCFGPIO_PPDSDR_ADDR,
-		.setr				= MCFGPIO_PPDSDR_ADDR,
-		.clrr				= MCFGPIO_PCLRR_ADDR,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_ADDR,
+		.podr				= (void __iomem *) MCFGPIO_PODR_ADDR,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_ADDR,
 	},
 	{
 		.gpio_chip			= {
@@ -67,11 +67,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 16,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_DATAH,
-		.podr				= MCFGPIO_PODR_DATAH,
-		.ppdr				= MCFGPIO_PPDSDR_DATAH,
-		.setr				= MCFGPIO_PPDSDR_DATAH,
-		.clrr				= MCFGPIO_PCLRR_DATAH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_DATAH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_DATAH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_DATAH,
 	},
 	{
 		.gpio_chip			= {
@@ -85,11 +85,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 24,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_DATAL,
-		.podr				= MCFGPIO_PODR_DATAL,
-		.ppdr				= MCFGPIO_PPDSDR_DATAL,
-		.setr				= MCFGPIO_PPDSDR_DATAL,
-		.clrr				= MCFGPIO_PCLRR_DATAL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_DATAL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_DATAL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_DATAL,
 	},
 	{
 		.gpio_chip			= {
@@ -103,11 +103,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_BUSCTL,
-		.podr				= MCFGPIO_PODR_BUSCTL,
-		.ppdr				= MCFGPIO_PPDSDR_BUSCTL,
-		.setr				= MCFGPIO_PPDSDR_BUSCTL,
-		.clrr				= MCFGPIO_PCLRR_BUSCTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BUSCTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
 	},
 	{
 		.gpio_chip			= {
@@ -121,11 +121,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 40,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_BS,
-		.podr				= MCFGPIO_PODR_BS,
-		.ppdr				= MCFGPIO_PPDSDR_BS,
-		.setr				= MCFGPIO_PPDSDR_BS,
-		.clrr				= MCFGPIO_PCLRR_BS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BS,
 	},
 	{
 		.gpio_chip			= {
@@ -139,11 +139,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 49,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFGPIO_PDDR_CS,
-		.podr				= MCFGPIO_PODR_CS,
-		.ppdr				= MCFGPIO_PPDSDR_CS,
-		.setr				= MCFGPIO_PPDSDR_CS,
-		.clrr				= MCFGPIO_PCLRR_CS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_CS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_CS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_CS,
 	},
 	{
 		.gpio_chip			= {
@@ -157,11 +157,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 56,
 			.ngpio			= 6,
 		},
-		.pddr				= MCFGPIO_PDDR_SDRAM,
-		.podr				= MCFGPIO_PODR_SDRAM,
-		.ppdr				= MCFGPIO_PPDSDR_SDRAM,
-		.setr				= MCFGPIO_PPDSDR_SDRAM,
-		.clrr				= MCFGPIO_PCLRR_SDRAM,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_SDRAM,
+		.podr				= (void __iomem *) MCFGPIO_PODR_SDRAM,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_SDRAM,
 	},
 	{
 		.gpio_chip			= {
@@ -175,11 +175,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 64,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_FECI2C,
-		.podr				= MCFGPIO_PODR_FECI2C,
-		.ppdr				= MCFGPIO_PPDSDR_FECI2C,
-		.setr				= MCFGPIO_PPDSDR_FECI2C,
-		.clrr				= MCFGPIO_PCLRR_FECI2C,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECI2C,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECI2C,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECI2C,
 	},
 	{
 		.gpio_chip			= {
@@ -193,11 +193,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 72,
 			.ngpio			= 2,
 		},
-		.pddr				= MCFGPIO_PDDR_UARTH,
-		.podr				= MCFGPIO_PODR_UARTH,
-		.ppdr				= MCFGPIO_PPDSDR_UARTH,
-		.setr				= MCFGPIO_PPDSDR_UARTH,
-		.clrr				= MCFGPIO_PCLRR_UARTH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UARTH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UARTH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UARTH,
 	},
 	{
 		.gpio_chip			= {
@@ -211,11 +211,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 80,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_UARTL,
-		.podr				= MCFGPIO_PODR_UARTL,
-		.ppdr				= MCFGPIO_PPDSDR_UARTL,
-		.setr				= MCFGPIO_PPDSDR_UARTL,
-		.clrr				= MCFGPIO_PCLRR_UARTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UARTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UARTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UARTL,
 	},
 	{
 		.gpio_chip			= {
@@ -229,11 +229,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 88,
 			.ngpio			= 5,
 		},
-		.pddr				= MCFGPIO_PDDR_QSPI,
-		.podr				= MCFGPIO_PODR_QSPI,
-		.ppdr				= MCFGPIO_PPDSDR_QSPI,
-		.setr				= MCFGPIO_PPDSDR_QSPI,
-		.clrr				= MCFGPIO_PCLRR_QSPI,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_QSPI,
+		.podr				= (void __iomem *) MCFGPIO_PODR_QSPI,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_QSPI,
 	},
 	{
 		.gpio_chip			= {
@@ -247,11 +247,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 96,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_TIMER,
-		.podr				= MCFGPIO_PODR_TIMER,
-		.ppdr				= MCFGPIO_PPDSDR_TIMER,
-		.setr				= MCFGPIO_PPDSDR_TIMER,
-		.clrr				= MCFGPIO_PCLRR_TIMER,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_TIMER,
+		.podr				= (void __iomem *) MCFGPIO_PODR_TIMER,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_TIMER,
 	},
 	{
 		.gpio_chip			= {
@@ -265,11 +265,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 104,
 			.ngpio			= 3,
 		},
-		.pddr				= MCFGPIO_PDDR_ETPU,
-		.podr				= MCFGPIO_PODR_ETPU,
-		.ppdr				= MCFGPIO_PPDSDR_ETPU,
-		.setr				= MCFGPIO_PPDSDR_ETPU,
-		.clrr				= MCFGPIO_PCLRR_ETPU,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_ETPU,
+		.podr				= (void __iomem *) MCFGPIO_PODR_ETPU,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_ETPU,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_ETPU,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_ETPU,
 	},
 };
 
-- 
cgit v1.2.3


From 2470758ae500a08d8d0e23b6c4024341ee2be4d7 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:05:40 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 5249 targets

Fix these compiler warnings:

arch/m68knommu/platform/5249/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5249/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5249/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5249/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5249/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5249/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5249/gpio.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c
index c611eab8b3b6..2b56c6ef65bf 100644
--- a/arch/m68knommu/platform/5249/gpio.c
+++ b/arch/m68knommu/platform/5249/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 32,
 		},
-		.pddr				= MCFSIM2_GPIOENABLE,
-		.podr				= MCFSIM2_GPIOWRITE,
-		.ppdr				= MCFSIM2_GPIOREAD,
+		.pddr				= (void __iomem *) MCFSIM2_GPIOENABLE,
+		.podr				= (void __iomem *) MCFSIM2_GPIOWRITE,
+		.ppdr				= (void __iomem *) MCFSIM2_GPIOREAD,
 	},
 	{
 		.gpio_chip			= {
@@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 32,
 		},
-		.pddr				= MCFSIM2_GPIO1ENABLE,
-		.podr				= MCFSIM2_GPIO1WRITE,
-		.ppdr				= MCFSIM2_GPIO1READ,
+		.pddr				= (void __iomem *) MCFSIM2_GPIO1ENABLE,
+		.podr				= (void __iomem *) MCFSIM2_GPIO1WRITE,
+		.ppdr				= (void __iomem *) MCFSIM2_GPIO1READ,
 	},
 };
 
-- 
cgit v1.2.3


From 4d1f692f3002b580b1fd49fba74c1b7c5c123a9c Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:07:36 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 5272 targets

Fix these compiler warnings:

arch/m68knommu/platform/5272/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:67:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:68:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5272/gpio.c:69:3: warning: initialisation makes pointer from integer without a cast

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5272/gpio.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68knommu/platform/5272/gpio.c
index 459db89a89cc..57ac10a5d7f7 100644
--- a/arch/m68knommu/platform/5272/gpio.c
+++ b/arch/m68knommu/platform/5272/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 16,
 		},
-		.pddr				= MCFSIM_PADDR,
-		.podr				= MCFSIM_PADAT,
-		.ppdr				= MCFSIM_PADAT,
+		.pddr				= (void __iomem *) MCFSIM_PADDR,
+		.podr				= (void __iomem *) MCFSIM_PADAT,
+		.ppdr				= (void __iomem *) MCFSIM_PADAT,
 	},
 	{
 		.gpio_chip			= {
@@ -48,9 +48,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 16,
 			.ngpio			= 16,
 		},
-		.pddr				= MCFSIM_PBDDR,
-		.podr				= MCFSIM_PBDAT,
-		.ppdr				= MCFSIM_PBDAT,
+		.pddr				= (void __iomem *) MCFSIM_PBDDR,
+		.podr				= (void __iomem *) MCFSIM_PBDAT,
+		.ppdr				= (void __iomem *) MCFSIM_PBDAT,
 	},
 	{
 		.gpio_chip			= {
@@ -64,9 +64,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 16,
 		},
-		.pddr				= MCFSIM_PCDDR,
-		.podr				= MCFSIM_PCDAT,
-		.ppdr				= MCFSIM_PCDAT,
+		.pddr				= (void __iomem *) MCFSIM_PCDDR,
+		.podr				= (void __iomem *) MCFSIM_PCDAT,
+		.ppdr				= (void __iomem *) MCFSIM_PCDAT,
 	},
 };
 
-- 
cgit v1.2.3


From d5dca1e09497c9477a30f1b9eb847c4c22f05a26 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:13:16 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 527x targets

Fix these compiler warnings:

arch/m68knommu/platform/527x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/527x/gpio.c:38:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/527x/gpio.c:39:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/527x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/527x/gpio.c:54:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/527x/gpio.c:55:3: warning: initialisation makes pointer from integer without a cast
...

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/527x/gpio.c | 312 ++++++++++++++++++------------------
 1 file changed, 156 insertions(+), 156 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68knommu/platform/527x/gpio.c
index 0b56e19db0f8..205da0aa0f2d 100644
--- a/arch/m68knommu/platform/527x/gpio.c
+++ b/arch/m68knommu/platform/527x/gpio.c
@@ -34,9 +34,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 1,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFEPORT_EPDDR,
-		.podr				= MCFEPORT_EPDR,
-		.ppdr				= MCFEPORT_EPPDR,
+		.pddr				= (void __iomem *) MCFEPORT_EPDDR,
+		.podr				= (void __iomem *) MCFEPORT_EPDR,
+		.ppdr				= (void __iomem *) MCFEPORT_EPPDR,
 	},
 	{
 		.gpio_chip			= {
@@ -50,11 +50,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 13,
 			.ngpio			= 3,
 		},
-		.pddr				= MCFGPIO_PDDR_ADDR,
-		.podr				= MCFGPIO_PODR_ADDR,
-		.ppdr				= MCFGPIO_PPDSDR_ADDR,
-		.setr				= MCFGPIO_PPDSDR_ADDR,
-		.clrr				= MCFGPIO_PCLRR_ADDR,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_ADDR,
+		.podr				= (void __iomem *) MCFGPIO_PODR_ADDR,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_ADDR,
 	},
 	{
 		.gpio_chip			= {
@@ -68,11 +68,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 16,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_DATAH,
-		.podr				= MCFGPIO_PODR_DATAH,
-		.ppdr				= MCFGPIO_PPDSDR_DATAH,
-		.setr				= MCFGPIO_PPDSDR_DATAH,
-		.clrr				= MCFGPIO_PCLRR_DATAH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_DATAH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_DATAH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_DATAH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_DATAH,
 	},
 	{
 		.gpio_chip			= {
@@ -86,11 +86,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 24,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_DATAL,
-		.podr				= MCFGPIO_PODR_DATAL,
-		.ppdr				= MCFGPIO_PPDSDR_DATAL,
-		.setr				= MCFGPIO_PPDSDR_DATAL,
-		.clrr				= MCFGPIO_PCLRR_DATAL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_DATAL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_DATAL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_DATAL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_DATAL,
 	},
 	{
 		.gpio_chip			= {
@@ -104,11 +104,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_BUSCTL,
-		.podr				= MCFGPIO_PODR_BUSCTL,
-		.ppdr				= MCFGPIO_PPDSDR_BUSCTL,
-		.setr				= MCFGPIO_PPDSDR_BUSCTL,
-		.clrr				= MCFGPIO_PCLRR_BUSCTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BUSCTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
 	},
 	{
 		.gpio_chip			= {
@@ -122,11 +122,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 40,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_BS,
-		.podr				= MCFGPIO_PODR_BS,
-		.ppdr				= MCFGPIO_PPDSDR_BS,
-		.setr				= MCFGPIO_PPDSDR_BS,
-		.clrr				= MCFGPIO_PCLRR_BS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BS,
 	},
 	{
 		.gpio_chip			= {
@@ -140,11 +140,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 49,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFGPIO_PDDR_CS,
-		.podr				= MCFGPIO_PODR_CS,
-		.ppdr				= MCFGPIO_PPDSDR_CS,
-		.setr				= MCFGPIO_PPDSDR_CS,
-		.clrr				= MCFGPIO_PCLRR_CS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_CS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_CS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_CS,
 	},
 	{
 		.gpio_chip			= {
@@ -158,11 +158,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 56,
 			.ngpio			= 6,
 		},
-		.pddr				= MCFGPIO_PDDR_SDRAM,
-		.podr				= MCFGPIO_PODR_SDRAM,
-		.ppdr				= MCFGPIO_PPDSDR_SDRAM,
-		.setr				= MCFGPIO_PPDSDR_SDRAM,
-		.clrr				= MCFGPIO_PCLRR_SDRAM,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_SDRAM,
+		.podr				= (void __iomem *) MCFGPIO_PODR_SDRAM,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_SDRAM,
 	},
 	{
 		.gpio_chip			= {
@@ -176,11 +176,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 64,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_FECI2C,
-		.podr				= MCFGPIO_PODR_FECI2C,
-		.ppdr				= MCFGPIO_PPDSDR_FECI2C,
-		.setr				= MCFGPIO_PPDSDR_FECI2C,
-		.clrr				= MCFGPIO_PCLRR_FECI2C,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECI2C,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECI2C,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECI2C,
 	},
 	{
 		.gpio_chip			= {
@@ -194,11 +194,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 72,
 			.ngpio			= 2,
 		},
-		.pddr				= MCFGPIO_PDDR_UARTH,
-		.podr				= MCFGPIO_PODR_UARTH,
-		.ppdr				= MCFGPIO_PPDSDR_UARTH,
-		.setr				= MCFGPIO_PPDSDR_UARTH,
-		.clrr				= MCFGPIO_PCLRR_UARTH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UARTH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UARTH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UARTH,
 	},
 	{
 		.gpio_chip			= {
@@ -212,11 +212,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 80,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_UARTL,
-		.podr				= MCFGPIO_PODR_UARTL,
-		.ppdr				= MCFGPIO_PPDSDR_UARTL,
-		.setr				= MCFGPIO_PPDSDR_UARTL,
-		.clrr				= MCFGPIO_PCLRR_UARTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UARTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UARTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UARTL,
 	},
 	{
 		.gpio_chip			= {
@@ -230,11 +230,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 88,
 			.ngpio			= 5,
 		},
-		.pddr				= MCFGPIO_PDDR_QSPI,
-		.podr				= MCFGPIO_PODR_QSPI,
-		.ppdr				= MCFGPIO_PPDSDR_QSPI,
-		.setr				= MCFGPIO_PPDSDR_QSPI,
-		.clrr				= MCFGPIO_PCLRR_QSPI,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_QSPI,
+		.podr				= (void __iomem *) MCFGPIO_PODR_QSPI,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_QSPI,
 	},
 	{
 		.gpio_chip			= {
@@ -248,11 +248,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 96,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_TIMER,
-		.podr				= MCFGPIO_PODR_TIMER,
-		.ppdr				= MCFGPIO_PPDSDR_TIMER,
-		.setr				= MCFGPIO_PPDSDR_TIMER,
-		.clrr				= MCFGPIO_PCLRR_TIMER,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_TIMER,
+		.podr				= (void __iomem *) MCFGPIO_PODR_TIMER,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_TIMER,
 	},
 #elif defined(CONFIG_M5275)
 	{
@@ -267,9 +267,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 1,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFEPORT_EPDDR,
-		.podr				= MCFEPORT_EPDR,
-		.ppdr				= MCFEPORT_EPPDR,
+		.pddr				= (void __iomem *) MCFEPORT_EPDDR,
+		.podr				= (void __iomem *) MCFEPORT_EPDR,
+		.ppdr				= (void __iomem *) MCFEPORT_EPPDR,
 	},
 	{
 		.gpio_chip			= {
@@ -283,11 +283,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 8,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_BUSCTL,
-		.podr				= MCFGPIO_PODR_BUSCTL,
-		.ppdr				= MCFGPIO_PPDSDR_BUSCTL,
-		.setr				= MCFGPIO_PPDSDR_BUSCTL,
-		.clrr				= MCFGPIO_PCLRR_BUSCTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BUSCTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
 	},
 	{
 		.gpio_chip			= {
@@ -301,11 +301,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 21,
 			.ngpio			= 3,
 		},
-		.pddr				= MCFGPIO_PDDR_ADDR,
-		.podr				= MCFGPIO_PODR_ADDR,
-		.ppdr				= MCFGPIO_PPDSDR_ADDR,
-		.setr				= MCFGPIO_PPDSDR_ADDR,
-		.clrr				= MCFGPIO_PCLRR_ADDR,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_ADDR,
+		.podr				= (void __iomem *) MCFGPIO_PODR_ADDR,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_ADDR,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_ADDR,
 	},
 	{
 		.gpio_chip			= {
@@ -319,11 +319,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 25,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFGPIO_PDDR_CS,
-		.podr				= MCFGPIO_PODR_CS,
-		.ppdr				= MCFGPIO_PPDSDR_CS,
-		.setr				= MCFGPIO_PPDSDR_CS,
-		.clrr				= MCFGPIO_PCLRR_CS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_CS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_CS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_CS,
 	},
 	{
 		.gpio_chip			= {
@@ -337,11 +337,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FEC0H,
-		.podr				= MCFGPIO_PODR_FEC0H,
-		.ppdr				= MCFGPIO_PPDSDR_FEC0H,
-		.setr				= MCFGPIO_PPDSDR_FEC0H,
-		.clrr				= MCFGPIO_PCLRR_FEC0H,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FEC0H,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FEC0H,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FEC0H,
 	},
 	{
 		.gpio_chip			= {
@@ -355,11 +355,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 40,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FEC0L,
-		.podr				= MCFGPIO_PODR_FEC0L,
-		.ppdr				= MCFGPIO_PPDSDR_FEC0L,
-		.setr				= MCFGPIO_PPDSDR_FEC0L,
-		.clrr				= MCFGPIO_PCLRR_FEC0L,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FEC0L,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FEC0L,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FEC0L,
 	},
 	{
 		.gpio_chip			= {
@@ -373,11 +373,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 48,
 			.ngpio			= 6,
 		},
-		.pddr				= MCFGPIO_PDDR_FECI2C,
-		.podr				= MCFGPIO_PODR_FECI2C,
-		.ppdr				= MCFGPIO_PPDSDR_FECI2C,
-		.setr				= MCFGPIO_PPDSDR_FECI2C,
-		.clrr				= MCFGPIO_PCLRR_FECI2C,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECI2C,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECI2C,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECI2C,
 	},
 	{
 		.gpio_chip			= {
@@ -391,11 +391,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 56,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFGPIO_PDDR_QSPI,
-		.podr				= MCFGPIO_PODR_QSPI,
-		.ppdr				= MCFGPIO_PPDSDR_QSPI,
-		.setr				= MCFGPIO_PPDSDR_QSPI,
-		.clrr				= MCFGPIO_PCLRR_QSPI,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_QSPI,
+		.podr				= (void __iomem *) MCFGPIO_PODR_QSPI,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_QSPI,
 	},
 	{
 		.gpio_chip			= {
@@ -409,11 +409,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 64,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_SDRAM,
-		.podr				= MCFGPIO_PODR_SDRAM,
-		.ppdr				= MCFGPIO_PPDSDR_SDRAM,
-		.setr				= MCFGPIO_PPDSDR_SDRAM,
-		.clrr				= MCFGPIO_PCLRR_SDRAM,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_SDRAM,
+		.podr				= (void __iomem *) MCFGPIO_PODR_SDRAM,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_SDRAM,
 	},
 	{
 		.gpio_chip			= {
@@ -427,11 +427,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 72,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_TIMERH,
-		.podr				= MCFGPIO_PODR_TIMERH,
-		.ppdr				= MCFGPIO_PPDSDR_TIMERH,
-		.setr				= MCFGPIO_PPDSDR_TIMERH,
-		.clrr				= MCFGPIO_PCLRR_TIMERH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_TIMERH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_TIMERH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_TIMERH,
 	},
 	{
 		.gpio_chip			= {
@@ -445,11 +445,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 80,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_TIMERL,
-		.podr				= MCFGPIO_PODR_TIMERL,
-		.ppdr				= MCFGPIO_PPDSDR_TIMERL,
-		.setr				= MCFGPIO_PPDSDR_TIMERL,
-		.clrr				= MCFGPIO_PCLRR_TIMERL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_TIMERL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_TIMERL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_TIMERL,
 	},
 	{
 		.gpio_chip			= {
@@ -463,11 +463,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 88,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_UARTL,
-		.podr				= MCFGPIO_PODR_UARTL,
-		.ppdr				= MCFGPIO_PPDSDR_UARTL,
-		.setr				= MCFGPIO_PPDSDR_UARTL,
-		.clrr				= MCFGPIO_PCLRR_UARTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UARTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UARTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UARTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UARTL,
 	},
 	{
 		.gpio_chip			= {
@@ -481,11 +481,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 96,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FEC1H,
-		.podr				= MCFGPIO_PODR_FEC1H,
-		.ppdr				= MCFGPIO_PPDSDR_FEC1H,
-		.setr				= MCFGPIO_PPDSDR_FEC1H,
-		.clrr				= MCFGPIO_PCLRR_FEC1H,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FEC1H,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FEC1H,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FEC1H,
 	},
 	{
 		.gpio_chip			= {
@@ -499,11 +499,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 104,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FEC1L,
-		.podr				= MCFGPIO_PODR_FEC1L,
-		.ppdr				= MCFGPIO_PPDSDR_FEC1L,
-		.setr				= MCFGPIO_PPDSDR_FEC1L,
-		.clrr				= MCFGPIO_PCLRR_FEC1L,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FEC1L,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FEC1L,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FEC1L,
 	},
 	{
 		.gpio_chip			= {
@@ -517,11 +517,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 114,
 			.ngpio			= 2,
 		},
-		.pddr				= MCFGPIO_PDDR_BS,
-		.podr				= MCFGPIO_PODR_BS,
-		.ppdr				= MCFGPIO_PPDSDR_BS,
-		.setr				= MCFGPIO_PPDSDR_BS,
-		.clrr				= MCFGPIO_PCLRR_BS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BS,
 	},
 	{
 		.gpio_chip			= {
@@ -535,11 +535,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 121,
 			.ngpio			= 7,
 		},
-		.pddr				= MCFGPIO_PDDR_IRQ,
-		.podr				= MCFGPIO_PODR_IRQ,
-		.ppdr				= MCFGPIO_PPDSDR_IRQ,
-		.setr				= MCFGPIO_PPDSDR_IRQ,
-		.clrr				= MCFGPIO_PCLRR_IRQ,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_IRQ,
+		.podr				= (void __iomem *) MCFGPIO_PODR_IRQ,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_IRQ,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_IRQ,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_IRQ,
 	},
 	{
 		.gpio_chip			= {
@@ -553,11 +553,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 128,
 			.ngpio			= 1,
 		},
-		.pddr				= MCFGPIO_PDDR_USBH,
-		.podr				= MCFGPIO_PODR_USBH,
-		.ppdr				= MCFGPIO_PPDSDR_USBH,
-		.setr				= MCFGPIO_PPDSDR_USBH,
-		.clrr				= MCFGPIO_PCLRR_USBH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_USBH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_USBH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_USBH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_USBH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_USBH,
 	},
 	{
 		.gpio_chip			= {
@@ -571,11 +571,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 136,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_USBL,
-		.podr				= MCFGPIO_PODR_USBL,
-		.ppdr				= MCFGPIO_PPDSDR_USBL,
-		.setr				= MCFGPIO_PPDSDR_USBL,
-		.clrr				= MCFGPIO_PCLRR_USBL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_USBL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_USBL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_USBL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_USBL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_USBL,
 	},
 	{
 		.gpio_chip			= {
@@ -589,11 +589,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 144,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_UARTH,
-		.podr				= MCFGPIO_PODR_UARTH,
-		.ppdr				= MCFGPIO_PPDSDR_UARTH,
-		.setr				= MCFGPIO_PPDSDR_UARTH,
-		.clrr				= MCFGPIO_PCLRR_UARTH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UARTH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UARTH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UARTH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UARTH,
 	},
 #endif
 };
-- 
cgit v1.2.3


From 2af36dc423fca37be9149329dff1635e4ff72ac4 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:14:49 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 5307 targets

Fix these compiler warnings:

arch/m68knommu/platform/5307/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5307/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5307/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5307/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68knommu/platform/5307/gpio.c
index 8da5880e4066..5850612b4a38 100644
--- a/arch/m68knommu/platform/5307/gpio.c
+++ b/arch/m68knommu/platform/5307/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 16,
 		},
-		.pddr				= MCFSIM_PADDR,
-		.podr				= MCFSIM_PADAT,
-		.ppdr				= MCFSIM_PADAT,
+		.pddr				= (void __iomem *) MCFSIM_PADDR,
+		.podr				= (void __iomem *) MCFSIM_PADAT,
+		.ppdr				= (void __iomem *) MCFSIM_PADAT,
 	},
 };
 
-- 
cgit v1.2.3


From 5d44b09610033d244cc157ac17fc7e6c6793b1d1 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:19:50 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 532x targets

Fix these compiler warnings:

arch/m68knommu/platform/532x/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/532x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/532x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/532x/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/532x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/532x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/532x/gpio.c:54:3: warning: initialisation makes pointer from integer without a cast
...

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/532x/gpio.c | 166 ++++++++++++++++++------------------
 1 file changed, 83 insertions(+), 83 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68knommu/platform/532x/gpio.c
index 184b77382c3d..212a85deac90 100644
--- a/arch/m68knommu/platform/532x/gpio.c
+++ b/arch/m68knommu/platform/532x/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFEPORT_EPDDR,
-		.podr				= MCFEPORT_EPDR,
-		.ppdr				= MCFEPORT_EPPDR,
+		.pddr				= (void __iomem *) MCFEPORT_EPDDR,
+		.podr				= (void __iomem *) MCFEPORT_EPDR,
+		.ppdr				= (void __iomem *) MCFEPORT_EPPDR,
 	},
 	{
 		.gpio_chip			= {
@@ -48,11 +48,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 8,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FECH,
-		.podr				= MCFGPIO_PODR_FECH,
-		.ppdr				= MCFGPIO_PPDSDR_FECH,
-		.setr				= MCFGPIO_PPDSDR_FECH,
-		.clrr				= MCFGPIO_PCLRR_FECH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECH,
 	},
 	{
 		.gpio_chip			= {
@@ -66,11 +66,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 16,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_FECL,
-		.podr				= MCFGPIO_PODR_FECL,
-		.ppdr				= MCFGPIO_PPDSDR_FECL,
-		.setr				= MCFGPIO_PPDSDR_FECL,
-		.clrr				= MCFGPIO_PCLRR_FECL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECL,
 	},
 	{
 		.gpio_chip			= {
@@ -84,11 +84,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 24,
 			.ngpio			= 5,
 		},
-		.pddr				= MCFGPIO_PDDR_SSI,
-		.podr				= MCFGPIO_PODR_SSI,
-		.ppdr				= MCFGPIO_PPDSDR_SSI,
-		.setr				= MCFGPIO_PPDSDR_SSI,
-		.clrr				= MCFGPIO_PCLRR_SSI,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_SSI,
+		.podr				= (void __iomem *) MCFGPIO_PODR_SSI,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_SSI,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_SSI,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_SSI,
 	},
 	{
 		.gpio_chip			= {
@@ -102,11 +102,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 32,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_BUSCTL,
-		.podr				= MCFGPIO_PODR_BUSCTL,
-		.ppdr				= MCFGPIO_PPDSDR_BUSCTL,
-		.setr				= MCFGPIO_PPDSDR_BUSCTL,
-		.clrr				= MCFGPIO_PCLRR_BUSCTL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BUSCTL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BUSCTL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
 	},
 	{
 		.gpio_chip			= {
@@ -120,11 +120,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 40,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_BE,
-		.podr				= MCFGPIO_PODR_BE,
-		.ppdr				= MCFGPIO_PPDSDR_BE,
-		.setr				= MCFGPIO_PPDSDR_BE,
-		.clrr				= MCFGPIO_PCLRR_BE,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_BE,
+		.podr				= (void __iomem *) MCFGPIO_PODR_BE,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_BE,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_BE,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_BE,
 	},
 	{
 		.gpio_chip			= {
@@ -138,11 +138,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 49,
 			.ngpio			= 5,
 		},
-		.pddr				= MCFGPIO_PDDR_CS,
-		.podr				= MCFGPIO_PODR_CS,
-		.ppdr				= MCFGPIO_PPDSDR_CS,
-		.setr				= MCFGPIO_PPDSDR_CS,
-		.clrr				= MCFGPIO_PCLRR_CS,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_CS,
+		.podr				= (void __iomem *) MCFGPIO_PODR_CS,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_CS,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_CS,
 	},
 	{
 		.gpio_chip			= {
@@ -156,11 +156,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 58,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_PWM,
-		.podr				= MCFGPIO_PODR_PWM,
-		.ppdr				= MCFGPIO_PPDSDR_PWM,
-		.setr				= MCFGPIO_PPDSDR_PWM,
-		.clrr				= MCFGPIO_PCLRR_PWM,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_PWM,
+		.podr				= (void __iomem *) MCFGPIO_PODR_PWM,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_PWM,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_PWM,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_PWM,
 	},
 	{
 		.gpio_chip			= {
@@ -174,11 +174,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 64,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_FECI2C,
-		.podr				= MCFGPIO_PODR_FECI2C,
-		.ppdr				= MCFGPIO_PPDSDR_FECI2C,
-		.setr				= MCFGPIO_PPDSDR_FECI2C,
-		.clrr				= MCFGPIO_PCLRR_FECI2C,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_FECI2C,
+		.podr				= (void __iomem *) MCFGPIO_PODR_FECI2C,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_FECI2C,
 	},
 	{
 		.gpio_chip			= {
@@ -192,11 +192,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 72,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_UART,
-		.podr				= MCFGPIO_PODR_UART,
-		.ppdr				= MCFGPIO_PPDSDR_UART,
-		.setr				= MCFGPIO_PPDSDR_UART,
-		.clrr				= MCFGPIO_PCLRR_UART,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_UART,
+		.podr				= (void __iomem *) MCFGPIO_PODR_UART,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_UART,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_UART,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_UART,
 	},
 	{
 		.gpio_chip			= {
@@ -210,11 +210,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 80,
 			.ngpio			= 6,
 		},
-		.pddr				= MCFGPIO_PDDR_QSPI,
-		.podr				= MCFGPIO_PODR_QSPI,
-		.ppdr				= MCFGPIO_PPDSDR_QSPI,
-		.setr				= MCFGPIO_PPDSDR_QSPI,
-		.clrr				= MCFGPIO_PCLRR_QSPI,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_QSPI,
+		.podr				= (void __iomem *) MCFGPIO_PODR_QSPI,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_QSPI,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_QSPI,
 	},
 	{
 		.gpio_chip			= {
@@ -228,11 +228,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 88,
 			.ngpio			= 4,
 		},
-		.pddr				= MCFGPIO_PDDR_TIMER,
-		.podr				= MCFGPIO_PODR_TIMER,
-		.ppdr				= MCFGPIO_PPDSDR_TIMER,
-		.setr				= MCFGPIO_PPDSDR_TIMER,
-		.clrr				= MCFGPIO_PCLRR_TIMER,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_TIMER,
+		.podr				= (void __iomem *) MCFGPIO_PODR_TIMER,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_TIMER,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_TIMER,
 	},
 	{
 		.gpio_chip			= {
@@ -246,11 +246,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 96,
 			.ngpio			= 2,
 		},
-		.pddr				= MCFGPIO_PDDR_LCDDATAH,
-		.podr				= MCFGPIO_PODR_LCDDATAH,
-		.ppdr				= MCFGPIO_PPDSDR_LCDDATAH,
-		.setr				= MCFGPIO_PPDSDR_LCDDATAH,
-		.clrr				= MCFGPIO_PCLRR_LCDDATAH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_LCDDATAH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
 	},
 	{
 		.gpio_chip			= {
@@ -264,11 +264,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 104,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_LCDDATAM,
-		.podr				= MCFGPIO_PODR_LCDDATAM,
-		.ppdr				= MCFGPIO_PPDSDR_LCDDATAM,
-		.setr				= MCFGPIO_PPDSDR_LCDDATAM,
-		.clrr				= MCFGPIO_PCLRR_LCDDATAM,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
+		.podr				= (void __iomem *) MCFGPIO_PODR_LCDDATAM,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
 	},
 	{
 		.gpio_chip			= {
@@ -282,11 +282,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 112,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_LCDDATAL,
-		.podr				= MCFGPIO_PODR_LCDDATAL,
-		.ppdr				= MCFGPIO_PPDSDR_LCDDATAL,
-		.setr				= MCFGPIO_PPDSDR_LCDDATAL,
-		.clrr				= MCFGPIO_PCLRR_LCDDATAL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_LCDDATAL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
 	},
 	{
 		.gpio_chip			= {
@@ -300,11 +300,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 120,
 			.ngpio			= 1,
 		},
-		.pddr				= MCFGPIO_PDDR_LCDCTLH,
-		.podr				= MCFGPIO_PODR_LCDCTLH,
-		.ppdr				= MCFGPIO_PPDSDR_LCDCTLH,
-		.setr				= MCFGPIO_PPDSDR_LCDCTLH,
-		.clrr				= MCFGPIO_PCLRR_LCDCTLH,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
+		.podr				= (void __iomem *) MCFGPIO_PODR_LCDCTLH,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
 	},
 	{
 		.gpio_chip			= {
@@ -318,11 +318,11 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.base			= 128,
 			.ngpio			= 8,
 		},
-		.pddr				= MCFGPIO_PDDR_LCDCTLL,
-		.podr				= MCFGPIO_PODR_LCDCTLL,
-		.ppdr				= MCFGPIO_PPDSDR_LCDCTLL,
-		.setr				= MCFGPIO_PPDSDR_LCDCTLL,
-		.clrr				= MCFGPIO_PCLRR_LCDCTLL,
+		.pddr				= (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
+		.podr				= (void __iomem *) MCFGPIO_PODR_LCDCTLL,
+		.ppdr				= (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
+		.setr				= (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
+		.clrr				= (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
 	},
 };
 
-- 
cgit v1.2.3


From 442ca465c0e775a0808e02d4fcddeddb2fcc882c Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 09:21:24 +1000
Subject: m68knommu: fix gpio warnings for ColdFire 5407 targets

Fix these compiler warnings:

arch/m68knommu/platform/5407/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5407/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast
arch/m68knommu/platform/5407/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68knommu/platform/5407/gpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'arch')

diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68knommu/platform/5407/gpio.c
index 8da5880e4066..5850612b4a38 100644
--- a/arch/m68knommu/platform/5407/gpio.c
+++ b/arch/m68knommu/platform/5407/gpio.c
@@ -32,9 +32,9 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = {
 			.set			= mcf_gpio_set_value,
 			.ngpio			= 16,
 		},
-		.pddr				= MCFSIM_PADDR,
-		.podr				= MCFSIM_PADAT,
-		.ppdr				= MCFSIM_PADAT,
+		.pddr				= (void __iomem *) MCFSIM_PADDR,
+		.podr				= (void __iomem *) MCFSIM_PADAT,
+		.ppdr				= (void __iomem *) MCFSIM_PADAT,
 	},
 };
 
-- 
cgit v1.2.3


From ce3de78a1c9504dba1781e47613b397e4028ae2b Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Wed, 9 Mar 2011 14:19:08 +1000
Subject: m68knommu: remove ColdFire CLOCK_DIV config option

The reality is that you do not need the abiltity to configure the
clock divider for ColdFire CPUs. It is a fixed ratio on any given
ColdFire family member. It is not the same for all ColdFire parts,
but it is always the same in a model range. So hard define the divider
for each supported ColdFire CPU type and remove the Kconfig option.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/coldfire.h |  9 ++++-----
 arch/m68k/include/asm/m5206sim.h |  1 +
 arch/m68k/include/asm/m520xsim.h |  1 +
 arch/m68k/include/asm/m523xsim.h |  1 +
 arch/m68k/include/asm/m5249sim.h |  1 +
 arch/m68k/include/asm/m5272sim.h |  1 +
 arch/m68k/include/asm/m527xsim.h |  1 +
 arch/m68k/include/asm/m528xsim.h |  1 +
 arch/m68k/include/asm/m5307sim.h |  1 +
 arch/m68k/include/asm/m532xsim.h |  1 +
 arch/m68k/include/asm/m5407sim.h |  1 +
 arch/m68k/include/asm/m54xxsim.h |  1 +
 arch/m68knommu/Kconfig           | 11 -----------
 13 files changed, 15 insertions(+), 16 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 98d1d25101f2..c94557b91448 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -14,14 +14,13 @@
 
 
 /*
- *	Define master clock frequency. This is essentially done at config
- *	time now. No point enumerating dozens of possible clock options
- *	here. Also the peripheral clock (bus clock) divide ratio is set
- *	at config time too.
+ *	Define master clock frequency. This is done at config time now.
+ *	No point enumerating dozens of possible clock options here. And
+ *	in any case new boards come along from time to time that have yet
+ *	another different clocking frequency.
  */
 #ifdef CONFIG_CLOCK_SET
 #define	MCF_CLK		CONFIG_CLOCK_FREQ
-#define	MCF_BUSCLK	(CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)
 #else
 #error "Don't know what your ColdFire CPU clock frequency is??"
 #endif
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index dfd6d3f73584..9015eadd5c00 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -14,6 +14,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m5206)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		MCF_CLK
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 87f8ce73b318..ee89801eec9d 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -13,6 +13,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m520x)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 3f3dbf01a109..3852f074fddd 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -13,6 +13,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m523x)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 33b0b4df07ca..805714ca8d7d 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -13,6 +13,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m5249)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 57ca4de1f911..759c2b07a994 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -14,6 +14,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m5272)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		MCF_CLK
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 838fb2b1e88b..c23046ee3a51 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -13,6 +13,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m527x)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 47324f2258a7..d798bd5df56c 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -13,6 +13,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m528x)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		MCF_CLK
 
 #include <asm/m52xxacr.h>
 
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index e4365f2e5c29..4c94c01f36c4 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -16,6 +16,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m5307)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m53xxacr.h>
 
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 0dea126f3fcf..ba4cc784f574 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -11,6 +11,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m532x)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 3)
 
 #include <asm/m53xxacr.h>
 
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index c1eba01d26b0..762c58c89050 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -16,6 +16,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m5407)"
 #define	CPU_INSTR_PER_JIFFY	3
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m54xxacr.h>
 
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index cc5d94d215b4..daaae276bb09 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -7,6 +7,7 @@
 
 #define	CPU_NAME		"COLDFIRE(m54xx)"
 #define	CPU_INSTR_PER_JIFFY	2
+#define	MCF_BUSCLK		(MCF_CLK / 2)
 
 #include <asm/m54xxacr.h>
 
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 2e6fe63b7a0f..b5424cf948e6 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -260,17 +260,6 @@ config CLOCK_FREQ
 	  if it is fitted (there are some exceptions). This value will be
 	  specific to the exact CPU that you are using.
 
-config CLOCK_DIV
-	int "Set the core/bus clock divide ratio"
-	default "1"
-	depends on CLOCK_SET
-	help
-	  On many SoC style CPUs the master CPU clock is also used to drive 
-	  on-chip peripherals. The clock that is distributed to these
-	  peripherals is sometimes a fixed ratio of the master clock
-	  frequency. If so then set this to the divider ratio of the
-	  master clock to the peripheral clock. If not sure then select 1.
-
 config OLDMASK
 	bool "Old mask 5307 (1H55J) silicon"
 	depends on M5307
-- 
cgit v1.2.3


From 57b481436f2a5580054784af8f044d2e3f602b53 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Fri, 11 Mar 2011 17:06:58 +1000
Subject: m68knommu: external interrupt support to ColdFire intc-2 controller

The EDGE Port module of some ColdFire parts using the intc-2 interrupt
controller provides support for 7 external interrupts. These interrupts
go off-chip (that is they are not for internal peripherals). They need
some special handling and have some extra setup registers. Add code to
support them.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m523xsim.h          |  3 ++
 arch/m68k/include/asm/m527xsim.h          |  3 ++
 arch/m68k/include/asm/m54xxsim.h          | 10 ++++
 arch/m68knommu/platform/coldfire/intc-2.c | 85 +++++++++++++++++++++++++++++--
 4 files changed, 97 insertions(+), 4 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 3852f074fddd..8996df62ede4 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -139,9 +139,12 @@
 /*
  * EPort
  */
+#define MCFEPORT_EPPAR		(MCF_IPSBAR + 0x130000)
 #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER		(MCF_IPSBAR + 0x130003)
 #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)
 
 /*
  * Generic GPIO support
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index c23046ee3a51..74855a66c050 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -259,9 +259,12 @@
 /*
  * EPort
  */
+#define MCFEPORT_EPPAR		(MCF_IPSBAR + 0x130000)
 #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
+#define MCFEPORT_EPIER		(MCF_IPSBAR + 0x130003)
 #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
 #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
+#define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)
 
 /*
  *	GPIO pins setups to enable the UARTs.
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index daaae276bb09..1ed8bfb02772 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -49,6 +49,16 @@
 #define MCFGPIO_IRQ_MAX		-1
 #define MCFGPIO_IRQ_VECBASE	-1
 
+/*
+ *	EDGE Port support.
+ */
+#define	MCFEPORT_EPPAR		(MCF_MBAR + 0xf00)	/* Pin assignment */
+#define	MCFEPORT_EPDDR		(MCF_MBAR + 0xf04)	/* Data direction */
+#define	MCFEPORT_EPIER		(MCF_MBAR + 0xf05)	/* Interrupt enable */
+#define	MCFEPORT_EPDR		(MCF_MBAR + 0xf08)	/* Port data (w) */
+#define	MCFEPORT_EPPDR		(MCF_MBAR + 0xf09)	/* Port data (r) */
+#define	MCFEPORT_EPFR		(MCF_MBAR + 0xf0c)	/* Flags */
+
 /*
  *	Some PSC related definitions
  */
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 66d4e47dd8d0..2cbfbf035db9 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -7,7 +7,10 @@
  * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
  * controllers, and the 547x and 548x families which have only one of them.
  *
- * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
+ * The external 7 fixed interrupts are part the the Edge Port unit of these
+ * ColdFire parts. They can be configured as level or edge triggered.
+ *
+ * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file COPYING in the main directory of this archive
@@ -30,6 +33,14 @@
 #define MCFSIM_ICR_LEVEL(l)	((l)<<3)	/* Level l intr */
 #define MCFSIM_ICR_PRI(p)	(p)		/* Priority p intr */
 
+/*
+ *	The EDGE Port interrupts are the fixed 7 external interrupts.
+ *	They need some special treatment, for example they need to be acked.
+ */
+#define	EINT0	64	/* Is not actually used, but spot reserved for it */
+#define	EINT1	65	/* EDGE Port interrupt 1 */
+#define	EINT7	71	/* EDGE Port interrupt 7 */
+
 #ifdef MCFICM_INTC1
 #define NR_VECS	128
 #else
@@ -76,9 +87,17 @@ static void intc_irq_unmask(struct irq_data *d)
 	__raw_writel(val & ~imrbit, imraddr);
 }
 
-static int intc_irq_set_type(struct irq_data *d, unsigned int type)
+/*
+ *	Only the external (or EDGE Port) interrupts need to be acknowledged
+ *	here, as part of the IRQ handler. They only really need to be ack'ed
+ *	if they are in edge triggered mode, but there is no harm in doing it
+ *	for all types.
+ */
+static void intc_irq_ack(struct irq_data *d)
 {
-	return 0;
+	unsigned int irq = d->irq;
+
+	__raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
 }
 
 /*
@@ -104,15 +123,70 @@ static unsigned int intc_irq_startup(struct irq_data *d)
 	if (__raw_readb(icraddr) == 0)
 		__raw_writeb(intc_intpri--, icraddr);
 
+	irq = d->irq;
+	if ((irq >= EINT1) && (irq <= EINT7)) {
+		u8 v;
+
+		irq -= EINT0;
+
+		/* Set EPORT line as input */
+		v = __raw_readb(MCFEPORT_EPDDR);
+		__raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
+
+		/* Set EPORT line as interrupt source */
+		v = __raw_readb(MCFEPORT_EPIER);
+		__raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
+	}
+
 	intc_irq_unmask(d);
 	return 0;
 }
 
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	unsigned int irq = d->irq;
+	u16 pa, tb;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		tb = 0x1;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		tb = 0x2;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		tb = 0x3;
+		break;
+	default:
+		/* Level triggered */
+		tb = 0;
+		break;
+	}
+
+	if (tb)
+		set_irq_handler(irq, handle_edge_irq);
+
+	irq -= EINT0;
+	pa = __raw_readw(MCFEPORT_EPPAR);
+	pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
+	__raw_writew(pa, MCFEPORT_EPPAR);
+	
+	return 0;
+}
+
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
 	.irq_startup	= intc_irq_startup,
 	.irq_mask	= intc_irq_mask,
 	.irq_unmask	= intc_irq_unmask,
+};
+
+static struct irq_chip intc_irq_chip_edge_port = {
+	.name		= "CF-INTC-EP",
+	.irq_startup	= intc_irq_startup,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+	.irq_ack	= intc_irq_ack,
 	.irq_set_type	= intc_irq_set_type,
 };
 
@@ -129,7 +203,10 @@ void __init init_IRQ(void)
 #endif
 
 	for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
-		set_irq_chip(irq, &intc_irq_chip);
+		if ((irq >= EINT1) && (irq <=EINT7))
+			set_irq_chip(irq, &intc_irq_chip_edge_port);
+		else
+			set_irq_chip(irq, &intc_irq_chip);
 		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
 		set_irq_handler(irq, handle_level_irq);
 	}
-- 
cgit v1.2.3


From 47e0c7e128afb85cf4fb7792e6e7fcb91e2a5cc4 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@uclinux.org>
Date: Fri, 11 Mar 2011 22:25:44 +1000
Subject: m68knommu: external interrupt support to ColdFire intc-simr
 controller

The EDGE Port module of some ColdFire parts using the intc-simr interrupt
controller provides support for 7 external interrupts. These interrupts
go off-chip (that is they are not for internal peripherals). They need
some special handling and have some extra setup registers. Add code to
support them.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m520xsim.h             |   3 +
 arch/m68knommu/platform/coldfire/intc-simr.c | 114 ++++++++++++++++++++++++++-
 2 files changed, 113 insertions(+), 4 deletions(-)

(limited to 'arch')

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index ee89801eec9d..55d5a4c5fe0b 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -63,9 +63,12 @@
 /*
  * EPORT and GPIO registers.
  */
+#define MCFEPORT_EPPAR			0xFC088000
 #define MCFEPORT_EPDDR			0xFC088002
+#define MCFEPORT_EPIER			0xFC088003
 #define MCFEPORT_EPDR			0xFC088004
 #define MCFEPORT_EPPDR			0xFC088005
+#define MCFEPORT_EPFR			0xFC088006
 
 #define MCFGPIO_PODR_BUSCTL		0xFC0A4000
 #define MCFGPIO_PODR_BE			0xFC0A4001
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 8876f434c125..e642b24ab729 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -3,7 +3,7 @@
  *
  * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
  *
- * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
+ * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file COPYING in the main directory of this archive
@@ -20,6 +20,44 @@
 #include <asm/mcfsim.h>
 #include <asm/traps.h>
 
+/*
+ *	The EDGE Port interrupts are the fixed 7 external interrupts.
+ *	They need some special treatment, for example they need to be acked.
+ */
+#ifdef CONFIG_M520x
+/*
+ *	The 520x parts only support a limited range of these external
+ *	interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67).
+ */
+#define	EINT0	64	/* Is not actually used, but spot reserved for it */
+#define	EINT1	65	/* EDGE Port interrupt 1 */
+#define	EINT4	66	/* EDGE Port interrupt 4 */
+#define	EINT7	67	/* EDGE Port interrupt 7 */
+
+static unsigned int irqebitmap[] = { 0, 1, 4, 7 };
+static unsigned int inline irq2ebit(unsigned int irq)
+{
+	return irqebitmap[irq - EINT0];
+}
+
+#else
+
+/*
+ *	Most of the ColdFire parts with the EDGE Port module just have
+ *	a strait direct mapping of the 7 external interrupts. Although
+ *	there is a bit reserved for 0, it is not used.
+ */
+#define	EINT0	64	/* Is not actually used, but spot reserved for it */
+#define	EINT1	65	/* EDGE Port interrupt 1 */
+#define	EINT7	71	/* EDGE Port interrupt 7 */
+
+static unsigned int inline irq2ebit(unsigned int irq)
+{
+	return irq - EINT0;
+}
+
+#endif
+
 /*
  *	There maybe one or two interrupt control units, each has 64
  *	interrupts. If there is no second unit then MCFINTC1_* defines
@@ -46,21 +84,86 @@ static void intc_irq_unmask(struct irq_data *d)
 		__raw_writeb(irq, MCFINTC0_CIMR);
 }
 
-static int intc_irq_set_type(struct irq_data *d, unsigned int type)
+static void intc_irq_ack(struct irq_data *d)
 {
-	unsigned int irq = d->irq - MCFINT_VECBASE;
+	unsigned int ebit = irq2ebit(d->irq);
 
+	__raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
+}
+
+static unsigned int intc_irq_startup(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+
+	if ((irq >= EINT1) && (irq <= EINT7)) {
+		unsigned int ebit = irq2ebit(irq);
+		u8 v;
+
+		/* Set EPORT line as input */
+		v = __raw_readb(MCFEPORT_EPDDR);
+		__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
+
+		/* Set EPORT line as interrupt source */
+		v = __raw_readb(MCFEPORT_EPIER);
+		__raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
+	}
+
+	irq -= MCFINT_VECBASE;
 	if (MCFINTC1_ICR0 && (irq > 64))
 		__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
 	else
 		__raw_writeb(5, MCFINTC0_ICR0 + irq);
+
+
+	intc_irq_unmask(d);
+	return 0;
+}
+
+static int intc_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	unsigned int ebit, irq = d->irq;
+	u16 pa, tb;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		tb = 0x1;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		tb = 0x2;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		tb = 0x3;
+		break;
+	default:
+		/* Level triggered */
+		tb = 0;
+		break;
+	}
+
+	if (tb)
+		set_irq_handler(irq, handle_edge_irq);
+
+	ebit = irq2ebit(irq) * 2;
+	pa = __raw_readw(MCFEPORT_EPPAR);
+	pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
+	__raw_writew(pa, MCFEPORT_EPPAR);
+	
 	return 0;
 }
 
 static struct irq_chip intc_irq_chip = {
 	.name		= "CF-INTC",
+	.irq_startup	= intc_irq_startup,
+	.irq_mask	= intc_irq_mask,
+	.irq_unmask	= intc_irq_unmask,
+};
+
+static struct irq_chip intc_irq_chip_edge_port = {
+	.name		= "CF-INTC-EP",
+	.irq_startup	= intc_irq_startup,
 	.irq_mask	= intc_irq_mask,
 	.irq_unmask	= intc_irq_unmask,
+	.irq_ack	= intc_irq_ack,
 	.irq_set_type	= intc_irq_set_type,
 };
 
@@ -77,7 +180,10 @@ void __init init_IRQ(void)
 
 	eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
 	for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
-		set_irq_chip(irq, &intc_irq_chip);
+		if ((irq >= EINT1) && (irq <= EINT7))
+			set_irq_chip(irq, &intc_irq_chip_edge_port);
+		else
+			set_irq_chip(irq, &intc_irq_chip);
 		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
 		set_irq_handler(irq, handle_level_irq);
 	}
-- 
cgit v1.2.3