From 25e56eba0ae783fc5b66d50c68826f276e8bd8c6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 10 Apr 2013 11:31:44 +0200 Subject: clk: exynos: prepare for multiplatform The new common clock drivers for exynos are using compile time constants and soc_is_exynos* macros to provide backwards compatibility for pre-DT systems, which is not possible with multiplatform kernels. This moves all the necessary information back into platform code and removes the mach/* header inclusions. Signed-off-by: Arnd Bergmann Cc: Mike Turquette --- arch/arm/mach-exynos/common.c | 2 +- arch/arm/mach-exynos/common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index a3ab0ecc7c6a..c3167b741180 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -413,7 +413,7 @@ void __init exynos_init_time(void) } else { /* todo: remove after migrating legacy E4 platforms to dt */ #ifdef CONFIG_ARCH_EXYNOS4 - exynos4_clk_init(NULL); + exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1); exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); #endif mct_init(); diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index cb89ab886950..4ed8eef2b096 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -27,7 +27,7 @@ void exynos5_restart(char mode, const char *cmd); void exynos_init_late(void); /* ToDo: remove these after migrating legacy exynos4 platforms to dt */ -void exynos4_clk_init(struct device_node *np); +void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom); void exynos4_clk_register_fixed_ext(unsigned long, unsigned long); #ifdef CONFIG_PM_GENERIC_DOMAINS -- cgit v1.2.3 From 034c097ca27fb163754ee4f4e26f85559bece69b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 10 Apr 2013 11:35:29 +0200 Subject: clocksource: exynos_mct: remove platform header dependency For the non-DT case, the mct_init() function requires access to a couple of platform specific constants, but cannot include the header files in case we are building for multiplatform. This changes the interface to the platform so we pass all the necessary data as arguments to mct_init. Signed-off-by: Arnd Bergmann Cc: Thomas Gleixner Cc: John Stultz --- arch/arm/mach-exynos/common.c | 2 +- arch/arm/mach-exynos/common.h | 2 +- drivers/clocksource/exynos_mct.c | 21 ++++++--------------- 3 files changed, 8 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index c3167b741180..a453991ce90b 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -416,7 +416,7 @@ void __init exynos_init_time(void) exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1); exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f); #endif - mct_init(); + mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1); } } diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 4ed8eef2b096..9717d0f6088f 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -14,7 +14,7 @@ #include -extern void mct_init(void); +void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); void exynos_init_time(void); extern unsigned long xxti_f, xusbxti_f; diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 661026834b23..a6ca0fb06939 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -26,11 +26,6 @@ #include #include - -#include - -#include -#include #include #define EXYNOS4_MCTREG(x) (x) @@ -511,18 +506,14 @@ static void __init exynos4_timer_resources(struct device_node *np, void __iomem #endif /* CONFIG_LOCAL_TIMERS */ } -void __init mct_init(void) +void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1) { - if (soc_is_exynos4210()) { - mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; - mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0; - mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1; - mct_int_type = MCT_INT_SPI; - } else { - panic("unable to determine mct controller type\n"); - } + mct_irqs[MCT_G0_IRQ] = irq_g0; + mct_irqs[MCT_L0_IRQ] = irq_l0; + mct_irqs[MCT_L1_IRQ] = irq_l1; + mct_int_type = MCT_INT_SPI; - exynos4_timer_resources(NULL, S5P_VA_SYSTIMER); + exynos4_timer_resources(NULL, base); exynos4_clocksource_init(); exynos4_clockevent_init(); } -- cgit v1.2.3 From 30269ddff13f417677a27e37086c97a57f1cf2da Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 12 Apr 2013 15:15:58 +0200 Subject: ARM: exynos: add missing properties for combiner IRQs The exynos combiner irqchip needs to find the parent interrupts and needs to know their number, so add the missing properties for exynos4 as they were already present for exynos5. Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/exynos4210.dtsi | 1 + arch/arm/boot/dts/exynos4212.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4412.dtsi | 9 +++++++++ 3 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 15143bdbafb8..5feccffae409 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -41,6 +41,7 @@ }; combiner:interrupt-controller@10440000 { + samsung,combiner-nr = <16>; interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 36d4299789ef..c0f60f49cea6 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -26,6 +26,15 @@ cpu-offset = <0x8000>; }; + interrupt-controller@10440000 { + samsung,combiner-nr = <18>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 107 0>, <0 108 0>; + }; + mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d75c047e80a9..f433206bd3c5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -26,6 +26,15 @@ cpu-offset = <0x4000>; }; + interrupt-controller@10440000 { + samsung,combiner-nr = <20>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, + <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; + }; + mct@10050000 { compatible = "samsung,exynos4412-mct"; reg = <0x10050000 0x800>; -- cgit v1.2.3 From 6761dcfe8c42b55076753bc8bea7b5dcbfb445c0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 10 Apr 2013 15:17:47 +0200 Subject: irqchip: exynos: pass max combiner number to combiner_init We can find out the number of combined IRQs from the device tree, but in case of ATAGS boot, the driver currently uses hardcoded values based on the SoC type. We can't do that in general for a multiplatform kernel, so let's instead pass this information from platform code directly in case of ATAGS boot. Signed-off-by: Arnd Bergmann Cc: Thomas Gleixner --- arch/arm/mach-exynos/common.c | 15 ++++++++++++- arch/arm/mach-exynos/common.h | 3 ++- drivers/irqchip/exynos-combiner.c | 46 ++++++++++++++------------------------- 3 files changed, 32 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index a453991ce90b..368fa4b01e7c 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -420,6 +420,19 @@ void __init exynos_init_time(void) } } +static unsigned int max_combiner_nr(void) +{ + if (soc_is_exynos5250()) + return EXYNOS5_MAX_COMBINER_NR; + else if (soc_is_exynos4412()) + return EXYNOS4412_MAX_COMBINER_NR; + else if (soc_is_exynos4212()) + return EXYNOS4212_MAX_COMBINER_NR; + else + return EXYNOS4210_MAX_COMBINER_NR; +} + + void __init exynos4_init_irq(void) { unsigned int gic_bank_offset; @@ -434,7 +447,7 @@ void __init exynos4_init_irq(void) #endif if (!of_have_populated_dt()) - combiner_init(S5P_VA_COMBINER_BASE, NULL); + combiner_init(S5P_VA_COMBINER_BASE, NULL, max_combiner_nr()); /* * The parameters of s5p_init_irq() are for VIC init. diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9717d0f6088f..4ba8cbecc144 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -69,7 +69,8 @@ void exynos4212_register_clocks(void); #endif struct device_node; -void combiner_init(void __iomem *combiner_base, struct device_node *np); +void combiner_init(void __iomem *combiner_base, struct device_node *np, + unsigned int max_nr); extern struct smp_operations exynos_smp_ops; diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index e8501dbaa0b7..d8683836ee1e 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -25,6 +25,8 @@ #define COMBINER_ENABLE_CLEAR 0x4 #define COMBINER_INT_STATUS 0xC +#define IRQ_IN_COMBINER 8 + static DEFINE_SPINLOCK(irq_controller_lock); struct combiner_chip_data { @@ -112,23 +114,9 @@ static struct irq_chip combiner_chip = { #endif }; -static unsigned int max_combiner_nr(void) -{ - if (soc_is_exynos5250()) - return EXYNOS5_MAX_COMBINER_NR; - else if (soc_is_exynos4412()) - return EXYNOS4412_MAX_COMBINER_NR; - else if (soc_is_exynos4212()) - return EXYNOS4212_MAX_COMBINER_NR; - else - return EXYNOS4210_MAX_COMBINER_NR; -} - static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) { - if (combiner_nr >= max_combiner_nr()) - BUG(); if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) BUG(); irq_set_chained_handler(irq, combiner_handle_cascade_irq); @@ -139,7 +127,7 @@ static void __init combiner_init_one(unsigned int combiner_nr, { combiner_data[combiner_nr].base = base; combiner_data[combiner_nr].irq_offset = irq_find_mapping( - combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); + combiner_irq_domain, combiner_nr * IRQ_IN_COMBINER); combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); combiner_data[combiner_nr].parent_irq = irq; @@ -161,7 +149,7 @@ static int combiner_irq_domain_xlate(struct irq_domain *d, if (intsize < 2) return -EINVAL; - *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1]; + *out_hwirq = intspec[0] * IRQ_IN_COMBINER + intspec[1]; *out_type = 0; return 0; @@ -209,22 +197,13 @@ static unsigned int exynos4x12_combiner_extra_irq(int group) } void __init combiner_init(void __iomem *combiner_base, - struct device_node *np) + struct device_node *np, + unsigned int max_nr) { int i, irq, irq_base; - unsigned int max_nr, nr_irq; + unsigned int nr_irq; - max_nr = max_combiner_nr(); - - if (np) { - if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { - pr_info("%s: number of combiners not specified, " - "setting default as %d.\n", - __func__, max_nr); - } - } - - nr_irq = max_nr * MAX_IRQ_IN_COMBINER; + nr_irq = max_nr * IRQ_IN_COMBINER; irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); if (IS_ERR_VALUE(irq_base)) { @@ -258,6 +237,7 @@ static int __init combiner_of_init(struct device_node *np, struct device_node *parent) { void __iomem *combiner_base; + unsigned int max_nr = 20; combiner_base = of_iomap(np, 0); if (!combiner_base) { @@ -265,7 +245,13 @@ static int __init combiner_of_init(struct device_node *np, return -ENXIO; } - combiner_init(combiner_base, np); + if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { + pr_info("%s: number of combiners not specified, " + "setting default as %d.\n", + __func__, max_nr); + } + + combiner_init(combiner_base, np, max_nr); return 0; } -- cgit v1.2.3 From 863a08dc8bc7ce32ecc9136671610a93a0dd68b1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 12 Apr 2013 15:27:09 +0200 Subject: irqchip: exynos: pass irq_base from platform The platform code knows the IRQ base, while the irqchip driver should really not. This is a littly hacky because we still hardwire the IRQ base to 160 for the combiner in the DT case, when we should really use -1. Removing that line will cause a linear IRQ domain to be use, as we should. Signed-off-by: Arnd Bergmann Cc: Thomas Gleixner --- arch/arm/mach-exynos/common.c | 3 ++- arch/arm/mach-exynos/common.h | 2 +- drivers/irqchip/exynos-combiner.c | 23 +++++++++++++---------- 3 files changed, 16 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 368fa4b01e7c..9208079d5d52 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -447,7 +447,8 @@ void __init exynos4_init_irq(void) #endif if (!of_have_populated_dt()) - combiner_init(S5P_VA_COMBINER_BASE, NULL, max_combiner_nr()); + combiner_init(S5P_VA_COMBINER_BASE, NULL, + max_combiner_nr(), COMBINER_IRQ(0, 0)); /* * The parameters of s5p_init_irq() are for VIC init. diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 4ba8cbecc144..3e72d03a385e 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -70,7 +70,7 @@ void exynos4212_register_clocks(void); struct device_node; void combiner_init(void __iomem *combiner_base, struct device_node *np, - unsigned int max_nr); + unsigned int max_nr, int irq_base); extern struct smp_operations exynos_smp_ops; diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index acb9c74b070a..6855c92c2262 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -206,27 +206,22 @@ static unsigned int combiner_lookup_irq(int group) void __init combiner_init(void __iomem *combiner_base, struct device_node *np, - unsigned int max_nr) + unsigned int max_nr, + int irq_base) { - int i, irq, irq_base; + int i, irq; unsigned int nr_irq; struct combiner_chip_data *combiner_data; nr_irq = max_nr * IRQ_IN_COMBINER; - irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); - if (IS_ERR_VALUE(irq_base)) { - irq_base = COMBINER_IRQ(0, 0); - pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base); - } - combiner_data = kcalloc(max_nr, sizeof (*combiner_data), GFP_KERNEL); if (!combiner_data) { pr_warning("%s: could not allocate combiner data\n", __func__); return; } - combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0, + combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base, &combiner_irq_domain_ops, combiner_data); if (WARN_ON(!combiner_irq_domain)) { pr_warning("%s: irq domain init failed\n", __func__); @@ -253,6 +248,7 @@ static int __init combiner_of_init(struct device_node *np, { void __iomem *combiner_base; unsigned int max_nr = 20; + int irq_base = -1; combiner_base = of_iomap(np, 0); if (!combiner_base) { @@ -266,7 +262,14 @@ static int __init combiner_of_init(struct device_node *np, __func__, max_nr); } - combiner_init(combiner_base, np, max_nr); + /* + * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices + * get their IRQ from DT, remove this in order to get dynamic + * allocation. + */ + irq_base = 160; + + combiner_init(combiner_base, np, max_nr, irq_base); return 0; } -- cgit v1.2.3 From 278c800ec4bfcf26b76077e96f155c5b956bd1ad Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 23 Apr 2013 17:46:31 +0200 Subject: ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos This patch removes legacy PWM timer interrupt initialization from exynos{4,5}_init_irq() functions, since it conflicts with internal interrupt handling of the new PWM clocksource driver. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Arnd Bergmann Acked-by: Kukjin Kim Signed-off-by: Olof Johansson --- arch/arm/mach-exynos/common.c | 15 --------------- arch/arm/plat-samsung/Kconfig | 4 ++-- 2 files changed, 2 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d63d399c7bae..8abf2b6b98c6 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -456,13 +456,6 @@ void __init exynos4_init_irq(void) if (!of_have_populated_dt()) combiner_init(S5P_VA_COMBINER_BASE, NULL); - - /* - * The parameters of s5p_init_irq() are for VIC init. - * Theses parameters should be NULL and 0 because EXYNOS4 - * uses GIC instead of VIC. - */ - s5p_init_irq(NULL, 0); } void __init exynos5_init_irq(void) @@ -470,14 +463,6 @@ void __init exynos5_init_irq(void) #ifdef CONFIG_OF irqchip_init(); #endif - /* - * The parameters of s5p_init_irq() are for VIC init. - * Theses parameters should be NULL and 0 because EXYNOS4 - * uses GIC instead of VIC. - */ - if (!of_machine_is_compatible("samsung,exynos5440")) - s5p_init_irq(NULL, 0); - gic_arch_extn.irq_set_wake = s3c_irq_wake; } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a9d52167e16e..2e1b1905ac3a 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -101,9 +101,9 @@ config SAMSUNG_IRQ_VIC_TIMER Internal configuration to build the VIC timer interrupt code. config S5P_IRQ - def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) + def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) help - Support common interrup part for ARCH_S5P and ARCH_EXYNOS SoCs + Support common interrupt part for ARCH_S5P SoCs config S5P_EXT_INT bool -- cgit v1.2.3 From cc4193eaca1b3bed1da5bed18742386b21295b9a Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 23 Apr 2013 17:46:33 +0200 Subject: ARM: dts: exynos4: Add node for PWM device This patch adds device tree node for PWM block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Arnd Bergmann Acked-by: Kukjin Kim Signed-off-by: Olof Johansson --- arch/arm/boot/dts/exynos4.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e1347fceb5bc..4b866659ae98 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -264,6 +264,14 @@ status = "disabled"; }; + pwm@139D0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139D0000 0x1000>; + interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; + #pwm-cells = <2>; + status = "disabled"; + }; + amba { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 765d012c2389cc0481f04dcccd3949f1ba0969ba Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Tue, 23 Apr 2013 17:46:34 +0200 Subject: ARM: dts: exynos4210: Add basic dts file for universal_c210 board This patch adds basic device tree sources for Universal C210 board. Currently support includes: - eMMC - serial - max8952 and max8998 voltage regulators. - gpio-keys More support will be added in further patches. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Arnd Bergmann Acked-by: Kukjin Kim Signed-off-by: Olof Johansson --- arch/arm/boot/dts/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c6255884cbb..ff48893d621c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ + exynos4210-universal_c210.dtb \ exynos4412-smdk4412.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ -- cgit v1.2.3 From 0682edaaa32c778ad2efac73fe3c8d9309e35991 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Mon, 29 Apr 2013 10:28:57 -0700 Subject: ARM: dts: exynops4210: really add universal_c210 dts I fumbled when resolving a merge conflict on application of commit 765d012c2389 (ARM: dts: exynos4210: Add basic dts file for universal_c210 board), and left out the dts source file. Here it is. Signed-off-by: Olof Johansson --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 352 ++++++++++++++++++++++++ 1 file changed, 352 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4210-universal_c210.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts new file mode 100644 index 000000000000..345cdb51dcb7 --- /dev/null +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -0,0 +1,352 @@ +/* + * Samsung's Exynos4210 based Universal C210 board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Universal C210 board which is based on + * Samsung's Exynos4210 rev0 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ "exynos4210.dtsi" + +/ { + model = "Samsung Universal C210 based on Exynos4210 rev0"; + compatible = "samsung,universal_c210", "samsung,exynos4210"; + + memory { + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; + }; + + mct@10050000 { + compatible = "none"; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + vemmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2_8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe1 3 0>; + enable-active-high; + }; + + sdhci_emmc: sdhci@12510000 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; + pinctrl-names = "default"; + vmmc-supply = <&vemmc_reg>; + status = "okay"; + }; + + serial@13800000 { + status = "okay"; + }; + + serial@13810000 { + status = "okay"; + }; + + serial@13820000 { + status = "okay"; + }; + + serial@13830000 { + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + vol-up-key { + gpios = <&gpx2 0 1>; + linux,code = <115>; + label = "volume up"; + debounce-interval = <1>; + }; + + vol-down-key { + gpios = <&gpx2 1 1>; + linux,code = <114>; + label = "volume down"; + debounce-interval = <1>; + }; + + config-key { + gpios = <&gpx2 2 1>; + linux,code = <171>; + label = "config"; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + camera-key { + gpios = <&gpx2 3 1>; + linux,code = <212>; + label = "camera"; + debounce-interval = <1>; + }; + + power-key { + gpios = <&gpx2 7 1>; + linux,code = <116>; + label = "power"; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + ok-key { + gpios = <&gpx3 5 1>; + linux,code = <352>; + label = "ok"; + debounce-interval = <1>; + }; + }; + + tsp_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "TSP_2_8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 3 0>; + enable-active-high; + }; + + i2c@13890000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + tsp@4a { + /* TBD: Atmel maXtouch touchscreen */ + reg = <0x4a>; + }; + }; + + i2c@138B0000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + status = "okay"; + + vdd_arm_reg: pmic@60 { + compatible = "maxim,max8952"; + reg = <0x60>; + + max8952,vid-gpios = <&gpx0 3 0>, <&gpx0 4 0>; + max8952,default-mode = <0>; + max8952,dvs-mode-microvolt = <1250000>, <1200000>, + <1050000>, <950000>; + max8952,sync-freq = <0>; + max8952,ramp-speed = <0>; + + regulator-name = "vdd_arm"; + regulator-min-microvolt = <770000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + pmic@66 { + compatible = "national,lp3974"; + reg = <0x66>; + + max8998,pmic-buck1-default-dvs-idx = <0>; + max8998,pmic-buck1-dvs-gpios = <&gpx0 5 0>, + <&gpx0 6 0>; + max8998,pmic-buck1-dvs-voltage = <1100000>, <1000000>, + <1100000>, <1000000>; + + max8998,pmic-buck2-default-dvs-idx = <0>; + max8998,pmic-buck2-dvs-gpio = <&gpe2 0 0>; + max8998,pmic-buck2-dvs-voltage = <1200000>, <1100000>; + + regulators { + ldo2_reg: LDO2 { + regulator-name = "VALIVE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VUSB+MIPI_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VLCD+VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VCC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "CAM_AF_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo12_reg: LDO12 { + regulator-name = "PS_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VHIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "CAM_I_HOST_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "CAM_S_DIG+FM33_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "CAM_S_ANA_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VINT_1.1V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VG3D_1.1V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + + cp32khz_reg: EN32KHz-CP { + regulator-name = "32KHz CP"; + }; + + vichg_reg: ENVICHG { + regulator-name = "VICHG"; + }; + + safeout1_reg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + regulator-always-on; + }; + + safeout2_reg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + }; + }; + }; + + pwm@139D0000 { + compatible = "samsung,s5p6440-pwm"; + status = "okay"; + }; +}; -- cgit v1.2.3