From 352bfbb3e0230c96b2bce00d2ac3f0de303cc7b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Dec 2020 19:54:57 +0100 Subject: soc: samsung: exynos-chipid: convert to driver and merge exynos-asv The Exynos Chip ID driver on Exynos SoCs has so far only informational purpose - to expose the SoC device in sysfs. No other drivers depend on it so there is really no benefit of initializing it early. The code would be the most flexible if converted to a regular driver. However there is already another driver - Exynos ASV (Adaptive Supply Voltage) - which binds to the device node of Chip ID. The solution is to convert the Exynos Chip ID to a built in driver and merge the Exynos ASV into it. This has several benefits: 1. Although the Exynos ASV driver binds to a device node present in all Exynos DTS (generic compatible), it fails to probe except on the supported ones (only Exynos5422). This means that the regular boot process has a planned/normal device probe failure. Merging the ASV into Chip ID will remove this probe failure because the final driver will always bind, just with disabled ASV features. 2. Allows to use dev_info() as the SoC bus is present (since core_initcall). 3. Could speed things up because of execution of Chip ID code in a SMP environment (after bringing up secondary CPUs, unlike early_initcall), This reduces the amount of work to be done early, when the kernel has to bring up critical devices. 5. Makes the Chip ID code defer-probe friendly, Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201207190517.262051-5-krzk@kernel.org Reviewed-by: Pankaj Dubey --- arch/arm/mach-exynos/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 56d272967fc0..5a48abac6af4 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS select ARM_GIC select EXYNOS_IRQ_COMBINER select COMMON_CLK_SAMSUNG - select EXYNOS_ASV select EXYNOS_CHIPID select EXYNOS_THERMAL select EXYNOS_PMU -- cgit v1.2.3 From c7e73b5051d672a707cc52195b761e2bc76dade0 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 9 Dec 2020 13:20:51 +0100 Subject: ARM: imx: mach-imx6ul: remove 14x14 EVK specific PHY fixup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove board specific PHY fixup introduced by commit: | 709bc0657fe6f9f5 ("ARM: imx6ul: add fec MAC refrence clock and phy fixup init") This fixup addresses boards with a specific configuration: a KSZ8081RNA PHY with attached clock source to XI (Pin 8) of the PHY equal to 50MHz. For the KSZ8081RND PHY, the meaning of the reg 0x1F bit 7 is different (compared to the KSZ8081RNA). A set bit means: - KSZ8081RNA: clock input to XI (Pin 8) is 50MHz for RMII - KSZ8081RND: clock input to XI (Pin 8) is 25MHz for RMII In other configurations, for example a KSZ8081RND PHY or a KSZ8081RNA with 25Mhz clock source, the PHY will glitch and stay in not recoverable state. It is not possible to detect the clock source frequency of the PHY. And it is not possible to automatically detect KSZ8081 PHY variant - both have same PHY ID. It is not possible to overwrite the fixup configuration by providing proper device tree description. The only way is to remove this fixup. If this patch breaks network functionality on your board, fix it by adding PHY node with following properties: ethernet-phy@x { ... micrel,led-mode = <1>; clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; ... }; The board which was referred in the initial patch is already fixed. See: arch/arm/boot/dts/imx6ul-14x14-evk.dtsi Signed-off-by: Oleksij Rempel Reviewed-by: Fabio Estevam Tested-by: Sébastien Szymanski Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6ul.c | 21 --------------------- 1 file changed, 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index e018e716735f..eabcd35c01a5 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -27,30 +27,9 @@ static void __init imx6ul_enet_clk_init(void) pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n"); } -static int ksz8081_phy_fixup(struct phy_device *dev) -{ - if (dev && dev->interface == PHY_INTERFACE_MODE_MII) { - phy_write(dev, 0x1f, 0x8110); - phy_write(dev, 0x16, 0x201); - } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) { - phy_write(dev, 0x1f, 0x8190); - phy_write(dev, 0x16, 0x202); - } - - return 0; -} - -static void __init imx6ul_enet_phy_init(void) -{ - if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, - ksz8081_phy_fixup); -} - static inline void imx6ul_enet_init(void) { imx6ul_enet_clk_init(); - imx6ul_enet_phy_init(); } static void __init imx6ul_init_machine(void) -- cgit v1.2.3 From fbaff050bb092836912b195459ca915b5fea8952 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Wed, 9 Dec 2020 18:20:23 +0100 Subject: ARM: mach-imx: imx6ul: Print SOC revision on boot Add the print of the CPU type and SOC revision during boot. Signed-off-by: Stefan Riedmueller Signed-off-by: Robert Karszniewicz Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6ul.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index eabcd35c01a5..35e81201cb5d 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -14,6 +14,7 @@ #include "common.h" #include "cpuidle.h" +#include "hardware.h" static void __init imx6ul_enet_clk_init(void) { @@ -34,6 +35,9 @@ static inline void imx6ul_enet_init(void) static void __init imx6ul_init_machine(void) { + imx_print_silicon_rev(cpu_is_imx6ull() ? "i.MX6ULL" : "i.MX6UL", + imx_get_soc_revision()); + of_platform_default_populate(NULL, NULL, NULL); imx6ul_enet_init(); imx_anatop_init(); -- cgit v1.2.3 From 680ae44526ea9b656238ac768c8b6130961a0bdb Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 12 Jan 2021 16:50:31 +0300 Subject: ARM: tegra: Don't enable unused PLLs on resume from suspend PLLC and PLLM are usually disabled on system suspend because all devices which use these PLLs are either suspended or switched away to other clock source. Don't enable unused PLLs on resume from suspend by keeping track of the enable-state of the PLLs across suspend-resume. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Tested-by: Matt Merhar Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/sleep-tegra20.S | 38 +++++++++++++-- arch/arm/mach-tegra/sleep-tegra30.S | 94 +++++++++++++++++++++++++++++-------- 2 files changed, 108 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index 0e00ba8cf646..a5a36cce142a 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -43,11 +43,34 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 -.macro pll_enable, rd, r_car_base, pll_base +#define PLLC_STORE_MASK (1 << 0) +#define PLLM_STORE_MASK (1 << 1) +#define PLLP_STORE_MASK (1 << 2) + +.macro test_pll_state, rd, test_mask + ldr \rd, tegra_pll_state + tst \rd, #\test_mask +.endm + +.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 30) + ldr \rd, tegra_pll_state + biceq \rd, \rd, #\pll_mask + orrne \rd, \rd, #\pll_mask + adr \tmp, tegra_pll_state + str \rd, [\tmp] +.endm + +.macro pll_enable, rd, r_car_base, pll_base, test_mask + test_pll_state \rd, \test_mask + beq 1f + ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) orreq \rd, \rd, #(1 << 30) streq \rd, [\r_car_base, #\pll_base] +1: .endm .macro emc_device_mask, rd, base @@ -177,9 +200,9 @@ ENTRY(tegra20_lp1_reset) str r1, [r0, #CLK_RESET_CCLK_DIVIDER] str r1, [r0, #CLK_RESET_SCLK_DIVIDER] - pll_enable r1, r0, CLK_RESET_PLLM_BASE - pll_enable r1, r0, CLK_RESET_PLLP_BASE - pll_enable r1, r0, CLK_RESET_PLLC_BASE + pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK adr r2, tegra20_sdram_pad_address adr r4, tegra20_sdram_pad_save @@ -270,6 +293,10 @@ tegra20_switch_cpu_to_clk32k: add r1, r1, #2 wait_until r1, r7, r9 + store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + /* disable PLLM, PLLP and PLLC */ ldr r0, [r5, #CLK_RESET_PLLM_BASE] bic r0, r0, #(1 << 30) @@ -396,6 +423,9 @@ tegra20_sdram_pad_save: .long 0 .endr +tegra_pll_state: + .word 0x0 + .ltorg /* dummy symbol for end of IRAM */ .align L1_CACHE_SHIFT diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 2667bcdb5dc6..0cc40b6b2ba3 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -71,6 +71,13 @@ #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ +#define PLLA_STORE_MASK (1 << 0) +#define PLLC_STORE_MASK (1 << 1) +#define PLLM_STORE_MASK (1 << 2) +#define PLLP_STORE_MASK (1 << 3) +#define PLLX_STORE_MASK (1 << 4) +#define PLLM_PMC_STORE_MASK (1 << 5) + .macro emc_device_mask, rd, base ldr \rd, [\base, #EMC_ADR_CFG] tst \rd, #0x1 @@ -87,7 +94,43 @@ bne 1001b .endm -.macro pll_enable, rd, r_car_base, pll_base, pll_misc +.macro test_pll_state, rd, test_mask + ldr \rd, tegra_pll_state + tst \rd, #\test_mask +.endm + +.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask + ldr \rd, [\r_car_base, #\pll_base] + tst \rd, #(1 << 30) + ldr \rd, tegra_pll_state + biceq \rd, \rd, #\pll_mask + orrne \rd, \rd, #\pll_mask + adr \tmp, tegra_pll_state + str \rd, [\tmp] +.endm + +.macro store_pllm_pmc_state, rd, tmp, pmc_base + ldr \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] + tst \rd, #(1 << 12) + ldr \rd, tegra_pll_state + biceq \rd, \rd, #PLLM_PMC_STORE_MASK + orrne \rd, \rd, #PLLM_PMC_STORE_MASK + adr \tmp, tegra_pll_state + str \rd, [\tmp] +.endm + +.macro pllm_pmc_enable, rd, pmc_base + test_pll_state \rd, PLLM_PMC_STORE_MASK + + ldrne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] + orrne \rd, \rd, #(1 << 12) + strne \rd, [\pmc_base, #PMC_PLLP_WB0_OVERRIDE] +.endm + +.macro pll_enable, rd, r_car_base, pll_base, pll_misc, test_mask + test_pll_state \rd, \test_mask + beq 1f + ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30) orreq \rd, \rd, #(1 << 30) @@ -102,13 +145,17 @@ orr \rd, \rd, #(1 << 18) str \rd, [\r_car_base, #\pll_misc] .endif +1: .endm -.macro pll_locked, rd, r_car_base, pll_base +.macro pll_locked, rd, r_car_base, pll_base, test_mask + test_pll_state \rd, \test_mask + beq 2f 1: ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 27) beq 1b +2: .endm .macro pll_iddq_exit, rd, car, iddq, iddq_bit @@ -342,34 +389,30 @@ ENTRY(tegra30_lp1_reset) /* enable PLLM via PMC */ mov32 r2, TEGRA_PMC_BASE - ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] - orr r1, r1, #(1 << 12) - str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + pllm_pmc_enable r1, r2 - pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0 - pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0 - pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0 + pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0, PLLM_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0, PLLC_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0, PLLX_STORE_MASK b _pll_m_c_x_done _no_pll_iddq_exit: /* enable PLLM via PMC */ mov32 r2, TEGRA_PMC_BASE - ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE] - orr r1, r1, #(1 << 12) - str r1, [r2, #PMC_PLLP_WB0_OVERRIDE] + pllm_pmc_enable r1, r2 - pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC - pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC + pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC, PLLM_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC, PLLC_STORE_MASK _pll_m_c_x_done: - pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC - pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC + pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC, PLLP_STORE_MASK + pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC, PLLA_STORE_MASK - pll_locked r1, r0, CLK_RESET_PLLM_BASE - pll_locked r1, r0, CLK_RESET_PLLP_BASE - pll_locked r1, r0, CLK_RESET_PLLA_BASE - pll_locked r1, r0, CLK_RESET_PLLC_BASE + pll_locked r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + pll_locked r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + pll_locked r1, r0, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK + pll_locked r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK /* * CPUFreq driver could select other PLL for CPU. PLLX will be @@ -380,7 +423,7 @@ _pll_m_c_x_done: cmp r1, #TEGRA30 beq 1f - pll_locked r1, r0, CLK_RESET_PLLX_BASE + pll_locked r1, r0, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK ldr r1, [r0, #CLK_RESET_PLLP_BASE] bic r1, r1, #(1<<31) @ disable PllP bypass @@ -593,6 +636,9 @@ tegra_sdram_pad_save: .long 0 .endr +tegra_pll_state: + .word 0x0 + /* * tegra30_tear_down_core * @@ -641,6 +687,14 @@ tegra30_switch_cpu_to_clk32k: add r1, r1, #2 wait_until r1, r7, r9 + /* store enable-state of PLLs */ + store_pll_state r0, r1, r5, CLK_RESET_PLLA_BASE, PLLA_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK + store_pll_state r0, r1, r5, CLK_RESET_PLLX_BASE, PLLX_STORE_MASK + store_pllm_pmc_state r0, r1, r4 + /* disable PLLM via PMC in LP1 */ ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] bic r0, r0, #(1 << 12) -- cgit v1.2.3 From d5d5b7f3e2ad4b7c7c80c6a4d5686fe8a9624947 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 20 Jan 2021 12:01:53 -0800 Subject: ARM: brcmstb: Add debug UART entry for 72116 72116 has the same memory map as 7255 and the same physical address for the UART, alias the definition accordingly. Reviewed-by: Linus Walleij Signed-off-by: Florian Fainelli --- arch/arm/include/debug/brcmstb.S | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 0ff32ffc610c..f684e3a815f6 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -25,6 +25,7 @@ #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000) #define UARTA_3390 REG_PHYS_ADDR(0x40a900) +#define UARTA_72116 UARTA_7255 #define UARTA_7250 REG_PHYS_ADDR(0x40b400) #define UARTA_7255 REG_PHYS_ADDR(0x40c000) #define UARTA_7260 UARTA_7255 @@ -85,20 +86,21 @@ ARM_BE8( rev \rv, \rv ) /* Chip specific detection starts here */ 20: checkuart(\rp, \rv, 0x33900000, 3390) -21: checkuart(\rp, \rv, 0x72160000, 7216) -22: checkuart(\rp, \rv, 0x07216400, 72164) -23: checkuart(\rp, \rv, 0x07216500, 72165) -24: checkuart(\rp, \rv, 0x72500000, 7250) -25: checkuart(\rp, \rv, 0x72550000, 7255) -26: checkuart(\rp, \rv, 0x72600000, 7260) -27: checkuart(\rp, \rv, 0x72680000, 7268) -28: checkuart(\rp, \rv, 0x72710000, 7271) -29: checkuart(\rp, \rv, 0x72780000, 7278) -30: checkuart(\rp, \rv, 0x73640000, 7364) -31: checkuart(\rp, \rv, 0x73660000, 7366) -32: checkuart(\rp, \rv, 0x07437100, 74371) -33: checkuart(\rp, \rv, 0x74390000, 7439) -34: checkuart(\rp, \rv, 0x74450000, 7445) +21: checkuart(\rp, \rv, 0x07211600, 72116) +22: checkuart(\rp, \rv, 0x72160000, 7216) +23: checkuart(\rp, \rv, 0x07216400, 72164) +24: checkuart(\rp, \rv, 0x07216500, 72165) +25: checkuart(\rp, \rv, 0x72500000, 7250) +26: checkuart(\rp, \rv, 0x72550000, 7255) +27: checkuart(\rp, \rv, 0x72600000, 7260) +28: checkuart(\rp, \rv, 0x72680000, 7268) +29: checkuart(\rp, \rv, 0x72710000, 7271) +30: checkuart(\rp, \rv, 0x72780000, 7278) +31: checkuart(\rp, \rv, 0x73640000, 7364) +32: checkuart(\rp, \rv, 0x73660000, 7366) +33: checkuart(\rp, \rv, 0x07437100, 74371) +34: checkuart(\rp, \rv, 0x74390000, 7439) +35: checkuart(\rp, \rv, 0x74450000, 7445) /* No valid UART found */ 90: mov \rp, #0 -- cgit v1.2.3 From 5674e314e674d5a7c4d38d8e9beed14b91ef04d3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 11 Jan 2021 15:22:55 +0100 Subject: ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835 The BCM2711 has a number of instances of interrupt controllers handled by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2). Let's select that driver as part of the ARCH_BCM2835 Kconfig option. Signed-off-by: Maxime Ripard Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20210111142309.193441-1-maxime@cerno.tech --- arch/arm/mach-bcm/Kconfig | 1 + arch/arm64/Kconfig.platforms | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 9b594ae98153..2890e61b2b46 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -161,6 +161,7 @@ config ARCH_BCM2835 select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select BCM2835_TIMER + select BRCMSTB_L2_IRQ select PINCTRL select PINCTRL_BCM2835 select MFD_CORE diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6eecdef538bd..04c0c842c3e9 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -39,6 +39,7 @@ config ARCH_BCM2835 select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select BRCMSTB_L2_IRQ help This enables support for the Broadcom BCM2837 and BCM2711 SoC. These SoCs are used in the Raspberry Pi 3 and 4 devices. -- cgit v1.2.3 From 320f6f90cbe4818cf0d0f9441772d23aa441c506 Mon Sep 17 00:00:00 2001 From: Wang Qing Date: Thu, 17 Sep 2020 15:49:35 +0800 Subject: ARM: OMAP2+: fix spellint typo Change the comment typo: "ununsed" -> "unused". Signed-off-by: Wang Qing Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clockdomain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index dedd47e30b98..1feb0098705e 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -1299,7 +1299,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) * Due to a suspend or hibernation operation, the state of the registers * controlling this clkdm will be lost, save their context. */ -static int _clkdm_save_context(struct clockdomain *clkdm, void *ununsed) +static int _clkdm_save_context(struct clockdomain *clkdm, void *unused) { if (!arch_clkdm || !arch_clkdm->clkdm_save_context) return -EINVAL; @@ -1312,7 +1312,7 @@ static int _clkdm_save_context(struct clockdomain *clkdm, void *ununsed) * * Restore the register values for this clockdomain. */ -static int _clkdm_restore_context(struct clockdomain *clkdm, void *ununsed) +static int _clkdm_restore_context(struct clockdomain *clkdm, void *unused) { if (!arch_clkdm || !arch_clkdm->clkdm_restore_context) return -EINVAL; -- cgit v1.2.3 From 579c6f925e5ae3a70ec32e936908066707dbfef5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 18 Jan 2021 21:42:51 -0300 Subject: ARM: imx: Remove unused IMX_GPIO_NR() macro The IMX_GPIO_NR() macro was only used by non-DT i.MX platforms. As i.MX transitioned to a DT-only platform, get rid of this unused macro. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/hardware.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 7acf7ce467ed..0760fff39a0b 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -106,8 +106,4 @@ .type = _type, \ } -/* There's an off-by-one between the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ -- cgit v1.2.3 From 7f9942c61fa60eda7cc8e42f04bd25b7d175876e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 4 Feb 2021 17:23:42 +0100 Subject: ARM: s3c: fix fiq for clang IAS Building with the clang integrated assembler produces a couple of errors for the s3c24xx fiq support: arch/arm/mach-s3c/irq-s3c24xx-fiq.S:52:2: error: instruction 'subne' can not set flags, but 's' suffix specified subnes pc, lr, #4 @@ return, still have work to do arch/arm/mach-s3c/irq-s3c24xx-fiq.S:64:1: error: invalid symbol redefinition s3c24xx_spi_fiq_txrx: There are apparently two problems: one with extraneous or duplicate labels, and one with old-style opcode mnemonics. Stefan Agner has previously fixed other problems like this, but missed this particular file. Fixes: bec0806cfec6 ("spi_s3c24xx: add FIQ pseudo-DMA support") Cc: Stefan Agner Signed-off-by: Arnd Bergmann Reviewed-by: Nick Desaulniers Reviewed-by: Nathan Chancellor Link: https://lore.kernel.org/r/20210204162416.3030114-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-s3c/irq-s3c24xx-fiq.S | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S index b54cbd012241..5d238d9a798e 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S +++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S @@ -35,7 +35,6 @@ @ and an offset to the irq acknowledgment word ENTRY(s3c24xx_spi_fiq_rx) -s3c24xx_spi_fix_rx: .word fiq_rx_end - fiq_rx_start .word fiq_rx_irq_ack - fiq_rx_start fiq_rx_start: @@ -49,7 +48,7 @@ fiq_rx_start: strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do + subsne pc, lr, #4 @@ return, still have work to do @@ set IRQ controller so that next op will trigger IRQ mov fiq_rtmp, #0 @@ -61,7 +60,6 @@ fiq_rx_irq_ack: fiq_rx_end: ENTRY(s3c24xx_spi_fiq_txrx) -s3c24xx_spi_fiq_txrx: .word fiq_txrx_end - fiq_txrx_start .word fiq_txrx_irq_ack - fiq_txrx_start fiq_txrx_start: @@ -76,7 +74,7 @@ fiq_txrx_start: strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do + subsne pc, lr, #4 @@ return, still have work to do mov fiq_rtmp, #0 str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] @@ -88,7 +86,6 @@ fiq_txrx_irq_ack: fiq_txrx_end: ENTRY(s3c24xx_spi_fiq_tx) -s3c24xx_spi_fix_tx: .word fiq_tx_end - fiq_tx_start .word fiq_tx_irq_ack - fiq_tx_start fiq_tx_start: @@ -101,7 +98,7 @@ fiq_tx_start: strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] subs fiq_rcount, fiq_rcount, #1 - subnes pc, lr, #4 @@ return, still have work to do + subsne pc, lr, #4 @@ return, still have work to do mov fiq_rtmp, #0 str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] -- cgit v1.2.3 From 49dc85ca3c78d938d9eb41e05efcd85c92626e84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 6 Feb 2021 14:36:14 +0100 Subject: ARM: s3c: irq-s3c24xx: include headers for missing declarations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Include headers to fix W=1 build warnings: arch/arm/mach-s3c/irq-s3c24xx.c:389:5: warning: no previous prototype for ‘s3c24xx_set_fiq’ [-Wmissing-prototypes] arch/arm/mach-s3c/irq-s3c24xx.c:683:13: warning: no previous prototype for ‘s3c2410_init_irq’ [-Wmissing-prototypes] Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210206133615.119804-1-krzk@kernel.org --- arch/arm/mach-s3c/irq-s3c24xx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 79b5f19af7a5..3368159d3f3e 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -32,6 +33,7 @@ #include "cpu.h" #include "regs-irqtype.h" #include "pm.h" +#include "s3c24xx.h" #define S3C_IRQTYPE_NONE 0 #define S3C_IRQTYPE_EINT 1 -- cgit v1.2.3 From f503878564f5e68c1aeb1ea01e437060bf905c50 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 6 Feb 2021 14:36:15 +0100 Subject: ARM: s3c: irq-s3c24xx: staticize local functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make functions used only in this module static to fix W=1 build warnings: arch/arm/mach-s3c/irq-s3c24xx.c:360:39: warning: no previous prototype for ‘s3c24xx_handle_irq’ [-Wmissing-prototypes] arch/arm/mach-s3c/irq-s3c24xx.c:1308:12: warning: no previous prototype for ‘s3c2410_init_intc_of’ [-Wmissing-prototypes] arch/arm/mach-s3c/irq-s3c24xx.c:1330:12: warning: no previous prototype for ‘s3c2416_init_intc_of’ [-Wmissing-prototypes] Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210206133615.119804-2-krzk@kernel.org --- arch/arm/mach-s3c/irq-s3c24xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 3368159d3f3e..0c631c14a817 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -359,7 +359,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, return true; } -asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) +static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) { do { if (likely(s3c_intc[0])) @@ -1307,7 +1307,7 @@ static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { } }; -int __init s3c2410_init_intc_of(struct device_node *np, +static int __init s3c2410_init_intc_of(struct device_node *np, struct device_node *interrupt_parent) { return s3c_init_intc_of(np, interrupt_parent, @@ -1329,7 +1329,7 @@ static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { } }; -int __init s3c2416_init_intc_of(struct device_node *np, +static int __init s3c2416_init_intc_of(struct device_node *np, struct device_node *interrupt_parent) { return s3c_init_intc_of(np, interrupt_parent, -- cgit v1.2.3