From d1cb3ecf327066137fb6245b13030cde60241dd6 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 26 Nov 2013 19:44:18 +0000 Subject: ARM: plat-versatile: LEDs initialise to off state There really is no excuse to turn on all 8 LEDs at boot time, such that on the Versatile PB/926 we end up with 6 LEDs on continuously and forever. We're not a christmas decoration! Signed-off-by: Russell King Signed-off-by: Linus Walleij --- arch/arm/plat-versatile/leds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c index d2490d00b46c..2018f307f32e 100644 --- a/arch/arm/plat-versatile/leds.c +++ b/arch/arm/plat-versatile/leds.c @@ -72,8 +72,8 @@ static int __init versatile_leds_init(void) { int i; - /* All ON */ - writel(0xff, LEDREG); + /* All off */ + writel(0, LEDREG); for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) { struct versatile_led *led; -- cgit v1.2.3 From e4ecf2bda239ddef5f4edd0e05d48bfdf88a475d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 27 Feb 2014 14:29:22 +0100 Subject: ARM: plat-versatile: convert LEDs to platform device The LEDs were initialized unconditionally with an fs_initcall() which doesn't play well with multiplatform. Convert the driver to a platform device and convert all boards with these LEDs to register a platform device and pass the register as a resource instead. Tested successfully on the Versatile/AB and RealView PB1176. Cc: Bryan Wu Cc: Richard Purdie Cc: Russell King Cc: Pawel Moll Signed-off-by: Linus Walleij --- arch/arm/mach-realview/core.c | 15 ++++++++++ arch/arm/mach-realview/core.h | 1 + arch/arm/mach-realview/realview_eb.c | 1 + arch/arm/mach-realview/realview_pb1176.c | 1 + arch/arm/mach-realview/realview_pb11mp.c | 1 + arch/arm/mach-realview/realview_pba8.c | 1 + arch/arm/mach-realview/realview_pbx.c | 1 + arch/arm/mach-versatile/core.c | 16 +++++++++++ arch/arm/plat-versatile/leds.c | 49 ++++++++++++++++++-------------- 9 files changed, 65 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 1d5ee5c9a1dc..960b8dd78c44 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -148,6 +148,21 @@ struct platform_device realview_cf_device = { }, }; +static struct resource realview_leds_resources[] = { + { + .start = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET, + .end = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET + 4, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device realview_leds_device = { + .name = "versatile-leds", + .id = -1, + .num_resources = ARRAY_SIZE(realview_leds_resources), + .resource = realview_leds_resources, +}; + static struct resource realview_i2c_resource = { .start = REALVIEW_I2C_BASE, .end = REALVIEW_I2C_BASE + SZ_4K - 1, diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 602ca5ec52c5..13dc830ef469 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h @@ -37,6 +37,7 @@ struct machine_desc; extern struct platform_device realview_flash_device; extern struct platform_device realview_cf_device; +extern struct platform_device realview_leds_device; extern struct platform_device realview_i2c_device; extern struct mmci_platform_data realview_mmc0_plat_data; extern struct mmci_platform_data realview_mmc1_plat_data; diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index c85ddb2a0ad0..6bb070e80128 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c @@ -452,6 +452,7 @@ static void __init realview_eb_init(void) realview_flash_register(&realview_eb_flash_resource, 1); platform_device_register(&realview_i2c_device); platform_device_register(&char_lcd_device); + platform_device_register(&realview_leds_device); eth_device_register(); realview_usb_register(realview_eb_isp1761_resources); diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index c5eade76461b..173f2c15de49 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c @@ -367,6 +367,7 @@ static void __init realview_pb1176_init(void) realview_usb_register(realview_pb1176_isp1761_resources); platform_device_register(&pmu_device); platform_device_register(&char_lcd_device); + platform_device_register(&realview_leds_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index f4b0962578fe..bde7e6b1fd44 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c @@ -347,6 +347,7 @@ static void __init realview_pb11mp_init(void) realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); platform_device_register(&realview_i2c_device); platform_device_register(&realview_cf_device); + platform_device_register(&realview_leds_device); realview_usb_register(realview_pb11mp_isp1761_resources); platform_device_register(&pmu_device); diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 10a3e1d76891..4e57a8599265 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c @@ -289,6 +289,7 @@ static void __init realview_pba8_init(void) realview_eth_register(NULL, realview_pba8_smsc911x_resources); platform_device_register(&realview_i2c_device); platform_device_register(&realview_cf_device); + platform_device_register(&realview_leds_device); realview_usb_register(realview_pba8_isp1761_resources); platform_device_register(&pmu_device); diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index 9d75493e3f0c..72c96caebefa 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c @@ -385,6 +385,7 @@ static void __init realview_pbx_init(void) realview_eth_register(NULL, realview_pbx_smsc911x_resources); platform_device_register(&realview_i2c_device); platform_device_register(&realview_cf_device); + platform_device_register(&realview_leds_device); realview_usb_register(realview_pbx_isp1761_resources); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index a335126ae18f..b31878570a00 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -310,6 +310,21 @@ static struct platform_device char_lcd_device = { .resource = char_lcd_resources, }; +static struct resource leds_resources[] = { + { + .start = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET, + .end = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET + 4, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device leds_device = { + .name = "versatile-leds", + .id = -1, + .num_resources = ARRAY_SIZE(leds_resources), + .resource = leds_resources, +}; + /* * Clock handling */ @@ -795,6 +810,7 @@ void __init versatile_init(void) platform_device_register(&versatile_i2c_device); platform_device_register(&smc91x_device); platform_device_register(&char_lcd_device); + platform_device_register(&leds_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c index 2018f307f32e..80553022d661 100644 --- a/arch/arm/plat-versatile/leds.c +++ b/arch/arm/plat-versatile/leds.c @@ -7,22 +7,14 @@ */ #include #include +#include #include #include #include - -#include -#include - -#ifdef VERSATILE_SYS_BASE -#define LEDREG (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET) -#endif - -#ifdef REALVIEW_SYS_BASE -#define LEDREG (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET) -#endif +#include struct versatile_led { + void __iomem *base; struct led_classdev cdev; u8 mask; }; @@ -50,30 +42,37 @@ static void versatile_led_set(struct led_classdev *cdev, { struct versatile_led *led = container_of(cdev, struct versatile_led, cdev); - u32 reg = readl(LEDREG); + u32 reg = readl(led->base); if (b != LED_OFF) reg |= led->mask; else reg &= ~led->mask; - writel(reg, LEDREG); + writel(reg, led->base); } static enum led_brightness versatile_led_get(struct led_classdev *cdev) { struct versatile_led *led = container_of(cdev, struct versatile_led, cdev); - u32 reg = readl(LEDREG); + u32 reg = readl(led->base); return (reg & led->mask) ? LED_FULL : LED_OFF; } -static int __init versatile_leds_init(void) +static int versatile_leds_probe(struct platform_device *dev) { int i; + struct resource *res; + void __iomem *base; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&dev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); /* All off */ - writel(0, LEDREG); + writel(0, base); for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) { struct versatile_led *led; @@ -81,6 +80,7 @@ static int __init versatile_leds_init(void) if (!led) break; + led->base = base; led->cdev.name = versatile_leds[i].name; led->cdev.brightness_set = versatile_led_set; led->cdev.brightness_get = versatile_led_get; @@ -96,8 +96,15 @@ static int __init versatile_leds_init(void) return 0; } -/* - * Since we may have triggers on any subsystem, defer registration - * until after subsystem_init. - */ -fs_initcall(versatile_leds_init); +static struct platform_driver versatile_leds_driver = { + .driver = { + .name = "versatile-leds", + }, + .probe = versatile_leds_probe, +}; + +module_platform_driver(versatile_leds_driver); + +MODULE_AUTHOR("Linus Walleij "); +MODULE_DESCRIPTION("ARM Versatile LED driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 1dc7d8374dccf2815294ceb6a1092253f45ba860 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 27 Feb 2014 14:44:17 +0100 Subject: ARM/leds: move ARM Versatile LED driver to leds subsystem Now that we have converted this driver to a real platform device module-based thing, we move the driver down into the LEDs subsystem and rename the config option to LEDS_VERSATILE. Cc: Richard Purdie Cc: Russell King Cc: Pawel Moll Acked-by: Bryan Wu Signed-off-by: Linus Walleij --- arch/arm/plat-versatile/Kconfig | 6 --- arch/arm/plat-versatile/Makefile | 1 - arch/arm/plat-versatile/leds.c | 110 --------------------------------------- drivers/leds/Kconfig | 8 +++ drivers/leds/Makefile | 1 + drivers/leds/leds-versatile.c | 110 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 119 insertions(+), 117 deletions(-) delete mode 100644 arch/arm/plat-versatile/leds.c create mode 100644 drivers/leds/leds-versatile.c (limited to 'arch') diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig index 2c4332b9f948..fce41e93b6a4 100644 --- a/arch/arm/plat-versatile/Kconfig +++ b/arch/arm/plat-versatile/Kconfig @@ -6,12 +6,6 @@ config PLAT_VERSATILE_CLOCK config PLAT_VERSATILE_CLCD bool -config PLAT_VERSATILE_LEDS - def_bool y if NEW_LEDS - depends on ARCH_REALVIEW || ARCH_VERSATILE - select LEDS_CLASS - select LEDS_TRIGGERS - config PLAT_VERSATILE_SCHED_CLOCK def_bool y diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index f88d448b629c..2e0c472958ae 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile @@ -2,6 +2,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o -obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o obj-$(CONFIG_SMP) += headsmp.o platsmp.o diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c deleted file mode 100644 index 80553022d661..000000000000 --- a/arch/arm/plat-versatile/leds.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Driver for the 8 user LEDs found on the RealViews and Versatiles - * Based on DaVinci's DM365 board code - * - * License terms: GNU General Public License (GPL) version 2 - * Author: Linus Walleij - */ -#include -#include -#include -#include -#include -#include -#include - -struct versatile_led { - void __iomem *base; - struct led_classdev cdev; - u8 mask; -}; - -/* - * The triggers lines up below will only be used if the - * LED triggers are compiled in. - */ -static const struct { - const char *name; - const char *trigger; -} versatile_leds[] = { - { "versatile:0", "heartbeat", }, - { "versatile:1", "mmc0", }, - { "versatile:2", "cpu0" }, - { "versatile:3", "cpu1" }, - { "versatile:4", "cpu2" }, - { "versatile:5", "cpu3" }, - { "versatile:6", }, - { "versatile:7", }, -}; - -static void versatile_led_set(struct led_classdev *cdev, - enum led_brightness b) -{ - struct versatile_led *led = container_of(cdev, - struct versatile_led, cdev); - u32 reg = readl(led->base); - - if (b != LED_OFF) - reg |= led->mask; - else - reg &= ~led->mask; - writel(reg, led->base); -} - -static enum led_brightness versatile_led_get(struct led_classdev *cdev) -{ - struct versatile_led *led = container_of(cdev, - struct versatile_led, cdev); - u32 reg = readl(led->base); - - return (reg & led->mask) ? LED_FULL : LED_OFF; -} - -static int versatile_leds_probe(struct platform_device *dev) -{ - int i; - struct resource *res; - void __iomem *base; - - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&dev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - /* All off */ - writel(0, base); - for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) { - struct versatile_led *led; - - led = kzalloc(sizeof(*led), GFP_KERNEL); - if (!led) - break; - - led->base = base; - led->cdev.name = versatile_leds[i].name; - led->cdev.brightness_set = versatile_led_set; - led->cdev.brightness_get = versatile_led_get; - led->cdev.default_trigger = versatile_leds[i].trigger; - led->mask = BIT(i); - - if (led_classdev_register(NULL, &led->cdev) < 0) { - kfree(led); - break; - } - } - - return 0; -} - -static struct platform_driver versatile_leds_driver = { - .driver = { - .name = "versatile-leds", - }, - .probe = versatile_leds_probe, -}; - -module_platform_driver(versatile_leds_driver); - -MODULE_AUTHOR("Linus Walleij "); -MODULE_DESCRIPTION("ARM Versatile LED driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 72156c123033..93235f7378ba 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -487,6 +487,14 @@ config LEDS_BLINKM This option enables support for the BlinkM RGB LED connected through I2C. Say Y to enable support for the BlinkM LED. +config LEDS_VERSATILE + bool "LED support for the ARM Versatile and RealView" + depends on ARCH_REALVIEW || ARCH_VERSATILE + depends on LEDS_CLASS + help + This option enabled support for the LEDs on the ARM Versatile + and RealView boards. Say Y to enabled these. + comment "LED Triggers" source "drivers/leds/trigger/Kconfig" diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 3cd76dbd9be2..8b4c956e11ba 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_LEDS_ASIC3) += leds-asic3.o obj-$(CONFIG_LEDS_MAX8997) += leds-max8997.o obj-$(CONFIG_LEDS_LM355x) += leds-lm355x.o obj-$(CONFIG_LEDS_BLINKM) += leds-blinkm.o +obj-$(CONFIG_LEDS_VERSATILE) += leds-versatile.o # LED SPI Drivers obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/drivers/leds/leds-versatile.c b/drivers/leds/leds-versatile.c new file mode 100644 index 000000000000..80553022d661 --- /dev/null +++ b/drivers/leds/leds-versatile.c @@ -0,0 +1,110 @@ +/* + * Driver for the 8 user LEDs found on the RealViews and Versatiles + * Based on DaVinci's DM365 board code + * + * License terms: GNU General Public License (GPL) version 2 + * Author: Linus Walleij + */ +#include +#include +#include +#include +#include +#include +#include + +struct versatile_led { + void __iomem *base; + struct led_classdev cdev; + u8 mask; +}; + +/* + * The triggers lines up below will only be used if the + * LED triggers are compiled in. + */ +static const struct { + const char *name; + const char *trigger; +} versatile_leds[] = { + { "versatile:0", "heartbeat", }, + { "versatile:1", "mmc0", }, + { "versatile:2", "cpu0" }, + { "versatile:3", "cpu1" }, + { "versatile:4", "cpu2" }, + { "versatile:5", "cpu3" }, + { "versatile:6", }, + { "versatile:7", }, +}; + +static void versatile_led_set(struct led_classdev *cdev, + enum led_brightness b) +{ + struct versatile_led *led = container_of(cdev, + struct versatile_led, cdev); + u32 reg = readl(led->base); + + if (b != LED_OFF) + reg |= led->mask; + else + reg &= ~led->mask; + writel(reg, led->base); +} + +static enum led_brightness versatile_led_get(struct led_classdev *cdev) +{ + struct versatile_led *led = container_of(cdev, + struct versatile_led, cdev); + u32 reg = readl(led->base); + + return (reg & led->mask) ? LED_FULL : LED_OFF; +} + +static int versatile_leds_probe(struct platform_device *dev) +{ + int i; + struct resource *res; + void __iomem *base; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&dev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* All off */ + writel(0, base); + for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) { + struct versatile_led *led; + + led = kzalloc(sizeof(*led), GFP_KERNEL); + if (!led) + break; + + led->base = base; + led->cdev.name = versatile_leds[i].name; + led->cdev.brightness_set = versatile_led_set; + led->cdev.brightness_get = versatile_led_get; + led->cdev.default_trigger = versatile_leds[i].trigger; + led->mask = BIT(i); + + if (led_classdev_register(NULL, &led->cdev) < 0) { + kfree(led); + break; + } + } + + return 0; +} + +static struct platform_driver versatile_leds_driver = { + .driver = { + .name = "versatile-leds", + }, + .probe = versatile_leds_probe, +}; + +module_platform_driver(versatile_leds_driver); + +MODULE_AUTHOR("Linus Walleij "); +MODULE_DESCRIPTION("ARM Versatile LED driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 9b58d187fdce9df05fd331ad5790bf503d7e3dfe Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 27 Feb 2014 14:51:28 +0100 Subject: ARM: plat-versatile: update defconfigs for Versatile LEDs As we moved the Versatile LEDs to the LEDs subsystem and made it a module, the config options are no more default-selected. Make sure all users still experience LEDs properly by updating all RealView and Versatile defconfigs. Cc: Bryan Wu Cc: Richard Purdie Cc: Russell King Cc: Pawel Moll Signed-off-by: Linus Walleij --- arch/arm/configs/realview-smp_defconfig | 2 ++ arch/arm/configs/realview_defconfig | 2 ++ arch/arm/configs/versatile_defconfig | 3 +++ 3 files changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig index abe61bf379d2..1da5d9e48224 100644 --- a/arch/arm/configs/realview-smp_defconfig +++ b/arch/arm/configs/realview-smp_defconfig @@ -76,8 +76,10 @@ CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_VERSATILE=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PL031=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index 7079cbe898a8..d02e9d911bb7 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -75,8 +75,10 @@ CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_VERSATILE=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PL031=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 073541a50e23..d52b4ffe2012 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -61,6 +61,9 @@ CONFIG_SND_ARMAACI=m CONFIG_MMC=y CONFIG_MMC_ARMMMCI=m CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_VERSATILE=y +CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_EXT2_FS=y -- cgit v1.2.3 From 5f40f7d93898a473eb222aa8064144c1d6835470 Mon Sep 17 00:00:00 2001 From: Dimitri Sivanich Date: Mon, 31 Mar 2014 09:37:00 -0500 Subject: x86/UV: Set n_lshift based on GAM_GR_CONFIG MMR for UV3 The value of n_lshift for UV is currently set based on the socket m_val. For UV3, set the n_lshift value based on the GAM_GR_CONFIG MMR. This will allow bios to control the n_lshift value independent of the socket m_val. Then n_lshift can be assigned a fixed value across a multi-partition system, allowing for a fixed common global physical address format that is independent of socket m_val. Cleanup unneeded macros. Signed-off-by: Dimitri Sivanich Link: http://lkml.kernel.org/r/20140331143700.GB29916@sgi.com Signed-off-by: Ingo Molnar --- arch/x86/include/asm/uv/uv_hub.h | 12 +---------- arch/x86/include/asm/uv/uv_mmrs.h | 42 +++++++++++++++++++++++++++++++++++++- arch/x86/kernel/apic/x2apic_uv_x.c | 26 ++++++++++++++++++----- 3 files changed, 63 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index a30836c8ac4d..c63e925fd6b7 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h @@ -5,7 +5,7 @@ * * SGI UV architectural definitions * - * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_X86_UV_UV_HUB_H @@ -204,16 +204,6 @@ static inline int is_uvx_hub(void) return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; } -static inline int is_uv2_1_hub(void) -{ - return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE; -} - -static inline int is_uv2_2_hub(void) -{ - return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE + 1; -} - union uvh_apicid { unsigned long v; struct uvh_apicid_s { diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h index e42249bcf7e1..ddd8db6b6e70 100644 --- a/arch/x86/include/asm/uv/uv_mmrs.h +++ b/arch/x86/include/asm/uv/uv_mmrs.h @@ -5,7 +5,7 @@ * * SGI UV MMR definitions * - * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_X86_UV_UV_MMRS_H @@ -2802,6 +2802,46 @@ union uv1h_lb_target_physical_apic_id_mask_u { } s1; }; +/* ========================================================================= */ +/* UV3H_GR0_GAM_GR_CONFIG */ +/* ========================================================================= */ +#define UV3H_GR0_GAM_GR_CONFIG 0xc00028UL + +#define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0 +#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 +#define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL +#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL + +union uv3h_gr0_gam_gr_config_u { + unsigned long v; + struct uv3h_gr0_gam_gr_config_s { + unsigned long m_skt:6; /* RW */ + unsigned long undef_6_9:4; /* Undefined */ + unsigned long subspace:1; /* RW */ + unsigned long reserved:53; + } s3; +}; + +/* ========================================================================= */ +/* UV3H_GR1_GAM_GR_CONFIG */ +/* ========================================================================= */ +#define UV3H_GR1_GAM_GR_CONFIG 0x1000028UL + +#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_SHFT 0 +#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_SHFT 10 +#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL +#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL + +union uv3h_gr1_gam_gr_config_u { + unsigned long v; + struct uv3h_gr1_gam_gr_config_s { + unsigned long m_skt:6; /* RW */ + unsigned long undef_6_9:4; /* Undefined */ + unsigned long subspace:1; /* RW */ + unsigned long reserved:53; + } s3; +}; + /* ========================================================================= */ /* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ /* ========================================================================= */ diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 7834389ba5be..293b41df54ef 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -5,7 +5,7 @@ * * SGI UV APIC functions (note: not an Intel compatible APIC) * - * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. */ #include #include @@ -440,6 +440,20 @@ static __initdata struct redir_addr redir_addrs[] = { {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, }; +static unsigned char get_n_lshift(int m_val) +{ + union uv3h_gr0_gam_gr_config_u m_gr_config; + + if (is_uv1_hub()) + return m_val; + + if (is_uv2_hub()) + return m_val == 40 ? 40 : 39; + + m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); + return m_gr_config.s3.m_skt; +} + static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) { union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; @@ -849,6 +863,7 @@ void __init uv_system_init(void) int gnode_extra, min_pnode = 999999, max_pnode = -1; unsigned long mmr_base, present, paddr; unsigned short pnode_mask; + unsigned char n_lshift; char *hub = (is_uv1_hub() ? "UV1" : (is_uv2_hub() ? "UV2" : "UV3")); @@ -860,6 +875,7 @@ void __init uv_system_init(void) m_val = m_n_config.s.m_skt; n_val = m_n_config.s.n_skt; pnode_mask = (1 << n_val) - 1; + n_lshift = get_n_lshift(m_val); mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE; @@ -867,8 +883,9 @@ void __init uv_system_init(void) node_id.v = uv_read_local_mmr(UVH_NODE_ID); gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; gnode_upper = ((unsigned long)gnode_extra << m_val); - pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x\n", - n_val, m_val, pnode_mask, gnode_upper, gnode_extra); + pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n", + n_val, m_val, pnode_mask, gnode_upper, gnode_extra, + n_lshift); pr_info("UV: global MMR base 0x%lx\n", mmr_base); @@ -935,8 +952,7 @@ void __init uv_system_init(void) uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; - uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ? - (m_val == 40 ? 40 : 39) : m_val; + uv_cpu_hub_info(cpu)->n_lshift = n_lshift; pnode = uv_apicid_to_pnode(apicid); blade = boot_pnode_to_blade(pnode); -- cgit v1.2.3 From 0ea481466d1c7cbd9d8f70ddc17a443a6c6fc09b Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Fri, 4 Apr 2014 20:24:03 +0800 Subject: crypto: ghash-clmulni-intel - Use u128 instead of be128 for internal key The internal key isn't actually in big-endian format so let's switch to u128 which also happens to allow us to remove a sparse warning. Based on suggestion by Ard Biesheuvel. Signed-off-by: Herbert Xu Acked-by: Ard Biesheuvel --- arch/x86/crypto/ghash-clmulni-intel_asm.S | 4 ++-- arch/x86/crypto/ghash-clmulni-intel_glue.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/x86/crypto/ghash-clmulni-intel_asm.S b/arch/x86/crypto/ghash-clmulni-intel_asm.S index 185fad49d86f..5d1e0075ac24 100644 --- a/arch/x86/crypto/ghash-clmulni-intel_asm.S +++ b/arch/x86/crypto/ghash-clmulni-intel_asm.S @@ -92,7 +92,7 @@ __clmul_gf128mul_ble: ret ENDPROC(__clmul_gf128mul_ble) -/* void clmul_ghash_mul(char *dst, const be128 *shash) */ +/* void clmul_ghash_mul(char *dst, const u128 *shash) */ ENTRY(clmul_ghash_mul) movups (%rdi), DATA movups (%rsi), SHASH @@ -106,7 +106,7 @@ ENDPROC(clmul_ghash_mul) /* * void clmul_ghash_update(char *dst, const char *src, unsigned int srclen, - * const be128 *shash); + * const u128 *shash); */ ENTRY(clmul_ghash_update) cmp $16, %rdx diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c index d785cf2c529c..88bb7ba8b175 100644 --- a/arch/x86/crypto/ghash-clmulni-intel_glue.c +++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c @@ -25,17 +25,17 @@ #define GHASH_BLOCK_SIZE 16 #define GHASH_DIGEST_SIZE 16 -void clmul_ghash_mul(char *dst, const be128 *shash); +void clmul_ghash_mul(char *dst, const u128 *shash); void clmul_ghash_update(char *dst, const char *src, unsigned int srclen, - const be128 *shash); + const u128 *shash); struct ghash_async_ctx { struct cryptd_ahash *cryptd_tfm; }; struct ghash_ctx { - be128 shash; + u128 shash; }; struct ghash_desc_ctx { @@ -68,11 +68,11 @@ static int ghash_setkey(struct crypto_shash *tfm, a = be64_to_cpu(x->a); b = be64_to_cpu(x->b); - ctx->shash.a = (__be64)((b << 1) | (a >> 63)); - ctx->shash.b = (__be64)((a << 1) | (b >> 63)); + ctx->shash.a = (b << 1) | (a >> 63); + ctx->shash.b = (a << 1) | (b >> 63); if (a >> 63) - ctx->shash.b ^= cpu_to_be64(0xc2); + ctx->shash.b ^= ((u64)0xc2) << 56; return 0; } -- cgit v1.2.3 From 1668a7a699f8c96bc99a50e94aadfe328adf9b76 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Mar 2014 10:39:23 +0100 Subject: ARM: shmobile: armadillo800eva: Spelling and grammar Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0f92ba8e7884..edb1a914deb3 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -205,8 +205,8 @@ config MACH_ARMADILLO800EVA_REFERENCE select SND_SOC_WM8978 if SND_SIMPLE_CARD select USE_OF ---help--- - Use reference implementation of Aramdillo800 EVA board support - which makes a greater use of device tree at the expense + Use reference implementation of Armadillo800 EVA board support + which makes greater use of device tree at the expense of not supporting a number of devices. This is intended to aid developers -- cgit v1.2.3 From d477a4a2fcbf59feb617de9502ae8b862e1578ed Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:19 +0100 Subject: ARM: shmobile: multiplatform: Enable MSIOF in defconfig Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 83b07258a385..2a27d4622cc9 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -78,6 +78,7 @@ CONFIG_I2C_GPIO=y CONFIG_I2C_RCAR=y CONFIG_SPI=y CONFIG_SPI_RSPI=y +CONFIG_SPI_SH_MSIOF=y CONFIG_GPIO_EM=y CONFIG_GPIO_RCAR=y # CONFIG_HWMON is not set -- cgit v1.2.3 From c2e90c4b7c15fbb2215b47a23b446ba53e6dbf59 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 26 Mar 2014 14:16:19 +0900 Subject: ARM: shmobile: Include i2c-shmobile.c in shmobile_defconfig Many SoCs include I2C controller instances compatible with the i2c-shmobile.c driver. To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Signed-off-by: Magnus Damm Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 2a27d4622cc9..d96133a686e5 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -75,6 +75,7 @@ CONFIG_SERIAL_SH_SCI=y CONFIG_SERIAL_SH_SCI_NR_UARTS=20 CONFIG_SERIAL_SH_SCI_CONSOLE=y CONFIG_I2C_GPIO=y +CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_RCAR=y CONFIG_SPI=y CONFIG_SPI_RSPI=y -- cgit v1.2.3 From f5e1367f8f94293f098cab3e906934e535df1a94 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 26 Mar 2014 14:19:11 +0900 Subject: ARM: shmobile: Include at24.c in shmobile_defconfig The Koelsch board includes an at24-compatible EEPROM hooked up via I2C. To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Signed-off-by: Magnus Damm Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index d96133a686e5..146ee70dd459 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -43,6 +43,7 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_M25P80=y +CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_SATA_RCAR=y -- cgit v1.2.3 From 41551f3d7d9a37b55a6f84d77200bfe29d42c466 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 28 Mar 2014 17:54:01 +0100 Subject: ARM: shmobile: Enable USBHS gadget support in shmobile_defconfig The renesas_usbhs driver provides USB gadget support for most Renesas platforms. To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Signed-off-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 146ee70dd459..c10e626e8510 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -103,7 +103,11 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_RCAR=y +CONFIG_USB=y CONFIG_USB_RCAR_GEN2_PHY=y +CONFIG_USB_RENESAS_USBHS=y +CONFIG_USB_GADGET=y +CONFIG_USB_RENESAS_USBHS_UDC=y CONFIG_MMC=y CONFIG_MMC_SDHI=y CONFIG_MMC_SH_MMCIF=y -- cgit v1.2.3 From 667d0f7b0e940bf36e8d12bd7d64aa0f9217b3ac Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 2 Apr 2014 18:06:24 +0900 Subject: ARM: shmobile: Enable HIGHMEM in shmobile_defconfig Many mach-shmobile hardware platforms include support for more than 1GiB of RAM. Enable HIGHMEM by default to allow use of larger amounts of memory. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index c10e626e8510..b73a0380bb03 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -25,6 +25,7 @@ CONFIG_SCHED_MC=y CONFIG_HAVE_ARM_ARCH_TIMER=y CONFIG_NR_CPUS=8 CONFIG_AEABI=y +CONFIG_HIGHMEM=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y -- cgit v1.2.3 From e4224fe8bfd955d1aea5f89f2f3ac38dc4a590fc Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 8 Apr 2014 21:37:58 +0900 Subject: ARM: shmobile: Enable VSP1 in shmobile_defconfig Both r8a7790 and r8a7791 have multiple on-chip VSP1 devices, so enable the VSP1 driver by default in the shmobile_defconfig. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index b73a0380bb03..8fb30b09f960 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -92,10 +92,14 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SOC_CAMERA=y CONFIG_SOC_CAMERA_PLATFORM=y CONFIG_VIDEO_RCAR_VIN=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_RENESAS_VSP1=y # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_ADV7180=y CONFIG_DRM=y -- cgit v1.2.3 From 1d59eb190e3dc575c7bbee4a163c3facd0de2ed9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 10 Apr 2014 16:12:45 +0900 Subject: ARM: shmobile: Enable USB [EO]HCI HCD support in shmobile_defconfig The USB [EO]HCI HCD drivers provide USB host support for Renesas R-Car Gen2 platforms. To increase hardware support enable the driver in the shmobile_defconfig multiplatform configuration. Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/configs/shmobile_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 8fb30b09f960..6d6437cbbc52 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -110,6 +110,8 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_RCAR=y CONFIG_USB=y CONFIG_USB_RCAR_GEN2_PHY=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y CONFIG_USB_RENESAS_USBHS=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=y -- cgit v1.2.3 From ce4b6a04c49b0b414d537b45ededd9dfd4e48336 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 6 Mar 2014 12:16:58 +0900 Subject: ARM: shmobile: Update r8a7791 CPU freq to 1500MHz in C The correct maximum CPU frequency for r8a7791 is 1500 MHz so update the r8a7791 SoC C code to reflect this. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7791.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index e28404e43860..a7e4966f5e18 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c @@ -213,7 +213,7 @@ void __init r8a7791_add_standard_devices(void) void __init r8a7791_init_early(void) { #ifndef CONFIG_ARM_ARCH_TIMER - shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ + shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */ #endif } -- cgit v1.2.3 From c39dae380b4a11f1050a2ef6607598dcbe0541be Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 6 Mar 2014 12:28:24 +0900 Subject: ARM: shmobile: Add shared shmobile_init_delay() Introduce shmobile_init_delay() that gets CPU specific parameters from DT and sets up the early delay from there. This allows us to both remove frequency information from the C code and consolidate existing code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/common.h | 1 + arch/arm/mach-shmobile/timer.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h index cb8e32deb2a3..f7a360edcc35 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/include/mach/common.h @@ -4,6 +4,7 @@ extern void shmobile_earlytimer_init(void); extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, unsigned int mult, unsigned int div); +extern void shmobile_init_delay(void); struct twd_local_timer; extern void shmobile_setup_console(void); extern void shmobile_boot_vector(void); diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c index 62d7052d6f21..ccecde9a3362 100644 --- a/arch/arm/mach-shmobile/timer.c +++ b/arch/arm/mach-shmobile/timer.c @@ -21,6 +21,7 @@ #include #include #include +#include void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz, unsigned int mult, unsigned int div) @@ -39,6 +40,33 @@ void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz, preset_lpj = max_cpu_core_mhz * value; } +void __init shmobile_init_delay(void) +{ + struct device_node *np, *parent; + u32 max_freq, freq; + + max_freq = 0; + + parent = of_find_node_by_path("/cpus"); + if (parent) { + for_each_child_of_node(parent, np) { + if (!of_property_read_u32(np, "clock-frequency", &freq)) + max_freq = max(max_freq, freq); + } + of_node_put(parent); + } + + if (max_freq) { + if (of_find_compatible_node(NULL, NULL, "arm,cortex-a8")) + shmobile_setup_delay(max_freq, 1, 3); + else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) + shmobile_setup_delay(max_freq, 1, 3); + else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a15")) + if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) + shmobile_setup_delay(max_freq, 2, 4); + } +} + static void __init shmobile_late_time_init(void) { /* -- cgit v1.2.3 From 094c62c3313e1a1c7929a2f69c07ba3382c358e4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 13 Feb 2014 17:26:08 +0900 Subject: ARM: shmobile: Remove legacy EMEV2 SoC support Get rid of legacy EMEV2 SoC code including the legacy clock framework implementation. The multiplatform implementation together with DT board support shall be used instead. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/mach-shmobile/Kconfig | 10 -- arch/arm/mach-shmobile/Makefile | 1 - arch/arm/mach-shmobile/clock-emev2.c | 231 ---------------------------- arch/arm/mach-shmobile/include/mach/emev2.h | 1 - arch/arm/mach-shmobile/setup-emev2.c | 4 - 6 files changed, 1 insertion(+), 249 deletions(-) delete mode 100644 arch/arm/mach-shmobile/clock-emev2.c (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..178aa089b6c4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -304,8 +304,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ s3c6410-smdk6410.dtb -dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ - r7s72100-genmai.dtb \ +dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ r7s72100-genmai-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 0f92ba8e7884..ad0c6bc2747d 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -140,16 +140,6 @@ config ARCH_R8A7791 select SYS_SUPPORTS_SH_CMT select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE -config ARCH_EMEV2 - bool "Emma Mobile EV2" - select ARCH_WANT_OPTIONAL_GPIOLIB - select ARM_GIC - select CPU_V7 - select MIGHT_HAVE_PCI - select USE_OF - select AUTO_ZRELADDR - select SYS_SUPPORTS_EM_STI - config ARCH_R7S72100 bool "RZ/A1H (R7S72100)" select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 4caffc912a81..76053770aa04 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o -obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o obj-$(CONFIG_ARCH_R7S72100) += clock-r7s72100.o endif diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c deleted file mode 100644 index 5ac13ba71d54..000000000000 --- a/arch/arm/mach-shmobile/clock-emev2.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Emma Mobile EV2 clock framework support - * - * Copyright (C) 2012 Magnus Damm - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include -#include -#include -#include -#include - -#define EMEV2_SMU_BASE 0xe0110000 - -/* EMEV2 SMU registers */ -#define USIAU0_RSTCTRL 0x094 -#define USIBU1_RSTCTRL 0x0ac -#define USIBU2_RSTCTRL 0x0b0 -#define USIBU3_RSTCTRL 0x0b4 -#define STI_RSTCTRL 0x124 -#define USIAU0GCLKCTRL 0x4a0 -#define USIBU1GCLKCTRL 0x4b8 -#define USIBU2GCLKCTRL 0x4bc -#define USIBU3GCLKCTRL 0x04c0 -#define STIGCLKCTRL 0x528 -#define USIAU0SCLKDIV 0x61c -#define USIB2SCLKDIV 0x65c -#define USIB3SCLKDIV 0x660 -#define STI_CLKSEL 0x688 - -/* not pretty, but hey */ -static void __iomem *smu_base; - -static void emev2_smu_write(unsigned long value, int offs) -{ - BUG_ON(!smu_base || (offs >= PAGE_SIZE)); - iowrite32(value, smu_base + offs); -} - -static struct clk_mapping smu_mapping = { - .phys = EMEV2_SMU_BASE, - .len = PAGE_SIZE, -}; - -/* Fixed 32 KHz root clock from C32K pin */ -static struct clk c32k_clk = { - .rate = 32768, - .mapping = &smu_mapping, -}; - -/* PLL3 multiplies C32K with 7000 */ -static unsigned long pll3_recalc(struct clk *clk) -{ - return clk->parent->rate * 7000; -} - -static struct sh_clk_ops pll3_clk_ops = { - .recalc = pll3_recalc, -}; - -static struct clk pll3_clk = { - .ops = &pll3_clk_ops, - .parent = &c32k_clk, -}; - -static struct clk *main_clks[] = { - &c32k_clk, - &pll3_clk, -}; - -enum { SCLKDIV_USIAU0, SCLKDIV_USIBU2, SCLKDIV_USIBU1, SCLKDIV_USIBU3, - SCLKDIV_NR }; - -#define SCLKDIV(_reg, _shift) \ -{ \ - .parent = &pll3_clk, \ - .enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \ - .enable_bit = _shift, \ -} - -static struct clk sclkdiv_clks[SCLKDIV_NR] = { - [SCLKDIV_USIAU0] = SCLKDIV(USIAU0SCLKDIV, 0), - [SCLKDIV_USIBU2] = SCLKDIV(USIB2SCLKDIV, 16), - [SCLKDIV_USIBU1] = SCLKDIV(USIB2SCLKDIV, 0), - [SCLKDIV_USIBU3] = SCLKDIV(USIB3SCLKDIV, 0), -}; - -enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK, - GCLK_STI_SCLK, - GCLK_NR }; - -#define GCLK_SCLK(_parent, _reg) \ -{ \ - .parent = _parent, \ - .enable_reg = IOMEM(EMEV2_SMU_BASE + (_reg)), \ - .enable_bit = 1, /* SCLK_GCC */ \ -} - -static struct clk gclk_clks[GCLK_NR] = { - [GCLK_USIAU0_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIAU0], - USIAU0GCLKCTRL), - [GCLK_USIBU1_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU1], - USIBU1GCLKCTRL), - [GCLK_USIBU2_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU2], - USIBU2GCLKCTRL), - [GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3], - USIBU3GCLKCTRL), - [GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL), -}; - -static int emev2_gclk_enable(struct clk *clk) -{ - iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit), - clk->mapped_reg); - return 0; -} - -static void emev2_gclk_disable(struct clk *clk) -{ - iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit), - clk->mapped_reg); -} - -static struct sh_clk_ops emev2_gclk_clk_ops = { - .enable = emev2_gclk_enable, - .disable = emev2_gclk_disable, - .recalc = followparent_recalc, -}; - -static int __init emev2_gclk_register(struct clk *clks, int nr) -{ - struct clk *clkp; - int ret = 0; - int k; - - for (k = 0; !ret && (k < nr); k++) { - clkp = clks + k; - clkp->ops = &emev2_gclk_clk_ops; - ret |= clk_register(clkp); - } - - return ret; -} - -static unsigned long emev2_sclkdiv_recalc(struct clk *clk) -{ - unsigned int sclk_div; - - sclk_div = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0xff; - - return clk->parent->rate / (sclk_div + 1); -} - -static struct sh_clk_ops emev2_sclkdiv_clk_ops = { - .recalc = emev2_sclkdiv_recalc, -}; - -static int __init emev2_sclkdiv_register(struct clk *clks, int nr) -{ - struct clk *clkp; - int ret = 0; - int k; - - for (k = 0; !ret && (k < nr); k++) { - clkp = clks + k; - clkp->ops = &emev2_sclkdiv_clk_ops; - ret |= clk_register(clkp); - } - - return ret; -} - -static struct clk_lookup lookups[] = { - CLKDEV_DEV_ID("serial8250-em.0", &gclk_clks[GCLK_USIAU0_SCLK]), - CLKDEV_DEV_ID("e1020000.uart", &gclk_clks[GCLK_USIAU0_SCLK]), - CLKDEV_DEV_ID("serial8250-em.1", &gclk_clks[GCLK_USIBU1_SCLK]), - CLKDEV_DEV_ID("e1030000.uart", &gclk_clks[GCLK_USIBU1_SCLK]), - CLKDEV_DEV_ID("serial8250-em.2", &gclk_clks[GCLK_USIBU2_SCLK]), - CLKDEV_DEV_ID("e1040000.uart", &gclk_clks[GCLK_USIBU2_SCLK]), - CLKDEV_DEV_ID("serial8250-em.3", &gclk_clks[GCLK_USIBU3_SCLK]), - CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]), - CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]), - CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]), -}; - -void __init emev2_clock_init(void) -{ - int k, ret = 0; - - smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); - BUG_ON(!smu_base); - - /* setup STI timer to run on 32.768 kHz and deassert reset */ - emev2_smu_write(0, STI_CLKSEL); - emev2_smu_write(1, STI_RSTCTRL); - - /* deassert reset for UART0->UART3 */ - emev2_smu_write(2, USIAU0_RSTCTRL); - emev2_smu_write(2, USIBU1_RSTCTRL); - emev2_smu_write(2, USIBU2_RSTCTRL); - emev2_smu_write(2, USIBU3_RSTCTRL); - - for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) - ret = clk_register(main_clks[k]); - - if (!ret) - ret = emev2_sclkdiv_register(sclkdiv_clks, SCLKDIV_NR); - - if (!ret) - ret = emev2_gclk_register(gclk_clks, GCLK_NR); - - clkdev_add_table(lookups, ARRAY_SIZE(lookups)); - - if (!ret) - shmobile_clk_init(); - else - panic("failed to setup emev2 clocks\n"); -} diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h index fcb142a14e07..d64e188a9755 100644 --- a/arch/arm/mach-shmobile/include/mach/emev2.h +++ b/arch/arm/mach-shmobile/include/mach/emev2.h @@ -3,7 +3,6 @@ extern void emev2_map_io(void); extern void emev2_init_delay(void); -extern void emev2_clock_init(void); extern struct smp_operations emev2_smp_ops; #endif /* __ASM_EMEV2_H__ */ diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index c71d667007b8..b15a0ed769fe 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -50,11 +50,7 @@ void __init emev2_init_delay(void) static void __init emev2_add_standard_devices_dt(void) { -#ifdef CONFIG_COMMON_CLK of_clk_init(NULL); -#else - emev2_clock_init(); -#endif of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } -- cgit v1.2.3 From 505891ec2558771cd84fe00fc1646275b4c069ed Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 17 Feb 2014 16:35:08 +0900 Subject: ARM: shmobile: Remove EMEV2 header file There is no C board code left for the EMEV2 SoC, so get rid of the emev2.h include file to save some lines. While at it make functions static. Signed-off-by: Magnus Damm [horms+renesas@verge.net.au: Resolved conflict] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/include/mach/emev2.h | 8 -------- arch/arm/mach-shmobile/setup-emev2.c | 7 ++++--- arch/arm/mach-shmobile/smp-emev2.c | 1 - 3 files changed, 4 insertions(+), 12 deletions(-) delete mode 100644 arch/arm/mach-shmobile/include/mach/emev2.h (limited to 'arch') diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h deleted file mode 100644 index d64e188a9755..000000000000 --- a/arch/arm/mach-shmobile/include/mach/emev2.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef __ASM_EMEV2_H__ -#define __ASM_EMEV2_H__ - -extern void emev2_map_io(void); -extern void emev2_init_delay(void); -extern struct smp_operations emev2_smp_ops; - -#endif /* __ASM_EMEV2_H__ */ diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index b15a0ed769fe..d953ff6e78a2 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -38,12 +37,12 @@ static struct map_desc emev2_io_desc[] __initdata = { #endif }; -void __init emev2_map_io(void) +static void __init emev2_map_io(void) { iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); } -void __init emev2_init_delay(void) +static void __init emev2_init_delay(void) { shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ } @@ -59,6 +58,8 @@ static const char *emev2_boards_compat_dt[] __initconst = { NULL, }; +extern struct smp_operations emev2_smp_ops; + DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") .smp = smp_ops(emev2_smp_ops), .map_io = emev2_map_io, diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index f2ca92308f75..2dfd748da7f3 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3 From f05b4b52845a18e833644eb3a820a55e3278d2b4 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 24 Feb 2014 14:49:07 +0900 Subject: ARM: shmobile: Make use of r8a7790_add_standard_devices() Move non-PFC and non-GPIO devices off from r8a7790_pinmux_init() and into r8a7790_add_standard_devices() which is the normal place to keep regular devices in the legacy case. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7790.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c4616f0698c6..a901d9ef53f6 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -185,12 +185,6 @@ void __init r8a7790_pinmux_init(void) r8a7790_register_gpio(3); r8a7790_register_gpio(4); r8a7790_register_gpio(5); - r8a7790_register_i2c(0); - r8a7790_register_i2c(1); - r8a7790_register_i2c(2); - r8a7790_register_i2c(3); - r8a7790_register_audio_dmac(0); - r8a7790_register_audio_dmac(1); } #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \ @@ -308,6 +302,12 @@ void __init r8a7790_add_standard_devices(void) r8a7790_add_dt_devices(); r8a7790_register_irqc(0); r8a7790_register_thermal(); + r8a7790_register_i2c(0); + r8a7790_register_i2c(1); + r8a7790_register_i2c(2); + r8a7790_register_i2c(3); + r8a7790_register_audio_dmac(0); + r8a7790_register_audio_dmac(1); } void __init r8a7790_init_early(void) -- cgit v1.2.3 From 835d737d664650d7f164a5b688271a424db4434c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 12 Mar 2014 19:44:49 +0100 Subject: ARM: shmobile: rcar-gen2: Cache Mode Monitor Register Value The MD pins are sampled at reset time, hence the read value will always be the same, and we can avoid the overhead of ioremapping the register on every read. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-rcar-gen2.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 10604480f325..542c5a47173f 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -30,12 +30,16 @@ u32 rcar_gen2_read_mode_pins(void) { - void __iomem *modemr = ioremap_nocache(MODEMR, 4); - u32 mode; - - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); + static u32 mode; + static bool mode_valid; + + if (!mode_valid) { + void __iomem *modemr = ioremap_nocache(MODEMR, 4); + BUG_ON(!modemr); + mode = ioread32(modemr); + iounmap(modemr); + mode_valid = true; + } return mode; } -- cgit v1.2.3 From 277efd30cfc72ec2f44a9bc95d93807b867bd9e9 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 26 Feb 2014 18:59:16 +0900 Subject: ARM: shmobile: Check r8a7791 MD21 at SMP boot On r8a7791 the hardware boot mode bit MD21 indicates if hardware debug mode is enabled or not. In case hardware debug mode is enabled print a warning and refrain from booting secondary CPU cores. Without this patch Koelsch with SW8-4 set to OFF will hang at SMP boot. Signed-off-by: Magnus Damm Tested-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/smp-r8a7791.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c index 2df5bd190fe4..ec979529f30f 100644 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ b/arch/arm/mach-shmobile/smp-r8a7791.c @@ -20,6 +20,7 @@ #include #include #include +#include #define RST 0xe6160000 #define CA15BAR 0x0020 @@ -51,9 +52,21 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus) iounmap(p); } +static int r8a7791_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + /* Error out when hardware debug mode is enabled */ + if (rcar_gen2_read_mode_pins() & BIT(21)) { + pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu); + return -ENOTSUPP; + } + + return shmobile_smp_apmu_boot_secondary(cpu, idle); +} + struct smp_operations r8a7791_smp_ops __initdata = { .smp_prepare_cpus = r8a7791_smp_prepare_cpus, - .smp_boot_secondary = shmobile_smp_apmu_boot_secondary, + .smp_boot_secondary = r8a7791_smp_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_disable = shmobile_smp_cpu_disable, .cpu_die = shmobile_smp_apmu_cpu_die, -- cgit v1.2.3 From e35db38d66d1e4007cfc1bb90a05e11b4aaee2a8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 23 Mar 2014 20:36:18 +0100 Subject: ARM: shmobile: r8a7778/bockw: Move "select RENESAS_INTC_IRQPIN" under SoC Move the "select RENESAS_INTC_IRQPIN" from the two bockw-specific sections to the one r8a7778-specific section, like is done for the other SoCs. Signed-off-by: Geert Uytterhoeven [horms+renesas@verge.net.au: Resolved conflict] Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index ad0c6bc2747d..58bc6db6e79d 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -108,6 +108,7 @@ config ARCH_R8A7778 select SH_CLK_CPG select ARM_GIC select SYS_SUPPORTS_SH_TMU + select RENESAS_INTC_IRQPIN config ARCH_R8A7779 bool "R-Car H1 (R8A77790)" @@ -206,7 +207,6 @@ config MACH_BOCKW depends on ARCH_R8A7778 select ARCH_REQUIRE_GPIOLIB select REGULATOR_FIXED_VOLTAGE if REGULATOR - select RENESAS_INTC_IRQPIN select SND_SOC_AK4554 if SND_SIMPLE_CARD select SND_SOC_AK4642 if SND_SIMPLE_CARD select USE_OF @@ -215,7 +215,6 @@ config MACH_BOCKW_REFERENCE bool "BOCK-W - Reference Device Tree Implementation" depends on ARCH_R8A7778 select ARCH_REQUIRE_GPIOLIB - select RENESAS_INTC_IRQPIN select REGULATOR_FIXED_VOLTAGE if REGULATOR select USE_OF ---help--- -- cgit v1.2.3 From edcf139081f501b1468ae6665217e8320d4c75e8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 12 Mar 2014 19:44:50 +0100 Subject: ARM: shmobile: r8a7791: Use rcar_gen2_read_mode_pins() helper Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7791.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index 701383fe3267..36e57508d879 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c @@ -25,6 +25,7 @@ #include #include #include +#include /* * MD EXTAL PLL0 PLL1 PLL3 @@ -43,8 +44,6 @@ * see "p1 / 2" on R8A7791_CLOCK_ROOT() below */ -#define MD(nr) (1 << nr) - #define CPG_BASE 0xe6150000 #define CPG_LEN 0x1000 @@ -68,7 +67,6 @@ #define MSTPSR9 IOMEM(0xe61509a4) #define MSTPSR11 IOMEM(0xe61509ac) -#define MODEMR 0xE6160060 #define SDCKCR 0xE6150074 #define SD1CKCR 0xE6150078 #define SD2CKCR 0xE615026c @@ -295,14 +293,9 @@ static struct clk_lookup lookups[] = { void __init r8a7791_clock_init(void) { - void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); - u32 mode; + u32 mode = rcar_gen2_read_mode_pins(); int k, ret = 0; - BUG_ON(!modemr); - mode = ioread32(modemr); - iounmap(modemr); - switch (mode & (MD(14) | MD(13))) { case 0: R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); -- cgit v1.2.3 From 25f5550f5a4b18fd77a2e719ba63cb34931ab66a Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 13 Mar 2014 08:36:17 +0900 Subject: ARM: shmobile: Introduce shmobile_clk_workaround() Introduce a new clock workaround function used by DT reference code on the mach-shmobile subarchitecture. The new function shmobile_clk_workaround() is used to configure clkdev to allow DT and platform devices to coexist. It is possible for the DT reference board code to also request enabling of the clock in case the driver does not implement clock control. Signed-off-by: Magnus Damm [horms+renesas@verge.net.au: Removed trailing blank line] Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/Makefile | 2 +- arch/arm/mach-shmobile/clock.c | 28 ++++++++++++++++++++++++++++ arch/arm/mach-shmobile/include/mach/clock.h | 16 ++++++++++++++++ 3 files changed, 45 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 4caffc912a81..c12a1c50e9d2 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -21,8 +21,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o # Clock objects -ifndef CONFIG_COMMON_CLK obj-y += clock.o +ifndef CONFIG_COMMON_CLK obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index ad7df629d995..e7232a0373b9 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c @@ -21,6 +21,32 @@ */ #include #include + +#ifdef CONFIG_COMMON_CLK +#include +#include +#include + +void __init shmobile_clk_workaround(const struct clk_name *clks, + int nr_clks, bool enable) +{ + const struct clk_name *clkn; + struct clk *clk; + unsigned int i; + + for (i = 0; i < nr_clks; ++i) { + clkn = clks + i; + clk = clk_get(NULL, clkn->clk); + if (!IS_ERR(clk)) { + clk_register_clkdev(clk, clkn->con_id, clkn->dev_id); + if (enable) + clk_prepare_enable(clk); + clk_put(clk); + } + } +} + +#else /* CONFIG_COMMON_CLK */ #include #include #include @@ -58,3 +84,5 @@ void __clk_put(struct clk *clk) { } EXPORT_SYMBOL(__clk_put); + +#endif /* CONFIG_COMMON_CLK */ diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h index 03e56074928c..9a93cf924b9c 100644 --- a/arch/arm/mach-shmobile/include/mach/clock.h +++ b/arch/arm/mach-shmobile/include/mach/clock.h @@ -1,6 +1,21 @@ #ifndef CLOCK_H #define CLOCK_H +#ifdef CONFIG_COMMON_CLK +/* temporary clock configuration helper for platform devices */ + +struct clk_name { + const char *clk; + const char *con_id; + const char *dev_id; +}; + +void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks, + bool enable); + +#else /* CONFIG_COMMON_CLK */ +/* legacy clock implementation */ + unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk); extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops; @@ -36,4 +51,5 @@ do { \ (p)->div = d; \ } while (0) +#endif /* CONFIG_COMMON_CLK */ #endif -- cgit v1.2.3 From ab077bfdc4eaffa5328a9843d4d7970718ac0b8a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 1 Apr 2014 13:02:15 +0200 Subject: ARM: shmobile: r8a7790: Fix the I2C clocks parents in legacy code All I2C clocks derive from the HP clock, not from the P clock. Fix them. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7790.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 3f93503f5b96..331013995fe3 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -249,10 +249,10 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */ [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */ [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */ - [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */ - [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */ - [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ - [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ + [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */ + [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */ + [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ + [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */ [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */ [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */ -- cgit v1.2.3 From 2b1b6e6865aeb236f759ad3f91db27b514e29023 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 1 Apr 2014 13:02:16 +0200 Subject: ARM: shmobile: r8a7791: Fix the I2C clocks parents in legacy code All I2C clocks derive from the HP clock, not from the P clock. Fix them. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7791.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index 36e57508d879..3b26c7eee873 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c @@ -188,12 +188,12 @@ static struct clk mstp_clks[MSTP_NR] = { [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */ [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */ [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */ - [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */ - [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */ - [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ - [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ - [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */ - [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */ + [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */ + [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */ + [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */ + [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */ + [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */ + [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */ [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */ [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */ [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */ -- cgit v1.2.3 From 79ea9934b8df700fa306c8ced2d3bbf94ff276a8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 2 Apr 2014 16:31:46 +0200 Subject: ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R) The r8a7790 has four VSP1 instances, two of them being named VSPS (which stands for "VSP Standard") and VSPR (which stands for "VSP for Resizing"). The clock section in the SoC datasheet misunderstood the abbreviations as meaning VSP System and VSP Realtime, and named the corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been carried over to the kernel code. Fix this by renaming the VSP1_SY and VSP1_RT clocks to VSP1_S and VSP1_R. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 2 +- include/dt-bindings/clock/r8a7790-clock.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 618e5b537eaf..10b326bdf831 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -673,7 +673,7 @@ renesas,clock-indices = < R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 - R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY + R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 6548a5fbcf4a..9a7c4c5a35d1 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -33,8 +33,8 @@ #define R8A7790_CLK_TMU0 25 #define R8A7790_CLK_VSP1_DU1 27 #define R8A7790_CLK_VSP1_DU0 28 -#define R8A7790_CLK_VSP1_RT 30 -#define R8A7790_CLK_VSP1_SY 31 +#define R8A7790_CLK_VSP1_R 30 +#define R8A7790_CLK_VSP1_S 31 /* MSTP2 */ #define R8A7790_CLK_SCIFA2 2 -- cgit v1.2.3 From 58ea1d53ba93620ac50fef9d9720b2323971f243 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 2 Apr 2014 16:31:47 +0200 Subject: ARM: shmobile: r8a7791: Rename VSP1_SY clocks to VSP1_S The r8a7791 has three VSP1 instances, one of them being named VSPS (which stands for "VSP Standard"). The clock section in the SoC datasheet misunderstood the abbreviation as meaning VSP System, and named the corresponding clock VSP1(SY). This mistake has been carried over to the kernel code. Fix this by renaming the VSP1_SY clock to VSP1_S. Signed-off-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 2 +- include/dt-bindings/clock/r8a7791-clock.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 46181708e59c..aa1cba94196c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -688,7 +688,7 @@ renesas,clock-indices = < R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 - R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY + R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S >; clock-output-names = "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index 30f82f286e29..f069bc6627cb 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -32,7 +32,7 @@ #define R8A7791_CLK_TMU0 25 #define R8A7791_CLK_VSP1_DU1 27 #define R8A7791_CLK_VSP1_DU0 28 -#define R8A7791_CLK_VSP1_SY 31 +#define R8A7791_CLK_VSP1_S 31 /* MSTP2 */ #define R8A7791_CLK_SCIFA2 2 -- cgit v1.2.3 From e6597e0e19bbabfdd1983dbe79892d8ba210a180 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 13 Mar 2014 08:36:26 +0900 Subject: ARM: shmobile: Use shmobile_clk_workaround() on Lager Convert the Lager DT reference code to use the newly introduced function shmobile_clk_workaround(). Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-lager-reference.c | 65 ++++++++++---------------- 1 file changed, 25 insertions(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 440aac36d693..c76248b9a5e7 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -18,12 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include -#include #include #include #include #include +#include #include #include #include @@ -86,46 +85,32 @@ static void __init lager_add_du_device(void) platform_device_register_full(&info); } +/* + * This is a really crude hack to provide clkdev support to platform + * devices until they get moved to DT. + */ +static const struct clk_name clk_names[] = { + { "cmt0", NULL, "sh_cmt.0" }, + { "scifa0", NULL, "sh-sci.0" }, + { "scifa1", NULL, "sh-sci.1" }, + { "scifb0", NULL, "sh-sci.2" }, + { "scifb1", NULL, "sh-sci.3" }, + { "scifb2", NULL, "sh-sci.4" }, + { "scifa2", NULL, "sh-sci.5" }, + { "scif0", NULL, "sh-sci.6" }, + { "scif1", NULL, "sh-sci.7" }, + { "hscif0", NULL, "sh-sci.8" }, + { "hscif1", NULL, "sh-sci.9" }, + { "du0", "du.0", "rcar-du-r8a7790" }, + { "du1", "du.1", "rcar-du-r8a7790" }, + { "du2", "du.2", "rcar-du-r8a7790" }, + { "lvds0", "lvds.0", "rcar-du-r8a7790" }, + { "lvds1", "lvds.1", "rcar-du-r8a7790" }, +}; + static void __init lager_add_standard_devices(void) { - /* - * This is a really crude hack to provide clkdev support to platform - * devices until they get moved to DT. - */ - static const struct clk_name { - const char *clk; - const char *con_id; - const char *dev_id; - } clk_names[] = { - { "cmt0", NULL, "sh_cmt.0" }, - { "scifa0", NULL, "sh-sci.0" }, - { "scifa1", NULL, "sh-sci.1" }, - { "scifb0", NULL, "sh-sci.2" }, - { "scifb1", NULL, "sh-sci.3" }, - { "scifb2", NULL, "sh-sci.4" }, - { "scifa2", NULL, "sh-sci.5" }, - { "scif0", NULL, "sh-sci.6" }, - { "scif1", NULL, "sh-sci.7" }, - { "hscif0", NULL, "sh-sci.8" }, - { "hscif1", NULL, "sh-sci.9" }, - { "du0", "du.0", "rcar-du-r8a7790" }, - { "du1", "du.1", "rcar-du-r8a7790" }, - { "du2", "du.2", "rcar-du-r8a7790" }, - { "lvds0", "lvds.0", "rcar-du-r8a7790" }, - { "lvds1", "lvds.1", "rcar-du-r8a7790" }, - }; - struct clk *clk; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(clk_names); ++i) { - clk = clk_get(NULL, clk_names[i].clk); - if (!IS_ERR(clk)) { - clk_register_clkdev(clk, clk_names[i].con_id, - clk_names[i].dev_id); - clk_put(clk); - } - } - + shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); r8a7790_add_dt_devices(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -- cgit v1.2.3 From 89aff406dbc3ea3dfc008e8472181532c0c0f4ea Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 13 Mar 2014 08:36:35 +0900 Subject: ARM: shmobile: Use shmobile_clk_workaround() on Koelsch Convert the Koelsch DT reference code to use the newly introduced function shmobile_clk_workaround(). Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-koelsch-reference.c | 71 ++++++++++-------------- 1 file changed, 28 insertions(+), 43 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index a3fd30242bd8..a760f7f19bc9 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -19,12 +19,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include -#include #include #include #include #include +#include #include #include #include @@ -82,49 +81,35 @@ static void __init koelsch_add_du_device(void) platform_device_register_full(&info); } +/* + * This is a really crude hack to provide clkdev support to platform + * devices until they get moved to DT. + */ +static const struct clk_name clk_names[] = { + { "cmt0", NULL, "sh_cmt.0" }, + { "scifa0", NULL, "sh-sci.0" }, + { "scifa1", NULL, "sh-sci.1" }, + { "scifb0", NULL, "sh-sci.2" }, + { "scifb1", NULL, "sh-sci.3" }, + { "scifb2", NULL, "sh-sci.4" }, + { "scifa2", NULL, "sh-sci.5" }, + { "scif0", NULL, "sh-sci.6" }, + { "scif1", NULL, "sh-sci.7" }, + { "scif2", NULL, "sh-sci.8" }, + { "scif3", NULL, "sh-sci.9" }, + { "scif4", NULL, "sh-sci.10" }, + { "scif5", NULL, "sh-sci.11" }, + { "scifa3", NULL, "sh-sci.12" }, + { "scifa4", NULL, "sh-sci.13" }, + { "scifa5", NULL, "sh-sci.14" }, + { "du0", "du.0", "rcar-du-r8a7791" }, + { "du1", "du.1", "rcar-du-r8a7791" }, + { "lvds0", "lvds.0", "rcar-du-r8a7791" }, +}; + static void __init koelsch_add_standard_devices(void) { - /* - * This is a really crude hack to provide clkdev support to the CMT and - * DU devices until they get moved to DT. - */ - static const struct clk_name { - const char *clk; - const char *con_id; - const char *dev_id; - } clk_names[] = { - { "cmt0", NULL, "sh_cmt.0" }, - { "scifa0", NULL, "sh-sci.0" }, - { "scifa1", NULL, "sh-sci.1" }, - { "scifb0", NULL, "sh-sci.2" }, - { "scifb1", NULL, "sh-sci.3" }, - { "scifb2", NULL, "sh-sci.4" }, - { "scifa2", NULL, "sh-sci.5" }, - { "scif0", NULL, "sh-sci.6" }, - { "scif1", NULL, "sh-sci.7" }, - { "scif2", NULL, "sh-sci.8" }, - { "scif3", NULL, "sh-sci.9" }, - { "scif4", NULL, "sh-sci.10" }, - { "scif5", NULL, "sh-sci.11" }, - { "scifa3", NULL, "sh-sci.12" }, - { "scifa4", NULL, "sh-sci.13" }, - { "scifa5", NULL, "sh-sci.14" }, - { "du0", "du.0", "rcar-du-r8a7791" }, - { "du1", "du.1", "rcar-du-r8a7791" }, - { "lvds0", "lvds.0", "rcar-du-r8a7791" }, - }; - struct clk *clk; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(clk_names); ++i) { - clk = clk_get(NULL, clk_names[i].clk); - if (!IS_ERR(clk)) { - clk_register_clkdev(clk, clk_names[i].con_id, - clk_names[i].dev_id); - clk_put(clk); - } - } - + shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); r8a7791_add_dt_devices(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -- cgit v1.2.3 From f6f98b3e44ea408e33eb4d695a4225cc11210cdb Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 13 Mar 2014 15:29:57 +0900 Subject: ARM: shmobile: koelsch: Annotate clk_names with __initconst Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/board-koelsch-reference.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index a760f7f19bc9..1e6a4361c0eb 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -85,7 +85,7 @@ static void __init koelsch_add_du_device(void) * This is a really crude hack to provide clkdev support to platform * devices until they get moved to DT. */ -static const struct clk_name clk_names[] = { +static const struct clk_name clk_names[] __initconst = { { "cmt0", NULL, "sh_cmt.0" }, { "scifa0", NULL, "sh-sci.0" }, { "scifa1", NULL, "sh-sci.1" }, -- cgit v1.2.3 From f71c77286b2c1f809a85e8e42df88eb2ec132e5f Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 13 Mar 2014 15:29:58 +0900 Subject: ARM: shmobile: lager: Annotate clk_names with __initconst Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/board-lager-reference.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index c76248b9a5e7..7ff395efa9fe 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -89,7 +89,7 @@ static void __init lager_add_du_device(void) * This is a really crude hack to provide clkdev support to platform * devices until they get moved to DT. */ -static const struct clk_name clk_names[] = { +static const struct clk_name clk_names[] __initconst = { { "cmt0", NULL, "sh_cmt.0" }, { "scifa0", NULL, "sh-sci.0" }, { "scifa1", NULL, "sh-sci.1" }, -- cgit v1.2.3 From 53cf0cf7ba2ef785b339826a0765bb6b1756adeb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 13 Mar 2014 15:29:30 +0100 Subject: ARM: shmobile: koelsch-reference: Work around core clock issues Due to issues with runtime PM clock management, clocks not explicitly managed by their drivers may not be enabled at all, or be inadvertently disabled by the clk_disable_unused() late initcall. Until this is fixed, add a temporary workaround, calling shmobile_clk_workaround() with enable == true. For now this enables the clocks for: ether, i2c2, msiof0, qspi_mod, and thermal. More clocks can be added if needed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-koelsch-reference.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index 1e6a4361c0eb..a39114a1fe1b 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -107,9 +107,21 @@ static const struct clk_name clk_names[] __initconst = { { "lvds0", "lvds.0", "rcar-du-r8a7791" }, }; +/* + * This is a really crude hack to work around core platform clock issues + */ +static const struct clk_name clk_enables[] = { + { "ether", NULL, "ee700000.ethernet" }, + { "i2c2", NULL, "e6530000.i2c" }, + { "msiof0", NULL, "e6e20000.spi" }, + { "qspi_mod", NULL, "e6b10000.spi" }, + { "thermal", NULL, "e61f0000.thermal" }, +}; + static void __init koelsch_add_standard_devices(void) { shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); + shmobile_clk_workaround(clk_enables, ARRAY_SIZE(clk_enables), true); r8a7791_add_dt_devices(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -- cgit v1.2.3 From 9e7b83c221cc257f4dc37acc82bbcb80627c0ab9 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 17 Mar 2014 11:19:56 +0900 Subject: ARM: shmobile: koelsch-reference: Annotate clk_enables as __initconst Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/board-koelsch-reference.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index a39114a1fe1b..63117d52db9e 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -110,7 +110,7 @@ static const struct clk_name clk_names[] __initconst = { /* * This is a really crude hack to work around core platform clock issues */ -static const struct clk_name clk_enables[] = { +static const struct clk_name clk_enables[] __initconst = { { "ether", NULL, "ee700000.ethernet" }, { "i2c2", NULL, "e6530000.i2c" }, { "msiof0", NULL, "e6e20000.spi" }, -- cgit v1.2.3 From aa5de826afe747c353162bbc116c63ab5335f91c Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 17 Mar 2014 11:18:56 +0900 Subject: ARM: shmobile: lager-reference: Work around core clock issues Due to issues with runtime PM clock management, clocks not explicitly managed by their drivers may not be enabled at all, or be inadvertently disabled by the clk_disable_unused() late initcall. Until this is fixed, add a temporary workaround, calling shmobile_clk_workaround() with enable == true. For now this enables the clocks for: ether, msiof1, qspi_mod, and thermal. More clocks can be added if needed. Based on work for the koelsch board by Geert Uytterhoeven. Signed-off-by: Simon Horman Acked-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/board-lager-reference.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 7ff395efa9fe..313118c5f365 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -108,9 +108,20 @@ static const struct clk_name clk_names[] __initconst = { { "lvds1", "lvds.1", "rcar-du-r8a7790" }, }; +/* + * This is a really crude hack to work around core platform clock issues + */ +static const struct clk_name clk_enables[] __initconst = { + { "ether", NULL, "ee700000.ethernet" }, + { "msiof1", NULL, "e6e10000.spi" }, + { "qspi_mod", NULL, "e6b10000.spi" }, + { "thermal", NULL, "e61f0000.thermal" }, +}; + static void __init lager_add_standard_devices(void) { shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); + shmobile_clk_workaround(clk_enables, ARRAY_SIZE(clk_enables), true); r8a7790_add_dt_devices(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -- cgit v1.2.3 From f98b55d730492e664fb2649bd7054fec0fe81acd Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 18 Mar 2014 21:52:47 +0900 Subject: ARM: shmobile: Add Lager clock workarounds for SDHI and MMCIF Add MMCIF1, SDHI0 and SDHI2 to the clock workaround list for Lager multiplatform. Without these additional lines wakeup from Suspend-to-RAM never happens. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-lager-reference.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 313118c5f365..1eb48cffb4c5 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -114,7 +114,10 @@ static const struct clk_name clk_names[] __initconst = { static const struct clk_name clk_enables[] __initconst = { { "ether", NULL, "ee700000.ethernet" }, { "msiof1", NULL, "e6e10000.spi" }, + { "mmcif1", NULL, "ee220000.mmc" }, { "qspi_mod", NULL, "e6b10000.spi" }, + { "sdhi0", NULL, "ee100000.sd" }, + { "sdhi2", NULL, "ee140000.sd" }, { "thermal", NULL, "e61f0000.thermal" }, }; -- cgit v1.2.3 From f278ea78beeb17ea07d11fc3372d4f98c94dcf46 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 18 Mar 2014 21:54:34 +0900 Subject: ARM: shmobile: Add Koelsch clock workarounds for SDHI Add SDHI0, SDHI1 and SDHI2 to the clock workaround list for Koelsch multiplatform. Without these additional lines wakeup from Suspend-to-RAM never happens. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-koelsch-reference.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index 63117d52db9e..941f8b394e84 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c @@ -115,6 +115,9 @@ static const struct clk_name clk_enables[] __initconst = { { "i2c2", NULL, "e6530000.i2c" }, { "msiof0", NULL, "e6e20000.spi" }, { "qspi_mod", NULL, "e6b10000.spi" }, + { "sdhi0", NULL, "ee100000.sd" }, + { "sdhi1", NULL, "ee140000.sd" }, + { "sdhi2", NULL, "ee160000.sd" }, { "thermal", NULL, "e61f0000.thermal" }, }; -- cgit v1.2.3 From 896b79df8d60c01d46be23c10cc0f1a6691cc588 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 6 Mar 2014 12:15:36 +0900 Subject: ARM: shmobile: Update r8a7791 CPU freq to 1500MHz in DTS The correct maximum CPU frequency for r8a7791 is 1500 MHz so update the r8a7791 SoC DTS to reflect this. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 46181708e59c..23ae96ee3dde 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -37,14 +37,14 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; - clock-frequency = <1300000000>; + clock-frequency = <1500000000>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; - clock-frequency = <1300000000>; + clock-frequency = <1500000000>; }; }; -- cgit v1.2.3 From fad6d45cdf8269d6d1c6784792c74c53e2304b32 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:13 +0100 Subject: ARM: shmobile: r8a7790/lager dts: Rename label spi to qspi, add spi0 alias Prepare for the advent of MSIOF SPI, which will be spi1 to spi4. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 4 ++-- arch/arm/boot/dts/r8a7790.dtsi | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 6e99eb2df076..86dbdc10fe9c 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -155,7 +155,7 @@ renesas,function = "mmc1"; }; - qspi_pins: spi { + qspi_pins: spi0 { renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; }; @@ -190,7 +190,7 @@ status = "okay"; }; -&spi { +&qspi { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 618e5b537eaf..9383b8436111 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -24,6 +24,7 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + spi0 = &qspi; }; cpus { @@ -765,7 +766,7 @@ }; }; - spi: spi@e6b10000 { + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From 6f3e4ee340ea11d9aba39c5beaa80f0d3f368428 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:14 +0100 Subject: ARM: shmobile: r8a7791/koelsch dts: Rename label spi to qspi, add spi0 alias Prepare for the advent of MSIOF SPI, which will be spi1 to spi3. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 4 ++-- arch/arm/boot/dts/r8a7791.dtsi | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index bdd73e6657b2..bf9555bf08de 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -244,7 +244,7 @@ renesas,function = "sdhi2"; }; - qspi_pins: spi { + qspi_pins: spi0 { renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; }; @@ -301,7 +301,7 @@ status = "okay"; }; -&spi { +&qspi { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 23ae96ee3dde..6cda1886650b 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -27,6 +27,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + spi0 = &qspi; }; cpus { @@ -789,7 +790,7 @@ }; }; - spi: spi@e6b10000 { + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From ae8a6146afc9dddbbf342b3a77b9bf44618511dd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:15 +0100 Subject: ARM: shmobile: r8a7790 dtsi: Add MSIOF nodes and aliases Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 9383b8436111..da69afc9e5cb 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -25,6 +25,10 @@ i2c2 = &i2c2; i2c3 = &i2c3; spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; + spi4 = &msiof3; }; cpus { @@ -776,4 +780,44 @@ #size-cells = <0>; status = "disabled"; }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c90000 { + compatible = "renesas,msiof-r8a7790"; + reg = <0 0xe6c90000 0 0x0064>; + interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; -- cgit v1.2.3 From 7713d3abe220c7d578768c07d183f6efbfa8895b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:16 +0100 Subject: ARM: shmobile: r8a7791 dtsi: Add MSIOF nodes and aliases Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6cda1886650b..a70fb8069ef9 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -28,6 +28,9 @@ i2c4 = &i2c4; i2c5 = &i2c5; spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; }; cpus { @@ -800,4 +803,34 @@ #size-cells = <0>; status = "disabled"; }; + + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7791"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; -- cgit v1.2.3 From b0403b91e18c567fe68976253ed5759c50fb3eae Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:17 +0100 Subject: ARM: shmobile: lager dts: Add MSIOF nodes Add pinctrl and SPI device for MSIOF on Lager. On this board, only MSIOF1 is in use. Its bus contains a single device (a Renesas R2A11302FT PMIC), for which no bindings are defined yet. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 86dbdc10fe9c..cdec1af99be1 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -159,6 +159,12 @@ renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; }; + + msiof1_pins: spi2 { + renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", + "msiof1_tx"; + renesas,function = "msiof1"; + }; }; ðer { @@ -221,6 +227,22 @@ }; }; +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic: pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; + +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From b16f05ab75571ec360f5b7298888fd6cdf06f586 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Feb 2014 11:30:18 +0100 Subject: ARM: shmobile: koelsch dts: Add MSIOF nodes Add pinctrl and SPI device for MSIOF on Koelsch. On this board, only MSIOF0 is in use. Its bus contains a single device (a Renesas R2A11302FT PMIC), for which no bindings are defined yet. Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index bf9555bf08de..e24fed9c0462 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -248,6 +248,12 @@ renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,function = "qspi"; }; + + msiof0_pins: spi1 { + renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", + "msiof0_tx"; + renesas,function = "msiof0"; + }; }; ðer { @@ -331,3 +337,18 @@ }; }; }; + +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + pmic: pmic@0 { + compatible = "renesas,r2a11302ft"; + reg = <0>; + spi-max-frequency = <6000000>; + spi-cpol; + spi-cpha; + }; +}; -- cgit v1.2.3 From a34c50d53dc7779b404baab61b290827cb898562 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 14 Mar 2014 11:06:40 +0100 Subject: ARM: shmobile: r8a7778 dtsi: Improve and correct HSPI nodes - Add "renesas,hspi-r8a7778" compatible value, - Correct reference to parent interrupt controller (use "interrupt-parent" instead of "interrupt-controller"), - Add missing "#address-cells" and "#size-cells" properties, which are needed when populating the SPI buses. Signed-off-by: Geert Uytterhoeven Tested-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 85c5b3b99f5e..3c6fab5c9702 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -204,26 +204,32 @@ }; hspi0: spi@fffc7000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc7000 0x18>; - interrupt-controller = <&gic>; + interrupt-parent = <&gic>; interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi1: spi@fffc8000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc8000 0x18>; - interrupt-controller = <&gic>; + interrupt-parent = <&gic>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi2: spi@fffc6000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7778", "renesas,hspi"; reg = <0xfffc6000 0x18>; - interrupt-controller = <&gic>; + interrupt-parent = <&gic>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; -- cgit v1.2.3 From 7709c33b391e217d73b38853a7914a3a3e285cbc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 14 Mar 2014 11:06:40 +0100 Subject: ARM: shmobile: r8a7779 dtsi: Improve and correct HSPI nodes - Add "renesas,hspi-r8a7779" compatible value, - Correct reference to parent interrupt controller (use "interrupt-parent" instead of "interrupt-controller"), - Add missing "#address-cells" and "#size-cells" properties, which are needed when populating the SPI buses. Signed-off-by: Geert Uytterhoeven Tested-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index d0561d4c7c46..8b1a336ee401 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -256,26 +256,32 @@ }; hspi0: spi@fffc7000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; reg = <0xfffc7000 0x18>; - interrupt-controller = <&gic>; + interrupt-parent = <&gic>; interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi1: spi@fffc8000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; reg = <0xfffc8000 0x18>; - interrupt-controller = <&gic>; + interrupt-parent = <&gic>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; hspi2: spi@fffc6000 { - compatible = "renesas,hspi"; + compatible = "renesas,hspi-r8a7779", "renesas,hspi"; reg = <0xfffc6000 0x18>; - interrupt-controller = <&gic>; + interrupt-parent = <&gic>; interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; }; -- cgit v1.2.3 From 6d879a097acaeaa9deba6d4949b466886b18652e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 14 Mar 2014 11:06:41 +0100 Subject: ARM: shmobile: bockw reference dts: Add SPI FLASH Add Spansion s25fl008k SPI FLASH and MTD partition, based on bockw legacy board code. Signed-off-by: Geert Uytterhoeven Tested-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778-bockw-reference.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 06cda19dac6a..f76f6ec01e19 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -109,4 +109,18 @@ pinctrl-0 = <&hspi0_pins>; pinctrl-names = "default"; status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl008k"; + reg = <0>; + spi-max-frequency = <104000000>; + m25p,fast-read; + + partition@0 { + label = "data(spi)"; + reg = <0x00000000 0x00100000>; + }; + }; }; -- cgit v1.2.3 From f7dcd382a8d6ce8c6da12786c8311e71e214290d Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 18 Mar 2014 21:57:48 +0900 Subject: ARM: shmobile: Add DTS gpio-keys support for SW2 on Lager Add DTS gpio-keys support for SW2 on the Lager board. This makes the DT code match the legacy board code. Signed-off-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index cdec1af99be1..c3d8b17c5e3c 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "r8a7790.dtsi" #include +#include / { model = "Lager"; @@ -36,6 +37,39 @@ #size-cells = <1>; }; + gpio_keys { + compatible = "gpio-keys"; + + button@1 { + linux,code = ; + label = "SW2-1"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + button@2 { + linux,code = ; + label = "SW2-2"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; + button@3 { + linux,code = ; + label = "SW2-3"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + button@4 { + linux,code = ; + label = "SW2-4"; + gpio-key,wakeup; + debounce-interval = <20>; + gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + }; + }; + leds { compatible = "gpio-leds"; led6 { -- cgit v1.2.3 From 7f168b1e921f137db4f323428819f4c86ede4320 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 18 Mar 2014 22:01:17 +0900 Subject: ARM: shmobile: Add DTS gpio-keys support for SW2 on Koelsch Add DTS gpio-keys support for SW2 on the Koelsch board. This makes the DT code match the legacy board code. Also update the existing gpio-keys nodes to make use of KEY_n. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 43 +++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index e24fed9c0462..fd1d6ee48a28 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -13,6 +13,7 @@ /dts-v1/; #include "r8a7791.dtsi" #include +#include / { model = "Koelsch"; @@ -40,51 +41,79 @@ gpio-keys { compatible = "gpio-keys"; + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-1"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-2"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-3"; + gpio-key,wakeup; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW2-4"; + gpio-key,wakeup; + debounce-interval = <20>; + }; key-a { gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - linux,code = <30>; + linux,code = ; label = "SW30"; gpio-key,wakeup; debounce-interval = <20>; }; key-b { gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - linux,code = <48>; + linux,code = ; label = "SW31"; gpio-key,wakeup; debounce-interval = <20>; }; key-c { gpios = <&gpio7 2 GPIO_ACTIVE_LOW>; - linux,code = <46>; + linux,code = ; label = "SW32"; gpio-key,wakeup; debounce-interval = <20>; }; key-d { gpios = <&gpio7 3 GPIO_ACTIVE_LOW>; - linux,code = <32>; + linux,code = ; label = "SW33"; gpio-key,wakeup; debounce-interval = <20>; }; key-e { gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - linux,code = <18>; + linux,code = ; label = "SW34"; gpio-key,wakeup; debounce-interval = <20>; }; key-f { gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; - linux,code = <33>; + linux,code = ; label = "SW35"; gpio-key,wakeup; debounce-interval = <20>; }; key-g { gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - linux,code = <34>; + linux,code = ; label = "SW36"; gpio-key,wakeup; debounce-interval = <20>; -- cgit v1.2.3 From f17dd09d5133bc0705c8319df77169cb8491eaad Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 18 Mar 2014 19:04:47 +0100 Subject: ARM: shmobile: lager: Set ethernet PHY LED mode The Lager board uses the ethernet PHY LED0 as a link signal connected to the ethernet controller. Specify the corresponding LED mode for the PHY. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index c3d8b17c5e3c..a55c5f838b9a 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -213,6 +213,7 @@ reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + led-mode = <1>; }; }; -- cgit v1.2.3 From 19f647cbd432eff181777bbe0f302c62af4a180d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 18 Mar 2014 19:04:48 +0100 Subject: ARM: shmobile: koelsch: Set ethernet PHY LED mode The Koelsch board uses the ethernet PHY LED0 as a link signal connected to the ethernet controller. Specify the corresponding LED mode for the PHY. Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index fd1d6ee48a28..ee23b7b99ec9 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -297,6 +297,7 @@ reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; }; }; -- cgit v1.2.3 From c9b60e922c7551ff1c477a121ad09f3790c1a575 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 23 Mar 2014 20:35:01 +0100 Subject: ARM: shmobile: armadillo-reference dts: Use KEY_* macros for gpio-keys Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 95a849bf921f..97342a4820cf 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a7740.dtsi" #include +#include #include #include @@ -77,26 +78,26 @@ power-key { gpios = <&pfc 99 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = ; label = "SW3"; gpio-key,wakeup; }; back-key { gpios = <&pfc 100 GPIO_ACTIVE_LOW>; - linux,code = <158>; + linux,code = ; label = "SW4"; }; menu-key { gpios = <&pfc 97 GPIO_ACTIVE_LOW>; - linux,code = <139>; + linux,code = ; label = "SW5"; }; home-key { gpios = <&pfc 98 GPIO_ACTIVE_LOW>; - linux,code = <102>; + linux,code = ; label = "SW6"; }; }; -- cgit v1.2.3 From 39f0163098d136411538060fd53c8b8c255cda05 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Sun, 23 Mar 2014 20:35:02 +0100 Subject: ARM: shmobile: kzm9g-reference dts: Use KEY_* macros for gpio-keys Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/sh73a0-kzm9g-reference.dts | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index eb8886b535e4..a99171c8a782 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "sh73a0.dtsi" #include +#include #include / { @@ -112,43 +113,43 @@ back-key { gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>; - linux,code = <158>; + linux,code = ; label = "SW3"; }; right-key { gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>; - linux,code = <106>; + linux,code = ; label = "SW2-R"; }; left-key { gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>; - linux,code = <105>; + linux,code = ; label = "SW2-L"; }; enter-key { gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>; - linux,code = <28>; + linux,code = ; label = "SW2-P"; }; up-key { gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>; - linux,code = <103>; + linux,code = ; label = "SW2-U"; }; down-key { gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>; - linux,code = <108>; + linux,code = ; label = "SW2-D"; }; home-key { gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>; - linux,code = <102>; + linux,code = ; label = "SW1"; }; }; -- cgit v1.2.3 From c08691b578338004ee467cfe51850e7ffb523647 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 10 Mar 2014 12:26:57 +0100 Subject: ARM: shmobile: r8a7791: add IIC(B) clocks to dtsi Signed-off-by: Wolfram Sang Acked-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index a70fb8069ef9..dd45e0197baa 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -716,15 +716,16 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, - <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; + clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, + <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 - R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 + R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 + R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1 >; clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; + "tpu0", "sdhi2", "sdhi1", "sdhi0", + "mmcif0", "i2c7", "i2c8", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -768,17 +769,17 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&p_clk>, + <&cp_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD - R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 - R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 + R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 + R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 + R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 >; clock-output-names = - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", + "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; mstp11_clks: mstp11_clks@e615099c { -- cgit v1.2.3 From 36408d9dd0c398fc3efe87231a4c847601878c97 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 10 Mar 2014 12:26:58 +0100 Subject: ARM: shmobile: r8a7791: add IIC(B) cores to dtsi Signed-off-by: Wolfram Sang Acked-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index dd45e0197baa..1004355496f2 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -27,6 +27,9 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; spi0 = &qspi; spi1 = &msiof0; spi2 = &msiof1; @@ -184,6 +187,7 @@ <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; @@ -235,6 +239,7 @@ }; i2c5: i2c@e6528000 { + /* doesn't need pinmux */ #address-cells = <1>; #size-cells = <0>; compatible = "renesas,i2c-r8a7791"; @@ -244,6 +249,37 @@ status = "disabled"; }; + i2c6: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + status = "disabled"; + }; + + i2c7: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + status = "disabled"; + }; + + i2c8: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + status = "disabled"; + }; + pfc: pfc@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; -- cgit v1.2.3 From e6a4c001116ca28a3c5698168a2a1fe274fa6d2c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 10 Mar 2014 12:26:59 +0100 Subject: ARM: shmobile: koelsch: make i2c2-pfc node unique This node should have a unique name so it can be distinguished when other i2c busses are added later. Signed-off-by: Wolfram Sang Acked-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index ee23b7b99ec9..fc6c94a1fb49 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -228,7 +228,7 @@ pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; pinctrl-names = "default"; - i2c2_pins: i2c { + i2c2_pins: i2c2 { renesas,groups = "i2c2"; renesas,function = "i2c2"; }; -- cgit v1.2.3 From aa28e55dd9b6832a56b1a37fbe65c34ddcd32bdf Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 10 Mar 2014 12:27:00 +0100 Subject: ARM: shmobile: koelsch: activate i2c6 bus Signed-off-by: Wolfram Sang Acked-by: Laurent Pinchart Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index fc6c94a1fb49..2a0569d93b6e 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -224,6 +224,11 @@ }; }; +&i2c6 { + status = "okay"; + clock-frequency = <100000>; +}; + &pfc { pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 5c53f50c50badff499568a703467c3c9f23f9bfd Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Thu, 27 Mar 2014 11:45:44 +0100 Subject: ARM: shmobile: Use r8a7740 suffix for i2c, mmcif, fsi2 compat strings Add "renesas,*-r8a7740" to the compatible strings for consistency with other devices. Signed-off-by: Ulrich Hecht Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 8280884bfa59..9f659861f262 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -126,7 +126,7 @@ i2c0: i2c@fff20000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; reg = <0xfff20000 0x425>; interrupt-parent = <&gic>; interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH @@ -139,7 +139,7 @@ i2c1: i2c@e6c20000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; reg = <0xe6c20000 0x425>; interrupt-parent = <&gic>; interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH @@ -174,7 +174,7 @@ }; mmcif0: mmc@e6bd0000 { - compatible = "renesas,sh-mmcif"; + compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; interrupt-parent = <&gic>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH @@ -220,7 +220,7 @@ sh_fsi2: sound@fe1f0000 { #sound-dai-cells = <1>; - compatible = "renesas,sh_fsi2"; + compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupt-parent = <&gic>; interrupts = <0 9 0x4>; -- cgit v1.2.3 From 6225b99aa620d6e260228a30cc5d24cde60cb1e7 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Mon, 7 Apr 2014 15:04:21 +0900 Subject: ARM: shmobile: r8a7791: Add EHCI MSTP clock Add support for EHCI clock gating via the MSTP703 bit on r8a7791. Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 6 +++--- include/dt-bindings/clock/r8a7791-clock.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 1004355496f2..3b28c8f41fdc 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -774,19 +774,19 @@ mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 + R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 R8A7791_CLK_LVDS0 >; clock-output-names = - "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; }; mstp8_clks: mstp8_clks@e6150990 { diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index 2df1a11faeb3..602354365819 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -63,6 +63,7 @@ #define R8A7791_CLK_PWM 23 /* MSTP7 */ +#define R8A7791_CLK_EHCI 3 #define R8A7791_CLK_HSUSB 4 #define R8A7791_CLK_HSCIF2 13 #define R8A7791_CLK_SCIF5 14 -- cgit v1.2.3 From 584b23db5beb3bd3a3c0767248a4843cac848a58 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Mon, 31 Mar 2014 17:38:20 +0200 Subject: ARM: shmobile: armadillo-reference dts: enable RTC This enables the Seiko real-time clock that is attached to a couple of GPIO pins. Signed-off-by: Ulrich Hecht Signed-off-by: Simon Horman --- .../arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 97342a4820cf..0cb235a450b9 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -118,6 +118,16 @@ }; }; + i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ + &pfc 91 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + backlight { compatible = "pwm-backlight"; pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; @@ -167,6 +177,14 @@ }; }; +&i2c2 { + status = "okay"; + rtc@30 { + compatible = "seiko,s35390a"; + reg = <0x30>; + }; +}; + &pfc { pinctrl-0 = <&scifa1_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 1c47a6aae8bc6113463c47e9b8d35e35e97411b2 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 8 Apr 2014 09:21:35 +0900 Subject: ARM: shmobile: lager: Correct setting of ethernet PHY LED mode The correct binding is "micrel,led-mode", not "led-mode". This corrects an error which was introduced when setting of ethernet PHY LED mode was added by 82e62182d59bd1d0 ("ARM: shmobile: lager: Set ethernet PHY LED mode"). This makes the lager code consistent with the koelsch code which was added by ae00d12a032490b3 ("ARM: shmobile: koelsch: Set ethernet PHY LED mode"). Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index a55c5f838b9a..265cba1d53dc 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -213,7 +213,7 @@ reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - led-mode = <1>; + micrel,led-mode = <1>; }; }; -- cgit v1.2.3 From 3672b059e3a8582171863e1c588059a37aa56b75 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 1 Apr 2014 13:02:17 +0200 Subject: ARM: shmobile: r8a7790: Fix the I2C clocks parents in DT All I2C clocks derive from the HP clock, not from the P clock. Fix them. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index da69afc9e5cb..c4b9ff731f72 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -758,7 +758,7 @@ compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD -- cgit v1.2.3 From 11b48db9321d11c623155a1c82544988508f9aca Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 1 Apr 2014 13:02:18 +0200 Subject: ARM: shmobile: r8a7791: Fix the I2C clocks parents in DT All I2C clocks derive from the HP clock, not from the P clock. Fix them. Signed-off-by: Laurent Pinchart Acked-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 3b28c8f41fdc..98baff48e6ce 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -805,9 +805,9 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&p_clk>, - <&cp_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>; + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, + <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 -- cgit v1.2.3 From 17465149d8a1a3b7a00f02796d7d364522d0383b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 11 Mar 2014 22:24:37 +0100 Subject: ARM: shmobile: r8a7790: add IIC(B) clocks to dtsi Signed-off-by: Wolfram Sang [horms+renesas@verge.net.au resolved conflicts] [horms+renesas@verge.net.au consistently use space as separator] Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index c4b9ff731f72..79855e39469c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -702,18 +702,19 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, - <&mmc0_clk>, <&rclk_clk>; + clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, + <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, + <&hp_clk>, <&hp_clk>, <&rclk_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 - R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 + R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 + R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 >; clock-output-names = - "tpu0", "mmcif1", "sdhi3", "sdhi2", - "sdhi1", "sdhi0", "mmcif0", "cmt1"; + "iic2", "tpu0", "mmcif1", "sdhi3", + "sdhi2", "sdhi1", "sdhi0", "mmcif0", + "iic0", "iic1", "cmt1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -757,16 +758,16 @@ mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, + clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD - R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 - R8A7790_CLK_I2C0 + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS + R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 >; clock-output-names = - "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0"; + "rcan1", "rcan0", "qspi_mod", "iic3", + "i2c3", "i2c2", "i2c1", "i2c0"; }; }; -- cgit v1.2.3 From 05f3991622013692b8ef428a6703663331544248 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 25 Mar 2014 19:56:29 +0100 Subject: ARM: shmobile: r8a7790: add IIC(B) cores to dtsi Signed-off-by: Wolfram Sang Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 79855e39469c..bf2db38eade1 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -24,6 +24,10 @@ i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + i2c4 = &iic0; + i2c5 = &iic1; + i2c6 = &iic2; + i2c7 = &iic3; spi0 = &qspi; spi1 = &msiof0; spi2 = &msiof1; @@ -236,6 +240,46 @@ status = "disabled"; }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + status = "disabled"; + }; + + iic2: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe6520000 0 0x425>; + interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + status = "disabled"; + }; + mmcif0: mmcif@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; -- cgit v1.2.3 From a9d83bd6abc00e14e2db1660e2c7d889745bb3aa Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 13 Apr 2014 17:56:42 -0700 Subject: ARM: shmobile: r8a7778: remove old style audio clock Current sound driver moves to new style clock, but is keeping compatiblity at this point. Move to new style on r8a7778 Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7778.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index 2009a9bc6356..201fc487e4e1 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c @@ -175,10 +175,6 @@ static struct clk mstp_clks[MSTP_NR] = { static struct clk_lookup lookups[] = { /* main */ - CLKDEV_CON_ID("audio_clk_a", &audio_clk_a), - CLKDEV_CON_ID("audio_clk_b", &audio_clk_b), - CLKDEV_CON_ID("audio_clk_c", &audio_clk_c), - CLKDEV_CON_ID("audio_clk_internal", &s1_clk), CLKDEV_CON_ID("shyway_clk", &s_clk), CLKDEV_CON_ID("peripheral_clk", &p_clk), @@ -234,15 +230,15 @@ static struct clk_lookup lookups[] = { CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), - CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]), - CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]), - CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]), - CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]), - CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]), - CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]), - CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]), - CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]), - CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]), + CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]), + CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]), + CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]), + CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]), + CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]), + CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]), + CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]), + CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]), + CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]), }; void __init r8a7778_clock_init(void) -- cgit v1.2.3 From 932616eed0308cbebbb20a079e4bed3674bf1117 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 13 Apr 2014 17:56:50 -0700 Subject: ARM: shmobile: r8a7790: remove old style audio clock Current sound driver moves to new style clock, but is keeping compatiblity at this point. Move to new style on r8a7790 Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/clock-r8a7790.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 331013995fe3..a936ae7de083 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -294,10 +294,6 @@ static struct clk mstp_clks[MSTP_NR] = { static struct clk_lookup lookups[] = { /* main clocks */ - CLKDEV_CON_ID("audio_clk_a", &audio_clk_a), - CLKDEV_CON_ID("audio_clk_b", &audio_clk_b), - CLKDEV_CON_ID("audio_clk_c", &audio_clk_c), - CLKDEV_CON_ID("audio_clk_internal", &m2_clk), CLKDEV_CON_ID("extal", &extal_clk), CLKDEV_CON_ID("extal_div2", &extal_div2_clk), CLKDEV_CON_ID("main", &main_clk), @@ -381,16 +377,16 @@ static struct clk_lookup lookups[] = { CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b), CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c), CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk), - CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP1031]), - CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP1030]), - CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP1029]), - CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP1028]), - CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP1027]), - CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP1026]), - CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP1025]), - CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP1024]), - CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP1023]), - CLKDEV_ICK_ID("scu.9", "rcar_sound", &mstp_clks[MSTP1022]), + CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]), + CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]), + CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]), + CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]), + CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]), + CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]), + CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]), + CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]), + CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]), + CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]), CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]), CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]), CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]), -- cgit v1.2.3 From 115897dab004f580fc8b4c6bab057940ccb64989 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 13 Apr 2014 17:56:57 -0700 Subject: ARM: shmobile: bockw: remove old style audio clock Current audio clock didn't have dependency to device/driver, but, it was not good design for DT support. To avoid branch merge conflict issue, it is using this load map, and this patch is 3) part. 1) add new style clock in platform 2) add new style clock method in driver 3) remove old tyle clock from platform Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-bockw.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index b4122f8cb8d9..1aca107f959f 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -591,6 +591,7 @@ static void __init bockw_init(void) { void __iomem *base; struct clk *clk; + struct platform_device *pdev; int i; r8a7778_clock_init(); @@ -673,9 +674,6 @@ static void __init bockw_init(void) } /* for Audio */ - clk = clk_get(NULL, "audio_clk_b"); - clk_set_rate(clk, 24576000); - clk_put(clk); rsnd_codec_power(5, 1); /* enable ak4642 */ platform_device_register_simple( @@ -684,11 +682,15 @@ static void __init bockw_init(void) platform_device_register_simple( "ak4554-adc-dac", 1, NULL, 0); - platform_device_register_resndata( + pdev = platform_device_register_resndata( &platform_bus, "rcar_sound", -1, rsnd_resources, ARRAY_SIZE(rsnd_resources), &rsnd_info, sizeof(rsnd_info)); + clk = clk_get(&pdev->dev, "clk_b"); + clk_set_rate(clk, 24576000); + clk_put(clk); + for (i = 0; i < ARRAY_SIZE(rsnd_card_info); i++) { struct platform_device_info cardinfo = { .parent = &platform_bus, -- cgit v1.2.3 From a3f50d1bdd47dfa07cb42f7d954739389664f166 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 13 Apr 2014 17:57:05 -0700 Subject: ARM: shmobile: bockw: switch to use dai info for R-Car sound Now, R-Car sound driver supports dai info settings. switch to use it Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-bockw.c | 53 ++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 1aca107f959f..f444be2f241e 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c @@ -345,24 +345,39 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = { RSND_SSI_UNUSED, /* SSI 0 */ RSND_SSI_UNUSED, /* SSI 1 */ RSND_SSI_UNUSED, /* SSI 2 */ - RSND_SSI_SET(1, HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), RSND_SSI_PLAY), - RSND_SSI_SET(2, HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE), - RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), RSND_SSI_PLAY), - RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0), - RSND_SSI_SET(3, HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), RSND_SSI_PLAY), - RSND_SSI_SET(4, HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE), + RSND_SSI(HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), 0), + RSND_SSI(HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE), + RSND_SSI(HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), 0), + RSND_SSI(HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0), + RSND_SSI(HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), 0), + RSND_SSI(HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE), }; -static struct rsnd_scu_platform_info rsnd_scu[9] = { - { .flags = 0, }, /* SRU 0 */ - { .flags = 0, }, /* SRU 1 */ - { .flags = 0, }, /* SRU 2 */ - { .flags = RSND_SCU_USE_HPBIF, }, - { .flags = RSND_SCU_USE_HPBIF, }, - { .flags = RSND_SCU_USE_HPBIF, }, - { .flags = RSND_SCU_USE_HPBIF, }, - { .flags = RSND_SCU_USE_HPBIF, }, - { .flags = RSND_SCU_USE_HPBIF, }, +static struct rsnd_src_platform_info rsnd_src[9] = { + RSND_SRC_UNUSED, /* SRU 0 */ + RSND_SRC_UNUSED, /* SRU 1 */ + RSND_SRC_UNUSED, /* SRU 2 */ + RSND_SRC(0, 0), + RSND_SRC(0, 0), + RSND_SRC(0, 0), + RSND_SRC(0, 0), + RSND_SRC(0, 0), + RSND_SRC(0, 0), +}; + +static struct rsnd_dai_platform_info rsnd_dai[] = { + { + .playback = { .ssi = &rsnd_ssi[5], .src = &rsnd_src[5] }, + .capture = { .ssi = &rsnd_ssi[6], .src = &rsnd_src[6] }, + }, { + .playback = { .ssi = &rsnd_ssi[3], .src = &rsnd_src[3] }, + }, { + .capture = { .ssi = &rsnd_ssi[4], .src = &rsnd_src[4] }, + }, { + .playback = { .ssi = &rsnd_ssi[7], .src = &rsnd_src[7] }, + }, { + .capture = { .ssi = &rsnd_ssi[8], .src = &rsnd_src[8] }, + }, }; enum { @@ -437,8 +452,10 @@ static struct rcar_snd_info rsnd_info = { .flags = RSND_GEN1, .ssi_info = rsnd_ssi, .ssi_info_nr = ARRAY_SIZE(rsnd_ssi), - .scu_info = rsnd_scu, - .scu_info_nr = ARRAY_SIZE(rsnd_scu), + .src_info = rsnd_src, + .src_info_nr = ARRAY_SIZE(rsnd_src), + .dai_info = rsnd_dai, + .dai_info_nr = ARRAY_SIZE(rsnd_dai), .start = rsnd_start, .stop = rsnd_stop, }; -- cgit v1.2.3 From 50f359d7389be354b46d781f3b234d3008d20f2f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Sun, 13 Apr 2014 17:57:12 -0700 Subject: ARM: shmobile: lager: switch to use dai info for R-Car sound Now, R-Car sound driver supports dai info settings. switch to use it Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-lager.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index f0104bfe544e..6af09e1e0841 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -567,20 +567,27 @@ static struct resource rsnd_resources[] __initdata = { }; static struct rsnd_ssi_platform_info rsnd_ssi[] = { - RSND_SSI_SET(0, 0, gic_spi(370), RSND_SSI_PLAY), - RSND_SSI_SET(0, 0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE), + RSND_SSI(0, gic_spi(370), 0), + RSND_SSI(0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE), }; -static struct rsnd_scu_platform_info rsnd_scu[2] = { +static struct rsnd_src_platform_info rsnd_src[2] = { /* no member at this point */ }; +static struct rsnd_dai_platform_info rsnd_dai = { + .playback = { .ssi = &rsnd_ssi[0], }, + .capture = { .ssi = &rsnd_ssi[1], }, +}; + static struct rcar_snd_info rsnd_info = { .flags = RSND_GEN2, .ssi_info = rsnd_ssi, .ssi_info_nr = ARRAY_SIZE(rsnd_ssi), - .scu_info = rsnd_scu, - .scu_info_nr = ARRAY_SIZE(rsnd_scu), + .src_info = rsnd_src, + .src_info_nr = ARRAY_SIZE(rsnd_src), + .dai_info = &rsnd_dai, + .dai_info_nr = 1, }; static struct asoc_simple_card_info rsnd_card_info = { -- cgit v1.2.3 From a42ea603594c1d236a9770c5334edb0defeeada5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:02 +0200 Subject: ARM: sun6i: dt: Fixup prcm node name The prcm lives at address 0x01f01400 as the reg entry in its node already correctly indicates, rename the node to match this. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa74827c..bc46814d2ff0 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -479,14 +479,14 @@ interrupts = <1 9 0xf04>; }; + prcm@01f01400 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + }; + cpucfg@01f01c00 { compatible = "allwinner,sun6i-a31-cpuconfig"; reg = <0x01f01c00 0x300>; }; - - prcm@01f01c00 { - compatible = "allwinner,sun6i-a31-prcm"; - reg = <0x01f01400 0x200>; - }; }; }; -- cgit v1.2.3 From 60bbe31649ed65643f0b2b910a2d3191d10e7d4e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:03 +0200 Subject: ARM: sun4i: dt: Add address- and size-cells info to i2c controller nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 9174724571e2..fe845ebc27be 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -647,6 +647,8 @@ clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { @@ -656,6 +658,8 @@ clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { @@ -665,6 +669,8 @@ clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; }; }; -- cgit v1.2.3 From a470342e645400e4d05eb52e4488b9d2ca48b19c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:04 +0200 Subject: ARM: sun5i: dt: Add address- and size-cells info to i2c controller nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index f01c315bdc4b..d0836d43c28d 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -467,6 +467,8 @@ clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { @@ -476,6 +478,8 @@ clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { @@ -485,6 +489,8 @@ clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; timer@01c60000 { -- cgit v1.2.3 From d1412aed95ad80758a3dc532b368890dd846d39d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 13 Apr 2014 13:41:05 +0200 Subject: ARM: sun7i: dt: Add address- and size-cells info to i2c controller nodes Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 32efc105df83..88171f419e35 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -776,6 +776,8 @@ clocks = <&apb1_gates 0>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@01c2b000 { @@ -785,6 +787,8 @@ clocks = <&apb1_gates 1>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@01c2b400 { @@ -794,6 +798,8 @@ clocks = <&apb1_gates 2>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c3: i2c@01c2b800 { @@ -803,6 +809,8 @@ clocks = <&apb1_gates 3>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c4: i2c@01c2bc00 { @@ -812,6 +820,8 @@ clocks = <&apb1_gates 15>; clock-frequency = <100000>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; gmac: ethernet@01c50000 { -- cgit v1.2.3 From 79a51b25badae79d2da6f7b54530adf56697f669 Mon Sep 17 00:00:00 2001 From: Prarit Bhargava Date: Wed, 2 Apr 2014 08:13:47 -0400 Subject: x86/irq: Clean up VECTOR_UNDEFINED and VECTOR_RETRIGGERED definition During another patch review, David Rientjes noted that VECTOR_UNDEFINED and VECTOR_RETRIGGERED should be defined with ()s so that they are not erroneously used in an arithmetic operation. Suggested-by: David Rientjes Signed-off-by: Prarit Bhargava Cc: Seiji Aguchi Cc: Yang Zhang Link: http://lkml.kernel.org/r/1396440827-18352-1-git-send-email-prarit@redhat.com Signed-off-by: Ingo Molnar --- arch/x86/include/asm/hw_irq.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h index a307b7530e54..4615906d83df 100644 --- a/arch/x86/include/asm/hw_irq.h +++ b/arch/x86/include/asm/hw_irq.h @@ -190,8 +190,8 @@ extern void (*__initconst interrupt[NR_VECTORS-FIRST_EXTERNAL_VECTOR])(void); #define trace_interrupt interrupt #endif -#define VECTOR_UNDEFINED -1 -#define VECTOR_RETRIGGERED -2 +#define VECTOR_UNDEFINED (-1) +#define VECTOR_RETRIGGERED (-2) typedef int vector_irq_t[NR_VECTORS]; DECLARE_PER_CPU(vector_irq_t, vector_irq); -- cgit v1.2.3 From 766e3721990d2c78e0d614b57753f105adbaa8c5 Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Fri, 4 Apr 2014 16:27:17 +0800 Subject: spi: convert spi-bfin-v3.c to a multiplatform driver Spi v3 controller is not only used on Blackfin. So rename it and use ioread/iowrite api to make it work on other platform. Signed-off-by: Scott Jiang Signed-off-by: Mark Brown --- arch/blackfin/include/asm/bfin_spi3.h | 258 --------- arch/blackfin/mach-bf609/boards/ezkit.c | 22 +- drivers/spi/Kconfig | 4 +- drivers/spi/Makefile | 2 +- drivers/spi/spi-adi-v3.c | 985 ++++++++++++++++++++++++++++++++ drivers/spi/spi-bfin-v3.c | 965 ------------------------------- include/linux/spi/adi_spi3.h | 254 ++++++++ 7 files changed, 1253 insertions(+), 1237 deletions(-) delete mode 100644 arch/blackfin/include/asm/bfin_spi3.h create mode 100644 drivers/spi/spi-adi-v3.c delete mode 100644 drivers/spi/spi-bfin-v3.c create mode 100644 include/linux/spi/adi_spi3.h (limited to 'arch') diff --git a/arch/blackfin/include/asm/bfin_spi3.h b/arch/blackfin/include/asm/bfin_spi3.h deleted file mode 100644 index 0957e65a54be..000000000000 --- a/arch/blackfin/include/asm/bfin_spi3.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Analog Devices SPI3 controller driver - * - * Copyright (c) 2011 Analog Devices Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef _SPI_CHANNEL_H_ -#define _SPI_CHANNEL_H_ - -#include - -/* SPI_CONTROL */ -#define SPI_CTL_EN 0x00000001 /* Enable */ -#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */ -#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ -#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ -#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */ -#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ -#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ -#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */ -#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */ -#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */ -#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */ -#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */ -#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */ -#define SPI_CTL_LSBF 0x00001000 /* LSB First */ -#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */ -#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */ -#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */ -#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */ -#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */ -#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */ -#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */ -#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */ -#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */ -#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */ -#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */ -#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */ -#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */ -/* SPI_RX_CONTROL */ -#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */ -#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */ -#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */ -#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */ -#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */ -#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */ -#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */ -#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */ -#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */ -#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */ -#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */ -#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */ -#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */ -#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */ -#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */ -#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */ -#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */ -#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */ -#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */ -#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */ -#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */ -#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */ -/* SPI_TX_CONTROL */ -#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */ -#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */ -#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */ -#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */ -#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */ -#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */ -#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */ -#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */ -#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */ -#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */ -#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */ -#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */ -#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */ -#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */ -#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */ -#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */ -#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */ -#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */ -#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */ -#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */ -#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */ -#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */ -/* SPI_CLOCK */ -#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */ -/* SPI_DELAY */ -#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */ -#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */ -#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */ -/* SPI_SSEL */ -#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */ -#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */ -#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */ -#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */ -#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */ -#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */ -#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */ -#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */ -#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */ -#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */ -#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */ -#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */ -#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */ -#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */ -/* SPI_RWC */ -#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */ -/* SPI_RWCR */ -#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */ -/* SPI_TWC */ -#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */ -/* SPI_TWCR */ -#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */ -/* SPI_IMASK */ -#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ -#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ -#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ -#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ -#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ -#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ -#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */ -#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */ -#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */ -#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ -/* SPI_IMASKCL */ -#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ -#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ -#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ -#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ -#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ -#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ -#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */ -#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */ -#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */ -#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ -/* SPI_IMASKST */ -#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ -#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ -#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ -#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ -#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ -#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ -#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */ -#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */ -#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */ -#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ -/* SPI_STATUS */ -#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */ -#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */ -#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */ -#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */ -#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */ -#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */ -#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */ -#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */ -#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */ -#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */ -#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */ -#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */ -#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */ -#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */ -#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */ -#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */ -#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */ -#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */ -#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */ -#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */ -#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */ -#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */ -#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */ -#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */ -#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */ -#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */ -/* SPI_ILAT */ -#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ -#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ -#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */ -#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */ -#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */ -#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */ -#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */ -#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */ -#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */ -#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */ -/* SPI_ILATCL */ -#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ -#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ -#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */ -#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */ -#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */ -#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */ -#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */ -#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */ -#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */ -#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ - -/* - * bfin spi3 registers layout - */ -struct bfin_spi_regs { - u32 revid; - u32 control; - u32 rx_control; - u32 tx_control; - u32 clock; - u32 delay; - u32 ssel; - u32 rwc; - u32 rwcr; - u32 twc; - u32 twcr; - u32 reserved0; - u32 emask; - u32 emaskcl; - u32 emaskst; - u32 reserved1; - u32 status; - u32 elat; - u32 elatcl; - u32 reserved2; - u32 rfifo; - u32 reserved3; - u32 tfifo; -}; - -#define MAX_CTRL_CS 8 /* cs in spi controller */ - -/* device.platform_data for SSP controller devices */ -struct bfin_spi3_master { - u16 num_chipselect; - u16 pin_req[7]; -}; - -/* spi_board_info.controller_data for SPI slave devices, - * copied to spi_device.platform_data ... mostly for dma tuning - */ -struct bfin_spi3_chip { - u32 control; - u16 cs_chg_udelay; /* Some devices require 16-bit delays */ - u32 tx_dummy_val; /* tx value for rx only transfer */ - bool enable_dma; -}; - -#endif /* _SPI_CHANNEL_H_ */ diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c index 943f7e95ec15..1ba4600de69f 100644 --- a/arch/blackfin/mach-bf609/boards/ezkit.c +++ b/arch/blackfin/mach-bf609/boards/ezkit.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include @@ -767,13 +767,13 @@ static struct flash_platform_data bfin_spi_flash_data = { .type = "w25q32", }; -static struct bfin_spi3_chip spi_flash_chip_info = { +static struct adi_spi3_chip spi_flash_chip_info = { .enable_dma = true, /* use dma transfer with this chip*/ }; #endif #if IS_ENABLED(CONFIG_SPI_SPIDEV) -static struct bfin_spi3_chip spidev_chip_info = { +static struct adi_spi3_chip spidev_chip_info = { .enable_dma = true, }; #endif @@ -1736,7 +1736,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif }; -#if IS_ENABLED(CONFIG_SPI_BFIN_V3) +#if IS_ENABLED(CONFIG_SPI_ADI_V3) /* SPI (0) */ static struct resource bfin_spi0_resource[] = { { @@ -1777,13 +1777,13 @@ static struct resource bfin_spi1_resource[] = { }; /* SPI controller data */ -static struct bfin_spi3_master bf60x_spi_master_info0 = { +static struct adi_spi3_master bf60x_spi_master_info0 = { .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, }; static struct platform_device bf60x_spi_master0 = { - .name = "bfin-spi3", + .name = "adi-spi3", .id = 0, /* Bus number */ .num_resources = ARRAY_SIZE(bfin_spi0_resource), .resource = bfin_spi0_resource, @@ -1792,13 +1792,13 @@ static struct platform_device bf60x_spi_master0 = { }, }; -static struct bfin_spi3_master bf60x_spi_master_info1 = { +static struct adi_spi3_master bf60x_spi_master_info1 = { .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, }; static struct platform_device bf60x_spi_master1 = { - .name = "bfin-spi3", + .name = "adi-spi3", .id = 1, /* Bus number */ .num_resources = ARRAY_SIZE(bfin_spi1_resource), .resource = bfin_spi1_resource, @@ -1990,7 +1990,7 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_sdh_device, #endif -#if IS_ENABLED(CONFIG_SPI_BFIN_V3) +#if IS_ENABLED(CONFIG_SPI_ADI_V3) &bf60x_spi_master0, &bf60x_spi_master1, #endif @@ -2051,8 +2051,8 @@ static struct pinctrl_map __initdata bfin_pinmux_map[] = { PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.0", "pinctrl-adi2.0", NULL, "spi0"), - PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi3.1", "pinctrl-adi2.0", NULL, "spi1"), + PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"), + PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 60f2b41c7310..a52e0edb7146 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -91,8 +91,8 @@ config SPI_BFIN5XX help This is the SPI controller master driver for Blackfin 5xx processor. -config SPI_BFIN_V3 - tristate "SPI controller v3 for Blackfin" +config SPI_ADI_V3 + tristate "SPI controller v3 for ADI" depends on BF60x help This is the SPI controller v3 master driver diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index bd792669e563..71e65dfc0ea3 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o -obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o +obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o diff --git a/drivers/spi/spi-adi-v3.c b/drivers/spi/spi-adi-v3.c new file mode 100644 index 000000000000..0c2914cfcdb5 --- /dev/null +++ b/drivers/spi/spi-adi-v3.c @@ -0,0 +1,985 @@ +/* + * Analog Devices SPI3 controller driver + * + * Copyright (c) 2014 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +enum adi_spi_state { + START_STATE, + RUNNING_STATE, + DONE_STATE, + ERROR_STATE +}; + +struct adi_spi_master; + +struct adi_spi_transfer_ops { + void (*write) (struct adi_spi_master *); + void (*read) (struct adi_spi_master *); + void (*duplex) (struct adi_spi_master *); +}; + +/* runtime info for spi master */ +struct adi_spi_master { + /* SPI framework hookup */ + struct spi_master *master; + + /* Regs base of SPI controller */ + struct adi_spi_regs __iomem *regs; + + /* Pin request list */ + u16 *pin_req; + + /* Message Transfer pump */ + struct tasklet_struct pump_transfers; + + /* Current message transfer state info */ + struct spi_message *cur_msg; + struct spi_transfer *cur_transfer; + struct adi_spi_device *cur_chip; + unsigned transfer_len; + + /* transfer buffer */ + void *tx; + void *tx_end; + void *rx; + void *rx_end; + + /* dma info */ + unsigned int tx_dma; + unsigned int rx_dma; + dma_addr_t tx_dma_addr; + dma_addr_t rx_dma_addr; + unsigned long dummy_buffer; /* used in unidirectional transfer */ + unsigned long tx_dma_size; + unsigned long rx_dma_size; + int tx_num; + int rx_num; + + /* store register value for suspend/resume */ + u32 control; + u32 ssel; + + unsigned long sclk; + enum adi_spi_state state; + + const struct adi_spi_transfer_ops *ops; +}; + +struct adi_spi_device { + u32 control; + u32 clock; + u32 ssel; + + u8 cs; + u16 cs_chg_udelay; /* Some devices require > 255usec delay */ + u32 cs_gpio; + u32 tx_dummy_val; /* tx value for rx only transfer */ + bool enable_dma; + const struct adi_spi_transfer_ops *ops; +}; + +static void adi_spi_enable(struct adi_spi_master *drv_data) +{ + u32 ctl; + + ctl = ioread32(&drv_data->regs->control); + ctl |= SPI_CTL_EN; + iowrite32(ctl, &drv_data->regs->control); +} + +static void adi_spi_disable(struct adi_spi_master *drv_data) +{ + u32 ctl; + + ctl = ioread32(&drv_data->regs->control); + ctl &= ~SPI_CTL_EN; + iowrite32(ctl, &drv_data->regs->control); +} + +/* Caculate the SPI_CLOCK register value based on input HZ */ +static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz) +{ + u32 spi_clock = sclk / speed_hz; + + if (spi_clock) + spi_clock--; + return spi_clock; +} + +static int adi_spi_flush(struct adi_spi_master *drv_data) +{ + unsigned long limit = loops_per_jiffy << 1; + + /* wait for stop and clear stat */ + while (!(ioread32(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit) + cpu_relax(); + + iowrite32(0xFFFFFFFF, &drv_data->regs->status); + + return limit; +} + +/* Chip select operation functions for cs_change flag */ +static void adi_spi_cs_active(struct adi_spi_master *drv_data, struct adi_spi_device *chip) +{ + if (likely(chip->cs < MAX_CTRL_CS)) { + u32 reg; + reg = ioread32(&drv_data->regs->ssel); + reg &= ~chip->ssel; + iowrite32(reg, &drv_data->regs->ssel); + } else { + gpio_set_value(chip->cs_gpio, 0); + } +} + +static void adi_spi_cs_deactive(struct adi_spi_master *drv_data, + struct adi_spi_device *chip) +{ + if (likely(chip->cs < MAX_CTRL_CS)) { + u32 reg; + reg = ioread32(&drv_data->regs->ssel); + reg |= chip->ssel; + iowrite32(reg, &drv_data->regs->ssel); + } else { + gpio_set_value(chip->cs_gpio, 1); + } + + /* Move delay here for consistency */ + if (chip->cs_chg_udelay) + udelay(chip->cs_chg_udelay); +} + +/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ +static inline void adi_spi_cs_enable(struct adi_spi_master *drv_data, + struct adi_spi_device *chip) +{ + if (chip->cs < MAX_CTRL_CS) { + u32 reg; + reg = ioread32(&drv_data->regs->ssel); + reg |= chip->ssel >> 8; + iowrite32(reg, &drv_data->regs->ssel); + } +} + +static inline void adi_spi_cs_disable(struct adi_spi_master *drv_data, + struct adi_spi_device *chip) +{ + if (chip->cs < MAX_CTRL_CS) { + u32 reg; + reg = ioread32(&drv_data->regs->ssel); + reg &= ~(chip->ssel >> 8); + iowrite32(reg, &drv_data->regs->ssel); + } +} + +/* stop controller and re-config current chip*/ +static void adi_spi_restore_state(struct adi_spi_master *drv_data) +{ + struct adi_spi_device *chip = drv_data->cur_chip; + + /* Clear status and disable clock */ + iowrite32(0xFFFFFFFF, &drv_data->regs->status); + iowrite32(0x0, &drv_data->regs->rx_control); + iowrite32(0x0, &drv_data->regs->tx_control); + adi_spi_disable(drv_data); + + /* Load the registers */ + iowrite32(chip->control, &drv_data->regs->control); + iowrite32(chip->clock, &drv_data->regs->clock); + + adi_spi_enable(drv_data); + drv_data->tx_num = drv_data->rx_num = 0; + /* we always choose tx transfer initiate */ + iowrite32(SPI_RXCTL_REN, &drv_data->regs->rx_control); + iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI, &drv_data->regs->tx_control); + adi_spi_cs_active(drv_data, chip); +} + +/* discard invalid rx data and empty rfifo */ +static inline void dummy_read(struct adi_spi_master *drv_data) +{ + while (!(ioread32(&drv_data->regs->status) & SPI_STAT_RFE)) + ioread32(&drv_data->regs->rfifo); +} + +static void adi_spi_u8_write(struct adi_spi_master *drv_data) +{ + dummy_read(drv_data); + while (drv_data->tx < drv_data->tx_end) { + iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo); + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + ioread32(&drv_data->regs->rfifo); + } +} + +static void adi_spi_u8_read(struct adi_spi_master *drv_data) +{ + u32 tx_val = drv_data->cur_chip->tx_dummy_val; + + dummy_read(drv_data); + while (drv_data->rx < drv_data->rx_end) { + iowrite32(tx_val, &drv_data->regs->tfifo); + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo); + } +} + +static void adi_spi_u8_duplex(struct adi_spi_master *drv_data) +{ + dummy_read(drv_data); + while (drv_data->rx < drv_data->rx_end) { + iowrite32(*(u8 *)(drv_data->tx++), &drv_data->regs->tfifo); + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + *(u8 *)(drv_data->rx++) = ioread32(&drv_data->regs->rfifo); + } +} + +static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u8 = { + .write = adi_spi_u8_write, + .read = adi_spi_u8_read, + .duplex = adi_spi_u8_duplex, +}; + +static void adi_spi_u16_write(struct adi_spi_master *drv_data) +{ + dummy_read(drv_data); + while (drv_data->tx < drv_data->tx_end) { + iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo); + drv_data->tx += 2; + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + ioread32(&drv_data->regs->rfifo); + } +} + +static void adi_spi_u16_read(struct adi_spi_master *drv_data) +{ + u32 tx_val = drv_data->cur_chip->tx_dummy_val; + + dummy_read(drv_data); + while (drv_data->rx < drv_data->rx_end) { + iowrite32(tx_val, &drv_data->regs->tfifo); + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); + drv_data->rx += 2; + } +} + +static void adi_spi_u16_duplex(struct adi_spi_master *drv_data) +{ + dummy_read(drv_data); + while (drv_data->rx < drv_data->rx_end) { + iowrite32(*(u16 *)drv_data->tx, &drv_data->regs->tfifo); + drv_data->tx += 2; + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + *(u16 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); + drv_data->rx += 2; + } +} + +static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u16 = { + .write = adi_spi_u16_write, + .read = adi_spi_u16_read, + .duplex = adi_spi_u16_duplex, +}; + +static void adi_spi_u32_write(struct adi_spi_master *drv_data) +{ + dummy_read(drv_data); + while (drv_data->tx < drv_data->tx_end) { + iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo); + drv_data->tx += 4; + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + ioread32(&drv_data->regs->rfifo); + } +} + +static void adi_spi_u32_read(struct adi_spi_master *drv_data) +{ + u32 tx_val = drv_data->cur_chip->tx_dummy_val; + + dummy_read(drv_data); + while (drv_data->rx < drv_data->rx_end) { + iowrite32(tx_val, &drv_data->regs->tfifo); + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); + drv_data->rx += 4; + } +} + +static void adi_spi_u32_duplex(struct adi_spi_master *drv_data) +{ + dummy_read(drv_data); + while (drv_data->rx < drv_data->rx_end) { + iowrite32(*(u32 *)drv_data->tx, &drv_data->regs->tfifo); + drv_data->tx += 4; + while (ioread32(&drv_data->regs->status) & SPI_STAT_RFE) + cpu_relax(); + *(u32 *)drv_data->rx = ioread32(&drv_data->regs->rfifo); + drv_data->rx += 4; + } +} + +static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u32 = { + .write = adi_spi_u32_write, + .read = adi_spi_u32_read, + .duplex = adi_spi_u32_duplex, +}; + + +/* test if there is more transfer to be done */ +static void adi_spi_next_transfer(struct adi_spi_master *drv) +{ + struct spi_message *msg = drv->cur_msg; + struct spi_transfer *t = drv->cur_transfer; + + /* Move to next transfer */ + if (t->transfer_list.next != &msg->transfers) { + drv->cur_transfer = list_entry(t->transfer_list.next, + struct spi_transfer, transfer_list); + drv->state = RUNNING_STATE; + } else { + drv->state = DONE_STATE; + drv->cur_transfer = NULL; + } +} + +static void adi_spi_giveback(struct adi_spi_master *drv_data) +{ + struct adi_spi_device *chip = drv_data->cur_chip; + + adi_spi_cs_deactive(drv_data, chip); + spi_finalize_current_message(drv_data->master); +} + +static int adi_spi_setup_transfer(struct adi_spi_master *drv) +{ + struct spi_transfer *t = drv->cur_transfer; + u32 cr, cr_width; + + if (t->tx_buf) { + drv->tx = (void *)t->tx_buf; + drv->tx_end = drv->tx + t->len; + } else { + drv->tx = NULL; + } + + if (t->rx_buf) { + drv->rx = t->rx_buf; + drv->rx_end = drv->rx + t->len; + } else { + drv->rx = NULL; + } + + drv->transfer_len = t->len; + + /* bits per word setup */ + switch (t->bits_per_word) { + case 8: + cr_width = SPI_CTL_SIZE08; + drv->ops = &adi_spi_transfer_ops_u8; + break; + case 16: + cr_width = SPI_CTL_SIZE16; + drv->ops = &adi_spi_transfer_ops_u16; + break; + case 32: + cr_width = SPI_CTL_SIZE32; + drv->ops = &adi_spi_transfer_ops_u32; + break; + default: + return -EINVAL; + } + cr = ioread32(&drv->regs->control) & ~SPI_CTL_SIZE; + cr |= cr_width; + iowrite32(cr, &drv->regs->control); + + /* speed setup */ + iowrite32(hz_to_spi_clock(drv->sclk, t->speed_hz), &drv->regs->clock); + return 0; +} + +static int adi_spi_dma_xfer(struct adi_spi_master *drv_data) +{ + struct spi_transfer *t = drv_data->cur_transfer; + struct spi_message *msg = drv_data->cur_msg; + struct adi_spi_device *chip = drv_data->cur_chip; + u32 dma_config; + unsigned long word_count, word_size; + void *tx_buf, *rx_buf; + + switch (t->bits_per_word) { + case 8: + dma_config = WDSIZE_8 | PSIZE_8; + word_count = drv_data->transfer_len; + word_size = 1; + break; + case 16: + dma_config = WDSIZE_16 | PSIZE_16; + word_count = drv_data->transfer_len / 2; + word_size = 2; + break; + default: + dma_config = WDSIZE_32 | PSIZE_32; + word_count = drv_data->transfer_len / 4; + word_size = 4; + break; + } + + if (!drv_data->rx) { + tx_buf = drv_data->tx; + rx_buf = &drv_data->dummy_buffer; + drv_data->tx_dma_size = drv_data->transfer_len; + drv_data->rx_dma_size = sizeof(drv_data->dummy_buffer); + set_dma_x_modify(drv_data->tx_dma, word_size); + set_dma_x_modify(drv_data->rx_dma, 0); + } else if (!drv_data->tx) { + drv_data->dummy_buffer = chip->tx_dummy_val; + tx_buf = &drv_data->dummy_buffer; + rx_buf = drv_data->rx; + drv_data->tx_dma_size = sizeof(drv_data->dummy_buffer); + drv_data->rx_dma_size = drv_data->transfer_len; + set_dma_x_modify(drv_data->tx_dma, 0); + set_dma_x_modify(drv_data->rx_dma, word_size); + } else { + tx_buf = drv_data->tx; + rx_buf = drv_data->rx; + drv_data->tx_dma_size = drv_data->rx_dma_size + = drv_data->transfer_len; + set_dma_x_modify(drv_data->tx_dma, word_size); + set_dma_x_modify(drv_data->rx_dma, word_size); + } + + drv_data->tx_dma_addr = dma_map_single(&msg->spi->dev, + (void *)tx_buf, + drv_data->tx_dma_size, + DMA_TO_DEVICE); + if (dma_mapping_error(&msg->spi->dev, + drv_data->tx_dma_addr)) + return -ENOMEM; + + drv_data->rx_dma_addr = dma_map_single(&msg->spi->dev, + (void *)rx_buf, + drv_data->rx_dma_size, + DMA_FROM_DEVICE); + if (dma_mapping_error(&msg->spi->dev, + drv_data->rx_dma_addr)) { + dma_unmap_single(&msg->spi->dev, + drv_data->tx_dma_addr, + drv_data->tx_dma_size, + DMA_TO_DEVICE); + return -ENOMEM; + } + + dummy_read(drv_data); + set_dma_x_count(drv_data->tx_dma, word_count); + set_dma_x_count(drv_data->rx_dma, word_count); + set_dma_start_addr(drv_data->tx_dma, drv_data->tx_dma_addr); + set_dma_start_addr(drv_data->rx_dma, drv_data->rx_dma_addr); + dma_config |= DMAFLOW_STOP | RESTART | DI_EN; + set_dma_config(drv_data->tx_dma, dma_config); + set_dma_config(drv_data->rx_dma, dma_config | WNR); + enable_dma(drv_data->tx_dma); + enable_dma(drv_data->rx_dma); + + iowrite32(SPI_RXCTL_REN | SPI_RXCTL_RDR_NE, + &drv_data->regs->rx_control); + iowrite32(SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF, + &drv_data->regs->tx_control); + + return 0; +} + +static int adi_spi_pio_xfer(struct adi_spi_master *drv_data) +{ + struct spi_message *msg = drv_data->cur_msg; + + if (!drv_data->rx) { + /* write only half duplex */ + drv_data->ops->write(drv_data); + if (drv_data->tx != drv_data->tx_end) + return -EIO; + } else if (!drv_data->tx) { + /* read only half duplex */ + drv_data->ops->read(drv_data); + if (drv_data->rx != drv_data->rx_end) + return -EIO; + } else { + /* full duplex mode */ + drv_data->ops->duplex(drv_data); + if (drv_data->tx != drv_data->tx_end) + return -EIO; + } + + if (!adi_spi_flush(drv_data)) + return -EIO; + msg->actual_length += drv_data->transfer_len; + tasklet_schedule(&drv_data->pump_transfers); + return 0; +} + +static void adi_spi_pump_transfers(unsigned long data) +{ + struct adi_spi_master *drv_data = (struct adi_spi_master *)data; + struct spi_message *msg = NULL; + struct spi_transfer *t = NULL; + struct adi_spi_device *chip = NULL; + int ret; + + /* Get current state information */ + msg = drv_data->cur_msg; + t = drv_data->cur_transfer; + chip = drv_data->cur_chip; + + /* Handle for abort */ + if (drv_data->state == ERROR_STATE) { + msg->status = -EIO; + adi_spi_giveback(drv_data); + return; + } + + if (drv_data->state == RUNNING_STATE) { + if (t->delay_usecs) + udelay(t->delay_usecs); + if (t->cs_change) + adi_spi_cs_deactive(drv_data, chip); + adi_spi_next_transfer(drv_data); + t = drv_data->cur_transfer; + } + /* Handle end of message */ + if (drv_data->state == DONE_STATE) { + msg->status = 0; + adi_spi_giveback(drv_data); + return; + } + + if ((t->len == 0) || (t->tx_buf == NULL && t->rx_buf == NULL)) { + /* Schedule next transfer tasklet */ + tasklet_schedule(&drv_data->pump_transfers); + return; + } + + ret = adi_spi_setup_transfer(drv_data); + if (ret) { + msg->status = ret; + adi_spi_giveback(drv_data); + } + + iowrite32(0xFFFFFFFF, &drv_data->regs->status); + adi_spi_cs_active(drv_data, chip); + drv_data->state = RUNNING_STATE; + + if (chip->enable_dma) + ret = adi_spi_dma_xfer(drv_data); + else + ret = adi_spi_pio_xfer(drv_data); + if (ret) { + msg->status = ret; + adi_spi_giveback(drv_data); + } +} + +static int adi_spi_transfer_one_message(struct spi_master *master, + struct spi_message *m) +{ + struct adi_spi_master *drv_data = spi_master_get_devdata(master); + + drv_data->cur_msg = m; + drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); + adi_spi_restore_state(drv_data); + + drv_data->state = START_STATE; + drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, + struct spi_transfer, transfer_list); + + tasklet_schedule(&drv_data->pump_transfers); + return 0; +} + +#define MAX_SPI_SSEL 7 + +static const u16 ssel[][MAX_SPI_SSEL] = { + {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, + P_SPI0_SSEL4, P_SPI0_SSEL5, + P_SPI0_SSEL6, P_SPI0_SSEL7}, + + {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, + P_SPI1_SSEL4, P_SPI1_SSEL5, + P_SPI1_SSEL6, P_SPI1_SSEL7}, + + {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, + P_SPI2_SSEL4, P_SPI2_SSEL5, + P_SPI2_SSEL6, P_SPI2_SSEL7}, +}; + +static int adi_spi_setup(struct spi_device *spi) +{ + struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master); + struct adi_spi_device *chip = spi_get_ctldata(spi); + u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE; + int ret = -EINVAL; + + if (!chip) { + struct adi_spi3_chip *chip_info = spi->controller_data; + + chip = kzalloc(sizeof(*chip), GFP_KERNEL); + if (!chip) { + dev_err(&spi->dev, "can not allocate chip data\n"); + return -ENOMEM; + } + if (chip_info) { + if (chip_info->control & ~ctl_reg) { + dev_err(&spi->dev, + "do not set bits that the SPI framework manages\n"); + goto error; + } + chip->control = chip_info->control; + chip->cs_chg_udelay = chip_info->cs_chg_udelay; + chip->tx_dummy_val = chip_info->tx_dummy_val; + chip->enable_dma = chip_info->enable_dma; + } + chip->cs = spi->chip_select; + + if (chip->cs < MAX_CTRL_CS) { + chip->ssel = (1 << chip->cs) << 8; + ret = peripheral_request(ssel[spi->master->bus_num] + [chip->cs-1], dev_name(&spi->dev)); + if (ret) { + dev_err(&spi->dev, "peripheral_request() error\n"); + goto error; + } + } else { + chip->cs_gpio = chip->cs - MAX_CTRL_CS; + ret = gpio_request_one(chip->cs_gpio, GPIOF_OUT_INIT_HIGH, + dev_name(&spi->dev)); + if (ret) { + dev_err(&spi->dev, "gpio_request_one() error\n"); + goto error; + } + } + spi_set_ctldata(spi, chip); + } + + /* force a default base state */ + chip->control &= ctl_reg; + + if (spi->mode & SPI_CPOL) + chip->control |= SPI_CTL_CPOL; + if (spi->mode & SPI_CPHA) + chip->control |= SPI_CTL_CPHA; + if (spi->mode & SPI_LSB_FIRST) + chip->control |= SPI_CTL_LSBF; + chip->control |= SPI_CTL_MSTR; + /* we choose software to controll cs */ + chip->control &= ~SPI_CTL_ASSEL; + + chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz); + + adi_spi_cs_enable(drv_data, chip); + adi_spi_cs_deactive(drv_data, chip); + + return 0; +error: + if (chip) { + kfree(chip); + spi_set_ctldata(spi, NULL); + } + + return ret; +} + +static void adi_spi_cleanup(struct spi_device *spi) +{ + struct adi_spi_device *chip = spi_get_ctldata(spi); + struct adi_spi_master *drv_data = spi_master_get_devdata(spi->master); + + if (!chip) + return; + + if (chip->cs < MAX_CTRL_CS) { + peripheral_free(ssel[spi->master->bus_num] + [chip->cs-1]); + adi_spi_cs_disable(drv_data, chip); + } else { + gpio_free(chip->cs_gpio); + } + + kfree(chip); + spi_set_ctldata(spi, NULL); +} + +static irqreturn_t adi_spi_tx_dma_isr(int irq, void *dev_id) +{ + struct adi_spi_master *drv_data = dev_id; + u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma); + u32 tx_ctl; + + clear_dma_irqstat(drv_data->tx_dma); + if (dma_stat & DMA_DONE) { + drv_data->tx_num++; + } else { + dev_err(&drv_data->master->dev, + "spi tx dma error: %d\n", dma_stat); + if (drv_data->tx) + drv_data->state = ERROR_STATE; + } + tx_ctl = ioread32(&drv_data->regs->tx_control); + tx_ctl &= ~SPI_TXCTL_TDR_NF; + iowrite32(tx_ctl, &drv_data->regs->tx_control); + return IRQ_HANDLED; +} + +static irqreturn_t adi_spi_rx_dma_isr(int irq, void *dev_id) +{ + struct adi_spi_master *drv_data = dev_id; + struct spi_message *msg = drv_data->cur_msg; + u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma); + + clear_dma_irqstat(drv_data->rx_dma); + if (dma_stat & DMA_DONE) { + drv_data->rx_num++; + /* we may fail on tx dma */ + if (drv_data->state != ERROR_STATE) + msg->actual_length += drv_data->transfer_len; + } else { + drv_data->state = ERROR_STATE; + dev_err(&drv_data->master->dev, + "spi rx dma error: %d\n", dma_stat); + } + iowrite32(0, &drv_data->regs->tx_control); + iowrite32(0, &drv_data->regs->rx_control); + if (drv_data->rx_num != drv_data->tx_num) + dev_dbg(&drv_data->master->dev, + "dma interrupt missing: tx=%d,rx=%d\n", + drv_data->tx_num, drv_data->rx_num); + tasklet_schedule(&drv_data->pump_transfers); + return IRQ_HANDLED; +} + +static int adi_spi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct adi_spi3_master *info = dev_get_platdata(dev); + struct spi_master *master; + struct adi_spi_master *drv_data; + struct resource *mem, *res; + unsigned int tx_dma, rx_dma; + unsigned long sclk; + int ret; + + if (!info) { + dev_err(dev, "platform data missing!\n"); + return -ENODEV; + } + + sclk = get_sclk1(); + if (!sclk) { + dev_err(dev, "can not get sclk1\n"); + return -ENXIO; + } + + res = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (!res) { + dev_err(dev, "can not get tx dma resource\n"); + return -ENXIO; + } + tx_dma = res->start; + + res = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (!res) { + dev_err(dev, "can not get rx dma resource\n"); + return -ENXIO; + } + rx_dma = res->start; + + /* allocate master with space for drv_data */ + master = spi_alloc_master(dev, sizeof(*drv_data)); + if (!master) { + dev_err(dev, "can not alloc spi_master\n"); + return -ENOMEM; + } + platform_set_drvdata(pdev, master); + + /* the mode bits supported by this driver */ + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; + + master->bus_num = pdev->id; + master->num_chipselect = info->num_chipselect; + master->cleanup = adi_spi_cleanup; + master->setup = adi_spi_setup; + master->transfer_one_message = adi_spi_transfer_one_message; + master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | + SPI_BPW_MASK(8); + + drv_data = spi_master_get_devdata(master); + drv_data->master = master; + drv_data->tx_dma = tx_dma; + drv_data->rx_dma = rx_dma; + drv_data->pin_req = info->pin_req; + drv_data->sclk = sclk; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drv_data->regs = devm_ioremap_resource(dev, mem); + if (IS_ERR(drv_data->regs)) { + ret = PTR_ERR(drv_data->regs); + goto err_put_master; + } + + /* request tx and rx dma */ + ret = request_dma(tx_dma, "SPI_TX_DMA"); + if (ret) { + dev_err(dev, "can not request SPI TX DMA channel\n"); + goto err_put_master; + } + set_dma_callback(tx_dma, adi_spi_tx_dma_isr, drv_data); + + ret = request_dma(rx_dma, "SPI_RX_DMA"); + if (ret) { + dev_err(dev, "can not request SPI RX DMA channel\n"); + goto err_free_tx_dma; + } + set_dma_callback(drv_data->rx_dma, adi_spi_rx_dma_isr, drv_data); + + /* request CLK, MOSI and MISO */ + ret = peripheral_request_list(drv_data->pin_req, "adi-spi3"); + if (ret < 0) { + dev_err(dev, "can not request spi pins\n"); + goto err_free_rx_dma; + } + + iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control); + iowrite32(0x0000FE00, &drv_data->regs->ssel); + iowrite32(0x0, &drv_data->regs->delay); + + tasklet_init(&drv_data->pump_transfers, + adi_spi_pump_transfers, (unsigned long)drv_data); + /* register with the SPI framework */ + ret = devm_spi_register_master(dev, master); + if (ret) { + dev_err(dev, "can not register spi master\n"); + goto err_free_peripheral; + } + + return ret; + +err_free_peripheral: + peripheral_free_list(drv_data->pin_req); +err_free_rx_dma: + free_dma(rx_dma); +err_free_tx_dma: + free_dma(tx_dma); +err_put_master: + spi_master_put(master); + + return ret; +} + +static int adi_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct adi_spi_master *drv_data = spi_master_get_devdata(master); + + adi_spi_disable(drv_data); + peripheral_free_list(drv_data->pin_req); + free_dma(drv_data->rx_dma); + free_dma(drv_data->tx_dma); + return 0; +} + +#ifdef CONFIG_PM +static int adi_spi_suspend(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct adi_spi_master *drv_data = spi_master_get_devdata(master); + + spi_master_suspend(master); + + drv_data->control = ioread32(&drv_data->regs->control); + drv_data->ssel = ioread32(&drv_data->regs->ssel); + + iowrite32(SPI_CTL_MSTR | SPI_CTL_CPHA, &drv_data->regs->control); + iowrite32(0x0000FE00, &drv_data->regs->ssel); + dma_disable_irq(drv_data->rx_dma); + dma_disable_irq(drv_data->tx_dma); + + return 0; +} + +static int adi_spi_resume(struct device *dev) +{ + struct spi_master *master = dev_get_drvdata(dev); + struct adi_spi_master *drv_data = spi_master_get_devdata(master); + int ret = 0; + + /* bootrom may modify spi and dma status when resume in spi boot mode */ + disable_dma(drv_data->rx_dma); + + dma_enable_irq(drv_data->rx_dma); + dma_enable_irq(drv_data->tx_dma); + iowrite32(drv_data->control, &drv_data->regs->control); + iowrite32(drv_data->ssel, &drv_data->regs->ssel); + + ret = spi_master_resume(master); + if (ret) { + free_dma(drv_data->rx_dma); + free_dma(drv_data->tx_dma); + } + + return ret; +} +#endif +static const struct dev_pm_ops adi_spi_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(adi_spi_suspend, adi_spi_resume) +}; + +MODULE_ALIAS("platform:adi-spi3"); +static struct platform_driver adi_spi_driver = { + .driver = { + .name = "adi-spi3", + .owner = THIS_MODULE, + .pm = &adi_spi_pm_ops, + }, + .remove = adi_spi_remove, +}; + +module_platform_driver_probe(adi_spi_driver, adi_spi_probe); + +MODULE_DESCRIPTION("Analog Devices SPI3 controller driver"); +MODULE_AUTHOR("Scott Jiang "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/spi/spi-bfin-v3.c b/drivers/spi/spi-bfin-v3.c deleted file mode 100644 index 4089d0e0d84e..000000000000 --- a/drivers/spi/spi-bfin-v3.c +++ /dev/null @@ -1,965 +0,0 @@ -/* - * Analog Devices SPI3 controller driver - * - * Copyright (c) 2013 Analog Devices Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -enum bfin_spi_state { - START_STATE, - RUNNING_STATE, - DONE_STATE, - ERROR_STATE -}; - -struct bfin_spi_master; - -struct bfin_spi_transfer_ops { - void (*write) (struct bfin_spi_master *); - void (*read) (struct bfin_spi_master *); - void (*duplex) (struct bfin_spi_master *); -}; - -/* runtime info for spi master */ -struct bfin_spi_master { - /* SPI framework hookup */ - struct spi_master *master; - - /* Regs base of SPI controller */ - struct bfin_spi_regs __iomem *regs; - - /* Pin request list */ - u16 *pin_req; - - /* Message Transfer pump */ - struct tasklet_struct pump_transfers; - - /* Current message transfer state info */ - struct spi_message *cur_msg; - struct spi_transfer *cur_transfer; - struct bfin_spi_device *cur_chip; - unsigned transfer_len; - - /* transfer buffer */ - void *tx; - void *tx_end; - void *rx; - void *rx_end; - - /* dma info */ - unsigned int tx_dma; - unsigned int rx_dma; - dma_addr_t tx_dma_addr; - dma_addr_t rx_dma_addr; - unsigned long dummy_buffer; /* used in unidirectional transfer */ - unsigned long tx_dma_size; - unsigned long rx_dma_size; - int tx_num; - int rx_num; - - /* store register value for suspend/resume */ - u32 control; - u32 ssel; - - unsigned long sclk; - enum bfin_spi_state state; - - const struct bfin_spi_transfer_ops *ops; -}; - -struct bfin_spi_device { - u32 control; - u32 clock; - u32 ssel; - - u8 cs; - u16 cs_chg_udelay; /* Some devices require > 255usec delay */ - u32 cs_gpio; - u32 tx_dummy_val; /* tx value for rx only transfer */ - bool enable_dma; - const struct bfin_spi_transfer_ops *ops; -}; - -static void bfin_spi_enable(struct bfin_spi_master *drv_data) -{ - bfin_write_or(&drv_data->regs->control, SPI_CTL_EN); -} - -static void bfin_spi_disable(struct bfin_spi_master *drv_data) -{ - bfin_write_and(&drv_data->regs->control, ~SPI_CTL_EN); -} - -/* Caculate the SPI_CLOCK register value based on input HZ */ -static u32 hz_to_spi_clock(u32 sclk, u32 speed_hz) -{ - u32 spi_clock = sclk / speed_hz; - - if (spi_clock) - spi_clock--; - return spi_clock; -} - -static int bfin_spi_flush(struct bfin_spi_master *drv_data) -{ - unsigned long limit = loops_per_jiffy << 1; - - /* wait for stop and clear stat */ - while (!(bfin_read(&drv_data->regs->status) & SPI_STAT_SPIF) && --limit) - cpu_relax(); - - bfin_write(&drv_data->regs->status, 0xFFFFFFFF); - - return limit; -} - -/* Chip select operation functions for cs_change flag */ -static void bfin_spi_cs_active(struct bfin_spi_master *drv_data, struct bfin_spi_device *chip) -{ - if (likely(chip->cs < MAX_CTRL_CS)) - bfin_write_and(&drv_data->regs->ssel, ~chip->ssel); - else - gpio_set_value(chip->cs_gpio, 0); -} - -static void bfin_spi_cs_deactive(struct bfin_spi_master *drv_data, - struct bfin_spi_device *chip) -{ - if (likely(chip->cs < MAX_CTRL_CS)) - bfin_write_or(&drv_data->regs->ssel, chip->ssel); - else - gpio_set_value(chip->cs_gpio, 1); - - /* Move delay here for consistency */ - if (chip->cs_chg_udelay) - udelay(chip->cs_chg_udelay); -} - -/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ -static inline void bfin_spi_cs_enable(struct bfin_spi_master *drv_data, - struct bfin_spi_device *chip) -{ - if (chip->cs < MAX_CTRL_CS) - bfin_write_or(&drv_data->regs->ssel, chip->ssel >> 8); -} - -static inline void bfin_spi_cs_disable(struct bfin_spi_master *drv_data, - struct bfin_spi_device *chip) -{ - if (chip->cs < MAX_CTRL_CS) - bfin_write_and(&drv_data->regs->ssel, ~(chip->ssel >> 8)); -} - -/* stop controller and re-config current chip*/ -static void bfin_spi_restore_state(struct bfin_spi_master *drv_data) -{ - struct bfin_spi_device *chip = drv_data->cur_chip; - - /* Clear status and disable clock */ - bfin_write(&drv_data->regs->status, 0xFFFFFFFF); - bfin_write(&drv_data->regs->rx_control, 0x0); - bfin_write(&drv_data->regs->tx_control, 0x0); - bfin_spi_disable(drv_data); - - SSYNC(); - - /* Load the registers */ - bfin_write(&drv_data->regs->control, chip->control); - bfin_write(&drv_data->regs->clock, chip->clock); - - bfin_spi_enable(drv_data); - drv_data->tx_num = drv_data->rx_num = 0; - /* we always choose tx transfer initiate */ - bfin_write(&drv_data->regs->rx_control, SPI_RXCTL_REN); - bfin_write(&drv_data->regs->tx_control, - SPI_TXCTL_TEN | SPI_TXCTL_TTI); - bfin_spi_cs_active(drv_data, chip); -} - -/* discard invalid rx data and empty rfifo */ -static inline void dummy_read(struct bfin_spi_master *drv_data) -{ - while (!(bfin_read(&drv_data->regs->status) & SPI_STAT_RFE)) - bfin_read(&drv_data->regs->rfifo); -} - -static void bfin_spi_u8_write(struct bfin_spi_master *drv_data) -{ - dummy_read(drv_data); - while (drv_data->tx < drv_data->tx_end) { - bfin_write(&drv_data->regs->tfifo, (*(u8 *)(drv_data->tx++))); - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - bfin_read(&drv_data->regs->rfifo); - } -} - -static void bfin_spi_u8_read(struct bfin_spi_master *drv_data) -{ - u32 tx_val = drv_data->cur_chip->tx_dummy_val; - - dummy_read(drv_data); - while (drv_data->rx < drv_data->rx_end) { - bfin_write(&drv_data->regs->tfifo, tx_val); - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - *(u8 *)(drv_data->rx++) = bfin_read(&drv_data->regs->rfifo); - } -} - -static void bfin_spi_u8_duplex(struct bfin_spi_master *drv_data) -{ - dummy_read(drv_data); - while (drv_data->rx < drv_data->rx_end) { - bfin_write(&drv_data->regs->tfifo, (*(u8 *)(drv_data->tx++))); - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - *(u8 *)(drv_data->rx++) = bfin_read(&drv_data->regs->rfifo); - } -} - -static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = { - .write = bfin_spi_u8_write, - .read = bfin_spi_u8_read, - .duplex = bfin_spi_u8_duplex, -}; - -static void bfin_spi_u16_write(struct bfin_spi_master *drv_data) -{ - dummy_read(drv_data); - while (drv_data->tx < drv_data->tx_end) { - bfin_write(&drv_data->regs->tfifo, (*(u16 *)drv_data->tx)); - drv_data->tx += 2; - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - bfin_read(&drv_data->regs->rfifo); - } -} - -static void bfin_spi_u16_read(struct bfin_spi_master *drv_data) -{ - u32 tx_val = drv_data->cur_chip->tx_dummy_val; - - dummy_read(drv_data); - while (drv_data->rx < drv_data->rx_end) { - bfin_write(&drv_data->regs->tfifo, tx_val); - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - *(u16 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); - drv_data->rx += 2; - } -} - -static void bfin_spi_u16_duplex(struct bfin_spi_master *drv_data) -{ - dummy_read(drv_data); - while (drv_data->rx < drv_data->rx_end) { - bfin_write(&drv_data->regs->tfifo, (*(u16 *)drv_data->tx)); - drv_data->tx += 2; - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - *(u16 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); - drv_data->rx += 2; - } -} - -static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = { - .write = bfin_spi_u16_write, - .read = bfin_spi_u16_read, - .duplex = bfin_spi_u16_duplex, -}; - -static void bfin_spi_u32_write(struct bfin_spi_master *drv_data) -{ - dummy_read(drv_data); - while (drv_data->tx < drv_data->tx_end) { - bfin_write(&drv_data->regs->tfifo, (*(u32 *)drv_data->tx)); - drv_data->tx += 4; - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - bfin_read(&drv_data->regs->rfifo); - } -} - -static void bfin_spi_u32_read(struct bfin_spi_master *drv_data) -{ - u32 tx_val = drv_data->cur_chip->tx_dummy_val; - - dummy_read(drv_data); - while (drv_data->rx < drv_data->rx_end) { - bfin_write(&drv_data->regs->tfifo, tx_val); - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - *(u32 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); - drv_data->rx += 4; - } -} - -static void bfin_spi_u32_duplex(struct bfin_spi_master *drv_data) -{ - dummy_read(drv_data); - while (drv_data->rx < drv_data->rx_end) { - bfin_write(&drv_data->regs->tfifo, (*(u32 *)drv_data->tx)); - drv_data->tx += 4; - while (bfin_read(&drv_data->regs->status) & SPI_STAT_RFE) - cpu_relax(); - *(u32 *)drv_data->rx = bfin_read(&drv_data->regs->rfifo); - drv_data->rx += 4; - } -} - -static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u32 = { - .write = bfin_spi_u32_write, - .read = bfin_spi_u32_read, - .duplex = bfin_spi_u32_duplex, -}; - - -/* test if there is more transfer to be done */ -static void bfin_spi_next_transfer(struct bfin_spi_master *drv) -{ - struct spi_message *msg = drv->cur_msg; - struct spi_transfer *t = drv->cur_transfer; - - /* Move to next transfer */ - if (t->transfer_list.next != &msg->transfers) { - drv->cur_transfer = list_entry(t->transfer_list.next, - struct spi_transfer, transfer_list); - drv->state = RUNNING_STATE; - } else { - drv->state = DONE_STATE; - drv->cur_transfer = NULL; - } -} - -static void bfin_spi_giveback(struct bfin_spi_master *drv_data) -{ - struct bfin_spi_device *chip = drv_data->cur_chip; - - bfin_spi_cs_deactive(drv_data, chip); - spi_finalize_current_message(drv_data->master); -} - -static int bfin_spi_setup_transfer(struct bfin_spi_master *drv) -{ - struct spi_transfer *t = drv->cur_transfer; - u32 cr, cr_width; - - if (t->tx_buf) { - drv->tx = (void *)t->tx_buf; - drv->tx_end = drv->tx + t->len; - } else { - drv->tx = NULL; - } - - if (t->rx_buf) { - drv->rx = t->rx_buf; - drv->rx_end = drv->rx + t->len; - } else { - drv->rx = NULL; - } - - drv->transfer_len = t->len; - - /* bits per word setup */ - switch (t->bits_per_word) { - case 8: - cr_width = SPI_CTL_SIZE08; - drv->ops = &bfin_bfin_spi_transfer_ops_u8; - break; - case 16: - cr_width = SPI_CTL_SIZE16; - drv->ops = &bfin_bfin_spi_transfer_ops_u16; - break; - case 32: - cr_width = SPI_CTL_SIZE32; - drv->ops = &bfin_bfin_spi_transfer_ops_u32; - break; - default: - return -EINVAL; - } - cr = bfin_read(&drv->regs->control) & ~SPI_CTL_SIZE; - cr |= cr_width; - bfin_write(&drv->regs->control, cr); - - /* speed setup */ - bfin_write(&drv->regs->clock, - hz_to_spi_clock(drv->sclk, t->speed_hz)); - return 0; -} - -static int bfin_spi_dma_xfer(struct bfin_spi_master *drv_data) -{ - struct spi_transfer *t = drv_data->cur_transfer; - struct spi_message *msg = drv_data->cur_msg; - struct bfin_spi_device *chip = drv_data->cur_chip; - u32 dma_config; - unsigned long word_count, word_size; - void *tx_buf, *rx_buf; - - switch (t->bits_per_word) { - case 8: - dma_config = WDSIZE_8 | PSIZE_8; - word_count = drv_data->transfer_len; - word_size = 1; - break; - case 16: - dma_config = WDSIZE_16 | PSIZE_16; - word_count = drv_data->transfer_len / 2; - word_size = 2; - break; - default: - dma_config = WDSIZE_32 | PSIZE_32; - word_count = drv_data->transfer_len / 4; - word_size = 4; - break; - } - - if (!drv_data->rx) { - tx_buf = drv_data->tx; - rx_buf = &drv_data->dummy_buffer; - drv_data->tx_dma_size = drv_data->transfer_len; - drv_data->rx_dma_size = sizeof(drv_data->dummy_buffer); - set_dma_x_modify(drv_data->tx_dma, word_size); - set_dma_x_modify(drv_data->rx_dma, 0); - } else if (!drv_data->tx) { - drv_data->dummy_buffer = chip->tx_dummy_val; - tx_buf = &drv_data->dummy_buffer; - rx_buf = drv_data->rx; - drv_data->tx_dma_size = sizeof(drv_data->dummy_buffer); - drv_data->rx_dma_size = drv_data->transfer_len; - set_dma_x_modify(drv_data->tx_dma, 0); - set_dma_x_modify(drv_data->rx_dma, word_size); - } else { - tx_buf = drv_data->tx; - rx_buf = drv_data->rx; - drv_data->tx_dma_size = drv_data->rx_dma_size - = drv_data->transfer_len; - set_dma_x_modify(drv_data->tx_dma, word_size); - set_dma_x_modify(drv_data->rx_dma, word_size); - } - - drv_data->tx_dma_addr = dma_map_single(&msg->spi->dev, - (void *)tx_buf, - drv_data->tx_dma_size, - DMA_TO_DEVICE); - if (dma_mapping_error(&msg->spi->dev, - drv_data->tx_dma_addr)) - return -ENOMEM; - - drv_data->rx_dma_addr = dma_map_single(&msg->spi->dev, - (void *)rx_buf, - drv_data->rx_dma_size, - DMA_FROM_DEVICE); - if (dma_mapping_error(&msg->spi->dev, - drv_data->rx_dma_addr)) { - dma_unmap_single(&msg->spi->dev, - drv_data->tx_dma_addr, - drv_data->tx_dma_size, - DMA_TO_DEVICE); - return -ENOMEM; - } - - dummy_read(drv_data); - set_dma_x_count(drv_data->tx_dma, word_count); - set_dma_x_count(drv_data->rx_dma, word_count); - set_dma_start_addr(drv_data->tx_dma, drv_data->tx_dma_addr); - set_dma_start_addr(drv_data->rx_dma, drv_data->rx_dma_addr); - dma_config |= DMAFLOW_STOP | RESTART | DI_EN; - set_dma_config(drv_data->tx_dma, dma_config); - set_dma_config(drv_data->rx_dma, dma_config | WNR); - enable_dma(drv_data->tx_dma); - enable_dma(drv_data->rx_dma); - SSYNC(); - - bfin_write(&drv_data->regs->rx_control, SPI_RXCTL_REN | SPI_RXCTL_RDR_NE); - SSYNC(); - bfin_write(&drv_data->regs->tx_control, - SPI_TXCTL_TEN | SPI_TXCTL_TTI | SPI_TXCTL_TDR_NF); - - return 0; -} - -static int bfin_spi_pio_xfer(struct bfin_spi_master *drv_data) -{ - struct spi_message *msg = drv_data->cur_msg; - - if (!drv_data->rx) { - /* write only half duplex */ - drv_data->ops->write(drv_data); - if (drv_data->tx != drv_data->tx_end) - return -EIO; - } else if (!drv_data->tx) { - /* read only half duplex */ - drv_data->ops->read(drv_data); - if (drv_data->rx != drv_data->rx_end) - return -EIO; - } else { - /* full duplex mode */ - drv_data->ops->duplex(drv_data); - if (drv_data->tx != drv_data->tx_end) - return -EIO; - } - - if (!bfin_spi_flush(drv_data)) - return -EIO; - msg->actual_length += drv_data->transfer_len; - tasklet_schedule(&drv_data->pump_transfers); - return 0; -} - -static void bfin_spi_pump_transfers(unsigned long data) -{ - struct bfin_spi_master *drv_data = (struct bfin_spi_master *)data; - struct spi_message *msg = NULL; - struct spi_transfer *t = NULL; - struct bfin_spi_device *chip = NULL; - int ret; - - /* Get current state information */ - msg = drv_data->cur_msg; - t = drv_data->cur_transfer; - chip = drv_data->cur_chip; - - /* Handle for abort */ - if (drv_data->state == ERROR_STATE) { - msg->status = -EIO; - bfin_spi_giveback(drv_data); - return; - } - - if (drv_data->state == RUNNING_STATE) { - if (t->delay_usecs) - udelay(t->delay_usecs); - if (t->cs_change) - bfin_spi_cs_deactive(drv_data, chip); - bfin_spi_next_transfer(drv_data); - t = drv_data->cur_transfer; - } - /* Handle end of message */ - if (drv_data->state == DONE_STATE) { - msg->status = 0; - bfin_spi_giveback(drv_data); - return; - } - - if ((t->len == 0) || (t->tx_buf == NULL && t->rx_buf == NULL)) { - /* Schedule next transfer tasklet */ - tasklet_schedule(&drv_data->pump_transfers); - return; - } - - ret = bfin_spi_setup_transfer(drv_data); - if (ret) { - msg->status = ret; - bfin_spi_giveback(drv_data); - } - - bfin_write(&drv_data->regs->status, 0xFFFFFFFF); - bfin_spi_cs_active(drv_data, chip); - drv_data->state = RUNNING_STATE; - - if (chip->enable_dma) - ret = bfin_spi_dma_xfer(drv_data); - else - ret = bfin_spi_pio_xfer(drv_data); - if (ret) { - msg->status = ret; - bfin_spi_giveback(drv_data); - } -} - -static int bfin_spi_transfer_one_message(struct spi_master *master, - struct spi_message *m) -{ - struct bfin_spi_master *drv_data = spi_master_get_devdata(master); - - drv_data->cur_msg = m; - drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); - bfin_spi_restore_state(drv_data); - - drv_data->state = START_STATE; - drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, - struct spi_transfer, transfer_list); - - tasklet_schedule(&drv_data->pump_transfers); - return 0; -} - -#define MAX_SPI_SSEL 7 - -static const u16 ssel[][MAX_SPI_SSEL] = { - {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, - P_SPI0_SSEL4, P_SPI0_SSEL5, - P_SPI0_SSEL6, P_SPI0_SSEL7}, - - {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, - P_SPI1_SSEL4, P_SPI1_SSEL5, - P_SPI1_SSEL6, P_SPI1_SSEL7}, - - {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, - P_SPI2_SSEL4, P_SPI2_SSEL5, - P_SPI2_SSEL6, P_SPI2_SSEL7}, -}; - -static int bfin_spi_setup(struct spi_device *spi) -{ - struct bfin_spi_master *drv_data = spi_master_get_devdata(spi->master); - struct bfin_spi_device *chip = spi_get_ctldata(spi); - u32 bfin_ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE; - int ret = -EINVAL; - - if (!chip) { - struct bfin_spi3_chip *chip_info = spi->controller_data; - - chip = kzalloc(sizeof(*chip), GFP_KERNEL); - if (!chip) { - dev_err(&spi->dev, "can not allocate chip data\n"); - return -ENOMEM; - } - if (chip_info) { - if (chip_info->control & ~bfin_ctl_reg) { - dev_err(&spi->dev, - "do not set bits that the SPI framework manages\n"); - goto error; - } - chip->control = chip_info->control; - chip->cs_chg_udelay = chip_info->cs_chg_udelay; - chip->tx_dummy_val = chip_info->tx_dummy_val; - chip->enable_dma = chip_info->enable_dma; - } - chip->cs = spi->chip_select; - if (chip->cs < MAX_CTRL_CS) { - chip->ssel = (1 << chip->cs) << 8; - ret = peripheral_request(ssel[spi->master->bus_num] - [chip->cs-1], dev_name(&spi->dev)); - if (ret) { - dev_err(&spi->dev, "peripheral_request() error\n"); - goto error; - } - } else { - chip->cs_gpio = chip->cs - MAX_CTRL_CS; - ret = gpio_request_one(chip->cs_gpio, GPIOF_OUT_INIT_HIGH, - dev_name(&spi->dev)); - if (ret) { - dev_err(&spi->dev, "gpio_request_one() error\n"); - goto error; - } - } - spi_set_ctldata(spi, chip); - } - - /* force a default base state */ - chip->control &= bfin_ctl_reg; - - if (spi->mode & SPI_CPOL) - chip->control |= SPI_CTL_CPOL; - if (spi->mode & SPI_CPHA) - chip->control |= SPI_CTL_CPHA; - if (spi->mode & SPI_LSB_FIRST) - chip->control |= SPI_CTL_LSBF; - chip->control |= SPI_CTL_MSTR; - /* we choose software to controll cs */ - chip->control &= ~SPI_CTL_ASSEL; - - chip->clock = hz_to_spi_clock(drv_data->sclk, spi->max_speed_hz); - - bfin_spi_cs_enable(drv_data, chip); - bfin_spi_cs_deactive(drv_data, chip); - - return 0; -error: - if (chip) { - kfree(chip); - spi_set_ctldata(spi, NULL); - } - - return ret; -} - -static void bfin_spi_cleanup(struct spi_device *spi) -{ - struct bfin_spi_device *chip = spi_get_ctldata(spi); - struct bfin_spi_master *drv_data = spi_master_get_devdata(spi->master); - - if (!chip) - return; - - if (chip->cs < MAX_CTRL_CS) { - peripheral_free(ssel[spi->master->bus_num] - [chip->cs-1]); - bfin_spi_cs_disable(drv_data, chip); - } else { - gpio_free(chip->cs_gpio); - } - - kfree(chip); - spi_set_ctldata(spi, NULL); -} - -static irqreturn_t bfin_spi_tx_dma_isr(int irq, void *dev_id) -{ - struct bfin_spi_master *drv_data = dev_id; - u32 dma_stat = get_dma_curr_irqstat(drv_data->tx_dma); - - clear_dma_irqstat(drv_data->tx_dma); - if (dma_stat & DMA_DONE) { - drv_data->tx_num++; - } else { - dev_err(&drv_data->master->dev, - "spi tx dma error: %d\n", dma_stat); - if (drv_data->tx) - drv_data->state = ERROR_STATE; - } - bfin_write_and(&drv_data->regs->tx_control, ~SPI_TXCTL_TDR_NF); - return IRQ_HANDLED; -} - -static irqreturn_t bfin_spi_rx_dma_isr(int irq, void *dev_id) -{ - struct bfin_spi_master *drv_data = dev_id; - struct spi_message *msg = drv_data->cur_msg; - u32 dma_stat = get_dma_curr_irqstat(drv_data->rx_dma); - - clear_dma_irqstat(drv_data->rx_dma); - if (dma_stat & DMA_DONE) { - drv_data->rx_num++; - /* we may fail on tx dma */ - if (drv_data->state != ERROR_STATE) - msg->actual_length += drv_data->transfer_len; - } else { - drv_data->state = ERROR_STATE; - dev_err(&drv_data->master->dev, - "spi rx dma error: %d\n", dma_stat); - } - bfin_write(&drv_data->regs->tx_control, 0); - bfin_write(&drv_data->regs->rx_control, 0); - if (drv_data->rx_num != drv_data->tx_num) - dev_dbg(&drv_data->master->dev, - "dma interrupt missing: tx=%d,rx=%d\n", - drv_data->tx_num, drv_data->rx_num); - tasklet_schedule(&drv_data->pump_transfers); - return IRQ_HANDLED; -} - -static int bfin_spi_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct bfin_spi3_master *info = dev_get_platdata(dev); - struct spi_master *master; - struct bfin_spi_master *drv_data; - struct resource *mem, *res; - unsigned int tx_dma, rx_dma; - unsigned long sclk; - int ret; - - if (!info) { - dev_err(dev, "platform data missing!\n"); - return -ENODEV; - } - - sclk = get_sclk1(); - if (!sclk) { - dev_err(dev, "can not get sclk1\n"); - return -ENXIO; - } - - res = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (!res) { - dev_err(dev, "can not get tx dma resource\n"); - return -ENXIO; - } - tx_dma = res->start; - - res = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (!res) { - dev_err(dev, "can not get rx dma resource\n"); - return -ENXIO; - } - rx_dma = res->start; - - /* allocate master with space for drv_data */ - master = spi_alloc_master(dev, sizeof(*drv_data)); - if (!master) { - dev_err(dev, "can not alloc spi_master\n"); - return -ENOMEM; - } - platform_set_drvdata(pdev, master); - - /* the mode bits supported by this driver */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; - - master->bus_num = pdev->id; - master->num_chipselect = info->num_chipselect; - master->cleanup = bfin_spi_cleanup; - master->setup = bfin_spi_setup; - master->transfer_one_message = bfin_spi_transfer_one_message; - master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | - SPI_BPW_MASK(8); - - drv_data = spi_master_get_devdata(master); - drv_data->master = master; - drv_data->tx_dma = tx_dma; - drv_data->rx_dma = rx_dma; - drv_data->pin_req = info->pin_req; - drv_data->sclk = sclk; - - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - drv_data->regs = devm_ioremap_resource(dev, mem); - if (IS_ERR(drv_data->regs)) { - ret = PTR_ERR(drv_data->regs); - goto err_put_master; - } - - /* request tx and rx dma */ - ret = request_dma(tx_dma, "SPI_TX_DMA"); - if (ret) { - dev_err(dev, "can not request SPI TX DMA channel\n"); - goto err_put_master; - } - set_dma_callback(tx_dma, bfin_spi_tx_dma_isr, drv_data); - - ret = request_dma(rx_dma, "SPI_RX_DMA"); - if (ret) { - dev_err(dev, "can not request SPI RX DMA channel\n"); - goto err_free_tx_dma; - } - set_dma_callback(drv_data->rx_dma, bfin_spi_rx_dma_isr, drv_data); - - /* request CLK, MOSI and MISO */ - ret = peripheral_request_list(drv_data->pin_req, "bfin-spi3"); - if (ret < 0) { - dev_err(dev, "can not request spi pins\n"); - goto err_free_rx_dma; - } - - bfin_write(&drv_data->regs->control, SPI_CTL_MSTR | SPI_CTL_CPHA); - bfin_write(&drv_data->regs->ssel, 0x0000FE00); - bfin_write(&drv_data->regs->delay, 0x0); - - tasklet_init(&drv_data->pump_transfers, - bfin_spi_pump_transfers, (unsigned long)drv_data); - /* register with the SPI framework */ - ret = devm_spi_register_master(dev, master); - if (ret) { - dev_err(dev, "can not register spi master\n"); - goto err_free_peripheral; - } - - return ret; - -err_free_peripheral: - peripheral_free_list(drv_data->pin_req); -err_free_rx_dma: - free_dma(rx_dma); -err_free_tx_dma: - free_dma(tx_dma); -err_put_master: - spi_master_put(master); - - return ret; -} - -static int bfin_spi_remove(struct platform_device *pdev) -{ - struct spi_master *master = platform_get_drvdata(pdev); - struct bfin_spi_master *drv_data = spi_master_get_devdata(master); - - bfin_spi_disable(drv_data); - - peripheral_free_list(drv_data->pin_req); - free_dma(drv_data->rx_dma); - free_dma(drv_data->tx_dma); - - return 0; -} - -#ifdef CONFIG_PM -static int bfin_spi_suspend(struct device *dev) -{ - struct spi_master *master = dev_get_drvdata(dev); - struct bfin_spi_master *drv_data = spi_master_get_devdata(master); - - spi_master_suspend(master); - - drv_data->control = bfin_read(&drv_data->regs->control); - drv_data->ssel = bfin_read(&drv_data->regs->ssel); - - bfin_write(&drv_data->regs->control, SPI_CTL_MSTR | SPI_CTL_CPHA); - bfin_write(&drv_data->regs->ssel, 0x0000FE00); - dma_disable_irq(drv_data->rx_dma); - dma_disable_irq(drv_data->tx_dma); - - return 0; -} - -static int bfin_spi_resume(struct device *dev) -{ - struct spi_master *master = dev_get_drvdata(dev); - struct bfin_spi_master *drv_data = spi_master_get_devdata(master); - int ret = 0; - - /* bootrom may modify spi and dma status when resume in spi boot mode */ - disable_dma(drv_data->rx_dma); - - dma_enable_irq(drv_data->rx_dma); - dma_enable_irq(drv_data->tx_dma); - bfin_write(&drv_data->regs->control, drv_data->control); - bfin_write(&drv_data->regs->ssel, drv_data->ssel); - - ret = spi_master_resume(master); - if (ret) { - free_dma(drv_data->rx_dma); - free_dma(drv_data->tx_dma); - } - - return ret; -} -#endif -static const struct dev_pm_ops bfin_spi_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(bfin_spi_suspend, bfin_spi_resume) -}; - -MODULE_ALIAS("platform:bfin-spi3"); -static struct platform_driver bfin_spi_driver = { - .driver = { - .name = "bfin-spi3", - .owner = THIS_MODULE, - .pm = &bfin_spi_pm_ops, - }, - .remove = bfin_spi_remove, -}; - -module_platform_driver_probe(bfin_spi_driver, bfin_spi_probe); - -MODULE_DESCRIPTION("Analog Devices SPI3 controller driver"); -MODULE_AUTHOR("Scott Jiang "); -MODULE_LICENSE("GPL v2"); diff --git a/include/linux/spi/adi_spi3.h b/include/linux/spi/adi_spi3.h new file mode 100644 index 000000000000..c84123aa1d06 --- /dev/null +++ b/include/linux/spi/adi_spi3.h @@ -0,0 +1,254 @@ +/* + * Analog Devices SPI3 controller driver + * + * Copyright (c) 2014 Analog Devices Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ADI_SPI3_H_ +#define _ADI_SPI3_H_ + +#include + +/* SPI_CONTROL */ +#define SPI_CTL_EN 0x00000001 /* Enable */ +#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */ +#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */ +#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */ +#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */ +#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */ +#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */ +#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */ +#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */ +#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */ +#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */ +#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */ +#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */ +#define SPI_CTL_LSBF 0x00001000 /* LSB First */ +#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */ +#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */ +#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */ +#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */ +#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */ +#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */ +#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */ +#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */ +#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */ +#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */ +#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */ +#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */ +#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */ +/* SPI_RX_CONTROL */ +#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */ +#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */ +#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */ +#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */ +#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */ +#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */ +#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */ +#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */ +#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */ +#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */ +#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */ +#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */ +#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */ +#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */ +#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */ +#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */ +#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */ +#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */ +#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */ +#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */ +#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */ +#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */ +/* SPI_TX_CONTROL */ +#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */ +#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */ +#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */ +#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */ +#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */ +#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */ +#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */ +#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */ +#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */ +#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */ +#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */ +#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */ +#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */ +#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */ +#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */ +#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */ +#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */ +#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */ +#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */ +#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */ +#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */ +#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */ +/* SPI_CLOCK */ +#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */ +/* SPI_DELAY */ +#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */ +#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */ +#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */ +/* SPI_SSEL */ +#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */ +#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */ +#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */ +#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */ +#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */ +#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */ +#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */ +#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */ +#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */ +#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */ +#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */ +#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */ +#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */ +#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */ +/* SPI_RWC */ +#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */ +/* SPI_RWCR */ +#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */ +/* SPI_TWC */ +#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */ +/* SPI_TWCR */ +#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */ +/* SPI_IMASK */ +#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ +#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ +#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ +#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ +#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */ +#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */ +#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */ +#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ +/* SPI_IMASKCL */ +#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ +#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ +#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ +#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ +#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */ +#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */ +#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */ +#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ +/* SPI_IMASKST */ +#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */ +#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */ +#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */ +#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */ +#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */ +#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */ +#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */ +#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */ +#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */ +/* SPI_STATUS */ +#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */ +#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */ +#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */ +#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */ +#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */ +#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */ +#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */ +#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */ +#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */ +#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */ +#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */ +#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */ +#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */ +#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */ +#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */ +#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */ +#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */ +#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */ +#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */ +#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */ +#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */ +#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */ +#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */ +#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */ +#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */ +#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */ +/* SPI_ILAT */ +#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ +#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ +#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */ +#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */ +#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */ +#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */ +#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */ +#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */ +#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */ +#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */ +/* SPI_ILATCL */ +#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */ +#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */ +#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */ +#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */ +#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */ +#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */ +#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */ +#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */ +#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */ +#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */ + +/* + * adi spi3 registers layout + */ +struct adi_spi_regs { + u32 revid; + u32 control; + u32 rx_control; + u32 tx_control; + u32 clock; + u32 delay; + u32 ssel; + u32 rwc; + u32 rwcr; + u32 twc; + u32 twcr; + u32 reserved0; + u32 emask; + u32 emaskcl; + u32 emaskst; + u32 reserved1; + u32 status; + u32 elat; + u32 elatcl; + u32 reserved2; + u32 rfifo; + u32 reserved3; + u32 tfifo; +}; + +#define MAX_CTRL_CS 8 /* cs in spi controller */ + +/* device.platform_data for SSP controller devices */ +struct adi_spi3_master { + u16 num_chipselect; + u16 pin_req[7]; +}; + +/* spi_board_info.controller_data for SPI slave devices, + * copied to spi_device.platform_data ... mostly for dma tuning + */ +struct adi_spi3_chip { + u32 control; + u16 cs_chg_udelay; /* Some devices require 16-bit delays */ + u32 tx_dummy_val; /* tx value for rx only transfer */ + bool enable_dma; +}; + +#endif /* _ADI_SPI3_H_ */ -- cgit v1.2.3 From c34cc2487d5e6c225609696db3f49d40259787e2 Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Sat, 5 Apr 2014 11:29:09 +0800 Subject: spi: spi-adi-v3: convert to use common clk framework Use common clk api to get spi clock. Signed-off-by: Scott Jiang Signed-off-by: Mark Brown --- arch/blackfin/mach-bf609/clock.c | 7 +++++++ drivers/spi/spi-adi-v3.c | 13 +++++++------ 2 files changed, 14 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c index 56200f37cfc8..244fa4ab4c56 100644 --- a/arch/blackfin/mach-bf609/clock.c +++ b/arch/blackfin/mach-bf609/clock.c @@ -363,6 +363,12 @@ static struct clk ethclk = { .ops = &dummy_clk_ops, }; +static struct clk spiclk = { + .name = "spi", + .parent = &sclk1, + .ops = &dummy_clk_ops, +}; + static struct clk_lookup bf609_clks[] = { CLK(sys_clkin, NULL, "SYS_CLKIN"), CLK(pll_clk, NULL, "PLLCLK"), @@ -375,6 +381,7 @@ static struct clk_lookup bf609_clks[] = { CLK(dclk, NULL, "DCLK"), CLK(oclk, NULL, "OCLK"), CLK(ethclk, NULL, "stmmaceth"), + CLK(spiclk, NULL, "spi"), }; int __init clk_init(void) diff --git a/drivers/spi/spi-adi-v3.c b/drivers/spi/spi-adi-v3.c index 0c2914cfcdb5..dcb2287c7f8a 100644 --- a/drivers/spi/spi-adi-v3.c +++ b/drivers/spi/spi-adi-v3.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -800,7 +801,7 @@ static int adi_spi_probe(struct platform_device *pdev) struct adi_spi_master *drv_data; struct resource *mem, *res; unsigned int tx_dma, rx_dma; - unsigned long sclk; + struct clk *sclk; int ret; if (!info) { @@ -808,10 +809,10 @@ static int adi_spi_probe(struct platform_device *pdev) return -ENODEV; } - sclk = get_sclk1(); - if (!sclk) { - dev_err(dev, "can not get sclk1\n"); - return -ENXIO; + sclk = devm_clk_get(dev, "spi"); + if (IS_ERR(sclk)) { + dev_err(dev, "can not get spi clock\n"); + return PTR_ERR(sclk); } res = platform_get_resource(pdev, IORESOURCE_DMA, 0); @@ -852,7 +853,7 @@ static int adi_spi_probe(struct platform_device *pdev) drv_data->tx_dma = tx_dma; drv_data->rx_dma = rx_dma; drv_data->pin_req = info->pin_req; - drv_data->sclk = sclk; + drv_data->sclk = clk_get_rate(sclk); mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); drv_data->regs = devm_ioremap_resource(dev, mem); -- cgit v1.2.3 From 61fbb1d278cf09f29d67629b139b3ca08acbf177 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 19 Feb 2014 09:25:49 +0900 Subject: clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450 The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by: Heiko Stuebner Acked-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/Kconfig | 6 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-s3c2443.c | 462 ++++++++++++++++++++++++++++++++++++ include/dt-bindings/clock/s3c2443.h | 92 +++++++ 4 files changed, 561 insertions(+) create mode 100644 drivers/clk/samsung/clk-s3c2443.c create mode 100644 include/dt-bindings/clock/s3c2443.h (limited to 'arch') diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 40cf50b9940c..abf9179c9d03 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -647,6 +647,12 @@ config S3C2443_COMMON Common code for the S3C2443 and similar processors, which includes the S3C2416 and S3C2450. +config S3C2443_COMMON_CLK + bool + help + Temporary symbol to build the clock driver based on the common clock + framework. + config S3C2443_DMA bool help diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 8eb4799237f0..4c892c63a8dd 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o +obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c new file mode 100644 index 000000000000..8e4f4517e95c --- /dev/null +++ b/drivers/clk/samsung/clk-s3c2443.c @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2013 Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Common Clock Framework support for S3C2443 and following SoCs. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-pll.h" + +/* S3C2416 clock controller register offsets */ +#define LOCKCON0 0x00 +#define LOCKCON1 0x04 +#define MPLLCON 0x10 +#define EPLLCON 0x18 +#define EPLLCON_K 0x1C +#define CLKSRC 0x20 +#define CLKDIV0 0x24 +#define CLKDIV1 0x28 +#define CLKDIV2 0x2C +#define HCLKCON 0x30 +#define PCLKCON 0x34 +#define SCLKCON 0x38 + +/* the soc types */ +enum supported_socs { + S3C2416, + S3C2443, + S3C2450, +}; + +/* list of PLLs to be registered */ +enum s3c2443_plls { + mpll, epll, +}; + +static void __iomem *reg_base; + +#ifdef CONFIG_PM_SLEEP +static struct samsung_clk_reg_dump *s3c2443_save; + +/* + * list of controller registers to be saved and restored during a + * suspend/resume cycle. + */ +static unsigned long s3c2443_clk_regs[] __initdata = { + LOCKCON0, + LOCKCON1, + MPLLCON, + EPLLCON, + EPLLCON_K, + CLKSRC, + CLKDIV0, + CLKDIV1, + CLKDIV2, + PCLKCON, + HCLKCON, + SCLKCON, +}; + +static int s3c2443_clk_suspend(void) +{ + samsung_clk_save(reg_base, s3c2443_save, + ARRAY_SIZE(s3c2443_clk_regs)); + + return 0; +} + +static void s3c2443_clk_resume(void) +{ + samsung_clk_restore(reg_base, s3c2443_save, + ARRAY_SIZE(s3c2443_clk_regs)); +} + +static struct syscore_ops s3c2443_clk_syscore_ops = { + .suspend = s3c2443_clk_suspend, + .resume = s3c2443_clk_resume, +}; + +static void s3c2443_clk_sleep_init(void) +{ + s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs, + ARRAY_SIZE(s3c2443_clk_regs)); + if (!s3c2443_save) { + pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", + __func__); + return; + } + + register_syscore_ops(&s3c2443_clk_syscore_ops); + return; +} +#else +static void s3c2443_clk_sleep_init(void) {} +#endif + +PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" }; +PNAME(esysclk_p) = { "epllref", "epll" }; +PNAME(mpllref_p) = { "xti", "mdivclk" }; +PNAME(msysclk_p) = { "mpllref", "mpll" }; +PNAME(armclk_p) = { "armdiv" , "hclk" }; +PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" }; + +struct samsung_mux_clock s3c2443_common_muxes[] __initdata = { + MUX(0, "epllref", epllref_p, CLKSRC, 7, 2), + MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1), + MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1), + MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"), + MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"), + MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2), +}; + +static struct clk_div_table hclk_d[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 3, .div = 4 }, + { /* sentinel */ }, +}; + +static struct clk_div_table mdivclk_d[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 3 }, + { .val = 2, .div = 5 }, + { .val = 3, .div = 7 }, + { .val = 4, .div = 9 }, + { .val = 5, .div = 11 }, + { .val = 6, .div = 13 }, + { .val = 7, .div = 15 }, + { /* sentinel */ }, +}; + +struct samsung_div_clock s3c2443_common_dividers[] __initdata = { + DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d), + DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2), + DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d), + DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1), + DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2), + DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8), + DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4), + DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4), + DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2), + DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2), +}; + +struct samsung_gate_clock s3c2443_common_gates[] __initdata = { + GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0), + GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0), + GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0), + GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0), + GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0), + GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0), + GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0), + GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0), + GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0), + GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0), + GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0), + GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0), + GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0), + GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0), + GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0), + GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0), + GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0), + GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0), + GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0), + GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0), + GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0), + GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0), + GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0), + GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0), +}; + +struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { + ALIAS(HCLK, NULL, "hclk"), + ALIAS(HCLK_SSMC, NULL, "nand"), + ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), + ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"), + ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"), + ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"), + ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"), + ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"), + ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"), + ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"), + ALIAS(SCLK_UART, NULL, "clk_uart_baud3"), + ALIAS(PCLK_PWM, NULL, "timers"), + ALIAS(PCLK_RTC, NULL, "rtc"), + ALIAS(PCLK_WDT, NULL, "watchdog"), + ALIAS(PCLK_ADC, NULL, "adc"), + ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"), + ALIAS(HCLK_USBD, NULL, "usb-device"), + ALIAS(HCLK_USBH, NULL, "usb-host"), + ALIAS(SCLK_USBH, NULL, "usb-bus-host"), + ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"), + ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"), + ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"), + ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), + ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"), + ALIAS(SCLK_I2S0, NULL, "i2s-if"), + ALIAS(HCLK_LCD, NULL, "lcd"), + ALIAS(SCLK_FIMD, NULL, "sclk_fimd"), +}; + +/* S3C2416 specific clocks */ + +static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { + [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref", + LOCKCON0, MPLLCON, NULL), + [epll] = PLL(pll_6553, 0, "epll", "epllref", + LOCKCON1, EPLLCON, NULL), +}; + +PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" }; +PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" }; +PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" }; + +static struct clk_div_table armdiv_s3c2416_d[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 3 }, + { .val = 3, .div = 4 }, + { .val = 5, .div = 6 }, + { .val = 7, .div = 8 }, + { /* sentinel */ }, +}; + +struct samsung_div_clock s3c2416_dividers[] __initdata = { + DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d), + DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4), + DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2), +}; + +struct samsung_mux_clock s3c2416_muxes[] __initdata = { + MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1), + MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1), + MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1), +}; + +struct samsung_gate_clock s3c2416_gates[] __initdata = { + GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0), + GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0), + GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0), + GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0), + GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0), + GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0), + GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0), +}; + +struct samsung_clock_alias s3c2416_aliases[] __initdata = { + ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), + ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), + ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"), + ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"), + ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"), + ALIAS(ARMDIV, NULL, "armdiv"), +}; + +/* S3C2443 specific clocks */ + +static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = { + [mpll] = PLL(pll_3000, 0, "mpll", "mpllref", + LOCKCON0, MPLLCON, NULL), + [epll] = PLL(pll_2126, 0, "epll", "epllref", + LOCKCON1, EPLLCON, NULL), +}; + +static struct clk_div_table armdiv_s3c2443_d[] = { + { .val = 0, .div = 1 }, + { .val = 8, .div = 2 }, + { .val = 2, .div = 3 }, + { .val = 9, .div = 4 }, + { .val = 10, .div = 6 }, + { .val = 11, .div = 8 }, + { .val = 13, .div = 12 }, + { .val = 15, .div = 16 }, + { /* sentinel */ }, +}; + +struct samsung_div_clock s3c2443_dividers[] __initdata = { + DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d), + DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4), +}; + +struct samsung_gate_clock s3c2443_gates[] __initdata = { + GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0), + GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0), + GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0), + GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0), + GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0), +}; + +struct samsung_clock_alias s3c2443_aliases[] __initdata = { + ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"), + ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"), + ALIAS(SCLK_CAM, NULL, "camif-upll"), + ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"), + ALIAS(PCLK_SDI, NULL, "sdi"), + ALIAS(HCLK_CFC, NULL, "cfc"), + ALIAS(ARMDIV, NULL, "armdiv"), +}; + +/* S3C2450 specific clocks */ + +PNAME(s3c2450_cam_p) = { "div_cam", "hclk" }; +PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" }; +PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" }; + +struct samsung_div_clock s3c2450_dividers[] __initdata = { + DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4), + DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2), + DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4), + DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4), +}; + +struct samsung_mux_clock s3c2450_muxes[] __initdata = { + MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1), + MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1), + MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2), +}; + +struct samsung_gate_clock s3c2450_gates[] __initdata = { + GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0), + GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0), + GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0), + GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0), + GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0), + GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0), + GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0), + GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0), +}; + +struct samsung_clock_alias s3c2450_aliases[] __initdata = { + ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"), + ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"), + ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"), + ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"), +}; + +/* + * fixed rate clocks generated outside the soc + * Only necessary until the devicetree-move is complete + */ +struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = { + FRATE(0, "xti", NULL, CLK_IS_ROOT, 0), + FRATE(0, "ext", NULL, CLK_IS_ROOT, 0), + FRATE(0, "ext_i2s", NULL, CLK_IS_ROOT, 0), + FRATE(0, "ext_uart", NULL, CLK_IS_ROOT, 0), +}; + +static void __init s3c2443_common_clk_register_fixed_ext(unsigned long xti_f) +{ + s3c2443_common_frate_clks[0].fixed_rate = xti_f; + samsung_clk_register_fixed_rate(s3c2443_common_frate_clks, + ARRAY_SIZE(s3c2443_common_frate_clks)); +} + +void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, + int current_soc, + void __iomem *base) +{ + reg_base = base; + + if (np) { + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + } + + samsung_clk_init(np, reg_base, NR_CLKS); + + /* Register external clocks only in non-dt cases */ + if (!np) + s3c2443_common_clk_register_fixed_ext(xti_f); + + /* Register PLLs. */ + if (current_soc == S3C2416 || current_soc == S3C2450) + samsung_clk_register_pll(s3c2416_pll_clks, + ARRAY_SIZE(s3c2416_pll_clks), reg_base); + else + samsung_clk_register_pll(s3c2443_pll_clks, + ARRAY_SIZE(s3c2443_pll_clks), reg_base); + + /* Register common internal clocks. */ + samsung_clk_register_mux(s3c2443_common_muxes, + ARRAY_SIZE(s3c2443_common_muxes)); + samsung_clk_register_div(s3c2443_common_dividers, + ARRAY_SIZE(s3c2443_common_dividers)); + samsung_clk_register_gate(s3c2443_common_gates, + ARRAY_SIZE(s3c2443_common_gates)); + samsung_clk_register_alias(s3c2443_common_aliases, + ARRAY_SIZE(s3c2443_common_aliases)); + + /* Register SoC-specific clocks. */ + switch (current_soc) { + case S3C2450: + samsung_clk_register_div(s3c2450_dividers, + ARRAY_SIZE(s3c2450_dividers)); + samsung_clk_register_mux(s3c2450_muxes, + ARRAY_SIZE(s3c2450_muxes)); + samsung_clk_register_gate(s3c2450_gates, + ARRAY_SIZE(s3c2450_gates)); + samsung_clk_register_alias(s3c2450_aliases, + ARRAY_SIZE(s3c2450_aliases)); + /* fall through, as s3c2450 extends the s3c2416 clocks */ + case S3C2416: + samsung_clk_register_div(s3c2416_dividers, + ARRAY_SIZE(s3c2416_dividers)); + samsung_clk_register_mux(s3c2416_muxes, + ARRAY_SIZE(s3c2416_muxes)); + samsung_clk_register_gate(s3c2416_gates, + ARRAY_SIZE(s3c2416_gates)); + samsung_clk_register_alias(s3c2416_aliases, + ARRAY_SIZE(s3c2416_aliases)); + break; + case S3C2443: + samsung_clk_register_div(s3c2443_dividers, + ARRAY_SIZE(s3c2443_dividers)); + samsung_clk_register_gate(s3c2443_gates, + ARRAY_SIZE(s3c2443_gates)); + samsung_clk_register_alias(s3c2443_aliases, + ARRAY_SIZE(s3c2443_aliases)); + break; + } + + s3c2443_clk_sleep_init(); +} + +static void __init s3c2416_clk_init(struct device_node *np) +{ + s3c2443_common_clk_init(np, 0, S3C2416, 0); +} +CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init); + +static void __init s3c2443_clk_init(struct device_node *np) +{ + s3c2443_common_clk_init(np, 0, S3C2443, 0); +} +CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init); + +static void __init s3c2450_clk_init(struct device_node *np) +{ + s3c2443_common_clk_init(np, 0, S3C2450, 0); +} +CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init); diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h new file mode 100644 index 000000000000..37e66b054d64 --- /dev/null +++ b/include/dt-bindings/clock/s3c2443.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2013 Heiko Stuebner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants clock controllers of Samsung S3C2443 and later. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H + +/* + * Let each exported clock get a unique index, which is used on DT-enabled + * platforms to lookup the clock from a clock specifier. These indices are + * therefore considered an ABI and so must not be changed. This implies + * that new clocks should be added either in free spaces between clock groups + * or at the end. + */ + +/* Core clocks. */ +#define MSYSCLK 1 +#define ESYSCLK 2 +#define ARMDIV 3 +#define ARMCLK 4 +#define HCLK 5 +#define PCLK 6 + +/* Special clocks */ +#define SCLK_HSSPI0 16 +#define SCLK_FIMD 17 +#define SCLK_I2S0 18 +#define SCLK_I2S1 19 +#define SCLK_HSMMC1 20 +#define SCLK_HSMMC_EXT 21 +#define SCLK_CAM 22 +#define SCLK_UART 23 +#define SCLK_USBH 24 + +/* Muxes */ +#define MUX_HSSPI0 32 +#define MUX_HSSPI1 33 +#define MUX_HSMMC0 34 +#define MUX_HSMMC1 35 + +/* hclk-gates */ +#define HCLK_DMA0 48 +#define HCLK_DMA1 49 +#define HCLK_DMA2 50 +#define HCLK_DMA3 51 +#define HCLK_DMA4 52 +#define HCLK_DMA5 53 +#define HCLK_DMA6 54 +#define HCLK_DMA7 55 +#define HCLK_CAM 56 +#define HCLK_LCD 57 +#define HCLK_USBH 58 +#define HCLK_USBD 59 +#define HCLK_IROM 60 +#define HCLK_HSMMC0 61 +#define HCLK_HSMMC1 62 +#define HCLK_CFC 63 +#define HCLK_SSMC 64 +#define HCLK_DRAM 65 +#define HCLK_2D 66 + +/* pclk-gates */ +#define PCLK_UART0 72 +#define PCLK_UART1 73 +#define PCLK_UART2 74 +#define PCLK_UART3 75 +#define PCLK_I2C0 76 +#define PCLK_SDI 77 +#define PCLK_SPI0 78 +#define PCLK_ADC 79 +#define PCLK_AC97 80 +#define PCLK_I2S0 81 +#define PCLK_PWM 82 +#define PCLK_WDT 83 +#define PCLK_RTC 84 +#define PCLK_GPIO 85 +#define PCLK_SPI1 86 +#define PCLK_CHIPID 87 +#define PCLK_I2C1 88 +#define PCLK_I2S1 89 +#define PCLK_PCM 90 + +/* Total number of clocks. */ +#define NR_CLKS (PCLK_PCM + 1) + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ -- cgit v1.2.3 From 5ab9a428cf1d118779554b6a20161d7b339310db Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 19 Feb 2014 09:25:54 +0900 Subject: ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socs As the conversion to the common-clock-framework is done in multiple steps, it is necessary to prevent conflicts between the different struct clk implementations. For this include the s3c24xx_setup_clocks function only when SAMSUNG_CLOCK is selected and make the socs we don't convert this time explicitly depend on SAMSUNG_CLOCK, which gets only selected automatically if COMMON_CLK is not enabled. Signed-off-by: Heiko Stuebner Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/Kconfig | 4 ++++ arch/arm/mach-s3c24xx/common.c | 2 ++ 2 files changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index abf9179c9d03..f10af7faec98 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -25,6 +25,7 @@ comment "S3C24XX SoCs" config CPU_S3C2410 bool "SAMSUNG S3C2410" default y + depends on SAMSUNG_CLOCK select CPU_ARM920T select CPU_LLSERIAL_S3C2410 select S3C2410_CLOCK @@ -38,6 +39,7 @@ config CPU_S3C2410 config CPU_S3C2412 bool "SAMSUNG S3C2412" + depends on SAMSUNG_CLOCK select CPU_ARM926T select CPU_LLSERIAL_S3C2440 select S3C2412_DMA if S3C24XX_DMA @@ -58,6 +60,7 @@ config CPU_S3C2416 config CPU_S3C2440 bool "SAMSUNG S3C2440" + depends on SAMSUNG_CLOCK select CPU_ARM920T select CPU_LLSERIAL_S3C2440 select S3C2410_CLOCK @@ -68,6 +71,7 @@ config CPU_S3C2440 config CPU_S3C2442 bool "SAMSUNG S3C2442" + depends on SAMSUNG_CLOCK select CPU_ARM920T select CPU_LLSERIAL_S3C2440 select S3C2410_CLOCK diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 1bc8e73c94f9..0fc6641ac57d 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -318,6 +318,7 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { /* initialise all the clocks */ +#ifdef CONFIG_SAMSUNG_CLOCK void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, unsigned long hclk, unsigned long pclk) @@ -330,6 +331,7 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, clk_p.rate = pclk; clk_f.rate = fclk; } +#endif #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) -- cgit v1.2.3 From 8cb28748154db139180ea4e24252530aecc3745b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 19 Feb 2014 09:26:17 +0900 Subject: ARM: dts: add clock data for s3c2416 This adds the clock controller itself, the xti clock on the smdk2416 as well as the clock references in the individual device nodes. Signed-off-by: Heiko Stuebner Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/s3c2416-smdk2416.dts | 13 +++++++++++ arch/arm/boot/dts/s3c2416.dtsi | 42 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 59594cf15998..ea92fd69529a 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -19,6 +19,19 @@ reg = <0x30000000 0x4000000>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + xti: xti { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "xti"; + #clock-cells = <0>; + }; + }; + serial@50000000 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index e6555bdd81b8..955e4a4f8c31 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -8,6 +8,7 @@ * published by the Free Software Foundation. */ +#include #include "s3c24xx.dtsi" #include "s3c2416-pinctrl.dtsi" @@ -28,26 +29,53 @@ compatible = "samsung,s3c2416-irq"; }; + clocks: clock-controller@0x4c000000 { + compatible = "samsung,s3c2416-clock"; + reg = <0x4c000000 0x40>; + #clock-cells = <1>; + }; + pinctrl@56000000 { compatible = "samsung,s3c2416-pinctrl"; }; + timer@51000000 { + clocks = <&clocks PCLK_PWM>; + clock-names = "timers"; + }; + serial@50000000 { compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; }; serial@50004000 { compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, + <&clocks SCLK_UART>; }; serial@50008000 { compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, + <&clocks SCLK_UART>; }; serial@5000C000 { compatible = "samsung,s3c2440-uart"; reg = <0x5000C000 0x4000>; interrupts = <1 18 24 4>, <1 18 25 4>; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, + <&clocks SCLK_UART>; status = "disabled"; }; @@ -55,6 +83,10 @@ compatible = "samsung,s3c6410-sdhci"; reg = <0x4AC00000 0x100>; interrupts = <0 0 21 3>; + clock-names = "hsmmc", "mmc_busclk.0", + "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, + <&clocks MUX_HSMMC0>; status = "disabled"; }; @@ -62,18 +94,28 @@ compatible = "samsung,s3c6410-sdhci"; reg = <0x4A800000 0x100>; interrupts = <0 0 20 3>; + clock-names = "hsmmc", "mmc_busclk.0", + "mmc_busclk.2"; + clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, + <&clocks MUX_HSMMC1>; status = "disabled"; }; watchdog@53000000 { interrupts = <1 9 27 3>; + clocks = <&clocks PCLK_WDT>; + clock-names = "watchdog"; }; rtc@57000000 { compatible = "samsung,s3c2416-rtc"; + clocks = <&clocks PCLK_RTC>; + clock-names = "rtc"; }; i2c@54000000 { compatible = "samsung,s3c2440-i2c"; + clocks = <&clocks PCLK_I2C0>; + clock-names = "i2c"; }; }; -- cgit v1.2.3 From dfc0f5099a83f8633fc4480e2f0e8e5f6ac1331d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 19 Feb 2014 09:26:21 +0900 Subject: ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock framework This converts the mentioned platforms to use the newly introduced driver for the common clock framework for them. With this the whole legacy clock structure can go away too. Signed-off-by: Heiko Stuebner Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/Kconfig | 14 +- arch/arm/mach-s3c24xx/Makefile | 5 +- arch/arm/mach-s3c24xx/clock-s3c2416.c | 171 -------- arch/arm/mach-s3c24xx/clock-s3c2443.c | 212 ---------- arch/arm/mach-s3c24xx/common-s3c2443.c | 675 -------------------------------- arch/arm/mach-s3c24xx/common.c | 16 +- arch/arm/mach-s3c24xx/common.h | 6 + arch/arm/mach-s3c24xx/mach-s3c2416-dt.c | 38 +- arch/arm/mach-s3c24xx/mach-smdk2416.c | 9 +- arch/arm/mach-s3c24xx/mach-smdk2443.c | 9 +- 10 files changed, 41 insertions(+), 1114 deletions(-) delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2416.c delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2443.c delete mode 100644 arch/arm/mach-s3c24xx/common-s3c2443.c (limited to 'arch') diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index f10af7faec98..52f1c40ccf07 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -49,12 +49,12 @@ config CPU_S3C2412 config CPU_S3C2416 bool "SAMSUNG S3C2416/S3C2450" + select COMMON_CLK select CPU_ARM926T select CPU_LLSERIAL_S3C2440 select S3C2416_PM if PM - select S3C2443_COMMON + select S3C2443_COMMON_CLK select S3C2443_DMA if S3C24XX_DMA - select SAMSUNG_CLKSRC help Support for the S3C2416 SoC from the S3C24XX line @@ -87,11 +87,11 @@ config CPU_S3C244X config CPU_S3C2443 bool "SAMSUNG S3C2443" + select COMMON_CLK select CPU_ARM920T select CPU_LLSERIAL_S3C2440 - select S3C2443_COMMON + select S3C2443_COMMON_CLK select S3C2443_DMA if S3C24XX_DMA - select SAMSUNG_CLKSRC help Support for the S3C2443 SoC from the S3C24XX line @@ -645,12 +645,6 @@ endif # CPU_S3C2442 if CPU_S3C2443 || CPU_S3C2416 -config S3C2443_COMMON - bool - help - Common code for the S3C2443 and similar processors, which includes - the S3C2416 and S3C2450. - config S3C2443_COMMON_CLK bool help diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index 7f54e5b954ca..ba0e5475a807 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o -obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o +obj-$(CONFIG_CPU_S3C2416) += s3c2416.o obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o obj-$(CONFIG_CPU_S3C2440) += s3c2440.o clock-s3c2440.o @@ -36,7 +36,7 @@ obj-$(CONFIG_S3C2440_DMA) += dma-s3c2440.o obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o -obj-$(CONFIG_CPU_S3C2443) += s3c2443.o clock-s3c2443.o +obj-$(CONFIG_CPU_S3C2443) += s3c2443.o # PM @@ -53,7 +53,6 @@ obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o -obj-$(CONFIG_S3C2443_COMMON) += common-s3c2443.o obj-$(CONFIG_S3C2443_DMA) += dma-s3c2443.o # diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c deleted file mode 100644 index d421a72920a5..000000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ /dev/null @@ -1,171 +0,0 @@ -/* linux/arch/arm/mach-s3c2416/clock.c - * - * Copyright (c) 2010 Simtec Electronics - * Copyright (c) 2010 Ben Dooks - * - * S3C2416 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#include -#include - -/* armdiv - * - * this clock is sourced from msysclk and can have a number of - * divider values applied to it to then be fed into armclk. - * The real clock definition is done in s3c2443-clock.c, - * only the armdiv divisor table must be defined here. -*/ - -static unsigned int armdiv[8] = { - [0] = 1, - [1] = 2, - [2] = 3, - [3] = 4, - [5] = 6, - [7] = 8, -}; - -static struct clksrc_clk hsspi_eplldiv = { - .clk = { - .name = "hsspi-eplldiv", - .parent = &clk_esysclk.clk, - .ctrlbit = (1 << 14), - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 }, -}; - -static struct clk *hsspi_sources[] = { - [0] = &hsspi_eplldiv.clk, - [1] = NULL, /* to fix */ -}; - -static struct clksrc_clk hsspi_mux = { - .clk = { - .name = "hsspi-if", - }, - .sources = &(struct clksrc_sources) { - .sources = hsspi_sources, - .nr_sources = ARRAY_SIZE(hsspi_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 }, -}; - -static struct clksrc_clk hsmmc_div[] = { - [0] = { - .clk = { - .name = "hsmmc-div", - .devname = "s3c-sdhci.0", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 }, - }, - [1] = { - .clk = { - .name = "hsmmc-div", - .devname = "s3c-sdhci.1", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, - }, -}; - -static struct clksrc_clk hsmmc_mux0 = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.0", - .ctrlbit = (1 << 6), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk * []) { - [0] = &hsmmc_div[0].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 }, -}; - -static struct clksrc_clk hsmmc_mux1 = { - .clk = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .ctrlbit = (1 << 12), - .enable = s3c2443_clkcon_enable_s, - }, - .sources = &(struct clksrc_sources) { - .nr_sources = 2, - .sources = (struct clk * []) { - [0] = &hsmmc_div[1].clk, - [1] = NULL, /* to fix */ - }, - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 }, -}; - -static struct clk hsmmc0_clk = { - .name = "hsmmc", - .devname = "s3c-sdhci.0", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2416_HCLKCON_HSMMC0, -}; - -static struct clksrc_clk *clksrcs[] __initdata = { - &hsspi_eplldiv, - &hsspi_mux, - &hsmmc_div[0], - &hsmmc_div[1], - &hsmmc_mux0, - &hsmmc_mux1, -}; - -static struct clk_lookup s3c2416_clk_lookup[] = { - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), - CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), - /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */ - CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk), -}; - -void __init s3c2416_init_clocks(int xtal) -{ - u32 epllcon = __raw_readl(S3C2443_EPLLCON); - u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4); - int ptr; - - /* s3c2416 EPLL compatible with s3c64xx */ - clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1); - - clk_epll.parent = &clk_epllref.clk; - - s3c2443_common_init_clocks(xtal, s3c2416_get_pll, - armdiv, ARRAY_SIZE(armdiv), - S3C2416_CLKDIV0_ARMDIV_MASK); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_register_clksrc(clksrcs[ptr], 1); - - s3c24xx_register_clock(&hsmmc0_clk); - clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); - -} diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c deleted file mode 100644 index 76cd31f7804e..000000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ /dev/null @@ -1,212 +0,0 @@ -/* linux/arch/arm/mach-s3c2443/clock.c - * - * Copyright (c) 2007, 2010 Simtec Electronics - * Ben Dooks - * - * S3C2443 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include - -#include - -#include -#include -#include - -/* We currently have to assume that the system is running - * from the XTPll input, and that all ***REFCLKs are being - * fed from it, as we cannot read the state of OM[4] from - * software. - * - * It would be possible for each board initialisation to - * set the correct muxing at initialisation -*/ - -/* clock selections */ - -/* armdiv - * - * this clock is sourced from msysclk and can have a number of - * divider values applied to it to then be fed into armclk. - * The real clock definition is done in s3c2443-clock.c, - * only the armdiv divisor table must be defined here. -*/ - -static unsigned int armdiv[16] = { - [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, - [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, - [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, - [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, - [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, - [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, - [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, - [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, -}; - -/* hsspi - * - * high-speed spi clock, sourced from esysclk -*/ - -static struct clksrc_clk clk_hsspi = { - .clk = { - .name = "hsspi-if", - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_HSSPICLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, -}; - - -/* clk_hsmcc_div - * - * this clock is sourced from epll, and is fed through a divider, - * to a mux controlled by sclkcon where either it or a extclk can - * be fed to the hsmmc block -*/ - -static struct clksrc_clk clk_hsmmc_div = { - .clk = { - .name = "hsmmc-div", - .devname = "s3c-sdhci.1", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, -}; - -static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2443_SCLKCON); - - clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT | - S3C2443_SCLKCON_HSMMCCLK_EPLL); - - if (parent == &clk_epll) - clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL; - else if (parent == &clk_ext) - clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT; - else - return -EINVAL; - - if (clk->usage > 0) { - __raw_writel(clksrc, S3C2443_SCLKCON); - } - - clk->parent = parent; - return 0; -} - -static int s3c2443_enable_hsmmc(struct clk *clk, int enable) -{ - return s3c2443_setparent_hsmmc(clk, clk->parent); -} - -static struct clk clk_hsmmc = { - .name = "hsmmc-if", - .devname = "s3c-sdhci.1", - .parent = &clk_hsmmc_div.clk, - .enable = s3c2443_enable_hsmmc, - .ops = &(struct clk_ops) { - .set_parent = s3c2443_setparent_hsmmc, - }, -}; - -/* standard clock definitions */ - -static struct clk init_clocks_off[] = { - { - .name = "sdi", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_SDI, - }, { - .name = "spi", - .devname = "s3c2410-spi.0", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_SPI1, - } -}; - -/* clocks to add straight away */ - -static struct clksrc_clk *clksrcs[] __initdata = { - &clk_hsspi, - &clk_hsmmc_div, -}; - -static struct clk *clks[] __initdata = { - &clk_hsmmc, -}; - -static struct clk_lookup s3c2443_clk_lookup[] = { - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), - CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), -}; - -void __init s3c2443_init_clocks(int xtal) -{ - unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); - int ptr; - - clk_epll.rate = s3c2443_get_epll(epllcon, xtal); - clk_epll.parent = &clk_epllref.clk; - - s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, - armdiv, ARRAY_SIZE(armdiv), - S3C2443_CLKDIV0_ARMDIV_MASK); - - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_register_clksrc(clksrcs[ptr], 1); - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsystems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); -} diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c deleted file mode 100644 index 65d3eef73090..000000000000 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ /dev/null @@ -1,675 +0,0 @@ -/* - * Common code for SoCs starting with the S3C2443 - * - * Copyright (c) 2007, 2010 Simtec Electronics - * Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include - -#include -#include -#include - -#include - - -static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable) -{ - u32 ctrlbit = clk->ctrlbit; - u32 con = __raw_readl(reg); - - if (enable) - con |= ctrlbit; - else - con &= ~ctrlbit; - - __raw_writel(con, reg); - return 0; -} - -int s3c2443_clkcon_enable_h(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_HCLKCON, clk, enable); -} - -int s3c2443_clkcon_enable_p(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_PCLKCON, clk, enable); -} - -int s3c2443_clkcon_enable_s(struct clk *clk, int enable) -{ - return s3c2443_gate(S3C2443_SCLKCON, clk, enable); -} - -/* mpllref is a direct descendant of clk_xtal by default, but it is not - * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as - * such directly equating the two source clocks is impossible. - */ -static struct clk clk_mpllref = { - .name = "mpllref", - .parent = &clk_xtal, -}; - -static struct clk *clk_epllref_sources[] = { - [0] = &clk_mpllref, - [1] = &clk_mpllref, - [2] = &clk_xtal, - [3] = &clk_ext, -}; - -struct clksrc_clk clk_epllref = { - .clk = { - .name = "epllref", - }, - .sources = &(struct clksrc_sources) { - .sources = clk_epllref_sources, - .nr_sources = ARRAY_SIZE(clk_epllref_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 }, -}; - -/* esysclk - * - * this is sourced from either the EPLL or the EPLLref clock -*/ - -static struct clk *clk_sysclk_sources[] = { - [0] = &clk_epllref.clk, - [1] = &clk_epll, -}; - -struct clksrc_clk clk_esysclk = { - .clk = { - .name = "esysclk", - .parent = &clk_epll, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_sysclk_sources, - .nr_sources = ARRAY_SIZE(clk_sysclk_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 }, -}; - -static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2443_CLKDIV0); - - div &= S3C2443_CLKDIV0_EXTDIV_MASK; - div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */ - - return parent_rate / (div + 1); -} - -static struct clk clk_mdivclk = { - .name = "mdivclk", - .parent = &clk_mpllref, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_getrate_mdivclk, - }, -}; - -static struct clk *clk_msysclk_sources[] = { - [0] = &clk_mpllref, - [1] = &clk_mpll, - [2] = &clk_mdivclk, - [3] = &clk_mpllref, -}; - -static struct clksrc_clk clk_msysclk = { - .clk = { - .name = "msysclk", - .parent = &clk_xtal, - }, - .sources = &(struct clksrc_sources) { - .sources = clk_msysclk_sources, - .nr_sources = ARRAY_SIZE(clk_msysclk_sources), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 }, -}; - -/* prediv - * - * this divides the msysclk down to pass to h/p/etc. - */ - -static unsigned long s3c2443_prediv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK; - clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT; - - return rate / (clkdiv0 + 1); -} - -static struct clk clk_prediv = { - .name = "prediv", - .parent = &clk_msysclk.clk, - .ops = &(struct clk_ops) { - .get_rate = s3c2443_prediv_getrate, - }, -}; - -/* hclk divider - * - * divides the prediv and provides the hclk. - */ - -static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; - - return rate / (clkdiv0 + 1); -} - -static struct clk_ops clk_h_ops = { - .get_rate = s3c2443_hclkdiv_getrate, -}; - -/* pclk divider - * - * divides the hclk and provides the pclk. - */ - -static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); - - clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0); - - return rate / (clkdiv0 + 1); -} - -static struct clk_ops clk_p_ops = { - .get_rate = s3c2443_pclkdiv_getrate, -}; - -/* armdiv - * - * this clock is sourced from msysclk and can have a number of - * divider values applied to it to then be fed into armclk. -*/ - -static unsigned int *armdiv; -static int nr_armdiv; -static int armdivmask; - -static unsigned long s3c2443_armclk_roundrate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - unsigned long calc; - unsigned best = 256; /* bigger than any value */ - unsigned div; - int ptr; - - if (!nr_armdiv) - return -EINVAL; - - for (ptr = 0; ptr < nr_armdiv; ptr++) { - div = armdiv[ptr]; - if (div) { - /* cpufreq provides 266mhz as 266666000 not 266666666 */ - calc = (parent / div / 1000) * 1000; - if (calc <= rate && div < best) - best = div; - } - } - - return parent / best; -} - -static unsigned long s3c2443_armclk_getrate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkcon0; - int val; - - if (!nr_armdiv || !armdivmask) - return -EINVAL; - - clkcon0 = __raw_readl(S3C2443_CLKDIV0); - clkcon0 &= armdivmask; - val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT; - - return rate / armdiv[val]; -} - -static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - unsigned long calc; - unsigned div; - unsigned best = 256; /* bigger than any value */ - int ptr; - int val = -1; - - if (!nr_armdiv || !armdivmask) - return -EINVAL; - - for (ptr = 0; ptr < nr_armdiv; ptr++) { - div = armdiv[ptr]; - if (div) { - /* cpufreq provides 266mhz as 266666000 not 266666666 */ - calc = (parent / div / 1000) * 1000; - if (calc <= rate && div < best) { - best = div; - val = ptr; - } - } - } - - if (val >= 0) { - unsigned long clkcon0; - - clkcon0 = __raw_readl(S3C2443_CLKDIV0); - clkcon0 &= ~armdivmask; - clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; - __raw_writel(clkcon0, S3C2443_CLKDIV0); - } - - return (val == -1) ? -EINVAL : 0; -} - -static struct clk clk_armdiv = { - .name = "armdiv", - .parent = &clk_msysclk.clk, - .ops = &(struct clk_ops) { - .round_rate = s3c2443_armclk_roundrate, - .get_rate = s3c2443_armclk_getrate, - .set_rate = s3c2443_armclk_setrate, - }, -}; - -/* armclk - * - * this is the clock fed into the ARM core itself, from armdiv or from hclk. - */ - -static struct clk *clk_arm_sources[] = { - [0] = &clk_armdiv, - [1] = &clk_h, -}; - -static struct clksrc_clk clk_arm = { - .clk = { - .name = "armclk", - }, - .sources = &(struct clksrc_sources) { - .sources = clk_arm_sources, - .nr_sources = ARRAY_SIZE(clk_arm_sources), - }, - .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, -}; - -/* usbhost - * - * usb host bus-clock, usually 48MHz to provide USB bus clock timing -*/ - -static struct clksrc_clk clk_usb_bus_host = { - .clk = { - .name = "usb-bus-host-parent", - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_USBHOST, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, -}; - -/* common clksrc clocks */ - -static struct clksrc_clk clksrc_clks[] = { - { - /* camera interface bus-clock, divided down from esysclk */ - .clk = { - .name = "camif-upll", /* same as 2440 name */ - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_CAMCLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 }, - }, { - .clk = { - .name = "display-if", - .parent = &clk_esysclk.clk, - .ctrlbit = S3C2443_SCLKCON_DISPCLK, - .enable = s3c2443_clkcon_enable_s, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 }, - }, -}; - -static struct clksrc_clk clk_esys_uart = { - /* ART baud-rate clock sourced from esysclk via a divisor */ - .clk = { - .name = "uartclk", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 }, -}; - -static struct clk clk_i2s_ext = { - .name = "i2s-ext", -}; - -/* i2s_eplldiv - * - * This clock is the output from the I2S divisor of ESYSCLK, and is separate - * from the mux that comes after it (cannot merge into one single clock) -*/ - -static struct clksrc_clk clk_i2s_eplldiv = { - .clk = { - .name = "i2s-eplldiv", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, -}; - -/* i2s-ref - * - * i2s bus reference clock, selectable from external, esysclk or epllref - * - * Note, this used to be two clocks, but was compressed into one. -*/ - -static struct clk *clk_i2s_srclist[] = { - [0] = &clk_i2s_eplldiv.clk, - [1] = &clk_i2s_ext, - [2] = &clk_epllref.clk, - [3] = &clk_epllref.clk, -}; - -static struct clksrc_clk clk_i2s = { - .clk = { - .name = "i2s-if", - .ctrlbit = S3C2443_SCLKCON_I2SCLK, - .enable = s3c2443_clkcon_enable_s, - - }, - .sources = &(struct clksrc_sources) { - .sources = clk_i2s_srclist, - .nr_sources = ARRAY_SIZE(clk_i2s_srclist), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, -}; - -static struct clk init_clocks_off[] = { - { - .name = "iis", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_IIS, - }, { - .name = "adc", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_ADC, - }, { - .name = "i2c", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_IIC, - } -}; - -static struct clk init_clocks[] = { - { - .name = "dma.0", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA0, - }, { - .name = "dma.1", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA1, - }, { - .name = "dma.2", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA2, - }, { - .name = "dma.3", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA3, - }, { - .name = "dma.4", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA4, - }, { - .name = "dma.5", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_DMA5, - }, { - .name = "gpio", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_GPIO, - }, { - .name = "usb-host", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_USBH, - }, { - .name = "usb-device", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_USBD, - }, { - .name = "lcd", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_LCDC, - - }, { - .name = "timers", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_PWMT, - }, { - .name = "cfc", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_CFC, - }, { - .name = "ssmc", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_SSMC, - }, { - .name = "uart", - .devname = "s3c2440-uart.0", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART0, - }, { - .name = "uart", - .devname = "s3c2440-uart.1", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART1, - }, { - .name = "uart", - .devname = "s3c2440-uart.2", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART2, - }, { - .name = "uart", - .devname = "s3c2440-uart.3", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_UART3, - }, { - .name = "rtc", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_RTC, - }, { - .name = "watchdog", - .parent = &clk_p, - .ctrlbit = S3C2443_PCLKCON_WDT, - }, { - .name = "ac97", - .parent = &clk_p, - .ctrlbit = S3C2443_PCLKCON_AC97, - }, { - .name = "nand", - .parent = &clk_h, - }, { - .name = "usb-bus-host", - .parent = &clk_usb_bus_host.clk, - } -}; - -static struct clk hsmmc1_clk = { - .name = "hsmmc", - .devname = "s3c-sdhci.1", - .parent = &clk_h, - .enable = s3c2443_clkcon_enable_h, - .ctrlbit = S3C2443_HCLKCON_HSMMC, -}; - -static struct clk hsspi_clk = { - .name = "spi", - .devname = "s3c2443-spi.0", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_HSSPI, -}; - -/* EPLLCON compatible enough to get on/off information */ - -void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) -{ - unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); - unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); - struct clk *xtal_clk; - unsigned long xtal; - unsigned long pll; - int ptr; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - pll = get_mpll(mpllcon, xtal); - clk_msysclk.clk.rate = pll; - clk_mpll.rate = pll; - - printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", - (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on", - print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)), - print_mhz(clk_get_rate(&clk_h)), - print_mhz(clk_get_rate(&clk_p))); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) - s3c_set_clksrc(&clksrc_clks[ptr], true); - - /* ensure usb bus clock is within correct rate of 48MHz */ - - if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) { - printk(KERN_INFO "Warning: USB host bus not at 48MHz\n"); - clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000); - } - - printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", - (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on", - print_mhz(clk_get_rate(&clk_epll)), - print_mhz(clk_get_rate(&clk_usb_bus))); -} - -static struct clk *clks[] __initdata = { - &clk_prediv, - &clk_mpllref, - &clk_mdivclk, - &clk_ext, - &clk_epll, - &clk_usb_bus, - &clk_armdiv, - &hsmmc1_clk, - &hsspi_clk, -}; - -static struct clksrc_clk *clksrcs[] __initdata = { - &clk_i2s_eplldiv, - &clk_i2s, - &clk_usb_bus_host, - &clk_epllref, - &clk_esysclk, - &clk_msysclk, - &clk_arm, -}; - -static struct clk_lookup s3c2443_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), - CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), - CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), - CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk), -}; - -void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, - unsigned int *divs, int nr_divs, - int divmask) -{ - int ptr; - - armdiv = divs; - nr_armdiv = nr_divs; - armdivmask = divmask; - - /* s3c2443 parents h clock from prediv */ - clk_h.parent = &clk_prediv; - clk_h.ops = &clk_h_ops; - - /* and p clock from h clock */ - clk_p.parent = &clk_h; - clk_p.ops = &clk_p_ops; - - clk_usb_bus.parent = &clk_usb_bus_host.clk; - clk_epll.parent = &clk_epllref.clk; - - s3c24xx_register_baseclocks(xtal); - s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) - s3c_register_clksrc(clksrcs[ptr], 1); - - s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); - s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); - - /* See s3c2443/etc notes on disabling clocks at init time */ - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); - - s3c2443_common_setup_clocks(get_mpll); -} diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 0fc6641ac57d..412ca006fcce 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -145,7 +145,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32450003, .idmask = 0xffffffff, .map_io = s3c2416_map_io, - .init_clocks = s3c2416_init_clocks, .init_uarts = s3c2416_init_uarts, .init = s3c2416_init, .name = name_s3c2416, @@ -154,7 +153,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32443001, .idmask = 0xffffffff, .map_io = s3c2443_map_io, - .init_clocks = s3c2443_init_clocks, .init_uarts = s3c2443_init_uarts, .init = s3c2443_init, .name = name_s3c2443, @@ -536,3 +534,17 @@ struct platform_device s3c2443_device_dma = { }, }; #endif + +#ifdef CONFIG_CPU_S3C2416 +void __init s3c2416_init_clocks(int xtal) +{ + s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); +} +#endif + +#ifdef CONFIG_CPU_S3C2443 +void __init s3c2443_init_clocks(int xtal) +{ + s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR); +} +#endif diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index e46c10417216..d7323f16427f 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h @@ -114,4 +114,10 @@ extern struct platform_device s3c2412_device_dma; extern struct platform_device s3c2440_device_dma; extern struct platform_device s3c2443_device_dma; +#ifdef CONFIG_S3C2443_COMMON_CLK +void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, + int current_soc, + void __iomem *reg_base); +#endif + #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c index 70f0900d4bca..e4dcb9aa2ca2 100644 --- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c +++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -29,48 +28,14 @@ #include "common.h" -/* - * The following lookup table is used to override device names when devices - * are registered from device tree. This is temporarily added to enable - * device tree support addition for the S3C2416 architecture. - * - * For drivers that require platform data to be provided from the machine - * file, a platform data pointer can also be supplied along with the - * devices names. Usually, the platform data elements that cannot be parsed - * from the device tree by the drivers (example: function pointers) are - * supplied. But it should be noted that this is a temporary mechanism and - * at some point, the drivers should be capable of parsing all the platform - * data from the device tree. - */ -static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = { - OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART, - "s3c2440-uart.0", NULL), - OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000, - "s3c2440-uart.1", NULL), - OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000, - "s3c2440-uart.2", NULL), - OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000, - "s3c2440-uart.3", NULL), - OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0, - "s3c-sdhci.0", NULL), - OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1, - "s3c-sdhci.1", NULL), - OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC, - "s3c2440-i2c.0", NULL), - {}, -}; - static void __init s3c2416_dt_map_io(void) { s3c24xx_init_io(NULL, 0); - s3c24xx_init_clocks(12000000); } static void __init s3c2416_dt_machine_init(void) { - of_platform_populate(NULL, of_default_bus_match_table, - s3c2416_auxdata_lookup, NULL); - + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); s3c_pm_init(); } @@ -86,6 +51,5 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)") .map_io = s3c2416_dt_map_io, .init_irq = irqchip_init, .init_machine = s3c2416_dt_machine_init, - .init_time = clocksource_of_init, .restart = s3c2416_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c index b3b54d8e1410..fa6f30d23601 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c @@ -219,10 +219,15 @@ static struct platform_device *smdk2416_devices[] __initdata = { &s3c2443_device_dma, }; +static void __init smdk2416_init_time(void) +{ + s3c2416_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2416_map_io(void) { s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } @@ -257,6 +262,6 @@ MACHINE_START(SMDK2416, "SMDK2416") .init_irq = s3c2416_init_irq, .map_io = smdk2416_map_io, .init_machine = smdk2416_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2416_init_time, .restart = s3c2416_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c index 06c4d77de3a5..ef5d5ea33182 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c @@ -121,11 +121,16 @@ static struct platform_device *smdk2443_devices[] __initdata = { static void __init smdk2443_map_io(void) { s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init smdk2443_init_time(void) +{ + s3c2443_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2443_machine_init(void) { s3c_i2c0_set_platdata(NULL); @@ -145,6 +150,6 @@ MACHINE_START(SMDK2443, "SMDK2443") .init_irq = s3c2443_init_irq, .map_io = smdk2443_map_io, .init_machine = smdk2443_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2443_init_time, .restart = s3c2443_restart, MACHINE_END -- cgit v1.2.3 From 42637c59f36198a58069f94676007c62477321b7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 25 Feb 2014 09:50:43 +0900 Subject: ARM: S3C24XX: only store clock registers when old clock code is active The Samsung ccf driver already handles the save and restore of the clock registers on suspend and resume. The architecture code should not duplicate this when the ccf is active. Signed-off-by: Heiko Stuebner Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/pm.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c index 68ea5b7e5dc7..16281bdc750a 100644 --- a/arch/arm/mach-s3c24xx/pm.c +++ b/arch/arm/mach-s3c24xx/pm.c @@ -51,9 +51,6 @@ #define PFX "s3c24xx-pm: " static struct sleep_save core_save[] = { - SAVE_ITEM(S3C2410_LOCKTIME), - SAVE_ITEM(S3C2410_CLKCON), - /* we restore the timings here, with the proviso that the board * brings the system up in an slower, or equal frequency setting * to the original system. @@ -70,6 +67,9 @@ static struct sleep_save core_save[] = { SAVE_ITEM(S3C2410_BANKCON4), SAVE_ITEM(S3C2410_BANKCON5), +#ifdef CONFIG_SAMSUNG_CLOCK + SAVE_ITEM(S3C2410_LOCKTIME), + SAVE_ITEM(S3C2410_CLKCON), #ifndef CONFIG_CPU_FREQ SAVE_ITEM(S3C2410_CLKDIVN), SAVE_ITEM(S3C2410_MPLLCON), @@ -77,11 +77,14 @@ static struct sleep_save core_save[] = { #endif SAVE_ITEM(S3C2410_UPLLCON), SAVE_ITEM(S3C2410_CLKSLOW), +#endif /* CONFIG_SAMSUNG_CLOCK */ }; +#ifdef CONFIG_SAMSUNG_CLOCK static struct sleep_save misc_save[] = { SAVE_ITEM(S3C2410_DCLKCON), }; +#endif /* s3c_pm_check_resume_pin * @@ -140,12 +143,16 @@ void s3c_pm_configure_extint(void) void s3c_pm_restore_core(void) { s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); +#ifdef CONFIG_SAMSUNG_CLOCK s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); +#endif } void s3c_pm_save_core(void) { +#ifdef CONFIG_SAMSUNG_CLOCK s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); +#endif s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); } -- cgit v1.2.3 From 3c27f314c676ee31eafd423ce2c640ed129cd5e0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 25 Feb 2014 09:50:44 +0900 Subject: ARM: S3C24XX: convert s3c2412 to common clock framework Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Signed-off-by: Heiko Stuebner Reviewed-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/Kconfig | 8 +- arch/arm/mach-s3c24xx/Makefile | 2 +- arch/arm/mach-s3c24xx/clock-s3c2412.c | 760 ---------------------------------- arch/arm/mach-s3c24xx/common.c | 9 +- arch/arm/mach-s3c24xx/common.h | 4 + arch/arm/mach-s3c24xx/mach-jive.c | 9 +- arch/arm/mach-s3c24xx/mach-smdk2413.c | 9 +- arch/arm/mach-s3c24xx/mach-vstms.c | 9 +- arch/arm/mach-s3c24xx/s3c2412.c | 43 -- 9 files changed, 40 insertions(+), 813 deletions(-) delete mode 100644 arch/arm/mach-s3c24xx/clock-s3c2412.c (limited to 'arch') diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 52f1c40ccf07..fbafb9a1975b 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -39,9 +39,10 @@ config CPU_S3C2410 config CPU_S3C2412 bool "SAMSUNG S3C2412" - depends on SAMSUNG_CLOCK + select COMMON_CLK select CPU_ARM926T select CPU_LLSERIAL_S3C2440 + select S3C2412_COMMON_CLK select S3C2412_DMA if S3C24XX_DMA select S3C2412_PM if PM help @@ -363,6 +364,11 @@ config S3C2412_PM_SLEEP if CPU_S3C2412 +config S3C2412_COMMON_CLK + bool + help + Build the s3c2412 clock driver based on the common clock framework. + config CPU_S3C2412_ONLY bool depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile index ba0e5475a807..f25479721dc9 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c24xx/Makefile @@ -21,7 +21,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o -obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o +obj-$(CONFIG_CPU_S3C2412) += s3c2412.o obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c deleted file mode 100644 index 192a5b2550b0..000000000000 --- a/arch/arm/mach-s3c24xx/clock-s3c2412.c +++ /dev/null @@ -1,760 +0,0 @@ -/* linux/arch/arm/mach-s3c2412/clock.c - * - * Copyright (c) 2006 Simtec Electronics - * Ben Dooks - * - * S3C2412,S3C2413 Clock control support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include - -/* We currently have to assume that the system is running - * from the XTPll input, and that all ***REFCLKs are being - * fed from it, as we cannot read the state of OM[4] from - * software. - * - * It would be possible for each board initialisation to - * set the correct muxing at initialisation -*/ - -static int s3c2412_clkcon_enable(struct clk *clk, int enable) -{ - unsigned int clocks = clk->ctrlbit; - unsigned long clkcon; - - clkcon = __raw_readl(S3C2410_CLKCON); - - if (enable) - clkcon |= clocks; - else - clkcon &= ~clocks; - - __raw_writel(clkcon, S3C2410_CLKCON); - - return 0; -} - -static int s3c2412_upll_enable(struct clk *clk, int enable) -{ - unsigned long upllcon = __raw_readl(S3C2410_UPLLCON); - unsigned long orig = upllcon; - - if (!enable) - upllcon |= S3C2412_PLLCON_OFF; - else - upllcon &= ~S3C2412_PLLCON_OFF; - - __raw_writel(upllcon, S3C2410_UPLLCON); - - /* allow ~150uS for the PLL to settle and lock */ - - if (enable && (orig & S3C2412_PLLCON_OFF)) - udelay(150); - - return 0; -} - -/* clock selections */ - -static struct clk clk_erefclk = { - .name = "erefclk", -}; - -static struct clk clk_urefclk = { - .name = "urefclk", -}; - -static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_urefclk) - clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL; - else if (parent == &clk_upll) - clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static struct clk clk_usysclk = { - .name = "usysclk", - .parent = &clk_xtal, - .ops = &(struct clk_ops) { - .set_parent = s3c2412_setparent_usysclk, - }, -}; - -static struct clk clk_mrefclk = { - .name = "mrefclk", - .parent = &clk_xtal, -}; - -static struct clk clk_mdivclk = { - .name = "mdivclk", - .parent = &clk_xtal, -}; - -static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_usysclk) - clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK; - else if (parent == &clk_h) - clksrc |= S3C2412_CLKSRC_USBCLK_HCLK; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - div = parent_rate / rate; - if (div > 2) - div = 2; - - return parent_rate / div; -} - -static unsigned long s3c2412_getrate_usbsrc(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1); -} - -static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_usbsrc(clk, rate); - - if ((parent_rate / rate) == 2) - clkdivn |= S3C2412_CLKDIVN_USB48DIV; - else - clkdivn &= ~S3C2412_CLKDIVN_USB48DIV; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_usbsrc = { - .name = "usbsrc", - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_usbsrc, - .set_rate = s3c2412_setrate_usbsrc, - .round_rate = s3c2412_roundrate_usbsrc, - .set_parent = s3c2412_setparent_usbsrc, - }, -}; - -static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_mdivclk) - clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static struct clk clk_msysclk = { - .name = "msysclk", - .ops = &(struct clk_ops) { - .set_parent = s3c2412_setparent_msysclk, - }, -}; - -static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) -{ - unsigned long flags; - unsigned long clkdiv; - unsigned long dvs; - - /* Note, we current equate fclk andf msysclk for S3C2412 */ - - if (parent == &clk_msysclk || parent == &clk_f) - dvs = 0; - else if (parent == &clk_h) - dvs = S3C2412_CLKDIVN_DVSEN; - else - return -EINVAL; - - clk->parent = parent; - - /* update this under irq lockdown, clkdivn is not protected - * by the clock system. */ - - local_irq_save(flags); - - clkdiv = __raw_readl(S3C2410_CLKDIVN); - clkdiv &= ~S3C2412_CLKDIVN_DVSEN; - clkdiv |= dvs; - __raw_writel(clkdiv, S3C2410_CLKDIVN); - - local_irq_restore(flags); - - return 0; -} - -static struct clk clk_armclk = { - .name = "armclk", - .parent = &clk_msysclk, - .ops = &(struct clk_ops) { - .set_parent = s3c2412_setparent_armclk, - }, -}; - -/* these next clocks have an divider immediately after them, - * so we can register them with their divider and leave out the - * intermediate clock stage -*/ -static unsigned long s3c2412_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - return parent_rate; - - /* note, we remove the +/- 1 calculations as they cancel out */ - - div = (rate / parent_rate); - - if (div < 1) - div = 1; - else if (div > 16) - div = 16; - - return parent_rate / div; -} - -static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_erefclk) - clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_getrate_uart(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_UARTDIV_MASK; - div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_uart = { - .name = "uartclk", - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_uart, - .set_rate = s3c2412_setrate_uart, - .set_parent = s3c2412_setparent_uart, - .round_rate = s3c2412_roundrate_clksrc, - }, -}; - -static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_erefclk) - clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL; - else if (parent == &clk_mpll) - clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} - -static unsigned long s3c2412_getrate_i2s(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_I2SDIV_MASK; - div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_i2s = { - .name = "i2sclk", - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_i2s, - .set_rate = s3c2412_setrate_i2s, - .set_parent = s3c2412_setparent_i2s, - .round_rate = s3c2412_roundrate_clksrc, - }, -}; - -static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - - if (parent == &clk_usysclk) - clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK; - else if (parent == &clk_h) - clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK; - else - return -EINVAL; - - clk->parent = parent; - - __raw_writel(clksrc, S3C2412_CLKSRC); - return 0; -} -static unsigned long s3c2412_getrate_cam(struct clk *clk) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long div = __raw_readl(S3C2410_CLKDIVN); - - div &= S3C2412_CLKDIVN_CAMDIV_MASK; - div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT; - - return parent_rate / (div + 1); -} - -static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN); - - rate = s3c2412_roundrate_clksrc(clk, rate); - - clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK; - clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT; - - __raw_writel(clkdivn, S3C2410_CLKDIVN); - return 0; -} - -static struct clk clk_cam = { - .name = "camif-upll", /* same as 2440 name */ - .ops = &(struct clk_ops) { - .get_rate = s3c2412_getrate_cam, - .set_rate = s3c2412_setrate_cam, - .set_parent = s3c2412_setparent_cam, - .round_rate = s3c2412_roundrate_clksrc, - }, -}; - -/* standard clock definitions */ - -static struct clk init_clocks_disable[] = { - { - .name = "nand", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_NAND, - }, { - .name = "sdi", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_SDI, - }, { - .name = "adc", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_ADC, - }, { - .name = "i2c", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_IIC, - }, { - .name = "iis", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_IIS, - }, { - .name = "spi", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_SPI, - } -}; - -static struct clk init_clocks[] = { - { - .name = "dma.0", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA0, - }, { - .name = "dma.1", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA1, - }, { - .name = "dma.2", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA2, - }, { - .name = "dma.3", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_DMA3, - }, { - .name = "lcd", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_LCDC, - }, { - .name = "gpio", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_GPIO, - }, { - .name = "usb-host", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USBH, - }, { - .name = "usb-device", - .parent = &clk_h, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USBD, - }, { - .name = "timers", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_PWMT, - }, { - .name = "uart", - .devname = "s3c2412-uart.0", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART0, - }, { - .name = "uart", - .devname = "s3c2412-uart.1", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART1, - }, { - .name = "uart", - .devname = "s3c2412-uart.2", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_UART2, - }, { - .name = "rtc", - .parent = &clk_p, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_RTC, - }, { - .name = "watchdog", - .parent = &clk_p, - .ctrlbit = 0, - }, { - .name = "usb-bus-gadget", - .parent = &clk_usb_bus, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USB_DEV48, - }, { - .name = "usb-bus-host", - .parent = &clk_usb_bus, - .enable = s3c2412_clkcon_enable, - .ctrlbit = S3C2412_CLKCON_USB_HOST48, - } -}; - -/* clocks to add where we need to check their parentage */ - -struct clk_init { - struct clk *clk; - unsigned int bit; - struct clk *src_0; - struct clk *src_1; -}; - -static struct clk_init clks_src[] __initdata = { - { - .clk = &clk_usysclk, - .bit = S3C2412_CLKSRC_USBCLK_HCLK, - .src_0 = &clk_urefclk, - .src_1 = &clk_upll, - }, { - .clk = &clk_i2s, - .bit = S3C2412_CLKSRC_I2SCLK_MPLL, - .src_0 = &clk_erefclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_cam, - .bit = S3C2412_CLKSRC_CAMCLK_HCLK, - .src_0 = &clk_usysclk, - .src_1 = &clk_h, - }, { - .clk = &clk_msysclk, - .bit = S3C2412_CLKSRC_MSYSCLK_MPLL, - .src_0 = &clk_mdivclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_uart, - .bit = S3C2412_CLKSRC_UARTCLK_MPLL, - .src_0 = &clk_erefclk, - .src_1 = &clk_mpll, - }, { - .clk = &clk_usbsrc, - .bit = S3C2412_CLKSRC_USBCLK_HCLK, - .src_0 = &clk_usysclk, - .src_1 = &clk_h, - /* here we assume OM[4] select xtal */ - }, { - .clk = &clk_erefclk, - .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK, - .src_0 = &clk_xtal, - .src_1 = &clk_ext, - }, { - .clk = &clk_urefclk, - .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK, - .src_0 = &clk_xtal, - .src_1 = &clk_ext, - }, -}; - -/* s3c2412_clk_initparents - * - * Initialise the parents for the clocks that we get at start-time -*/ - -static void __init s3c2412_clk_initparents(void) -{ - unsigned long clksrc = __raw_readl(S3C2412_CLKSRC); - struct clk_init *cip = clks_src; - struct clk *src; - int ptr; - int ret; - - for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) { - ret = s3c24xx_register_clock(cip->clk); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - cip->clk->name, ret); - } - - src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0; - - printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name); - clk_set_parent(cip->clk, src); - } -} - -/* clocks to add straight away */ - -static struct clk *clks[] __initdata = { - &clk_ext, - &clk_usb_bus, - &clk_mrefclk, - &clk_armclk, -}; - -static struct clk_lookup s3c2412_clk_lookup[] = { - CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), - CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), - CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk), -}; - -int __init s3c2412_baseclk_add(void) -{ - unsigned long clkcon = __raw_readl(S3C2410_CLKCON); - unsigned int dvs; - struct clk *clkp; - int ret; - int ptr; - - clk_upll.enable = s3c2412_upll_enable; - clk_usb_bus.parent = &clk_usbsrc; - clk_usb_bus.rate = 0x0; - - clk_f.parent = &clk_msysclk; - - s3c2412_clk_initparents(); - - for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { - clkp = clks[ptr]; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* set the dvs state according to what we got at boot time */ - - dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN; - - if (dvs) - clk_armclk.parent = &clk_h; - - printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off"); - - /* ensure usb bus clock is within correct rate of 48MHz */ - - if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) { - printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n"); - - /* for the moment, let's use the UPLL, and see if we can - * get 48MHz */ - - clk_set_parent(&clk_usysclk, &clk_upll); - clk_set_parent(&clk_usbsrc, &clk_usysclk); - clk_set_rate(&clk_usbsrc, 48*1000*1000); - } - - printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n", - (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on", - print_mhz(clk_get_rate(&clk_upll)), - print_mhz(clk_get_rate(&clk_usb_bus))); - - /* register clocks from clock array */ - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - /* ensure that we note the clock state */ - - clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } - - /* We must be careful disabling the clocks we are not intending to - * be using at boot time, as subsystems such as the LCD which do - * their own DMA requests to the bus can cause the system to lockup - * if they where in the middle of requesting bus access. - * - * Disabling the LCD clock if the LCD is active is very dangerous, - * and therefore the bootloader should be careful to not enable - * the LCD clock if it is not needed. - */ - - /* install (and disable) the clocks we do not need immediately */ - - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { - - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - - s3c2412_clkcon_enable(clkp, 0); - } - - clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup)); - return 0; -} diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 412ca006fcce..ad5b76bf4d51 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -127,7 +127,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32412001, .idmask = 0xffffffff, .map_io = s3c2412_map_io, - .init_clocks = s3c2412_init_clocks, .init_uarts = s3c2412_init_uarts, .init = s3c2412_init, .name = name_s3c2412, @@ -136,7 +135,6 @@ static struct cpu_table cpu_ids[] __initdata = { .idcode = 0x32412003, .idmask = 0xffffffff, .map_io = s3c2412_map_io, - .init_clocks = s3c2412_init_clocks, .init_uarts = s3c2412_init_uarts, .init = s3c2412_init, .name = name_s3c2412, @@ -535,6 +533,13 @@ struct platform_device s3c2443_device_dma = { }; #endif +#ifdef CONFIG_CPU_S3C2412 +void __init s3c2412_init_clocks(int xtal) +{ + s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR); +} +#endif + #ifdef CONFIG_CPU_S3C2416 void __init s3c2416_init_clocks(int xtal) { diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h index d7323f16427f..3fade6d796f9 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c24xx/common.h @@ -114,6 +114,10 @@ extern struct platform_device s3c2412_device_dma; extern struct platform_device s3c2440_device_dma; extern struct platform_device s3c2443_device_dma; +#ifdef CONFIG_S3C2412_COMMON_CLK +void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, + unsigned long ext_f, void __iomem *reg_base); +#endif #ifdef CONFIG_S3C2443_COMMON_CLK void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, int current_soc, diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c index 5faa7239e7d6..e81ea82c55f9 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c24xx/mach-jive.c @@ -507,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = { static void __init jive_map_io(void) { s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init jive_init_time(void) +{ + s3c2412_init_clocks(12000000); + samsung_timer_init(); +} + static void jive_power_off(void) { printk(KERN_INFO "powering system down...\n"); @@ -665,6 +670,6 @@ MACHINE_START(JIVE, "JIVE") .init_irq = s3c2412_init_irq, .map_io = jive_map_io, .init_machine = jive_machine_init, - .init_time = samsung_timer_init, + .init_time = jive_init_time, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c index 233fe52d2015..a38f8a049e22 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c @@ -106,11 +106,16 @@ static void __init smdk2413_fixup(struct tag *tags, char **cmdline, static void __init smdk2413_map_io(void) { s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init smdk2413_init_time(void) +{ + s3c2412_init_clocks(12000000); + samsung_timer_init(); +} + static void __init smdk2413_machine_init(void) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ @@ -159,6 +164,6 @@ MACHINE_START(SMDK2413, "SMDK2413") .init_irq = s3c2412_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = smdk2413_init_time, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c index 40868c0e0a68..6b706c915387 100644 --- a/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/arch/arm/mach-s3c24xx/mach-vstms.c @@ -142,11 +142,16 @@ static void __init vstms_fixup(struct tag *tags, char **cmdline, static void __init vstms_map_io(void) { s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); - s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); } +static void __init vstms_init_time(void) +{ + s3c2412_init_clocks(12000000); + samsung_timer_init(); +} + static void __init vstms_init(void) { s3c_i2c0_set_platdata(NULL); @@ -162,6 +167,6 @@ MACHINE_START(VSTMS, "VSTMS") .init_irq = s3c2412_init_irq, .init_machine = vstms_init, .map_io = vstms_map_io, - .init_time = samsung_timer_init, + .init_time = vstms_init_time, .restart = s3c2412_restart, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index 657cbaca80ac..d49f52fbc842 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c @@ -173,49 +173,6 @@ void __init s3c2412_map_io(void) void __init_or_cpufreq s3c2412_setup_clocks(void) { - struct clk *xtal_clk; - unsigned long tmp; - unsigned long xtal; - unsigned long fclk; - unsigned long hclk; - unsigned long pclk; - - xtal_clk = clk_get(NULL, "xtal"); - xtal = clk_get_rate(xtal_clk); - clk_put(xtal_clk); - - /* now we've got our machine bits initialised, work out what - * clocks we've got */ - - fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); - - clk_mpll.rate = fclk; - - tmp = __raw_readl(S3C2410_CLKDIVN); - - /* work out clock scalings */ - - hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1); - hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1); - pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1); - - /* print brieft summary of clocks, etc */ - - printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", - print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); - - s3c24xx_setup_clocks(fclk, hclk, pclk); -} - -void __init s3c2412_init_clocks(int xtal) -{ - /* initialise the clocks here, to allow other things like the - * console to use them - */ - - s3c24xx_register_baseclocks(xtal); - s3c2412_setup_clocks(); - s3c2412_baseclk_add(); } /* need to register the subsystem before we actually register the device, and -- cgit v1.2.3 From ff0c41b2df1577f3354f788af4f6bb5dbdfd26da Mon Sep 17 00:00:00 2001 From: Mike Qiu Date: Mon, 14 Apr 2014 16:12:35 -0600 Subject: powerpc/PCI: Fix NULL dereference in sys_pciconfig_iobase() list traversal 3bc955987fb3 ("powerpc/PCI: Use list_for_each_entry() for bus traversal") caused a NULL pointer dereference because the loop body set the iterator to NULL: Unable to handle kernel paging request for data at address 0x00000000 Faulting instruction address: 0xc000000000041d78 Oops: Kernel access of bad area, sig: 11 [#1] ... NIP [c000000000041d78] .sys_pciconfig_iobase+0x68/0x1f0 LR [c000000000041e0c] .sys_pciconfig_iobase+0xfc/0x1f0 Call Trace: [c0000003b4787db0] [c000000000041e0c] .sys_pciconfig_iobase+0xfc/0x1f0 (unreliable) [c0000003b4787e30] [c000000000009ed8] syscall_exit+0x0/0x98 Fix it by using a temporary variable for the iterator. [bhelgaas: changelog, drop tmp_bus initialization] Fixes: 3bc955987fb3 powerpc/PCI: Use list_for_each_entry() for bus traversal Signed-off-by: Mike Qiu Signed-off-by: Bjorn Helgaas --- arch/powerpc/kernel/pci_64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c index 2a4779091a58..155013da27e0 100644 --- a/arch/powerpc/kernel/pci_64.c +++ b/arch/powerpc/kernel/pci_64.c @@ -208,7 +208,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus, unsigned long in_devfn) { struct pci_controller* hose; - struct pci_bus *bus = NULL; + struct pci_bus *tmp_bus, *bus = NULL; struct device_node *hose_node; /* Argh ! Please forgive me for that hack, but that's the @@ -229,10 +229,12 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus, * used on pre-domains setup. We return the first match */ - list_for_each_entry(bus, &pci_root_buses, node) { - if (in_bus >= bus->number && in_bus <= bus->busn_res.end) + list_for_each_entry(tmp_bus, &pci_root_buses, node) { + if (in_bus >= tmp_bus->number && + in_bus <= tmp_bus->busn_res.end) { + bus = tmp_bus; break; - bus = NULL; + } } if (bus == NULL || bus->dev.of_node == NULL) return -ENODEV; -- cgit v1.2.3 From 44ae903b96b1e5f9ff3103cd86918619c188003f Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 20 Mar 2014 15:16:54 +0100 Subject: ARM: 8008/1: topology: Coding style fixes Use kcalloc() and ULONG_MAX rather than open coding them. Signed-off-by: Mark Brown Signed-off-by: Russell King --- arch/arm/kernel/topology.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 0bc94b1fd1ae..0fa8825cea04 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -91,13 +91,13 @@ static void __init parse_dt_topology(void) { const struct cpu_efficiency *cpu_eff; struct device_node *cn = NULL; - unsigned long min_capacity = (unsigned long)(-1); + unsigned long min_capacity = ULONG_MAX; unsigned long max_capacity = 0; unsigned long capacity = 0; - int alloc_size, cpu = 0; + int cpu = 0; - alloc_size = nr_cpu_ids * sizeof(*__cpu_capacity); - __cpu_capacity = kzalloc(alloc_size, GFP_NOWAIT); + __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity), + GFP_NOWAIT); for_each_possible_cpu(cpu) { const u32 *rate; -- cgit v1.2.3 From 4d4a0ff30c39b82c1dc549f2cc7a62b514431e64 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Apr 2014 19:35:57 +0200 Subject: ARM: shmobile: koelsch legacy: Enable Quad SPI transfers for the SPI FLASH Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-koelsch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c index 5a034ff405d0..a12a9d3b4b6e 100644 --- a/arch/arm/mach-shmobile/board-koelsch.c +++ b/arch/arm/mach-shmobile/board-koelsch.c @@ -216,7 +216,7 @@ static const struct spi_board_info spi_info[] __initconst = { { .modalias = "m25p80", .platform_data = &spi_flash_data, - .mode = SPI_MODE_0, + .mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD, .max_speed_hz = 30000000, .bus_num = 0, .chip_select = 0, -- cgit v1.2.3 From ed56083acfe7c872318b8321c7d0e25a6b520371 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Apr 2014 19:35:58 +0200 Subject: ARM: shmobile: koelsch dts: Enable Quad SPI transfers for the SPI FLASH Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 2a0569d93b6e..22edf3efe4c8 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -354,6 +354,8 @@ compatible = "spansion,s25fl512s"; reg = <0>; spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; partition@0 { -- cgit v1.2.3 From 9909d2cb41a9c752cbbef5d9fb57d80a7196e951 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Apr 2014 19:36:00 +0200 Subject: ARM: shmobile: lager dts: Enable Quad SPI transfers for the SPI FLASH Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 265cba1d53dc..d350d7c6e9f5 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -243,6 +243,8 @@ compatible = "spansion,s25fl512s"; reg = <0>; spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; partition@0 { -- cgit v1.2.3 From a09b2f0ba170dc89a67d6c4c4f027b37a085dad9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 14 Apr 2014 19:35:59 +0200 Subject: ARM: shmobile: lager legacy: Enable Quad SPI transfers for the SPI FLASH Signed-off-by: Geert Uytterhoeven Acked-by: Magnus Damm Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/board-lager.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index 6af09e1e0841..6c4fcfe5d9db 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -325,12 +325,12 @@ static const struct rspi_plat_data qspi_pdata __initconst = { static const struct spi_board_info spi_info[] __initconst = { { - .modalias = "m25p80", - .platform_data = &spi_flash_data, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 0, - .chip_select = 0, + .modalias = "m25p80", + .platform_data = &spi_flash_data, + .mode = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD, + .max_speed_hz = 30000000, + .bus_num = 0, + .chip_select = 0, }, }; -- cgit v1.2.3 From 15e524a4ea23015aa3df37bfc37bf8be8eae8ead Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 19 Mar 2014 15:47:53 -0600 Subject: ARM: tegra: add Jetson TK1 device tree Jetson TK1 is an NVIDIA Tegra124 development board, containing Tegra124, 2GB RAM, eMMC, SD card, SPI flash, serial port, PCIe Ethernet, HDMI, audio, mini PCIe, JTAG, SATA, and an expansion IO connector containing GPIOs, I2C, SPI, CSI, eDP, etc. The following features work with this device tree: UART, SD card, eMMC, SPI flash, USB (full-size jack, and mini-PCIe), audio, AS3722 RTC, system power-off, suspend/resume (LP1) with wake via RTC alarm. The following features should work with this device tree, but are not validated: Expansion I2C, expansion SPI, expansion GPIO, gpio-key for the power button. The following features are not yet implemented in this device tree: Most voltage regulators, expansion UART, HDMI, eDP, PCIe (Ethernet, and mini- PCIe connector), CSI, SATA. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra124-jetson-tk1.dts | 1561 +++++++++++++++++++++++++++++ 2 files changed, 1562 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-jetson-tk1.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..d96b2c2ec429 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -368,6 +368,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra114-dalmore.dtb \ + tegra124-jetson-tk1.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ versatile-pb.dtb diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts new file mode 100644 index 000000000000..dedcb0c165c5 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -0,0 +1,1561 @@ +/dts-v1/; + +#include +#include "tegra124.dtsi" + +/ { + model = "NVIDIA Tegra124 Jetson TK1"; + compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + pinmux: pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb0 { + nvidia,pins = "pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pb1 { + nvidia,pins = "pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pc7 { + nvidia,pins = "pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg0 { + nvidia,pins = "pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg1 { + nvidia,pins = "pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg2 { + nvidia,pins = "pg2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg3 { + nvidia,pins = "pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg4 { + nvidia,pins = "pg4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg5 { + nvidia,pins = "pg5"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg6 { + nvidia,pins = "pg6"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph2 { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph3 { + nvidia,pins = "ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph4 { + nvidia,pins = "ph4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph5 { + nvidia,pins = "ph5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph6 { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi0 { + nvidia,pins = "pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi1 { + nvidia,pins = "pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi2 { + nvidia,pins = "pi2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi3 { + nvidia,pins = "pi3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi4 { + nvidia,pins = "pi4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi5 { + nvidia,pins = "pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi6 { + nvidia,pins = "pi6"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pi7 { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj0 { + nvidia,pins = "pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj2 { + nvidia,pins = "pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pj7 { + nvidia,pins = "pj7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk0 { + nvidia,pins = "pk0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk1 { + nvidia,pins = "pk1"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk2 { + nvidia,pins = "pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk3 { + nvidia,pins = "pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk4 { + nvidia,pins = "pk4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pk7 { + nvidia,pins = "pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "sys"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "displaya_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row16_pt0 { + nvidia,pins = "kb_row16_pt0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row17_pt1 { + nvidia,pins = "kb_row17_pt1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cd_n_pv2 { + nvidia,pins = "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_wp_n_pv3 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + gpio_w2_aud_pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_w3_aud_pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x1_aud_px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x3_aud_px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x4_aud_px4 { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x5_aud_px5 { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x6_aud_px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio_x7_aud_px7 { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "vimclk2_alt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap_mclk1_req_pee2 { + nvidia,pins = "dap_mclk1_req_pee2"; + nvidia,function = "sata"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc3_clk_lb_out_pee4 { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_lb_in_pee5 { + nvidia,pins = "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dp_hpd_pff0 { + nvidia,pins = "dp_hpd_pff0"; + nvidia,function = "dp"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + usb_vbus_en2_pff1 { + nvidia,pins = "usb_vbus_en2_pff1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pff2 { + nvidia,pins = "pff2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + /* DB9 serial port */ + serial@0,70006300 { + status = "okay"; + }; + + /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + rt5640: audio-codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + realtek,ldo1-en-gpios = + <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + pagesize = <8>; + }; + }; + + /* Expansion GEN2_I2C_* */ + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion CAM_I2C_* */ + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* HDMI DDC */ + i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + /* Expansion PWR_I2C_*, on-board components */ + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1_2_4_7 { + pins = "gpio1", "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_5_6 { + pins = "gpio3", "gpio5", "gpio6"; + bias-high-impedance; + }; + }; + }; + }; + + /* Expansion TS_SPI_* */ + spi@0,7000d400 { + status = "okay"; + }; + + /* Internal SPI */ + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + /* SD card */ + sdhci@0,700b0400 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + /* eMMC */ + sdhci@0,700b0600 { + status = "okay"; + bus-width = <8>; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + /* mini-PCIe USB */ + usb@0,7d004000 { + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + }; + + /* USB A connector */ + usb@0,7d008000 { + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", + "nvidia,tegra-audio-rt5640"; + nvidia,model = "NVIDIA Tegra Jetson TK1"; + + nvidia,audio-routing = + "Headphones", "HPOR", + "Headphones", "HPOL", + "Mic Jack", "MICBIAS1", + "IN2P", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&rt5640>; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; +}; -- cgit v1.2.3 From 22b3577659fd2d001ef9455a2856321a99229747 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 24 Mar 2014 18:04:43 -0600 Subject: ARM: tegra: define Jetson TK1 regulators These are mostly identical to the Venice2 regulator definitions, since the board designs are very similar. Differences are: - Jetson TK1 doesn't have a built-in LCD panel, so on-board regulators are not present for the backlight, touchscreen, or panel. - +3.3V_RUN needs to be boot-on/always-on, since it's widely used. This change should likely be propagated to Venice2 for completeness, although it will have no practical effect there since various other regulators use +3.3V_RUN as their supply and are always-on. - +3.3V_LP0 needs to be boot-on as well as always-on. One reason is because it's used to driver the UART level-shifter; without this, I see a brief period of UART corruption during cold boots.I suspect this change needs to be propagated to Venice2, and we simply haven't noticed the need since there's no UART level-shifter on Venice2. - A few rails have different names in the schematics. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 230 ++++++++++++++++++++++++++++++ 1 file changed, 230 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index dedcb0c165c5..ae5c750dc515 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1426,6 +1426,155 @@ bias-high-impedance; }; }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <2500000>; + regulator-always-on; + regulator-boot-on; + ams,external-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,external-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.05V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + ldo4 { + regulator-name = "+2.8V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+3.3V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; }; }; @@ -1462,6 +1611,7 @@ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; bus-width = <4>; + vmmc-supply = <&vddio_sdmmc3>; }; /* eMMC */ @@ -1525,6 +1675,72 @@ #address-cells = <1>; #size-cells = <0>; + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+USB0_VBUS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + vdd_usb3_vbus: regulator@8 { compatible = "regulator-fixed"; reg = <8>; @@ -1534,6 +1750,20 @@ gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; enable-active-high; gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; }; }; -- cgit v1.2.3 From 72dc392ae5bbad3477053ac4c5708dba6706ffa0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 15 Apr 2014 14:33:57 +0200 Subject: ARM: shmobile: r8a7740: Remove unused r8a7740_add_early_devices_dt() It was removed in commit 744fdc8dc0e22cc5b61ee1bcde9375f188daa330 ("ARM: shmobile: r8a7740: Prepare for reference DT setup"), but accidentally resurrected in commit 88378837780166d67a11142cd6f76596c0a2d8c3 ("ARM: shmobile: Remove unused r8a7740 auxdata table"). Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7740.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 8f3c68101d59..cba3a07a97c2 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -869,17 +869,6 @@ void __init r8a7740_add_early_devices(void) #ifdef CONFIG_USE_OF -void __init r8a7740_add_early_devices_dt(void) -{ - shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ - - early_platform_add_devices(r8a7740_early_devices, - ARRAY_SIZE(r8a7740_early_devices)); - - /* setup early console here as well */ - shmobile_setup_console(); -} - void __init r8a7740_add_standard_devices_dt(void) { platform_add_devices(r8a7740_devices_dt, -- cgit v1.2.3 From 1fba31f047639a6c7accf4f6d075a6cf9eacecc0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 15 Apr 2014 14:33:59 +0200 Subject: ARM: shmobile: sh7372: Call sh7372_add_early_devices() instead of open coding Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-sh7372.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 27301278c208..f8176b051be4 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c @@ -1037,11 +1037,7 @@ void __init sh7372_add_early_devices_dt(void) { shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */ - early_platform_add_devices(sh7372_early_devices, - ARRAY_SIZE(sh7372_early_devices)); - - /* setup early console here as well */ - shmobile_setup_console(); + sh7372_add_early_devices(); } void __init sh7372_add_standard_devices_dt(void) -- cgit v1.2.3 From bb6c3d58c36adb205b4bf233fd1c4079e02a6811 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 15 Apr 2014 14:33:58 +0200 Subject: ARM: shmobile: r8a7740: Make r8a7740_meram_workaround() __init It's called from eva_init() only, which is __init Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/setup-r8a7740.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index cba3a07a97c2..a177a7b3bdbd 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c @@ -765,7 +765,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = { * "Media RAM (MERAM)" on r8a7740 documentation */ #define MEBUFCNTR 0xFE950098 -void r8a7740_meram_workaround(void) +void __init r8a7740_meram_workaround(void) { void __iomem *reg; -- cgit v1.2.3 From dd485ab9a88267f4db0d58ace23b19e876ebf8ac Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 15 Apr 2014 14:51:50 +0200 Subject: ARM: shmobile: armadillo-reference dts: Seiko Instruments, Inc is "sii" Use "sii,s35390a" instead of "seiko,s35390a", cfr. Documentation/devicetree/bindings/i2c/trivial-devices.txt and Documentation/devicetree/bindings/vendor-prefixes.txt. Signed-off-by: Geert Uytterhoeven Acked-by: Ulrich Hecht Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts index 0cb235a450b9..10344e6edd20 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts @@ -180,7 +180,7 @@ &i2c2 { status = "okay"; rtc@30 { - compatible = "seiko,s35390a"; + compatible = "sii,s35390a"; reg = <0x30>; }; }; -- cgit v1.2.3 From b13b1d2d8692b437203de7a404c6b809d2cc4d99 Mon Sep 17 00:00:00 2001 From: Shaohua Li Date: Tue, 8 Apr 2014 15:58:09 +0800 Subject: x86/mm: In the PTE swapout page reclaim case clear the accessed bit instead of flushing the TLB We use the accessed bit to age a page at page reclaim time, and currently we also flush the TLB when doing so. But in some workloads TLB flush overhead is very heavy. In my simple multithreaded app with a lot of swap to several pcie SSDs, removing the tlb flush gives about 20% ~ 30% swapout speedup. Fortunately just removing the TLB flush is a valid optimization: on x86 CPUs, clearing the accessed bit without a TLB flush doesn't cause data corruption. It could cause incorrect page aging and the (mistaken) reclaim of hot pages, but the chance of that should be relatively low. So as a performance optimization don't flush the TLB when clearing the accessed bit, it will eventually be flushed by a context switch or a VM operation anyway. [ In the rare event of it not getting flushed for a long time the delay shouldn't really matter because there's no real memory pressure for swapout to react to. ] Suggested-by: Linus Torvalds Signed-off-by: Shaohua Li Acked-by: Rik van Riel Acked-by: Mel Gorman Acked-by: Hugh Dickins Acked-by: Johannes Weiner Cc: linux-mm@kvack.org Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/20140408075809.GA1764@kernel.org [ Rewrote the changelog and the code comments. ] Signed-off-by: Ingo Molnar --- arch/x86/mm/pgtable.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index c96314abd144..0004ac72dbdd 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -399,13 +399,20 @@ int pmdp_test_and_clear_young(struct vm_area_struct *vma, int ptep_clear_flush_young(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) { - int young; - - young = ptep_test_and_clear_young(vma, address, ptep); - if (young) - flush_tlb_page(vma, address); - - return young; + /* + * On x86 CPUs, clearing the accessed bit without a TLB flush + * doesn't cause data corruption. [ It could cause incorrect + * page aging and the (mistaken) reclaim of hot pages, but the + * chance of that should be relatively low. ] + * + * So as a performance optimization don't flush the TLB when + * clearing the accessed bit, it will eventually be flushed by + * a context switch or a VM operation anyway. [ In the rare + * event of it not getting flushed for a long time the delay + * shouldn't really matter because there's no real memory + * pressure for swapout to react to. ] + */ + return ptep_test_and_clear_young(vma, address, ptep); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE -- cgit v1.2.3 From 52e6e543f2d8c8320b6e9c53110bd1c5768d6b43 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 10 Apr 2014 14:30:56 +0800 Subject: crypto: bfin_crc - access crc registers by readl and writel functions Move architecture independant crc header file out of the blackfin folder. Signed-off-by: Sonic Zhang Reviewed-by: Marek Vasut Signed-off-by: Herbert Xu --- arch/blackfin/include/asm/bfin_crc.h | 125 ----------------------------------- drivers/crypto/bfin_crc.c | 42 +++++++----- drivers/crypto/bfin_crc.h | 125 +++++++++++++++++++++++++++++++++++ 3 files changed, 150 insertions(+), 142 deletions(-) delete mode 100644 arch/blackfin/include/asm/bfin_crc.h create mode 100644 drivers/crypto/bfin_crc.h (limited to 'arch') diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h deleted file mode 100644 index 75cef4dc85a1..000000000000 --- a/arch/blackfin/include/asm/bfin_crc.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * bfin_crc.h - interface to Blackfin CRC controllers - * - * Copyright 2012 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __BFIN_CRC_H__ -#define __BFIN_CRC_H__ - -/* Function driver which use hardware crc must initialize the structure */ -struct crc_info { - /* Input data address */ - unsigned char *in_addr; - /* Output data address */ - unsigned char *out_addr; - /* Input or output bytes */ - unsigned long datasize; - union { - /* CRC to compare with that of input buffer */ - unsigned long crc_compare; - /* Value to compare with input data */ - unsigned long val_verify; - /* Value to fill */ - unsigned long val_fill; - }; - /* Value to program the 32b CRC Polynomial */ - unsigned long crc_poly; - union { - /* CRC calculated from the input data */ - unsigned long crc_result; - /* First failed position to verify input data */ - unsigned long pos_verify; - }; - /* CRC mirror flags */ - unsigned int bitmirr:1; - unsigned int bytmirr:1; - unsigned int w16swp:1; - unsigned int fdsel:1; - unsigned int rsltmirr:1; - unsigned int polymirr:1; - unsigned int cmpmirr:1; -}; - -/* Userspace interface */ -#define CRC_IOC_MAGIC 'C' -#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int) -#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int) -#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int) -#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int) - - -#ifdef __KERNEL__ - -#include -#include -#include - -struct crc_register { - u32 control; - u32 datacnt; - u32 datacntrld; - u32 __pad_1[2]; - u32 compare; - u32 fillval; - u32 datafifo; - u32 intren; - u32 intrenset; - u32 intrenclr; - u32 poly; - u32 __pad_2[4]; - u32 status; - u32 datacntcap; - u32 __pad_3; - u32 result; - u32 curresult; - u32 __pad_4[3]; - u32 revid; -}; - -/* CRC_STATUS Masks */ -#define CMPERR 0x00000002 /* Compare error */ -#define DCNTEXP 0x00000010 /* datacnt register expired */ -#define IBR 0x00010000 /* Input buffer ready */ -#define OBR 0x00020000 /* Output buffer ready */ -#define IRR 0x00040000 /* Immediate result readt */ -#define LUTDONE 0x00080000 /* Look-up table generation done */ -#define FSTAT 0x00700000 /* FIFO status */ -#define MAX_FIFO 4 /* Max fifo size */ - -/* CRC_CONTROL Masks */ -#define BLKEN 0x00000001 /* Block enable */ -#define OPMODE 0x000000F0 /* Operation mode */ -#define OPMODE_OFFSET 4 /* Operation mode mask offset*/ -#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */ -#define MODE_DATA_FILL 2 /* MTM data fill */ -#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */ -#define MODE_DATA_VERIFY 4 /* MSM data verify */ -#define AUTOCLRZ 0x00000100 /* Auto clear to zero */ -#define AUTOCLRF 0x00000200 /* Auto clear to one */ -#define OBRSTALL 0x00001000 /* Stall on output buffer ready */ -#define IRRSTALL 0x00002000 /* Stall on immediate result ready */ -#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */ -#define BITMIRR_OFFSET 16 /* Mirror bits offset */ -#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */ -#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */ -#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */ -#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */ -#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */ -#define FDSEL_OFFSET 19 /* Mirror FIFO offset */ -#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */ -#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */ -#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */ -#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */ -#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */ -#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */ - -/* CRC_INTREN Masks */ -#define CMPERRI 0x02 /* CRC_ERROR_INTR */ -#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */ - -#endif - -#endif diff --git a/drivers/crypto/bfin_crc.c b/drivers/crypto/bfin_crc.c index c9ff298e6d26..cea3e8c1fdf9 100644 --- a/drivers/crypto/bfin_crc.c +++ b/drivers/crypto/bfin_crc.c @@ -30,9 +30,11 @@ #include #include -#include #include #include +#include + +#include "bfin_crc.h" #define CRC_CCRYPTO_QUEUE_LENGTH 5 @@ -54,7 +56,7 @@ struct bfin_crypto_crc { int irq; int dma_ch; u32 poly; - volatile struct crc_register *regs; + struct crc_register *regs; struct ahash_request *req; /* current request in operation */ struct dma_desc_array *sg_cpu; /* virt addr of sg dma descriptors */ @@ -132,13 +134,13 @@ static struct scatterlist *sg_get(struct scatterlist *sg_list, unsigned int nent static int bfin_crypto_crc_init_hw(struct bfin_crypto_crc *crc, u32 key) { - crc->regs->datacntrld = 0; - crc->regs->control = MODE_CALC_CRC << OPMODE_OFFSET; - crc->regs->curresult = key; + writel(0, &crc->regs->datacntrld); + writel(MODE_CALC_CRC << OPMODE_OFFSET, &crc->regs->control); + writel(key, &crc->regs->curresult); /* setup CRC interrupts */ - crc->regs->status = CMPERRI | DCNTEXPI; - crc->regs->intrenset = CMPERRI | DCNTEXPI; + writel(CMPERRI | DCNTEXPI, &crc->regs->status); + writel(CMPERRI | DCNTEXPI, &crc->regs->intrenset); return 0; } @@ -303,6 +305,7 @@ static int bfin_crypto_crc_handle_queue(struct bfin_crypto_crc *crc, int nsg, i, j; unsigned int nextlen; unsigned long flags; + u32 reg; spin_lock_irqsave(&crc->lock, flags); if (req) @@ -402,13 +405,14 @@ finish_update: ctx->sg_buflen += CHKSUM_DIGEST_SIZE; /* set CRC data count before start DMA */ - crc->regs->datacnt = ctx->sg_buflen >> 2; + writel(ctx->sg_buflen >> 2, &crc->regs->datacnt); /* setup and enable CRC DMA */ bfin_crypto_crc_config_dma(crc); /* finally kick off CRC operation */ - crc->regs->control |= BLKEN; + reg = readl(&crc->regs->control); + writel(reg | BLKEN, &crc->regs->control); return -EINPROGRESS; } @@ -529,14 +533,17 @@ static void bfin_crypto_crc_done_task(unsigned long data) static irqreturn_t bfin_crypto_crc_handler(int irq, void *dev_id) { struct bfin_crypto_crc *crc = dev_id; + u32 reg; - if (crc->regs->status & DCNTEXP) { - crc->regs->status = DCNTEXP; + if (readl(&crc->regs->status) & DCNTEXP) { + writel(DCNTEXP, &crc->regs->status); /* prepare results */ - put_unaligned_le32(crc->regs->result, crc->req->result); + put_unaligned_le32(readl(&crc->regs->result), + crc->req->result); - crc->regs->control &= ~BLKEN; + reg = readl(&crc->regs->control); + writel(reg & ~BLKEN, &crc->regs->control); crc->busy = 0; if (crc->req->base.complete) @@ -560,7 +567,7 @@ static int bfin_crypto_crc_suspend(struct platform_device *pdev, pm_message_t st struct bfin_crypto_crc *crc = platform_get_drvdata(pdev); int i = 100000; - while ((crc->regs->control & BLKEN) && --i) + while ((readl(&crc->regs->control) & BLKEN) && --i) cpu_relax(); if (i == 0) @@ -648,10 +655,11 @@ static int bfin_crypto_crc_probe(struct platform_device *pdev) */ crc->sg_mid_buf = (u8 *)(crc->sg_cpu + ((CRC_MAX_DMA_DESC + 1) << 1)); - crc->regs->control = 0; - crc->regs->poly = crc->poly = (u32)pdev->dev.platform_data; + writel(0, &crc->regs->control); + crc->poly = (u32)pdev->dev.platform_data; + writel(crc->poly, &crc->regs->poly); - while (!(crc->regs->status & LUTDONE) && (--timeout) > 0) + while (!(readl(&crc->regs->status) & LUTDONE) && (--timeout) > 0) cpu_relax(); if (timeout == 0) diff --git a/drivers/crypto/bfin_crc.h b/drivers/crypto/bfin_crc.h new file mode 100644 index 000000000000..75cef4dc85a1 --- /dev/null +++ b/drivers/crypto/bfin_crc.h @@ -0,0 +1,125 @@ +/* + * bfin_crc.h - interface to Blackfin CRC controllers + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CRC_H__ +#define __BFIN_CRC_H__ + +/* Function driver which use hardware crc must initialize the structure */ +struct crc_info { + /* Input data address */ + unsigned char *in_addr; + /* Output data address */ + unsigned char *out_addr; + /* Input or output bytes */ + unsigned long datasize; + union { + /* CRC to compare with that of input buffer */ + unsigned long crc_compare; + /* Value to compare with input data */ + unsigned long val_verify; + /* Value to fill */ + unsigned long val_fill; + }; + /* Value to program the 32b CRC Polynomial */ + unsigned long crc_poly; + union { + /* CRC calculated from the input data */ + unsigned long crc_result; + /* First failed position to verify input data */ + unsigned long pos_verify; + }; + /* CRC mirror flags */ + unsigned int bitmirr:1; + unsigned int bytmirr:1; + unsigned int w16swp:1; + unsigned int fdsel:1; + unsigned int rsltmirr:1; + unsigned int polymirr:1; + unsigned int cmpmirr:1; +}; + +/* Userspace interface */ +#define CRC_IOC_MAGIC 'C' +#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int) +#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int) +#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int) +#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int) + + +#ifdef __KERNEL__ + +#include +#include +#include + +struct crc_register { + u32 control; + u32 datacnt; + u32 datacntrld; + u32 __pad_1[2]; + u32 compare; + u32 fillval; + u32 datafifo; + u32 intren; + u32 intrenset; + u32 intrenclr; + u32 poly; + u32 __pad_2[4]; + u32 status; + u32 datacntcap; + u32 __pad_3; + u32 result; + u32 curresult; + u32 __pad_4[3]; + u32 revid; +}; + +/* CRC_STATUS Masks */ +#define CMPERR 0x00000002 /* Compare error */ +#define DCNTEXP 0x00000010 /* datacnt register expired */ +#define IBR 0x00010000 /* Input buffer ready */ +#define OBR 0x00020000 /* Output buffer ready */ +#define IRR 0x00040000 /* Immediate result readt */ +#define LUTDONE 0x00080000 /* Look-up table generation done */ +#define FSTAT 0x00700000 /* FIFO status */ +#define MAX_FIFO 4 /* Max fifo size */ + +/* CRC_CONTROL Masks */ +#define BLKEN 0x00000001 /* Block enable */ +#define OPMODE 0x000000F0 /* Operation mode */ +#define OPMODE_OFFSET 4 /* Operation mode mask offset*/ +#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */ +#define MODE_DATA_FILL 2 /* MTM data fill */ +#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */ +#define MODE_DATA_VERIFY 4 /* MSM data verify */ +#define AUTOCLRZ 0x00000100 /* Auto clear to zero */ +#define AUTOCLRF 0x00000200 /* Auto clear to one */ +#define OBRSTALL 0x00001000 /* Stall on output buffer ready */ +#define IRRSTALL 0x00002000 /* Stall on immediate result ready */ +#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */ +#define BITMIRR_OFFSET 16 /* Mirror bits offset */ +#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */ +#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */ +#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */ +#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */ +#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */ +#define FDSEL_OFFSET 19 /* Mirror FIFO offset */ +#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */ +#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */ +#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */ +#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */ +#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */ +#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */ + +/* CRC_INTREN Masks */ +#define CMPERRI 0x02 /* CRC_ERROR_INTR */ +#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */ + +#endif + +#endif -- cgit v1.2.3 From a9358bc3531901a15e2f7cd48550c9555fc0288f Mon Sep 17 00:00:00 2001 From: Peter Foley Date: Tue, 15 Apr 2014 13:58:13 -0400 Subject: x86/build: Supress realmode.bin is up to date message Supress this unnecessary message during kernel re-build: make[3]: 'arch/x86/realmode/rm/realmode.bin' is up to date. Signed-off-by: Peter Foley Link: http://lkml.kernel.org/r/1397584693-15902-1-git-send-email-pefoley2@pefoley.com Signed-off-by: Ingo Molnar --- arch/x86/realmode/rm/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/realmode/rm/Makefile b/arch/x86/realmode/rm/Makefile index 3497f14e4dea..7c0d7be176a5 100644 --- a/arch/x86/realmode/rm/Makefile +++ b/arch/x86/realmode/rm/Makefile @@ -52,8 +52,9 @@ $(obj)/realmode.elf: $(obj)/realmode.lds $(REALMODE_OBJS) FORCE OBJCOPYFLAGS_realmode.bin := -O binary targets += realmode.bin -$(obj)/realmode.bin: $(obj)/realmode.elf $(obj)/realmode.relocs +$(obj)/realmode.bin: $(obj)/realmode.elf $(obj)/realmode.relocs FORCE $(call if_changed,objcopy) + @: quiet_cmd_relocs = RELOCS $@ cmd_relocs = arch/x86/tools/relocs --realmode $< > $@ -- cgit v1.2.3 From cd9ae5fe47dfb9820976c3c38c70f4b07a5a1c36 Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 4 Apr 2014 06:31:04 +0300 Subject: KVM: x86: Fix page-tables reserved bits KVM does not handle the reserved bits of x86 page tables correctly: In PAE, bits 5:8 are reserved in the PDPTE. In IA-32e, bit 8 is not reserved. Signed-off-by: Nadav Amit Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/mmu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 813d31038b93..668ae5916de9 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -3538,7 +3538,7 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, case PT32E_ROOT_LEVEL: context->rsvd_bits_mask[0][2] = rsvd_bits(maxphyaddr, 63) | - rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */ + rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ context->rsvd_bits_mask[0][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 62); /* PDE */ context->rsvd_bits_mask[0][0] = exb_bit_rsvd | @@ -3550,9 +3550,9 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, break; case PT64_ROOT_LEVEL: context->rsvd_bits_mask[0][3] = exb_bit_rsvd | - rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7); context->rsvd_bits_mask[0][2] = exb_bit_rsvd | - rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8); + rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7); context->rsvd_bits_mask[0][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51); context->rsvd_bits_mask[0][0] = exb_bit_rsvd | -- cgit v1.2.3 From 9260764cb3daea8738ae308f8a8ecb31507c0d6f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 16 Apr 2014 10:34:18 -0600 Subject: ARM: tegra: fix Jetson TK1 SD card supply Regulator vddio_sdmmc3 provides the Tegra<->SD IO voltage, not the card core supply voltage. That is, it provides vqmmc, not vmmc. Fix the DT to correctly reflect this. Reported-by: Andrew Bresticker Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index ae5c750dc515..dd3076d94727 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1611,7 +1611,7 @@ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; bus-width = <4>; - vmmc-supply = <&vddio_sdmmc3>; + vqmmc-supply = <&vddio_sdmmc3>; }; /* eMMC */ -- cgit v1.2.3 From c7fe76721eb546d13fd5576cf135c414136ae4ff Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 15 Apr 2014 16:27:01 -0600 Subject: ARM: tegra: make Venice's +3.3V_RUN regulator always on This regulator supplies power to pretty much everything on the board, so it doesn't make sense to allow it to turn off. Mark it boot-on and always-on so it doesn't get turned off. Without this, I see issues with the eMMC device; it can't be correctly detected during boot. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index c17283c04598..87537f499875 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -1060,6 +1060,8 @@ regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_3v3_sys>; -- cgit v1.2.3 From 49228caee067854656778978c633f37815f0538e Mon Sep 17 00:00:00 2001 From: Andrew Bresticker Date: Wed, 16 Apr 2014 16:08:39 -0700 Subject: ARM: tegra: fix Venice2 SD card VQMMC supply VDDIO_SDMMC3 is the VQMMC (I/O) supply, not the VMMC (core) supply, for the SD slot on Venice2. Signed-off-by: Andrew Bresticker Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 87537f499875..6770e2bdf226 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -933,7 +933,7 @@ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; status = "okay"; bus-width = <4>; - vmmc-supply = <&vddio_sdmmc3>; + vqmmc-supply = <&vddio_sdmmc3>; }; sdhci@0,700b0600 { -- cgit v1.2.3 From c625d1c203941fad755eb4eb729db1f65d6e9836 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Fri, 20 Sep 2013 09:55:39 -0500 Subject: efi: x86: Handle arbitrary Unicode characters Instead of truncating UTF-16 assuming all characters is ASCII, properly convert it to UTF-8. Signed-off-by: H. Peter Anvin [ Bug and style fixes. ] Signed-off-by: Roy Franz Signed-off-by: Leif Lindholm Signed-off-by: Matt Fleming --- arch/x86/boot/compressed/eboot.c | 3 +- drivers/firmware/efi/efi-stub-helper.c | 87 ++++++++++++++++++++++++++-------- 2 files changed, 68 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c index 4703a6c4b8e3..0331d765c2bb 100644 --- a/arch/x86/boot/compressed/eboot.c +++ b/arch/x86/boot/compressed/eboot.c @@ -1087,8 +1087,7 @@ struct boot_params *make_boot_params(struct efi_config *c) hdr->type_of_loader = 0x21; /* Convert unicode cmdline to ascii */ - cmdline_ptr = efi_convert_cmdline_to_ascii(sys_table, image, - &options_size); + cmdline_ptr = efi_convert_cmdline(sys_table, image, &options_size); if (!cmdline_ptr) goto fail; hdr->cmd_line_ptr = (unsigned long)cmdline_ptr; diff --git a/drivers/firmware/efi/efi-stub-helper.c b/drivers/firmware/efi/efi-stub-helper.c index a168dd20511f..eb6d4be9e722 100644 --- a/drivers/firmware/efi/efi-stub-helper.c +++ b/drivers/firmware/efi/efi-stub-helper.c @@ -535,53 +535,100 @@ static efi_status_t efi_relocate_kernel(efi_system_table_t *sys_table_arg, return status; } +/* + * Get the number of UTF-8 bytes corresponding to an UTF-16 character. + * This overestimates for surrogates, but that is okay. + */ +static int efi_utf8_bytes(u16 c) +{ + return 1 + (c >= 0x80) + (c >= 0x800); +} + +/* + * Convert an UTF-16 string, not necessarily null terminated, to UTF-8. + */ +static u8 *efi_utf16_to_utf8(u8 *dst, const u16 *src, int n) +{ + unsigned int c; + + while (n--) { + c = *src++; + if (n && c >= 0xd800 && c <= 0xdbff && + *src >= 0xdc00 && *src <= 0xdfff) { + c = 0x10000 + ((c & 0x3ff) << 10) + (*src & 0x3ff); + src++; + n--; + } + if (c >= 0xd800 && c <= 0xdfff) + c = 0xfffd; /* Unmatched surrogate */ + if (c < 0x80) { + *dst++ = c; + continue; + } + if (c < 0x800) { + *dst++ = 0xc0 + (c >> 6); + goto t1; + } + if (c < 0x10000) { + *dst++ = 0xe0 + (c >> 12); + goto t2; + } + *dst++ = 0xf0 + (c >> 18); + *dst++ = 0x80 + ((c >> 12) & 0x3f); + t2: + *dst++ = 0x80 + ((c >> 6) & 0x3f); + t1: + *dst++ = 0x80 + (c & 0x3f); + } + + return dst; +} + /* * Convert the unicode UEFI command line to ASCII to pass to kernel. * Size of memory allocated return in *cmd_line_len. * Returns NULL on error. */ -static char *efi_convert_cmdline_to_ascii(efi_system_table_t *sys_table_arg, - efi_loaded_image_t *image, - int *cmd_line_len) +static char *efi_convert_cmdline(efi_system_table_t *sys_table_arg, + efi_loaded_image_t *image, + int *cmd_line_len) { - u16 *s2; + const u16 *s2; u8 *s1 = NULL; unsigned long cmdline_addr = 0; - int load_options_size = image->load_options_size / 2; /* ASCII */ - void *options = image->load_options; - int options_size = 0; + int load_options_chars = image->load_options_size / 2; /* UTF-16 */ + const u16 *options = image->load_options; + int options_bytes = 0; /* UTF-8 bytes */ + int options_chars = 0; /* UTF-16 chars */ efi_status_t status; - int i; u16 zero = 0; if (options) { s2 = options; - while (*s2 && *s2 != '\n' && options_size < load_options_size) { - s2++; - options_size++; + while (*s2 && *s2 != '\n' + && options_chars < load_options_chars) { + options_bytes += efi_utf8_bytes(*s2++); + options_chars++; } } - if (options_size == 0) { + if (!options_chars) { /* No command line options, so return empty string*/ - options_size = 1; options = &zero; } - options_size++; /* NUL termination */ + options_bytes++; /* NUL termination */ - status = efi_low_alloc(sys_table_arg, options_size, 0, &cmdline_addr); + status = efi_low_alloc(sys_table_arg, options_bytes, 0, &cmdline_addr); if (status != EFI_SUCCESS) return NULL; s1 = (u8 *)cmdline_addr; - s2 = (u16 *)options; - - for (i = 0; i < options_size - 1; i++) - *s1++ = *s2++; + s2 = (const u16 *)options; + s1 = efi_utf16_to_utf8(s1, s2, options_chars); *s1 = '\0'; - *cmd_line_len = options_size; + *cmd_line_len = options_bytes; return (char *)cmdline_addr; } -- cgit v1.2.3 From 62fa6e69a436f662090f3996538adb9e568817f6 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Thu, 27 Mar 2014 15:10:39 -0700 Subject: x86/efi: Delete most of the efi_call* macros We really only need one phys and one virt function call, and then only one assembly function to make firmware calls. Since we are not using the C type system anyway, we're not really losing much by deleting the macros apart from no longer having a check that we are passing the correct number of parameters. The lack of duplicated code seems like a worthwhile trade-off. Cc: Ricardo Neri Cc: Borislav Petkov Signed-off-by: Matt Fleming --- arch/x86/boot/compressed/head_64.S | 2 +- arch/x86/include/asm/efi.h | 74 ++++----------------------------- arch/x86/platform/efi/efi.c | 48 +++++++++++----------- arch/x86/platform/efi/efi_stub_64.S | 81 +------------------------------------ arch/x86/platform/uv/bios_uv.c | 2 +- 5 files changed, 35 insertions(+), 172 deletions(-) (limited to 'arch') diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 0d558ee899ae..2884e0c3e8a5 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S @@ -452,7 +452,7 @@ efi32_config: .global efi64_config efi64_config: .fill 11,8,0 - .quad efi_call6 + .quad efi_call .byte 1 #endif /* CONFIG_EFI_STUB */ diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index 0869434eaf72..e3975597b289 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -27,16 +27,6 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); -#define efi_call_phys0(f) efi_call_phys(f) -#define efi_call_phys1(f, a1) efi_call_phys(f, a1) -#define efi_call_phys2(f, a1, a2) efi_call_phys(f, a1, a2) -#define efi_call_phys3(f, a1, a2, a3) efi_call_phys(f, a1, a2, a3) -#define efi_call_phys4(f, a1, a2, a3, a4) \ - efi_call_phys(f, a1, a2, a3, a4) -#define efi_call_phys5(f, a1, a2, a3, a4, a5) \ - efi_call_phys(f, a1, a2, a3, a4, a5) -#define efi_call_phys6(f, a1, a2, a3, a4, a5, a6) \ - efi_call_phys(f, a1, a2, a3, a4, a5, a6) /* * Wrap all the virtual calls in a way that forces the parameters on the stack. */ @@ -44,75 +34,27 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); #define efi_call_virt(f, args...) \ ((efi_##f##_t __attribute__((regparm(0)))*)efi.systab->runtime->f)(args) -#define efi_call_virt0(f) efi_call_virt(f) -#define efi_call_virt1(f, a1) efi_call_virt(f, a1) -#define efi_call_virt2(f, a1, a2) efi_call_virt(f, a1, a2) -#define efi_call_virt3(f, a1, a2, a3) efi_call_virt(f, a1, a2, a3) -#define efi_call_virt4(f, a1, a2, a3, a4) \ - efi_call_virt(f, a1, a2, a3, a4) -#define efi_call_virt5(f, a1, a2, a3, a4, a5) \ - efi_call_virt(f, a1, a2, a3, a4, a5) -#define efi_call_virt6(f, a1, a2, a3, a4, a5, a6) \ - efi_call_virt(f, a1, a2, a3, a4, a5, a6) - #define efi_ioremap(addr, size, type, attr) ioremap_cache(addr, size) #else /* !CONFIG_X86_32 */ -extern u64 efi_call0(void *fp); -extern u64 efi_call1(void *fp, u64 arg1); -extern u64 efi_call2(void *fp, u64 arg1, u64 arg2); -extern u64 efi_call3(void *fp, u64 arg1, u64 arg2, u64 arg3); -extern u64 efi_call4(void *fp, u64 arg1, u64 arg2, u64 arg3, u64 arg4); -extern u64 efi_call5(void *fp, u64 arg1, u64 arg2, u64 arg3, - u64 arg4, u64 arg5); -extern u64 efi_call6(void *fp, u64 arg1, u64 arg2, u64 arg3, - u64 arg4, u64 arg5, u64 arg6); - -#define efi_call_phys0(f) \ - efi_call0((f)) -#define efi_call_phys1(f, a1) \ - efi_call1((f), (u64)(a1)) -#define efi_call_phys2(f, a1, a2) \ - efi_call2((f), (u64)(a1), (u64)(a2)) -#define efi_call_phys3(f, a1, a2, a3) \ - efi_call3((f), (u64)(a1), (u64)(a2), (u64)(a3)) -#define efi_call_phys4(f, a1, a2, a3, a4) \ - efi_call4((f), (u64)(a1), (u64)(a2), (u64)(a3), \ - (u64)(a4)) -#define efi_call_phys5(f, a1, a2, a3, a4, a5) \ - efi_call5((f), (u64)(a1), (u64)(a2), (u64)(a3), \ - (u64)(a4), (u64)(a5)) -#define efi_call_phys6(f, a1, a2, a3, a4, a5, a6) \ - efi_call6((f), (u64)(a1), (u64)(a2), (u64)(a3), \ - (u64)(a4), (u64)(a5), (u64)(a6)) - -#define _efi_call_virtX(x, f, ...) \ +#define EFI_LOADER_SIGNATURE "EL64" + +extern u64 asmlinkage efi_call(void *fp, ...); + +#define efi_call_phys(f, args...) efi_call((f), args) + +#define efi_call_virt(f, ...) \ ({ \ efi_status_t __s; \ \ efi_sync_low_kernel_mappings(); \ preempt_disable(); \ - __s = efi_call##x((void *)efi.systab->runtime->f, __VA_ARGS__); \ + __s = efi_call((void *)efi.systab->runtime->f, __VA_ARGS__); \ preempt_enable(); \ __s; \ }) -#define efi_call_virt0(f) \ - _efi_call_virtX(0, f) -#define efi_call_virt1(f, a1) \ - _efi_call_virtX(1, f, (u64)(a1)) -#define efi_call_virt2(f, a1, a2) \ - _efi_call_virtX(2, f, (u64)(a1), (u64)(a2)) -#define efi_call_virt3(f, a1, a2, a3) \ - _efi_call_virtX(3, f, (u64)(a1), (u64)(a2), (u64)(a3)) -#define efi_call_virt4(f, a1, a2, a3, a4) \ - _efi_call_virtX(4, f, (u64)(a1), (u64)(a2), (u64)(a3), (u64)(a4)) -#define efi_call_virt5(f, a1, a2, a3, a4, a5) \ - _efi_call_virtX(5, f, (u64)(a1), (u64)(a2), (u64)(a3), (u64)(a4), (u64)(a5)) -#define efi_call_virt6(f, a1, a2, a3, a4, a5, a6) \ - _efi_call_virtX(6, f, (u64)(a1), (u64)(a2), (u64)(a3), (u64)(a4), (u64)(a5), (u64)(a6)) - extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size, u32 type, u64 attribute); diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 3781dd39e8bd..8f6531e8d32f 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -110,7 +110,7 @@ static efi_status_t virt_efi_get_time(efi_time_t *tm, efi_time_cap_t *tc) efi_status_t status; spin_lock_irqsave(&rtc_lock, flags); - status = efi_call_virt2(get_time, tm, tc); + status = efi_call_virt(get_time, tm, tc); spin_unlock_irqrestore(&rtc_lock, flags); return status; } @@ -121,7 +121,7 @@ static efi_status_t virt_efi_set_time(efi_time_t *tm) efi_status_t status; spin_lock_irqsave(&rtc_lock, flags); - status = efi_call_virt1(set_time, tm); + status = efi_call_virt(set_time, tm); spin_unlock_irqrestore(&rtc_lock, flags); return status; } @@ -134,8 +134,7 @@ static efi_status_t virt_efi_get_wakeup_time(efi_bool_t *enabled, efi_status_t status; spin_lock_irqsave(&rtc_lock, flags); - status = efi_call_virt3(get_wakeup_time, - enabled, pending, tm); + status = efi_call_virt(get_wakeup_time, enabled, pending, tm); spin_unlock_irqrestore(&rtc_lock, flags); return status; } @@ -146,8 +145,7 @@ static efi_status_t virt_efi_set_wakeup_time(efi_bool_t enabled, efi_time_t *tm) efi_status_t status; spin_lock_irqsave(&rtc_lock, flags); - status = efi_call_virt2(set_wakeup_time, - enabled, tm); + status = efi_call_virt(set_wakeup_time, enabled, tm); spin_unlock_irqrestore(&rtc_lock, flags); return status; } @@ -158,17 +156,17 @@ static efi_status_t virt_efi_get_variable(efi_char16_t *name, unsigned long *data_size, void *data) { - return efi_call_virt5(get_variable, - name, vendor, attr, - data_size, data); + return efi_call_virt(get_variable, + name, vendor, attr, + data_size, data); } static efi_status_t virt_efi_get_next_variable(unsigned long *name_size, efi_char16_t *name, efi_guid_t *vendor) { - return efi_call_virt3(get_next_variable, - name_size, name, vendor); + return efi_call_virt(get_next_variable, + name_size, name, vendor); } static efi_status_t virt_efi_set_variable(efi_char16_t *name, @@ -177,9 +175,9 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name, unsigned long data_size, void *data) { - return efi_call_virt5(set_variable, - name, vendor, attr, - data_size, data); + return efi_call_virt(set_variable, + name, vendor, attr, + data_size, data); } static efi_status_t virt_efi_query_variable_info(u32 attr, @@ -190,13 +188,13 @@ static efi_status_t virt_efi_query_variable_info(u32 attr, if (efi.runtime_version < EFI_2_00_SYSTEM_TABLE_REVISION) return EFI_UNSUPPORTED; - return efi_call_virt4(query_variable_info, attr, storage_space, - remaining_space, max_variable_size); + return efi_call_virt(query_variable_info, attr, storage_space, + remaining_space, max_variable_size); } static efi_status_t virt_efi_get_next_high_mono_count(u32 *count) { - return efi_call_virt1(get_next_high_mono_count, count); + return efi_call_virt(get_next_high_mono_count, count); } static void virt_efi_reset_system(int reset_type, @@ -204,8 +202,8 @@ static void virt_efi_reset_system(int reset_type, unsigned long data_size, efi_char16_t *data) { - efi_call_virt4(reset_system, reset_type, status, - data_size, data); + efi_call_virt(reset_system, reset_type, status, + data_size, data); } static efi_status_t virt_efi_update_capsule(efi_capsule_header_t **capsules, @@ -215,7 +213,7 @@ static efi_status_t virt_efi_update_capsule(efi_capsule_header_t **capsules, if (efi.runtime_version < EFI_2_00_SYSTEM_TABLE_REVISION) return EFI_UNSUPPORTED; - return efi_call_virt3(update_capsule, capsules, count, sg_list); + return efi_call_virt(update_capsule, capsules, count, sg_list); } static efi_status_t virt_efi_query_capsule_caps(efi_capsule_header_t **capsules, @@ -226,8 +224,8 @@ static efi_status_t virt_efi_query_capsule_caps(efi_capsule_header_t **capsules, if (efi.runtime_version < EFI_2_00_SYSTEM_TABLE_REVISION) return EFI_UNSUPPORTED; - return efi_call_virt4(query_capsule_caps, capsules, count, max_size, - reset_type); + return efi_call_virt(query_capsule_caps, capsules, count, max_size, + reset_type); } static efi_status_t __init phys_efi_set_virtual_address_map( @@ -239,9 +237,9 @@ static efi_status_t __init phys_efi_set_virtual_address_map( efi_status_t status; efi_call_phys_prelog(); - status = efi_call_phys4(efi_phys.set_virtual_address_map, - memory_map_size, descriptor_size, - descriptor_version, virtual_map); + status = efi_call_phys(efi_phys.set_virtual_address_map, + memory_map_size, descriptor_size, + descriptor_version, virtual_map); efi_call_phys_epilog(); return status; } diff --git a/arch/x86/platform/efi/efi_stub_64.S b/arch/x86/platform/efi/efi_stub_64.S index e0984ef0374b..5fcda7272550 100644 --- a/arch/x86/platform/efi/efi_stub_64.S +++ b/arch/x86/platform/efi/efi_stub_64.S @@ -73,84 +73,7 @@ 2: .endm -ENTRY(efi_call0) - SAVE_XMM - subq $32, %rsp - SWITCH_PGT - call *%rdi - RESTORE_PGT - addq $32, %rsp - RESTORE_XMM - ret -ENDPROC(efi_call0) - -ENTRY(efi_call1) - SAVE_XMM - subq $32, %rsp - mov %rsi, %rcx - SWITCH_PGT - call *%rdi - RESTORE_PGT - addq $32, %rsp - RESTORE_XMM - ret -ENDPROC(efi_call1) - -ENTRY(efi_call2) - SAVE_XMM - subq $32, %rsp - mov %rsi, %rcx - SWITCH_PGT - call *%rdi - RESTORE_PGT - addq $32, %rsp - RESTORE_XMM - ret -ENDPROC(efi_call2) - -ENTRY(efi_call3) - SAVE_XMM - subq $32, %rsp - mov %rcx, %r8 - mov %rsi, %rcx - SWITCH_PGT - call *%rdi - RESTORE_PGT - addq $32, %rsp - RESTORE_XMM - ret -ENDPROC(efi_call3) - -ENTRY(efi_call4) - SAVE_XMM - subq $32, %rsp - mov %r8, %r9 - mov %rcx, %r8 - mov %rsi, %rcx - SWITCH_PGT - call *%rdi - RESTORE_PGT - addq $32, %rsp - RESTORE_XMM - ret -ENDPROC(efi_call4) - -ENTRY(efi_call5) - SAVE_XMM - subq $48, %rsp - mov %r9, 32(%rsp) - mov %r8, %r9 - mov %rcx, %r8 - mov %rsi, %rcx - SWITCH_PGT - call *%rdi - RESTORE_PGT - addq $48, %rsp - RESTORE_XMM - ret -ENDPROC(efi_call5) - -ENTRY(efi_call6) +ENTRY(efi_call) SAVE_XMM mov (%rsp), %rax mov 8(%rax), %rax @@ -166,7 +89,7 @@ ENTRY(efi_call6) addq $48, %rsp RESTORE_XMM ret -ENDPROC(efi_call6) +ENDPROC(efi_call) #ifdef CONFIG_EFI_MIXED diff --git a/arch/x86/platform/uv/bios_uv.c b/arch/x86/platform/uv/bios_uv.c index 766612137a62..1584cbed0dce 100644 --- a/arch/x86/platform/uv/bios_uv.c +++ b/arch/x86/platform/uv/bios_uv.c @@ -39,7 +39,7 @@ s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5) */ return BIOS_STATUS_UNIMPLEMENTED; - ret = efi_call6((void *)__va(tab->function), (u64)which, + ret = efi_call((void *)__va(tab->function), (u64)which, a1, a2, a3, a4, a5); return ret; } -- cgit v1.2.3 From c6b406919288a617815f710175da20f3fca72065 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Thu, 27 Mar 2014 15:10:40 -0700 Subject: x86, fpu: Extend the use of static_cpu_has_safe It may be necessary to save and restore the FPU context during EFI runtime system services calls. However, this may happen during boot and before alternatives have run. Thus, we need to use static_cpu_has_safe instead. The rationale behind the use of static_cpu_has_safe is the same as in commit 5f8c4218148822fde6ee ("x86, fpu: Use static_cpu_has_safe before alternatives") by Borislav Petkov. Signed-off-by: Matt Fleming Signed-off-by: Ricardo Neri Cc: Borislav Petkov --- arch/x86/include/asm/fpu-internal.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h index cea1c76d49bf..115e3689cd53 100644 --- a/arch/x86/include/asm/fpu-internal.h +++ b/arch/x86/include/asm/fpu-internal.h @@ -87,22 +87,22 @@ static inline int is_x32_frame(void) static __always_inline __pure bool use_eager_fpu(void) { - return static_cpu_has(X86_FEATURE_EAGER_FPU); + return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); } static __always_inline __pure bool use_xsaveopt(void) { - return static_cpu_has(X86_FEATURE_XSAVEOPT); + return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); } static __always_inline __pure bool use_xsave(void) { - return static_cpu_has(X86_FEATURE_XSAVE); + return static_cpu_has_safe(X86_FEATURE_XSAVE); } static __always_inline __pure bool use_fxsr(void) { - return static_cpu_has(X86_FEATURE_FXSR); + return static_cpu_has_safe(X86_FEATURE_FXSR); } static inline void fx_finit(struct i387_fxsave_struct *fx) @@ -293,7 +293,7 @@ static inline int restore_fpu_checking(struct task_struct *tsk) /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is pending. Clear the x87 state here by setting it to fixed values. "m" is a random variable that should be in L1 */ - if (unlikely(static_cpu_has(X86_FEATURE_FXSAVE_LEAK))) { + if (unlikely(static_cpu_has_safe(X86_FEATURE_FXSAVE_LEAK))) { asm volatile( "fnclex\n\t" "emms\n\t" -- cgit v1.2.3 From 982e239cd2c73d2c70e14615a42c0c7391415a44 Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Thu, 27 Mar 2014 15:10:41 -0700 Subject: x86/efi: Implement a __efi_call_virt macro For i386, all the EFI system runtime services functions return efi_status_t except efi_reset_system_system. Therefore, not all functions can be covered by the same macro in case the macro needs to do more than calling the function (i.e., return a value). The purpose of the __efi_call_virt macro is to be used when no return value is expected. For x86_64, this macro would not be needed as all the runtime services return u64. However, the same code is used for both x86_64 and i386. Thus, the macro __efi_call_virt is also defined to not break compilation. Signed-off-by: Ricardo Neri Cc: Borislav Petkov Signed-off-by: Matt Fleming --- arch/x86/include/asm/efi.h | 10 ++++++++++ arch/x86/platform/efi/efi.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index e3975597b289..19292e7cae58 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -31,9 +31,13 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); * Wrap all the virtual calls in a way that forces the parameters on the stack. */ +/* Use this macro if your virtual returns a non-void value */ #define efi_call_virt(f, args...) \ ((efi_##f##_t __attribute__((regparm(0)))*)efi.systab->runtime->f)(args) +/* Use this macro if your virtual call does not return any value */ +#define __efi_call_virt(f, args...) efi_call_virt(f, args) + #define efi_ioremap(addr, size, type, attr) ioremap_cache(addr, size) #else /* !CONFIG_X86_32 */ @@ -55,6 +59,12 @@ extern u64 asmlinkage efi_call(void *fp, ...); __s; \ }) +/* + * All X86_64 virt calls return non-void values. Thus, use non-void call for + * virt calls that would be void on X86_32. + */ +#define __efi_call_virt(f, args...) efi_call_virt(f, args) + extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size, u32 type, u64 attribute); diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c index 8f6531e8d32f..835b24820eaa 100644 --- a/arch/x86/platform/efi/efi.c +++ b/arch/x86/platform/efi/efi.c @@ -202,8 +202,8 @@ static void virt_efi_reset_system(int reset_type, unsigned long data_size, efi_char16_t *data) { - efi_call_virt(reset_system, reset_type, status, - data_size, data); + __efi_call_virt(reset_system, reset_type, status, + data_size, data); } static efi_status_t virt_efi_update_capsule(efi_capsule_header_t **capsules, -- cgit v1.2.3 From de05764e0b2a3d9559e099a2e134f8cef4500fdd Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Thu, 27 Mar 2014 15:10:42 -0700 Subject: x86/efi: Save and restore FPU context around efi_calls (x86_64) Do a complete FPU context save/restore around the EFI calls. This required as runtime EFI firmware may potentially use the FPU. This change covers only the x86_64 configuration. Signed-off-by: Ricardo Neri Cc: Borislav Petkov Signed-off-by: Matt Fleming --- arch/x86/include/asm/efi.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index 19292e7cae58..0b19187cc882 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -1,6 +1,7 @@ #ifndef _ASM_X86_EFI_H #define _ASM_X86_EFI_H +#include /* * We map the EFI regions needed for runtime services non-contiguously, * with preserved alignment on virtual addresses starting from -4G down @@ -54,7 +55,9 @@ extern u64 asmlinkage efi_call(void *fp, ...); \ efi_sync_low_kernel_mappings(); \ preempt_disable(); \ + __kernel_fpu_begin(); \ __s = efi_call((void *)efi.systab->runtime->f, __VA_ARGS__); \ + __kernel_fpu_end(); \ preempt_enable(); \ __s; \ }) -- cgit v1.2.3 From b738c6ea49b4e98e6ca0651da82a610f996a16ae Mon Sep 17 00:00:00 2001 From: Ricardo Neri Date: Thu, 27 Mar 2014 15:10:43 -0700 Subject: x86/efi: Save and restore FPU context around efi_calls (i386) Do a complete FPU context save/restore around the EFI calls. This required as runtime EFI firmware may potentially use the FPU. This change covers only the i386 configuration. Signed-off-by: Ricardo Neri Cc: Borislav Petkov Signed-off-by: Matt Fleming --- arch/x86/include/asm/efi.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index 0b19187cc882..1eb5f6433ad8 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -34,10 +34,23 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); /* Use this macro if your virtual returns a non-void value */ #define efi_call_virt(f, args...) \ - ((efi_##f##_t __attribute__((regparm(0)))*)efi.systab->runtime->f)(args) +({ \ + efi_status_t __s; \ + kernel_fpu_begin(); \ + __s = ((efi_##f##_t __attribute__((regparm(0)))*) \ + efi.systab->runtime->f)(args); \ + kernel_fpu_end(); \ + __s; \ +}) /* Use this macro if your virtual call does not return any value */ -#define __efi_call_virt(f, args...) efi_call_virt(f, args) +#define __efi_call_virt(f, args...) \ +({ \ + kernel_fpu_begin(); \ + ((efi_##f##_t __attribute__((regparm(0)))*) \ + efi.systab->runtime->f)(args); \ + kernel_fpu_end(); \ +}) #define efi_ioremap(addr, size, type, attr) ioremap_cache(addr, size) -- cgit v1.2.3 From f848a5a8dcb655553423f77cc98909a04e64173d Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Mon, 31 Mar 2014 21:50:38 +0300 Subject: KVM: support any-length wildcard ioeventfd It is sometimes benefitial to ignore IO size, and only match on address. In hindsight this would have been a better default than matching length when KVM_IOEVENTFD_FLAG_DATAMATCH is not set, In particular, this kind of access can be optimized on VMX: there no need to do page lookups. This can currently be done with many ioeventfds but in a suboptimal way. However we can't change kernel/userspace ABI without risk of breaking some applications. Use len = 0 to mean "ignore length for matching" in a more optimal way. Signed-off-by: Michael S. Tsirkin Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/x86.c | 1 + include/uapi/linux/kvm.h | 3 ++- virt/kvm/eventfd.c | 27 ++++++++++++++++++++++----- 3 files changed, 25 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 8b8fc0b792ba..bc4aaf68190c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2644,6 +2644,7 @@ int kvm_dev_ioctl_check_extension(long ext) case KVM_CAP_IRQ_INJECT_STATUS: case KVM_CAP_IRQFD: case KVM_CAP_IOEVENTFD: + case KVM_CAP_IOEVENTFD_NO_LENGTH: case KVM_CAP_PIT2: case KVM_CAP_PIT_STATE2: case KVM_CAP_SET_IDENTITY_MAP_ADDR: diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index a8f4ee5d2e82..39098a61f41c 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -529,7 +529,7 @@ enum { struct kvm_ioeventfd { __u64 datamatch; __u64 addr; /* legal pio/mmio address */ - __u32 len; /* 1, 2, 4, or 8 bytes */ + __u32 len; /* 1, 2, 4, or 8 bytes; or 0 to ignore length */ __s32 fd; __u32 flags; __u8 pad[36]; @@ -743,6 +743,7 @@ struct kvm_ppc_smmu_info { #define KVM_CAP_IOAPIC_POLARITY_IGNORED 97 #define KVM_CAP_ENABLE_CAP_VM 98 #define KVM_CAP_S390_IRQCHIP 99 +#define KVM_CAP_IOEVENTFD_NO_LENGTH 100 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/virt/kvm/eventfd.c b/virt/kvm/eventfd.c index 29c2a04e036e..2721996bb9c2 100644 --- a/virt/kvm/eventfd.c +++ b/virt/kvm/eventfd.c @@ -600,7 +600,15 @@ ioeventfd_in_range(struct _ioeventfd *p, gpa_t addr, int len, const void *val) { u64 _val; - if (!(addr == p->addr && len == p->length)) + if (addr != p->addr) + /* address must be precise for a hit */ + return false; + + if (!p->length) + /* length = 0 means only look at the address, so always a hit */ + return true; + + if (len != p->length) /* address-range must be precise for a hit */ return false; @@ -671,9 +679,11 @@ ioeventfd_check_collision(struct kvm *kvm, struct _ioeventfd *p) list_for_each_entry(_p, &kvm->ioeventfds, list) if (_p->bus_idx == p->bus_idx && - _p->addr == p->addr && _p->length == p->length && - (_p->wildcard || p->wildcard || - _p->datamatch == p->datamatch)) + _p->addr == p->addr && + (!_p->length || !p->length || + (_p->length == p->length && + (_p->wildcard || p->wildcard || + _p->datamatch == p->datamatch)))) return true; return false; @@ -697,8 +707,9 @@ kvm_assign_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args) int ret; bus_idx = ioeventfd_bus_from_flags(args->flags); - /* must be natural-word sized */ + /* must be natural-word sized, or 0 to ignore length */ switch (args->len) { + case 0: case 1: case 2: case 4: @@ -716,6 +727,12 @@ kvm_assign_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args) if (args->flags & ~KVM_IOEVENTFD_VALID_FLAG_MASK) return -EINVAL; + /* ioeventfd with no length can't be combined with DATAMATCH */ + if (!args->len && + args->flags & (KVM_IOEVENTFD_FLAG_PIO | + KVM_IOEVENTFD_FLAG_DATAMATCH)) + return -EINVAL; + eventfd = eventfd_ctx_fdget(args->fd); if (IS_ERR(eventfd)) return PTR_ERR(eventfd); -- cgit v1.2.3 From 68c3b4d1676d870f0453c31d5a52e7e65c7448ae Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Mon, 31 Mar 2014 21:50:44 +0300 Subject: KVM: VMX: speed up wildcard MMIO EVENTFD With KVM, MMIO is much slower than PIO, due to the need to do page walk and emulation. But with EPT, it does not have to be: we know the address from the VMCS so if the address is unique, we can look up the eventfd directly, bypassing emulation. Unfortunately, this only works if userspace does not need to match on access length and data. The implementation adds a separate FAST_MMIO bus internally. This serves two purposes: - minimize overhead for old userspace that does not use eventfd with lengtth = 0 - minimize disruption in other code (since we don't know the length, devices on the MMIO bus only get a valid address in write, this way we don't need to touch all devices to teach them to handle an invalid length) At the moment, this optimization only has effect for EPT on x86. It will be possible to speed up MMIO for NPT and MMU using the same idea in the future. With this patch applied, on VMX MMIO EVENTFD is essentially as fast as PIO. I was unable to detect any measureable slowdown to non-eventfd MMIO. Making MMIO faster is important for the upcoming virtio 1.0 which includes an MMIO signalling capability. The idea was suggested by Peter Anvin. Lots of thanks to Gleb for pre-review and suggestions. Signed-off-by: Michael S. Tsirkin Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/vmx.c | 4 ++++ include/linux/kvm_host.h | 1 + include/uapi/linux/kvm.h | 1 + virt/kvm/eventfd.c | 16 ++++++++++++++++ virt/kvm/kvm_main.c | 1 + 5 files changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 1f68c5831924..eb3f2b1b764c 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -5528,6 +5528,10 @@ static int handle_ept_misconfig(struct kvm_vcpu *vcpu) gpa_t gpa; gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); + if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { + skip_emulated_instruction(vcpu); + return 1; + } ret = handle_mmio_page_fault_common(vcpu, gpa, true); if (likely(ret == RET_MMIO_PF_EMULATE)) diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 7d21cf9f4380..6c3c2eb96d06 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -163,6 +163,7 @@ enum kvm_bus { KVM_MMIO_BUS, KVM_PIO_BUS, KVM_VIRTIO_CCW_NOTIFY_BUS, + KVM_FAST_MMIO_BUS, KVM_NR_BUSES }; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 39098a61f41c..d8a6ce4c2a83 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -515,6 +515,7 @@ enum { kvm_ioeventfd_flag_nr_pio, kvm_ioeventfd_flag_nr_deassign, kvm_ioeventfd_flag_nr_virtio_ccw_notify, + kvm_ioeventfd_flag_nr_fast_mmio, kvm_ioeventfd_flag_nr_max, }; diff --git a/virt/kvm/eventfd.c b/virt/kvm/eventfd.c index 2721996bb9c2..912ec5a95e2c 100644 --- a/virt/kvm/eventfd.c +++ b/virt/kvm/eventfd.c @@ -770,6 +770,16 @@ kvm_assign_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args) if (ret < 0) goto unlock_fail; + /* When length is ignored, MMIO is also put on a separate bus, for + * faster lookups. + */ + if (!args->len && !(args->flags & KVM_IOEVENTFD_FLAG_PIO)) { + ret = kvm_io_bus_register_dev(kvm, KVM_FAST_MMIO_BUS, + p->addr, 0, &p->dev); + if (ret < 0) + goto register_fail; + } + kvm->buses[bus_idx]->ioeventfd_count++; list_add_tail(&p->list, &kvm->ioeventfds); @@ -777,6 +787,8 @@ kvm_assign_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args) return 0; +register_fail: + kvm_io_bus_unregister_dev(kvm, bus_idx, &p->dev); unlock_fail: mutex_unlock(&kvm->slots_lock); @@ -816,6 +828,10 @@ kvm_deassign_ioeventfd(struct kvm *kvm, struct kvm_ioeventfd *args) continue; kvm_io_bus_unregister_dev(kvm, bus_idx, &p->dev); + if (!p->length) { + kvm_io_bus_unregister_dev(kvm, KVM_FAST_MMIO_BUS, + &p->dev); + } kvm->buses[bus_idx]->ioeventfd_count--; ioeventfd_release(p); ret = 0; diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 56baae8c2f56..96456ac888ba 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -2922,6 +2922,7 @@ static int __kvm_io_bus_read(struct kvm_io_bus *bus, struct kvm_io_range *range, return -EOPNOTSUPP; } +EXPORT_SYMBOL_GPL(kvm_io_bus_write); /* kvm_io_bus_read - called under kvm->slots_lock */ int kvm_io_bus_read(struct kvm *kvm, enum kvm_bus bus_idx, gpa_t addr, -- cgit v1.2.3 From ddb69f276c4af8bb47ad4f24a72f72ddf58c228a Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 31 Mar 2014 15:16:22 +0200 Subject: uprobes/x86: Fold prepare_fixups() into arch_uprobe_analyze_insn() No functional changes, preparation. Shift the code from prepare_fixups() to arch_uprobe_analyze_insn() with the following modifications: - Do not call insn_get_opcode() again, it was already called by validate_insn_bits(). - Move "case 0xea" up. This way "case 0xff" can fall through to default case. - change "case 0xff" to use the nested "switch (MODRM_REG)", this way the code looks a bit simpler. - Make the comments look consistent. While at it, kill the initialization of rip_rela_target_address and ->fixups, we can rely on kzalloc(). We will add the new members into arch_uprobe, it would be better to assume that everything is zero by default. TODO: cleanup/fix the mess in validate_insn_bits() paths: - validate_insn_64bits() and validate_insn_32bits() should be unified. - "ifdef" is not used consistently; if good_insns_64 depends on CONFIG_X86_64, then probably good_insns_32 should depend on CONFIG_X86_32/EMULATION - the usage of mm->context.ia32_compat looks wrong if the task is TIF_X32. Signed-off-by: Oleg Nesterov Reviewed-by: Masami Hiramatsu Reviewed-by: Jim Keniston Acked-by: Srikar Dronamraju --- arch/x86/kernel/uprobes.c | 110 ++++++++++++++++++++-------------------------- 1 file changed, 47 insertions(+), 63 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 2ed845928b5f..098e56ec7954 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -53,7 +53,7 @@ #define OPCODE1(insn) ((insn)->opcode.bytes[0]) #define OPCODE2(insn) ((insn)->opcode.bytes[1]) #define OPCODE3(insn) ((insn)->opcode.bytes[2]) -#define MODRM_REG(insn) X86_MODRM_REG(insn->modrm.value) +#define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ @@ -229,63 +229,6 @@ static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn) return -ENOTSUPP; } -/* - * Figure out which fixups arch_uprobe_post_xol() will need to perform, and - * annotate arch_uprobe->fixups accordingly. To start with, - * arch_uprobe->fixups is either zero or it reflects rip-related fixups. - */ -static void prepare_fixups(struct arch_uprobe *auprobe, struct insn *insn) -{ - bool fix_ip = true, fix_call = false; /* defaults */ - int reg; - - insn_get_opcode(insn); /* should be a nop */ - - switch (OPCODE1(insn)) { - case 0x9d: - /* popf */ - auprobe->fixups |= UPROBE_FIX_SETF; - break; - case 0xc3: /* ret/lret */ - case 0xcb: - case 0xc2: - case 0xca: - /* ip is correct */ - fix_ip = false; - break; - case 0xe8: /* call relative - Fix return addr */ - fix_call = true; - break; - case 0x9a: /* call absolute - Fix return addr, not ip */ - fix_call = true; - fix_ip = false; - break; - case 0xff: - insn_get_modrm(insn); - reg = MODRM_REG(insn); - if (reg == 2 || reg == 3) { - /* call or lcall, indirect */ - /* Fix return addr; ip is correct. */ - fix_call = true; - fix_ip = false; - } else if (reg == 4 || reg == 5) { - /* jmp or ljmp, indirect */ - /* ip is correct. */ - fix_ip = false; - } - break; - case 0xea: /* jmp absolute -- ip is correct */ - fix_ip = false; - break; - default: - break; - } - if (fix_ip) - auprobe->fixups |= UPROBE_FIX_IP; - if (fix_call) - auprobe->fixups |= UPROBE_FIX_CALL; -} - #ifdef CONFIG_X86_64 /* * If arch_uprobe->insn doesn't use rip-relative addressing, return @@ -318,7 +261,6 @@ handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct ins if (mm->context.ia32_compat) return; - auprobe->rip_rela_target_address = 0x0; if (!insn_rip_relative(insn)) return; @@ -421,16 +363,58 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, */ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) { - int ret; struct insn insn; + bool fix_ip = true, fix_call = false; + int ret; - auprobe->fixups = 0; ret = validate_insn_bits(auprobe, mm, &insn); - if (ret != 0) + if (ret) return ret; + /* + * Figure out which fixups arch_uprobe_post_xol() will need to perform, + * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups + * is either zero or it reflects rip-related fixups. + */ handle_riprel_insn(auprobe, mm, &insn); - prepare_fixups(auprobe, &insn); + + switch (OPCODE1(&insn)) { + case 0x9d: /* popf */ + auprobe->fixups |= UPROBE_FIX_SETF; + break; + case 0xc3: /* ret or lret -- ip is correct */ + case 0xcb: + case 0xc2: + case 0xca: + fix_ip = false; + break; + case 0xe8: /* call relative - Fix return addr */ + fix_call = true; + break; + case 0x9a: /* call absolute - Fix return addr, not ip */ + fix_call = true; + fix_ip = false; + break; + case 0xea: /* jmp absolute -- ip is correct */ + fix_ip = false; + break; + case 0xff: + insn_get_modrm(&insn); + switch (MODRM_REG(&insn)) { + case 2: case 3: /* call or lcall, indirect */ + fix_call = true; + case 4: case 5: /* jmp or ljmp, indirect */ + fix_ip = false; + } + break; + default: + break; + } + + if (fix_ip) + auprobe->fixups |= UPROBE_FIX_IP; + if (fix_call) + auprobe->fixups |= UPROBE_FIX_CALL; return 0; } -- cgit v1.2.3 From 59078d4b96bb548f97d9fb429b929a289e4884d9 Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 31 Mar 2014 18:09:36 +0200 Subject: uprobes/x86: Kill the "ia32_compat" check in handle_riprel_insn(), remove "mm" arg Kill the "mm->context.ia32_compat" check in handle_riprel_insn(), if it is true insn_rip_relative() must return false. validate_insn_bits() passed "ia32_compat" as !x86_64 to insn_init(), and insn_rip_relative() checks insn->x86_64. Also, remove the no longer needed "struct mm_struct *mm" argument and the unnecessary "return" at the end. Signed-off-by: Oleg Nesterov Reviewed-by: Masami Hiramatsu Reviewed-by: Jim Keniston Acked-by: Srikar Dronamraju --- arch/x86/kernel/uprobes.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 098e56ec7954..963c121c0307 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -253,14 +253,11 @@ static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn) * - The displacement is always 4 bytes. */ static void -handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) +handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) { u8 *cursor; u8 reg; - if (mm->context.ia32_compat) - return; - if (!insn_rip_relative(insn)) return; @@ -314,7 +311,6 @@ handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct ins cursor++; memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes); } - return; } static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn) @@ -343,7 +339,7 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, return validate_insn_64bits(auprobe, insn); } #else /* 32-bit: */ -static void handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) +static void handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) { /* No RIP-relative addressing on 32-bit */ } @@ -376,7 +372,7 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups * is either zero or it reflects rip-related fixups. */ - handle_riprel_insn(auprobe, mm, &insn); + handle_riprel_insn(auprobe, &insn); switch (OPCODE1(&insn)) { case 0x9d: /* popf */ -- cgit v1.2.3 From d20737c07a1063d681fe9fb86f3da369da1edab7 Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 31 Mar 2014 18:35:09 +0200 Subject: uprobes/x86: Gather "riprel" functions together Cosmetic. Move pre_xol_rip_insn() and handle_riprel_post_xol() up to the closely related handle_riprel_insn(). This way it is simpler to read and understand this code, and this lessens the number of ifdef's. While at it, update the comment in handle_riprel_post_xol() as Jim suggested. TODO: rename them somehow to make the naming consistent. Signed-off-by: Oleg Nesterov Reviewed-by: Masami Hiramatsu Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 118 +++++++++++++++++++++------------------------- 1 file changed, 53 insertions(+), 65 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 963c121c0307..c52c30fa7871 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -313,6 +313,48 @@ handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) } } +/* + * If we're emulating a rip-relative instruction, save the contents + * of the scratch register and store the target address in that register. + */ +static void +pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, + struct arch_uprobe_task *autask) +{ + if (auprobe->fixups & UPROBE_FIX_RIP_AX) { + autask->saved_scratch_register = regs->ax; + regs->ax = current->utask->vaddr; + regs->ax += auprobe->rip_rela_target_address; + } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) { + autask->saved_scratch_register = regs->cx; + regs->cx = current->utask->vaddr; + regs->cx += auprobe->rip_rela_target_address; + } +} + +static void +handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction) +{ + if (auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) { + struct arch_uprobe_task *autask; + + autask = ¤t->utask->autask; + if (auprobe->fixups & UPROBE_FIX_RIP_AX) + regs->ax = autask->saved_scratch_register; + else + regs->cx = autask->saved_scratch_register; + + /* + * The original instruction includes a displacement, and so + * is 4 bytes longer than what we've just single-stepped. + * Caller may need to apply other fixups to handle stuff + * like "jmpq *...(%rip)" and "callq *...(%rip)". + */ + if (correction) + *correction += 4; + } +} + static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn) { insn_init(insn, auprobe->insn, true); @@ -339,9 +381,19 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, return validate_insn_64bits(auprobe, insn); } #else /* 32-bit: */ +/* + * No RIP-relative addressing on 32-bit + */ static void handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) { - /* No RIP-relative addressing on 32-bit */ +} +static void pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, + struct arch_uprobe_task *autask) +{ +} +static void handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, + long *correction) +{ } static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) @@ -415,34 +467,6 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, return 0; } -#ifdef CONFIG_X86_64 -/* - * If we're emulating a rip-relative instruction, save the contents - * of the scratch register and store the target address in that register. - */ -static void -pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, - struct arch_uprobe_task *autask) -{ - if (auprobe->fixups & UPROBE_FIX_RIP_AX) { - autask->saved_scratch_register = regs->ax; - regs->ax = current->utask->vaddr; - regs->ax += auprobe->rip_rela_target_address; - } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) { - autask->saved_scratch_register = regs->cx; - regs->cx = current->utask->vaddr; - regs->cx += auprobe->rip_rela_target_address; - } -} -#else -static void -pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, - struct arch_uprobe_task *autask) -{ - /* No RIP-relative addressing on 32-bit */ -} -#endif - /* * arch_uprobe_pre_xol - prepare to execute out of line. * @auprobe: the probepoint information. @@ -492,42 +516,6 @@ static int adjust_ret_addr(unsigned long sp, long correction) return 0; } -#ifdef CONFIG_X86_64 -static bool is_riprel_insn(struct arch_uprobe *auprobe) -{ - return ((auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) != 0); -} - -static void -handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction) -{ - if (is_riprel_insn(auprobe)) { - struct arch_uprobe_task *autask; - - autask = ¤t->utask->autask; - if (auprobe->fixups & UPROBE_FIX_RIP_AX) - regs->ax = autask->saved_scratch_register; - else - regs->cx = autask->saved_scratch_register; - - /* - * The original instruction includes a displacement, and so - * is 4 bytes longer than what we've just single-stepped. - * Fall through to handle stuff like "jmpq *...(%rip)" and - * "callq *...(%rip)". - */ - if (correction) - *correction += 4; - } -} -#else -static void -handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction) -{ - /* No RIP-relative addressing on 32-bit */ -} -#endif - /* * If xol insn itself traps and generates a signal(Say, * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped -- cgit v1.2.3 From 34e7317d6ae8f6111ac449444f22e14f4a14ebfd Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 31 Mar 2014 19:38:09 +0200 Subject: uprobes/x86: move the UPROBE_FIX_{RIP,IP,CALL} code at the end of pre/post hooks No functional changes. Preparation to simplify the review of the next change. Just reorder the code in arch_uprobe_pre/post_xol() functions so that UPROBE_FIX_{RIP_*,IP,CALL} logic goes to the end. Also change arch_uprobe_pre_xol() to use utask instead of autask, to make the code more symmetrical with arch_uprobe_post_xol(). Signed-off-by: Oleg Nesterov Reviewed-by: Masami Hiramatsu Reviewed-by: Jim Keniston Acked-by: Srikar Dronamraju --- arch/x86/kernel/uprobes.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index c52c30fa7871..3bb4198aa588 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -474,19 +474,18 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, */ int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) { - struct arch_uprobe_task *autask; + struct uprobe_task *utask = current->utask; - autask = ¤t->utask->autask; - autask->saved_trap_nr = current->thread.trap_nr; + regs->ip = utask->xol_vaddr; + utask->autask.saved_trap_nr = current->thread.trap_nr; current->thread.trap_nr = UPROBE_TRAP_NR; - regs->ip = current->utask->xol_vaddr; - pre_xol_rip_insn(auprobe, regs, autask); - autask->saved_tf = !!(regs->flags & X86_EFLAGS_TF); + utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); regs->flags |= X86_EFLAGS_TF; if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) set_task_blockstep(current, false); + pre_xol_rip_insn(auprobe, regs, &utask->autask); return 0; } @@ -560,22 +559,13 @@ bool arch_uprobe_xol_was_trapped(struct task_struct *t) */ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) { - struct uprobe_task *utask; + struct uprobe_task *utask = current->utask; long correction; int result = 0; WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); - utask = current->utask; current->thread.trap_nr = utask->autask.saved_trap_nr; - correction = (long)(utask->vaddr - utask->xol_vaddr); - handle_riprel_post_xol(auprobe, regs, &correction); - if (auprobe->fixups & UPROBE_FIX_IP) - regs->ip += correction; - - if (auprobe->fixups & UPROBE_FIX_CALL) - result = adjust_ret_addr(regs->sp, correction); - /* * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP * so we can get an extra SIGTRAP if we do not clear TF. We need @@ -586,6 +576,14 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) else if (!(auprobe->fixups & UPROBE_FIX_SETF)) regs->flags &= ~X86_EFLAGS_TF; + correction = (long)(utask->vaddr - utask->xol_vaddr); + handle_riprel_post_xol(auprobe, regs, &correction); + if (auprobe->fixups & UPROBE_FIX_IP) + regs->ip += correction; + + if (auprobe->fixups & UPROBE_FIX_CALL) + result = adjust_ret_addr(regs->sp, correction); + return result; } -- cgit v1.2.3 From 8ad8e9d3fd64f101eed6652964670672d699e563 Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 31 Mar 2014 21:01:31 +0200 Subject: uprobes/x86: Introduce uprobe_xol_ops and arch_uprobe->ops Introduce arch_uprobe->ops pointing to the "struct uprobe_xol_ops", move the current UPROBE_FIX_{RIP*,IP,CALL} code into the default set of methods and change arch_uprobe_pre/post_xol() accordingly. This way we can add the new uprobe_xol_ops's to handle the insns which need the special processing (rip-relative jmp/call at least). Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston Reviewed-by: Masami Hiramatsu --- arch/x86/include/asm/uprobes.h | 7 ++- arch/x86/kernel/uprobes.c | 107 ++++++++++++++++++++++++++--------------- 2 files changed, 74 insertions(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h index 3087ea9c5f2e..9f8210bcbb49 100644 --- a/arch/x86/include/asm/uprobes.h +++ b/arch/x86/include/asm/uprobes.h @@ -33,12 +33,17 @@ typedef u8 uprobe_opcode_t; #define UPROBE_SWBP_INSN 0xcc #define UPROBE_SWBP_INSN_SIZE 1 +struct uprobe_xol_ops; + struct arch_uprobe { - u16 fixups; union { u8 insn[MAX_UINSN_BYTES]; u8 ixol[MAX_UINSN_BYTES]; }; + + u16 fixups; + const struct uprobe_xol_ops *ops; + #ifdef CONFIG_X86_64 unsigned long rip_rela_target_address; #endif diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 3bb4198aa588..13ad8a38c2d9 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -402,6 +402,64 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, } #endif /* CONFIG_X86_64 */ +struct uprobe_xol_ops { + bool (*emulate)(struct arch_uprobe *, struct pt_regs *); + int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); + int (*post_xol)(struct arch_uprobe *, struct pt_regs *); +}; + +static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + pre_xol_rip_insn(auprobe, regs, ¤t->utask->autask); + return 0; +} + +/* + * Adjust the return address pushed by a call insn executed out of line. + */ +static int adjust_ret_addr(unsigned long sp, long correction) +{ + int rasize, ncopied; + long ra = 0; + + if (is_ia32_task()) + rasize = 4; + else + rasize = 8; + + ncopied = copy_from_user(&ra, (void __user *)sp, rasize); + if (unlikely(ncopied)) + return -EFAULT; + + ra += correction; + ncopied = copy_to_user((void __user *)sp, &ra, rasize); + if (unlikely(ncopied)) + return -EFAULT; + + return 0; +} + +static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + struct uprobe_task *utask = current->utask; + long correction = (long)(utask->vaddr - utask->xol_vaddr); + int ret = 0; + + handle_riprel_post_xol(auprobe, regs, &correction); + if (auprobe->fixups & UPROBE_FIX_IP) + regs->ip += correction; + + if (auprobe->fixups & UPROBE_FIX_CALL) + ret = adjust_ret_addr(regs->sp, correction); + + return ret; +} + +static struct uprobe_xol_ops default_xol_ops = { + .pre_xol = default_pre_xol_op, + .post_xol = default_post_xol_op, +}; + /** * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. * @mm: the probed address space. @@ -464,6 +522,7 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, if (fix_call) auprobe->fixups |= UPROBE_FIX_CALL; + auprobe->ops = &default_xol_ops; return 0; } @@ -485,33 +544,8 @@ int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) set_task_blockstep(current, false); - pre_xol_rip_insn(auprobe, regs, &utask->autask); - return 0; -} - -/* - * This function is called by arch_uprobe_post_xol() to adjust the return - * address pushed by a call instruction executed out of line. - */ -static int adjust_ret_addr(unsigned long sp, long correction) -{ - int rasize, ncopied; - long ra = 0; - - if (is_ia32_task()) - rasize = 4; - else - rasize = 8; - - ncopied = copy_from_user(&ra, (void __user *)sp, rasize); - if (unlikely(ncopied)) - return -EFAULT; - - ra += correction; - ncopied = copy_to_user((void __user *)sp, &ra, rasize); - if (unlikely(ncopied)) - return -EFAULT; - + if (auprobe->ops->pre_xol) + return auprobe->ops->pre_xol(auprobe, regs); return 0; } @@ -560,11 +594,8 @@ bool arch_uprobe_xol_was_trapped(struct task_struct *t) int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) { struct uprobe_task *utask = current->utask; - long correction; - int result = 0; WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); - current->thread.trap_nr = utask->autask.saved_trap_nr; /* * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP @@ -576,15 +607,9 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) else if (!(auprobe->fixups & UPROBE_FIX_SETF)) regs->flags &= ~X86_EFLAGS_TF; - correction = (long)(utask->vaddr - utask->xol_vaddr); - handle_riprel_post_xol(auprobe, regs, &correction); - if (auprobe->fixups & UPROBE_FIX_IP) - regs->ip += correction; - - if (auprobe->fixups & UPROBE_FIX_CALL) - result = adjust_ret_addr(regs->sp, correction); - - return result; + if (auprobe->ops->post_xol) + return auprobe->ops->post_xol(auprobe, regs); + return 0; } /* callback routine for handling exceptions. */ @@ -642,6 +667,10 @@ static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) { int i; + if (auprobe->ops->emulate) + return auprobe->ops->emulate(auprobe, regs); + + /* TODO: move this code into ->emulate() hook */ for (i = 0; i < MAX_UINSN_BYTES; i++) { if (auprobe->insn[i] == 0x66) continue; -- cgit v1.2.3 From e55848a4f8ee52465771983e144f0c3337776eda Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 31 Mar 2014 17:24:14 +0200 Subject: uprobes/x86: Conditionalize the usage of handle_riprel_insn() arch_uprobe_analyze_insn() calls handle_riprel_insn() at the start, but only "0xff" and "default" cases need the UPROBE_FIX_RIP_ logic. Move the callsite into "default" case and change the "0xff" case to fall-through. We are going to add the various hooks to handle the rip-relative jmp/call instructions (and more), we need this change to enforce the fact that the new code can not conflict with is_riprel_insn() logic which, after this change, can only be used by default_xol_ops. Note: arch_uprobe_abort_xol() still calls handle_riprel_post_xol() directly. This is fine unless another _xol_ops we may add later will need to reuse "UPROBE_FIX_RIP_AX|UPROBE_FIX_RIP_CX" bits in ->fixup. In this case we can add uprobe_xol_ops->abort() hook, which (perhaps) we will need anyway in the long term. Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston Reviewed-by: Masami Hiramatsu --- arch/x86/kernel/uprobes.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 13ad8a38c2d9..08cdb82815fe 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -482,8 +482,6 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups * is either zero or it reflects rip-related fixups. */ - handle_riprel_insn(auprobe, &insn); - switch (OPCODE1(&insn)) { case 0x9d: /* popf */ auprobe->fixups |= UPROBE_FIX_SETF; @@ -512,9 +510,9 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, case 4: case 5: /* jmp or ljmp, indirect */ fix_ip = false; } - break; + /* fall through */ default: - break; + handle_riprel_insn(auprobe, &insn); } if (fix_ip) -- cgit v1.2.3 From 014940bad8e46ca7bd0483f760f9cba60088a3d4 Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Thu, 3 Apr 2014 20:20:10 +0200 Subject: uprobes/x86: Send SIGILL if arch_uprobe_post_xol() fails Currently the error from arch_uprobe_post_xol() is silently ignored. This doesn't look good and this can lead to the hard-to-debug problems. 1. Change handle_singlestep() to loudly complain and send SIGILL. Note: this only affects x86, ppc/arm can't fail. 2. Change arch_uprobe_post_xol() to call arch_uprobe_abort_xol() and avoid TF games if it is going to return an error. This can help to to analyze the problem, if nothing else we should not report ->ip = xol_slot in the core-file. Note: this means that handle_riprel_post_xol() can be called twice, but this is fine because it is idempotent. Signed-off-by: Oleg Nesterov Reviewed-by: Masami Hiramatsu Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 16 ++++++++++++---- kernel/events/uprobes.c | 8 +++++++- 2 files changed, 19 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 08cdb82815fe..e72903eacd43 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -594,6 +594,15 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) struct uprobe_task *utask = current->utask; WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); + + if (auprobe->ops->post_xol) { + int err = auprobe->ops->post_xol(auprobe, regs); + if (err) { + arch_uprobe_abort_xol(auprobe, regs); + return err; + } + } + current->thread.trap_nr = utask->autask.saved_trap_nr; /* * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP @@ -605,8 +614,6 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) else if (!(auprobe->fixups & UPROBE_FIX_SETF)) regs->flags &= ~X86_EFLAGS_TF; - if (auprobe->ops->post_xol) - return auprobe->ops->post_xol(auprobe, regs); return 0; } @@ -641,8 +648,9 @@ int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, /* * This function gets called when XOL instruction either gets trapped or - * the thread has a fatal signal, so reset the instruction pointer to its - * probed address. + * the thread has a fatal signal, or if arch_uprobe_post_xol() failed. + * Reset the instruction pointer to its probed address for the potential + * restart or for post mortem analysis. */ void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) { diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index ea2a7c0728bb..d1edc5e6fd03 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -1867,10 +1867,11 @@ out: static void handle_singlestep(struct uprobe_task *utask, struct pt_regs *regs) { struct uprobe *uprobe; + int err = 0; uprobe = utask->active_uprobe; if (utask->state == UTASK_SSTEP_ACK) - arch_uprobe_post_xol(&uprobe->arch, regs); + err = arch_uprobe_post_xol(&uprobe->arch, regs); else if (utask->state == UTASK_SSTEP_TRAPPED) arch_uprobe_abort_xol(&uprobe->arch, regs); else @@ -1884,6 +1885,11 @@ static void handle_singlestep(struct uprobe_task *utask, struct pt_regs *regs) spin_lock_irq(¤t->sighand->siglock); recalc_sigpending(); /* see uprobe_deny_signal() */ spin_unlock_irq(¤t->sighand->siglock); + + if (unlikely(err)) { + uprobe_warn(current, "execute the probed insn, sending SIGILL."); + force_sig_info(SIGILL, SEND_SIG_FORCED, current); + } } /* -- cgit v1.2.3 From 75f9ef0b7f1aae33b7be7ba8d9c23c8cb48c2212 Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Thu, 3 Apr 2014 20:52:19 +0200 Subject: uprobes/x86: Teach arch_uprobe_post_xol() to restart if possible SIGILL after the failed arch_uprobe_post_xol() should only be used as a last resort, we should try to restart the probed insn if possible. Currently only adjust_ret_addr() can fail, and this can only happen if another thread unmapped our stack after we executed "call" out-of-line. Most probably the application if buggy, but even in this case it can have a handler for SIGSEGV/etc. And in theory it can be even correct and do something non-trivial with its memory. Of course we can't restart unconditionally, so arch_uprobe_post_xol() does this only if ->post_xol() returns -ERESTART even if currently this is the only possible error. default_post_xol_op(UPROBE_FIX_CALL) can always restart, but as Jim pointed out it should not forget to pop off the return address pushed by this insn executed out-of-line. Note: this is not "perfect", we do not want the extra handler_chain() after restart, but I think this is the best solution we can realistically do without too much uglifications. Signed-off-by: Oleg Nesterov Reviewed-by: Masami Hiramatsu Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index e72903eacd43..cdd6909affcb 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -443,16 +443,22 @@ static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs { struct uprobe_task *utask = current->utask; long correction = (long)(utask->vaddr - utask->xol_vaddr); - int ret = 0; handle_riprel_post_xol(auprobe, regs, &correction); if (auprobe->fixups & UPROBE_FIX_IP) regs->ip += correction; - if (auprobe->fixups & UPROBE_FIX_CALL) - ret = adjust_ret_addr(regs->sp, correction); + if (auprobe->fixups & UPROBE_FIX_CALL) { + if (adjust_ret_addr(regs->sp, correction)) { + if (is_ia32_task()) + regs->sp += 4; + else + regs->sp += 8; + return -ERESTART; + } + } - return ret; + return 0; } static struct uprobe_xol_ops default_xol_ops = { @@ -599,6 +605,12 @@ int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) int err = auprobe->ops->post_xol(auprobe, regs); if (err) { arch_uprobe_abort_xol(auprobe, regs); + /* + * Restart the probed insn. ->post_xol() must ensure + * this is really possible if it returns -ERESTART. + */ + if (err == -ERESTART) + return 0; return err; } } -- cgit v1.2.3 From 8faaed1b9f500d6cf32702716733a645c9b0727a Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Sun, 6 Apr 2014 17:16:10 +0200 Subject: uprobes/x86: Introduce sizeof_long(), cleanup adjust_ret_addr() and arch_uretprobe_hijack_return_addr() 1. Add the trivial sizeof_long() helper and change other callers of is_ia32_task() to use it. TODO: is_ia32_task() is not what we actually want, TS_COMPAT does not necessarily mean 32bit. Fortunately syscall-like insns can't be probed so it actually works, but it would be better to rename and use is_ia32_frame(). 2. As Jim pointed out "ncopied" in arch_uretprobe_hijack_return_addr() and adjust_ret_addr() should be named "nleft". And in fact only the last copy_to_user() in arch_uretprobe_hijack_return_addr() actually needs to inspect the non-zero error code. TODO: adjust_ret_addr() should die. We can always calculate the value we need to write into *regs->sp, just UPROBE_FIX_CALL should record insn->length. Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 37 +++++++++++++++---------------------- 1 file changed, 15 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index cdd6909affcb..aecc22054384 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -408,6 +408,11 @@ struct uprobe_xol_ops { int (*post_xol)(struct arch_uprobe *, struct pt_regs *); }; +static inline int sizeof_long(void) +{ + return is_ia32_task() ? 4 : 8; +} + static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) { pre_xol_rip_insn(auprobe, regs, ¤t->utask->autask); @@ -419,21 +424,14 @@ static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) */ static int adjust_ret_addr(unsigned long sp, long correction) { - int rasize, ncopied; - long ra = 0; - - if (is_ia32_task()) - rasize = 4; - else - rasize = 8; + int rasize = sizeof_long(); + long ra; - ncopied = copy_from_user(&ra, (void __user *)sp, rasize); - if (unlikely(ncopied)) + if (copy_from_user(&ra, (void __user *)sp, rasize)) return -EFAULT; ra += correction; - ncopied = copy_to_user((void __user *)sp, &ra, rasize); - if (unlikely(ncopied)) + if (copy_to_user((void __user *)sp, &ra, rasize)) return -EFAULT; return 0; @@ -450,10 +448,7 @@ static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs if (auprobe->fixups & UPROBE_FIX_CALL) { if (adjust_ret_addr(regs->sp, correction)) { - if (is_ia32_task()) - regs->sp += 4; - else - regs->sp += 8; + regs->sp += sizeof_long(); return -ERESTART; } } @@ -714,23 +709,21 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) { - int rasize, ncopied; + int rasize = sizeof_long(), nleft; unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ - rasize = is_ia32_task() ? 4 : 8; - ncopied = copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize); - if (unlikely(ncopied)) + if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) return -1; /* check whether address has been already hijacked */ if (orig_ret_vaddr == trampoline_vaddr) return orig_ret_vaddr; - ncopied = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); - if (likely(!ncopied)) + nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); + if (likely(!nleft)) return orig_ret_vaddr; - if (ncopied != rasize) { + if (nleft != rasize) { pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, " "%%ip=%#lx\n", current->pid, regs->sp, regs->ip); -- cgit v1.2.3 From 7ba6db2d688bdf83049a18c8e55b2d1e58e8b0bc Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Sat, 5 Apr 2014 20:05:02 +0200 Subject: uprobes/x86: Emulate unconditional relative jmp's Currently we always execute all insns out-of-line, including relative jmp's and call's. This assumes that even if regs->ip points to nowhere after the single-step, default_post_xol_op(UPROBE_FIX_IP) logic will update it correctly. However, this doesn't work if this regs->ip == xol_vaddr + insn_offset is not canonical. In this case CPU generates #GP and general_protection() kills the task which tries to execute this insn out-of-line. Now that we have uprobe_xol_ops we can teach uprobes to emulate these insns and solve the problem. This patch adds branch_xol_ops which has a single branch_emulate_op() hook, so far it can only handle rel8/32 relative jmp's. TODO: move ->fixup into the union along with rip_rela_target_address. Signed-off-by: Oleg Nesterov Reported-by: Jonathan Lebon Reviewed-by: Jim Keniston --- arch/x86/include/asm/uprobes.h | 8 +++++++- arch/x86/kernel/uprobes.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h index 9f8210bcbb49..e9fd4d5537ed 100644 --- a/arch/x86/include/asm/uprobes.h +++ b/arch/x86/include/asm/uprobes.h @@ -44,9 +44,15 @@ struct arch_uprobe { u16 fixups; const struct uprobe_xol_ops *ops; + union { #ifdef CONFIG_X86_64 - unsigned long rip_rela_target_address; + unsigned long rip_rela_target_address; #endif + struct { + s32 offs; + u8 ilen; + } branch; + }; }; struct arch_uprobe_task { diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index aecc22054384..c3baeaacf1b6 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -461,6 +461,40 @@ static struct uprobe_xol_ops default_xol_ops = { .post_xol = default_post_xol_op, }; +static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + regs->ip += auprobe->branch.ilen + auprobe->branch.offs; + return true; +} + +static struct uprobe_xol_ops branch_xol_ops = { + .emulate = branch_emulate_op, +}; + +/* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ +static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) +{ + + switch (OPCODE1(insn)) { + case 0xeb: /* jmp 8 */ + case 0xe9: /* jmp 32 */ + break; + default: + return -ENOSYS; + } + + /* has the side-effect of processing the entire instruction */ + insn_get_length(insn); + if (WARN_ON_ONCE(!insn_complete(insn))) + return -ENOEXEC; + + auprobe->branch.ilen = insn->length; + auprobe->branch.offs = insn->immediate.value; + + auprobe->ops = &branch_xol_ops; + return 0; +} + /** * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. * @mm: the probed address space. @@ -478,6 +512,10 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, if (ret) return ret; + ret = branch_setup_xol_ops(auprobe, &insn); + if (ret != -ENOSYS) + return ret; + /* * Figure out which fixups arch_uprobe_post_xol() will need to perform, * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups -- cgit v1.2.3 From d241006354c550c7d22f304e2fdf90137fb8eaab Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Sat, 5 Apr 2014 21:06:10 +0200 Subject: uprobes/x86: Emulate nop's using ops->emulate() Finally we can kill the ugly (and very limited) code in __skip_sstep(). Just change branch_setup_xol_ops() to treat "nop" as jmp to the next insn. Thanks to lib/insn.c, it is clever enough. OPCODE1() == 0x90 includes "(rep;)+ nop;" at least, and (afaics) much more. Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index c3baeaacf1b6..f3c4212f3819 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -478,6 +478,7 @@ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) switch (OPCODE1(insn)) { case 0xeb: /* jmp 8 */ case 0xe9: /* jmp 32 */ + case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ break; default: return -ENOSYS; @@ -710,29 +711,10 @@ void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) regs->flags &= ~X86_EFLAGS_TF; } -/* - * Skip these instructions as per the currently known x86 ISA. - * rep=0x66*; nop=0x90 - */ static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) { - int i; - if (auprobe->ops->emulate) return auprobe->ops->emulate(auprobe, regs); - - /* TODO: move this code into ->emulate() hook */ - for (i = 0; i < MAX_UINSN_BYTES; i++) { - if (auprobe->insn[i] == 0x66) - continue; - - if (auprobe->insn[i] == 0x90) { - regs->ip += i + 1; - return true; - } - - break; - } return false; } -- cgit v1.2.3 From 8e89c0be171b1a9ed2ba67168733ca811bb45d5c Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Sun, 6 Apr 2014 18:11:02 +0200 Subject: uprobes/x86: Emulate relative call's See the previous "Emulate unconditional relative jmp's" which explains why we can not execute "jmp" out-of-line, the same applies to "call". Emulating of rip-relative call is trivial, we only need to additionally push the ret-address. If this fails, we execute this instruction out of line and this should trigger the trap, the probed application should die or the same insn will be restarted if a signal handler expands the stack. We do not even need ->post_xol() for this case. But there is a corner (and almost theoretical) case: another thread can expand the stack right before we execute this insn out of line. In this case it hit the same problem we are trying to solve. So we simply turn the probed insn into "call 1f; 1:" and add ->post_xol() which restores ->sp and restarts. Many thanks to Jonathan who finally found the standalone reproducer, otherwise I would never resolve the "random SIGSEGV's under systemtap" bug-report. Now that the problem is clear we can write the simplified test-case: void probe_func(void), callee(void); int failed = 1; asm ( ".text\n" ".align 4096\n" ".globl probe_func\n" "probe_func:\n" "call callee\n" "ret" ); /* * This assumes that: * * - &probe_func = 0x401000 + a_bit, aligned = 0x402000 * * - xol_vma->vm_start = TASK_SIZE_MAX - PAGE_SIZE = 0x7fffffffe000 * as xol_add_vma() asks; the 1st slot = 0x7fffffffe080 * * so we can target the non-canonical address from xol_vma using * the simple math below, 100 * 4096 is just the random offset */ asm (".org . + 0x800000000000 - 0x7fffffffe080 - 5 - 1 + 100 * 4096\n"); void callee(void) { failed = 0; } int main(void) { probe_func(); return failed; } It SIGSEGV's if you probe "probe_func" (although this is not very reliable, randomize_va_space/etc can change the placement of xol area). Note: as Denys Vlasenko pointed out, amd and intel treat "callw" (0x66 0xe8) differently. This patch relies on lib/insn.c and thus implements the intel's behaviour: 0x66 is simply ignored. Fortunately nothing sane should ever use this insn, so we postpone the fix until we decide what should we do; emulate or not, support or not, etc. Reported-by: Jonathan Lebon Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston --- arch/x86/include/asm/uprobes.h | 1 + arch/x86/kernel/uprobes.c | 80 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 71 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h index e9fd4d5537ed..93bee7b93854 100644 --- a/arch/x86/include/asm/uprobes.h +++ b/arch/x86/include/asm/uprobes.h @@ -51,6 +51,7 @@ struct arch_uprobe { struct { s32 offs; u8 ilen; + u8 opc1; } branch; }; }; diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index f3c4212f3819..0914435001f5 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -461,34 +461,97 @@ static struct uprobe_xol_ops default_xol_ops = { .post_xol = default_post_xol_op, }; +static bool branch_is_call(struct arch_uprobe *auprobe) +{ + return auprobe->branch.opc1 == 0xe8; +} + static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) { - regs->ip += auprobe->branch.ilen + auprobe->branch.offs; + unsigned long new_ip = regs->ip += auprobe->branch.ilen; + + if (branch_is_call(auprobe)) { + unsigned long new_sp = regs->sp - sizeof_long(); + /* + * If it fails we execute this (mangled, see the comment in + * branch_clear_offset) insn out-of-line. In the likely case + * this should trigger the trap, and the probed application + * should die or restart the same insn after it handles the + * signal, arch_uprobe_post_xol() won't be even called. + * + * But there is corner case, see the comment in ->post_xol(). + */ + if (copy_to_user((void __user *)new_sp, &new_ip, sizeof_long())) + return false; + regs->sp = new_sp; + } + + regs->ip = new_ip + auprobe->branch.offs; return true; } +static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + BUG_ON(!branch_is_call(auprobe)); + /* + * We can only get here if branch_emulate_op() failed to push the ret + * address _and_ another thread expanded our stack before the (mangled) + * "call" insn was executed out-of-line. Just restore ->sp and restart. + * We could also restore ->ip and try to call branch_emulate_op() again. + */ + regs->sp += sizeof_long(); + return -ERESTART; +} + +static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) +{ + /* + * Turn this insn into "call 1f; 1:", this is what we will execute + * out-of-line if ->emulate() fails. We only need this to generate + * a trap, so that the probed task receives the correct signal with + * the properly filled siginfo. + * + * But see the comment in ->post_xol(), in the unlikely case it can + * succeed. So we need to ensure that the new ->ip can not fall into + * the non-canonical area and trigger #GP. + * + * We could turn it into (say) "pushf", but then we would need to + * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte + * of ->insn[] for set_orig_insn(). + */ + memset(auprobe->insn + insn_offset_immediate(insn), + 0, insn->immediate.nbytes); +} + static struct uprobe_xol_ops branch_xol_ops = { .emulate = branch_emulate_op, + .post_xol = branch_post_xol_op, }; /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) { + u8 opc1 = OPCODE1(insn); + + /* has the side-effect of processing the entire instruction */ + insn_get_length(insn); + if (WARN_ON_ONCE(!insn_complete(insn))) + return -ENOEXEC; - switch (OPCODE1(insn)) { + switch (opc1) { case 0xeb: /* jmp 8 */ case 0xe9: /* jmp 32 */ case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ break; + + case 0xe8: /* call relative */ + branch_clear_offset(auprobe, insn); + break; default: return -ENOSYS; } - /* has the side-effect of processing the entire instruction */ - insn_get_length(insn); - if (WARN_ON_ONCE(!insn_complete(insn))) - return -ENOEXEC; - + auprobe->branch.opc1 = opc1; auprobe->branch.ilen = insn->length; auprobe->branch.offs = insn->immediate.value; @@ -532,9 +595,6 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, case 0xca: fix_ip = false; break; - case 0xe8: /* call relative - Fix return addr */ - fix_call = true; - break; case 0x9a: /* call absolute - Fix return addr, not ip */ fix_call = true; fix_ip = false; -- cgit v1.2.3 From 8f95505bc18a026ef7d3dfdbce4e5b31b3e4fc1b Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Sun, 6 Apr 2014 21:53:47 +0200 Subject: uprobes/x86: Emulate relative conditional "short" jmp's Teach branch_emulate_op() to emulate the conditional "short" jmp's which check regs->flags. Note: this doesn't support jcxz/jcexz, loope/loopz, and loopne/loopnz. They all are rel8 and thus they can't trigger the problem, but perhaps we will add the support in future just for completeness. Reported-by: Jonathan Lebon Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 57 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 0914435001f5..0460d04f0acc 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -466,9 +466,58 @@ static bool branch_is_call(struct arch_uprobe *auprobe) return auprobe->branch.opc1 == 0xe8; } +#define CASE_COND \ + COND(70, 71, XF(OF)) \ + COND(72, 73, XF(CF)) \ + COND(74, 75, XF(ZF)) \ + COND(78, 79, XF(SF)) \ + COND(7a, 7b, XF(PF)) \ + COND(76, 77, XF(CF) || XF(ZF)) \ + COND(7c, 7d, XF(SF) != XF(OF)) \ + COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) + +#define COND(op_y, op_n, expr) \ + case 0x ## op_y: DO((expr) != 0) \ + case 0x ## op_n: DO((expr) == 0) + +#define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) + +static bool is_cond_jmp_opcode(u8 opcode) +{ + switch (opcode) { + #define DO(expr) \ + return true; + CASE_COND + #undef DO + + default: + return false; + } +} + +static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) +{ + unsigned long flags = regs->flags; + + switch (auprobe->branch.opc1) { + #define DO(expr) \ + return expr; + CASE_COND + #undef DO + + default: /* not a conditional jmp */ + return true; + } +} + +#undef XF +#undef COND +#undef CASE_COND + static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) { unsigned long new_ip = regs->ip += auprobe->branch.ilen; + unsigned long offs = (long)auprobe->branch.offs; if (branch_is_call(auprobe)) { unsigned long new_sp = regs->sp - sizeof_long(); @@ -484,9 +533,11 @@ static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) if (copy_to_user((void __user *)new_sp, &new_ip, sizeof_long())) return false; regs->sp = new_sp; + } else if (!check_jmp_cond(auprobe, regs)) { + offs = 0; } - regs->ip = new_ip + auprobe->branch.offs; + regs->ip = new_ip + offs; return true; } @@ -547,8 +598,10 @@ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) case 0xe8: /* call relative */ branch_clear_offset(auprobe, insn); break; + default: - return -ENOSYS; + if (!is_cond_jmp_opcode(opc1)) + return -ENOSYS; } auprobe->branch.opc1 = opc1; -- cgit v1.2.3 From 6cc5e7ff2c38641060f20786a5caf2815edbca5f Mon Sep 17 00:00:00 2001 From: Oleg Nesterov Date: Mon, 7 Apr 2014 16:22:58 +0200 Subject: uprobes/x86: Emulate relative conditional "near" jmp's Change branch_setup_xol_ops() to simply use opc1 = OPCODE2(insn) - 0x10 if OPCODE1() == 0x0f; this matches the "short" jmp which checks the same condition. Thanks to lib/insn.c, it does the rest correctly. branch->ilen/offs are correct no matter if this jmp is "near" or "short". Reported-by: Jonathan Lebon Signed-off-by: Oleg Nesterov Reviewed-by: Jim Keniston --- arch/x86/kernel/uprobes.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index 0460d04f0acc..ace22916ade3 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c @@ -599,6 +599,14 @@ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) branch_clear_offset(auprobe, insn); break; + case 0x0f: + if (insn->opcode.nbytes != 2) + return -ENOSYS; + /* + * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches + * OPCODE1() of the "short" jmp which checks the same condition. + */ + opc1 = OPCODE2(insn) - 0x10; default: if (!is_cond_jmp_opcode(opc1)) return -ENOSYS; -- cgit v1.2.3 From e4f9bfb3feaeaca55cf177dadb7e3313836b10f4 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Tue, 4 Feb 2014 20:36:01 +0100 Subject: ia64: Fix up smp_mb__{before,after}_clear_bit() IA64 doesn't actually have acquire/release barriers, its a lie! Add a comment explaining this and fix up the bitop barriers. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-akevfh136um9dqvb1ohm55ca@git.kernel.org Cc: Akinobu Mita Cc: Fenghua Yu Cc: Linus Torvalds Cc: Tony Luck Cc: linux-ia64@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/ia64/include/asm/bitops.h | 7 ++----- arch/ia64/include/uapi/asm/cmpxchg.h | 9 +++++++++ 2 files changed, 11 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h index c27eccd33349..feb8117ed06a 100644 --- a/arch/ia64/include/asm/bitops.h +++ b/arch/ia64/include/asm/bitops.h @@ -65,11 +65,8 @@ __set_bit (int nr, volatile void *addr) *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31)); } -/* - * clear_bit() has "acquire" semantics. - */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() do { /* skip */; } while (0) +#define smp_mb__before_clear_bit() barrier(); +#define smp_mb__after_clear_bit() barrier(); /** * clear_bit - Clears a bit in memory diff --git a/arch/ia64/include/uapi/asm/cmpxchg.h b/arch/ia64/include/uapi/asm/cmpxchg.h index 4f37dbbb8640..f35109b1d907 100644 --- a/arch/ia64/include/uapi/asm/cmpxchg.h +++ b/arch/ia64/include/uapi/asm/cmpxchg.h @@ -118,6 +118,15 @@ extern long ia64_cmpxchg_called_with_bad_pointer(void); #define cmpxchg_rel(ptr, o, n) \ ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr))) +/* + * Worse still - early processor implementations actually just ignored + * the acquire/release and did a full fence all the time. Unfortunately + * this meant a lot of badly written code that used .acq when they really + * wanted .rel became legacy out in the wild - so when we made a cpu + * that strictly did the .acq or .rel ... all that code started breaking - so + * we had to back-pedal and keep the "legacy" behavior of a full fence :-( + */ + /* for compatibility with other platforms: */ #define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) #define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n)) -- cgit v1.2.3 From 2ab08ee9f0a4eba27c7c4ce0b6d5118e8a18554b Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 6 Feb 2014 14:26:10 +0100 Subject: arc,hexagon: Delete asm/barrier.h Both already use asm-generic/barrier.h as per their include/asm/Kbuild. Remove the stale files. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-c7vlkshl3tblim0o8z2p70kt@git.kernel.org Cc: Linus Torvalds Cc: Richard Kuo Cc: Vineet Gupta Cc: linux-hexagon@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/arc/include/asm/barrier.h | 37 ------------------------------------- arch/hexagon/include/asm/barrier.h | 37 ------------------------------------- 2 files changed, 74 deletions(-) delete mode 100644 arch/arc/include/asm/barrier.h delete mode 100644 arch/hexagon/include/asm/barrier.h (limited to 'arch') diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h deleted file mode 100644 index c32245c3d1e9..000000000000 --- a/arch/arc/include/asm/barrier.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_BARRIER_H -#define __ASM_BARRIER_H - -#ifndef __ASSEMBLY__ - -/* TODO-vineetg: Need to see what this does, don't we need sync anywhere */ -#define mb() __asm__ __volatile__ ("" : : : "memory") -#define rmb() mb() -#define wmb() mb() -#define set_mb(var, value) do { var = value; mb(); } while (0) -#define set_wmb(var, value) do { var = value; wmb(); } while (0) -#define read_barrier_depends() mb() - -/* TODO-vineetg verify the correctness of macros here */ -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#endif - -#define smp_read_barrier_depends() do { } while (0) - -#endif - -#endif diff --git a/arch/hexagon/include/asm/barrier.h b/arch/hexagon/include/asm/barrier.h deleted file mode 100644 index 4e863daea25b..000000000000 --- a/arch/hexagon/include/asm/barrier.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Memory barrier definitions for the Hexagon architecture - * - * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA - * 02110-1301, USA. - */ - -#ifndef _ASM_BARRIER_H -#define _ASM_BARRIER_H - -#define rmb() barrier() -#define read_barrier_depends() barrier() -#define wmb() barrier() -#define mb() barrier() -#define smp_rmb() barrier() -#define smp_read_barrier_depends() barrier() -#define smp_wmb() barrier() -#define smp_mb() barrier() - -/* Set a value and use a memory barrier. Used by the scheduler somewhere. */ -#define set_mb(var, value) \ - do { var = value; mb(); } while (0) - -#endif /* _ASM_BARRIER_H */ -- cgit v1.2.3 From 6ae11028a62b2f82ee283392a84f33da599a81e7 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 12 Mar 2014 17:11:00 +0100 Subject: arch,alpha: Convert smp_mb__*() to the asm-generic primitives The Alpha ll/sc primitives do not imply any sort of barrier; therefore the smp_mb__{before,after} should be a full barrier. This is the default from asm-generic/barrier.h and therefore just remove the current definitions. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-iacwfd15lq3ta2v7jut747r7@git.kernel.org Cc: Ivan Kokshaysky Cc: Linus Torvalds Cc: Matt Turner Cc: Richard Henderson Cc: linux-alpha@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/alpha/include/asm/atomic.h | 5 ----- arch/alpha/include/asm/bitops.h | 3 --- 2 files changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h index 78b03ef39f6f..ed60a1ee1ed3 100644 --- a/arch/alpha/include/asm/atomic.h +++ b/arch/alpha/include/asm/atomic.h @@ -292,9 +292,4 @@ static inline long atomic64_dec_if_positive(atomic64_t *v) #define atomic_dec(v) atomic_sub(1,(v)) #define atomic64_dec(v) atomic64_sub(1,(v)) -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - #endif /* _ALPHA_ATOMIC_H */ diff --git a/arch/alpha/include/asm/bitops.h b/arch/alpha/include/asm/bitops.h index a19ba5efea4c..4bdfbd444e63 100644 --- a/arch/alpha/include/asm/bitops.h +++ b/arch/alpha/include/asm/bitops.h @@ -53,9 +53,6 @@ __set_bit(unsigned long nr, volatile void * addr) *m |= 1 << (nr & 31); } -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() - static inline void clear_bit(unsigned long nr, volatile void * addr) { -- cgit v1.2.3 From d594ffa94b7efdd8c6da5ee48aea8ae229809b55 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 12 Mar 2014 17:11:00 +0100 Subject: arch,arc: Convert smp_mb__*() The arc mb() implementation is a compiler barrier(), therefore it all doesn't matter one way or the other. Simply remove the existing definitions and use whatever is generated by the defaults. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-ua48a59wri3ybz1rz8i7uvbr@git.kernel.org Cc: Linus Torvalds Cc: Vineet Gupta Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/arc/include/asm/atomic.h | 5 ----- arch/arc/include/asm/bitops.h | 5 +---- 2 files changed, 1 insertion(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h index 03e494f695d1..83f03ca6caf6 100644 --- a/arch/arc/include/asm/atomic.h +++ b/arch/arc/include/asm/atomic.h @@ -190,11 +190,6 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) #endif /* !CONFIG_ARC_HAS_LLSC */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - /** * __atomic_add_unless - add unless the number is a given value * @v: pointer of type atomic_t diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h index 647a83a8e756..ebc0cf3164dc 100644 --- a/arch/arc/include/asm/bitops.h +++ b/arch/arc/include/asm/bitops.h @@ -19,6 +19,7 @@ #include #include +#include /* * Hardware assisted read-modify-write using ARC700 LLOCK/SCOND insns. @@ -496,10 +497,6 @@ static inline __attribute__ ((const)) int __ffs(unsigned long word) */ #define ffz(x) __ffs(~(x)) -/* TODO does this affect uni-processor code */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - #include #include #include -- cgit v1.2.3 From 030d0178bdbd237c1f0577f03bbc1d7140a75044 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 12 Mar 2014 17:11:00 +0100 Subject: arch,arm: Convert smp_mb__*() ARM uses ll/sc primitives that do not imply barriers for all regular atomic ops, therefore smp_mb__{before,after} need be a full barrier. Since ARM doesn't use asm-generic/barrier.h include the required definitions in its asm/barrier.h Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-yijo7sglsl7uusbp13upcuvo@git.kernel.org Cc: Albin Tonnerre Cc: Catalin Marinas Cc: Chen Gang Cc: Linus Torvalds Cc: Nicolas Pitre Cc: Russell King Cc: Victor Kamensky Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/arm/include/asm/atomic.h | 5 ----- arch/arm/include/asm/barrier.h | 3 +++ arch/arm/include/asm/bitops.h | 4 +--- 3 files changed, 4 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 9a92fd7864a8..3040359094d9 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -241,11 +241,6 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - #ifndef CONFIG_GENERIC_ATOMIC64 typedef struct { long long counter; diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h index 2f59f7443396..c6a3e73a6e24 100644 --- a/arch/arm/include/asm/barrier.h +++ b/arch/arm/include/asm/barrier.h @@ -79,5 +79,8 @@ do { \ #define set_mb(var, value) do { var = value; smp_mb(); } while (0) +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_BARRIER_H */ diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index b2e298a90d76..56380995f4c3 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -25,9 +25,7 @@ #include #include - -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#include /* * These functions are the basis of our bit ops. -- cgit v1.2.3 From 8715466b602729061394df18864ea64b97951589 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:37 +0100 Subject: arch,arm64: Convert smp_mb__*() AARGH64 uses ll/sc primitives that do not imply any barriers for the normal atomics, therefore smp_mb__{before,after} should be a full barrier. Since AARGH64 doesn't use asm-generic/barrier.h, add the required definitions to its asm/barrier.h. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-8p5iclqgy78al33kck3ht7nr@git.kernel.org Cc: Catalin Marinas Cc: Chen Gang Cc: Linus Torvalds Cc: Russell King Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/arm64/include/asm/atomic.h | 5 ----- arch/arm64/include/asm/barrier.h | 3 +++ arch/arm64/include/asm/bitops.h | 9 --------- 3 files changed, 3 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm64/include/asm/atomic.h b/arch/arm64/include/asm/atomic.h index 0237f0867e37..57e8cb49824c 100644 --- a/arch/arm64/include/asm/atomic.h +++ b/arch/arm64/include/asm/atomic.h @@ -152,11 +152,6 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0) -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - /* * 64-bit atomic operations. */ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 66eb7648043b..48b9e704af7c 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -98,6 +98,9 @@ do { \ #define set_mb(var, value) do { var = value; smp_mb(); } while (0) #define nop() asm volatile("nop"); +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() + #endif /* __ASSEMBLY__ */ #endif /* __ASM_BARRIER_H */ diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index aa5b59d6ba43..9c19594ce7cb 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -17,17 +17,8 @@ #define __ASM_BITOPS_H #include - #include -/* - * clear_bit may not imply a memory barrier - */ -#ifndef smp_mb__before_clear_bit -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() -#endif - #ifndef _LINUX_BITOPS_H #error only can be included directly #endif -- cgit v1.2.3 From 710adaa913169d7183cdf0de41c2a349101ff615 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:37 +0100 Subject: arch,avr32: Convert smp_mb__*() AVR32's mb() implementation is a compiler barrier(), therefore it all doesn't matter, fully rely on whatever asm-generic/barrier.h generates. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-8gow97a7mapmnec0pvf729pj@git.kernel.org Cc: Haavard Skinnemoen Cc: Hans-Christian Egtvedt Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/avr32/include/asm/atomic.h | 5 ----- arch/avr32/include/asm/bitops.h | 9 ++------- 2 files changed, 2 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/avr32/include/asm/atomic.h b/arch/avr32/include/asm/atomic.h index 61407279208a..0780f3f2415b 100644 --- a/arch/avr32/include/asm/atomic.h +++ b/arch/avr32/include/asm/atomic.h @@ -183,9 +183,4 @@ static inline int atomic_sub_if_positive(int i, atomic_t *v) #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v) -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* __ASM_AVR32_ATOMIC_H */ diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h index ebe7ad3f490b..910d5374ce59 100644 --- a/arch/avr32/include/asm/bitops.h +++ b/arch/avr32/include/asm/bitops.h @@ -13,12 +13,7 @@ #endif #include - -/* - * clear_bit() doesn't provide any barrier for the compiler - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() +#include /* * set_bit - Atomically set a bit in memory @@ -67,7 +62,7 @@ static inline void set_bit(int nr, volatile void * addr) * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static inline void clear_bit(int nr, volatile void * addr) -- cgit v1.2.3 From b7bb7d9b28f6278625fbe7892b8c7799bb12a26a Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:37 +0100 Subject: arch,blackfin: Convert smp_mb__*() Blackfin's atomic primitives do not imply a full barrier as whitnessed from its SMP smp_mb__{before,after}_clear_bit() implementations. However since !SMP smp_mb() reduces to barrier() remove everything and rely on the asm-generic/barrier.h implentation. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-1widdkdsb3c1titq8jez6g3g@git.kernel.org Cc: Geert Uytterhoeven Cc: Linus Torvalds Cc: Mathieu Desnoyers Cc: Steven Miao Cc: adi-buildroot-devel@lists.sourceforge.net Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/blackfin/include/asm/barrier.h | 3 +++ arch/blackfin/include/asm/bitops.h | 14 ++------------ 2 files changed, 5 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/barrier.h b/arch/blackfin/include/asm/barrier.h index 19283a16ac08..420006877998 100644 --- a/arch/blackfin/include/asm/barrier.h +++ b/arch/blackfin/include/asm/barrier.h @@ -27,6 +27,9 @@ #endif /* !CONFIG_SMP */ +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + #include #endif /* _BLACKFIN_BARRIER_H */ diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 0ca40dd44724..b298b654a26f 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -27,21 +27,17 @@ #include +#include + #ifndef CONFIG_SMP #include - /* * clear_bit may not imply a memory barrier */ -#ifndef smp_mb__before_clear_bit -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() -#endif #include #include #else -#include #include /* swab32 */ #include @@ -101,12 +97,6 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) return __raw_bit_test_toggle_asm(a, nr & 0x1f); } -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - #define test_bit __skip_test_bit #include #undef test_bit -- cgit v1.2.3 From a8ec1516a74554992605f230859936d5d79c27ed Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:37 +0100 Subject: arch,c6x: Convert smp_mb__*() c6x doesn't have a barrier.h and completely relies on asm-generic/barrier.h. Therefore its smp_mb() is barrier() and we can use the default versions that are smp_mb(). Signed-off-by: Peter Zijlstra Acked-by: Mark Salter Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-kl53k3pyj0rbd80jq8ralpf3@git.kernel.org Cc: Aurelien Jacquiot Cc: Linus Torvalds Cc: Mark Salter Cc: linux-c6x-dev@linux-c6x.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/c6x/include/asm/bitops.h | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/c6x/include/asm/bitops.h b/arch/c6x/include/asm/bitops.h index 0bec7e5036a8..f0ab012401b6 100644 --- a/arch/c6x/include/asm/bitops.h +++ b/arch/c6x/include/asm/bitops.h @@ -14,14 +14,8 @@ #ifdef __KERNEL__ #include - #include - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() +#include /* * We are lucky, DSP is perfect for bitops: do it in 3 cycles -- cgit v1.2.3 From 4a3dc121d3c370625575247bf714db3f601d83e9 Mon Sep 17 00:00:00 2001 From: "Yan, Zheng" Date: Tue, 18 Mar 2014 16:56:43 +0800 Subject: perf/x86: Export perf_assign_events() export perf_assign_events to allow building perf Intel uncore driver as module Signed-off-by: Yan, Zheng Signed-off-by: Peter Zijlstra Link: http://lkml.kernel.org/r/1395133004-23205-3-git-send-email-zheng.z.yan@intel.com Cc: Arnaldo Carvalho de Melo Cc: eranian@google.com Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index ae407f7226c8..89f3b7c1af20 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -721,6 +721,7 @@ int perf_assign_events(struct perf_event **events, int n, return sched.state.unassigned; } +EXPORT_SYMBOL_GPL(perf_assign_events); int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) { -- cgit v1.2.3 From 17b40213ab2b091fd5d2a9337eae62312608ad3d Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:37 +0100 Subject: arch,cris: Convert smp_mb__*() Cris fully relies on asm-generic/barrier.h, therefore its smp_mb() is barrier(), thus we can use the default implementation that uses smp_mb(). (Include asm/system.h and asm/barrier.h to avoid header dependency hell.) Signed-off-by: Peter Zijlstra Acked-by: Jesper Nilsson Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-wvewbe8os3s1e4pt1cdotuee@git.kernel.org Cc: Andrew Morton Cc: Geert Uytterhoeven Cc: Jesper Nilsson Cc: Linus Torvalds Cc: Mikael Starvik Cc: linux-cris-kernel@axis.com Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/cris/include/asm/atomic.h | 8 ++------ arch/cris/include/asm/bitops.h | 9 ++------- 2 files changed, 4 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/cris/include/asm/atomic.h b/arch/cris/include/asm/atomic.h index 1056a5dfe04f..aa429baebaf9 100644 --- a/arch/cris/include/asm/atomic.h +++ b/arch/cris/include/asm/atomic.h @@ -7,6 +7,8 @@ #include #include #include +#include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -151,10 +153,4 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) return ret; } -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif diff --git a/arch/cris/include/asm/bitops.h b/arch/cris/include/asm/bitops.h index 053c17b36559..bd49a546f4f5 100644 --- a/arch/cris/include/asm/bitops.h +++ b/arch/cris/include/asm/bitops.h @@ -21,6 +21,7 @@ #include #include #include +#include /* * set_bit - Atomically set a bit in memory @@ -42,7 +43,7 @@ * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ @@ -84,12 +85,6 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr) return retval; } -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - /** * test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to clear -- cgit v1.2.3 From d038c0e8380fa8cae049bee8d81a5672cd159013 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:37 +0100 Subject: arch,frv: Convert smp_mb__*() Because: arch/frv/include/asm/smp.h:#error SMP not supported smp_mb() is barrier() and we can use the default implementation that uses smp_mb(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-n296g51yzdu5ru1vp7mccxmf@git.kernel.org Cc: David Howells Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/frv/include/asm/atomic.h | 7 +------ arch/frv/include/asm/bitops.h | 6 ------ 2 files changed, 1 insertion(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h index b86329d0e316..f6c3a1690101 100644 --- a/arch/frv/include/asm/atomic.h +++ b/arch/frv/include/asm/atomic.h @@ -17,6 +17,7 @@ #include #include #include +#include #ifdef CONFIG_SMP #error not SMP safe @@ -29,12 +30,6 @@ * We do not have SMP systems, so we don't have to deal with that. */ -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #define ATOMIC_INIT(i) { (i) } #define atomic_read(v) (*(volatile int *)&(v)->counter) #define atomic_set(v, i) (((v)->counter) = (i)) diff --git a/arch/frv/include/asm/bitops.h b/arch/frv/include/asm/bitops.h index 57bf85db893f..96de220ef131 100644 --- a/arch/frv/include/asm/bitops.h +++ b/arch/frv/include/asm/bitops.h @@ -25,12 +25,6 @@ #include -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS static inline unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v) -- cgit v1.2.3 From 94cf42f823bc904305b0ee93a09bcd51ba380497 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,hexagon: Convert smp_mb__*() Hexagon uses asm-gemeric/barrier.h and its smp_mb() is barrier(). Therefore we can use the default implementation that uses smp_mb(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-87irqrrbgizeojjfdqhypud3@git.kernel.org Cc: Linus Torvalds Cc: Richard Kuo Cc: Vineet Gupta Cc: linux-hexagon@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/hexagon/include/asm/atomic.h | 6 +----- arch/hexagon/include/asm/bitops.h | 4 +--- 2 files changed, 2 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/hexagon/include/asm/atomic.h b/arch/hexagon/include/asm/atomic.h index 17dc63780c06..de916b11bff5 100644 --- a/arch/hexagon/include/asm/atomic.h +++ b/arch/hexagon/include/asm/atomic.h @@ -24,6 +24,7 @@ #include #include +#include #define ATOMIC_INIT(i) { (i) } @@ -176,9 +177,4 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) #define atomic_inc_return(v) (atomic_add_return(1, v)) #define atomic_dec_return(v) (atomic_sub_return(1, v)) -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif diff --git a/arch/hexagon/include/asm/bitops.h b/arch/hexagon/include/asm/bitops.h index 9b1e4afbab3c..5e4a59b3ec1b 100644 --- a/arch/hexagon/include/asm/bitops.h +++ b/arch/hexagon/include/asm/bitops.h @@ -25,12 +25,10 @@ #include #include #include +#include #ifdef __KERNEL__ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - /* * The offset calculations for these are based on BITS_PER_LONG == 32 * (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access), -- cgit v1.2.3 From 0cd64efb61f1e68be26bd5121ccff3c779dc488b Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,ia64: Convert smp_mb__*() ia64 atomic ops are full barriers; implement the new smp_mb__{before,after}_atomic(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-hyp7yj68cmqz1nqbfpr541ca@git.kernel.org Cc: Akinobu Mita Cc: Fenghua Yu Cc: Linus Torvalds Cc: Tony Luck Cc: Will Deacon Cc: linux-ia64@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/ia64/include/asm/atomic.h | 7 +------ arch/ia64/include/asm/barrier.h | 3 +++ arch/ia64/include/asm/bitops.h | 6 ++---- 3 files changed, 6 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h index 6e6fe1839f5d..0f8bf48dadf3 100644 --- a/arch/ia64/include/asm/atomic.h +++ b/arch/ia64/include/asm/atomic.h @@ -15,6 +15,7 @@ #include #include +#include #define ATOMIC_INIT(i) { (i) } @@ -208,10 +209,4 @@ atomic64_add_negative (__s64 i, atomic64_t *v) #define atomic64_inc(v) atomic64_add(1, (v)) #define atomic64_dec(v) atomic64_sub(1, (v)) -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* _ASM_IA64_ATOMIC_H */ diff --git a/arch/ia64/include/asm/barrier.h b/arch/ia64/include/asm/barrier.h index d0a69aa35e27..a48957c7b445 100644 --- a/arch/ia64/include/asm/barrier.h +++ b/arch/ia64/include/asm/barrier.h @@ -55,6 +55,9 @@ #endif +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + /* * IA64 GCC turns volatile stores into st.rel and volatile loads into ld.acq no * need for asm trickery! diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h index feb8117ed06a..71e8145243ee 100644 --- a/arch/ia64/include/asm/bitops.h +++ b/arch/ia64/include/asm/bitops.h @@ -16,6 +16,7 @@ #include #include #include +#include /** * set_bit - Atomically set a bit in memory @@ -65,9 +66,6 @@ __set_bit (int nr, volatile void *addr) *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31)); } -#define smp_mb__before_clear_bit() barrier(); -#define smp_mb__after_clear_bit() barrier(); - /** * clear_bit - Clears a bit in memory * @nr: Bit to clear @@ -75,7 +73,7 @@ __set_bit (int nr, volatile void *addr) * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static __inline__ void -- cgit v1.2.3 From 89607d5e2928d49bb64669d6d1e30e933a33f817 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,m32r: Convert smp_mb__*() M32r uses asm-generic/barrier.h and its smp_mb() is barrier(); therefore we can use the generic versions which default to smp_mb(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-wh6xljltyvmpy9t0bc80k1fy@git.kernel.org Cc: Hirokazu Takata Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Cc: linux-m32r-ja@ml.linux-m32r.org Cc: linux-m32r@ml.linux-m32r.org Signed-off-by: Ingo Molnar --- arch/m32r/include/asm/atomic.h | 7 +------ arch/m32r/include/asm/bitops.h | 6 ++---- 2 files changed, 3 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/m32r/include/asm/atomic.h b/arch/m32r/include/asm/atomic.h index 0d81697c326c..8ad0ed4182a5 100644 --- a/arch/m32r/include/asm/atomic.h +++ b/arch/m32r/include/asm/atomic.h @@ -13,6 +13,7 @@ #include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -308,10 +309,4 @@ static __inline__ void atomic_set_mask(unsigned long mask, atomic_t *addr) local_irq_restore(flags); } -/* Atomic operations are already serializing on m32r */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* _ASM_M32R_ATOMIC_H */ diff --git a/arch/m32r/include/asm/bitops.h b/arch/m32r/include/asm/bitops.h index d3dea9ac7d4e..86ba2b42a6cf 100644 --- a/arch/m32r/include/asm/bitops.h +++ b/arch/m32r/include/asm/bitops.h @@ -21,6 +21,7 @@ #include #include #include +#include /* * These have to be done with inline assembly: that way the bit-setting @@ -73,7 +74,7 @@ static __inline__ void set_bit(int nr, volatile void * addr) * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static __inline__ void clear_bit(int nr, volatile void * addr) @@ -103,9 +104,6 @@ static __inline__ void clear_bit(int nr, volatile void * addr) local_irq_restore(flags); } -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - /** * change_bit - Toggle a bit in memory * @nr: Bit to clear -- cgit v1.2.3 From 2db56e8606016e33903c64feaed989ffecd66a1b Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,m68k: Convert smp_mb__*() m68k uses asm-generic/barrier.h and its smp_mb() is barrier(), therefore we can use the generic versions that use smp_mb(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-s5dvosrb7qhvpmtaffwfn0zg@git.kernel.org Cc: Geert Uytterhoeven Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Cc: linux-m68k@lists.linux-m68k.org Signed-off-by: Ingo Molnar --- arch/m68k/include/asm/atomic.h | 8 +------- arch/m68k/include/asm/bitops.h | 7 +------ 2 files changed, 2 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index f4e32de263a7..55695212a2ae 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -4,6 +4,7 @@ #include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -209,11 +210,4 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u) return c; } - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* __ARCH_M68K_ATOMIC __ */ diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index c6baa913592a..b4a9b0d5928d 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -13,6 +13,7 @@ #endif #include +#include /* * Bit access functions vary across the ColdFire and 68k families. @@ -67,12 +68,6 @@ static inline void bfset_mem_set_bit(int nr, volatile unsigned long *vaddr) #define __set_bit(nr, vaddr) set_bit(nr, vaddr) -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - static inline void bclr_reg_clear_bit(int nr, volatile unsigned long *vaddr) { char *p = (char *)vaddr + (nr ^ 31) / 8; -- cgit v1.2.3 From 40074dece684fc61ab72cfc1689d564cba1c5f64 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,metag: Convert smp_mb__*() Implement the new barriers; as per the old versions the metag atomic imply a full barrier. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-dqnyo215kq38wi4xcxnbpjw3@git.kernel.org Cc: James Hogan Cc: Linus Torvalds Cc: Will Deacon Cc: linux-kernel@vger.kernel.org Cc: linux-metag@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/metag/include/asm/atomic.h | 6 +----- arch/metag/include/asm/barrier.h | 3 +++ arch/metag/include/asm/bitops.h | 6 ------ 3 files changed, 4 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/metag/include/asm/atomic.h b/arch/metag/include/asm/atomic.h index 307ecd2bd9a1..470e365f04ea 100644 --- a/arch/metag/include/asm/atomic.h +++ b/arch/metag/include/asm/atomic.h @@ -4,6 +4,7 @@ #include #include #include +#include #if defined(CONFIG_METAG_ATOMICITY_IRQSOFF) /* The simple UP case. */ @@ -39,11 +40,6 @@ #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v) diff --git a/arch/metag/include/asm/barrier.h b/arch/metag/include/asm/barrier.h index 5d6b4b407dda..d1768c6f5b18 100644 --- a/arch/metag/include/asm/barrier.h +++ b/arch/metag/include/asm/barrier.h @@ -97,4 +97,7 @@ do { \ ___p1; \ }) +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + #endif /* _ASM_METAG_BARRIER_H */ diff --git a/arch/metag/include/asm/bitops.h b/arch/metag/include/asm/bitops.h index c0d0df0d1378..2671134ee745 100644 --- a/arch/metag/include/asm/bitops.h +++ b/arch/metag/include/asm/bitops.h @@ -5,12 +5,6 @@ #include #include -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - #ifdef CONFIG_SMP /* * These functions are the basis of our bit ops. -- cgit v1.2.3 From 91bbefe6b0fcd2968c34a5a566bda870477afc82 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,mips: Convert smp_mb__*() MIPS is interesting and has hardware variants that reorder over ll/sc as well as those that do not. Implement the 2 new barrier functions as per the old barriers. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-9ph49jbae3hol9v721sbc2g6@git.kernel.org Cc: Linus Torvalds Cc: Maciej W. Rozycki" Cc: Ralf Baechle Cc: Will Deacon Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ingo Molnar --- arch/mips/include/asm/atomic.h | 9 --------- arch/mips/include/asm/barrier.h | 3 +++ arch/mips/include/asm/bitops.h | 11 ++--------- arch/mips/kernel/irq.c | 4 ++-- 4 files changed, 7 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index e8eb3d53a241..37b2befe651a 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -761,13 +761,4 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u) #endif /* CONFIG_64BIT */ -/* - * atomic*_return operations are serializing but not the non-*_return - * versions. - */ -#define smp_mb__before_atomic_dec() smp_mb__before_llsc() -#define smp_mb__after_atomic_dec() smp_llsc_mb() -#define smp_mb__before_atomic_inc() smp_mb__before_llsc() -#define smp_mb__after_atomic_inc() smp_llsc_mb() - #endif /* _ASM_ATOMIC_H */ diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index e1aa4e4c2984..d0101dd0575e 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -195,4 +195,7 @@ do { \ ___p1; \ }) +#define smp_mb__before_atomic() smp_mb__before_llsc() +#define smp_mb__after_atomic() smp_llsc_mb() + #endif /* __ASM_BARRIER_H */ diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 6a65d49e2c0d..7c8816f7b7c4 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -37,13 +37,6 @@ #define __EXT "dext " #endif -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() smp_mb__before_llsc() -#define smp_mb__after_clear_bit() smp_llsc_mb() - - /* * These are the "slower" versions of the functions and are in bitops.c. * These functions call raw_local_irq_{save,restore}(). @@ -120,7 +113,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) @@ -175,7 +168,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) */ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr) { - smp_mb__before_clear_bit(); + smp_mb__before_atomic(); clear_bit(nr, addr); } diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index d1fea7a054be..1818da4dbb85 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -62,9 +62,9 @@ void __init alloc_legacy_irqno(void) void free_irqno(unsigned int irq) { - smp_mb__before_clear_bit(); + smp_mb__before_atomic(); clear_bit(irq, irq_map); - smp_mb__after_clear_bit(); + smp_mb__after_atomic(); } /* -- cgit v1.2.3 From 9424cdf0fc7f768f20daef77980da9617a76679b Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,mn10300: Convert smp_mb__*() mn10300 fully relies on asm-generic/barrier.h and therefore its smp_mb() is barrier(). We can use the default implementation. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-wotyeoj99h1dpojjeest2jbk@git.kernel.org Cc: David Howells Cc: Koichi Yasutake Cc: Linus Torvalds Cc: linux-am33-list@redhat.com Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/mn10300/include/asm/atomic.h | 7 +------ arch/mn10300/include/asm/bitops.h | 4 +--- arch/mn10300/mm/tlb-smp.c | 4 ++-- 3 files changed, 4 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/mn10300/include/asm/atomic.h b/arch/mn10300/include/asm/atomic.h index 975e1841ca64..cadeb1e2cdfc 100644 --- a/arch/mn10300/include/asm/atomic.h +++ b/arch/mn10300/include/asm/atomic.h @@ -13,6 +13,7 @@ #include #include +#include #ifndef CONFIG_SMP #include @@ -234,12 +235,6 @@ static inline void atomic_set_mask(unsigned long mask, unsigned long *addr) #endif } -/* Atomic operations are already serializing on MN10300??? */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* __KERNEL__ */ #endif /* CONFIG_SMP */ #endif /* _ASM_ATOMIC_H */ diff --git a/arch/mn10300/include/asm/bitops.h b/arch/mn10300/include/asm/bitops.h index 596bb2706d81..fe6f8e2c3617 100644 --- a/arch/mn10300/include/asm/bitops.h +++ b/arch/mn10300/include/asm/bitops.h @@ -18,9 +18,7 @@ #define __ASM_BITOPS_H #include - -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() +#include /* * set bit diff --git a/arch/mn10300/mm/tlb-smp.c b/arch/mn10300/mm/tlb-smp.c index 3e57faf04083..e5d0ef722bfa 100644 --- a/arch/mn10300/mm/tlb-smp.c +++ b/arch/mn10300/mm/tlb-smp.c @@ -78,9 +78,9 @@ void smp_flush_tlb(void *unused) else local_flush_tlb_page(flush_mm, flush_va); - smp_mb__before_clear_bit(); + smp_mb__before_atomic(); cpumask_clear_cpu(cpu_id, &flush_cpumask); - smp_mb__after_clear_bit(); + smp_mb__after_atomic(); out: put_cpu(); } -- cgit v1.2.3 From 0f5c6f9e18e14b4ebd83dd08e81ca8143d43de28 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,openrisc: Convert smp_mb__*() Openrisc fully relies on asm-generic/barrier.h and therefore its smp_mb() is barrier(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-sxgxgqag9tond4kji07d22oh@git.kernel.org Cc: Jonas Bonn Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Cc: linux@lists.openrisc.net Signed-off-by: Ingo Molnar --- arch/openrisc/include/asm/bitops.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h index 2c64f2228dc7..3003cdad561b 100644 --- a/arch/openrisc/include/asm/bitops.h +++ b/arch/openrisc/include/asm/bitops.h @@ -27,14 +27,7 @@ #include #include - -/* - * clear_bit may not imply a memory barrier - */ -#ifndef smp_mb__before_clear_bit -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() -#endif +#include #include #include -- cgit v1.2.3 From e4a65e9d395feee195f1219d708e9eb2a2d4b583 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:36 +0100 Subject: arch,parisc: Convert smp_mb__*() parisc fully relies on asm-generic/barrier.h, therefore its smp_mb() is barrier and the default implementation suffices. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-mxs4aubiyesi79v8xx53093q@git.kernel.org Cc: Helge Deller Cc: James E.J. Bottomley Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Cc: linux-parisc@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/parisc/include/asm/atomic.h | 6 +----- arch/parisc/include/asm/bitops.h | 4 +--- 2 files changed, 2 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h index 472886ceab1d..0be2db2c7d44 100644 --- a/arch/parisc/include/asm/atomic.h +++ b/arch/parisc/include/asm/atomic.h @@ -7,6 +7,7 @@ #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -143,11 +144,6 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u) #define ATOMIC_INIT(i) { (i) } -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - #ifdef CONFIG_64BIT #define ATOMIC64_INIT(i) { (i) } diff --git a/arch/parisc/include/asm/bitops.h b/arch/parisc/include/asm/bitops.h index 8c9b631d2a78..3f9406d9b9d6 100644 --- a/arch/parisc/include/asm/bitops.h +++ b/arch/parisc/include/asm/bitops.h @@ -8,6 +8,7 @@ #include #include /* for BITS_PER_LONG/SHIFT_PER_LONG */ #include +#include #include /* @@ -19,9 +20,6 @@ #define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1)) -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() - /* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion * on use of volatile and __*_bit() (set/clear/change): * *_bit() want use of volatile. -- cgit v1.2.3 From c645073f7e4f073e1ebcd0f0d91652c4468b8364 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,powerpc: Convert smp_mb__*() Powerpc allows reordering over its ll/sc implementation. Implement the two new barriers as appropriate. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-gg2ffgq32sjgy9b8lj6m3hsc@git.kernel.org Cc: Benjamin Herrenschmidt Cc: Linus Torvalds Cc: Mahesh Salgaonkar Cc: Paul Gortmaker Cc: Paul Mackerras Cc: Will Deacon Cc: linux-kernel@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Ingo Molnar --- arch/powerpc/include/asm/atomic.h | 6 +----- arch/powerpc/include/asm/barrier.h | 3 +++ arch/powerpc/include/asm/bitops.h | 6 +----- arch/powerpc/kernel/crash.c | 2 +- 4 files changed, 6 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h index e3b1d41c89be..28992d012926 100644 --- a/arch/powerpc/include/asm/atomic.h +++ b/arch/powerpc/include/asm/atomic.h @@ -8,6 +8,7 @@ #ifdef __KERNEL__ #include #include +#include #define ATOMIC_INIT(i) { (i) } @@ -270,11 +271,6 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v) } #define atomic_dec_if_positive atomic_dec_if_positive -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - #ifdef __powerpc64__ #define ATOMIC64_INIT(i) { (i) } diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index f89da808ce31..bab79a110c7b 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -84,4 +84,7 @@ do { \ ___p1; \ }) +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() + #endif /* _ASM_POWERPC_BARRIER_H */ diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index a5e9a7d494d8..bd3bd573d0ae 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -51,11 +51,7 @@ #define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit)) #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) -/* - * clear_bit doesn't imply a memory barrier - */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#include /* Macro for generating the ***_bits() functions */ #define DEFINE_BITOP(fn, op, prefix) \ diff --git a/arch/powerpc/kernel/crash.c b/arch/powerpc/kernel/crash.c index 18d7c80ddeb9..51dbace3269b 100644 --- a/arch/powerpc/kernel/crash.c +++ b/arch/powerpc/kernel/crash.c @@ -81,7 +81,7 @@ void crash_ipi_callback(struct pt_regs *regs) } atomic_inc(&cpus_in_crash); - smp_mb__after_atomic_inc(); + smp_mb__after_atomic(); /* * Starting the kdump boot. -- cgit v1.2.3 From 0e530747c69f1e191f101a925bb4051894e5c7b0 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,s390: Convert smp_mb__*() As per the existing implementation; implement the new one using smp_mb(). AFAICT the s390 compare-and-swap does imply a barrier, however there are some immediate ops that seem to be singly-copy atomic and do not imply a barrier. One such is the "ni" op (which would be and-immediate) which is used for the constant clear_bit implementation. Therefore s390 needs full barriers for the {before,after} atomic ops. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-kme5dz5hcobpnufnnkh1ech2@git.kernel.org Cc: Chen Gang Cc: Heiko Carstens Cc: Linus Torvalds Cc: Martin Schwidefsky Cc: Will Deacon Cc: linux390@de.ibm.com Cc: linux-kernel@vger.kernel.org Cc: linux-s390@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/s390/include/asm/atomic.h | 5 ----- arch/s390/include/asm/barrier.h | 5 +++-- 2 files changed, 3 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h index 1d4706114a45..fa934fe080c1 100644 --- a/arch/s390/include/asm/atomic.h +++ b/arch/s390/include/asm/atomic.h @@ -412,9 +412,4 @@ static inline long long atomic64_dec_if_positive(atomic64_t *v) #define atomic64_dec_and_test(_v) (atomic64_sub_return(1, _v) == 0) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - #endif /* __ARCH_S390_ATOMIC__ */ diff --git a/arch/s390/include/asm/barrier.h b/arch/s390/include/asm/barrier.h index 578680f6207a..19ff956b752b 100644 --- a/arch/s390/include/asm/barrier.h +++ b/arch/s390/include/asm/barrier.h @@ -27,8 +27,9 @@ #define smp_rmb() rmb() #define smp_wmb() wmb() #define smp_read_barrier_depends() read_barrier_depends() -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() + +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() #define set_mb(var, value) do { var = value; mb(); } while (0) -- cgit v1.2.3 From 57aa6a76864dfbb5450728199c37c02f401586ec Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,score: Convert smp_mb__*() score fully relies on asm-generic/barrier.h, so it can use its default implementation. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Acked-by: Lennox Wu Link: http://lkml.kernel.org/n/tip-4mv9svf28lnotjpfuza8urh8@git.kernel.org Cc: Chen Liqin Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/score/include/asm/bitops.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/score/include/asm/bitops.h b/arch/score/include/asm/bitops.h index a304096b1894..c1bf8d6d0fb0 100644 --- a/arch/score/include/asm/bitops.h +++ b/arch/score/include/asm/bitops.h @@ -2,12 +2,7 @@ #define _ASM_SCORE_BITOPS_H #include /* swab32 */ - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() +#include #include #include -- cgit v1.2.3 From 603228bcb8da90f8f8a5cdd8de74178f6c3e7e13 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,sh: Convert smp_mb__*() SH can use the asm-generic/barrier.h implementation since that uses smp_mb(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-2z962by2ppzcd984ybw2mwdw@git.kernel.org Cc: Linus Torvalds Cc: linux-kernel@vger.kernel.org Cc: linux-sh@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/sh/include/asm/atomic.h | 6 +----- arch/sh/include/asm/bitops.h | 7 +------ 2 files changed, 2 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h index f4c1c20bcdf6..f57b8a6743b3 100644 --- a/arch/sh/include/asm/atomic.h +++ b/arch/sh/include/asm/atomic.h @@ -10,6 +10,7 @@ #include #include #include +#include #define ATOMIC_INIT(i) { (i) } @@ -62,9 +63,4 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u) return c; } -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - #endif /* __ASM_SH_ATOMIC_H */ diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h index ea8706d94f08..fc8e652cf173 100644 --- a/arch/sh/include/asm/bitops.h +++ b/arch/sh/include/asm/bitops.h @@ -9,6 +9,7 @@ /* For __swab32 */ #include +#include #ifdef CONFIG_GUSA_RB #include @@ -22,12 +23,6 @@ #include #endif -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() - #ifdef CONFIG_SUPERH32 static inline unsigned long ffz(unsigned long word) { -- cgit v1.2.3 From 56d3648948c202e8b89cd786a004c451a3eb264f Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,sparc: Convert smp_mb__*() sparc32: fully relies on asm-generic/barrier.h and thus can use its implementation. sparc64: is strongly ordered and its atomic ops imply a full barrier, implement the new primitives using barrier(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Acked-by: David S. Miller Link: http://lkml.kernel.org/n/tip-2cla9ubpd8chrntnm7e4zdt4@git.kernel.org Cc: Linus Torvalds Cc: Will Deacon Cc: linux-kernel@vger.kernel.org Cc: sparclinux@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/sparc/include/asm/atomic_32.h | 7 +------ arch/sparc/include/asm/atomic_64.h | 7 +------ arch/sparc/include/asm/barrier_64.h | 3 +++ arch/sparc/include/asm/bitops_32.h | 3 --- arch/sparc/include/asm/bitops_64.h | 4 +--- 5 files changed, 6 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/sparc/include/asm/atomic_32.h b/arch/sparc/include/asm/atomic_32.h index 905832aa9e9e..f08fe51b264d 100644 --- a/arch/sparc/include/asm/atomic_32.h +++ b/arch/sparc/include/asm/atomic_32.h @@ -14,6 +14,7 @@ #include #include +#include #include @@ -52,10 +53,4 @@ extern void atomic_set(atomic_t *, int); #define atomic_dec_and_test(v) (atomic_dec_return(v) == 0) #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* !(__ARCH_SPARC_ATOMIC__) */ diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h index be56a244c9cf..8b2f1bde2889 100644 --- a/arch/sparc/include/asm/atomic_64.h +++ b/arch/sparc/include/asm/atomic_64.h @@ -9,6 +9,7 @@ #include #include +#include #define ATOMIC_INIT(i) { (i) } #define ATOMIC64_INIT(i) { (i) } @@ -108,10 +109,4 @@ static inline long atomic64_add_unless(atomic64_t *v, long a, long u) extern long atomic64_dec_if_positive(atomic64_t *v); -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* !(__ARCH_SPARC64_ATOMIC__) */ diff --git a/arch/sparc/include/asm/barrier_64.h b/arch/sparc/include/asm/barrier_64.h index b5aad964558e..305dcc3dc721 100644 --- a/arch/sparc/include/asm/barrier_64.h +++ b/arch/sparc/include/asm/barrier_64.h @@ -68,4 +68,7 @@ do { \ ___p1; \ }) +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + #endif /* !(__SPARC64_BARRIER_H) */ diff --git a/arch/sparc/include/asm/bitops_32.h b/arch/sparc/include/asm/bitops_32.h index 25a676653d45..88c9a962502c 100644 --- a/arch/sparc/include/asm/bitops_32.h +++ b/arch/sparc/include/asm/bitops_32.h @@ -90,9 +90,6 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) #include -#define smp_mb__before_clear_bit() do { } while(0) -#define smp_mb__after_clear_bit() do { } while(0) - #include #include #include diff --git a/arch/sparc/include/asm/bitops_64.h b/arch/sparc/include/asm/bitops_64.h index 29011cc0e4be..f1a051ca301a 100644 --- a/arch/sparc/include/asm/bitops_64.h +++ b/arch/sparc/include/asm/bitops_64.h @@ -13,6 +13,7 @@ #include #include +#include extern int test_and_set_bit(unsigned long nr, volatile unsigned long *addr); extern int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr); @@ -23,9 +24,6 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr); #include -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - #include #include #include -- cgit v1.2.3 From ce3609f93445846f7b5a5b4bacb236a9bdc35216 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,tile: Convert smp_mb__*() Implement the new smp_mb__* ops as per the old ones. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Acked-by: Chris Metcalf Link: http://lkml.kernel.org/n/tip-euuabnf5a3u23fy4fq8m3jcg@git.kernel.org Cc: Akinobu Mita Cc: Chen Gang Cc: Geert Uytterhoeven Cc: Linus Torvalds Cc: Mathieu Desnoyers Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/tile/include/asm/atomic_32.h | 10 ---------- arch/tile/include/asm/atomic_64.h | 6 ------ arch/tile/include/asm/barrier.h | 14 ++++++++++++++ arch/tile/include/asm/bitops.h | 1 + arch/tile/include/asm/bitops_32.h | 8 ++------ arch/tile/include/asm/bitops_64.h | 4 ---- 6 files changed, 17 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h index 1ad4a1f7d42b..1b109fad9fff 100644 --- a/arch/tile/include/asm/atomic_32.h +++ b/arch/tile/include/asm/atomic_32.h @@ -169,16 +169,6 @@ static inline void atomic64_set(atomic64_t *v, long long n) #define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL) -/* - * We need to barrier before modifying the word, since the _atomic_xxx() - * routines just tns the lock and then read/modify/write of the word. - * But after the word is updated, the routine issues an "mf" before returning, - * and since it's a function call, we don't even need a compiler barrier. - */ -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_dec() do { } while (0) -#define smp_mb__after_atomic_inc() do { } while (0) #endif /* !__ASSEMBLY__ */ diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h index ad220eed05fc..7b11c5fadd42 100644 --- a/arch/tile/include/asm/atomic_64.h +++ b/arch/tile/include/asm/atomic_64.h @@ -105,12 +105,6 @@ static inline long atomic64_add_unless(atomic64_t *v, long a, long u) #define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) -/* Atomic dec and inc don't implement barrier, so provide them if needed. */ -#define smp_mb__before_atomic_dec() smp_mb() -#define smp_mb__after_atomic_dec() smp_mb() -#define smp_mb__before_atomic_inc() smp_mb() -#define smp_mb__after_atomic_inc() smp_mb() - /* Define this to indicate that cmpxchg is an efficient operation. */ #define __HAVE_ARCH_CMPXCHG diff --git a/arch/tile/include/asm/barrier.h b/arch/tile/include/asm/barrier.h index b5a05d050a8f..96a42ae79f4d 100644 --- a/arch/tile/include/asm/barrier.h +++ b/arch/tile/include/asm/barrier.h @@ -72,6 +72,20 @@ mb_incoherent(void) #define mb() fast_mb() #define iob() fast_iob() +#ifndef __tilegx__ /* 32 bit */ +/* + * We need to barrier before modifying the word, since the _atomic_xxx() + * routines just tns the lock and then read/modify/write of the word. + * But after the word is updated, the routine issues an "mf" before returning, + * and since it's a function call, we don't even need a compiler barrier. + */ +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() do { } while (0) +#else /* 64 bit */ +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() +#endif + #include #endif /* !__ASSEMBLY__ */ diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h index d5a206865036..20caa346ac06 100644 --- a/arch/tile/include/asm/bitops.h +++ b/arch/tile/include/asm/bitops.h @@ -17,6 +17,7 @@ #define _ASM_TILE_BITOPS_H #include +#include #ifndef _LINUX_BITOPS_H #error only can be included directly diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h index 386865ad2f55..bbf7b666f21d 100644 --- a/arch/tile/include/asm/bitops_32.h +++ b/arch/tile/include/asm/bitops_32.h @@ -49,8 +49,8 @@ static inline void set_bit(unsigned nr, volatile unsigned long *addr) * restricted to acting on a single-word quantity. * * clear_bit() may not contain a memory barrier, so if it is used for - * locking purposes, you should call smp_mb__before_clear_bit() and/or - * smp_mb__after_clear_bit() to ensure changes are visible on other cpus. + * locking purposes, you should call smp_mb__before_atomic() and/or + * smp_mb__after_atomic() to ensure changes are visible on other cpus. */ static inline void clear_bit(unsigned nr, volatile unsigned long *addr) { @@ -121,10 +121,6 @@ static inline int test_and_change_bit(unsigned nr, return (_atomic_xor(addr, mask) & mask) != 0; } -/* See discussion at smp_mb__before_atomic_dec() in . */ -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() do {} while (0) - #include #endif /* _ASM_TILE_BITOPS_32_H */ diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h index ad34cd056085..bb1a29221fcd 100644 --- a/arch/tile/include/asm/bitops_64.h +++ b/arch/tile/include/asm/bitops_64.h @@ -32,10 +32,6 @@ static inline void clear_bit(unsigned nr, volatile unsigned long *addr) __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask); } -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() - - static inline void change_bit(unsigned nr, volatile unsigned long *addr) { unsigned long mask = (1UL << (nr % BITS_PER_LONG)); -- cgit v1.2.3 From d00a569284b1340c16fe2c148099e077ea09ebc9 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,x86: Convert smp_mb__*() x86 is strongly ordered and all its atomic ops imply a full barrier. Implement the two new primitives as the old ones were. Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-knswsr5mldkr0w1lrdxvc81w@git.kernel.org Cc: Dave Jones Cc: Jesse Brandeburg Cc: Linus Torvalds Cc: Michel Lespinasse Cc: Will Deacon Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar --- arch/x86/include/asm/atomic.h | 7 +------ arch/x86/include/asm/barrier.h | 4 ++++ arch/x86/include/asm/bitops.h | 6 ++---- arch/x86/include/asm/sync_bitops.h | 2 +- arch/x86/kernel/apic/hw_nmi.c | 2 +- 5 files changed, 9 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h index b17f4f48ecd7..6dd1c7dd0473 100644 --- a/arch/x86/include/asm/atomic.h +++ b/arch/x86/include/asm/atomic.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -243,12 +244,6 @@ static inline void atomic_or_long(unsigned long *v1, unsigned long v2) : : "r" ((unsigned)(mask)), "m" (*(addr)) \ : "memory") -/* Atomic operations are already serializing on x86 */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #ifdef CONFIG_X86_32 # include #else diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index 69bbb4845020..5c7198cca5ed 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -137,6 +137,10 @@ do { \ #endif +/* Atomic operations are already serializing on x86 */ +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + /* * Stop RDTSC speculation. This is needed when you need to use RDTSC * (or get_cycles or vread that possibly accesses the TSC) in a defined diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 9fc1af74dc83..afcd35d331de 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -15,6 +15,7 @@ #include #include #include +#include #if BITS_PER_LONG == 32 # define _BITOPS_LONG_SHIFT 5 @@ -102,7 +103,7 @@ static inline void __set_bit(long nr, volatile unsigned long *addr) * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static __always_inline void @@ -156,9 +157,6 @@ static inline void __clear_bit_unlock(long nr, volatile unsigned long *addr) __clear_bit(nr, addr); } -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - /** * __change_bit - Toggle a bit in memory * @nr: the bit to change diff --git a/arch/x86/include/asm/sync_bitops.h b/arch/x86/include/asm/sync_bitops.h index 05af3b31d522..f28a24b51dc7 100644 --- a/arch/x86/include/asm/sync_bitops.h +++ b/arch/x86/include/asm/sync_bitops.h @@ -41,7 +41,7 @@ static inline void sync_set_bit(long nr, volatile unsigned long *addr) * * sync_clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() * in order to ensure changes are visible on other processors. */ static inline void sync_clear_bit(long nr, volatile unsigned long *addr) diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c index a698d7165c96..eab67047dec3 100644 --- a/arch/x86/kernel/apic/hw_nmi.c +++ b/arch/x86/kernel/apic/hw_nmi.c @@ -57,7 +57,7 @@ void arch_trigger_all_cpu_backtrace(void) } clear_bit(0, &backtrace_flag); - smp_mb__after_clear_bit(); + smp_mb__after_atomic(); } static int __kprobes -- cgit v1.2.3 From 09a01c0ccb1837abb28afcfdd668fa0dfabed928 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Thu, 13 Mar 2014 19:00:35 +0100 Subject: arch,xtensa: Convert smp_mb__*() Xtensa SMP has compare-and-swap which is fully serializing, therefore its exising smp_mb__{before,after}_clear_bit() appear unduly heavy. Implement the new barriers as barrier(). Signed-off-by: Peter Zijlstra Acked-by: Paul E. McKenney Link: http://lkml.kernel.org/n/tip-e9rqjxr1m1ejsob9p433kmji@git.kernel.org Cc: Chris Zankel Cc: Geert Uytterhoeven Cc: Linus Torvalds Cc: Mathieu Desnoyers Cc: Max Filippov Cc: linux-kernel@vger.kernel.org Cc: linux-xtensa@linux-xtensa.org Signed-off-by: Ingo Molnar --- arch/xtensa/include/asm/atomic.h | 7 +------ arch/xtensa/include/asm/barrier.h | 3 +++ arch/xtensa/include/asm/bitops.h | 4 +--- 3 files changed, 5 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h index e7fb447bce8e..e5103b47a8ce 100644 --- a/arch/xtensa/include/asm/atomic.h +++ b/arch/xtensa/include/asm/atomic.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ #include #include +#include #define ATOMIC_INIT(i) { (i) } @@ -387,12 +388,6 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v) #endif } -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - #endif /* __KERNEL__ */ #endif /* _XTENSA_ATOMIC_H */ diff --git a/arch/xtensa/include/asm/barrier.h b/arch/xtensa/include/asm/barrier.h index 0a24b04d6b21..5b88774c75ab 100644 --- a/arch/xtensa/include/asm/barrier.h +++ b/arch/xtensa/include/asm/barrier.h @@ -13,6 +13,9 @@ #define rmb() barrier() #define wmb() mb() +#define smp_mb__before_atomic() barrier() +#define smp_mb__after_atomic() barrier() + #include #endif /* _XTENSA_SYSTEM_H */ diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h index 7b6873ae84c2..3f44fa2a53e9 100644 --- a/arch/xtensa/include/asm/bitops.h +++ b/arch/xtensa/include/asm/bitops.h @@ -21,9 +21,7 @@ #include #include - -#define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#include #include -- cgit v1.2.3 From a4c1d6c75822eb76b818cbffda2cf26a3e3ba5ac Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 15 Apr 2014 13:07:42 +0200 Subject: ARM: at91/dt: sam9rl: add lcd, adc, usb gadget and pwm support This patch adds support for the ADC, LCD, USB gadget and PWM controllers to the at91sam9rl. It also reorders the pinctrl_spi0 as it was not correctly sorted. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9rl.dtsi | 265 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 256 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 63e1784d272c..6202e161314a 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { model = "Atmel AT91SAM9RL family SoC"; @@ -32,6 +33,7 @@ i2c1 = &i2c1; ssc0 = &ssc0; ssc1 = &ssc1; + pwm0 = &pwm0; }; cpus { @@ -48,12 +50,31 @@ reg = <0x20000000 0x04000000>; }; + clocks { + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + fb0: fb@00500000 { + compatible = "atmel,at91sam9rl-lcdc"; + reg = <0x00500000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fb>; + clocks = <&lcd_clk>, <&lcd_clk>; + clock-names = "hclk", "lcdc_clk"; + status = "disabled"; + }; + nand0: nand@40000000 { compatible = "atmel,at91rm9200-nand"; #address-cells = <1>; @@ -187,6 +208,16 @@ status = "disabled"; }; + pwm0: pwm@fffc8000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xfffc8000 0x300>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; + #pwm-cells = <3>; + clocks = <&pwm_clk>; + clock-names = "pwm_clk"; + status = "disabled"; + }; + spi0: spi@fffcc000 { #address-cells = <1>; #size-cells = <0>; @@ -200,6 +231,111 @@ status = "disabled"; }; + adc0: adc@fffd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-adc"; + reg = <0xfffd0000 0x100>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&adc_clk>, <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-use-external-triggers; + atmel,adc-channels-used = <0x3f>; + atmel,adc-vref = <3300>; + atmel,adc-startup-time = <40>; + atmel,adc-res = <8 10>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-use-res = "highres"; + + trigger@0 { + reg = <0>; + trigger-name = "timer-counter-0"; + trigger-value = <0x1>; + }; + trigger@1 { + reg = <1>; + trigger-name = "timer-counter-1"; + trigger-value = <0x3>; + }; + + trigger@2 { + reg = <2>; + trigger-name = "timer-counter-2"; + trigger-value = <0x5>; + }; + + trigger@3 { + reg = <3>; + trigger-name = "external"; + trigger-value = <0x13>; + trigger-external; + }; + }; + + usb0: gadget@fffd4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00600000 0x100000>, + <0xfffd4000 0x4000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + }; + ramc0: ramc@ffffea00 { compatible = "atmel,at91sam9260-sdramc"; reg = <0xffffea00 0x200>; @@ -238,6 +374,44 @@ <0x003fffff 0x0001ff3c>; /* pioD */ /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_ts: adc0_ts-0 { + atmel,pins = + , + , + , + ; + }; + + pinctrl_adc0_ad0: adc0_ad0-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad1: adc0_ad1-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad2: adc0_ad2-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad3: adc0_ad3-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad4: adc0_ad4-0 { + atmel,pins = ; + }; + + pinctrl_adc0_ad5: adc0_ad5-0 { + atmel,pins = ; + }; + + pinctrl_adc0_adtrg: adc0_adtrg-0 { + atmel,pins = ; + }; + }; + dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = @@ -246,6 +420,33 @@ }; }; + fb { + pinctrl_fb: fb-0 { + atmel,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + i2c_gpio0 { pinctrl_i2c_gpio0: i2c_gpio0-0 { atmel,pins = @@ -307,6 +508,61 @@ }; }; + pwm0 { + pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { + atmel,pins = ; + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + , + , + ; + }; + }; + ssc0 { pinctrl_ssc0_tx: ssc0_tx-0 { atmel,pins = @@ -339,15 +595,6 @@ }; }; - spi0 { - pinctrl_spi0: spi0-0 { - atmel,pins = - , - , - ; - }; - }; - tcb0 { pinctrl_tcb0_tclk0: tcb0_tclk0-0 { atmel,pins = ; -- cgit v1.2.3 From 3d293138f6793a87594be2d74191b6645421bc65 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 15 Apr 2014 13:07:43 +0200 Subject: ARM: at91/dt: add peripherals to the at91sam9rlek board This adds support for: - SPI - Dataflash - LCD - i2c - ADC - Touchscreen - USB gadget - PWM Also it switches the ds1 and ds2 leds to PWM control. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9rlek.dts | 90 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 86 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index cddb37825fad..f148fa4b3ab9 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -32,6 +32,37 @@ }; ahb { + fb0: fb@00500000 { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "RGB"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + nand0: nand@40000000 { nand-bus-width = <8>; nand-ecc-mode = "soft"; @@ -92,6 +123,43 @@ status = "okay"; }; + adc0: adc@fffd0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_adtrg>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + + usb0: gadget@fffd4000 { + atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffcc000 { + status = "okay"; + cs-gpios = <&pioA 28 0>, <0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <15000000>; + reg = <0>; + }; + }; + + pwm0: pwm@fffc8000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm1_2>, + <&pinctrl_pwm0_pwm2_2>; + }; + dbgu: serial@fffff200 { status = "okay"; }; @@ -117,18 +185,24 @@ }; }; - leds { - compatible = "gpio-leds"; + pwmleds { + compatible = "pwm-leds"; ds1 { label = "ds1"; - gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; }; ds2 { label = "ds2"; - gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; + max-brightness = <255>; }; + }; + + leds { + compatible = "gpio-leds"; ds3 { label = "ds3"; @@ -154,4 +228,12 @@ gpio-key,wakeup; }; }; + + i2c@0 { + status = "okay"; + }; + + i2c@1 { + status = "okay"; + }; }; -- cgit v1.2.3 From 72e6caca6389713c6c37c230b58657b28bcd6a00 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Mar 2014 00:15:39 +0100 Subject: ARM: at91/dt: sam9g45: improve ADC/touchscreen support Fixes the compatible string, adds the pinmuxing for the ADC pins. Also, removes atmel,adc-use-external-triggers as it is not possible to remove it unless redefining the whole adc node Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9g45.dtsi | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 9cdaecff13b3..ace6bf197b70 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -136,6 +136,36 @@ >; /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = ; + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = ; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = ; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = ; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = ; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = ; + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = ; + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = ; + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = ; + }; + }; + dbgu { pinctrl_dbgu: dbgu-0 { atmel,pins = @@ -634,10 +664,9 @@ adc0: adc@fffb0000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; + compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - atmel,adc-use-external-triggers; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; -- cgit v1.2.3 From e10a57e341a6799db7e1414f38940ba800d4f297 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Mar 2014 00:15:40 +0100 Subject: ARM: at91/dt: at91sam9m10g45ek: add ADC and touchscreen support Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9m10g45ek.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 7ff665a8c708..7800931a4b16 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -130,6 +130,21 @@ status = "okay"; }; + adc0: adc@fffb0000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7>; + atmel,adc-ts-wires = <4>; + status = "okay"; + }; + pwm0: pwm@fffb8000 { status = "okay"; -- cgit v1.2.3 From 66844c749c3520f99aa2e0f29601db6b571a284e Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 19 Mar 2014 00:15:41 +0100 Subject: ARM: at91/dt: at91sam9m10g45ek PWM leds polarity is inversed The real polarity of the LEDs is inversed. The led is between 3.3v and the PWM. It was working before because the driver was getting the duty cycle calculation wrong. Signed-off-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9m10g45ek.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 7800931a4b16..9f5b0a674995 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "at91sam9g45.dtsi" +#include / { model = "Atmel AT91SAM9M10G45-EK"; @@ -231,14 +232,14 @@ d6 { label = "d6"; - pwms = <&pwm0 3 5000 0>; + pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "nand-disk"; }; d7 { label = "d7"; - pwms = <&pwm0 1 5000 0>; + pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "mmc0"; }; -- cgit v1.2.3 From 58962b7494c0fc7d528874dd6e11ba2eb4ae9207 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 17 Mar 2014 17:45:34 +0800 Subject: ARM: at91: sama5d3: add DMA property for SSC devices Add DMA property for SSC devices on SAMA5D3 SoC. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index eabcfdbb403a..9caa06b3641e 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -113,6 +113,9 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf0008000 0x4000>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma0 2 AT91_DMA_CFG_PER_ID(14)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; clocks = <&ssc0_clk>; @@ -231,6 +234,9 @@ compatible = "atmel,at91sam9g45-ssc"; reg = <0xf800c000 0x4000>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma1 2 AT91_DMA_CFG_PER_ID(4)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; clocks = <&ssc1_clk>; -- cgit v1.2.3 From 208ec6ff4fbc603f88209fce167dd955db5aa342 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 17 Mar 2014 17:45:35 +0800 Subject: ARM: at91: sama5d3: disable sound by default Make the sound device in disabled status by default Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xmb.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index dba739b6ef36..29386057fbb2 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -170,5 +170,7 @@ atmel,ssc-controller = <&ssc0>; atmel,audio-codec = <&wm8904>; + + status = "disabled"; }; }; -- cgit v1.2.3 From 469bbf0a76a0fd95b8cf5b36b1f6c413b4008c99 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 17 Mar 2014 17:45:36 +0800 Subject: ARM: at91: sama5d3: correct the sound compatible string As the sama5d3 dtsi file in go into mainline before sound driver, and, the sound compatible string is changed when go into mainline. Add this patch to correct the sound compatible string. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xmb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 29386057fbb2..e1bd576760c6 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -156,7 +156,7 @@ }; sound { - compatible = "atmel,sama5d3ek-wm8904"; + compatible = "atmel,asoc-wm8904"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; -- cgit v1.2.3 From 7a61fb077d6dc4d6d93691654f754406b6d4baf0 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 17 Mar 2014 17:45:37 +0800 Subject: ARM: at91: sama5d3: add the missing property If without the MICBIAS routing, the record don't work. Add the missing MICBIAS routing to let record from mic working. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xmb.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index e1bd576760c6..060015375e44 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -166,6 +166,7 @@ "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", "IN2R", "Line In Jack", + "MICBIAS", "IN1L", "IN1L", "Mic"; atmel,ssc-controller = <&ssc0>; -- cgit v1.2.3 From 27a96a0364787d2b41d2a72d08143d95263e1b07 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Mon, 17 Mar 2014 17:45:38 +0800 Subject: ARM: at91: sama5d3: clock for ssc from rk pin According to hardware design the clock for SSC device is from rk pin. Signed-off-by: Bo Shen Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xmb.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index 060015375e44..306eef0f97ef 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -32,6 +32,10 @@ }; }; + ssc0: ssc@f0008000 { + atmel,clk-from-rk-pin; + }; + /* * i2c0 conflicts with ISI: * disable it to allow the use of ISI -- cgit v1.2.3 From 4525beeb9aadbb9e1cb3e9e135f4371553f26a70 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 16 Apr 2014 15:20:44 -0500 Subject: usb: phy: rename usb_nop_xceiv to usb_phy_generic no functional changes, just renaming the function in order to make it slightly clearer what it should be used for, also matching the driver name. Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/usb-host.c | 8 +++--- drivers/usb/dwc3/dwc3-exynos.c | 6 ++--- drivers/usb/dwc3/dwc3-pci.c | 6 ++--- drivers/usb/musb/am35x.c | 4 +-- drivers/usb/musb/blackfin.c | 4 +-- drivers/usb/musb/da8xx.c | 4 +-- drivers/usb/musb/davinci.c | 6 ++--- drivers/usb/musb/tusb6010.c | 6 ++--- drivers/usb/phy/phy-am335x.c | 2 +- drivers/usb/phy/phy-generic.c | 50 +++++++++++++++++------------------ drivers/usb/phy/phy-generic.h | 6 ++--- drivers/usb/phy/phy-keystone.c | 2 +- include/linux/usb/usb_phy_gen_xceiv.h | 10 +++---- 13 files changed, 57 insertions(+), 57 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 10855eb4ccc1..ab983cdd3edf 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -349,7 +349,7 @@ static struct fixed_voltage_config hsusb_reg_config = { /* .init_data filled later */ }; -static const char *nop_name = "usb_phy_gen_xceiv"; /* NOP PHY driver */ +static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */ static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ /** @@ -435,7 +435,7 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) struct platform_device *pdev; char *phy_id; struct platform_device_info pdevinfo; - struct usb_phy_gen_xceiv_platform_data nop_pdata; + struct usb_phy_generic_platform_data nop_pdata; for (i = 0; i < num_phys; i++) { @@ -469,8 +469,8 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) pdevinfo.id = phy->port; pdevinfo.data = &nop_pdata; pdevinfo.size_data = - sizeof(struct usb_phy_gen_xceiv_platform_data); - scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d", + sizeof(struct usb_phy_generic_platform_data); + scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d", phy->port); pdev = platform_device_register_full(&pdevinfo); if (IS_ERR(pdev)) { diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index 28c8ad79f5e6..821cc59e6e1d 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -38,13 +38,13 @@ struct dwc3_exynos { static int dwc3_exynos_register_phys(struct dwc3_exynos *exynos) { - struct usb_phy_gen_xceiv_platform_data pdata; + struct usb_phy_generic_platform_data pdata; struct platform_device *pdev; int ret; memset(&pdata, 0x00, sizeof(pdata)); - pdev = platform_device_alloc("usb_phy_gen_xceiv", PLATFORM_DEVID_AUTO); + pdev = platform_device_alloc("usb_phy_generic", PLATFORM_DEVID_AUTO); if (!pdev) return -ENOMEM; @@ -56,7 +56,7 @@ static int dwc3_exynos_register_phys(struct dwc3_exynos *exynos) if (ret) goto err1; - pdev = platform_device_alloc("usb_phy_gen_xceiv", PLATFORM_DEVID_AUTO); + pdev = platform_device_alloc("usb_phy_generic", PLATFORM_DEVID_AUTO); if (!pdev) { ret = -ENOMEM; goto err1; diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index f393c183cc69..8b162f0e293c 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -40,13 +40,13 @@ struct dwc3_pci { static int dwc3_pci_register_phys(struct dwc3_pci *glue) { - struct usb_phy_gen_xceiv_platform_data pdata; + struct usb_phy_generic_platform_data pdata; struct platform_device *pdev; int ret; memset(&pdata, 0x00, sizeof(pdata)); - pdev = platform_device_alloc("usb_phy_gen_xceiv", 0); + pdev = platform_device_alloc("usb_phy_generic", 0); if (!pdev) return -ENOMEM; @@ -58,7 +58,7 @@ static int dwc3_pci_register_phys(struct dwc3_pci *glue) if (ret) goto err1; - pdev = platform_device_alloc("usb_phy_gen_xceiv", 1); + pdev = platform_device_alloc("usb_phy_generic", 1); if (!pdev) { ret = -ENOMEM; goto err1; diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c index b3aa0184af9a..77ed66427969 100644 --- a/drivers/usb/musb/am35x.c +++ b/drivers/usb/musb/am35x.c @@ -360,7 +360,7 @@ static int am35x_musb_init(struct musb *musb) if (!rev) return -ENODEV; - usb_nop_xceiv_register(); + usb_phy_generic_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) return -EPROBE_DEFER; @@ -402,7 +402,7 @@ static int am35x_musb_exit(struct musb *musb) data->set_phy_power(0); usb_put_phy(musb->xceiv); - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); return 0; } diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c index 796677fa9a15..607f3ae04591 100644 --- a/drivers/usb/musb/blackfin.c +++ b/drivers/usb/musb/blackfin.c @@ -401,7 +401,7 @@ static int bfin_musb_init(struct musb *musb) } gpio_direction_output(musb->config->gpio_vrsel, 0); - usb_nop_xceiv_register(); + usb_phy_generic_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) { gpio_free(musb->config->gpio_vrsel); @@ -426,7 +426,7 @@ static int bfin_musb_exit(struct musb *musb) gpio_free(musb->config->gpio_vrsel); usb_put_phy(musb->xceiv); - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); return 0; } diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c index e3486de71995..bcdce8e64670 100644 --- a/drivers/usb/musb/da8xx.c +++ b/drivers/usb/musb/da8xx.c @@ -418,7 +418,7 @@ static int da8xx_musb_init(struct musb *musb) if (!rev) goto fail; - usb_nop_xceiv_register(); + usb_phy_generic_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) { ret = -EPROBE_DEFER; @@ -453,7 +453,7 @@ static int da8xx_musb_exit(struct musb *musb) phy_off(); usb_put_phy(musb->xceiv); - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); return 0; } diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index c259dac9d056..c0e07eddb079 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -381,7 +381,7 @@ static int davinci_musb_init(struct musb *musb) u32 revision; int ret = -ENODEV; - usb_nop_xceiv_register(); + usb_phy_generic_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) { ret = -EPROBE_DEFER; @@ -439,7 +439,7 @@ static int davinci_musb_init(struct musb *musb) fail: usb_put_phy(musb->xceiv); unregister: - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); return ret; } @@ -487,7 +487,7 @@ static int davinci_musb_exit(struct musb *musb) phy_off(); usb_put_phy(musb->xceiv); - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); return 0; } diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c index 4e9fb1d08698..0c0f5ee1e3f1 100644 --- a/drivers/usb/musb/tusb6010.c +++ b/drivers/usb/musb/tusb6010.c @@ -1065,7 +1065,7 @@ static int tusb_musb_init(struct musb *musb) void __iomem *sync = NULL; int ret; - usb_nop_xceiv_register(); + usb_phy_generic_register(); musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) return -EPROBE_DEFER; @@ -1117,7 +1117,7 @@ done: iounmap(sync); usb_put_phy(musb->xceiv); - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); } return ret; } @@ -1133,7 +1133,7 @@ static int tusb_musb_exit(struct musb *musb) iounmap(musb->sync_va); usb_put_phy(musb->xceiv); - usb_nop_xceiv_unregister(); + usb_phy_generic_unregister(); return 0; } diff --git a/drivers/usb/phy/phy-am335x.c b/drivers/usb/phy/phy-am335x.c index 12fc3468a01e..bb866e466051 100644 --- a/drivers/usb/phy/phy-am335x.c +++ b/drivers/usb/phy/phy-am335x.c @@ -13,7 +13,7 @@ #include "phy-generic.h" struct am335x_phy { - struct usb_phy_gen_xceiv usb_phy_gen; + struct usb_phy_generic usb_phy_gen; struct phy_control *phy_ctrl; int id; }; diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c index 95e70bc384c2..e76ca4ca3a8a 100644 --- a/drivers/usb/phy/phy-generic.c +++ b/drivers/usb/phy/phy-generic.c @@ -43,32 +43,32 @@ static struct platform_device *pd; -void usb_nop_xceiv_register(void) +void usb_phy_generic_register(void) { if (pd) return; - pd = platform_device_register_simple("usb_phy_gen_xceiv", -1, NULL, 0); + pd = platform_device_register_simple("usb_phy_generic", -1, NULL, 0); if (IS_ERR(pd)) { pr_err("Unable to register generic usb transceiver\n"); pd = NULL; return; } } -EXPORT_SYMBOL_GPL(usb_nop_xceiv_register); +EXPORT_SYMBOL_GPL(usb_phy_generic_register); -void usb_nop_xceiv_unregister(void) +void usb_phy_generic_unregister(void) { platform_device_unregister(pd); pd = NULL; } -EXPORT_SYMBOL_GPL(usb_nop_xceiv_unregister); +EXPORT_SYMBOL_GPL(usb_phy_generic_unregister); static int nop_set_suspend(struct usb_phy *x, int suspend) { return 0; } -static void nop_reset_set(struct usb_phy_gen_xceiv *nop, int asserted) +static void nop_reset_set(struct usb_phy_generic *nop, int asserted) { int value; @@ -87,7 +87,7 @@ static void nop_reset_set(struct usb_phy_gen_xceiv *nop, int asserted) int usb_gen_phy_init(struct usb_phy *phy) { - struct usb_phy_gen_xceiv *nop = dev_get_drvdata(phy->dev); + struct usb_phy_generic *nop = dev_get_drvdata(phy->dev); if (!IS_ERR(nop->vcc)) { if (regulator_enable(nop->vcc)) @@ -106,7 +106,7 @@ EXPORT_SYMBOL_GPL(usb_gen_phy_init); void usb_gen_phy_shutdown(struct usb_phy *phy) { - struct usb_phy_gen_xceiv *nop = dev_get_drvdata(phy->dev); + struct usb_phy_generic *nop = dev_get_drvdata(phy->dev); /* Assert RESET */ nop_reset_set(nop, 1); @@ -150,8 +150,8 @@ static int nop_set_host(struct usb_otg *otg, struct usb_bus *host) return 0; } -int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop, - struct usb_phy_gen_xceiv_platform_data *pdata) +int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_generic *nop, + struct usb_phy_generic_platform_data *pdata) { enum usb_phy_type type = USB_PHY_TYPE_USB2; int err; @@ -245,10 +245,10 @@ int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop, } EXPORT_SYMBOL_GPL(usb_phy_gen_create_phy); -static int usb_phy_gen_xceiv_probe(struct platform_device *pdev) +static int usb_phy_generic_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct usb_phy_gen_xceiv *nop; + struct usb_phy_generic *nop; int err; nop = devm_kzalloc(dev, sizeof(*nop), GFP_KERNEL); @@ -274,9 +274,9 @@ static int usb_phy_gen_xceiv_probe(struct platform_device *pdev) return 0; } -static int usb_phy_gen_xceiv_remove(struct platform_device *pdev) +static int usb_phy_generic_remove(struct platform_device *pdev) { - struct usb_phy_gen_xceiv *nop = platform_get_drvdata(pdev); + struct usb_phy_generic *nop = platform_get_drvdata(pdev); usb_remove_phy(&nop->phy); @@ -290,29 +290,29 @@ static const struct of_device_id nop_xceiv_dt_ids[] = { MODULE_DEVICE_TABLE(of, nop_xceiv_dt_ids); -static struct platform_driver usb_phy_gen_xceiv_driver = { - .probe = usb_phy_gen_xceiv_probe, - .remove = usb_phy_gen_xceiv_remove, +static struct platform_driver usb_phy_generic_driver = { + .probe = usb_phy_generic_probe, + .remove = usb_phy_generic_remove, .driver = { - .name = "usb_phy_gen_xceiv", + .name = "usb_phy_generic", .owner = THIS_MODULE, .of_match_table = nop_xceiv_dt_ids, }, }; -static int __init usb_phy_gen_xceiv_init(void) +static int __init usb_phy_generic_init(void) { - return platform_driver_register(&usb_phy_gen_xceiv_driver); + return platform_driver_register(&usb_phy_generic_driver); } -subsys_initcall(usb_phy_gen_xceiv_init); +subsys_initcall(usb_phy_generic_init); -static void __exit usb_phy_gen_xceiv_exit(void) +static void __exit usb_phy_generic_exit(void) { - platform_driver_unregister(&usb_phy_gen_xceiv_driver); + platform_driver_unregister(&usb_phy_generic_driver); } -module_exit(usb_phy_gen_xceiv_exit); +module_exit(usb_phy_generic_exit); -MODULE_ALIAS("platform:usb_phy_gen_xceiv"); +MODULE_ALIAS("platform:usb_phy_generic"); MODULE_AUTHOR("Texas Instruments Inc"); MODULE_DESCRIPTION("NOP USB Transceiver driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/usb/phy/phy-generic.h b/drivers/usb/phy/phy-generic.h index 38a81f307b82..f32450ada12d 100644 --- a/drivers/usb/phy/phy-generic.h +++ b/drivers/usb/phy/phy-generic.h @@ -3,7 +3,7 @@ #include -struct usb_phy_gen_xceiv { +struct usb_phy_generic { struct usb_phy phy; struct device *dev; struct clk *clk; @@ -15,7 +15,7 @@ struct usb_phy_gen_xceiv { int usb_gen_phy_init(struct usb_phy *phy); void usb_gen_phy_shutdown(struct usb_phy *phy); -int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_gen_xceiv *nop, - struct usb_phy_gen_xceiv_platform_data *pdata); +int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_generic *nop, + struct usb_phy_generic_platform_data *pdata); #endif diff --git a/drivers/usb/phy/phy-keystone.c b/drivers/usb/phy/phy-keystone.c index d762003896c0..2404c442c302 100644 --- a/drivers/usb/phy/phy-keystone.c +++ b/drivers/usb/phy/phy-keystone.c @@ -35,7 +35,7 @@ #define PHY_REF_SSP_EN BIT(29) struct keystone_usbphy { - struct usb_phy_gen_xceiv usb_phy_gen; + struct usb_phy_generic usb_phy_gen; void __iomem *phy_ctrl; }; diff --git a/include/linux/usb/usb_phy_gen_xceiv.h b/include/linux/usb/usb_phy_gen_xceiv.h index cc8d818a83be..c00176d48625 100644 --- a/include/linux/usb/usb_phy_gen_xceiv.h +++ b/include/linux/usb/usb_phy_gen_xceiv.h @@ -3,7 +3,7 @@ #include -struct usb_phy_gen_xceiv_platform_data { +struct usb_phy_generic_platform_data { enum usb_phy_type type; unsigned long clk_rate; @@ -15,14 +15,14 @@ struct usb_phy_gen_xceiv_platform_data { #if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE)) /* sometimes transceivers are accessed only through e.g. ULPI */ -extern void usb_nop_xceiv_register(void); -extern void usb_nop_xceiv_unregister(void); +extern void usb_phy_generic_register(void); +extern void usb_phy_generic_unregister(void); #else -static inline void usb_nop_xceiv_register(void) +static inline void usb_phy_generic_register(void) { } -static inline void usb_nop_xceiv_unregister(void) +static inline void usb_phy_generic_unregister(void) { } #endif -- cgit v1.2.3 From d7078df6be6e9e5e3ac354859f5b8d60114391b4 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 16 Apr 2014 15:28:32 -0500 Subject: usb: phy: rename to now that all functions match the driver name, the only missing piece is to rename the header file itself. Signed-off-by: Felipe Balbi --- arch/arm/mach-omap2/board-omap3beagle.c | 1 - arch/arm/mach-omap2/usb-host.c | 2 +- drivers/usb/dwc3/dwc3-exynos.c | 2 +- drivers/usb/dwc3/dwc3-pci.c | 2 +- drivers/usb/musb/am35x.c | 2 +- drivers/usb/musb/blackfin.c | 2 +- drivers/usb/musb/da8xx.c | 2 +- drivers/usb/musb/davinci.c | 2 +- drivers/usb/musb/musb_dsps.c | 2 +- drivers/usb/musb/tusb6010.c | 2 +- drivers/usb/phy/phy-am335x.c | 2 +- drivers/usb/phy/phy-generic.c | 2 +- drivers/usb/phy/phy-generic.h | 2 +- drivers/usb/phy/phy-keystone.c | 2 +- include/linux/usb/usb_phy_gen_xceiv.h | 30 ------------------------------ include/linux/usb/usb_phy_generic.h | 30 ++++++++++++++++++++++++++++++ 16 files changed, 43 insertions(+), 44 deletions(-) delete mode 100644 include/linux/usb/usb_phy_gen_xceiv.h create mode 100644 include/linux/usb/usb_phy_generic.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index d6ed819ff15c..660bfc5a70d7 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index ab983cdd3edf..745367c0c2bb 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include "soc.h" #include "omap_device.h" diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index 821cc59e6e1d..ed22d722884e 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 8b162f0e293c..1ed95e0386eb 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -23,7 +23,7 @@ #include #include -#include +#include /* FIXME define these in */ #define PCI_VENDOR_ID_SYNOPSYS 0x16c3 diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c index 77ed66427969..044cd824c70d 100644 --- a/drivers/usb/musb/am35x.c +++ b/drivers/usb/musb/am35x.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include "musb_core.h" diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c index 607f3ae04591..c9992a2eaaa8 100644 --- a/drivers/usb/musb/blackfin.c +++ b/drivers/usb/musb/blackfin.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c index bcdce8e64670..a0dabb05de76 100644 --- a/drivers/usb/musb/da8xx.c +++ b/drivers/usb/musb/da8xx.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c index c0e07eddb079..737035457858 100644 --- a/drivers/usb/musb/davinci.c +++ b/drivers/usb/musb/davinci.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/usb/musb/musb_dsps.c b/drivers/usb/musb/musb_dsps.c index 3372ded5def7..18882924d9d5 100644 --- a/drivers/usb/musb/musb_dsps.c +++ b/drivers/usb/musb/musb_dsps.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c index 0c0f5ee1e3f1..8d4a8194c8f2 100644 --- a/drivers/usb/musb/tusb6010.c +++ b/drivers/usb/musb/tusb6010.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include "musb_core.h" diff --git a/drivers/usb/phy/phy-am335x.c b/drivers/usb/phy/phy-am335x.c index bb866e466051..585e50cb1980 100644 --- a/drivers/usb/phy/phy-am335x.c +++ b/drivers/usb/phy/phy-am335x.c @@ -2,7 +2,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c index e76ca4ca3a8a..2c49cd8f6d25 100644 --- a/drivers/usb/phy/phy-generic.c +++ b/drivers/usb/phy/phy-generic.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/usb/phy/phy-generic.h b/drivers/usb/phy/phy-generic.h index f32450ada12d..d8feacc0b7fb 100644 --- a/drivers/usb/phy/phy-generic.h +++ b/drivers/usb/phy/phy-generic.h @@ -1,7 +1,7 @@ #ifndef _PHY_GENERIC_H_ #define _PHY_GENERIC_H_ -#include +#include struct usb_phy_generic { struct usb_phy phy; diff --git a/drivers/usb/phy/phy-keystone.c b/drivers/usb/phy/phy-keystone.c index 2404c442c302..f4d722de912b 100644 --- a/drivers/usb/phy/phy-keystone.c +++ b/drivers/usb/phy/phy-keystone.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include diff --git a/include/linux/usb/usb_phy_gen_xceiv.h b/include/linux/usb/usb_phy_gen_xceiv.h deleted file mode 100644 index c00176d48625..000000000000 --- a/include/linux/usb/usb_phy_gen_xceiv.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __LINUX_USB_NOP_XCEIV_H -#define __LINUX_USB_NOP_XCEIV_H - -#include - -struct usb_phy_generic_platform_data { - enum usb_phy_type type; - unsigned long clk_rate; - - /* if set fails with -EPROBE_DEFER if can't get regulator */ - unsigned int needs_vcc:1; - unsigned int needs_reset:1; /* deprecated */ - int gpio_reset; -}; - -#if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE)) -/* sometimes transceivers are accessed only through e.g. ULPI */ -extern void usb_phy_generic_register(void); -extern void usb_phy_generic_unregister(void); -#else -static inline void usb_phy_generic_register(void) -{ -} - -static inline void usb_phy_generic_unregister(void) -{ -} -#endif - -#endif /* __LINUX_USB_NOP_XCEIV_H */ diff --git a/include/linux/usb/usb_phy_generic.h b/include/linux/usb/usb_phy_generic.h new file mode 100644 index 000000000000..c00176d48625 --- /dev/null +++ b/include/linux/usb/usb_phy_generic.h @@ -0,0 +1,30 @@ +#ifndef __LINUX_USB_NOP_XCEIV_H +#define __LINUX_USB_NOP_XCEIV_H + +#include + +struct usb_phy_generic_platform_data { + enum usb_phy_type type; + unsigned long clk_rate; + + /* if set fails with -EPROBE_DEFER if can't get regulator */ + unsigned int needs_vcc:1; + unsigned int needs_reset:1; /* deprecated */ + int gpio_reset; +}; + +#if defined(CONFIG_NOP_USB_XCEIV) || (defined(CONFIG_NOP_USB_XCEIV_MODULE) && defined(MODULE)) +/* sometimes transceivers are accessed only through e.g. ULPI */ +extern void usb_phy_generic_register(void); +extern void usb_phy_generic_unregister(void); +#else +static inline void usb_phy_generic_register(void) +{ +} + +static inline void usb_phy_generic_unregister(void) +{ +} +#endif + +#endif /* __LINUX_USB_NOP_XCEIV_H */ -- cgit v1.2.3 From 5c7411e2937401bf4d024744032f879475364996 Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Mon, 7 Apr 2014 18:37:47 +0300 Subject: KVM: x86: Fix CR3 and LDT sel should not be saved in TSS According to Intel specifications, only general purpose registers and segment selectors should be saved in the old TSS during 32-bit task-switch. Signed-off-by: Nadav Amit Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/emulate.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 205b17eed93c..0dec502d20be 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -2496,7 +2496,7 @@ static int task_switch_16(struct x86_emulate_ctxt *ctxt, static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, struct tss_segment_32 *tss) { - tss->cr3 = ctxt->ops->get_cr(ctxt, 3); + /* CR3 and ldt selector are not saved intentionally */ tss->eip = ctxt->_eip; tss->eflags = ctxt->eflags; tss->eax = reg_read(ctxt, VCPU_REGS_RAX); @@ -2514,7 +2514,6 @@ static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); - tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); } static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, @@ -2604,6 +2603,8 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt, struct tss_segment_32 tss_seg; int ret; u32 new_tss_base = get_desc_base(new_desc); + u32 eip_offset = offsetof(struct tss_segment_32, eip); + u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, &ctxt->exception); @@ -2613,8 +2614,9 @@ static int task_switch_32(struct x86_emulate_ctxt *ctxt, save_state_to_tss32(ctxt, &tss_seg); - ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, - &ctxt->exception); + /* Only GP registers and segment selectors are saved */ + ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip, + ldt_sel_offset - eip_offset, &ctxt->exception); if (ret != X86EMUL_CONTINUE) /* FIXME: need to provide precise fault address */ return ret; -- cgit v1.2.3 From 65eef33550f68e9a7f7d2dc64da94fb6cb85be2c Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Tue, 14 Jan 2014 15:02:11 +0100 Subject: KVM: s390: Adding skey bit to mmu context For lazy storage key handling, we need a mechanism to track if the process ever issued a storage key operation. This patch adds the basic infrastructure for making the storage key handling optional, but still leaves it enabled for now by default. Signed-off-by: Dominik Dingel Acked-by: Martin Schwidefsky Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/mmu.h | 2 ++ arch/s390/include/asm/mmu_context.h | 1 + arch/s390/include/asm/pgtable.h | 41 ++++++++++++++++++++++++------------- 3 files changed, 30 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h index f77695a82f64..a5e656260a70 100644 --- a/arch/s390/include/asm/mmu.h +++ b/arch/s390/include/asm/mmu.h @@ -16,6 +16,8 @@ typedef struct { unsigned long vdso_base; /* The mmu context has extended page tables. */ unsigned int has_pgste:1; + /* The mmu context uses storage keys. */ + unsigned int use_skey:1; } mm_context_t; #define INIT_MM_CONTEXT(name) \ diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index 71be346d0e3c..05925ead0748 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -23,6 +23,7 @@ static inline int init_new_context(struct task_struct *tsk, mm->context.asce_bits |= _ASCE_TYPE_REGION3; #endif mm->context.has_pgste = 0; + mm->context.use_skey = 1; mm->context.asce_limit = STACK_TOP_MAX; crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm)); return 0; diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 12f75313e086..e88e9f6b07cc 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -466,6 +466,16 @@ static inline int mm_has_pgste(struct mm_struct *mm) #endif return 0; } + +static inline int mm_use_skey(struct mm_struct *mm) +{ +#ifdef CONFIG_PGSTE + if (mm->context.use_skey) + return 1; +#endif + return 0; +} + /* * pgd/pmd/pte query functions */ @@ -699,12 +709,13 @@ static inline void pgste_set(pte_t *ptep, pgste_t pgste) #endif } -static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) +static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, + struct mm_struct *mm) { #ifdef CONFIG_PGSTE unsigned long address, bits, skey; - if (pte_val(*ptep) & _PAGE_INVALID) + if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) return pgste; address = pte_val(*ptep) & PAGE_MASK; skey = (unsigned long) page_get_storage_key(address); @@ -729,10 +740,11 @@ static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) } -static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) +static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste, + struct mm_struct *mm) { #ifdef CONFIG_PGSTE - if (pte_val(*ptep) & _PAGE_INVALID) + if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) return pgste; /* Get referenced bit from storage key */ if (page_reset_referenced(pte_val(*ptep) & PAGE_MASK)) @@ -741,13 +753,14 @@ static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste) return pgste; } -static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry) +static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, + struct mm_struct *mm) { #ifdef CONFIG_PGSTE unsigned long address; unsigned long nkey; - if (pte_val(entry) & _PAGE_INVALID) + if (!mm_use_skey(mm) || pte_val(entry) & _PAGE_INVALID) return; VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID)); address = pte_val(entry) & PAGE_MASK; @@ -870,7 +883,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, if (mm_has_pgste(mm)) { pgste = pgste_get_lock(ptep); pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; - pgste_set_key(ptep, pgste, entry); + pgste_set_key(ptep, pgste, entry, mm); pgste_set_pte(ptep, entry); pgste_set_unlock(ptep, pgste); } else { @@ -1028,7 +1041,7 @@ static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, if (mm_has_pgste(mm)) { pgste = pgste_get_lock(ptep); - pgste = pgste_update_all(ptep, pgste); + pgste = pgste_update_all(ptep, pgste, mm); dirty = !!(pgste_val(pgste) & PGSTE_HC_BIT); pgste_val(pgste) &= ~PGSTE_HC_BIT; pgste_set_unlock(ptep, pgste); @@ -1048,7 +1061,7 @@ static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, if (mm_has_pgste(mm)) { pgste = pgste_get_lock(ptep); - pgste = pgste_update_young(ptep, pgste); + pgste = pgste_update_young(ptep, pgste, mm); young = !!(pgste_val(pgste) & PGSTE_HR_BIT); pgste_val(pgste) &= ~PGSTE_HR_BIT; pgste_set_unlock(ptep, pgste); @@ -1182,7 +1195,7 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm, pte_val(*ptep) = _PAGE_INVALID; if (mm_has_pgste(mm)) { - pgste = pgste_update_all(&pte, pgste); + pgste = pgste_update_all(&pte, pgste, mm); pgste_set_unlock(ptep, pgste); } return pte; @@ -1205,7 +1218,7 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, ptep_flush_lazy(mm, address, ptep); if (mm_has_pgste(mm)) { - pgste = pgste_update_all(&pte, pgste); + pgste = pgste_update_all(&pte, pgste, mm); pgste_set(ptep, pgste); } return pte; @@ -1219,7 +1232,7 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm, if (mm_has_pgste(mm)) { pgste = pgste_get(ptep); - pgste_set_key(ptep, pgste, pte); + pgste_set_key(ptep, pgste, pte, mm); pgste_set_pte(ptep, pte); pgste_set_unlock(ptep, pgste); } else @@ -1246,7 +1259,7 @@ static inline pte_t ptep_clear_flush(struct vm_area_struct *vma, if ((pgste_val(pgste) & _PGSTE_GPS_USAGE_MASK) == _PGSTE_GPS_USAGE_UNUSED) pte_val(pte) |= _PAGE_UNUSED; - pgste = pgste_update_all(&pte, pgste); + pgste = pgste_update_all(&pte, pgste, vma->vm_mm); pgste_set_unlock(ptep, pgste); } return pte; @@ -1278,7 +1291,7 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, pte_val(*ptep) = _PAGE_INVALID; if (!full && mm_has_pgste(mm)) { - pgste = pgste_update_all(&pte, pgste); + pgste = pgste_update_all(&pte, pgste, mm); pgste_set_unlock(ptep, pgste); } return pte; -- cgit v1.2.3 From d4cb11340be6a1613d40d2b546cb111ea2547066 Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Wed, 29 Jan 2014 16:02:32 +0100 Subject: KVM: s390: Clear storage keys page_table_reset_pgste() already does a complete page table walk to reset the pgste. Enhance it to initialize the storage keys to PAGE_DEFAULT_KEY if requested by the caller. This will be used for lazy storage key handling. Also provide an empty stub for !CONFIG_PGSTE Lets adopt the current code (diag 308) to not clear the keys. Signed-off-by: Dominik Dingel Acked-by: Martin Schwidefsky Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/pgalloc.h | 3 ++- arch/s390/kvm/diag.c | 6 +++--- arch/s390/mm/pgtable.c | 43 ++++++++++++++++++++++++++++++----------- 3 files changed, 37 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h index 884017cbfa9f..9e18a61d3df3 100644 --- a/arch/s390/include/asm/pgalloc.h +++ b/arch/s390/include/asm/pgalloc.h @@ -22,7 +22,8 @@ unsigned long *page_table_alloc(struct mm_struct *, unsigned long); void page_table_free(struct mm_struct *, unsigned long *); void page_table_free_rcu(struct mmu_gather *, unsigned long *); -void page_table_reset_pgste(struct mm_struct *, unsigned long, unsigned long); +void page_table_reset_pgste(struct mm_struct *, unsigned long, unsigned long, + bool init_skey); int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, unsigned long key, bool nq); diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index 08dfc839a6cf..44dcfa8860b5 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -169,15 +169,15 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu) switch (subcode) { case 0: case 1: - page_table_reset_pgste(current->mm, 0, TASK_SIZE); + page_table_reset_pgste(current->mm, 0, TASK_SIZE, false); return -EOPNOTSUPP; case 3: vcpu->run->s390_reset_flags = KVM_S390_RESET_CLEAR; - page_table_reset_pgste(current->mm, 0, TASK_SIZE); + page_table_reset_pgste(current->mm, 0, TASK_SIZE, false); break; case 4: vcpu->run->s390_reset_flags = 0; - page_table_reset_pgste(current->mm, 0, TASK_SIZE); + page_table_reset_pgste(current->mm, 0, TASK_SIZE, false); break; default: return -EOPNOTSUPP; diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index d7cfd57815fb..be80f55a1b78 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -883,8 +883,8 @@ static inline void page_table_free_pgste(unsigned long *table) __free_page(page); } -static inline unsigned long page_table_reset_pte(struct mm_struct *mm, - pmd_t *pmd, unsigned long addr, unsigned long end) +static inline unsigned long page_table_reset_pte(struct mm_struct *mm, pmd_t *pmd, + unsigned long addr, unsigned long end, bool init_skey) { pte_t *start_pte, *pte; spinlock_t *ptl; @@ -895,6 +895,22 @@ static inline unsigned long page_table_reset_pte(struct mm_struct *mm, do { pgste = pgste_get_lock(pte); pgste_val(pgste) &= ~_PGSTE_GPS_USAGE_MASK; + if (init_skey) { + unsigned long address; + + pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT | + PGSTE_GR_BIT | PGSTE_GC_BIT); + + /* skip invalid and not writable pages */ + if (pte_val(*pte) & _PAGE_INVALID || + !(pte_val(*pte) & _PAGE_WRITE)) { + pgste_set_unlock(pte, pgste); + continue; + } + + address = pte_val(*pte) & PAGE_MASK; + page_set_storage_key(address, PAGE_DEFAULT_KEY, 1); + } pgste_set_unlock(pte, pgste); } while (pte++, addr += PAGE_SIZE, addr != end); pte_unmap_unlock(start_pte, ptl); @@ -902,8 +918,8 @@ static inline unsigned long page_table_reset_pte(struct mm_struct *mm, return addr; } -static inline unsigned long page_table_reset_pmd(struct mm_struct *mm, - pud_t *pud, unsigned long addr, unsigned long end) +static inline unsigned long page_table_reset_pmd(struct mm_struct *mm, pud_t *pud, + unsigned long addr, unsigned long end, bool init_skey) { unsigned long next; pmd_t *pmd; @@ -913,14 +929,14 @@ static inline unsigned long page_table_reset_pmd(struct mm_struct *mm, next = pmd_addr_end(addr, end); if (pmd_none_or_clear_bad(pmd)) continue; - next = page_table_reset_pte(mm, pmd, addr, next); + next = page_table_reset_pte(mm, pmd, addr, next, init_skey); } while (pmd++, addr = next, addr != end); return addr; } -static inline unsigned long page_table_reset_pud(struct mm_struct *mm, - pgd_t *pgd, unsigned long addr, unsigned long end) +static inline unsigned long page_table_reset_pud(struct mm_struct *mm, pgd_t *pgd, + unsigned long addr, unsigned long end, bool init_skey) { unsigned long next; pud_t *pud; @@ -930,14 +946,14 @@ static inline unsigned long page_table_reset_pud(struct mm_struct *mm, next = pud_addr_end(addr, end); if (pud_none_or_clear_bad(pud)) continue; - next = page_table_reset_pmd(mm, pud, addr, next); + next = page_table_reset_pmd(mm, pud, addr, next, init_skey); } while (pud++, addr = next, addr != end); return addr; } -void page_table_reset_pgste(struct mm_struct *mm, - unsigned long start, unsigned long end) +void page_table_reset_pgste(struct mm_struct *mm, unsigned long start, + unsigned long end, bool init_skey) { unsigned long addr, next; pgd_t *pgd; @@ -949,7 +965,7 @@ void page_table_reset_pgste(struct mm_struct *mm, next = pgd_addr_end(addr, end); if (pgd_none_or_clear_bad(pgd)) continue; - next = page_table_reset_pud(mm, pgd, addr, next); + next = page_table_reset_pud(mm, pgd, addr, next, init_skey); } while (pgd++, addr = next, addr != end); up_read(&mm->mmap_sem); } @@ -1011,6 +1027,11 @@ static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm, return NULL; } +void page_table_reset_pgste(struct mm_struct *mm, unsigned long start, + unsigned long end, bool init_skey) +{ +} + static inline void page_table_free_pgste(unsigned long *table) { } -- cgit v1.2.3 From 934bc131efc3e4be6a52f7dd6c4dbf99635e381a Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Tue, 14 Jan 2014 18:10:17 +0100 Subject: KVM: s390: Allow skeys to be enabled for the current process Introduce a new function s390_enable_skey(), which enables storage key handling via setting the use_skey flag in the mmu context. This function is only useful within the context of kvm. Note that enabling storage keys will cause a one-time hickup when walking the page table; however, it saves us special effort for cases like clear reset while making it possible for us to be architecture conform. s390_enable_skey() takes the page table lock to prevent reseting storage keys triggered from multiple vcpus. Signed-off-by: Dominik Dingel Acked-by: Martin Schwidefsky Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/pgtable.h | 1 + arch/s390/mm/pgtable.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index e88e9f6b07cc..51b002b5667e 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -1747,6 +1747,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) extern int vmem_add_mapping(unsigned long start, unsigned long size); extern int vmem_remove_mapping(unsigned long start, unsigned long size); extern int s390_enable_sie(void); +extern void s390_enable_skey(void); /* * No page table caches to initialise diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index be80f55a1b78..02a8607bbeb5 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -1378,6 +1378,29 @@ int s390_enable_sie(void) } EXPORT_SYMBOL_GPL(s390_enable_sie); +/* + * Enable storage key handling from now on and initialize the storage + * keys with the default key. + */ +void s390_enable_skey(void) +{ + /* + * To avoid races between multiple vcpus, ending in calling + * page_table_reset twice or more, + * the page_table_lock is taken for serialization. + */ + spin_lock(¤t->mm->page_table_lock); + if (mm_use_skey(current->mm)) { + spin_unlock(¤t->mm->page_table_lock); + return; + } + + current->mm->context.use_skey = 1; + spin_unlock(¤t->mm->page_table_lock); + page_table_reset_pgste(current->mm, 0, TASK_SIZE, true); +} +EXPORT_SYMBOL_GPL(s390_enable_skey); + #ifdef CONFIG_TRANSPARENT_HUGEPAGE int pmdp_clear_flush_young(struct vm_area_struct *vma, unsigned long address, pmd_t *pmdp) -- cgit v1.2.3 From 693ffc0802db41911ada95a3e77546f0ed1e7d00 Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Tue, 14 Jan 2014 18:11:14 +0100 Subject: KVM: s390: Don't enable skeys by default The first invocation of storage key operations on a given cpu will be intercepted. On these intercepts we will enable storage keys for the guest and remove the previously added intercepts. Signed-off-by: Dominik Dingel Acked-by: Martin Schwidefsky Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 3 +++ arch/s390/include/asm/mmu_context.h | 2 +- arch/s390/kvm/kvm-s390.c | 1 + arch/s390/kvm/priv.c | 14 ++++++++++++++ arch/s390/kvm/trace.h | 14 ++++++++++++++ 5 files changed, 33 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index 154b60089be9..a993b6f3429f 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -89,6 +89,9 @@ struct kvm_s390_sie_block { __u16 lctl; /* 0x0044 */ __s16 icpua; /* 0x0046 */ #define ICTL_LPSW 0x00400000 +#define ICTL_ISKE 0x00004000 +#define ICTL_SSKE 0x00002000 +#define ICTL_RRBE 0x00001000 __u32 ictl; /* 0x0048 */ __u32 eca; /* 0x004c */ __u8 icptcode; /* 0x0050 */ diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index 05925ead0748..d42fb1b728d8 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -23,7 +23,7 @@ static inline int init_new_context(struct task_struct *tsk, mm->context.asce_bits |= _ASCE_TYPE_REGION3; #endif mm->context.has_pgste = 0; - mm->context.use_skey = 1; + mm->context.use_skey = 0; mm->context.asce_limit = STACK_TOP_MAX; crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm)); return 0; diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index b3ecb8f5b6ce..b767ec97368a 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -465,6 +465,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) vcpu->arch.sie_block->ecb2 = 8; vcpu->arch.sie_block->eca = 0xC1002001U; vcpu->arch.sie_block->fac = (int) (long) vfacilities; + vcpu->arch.sie_block->ictl |= ICTL_ISKE | ICTL_SSKE | ICTL_RRBE; if (kvm_enabled_cmma()) { cbrl = alloc_page(GFP_KERNEL | __GFP_ZERO); if (cbrl) { diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 476e9e218f43..8a63e992936b 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -147,8 +147,21 @@ static int handle_store_cpu_address(struct kvm_vcpu *vcpu) return 0; } +static void __skey_check_enable(struct kvm_vcpu *vcpu) +{ + if (!(vcpu->arch.sie_block->ictl & (ICTL_ISKE | ICTL_SSKE | ICTL_RRBE))) + return; + + s390_enable_skey(); + trace_kvm_s390_skey_related_inst(vcpu); + vcpu->arch.sie_block->ictl &= ~(ICTL_ISKE | ICTL_SSKE | ICTL_RRBE); +} + + static int handle_skey(struct kvm_vcpu *vcpu) { + __skey_check_enable(vcpu); + vcpu->stat.instruction_storage_key++; if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) @@ -618,6 +631,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu) } if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK) { + __skey_check_enable(vcpu); if (set_guest_storage_key(current->mm, useraddr, vcpu->run->s.regs.gprs[reg1] & PFMF_KEY, vcpu->run->s.regs.gprs[reg1] & PFMF_NQ)) diff --git a/arch/s390/kvm/trace.h b/arch/s390/kvm/trace.h index e8e7213d4cc5..a4bf7d78a0db 100644 --- a/arch/s390/kvm/trace.h +++ b/arch/s390/kvm/trace.h @@ -30,6 +30,20 @@ TP_printk("%02d[%016lx-%016lx]: " p_str, __entry->id, \ __entry->pswmask, __entry->pswaddr, p_args) +TRACE_EVENT(kvm_s390_skey_related_inst, + TP_PROTO(VCPU_PROTO_COMMON), + TP_ARGS(VCPU_ARGS_COMMON), + + TP_STRUCT__entry( + VCPU_FIELD_COMMON + ), + + TP_fast_assign( + VCPU_ASSIGN_COMMON + ), + VCPU_TP_PRINTK("%s", "first instruction related to skeys on vcpu") + ); + TRACE_EVENT(kvm_s390_major_guest_pfault, TP_PROTO(VCPU_PROTO_COMMON), TP_ARGS(VCPU_ARGS_COMMON), -- cgit v1.2.3 From 0a61b222df75a6a69dc34816f7db2f61fee8c935 Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Fri, 18 Oct 2013 12:03:41 +0200 Subject: KVM: s390/mm: use software dirty bit detection for user dirty tracking Switch the user dirty bit detection used for migration from the hardware provided host change-bit in the pgste to a fault based detection method. This reduced the dependency of the host from the storage key to a point where it becomes possible to enable the RCP bypass for KVM guests. The fault based dirty detection will only indicate changes caused by accesses via the guest address space. The hardware based method can detect all changes, even those caused by I/O or accesses via the kernel page table. The KVM/qemu code needs to take this into account. Signed-off-by: Martin Schwidefsky Signed-off-by: Dominik Dingel Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/pgtable.h | 135 +++++++++++++++++----------------------- arch/s390/mm/pgtable.c | 6 +- 2 files changed, 59 insertions(+), 82 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 51b002b5667e..b2c630df0ca5 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -309,7 +309,8 @@ extern unsigned long MODULES_END; #define PGSTE_HC_BIT 0x00200000UL #define PGSTE_GR_BIT 0x00040000UL #define PGSTE_GC_BIT 0x00020000UL -#define PGSTE_IN_BIT 0x00008000UL /* IPTE notify bit */ +#define PGSTE_UC_BIT 0x00008000UL /* user dirty (migration) */ +#define PGSTE_IN_BIT 0x00004000UL /* IPTE notify bit */ #else /* CONFIG_64BIT */ @@ -391,7 +392,8 @@ extern unsigned long MODULES_END; #define PGSTE_HC_BIT 0x0020000000000000UL #define PGSTE_GR_BIT 0x0004000000000000UL #define PGSTE_GC_BIT 0x0002000000000000UL -#define PGSTE_IN_BIT 0x0000800000000000UL /* IPTE notify bit */ +#define PGSTE_UC_BIT 0x0000800000000000UL /* user dirty (migration) */ +#define PGSTE_IN_BIT 0x0000400000000000UL /* IPTE notify bit */ #endif /* CONFIG_64BIT */ @@ -720,16 +722,6 @@ static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, address = pte_val(*ptep) & PAGE_MASK; skey = (unsigned long) page_get_storage_key(address); bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED); - if (!(pgste_val(pgste) & PGSTE_HC_BIT) && (bits & _PAGE_CHANGED)) { - /* Transfer dirty + referenced bit to host bits in pgste */ - pgste_val(pgste) |= bits << 52; - page_set_storage_key(address, skey ^ bits, 0); - } else if (!(pgste_val(pgste) & PGSTE_HR_BIT) && - (bits & _PAGE_REFERENCED)) { - /* Transfer referenced bit to host bit in pgste */ - pgste_val(pgste) |= PGSTE_HR_BIT; - page_reset_referenced(address); - } /* Transfer page changed & referenced bit to guest bits in pgste */ pgste_val(pgste) |= bits << 48; /* GR bit & GC bit */ /* Copy page access key and fetch protection bit to pgste */ @@ -740,19 +732,6 @@ static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste, } -static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste, - struct mm_struct *mm) -{ -#ifdef CONFIG_PGSTE - if (!mm_use_skey(mm) || pte_val(*ptep) & _PAGE_INVALID) - return pgste; - /* Get referenced bit from storage key */ - if (page_reset_referenced(pte_val(*ptep) & PAGE_MASK)) - pgste_val(pgste) |= PGSTE_HR_BIT | PGSTE_GR_BIT; -#endif - return pgste; -} - static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, struct mm_struct *mm) { @@ -770,23 +749,30 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry, * key C/R to 0. */ nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56; + nkey |= (pgste_val(pgste) & (PGSTE_GR_BIT | PGSTE_GC_BIT)) >> 48; page_set_storage_key(address, nkey, 0); #endif } -static inline void pgste_set_pte(pte_t *ptep, pte_t entry) +static inline pgste_t pgste_set_pte(pte_t *ptep, pgste_t pgste, pte_t entry) { - if (!MACHINE_HAS_ESOP && - (pte_val(entry) & _PAGE_PRESENT) && - (pte_val(entry) & _PAGE_WRITE)) { - /* - * Without enhanced suppression-on-protection force - * the dirty bit on for all writable ptes. - */ - pte_val(entry) |= _PAGE_DIRTY; - pte_val(entry) &= ~_PAGE_PROTECT; + if ((pte_val(entry) & _PAGE_PRESENT) && + (pte_val(entry) & _PAGE_WRITE) && + !(pte_val(entry) & _PAGE_INVALID)) { + if (!MACHINE_HAS_ESOP) { + /* + * Without enhanced suppression-on-protection force + * the dirty bit on for all writable ptes. + */ + pte_val(entry) |= _PAGE_DIRTY; + pte_val(entry) &= ~_PAGE_PROTECT; + } + if (!(pte_val(entry) & _PAGE_PROTECT)) + /* This pte allows write access, set user-dirty */ + pgste_val(pgste) |= PGSTE_UC_BIT; } *ptep = entry; + return pgste; } /** @@ -884,7 +870,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pgste = pgste_get_lock(ptep); pgste_val(pgste) &= ~_PGSTE_GPS_ZERO; pgste_set_key(ptep, pgste, entry, mm); - pgste_set_pte(ptep, entry); + pgste = pgste_set_pte(ptep, pgste, entry); pgste_set_unlock(ptep, pgste); } else { if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1) @@ -1030,45 +1016,6 @@ static inline pte_t pte_mkhuge(pte_t pte) } #endif -/* - * Get (and clear) the user dirty bit for a pte. - */ -static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, - pte_t *ptep) -{ - pgste_t pgste; - int dirty = 0; - - if (mm_has_pgste(mm)) { - pgste = pgste_get_lock(ptep); - pgste = pgste_update_all(ptep, pgste, mm); - dirty = !!(pgste_val(pgste) & PGSTE_HC_BIT); - pgste_val(pgste) &= ~PGSTE_HC_BIT; - pgste_set_unlock(ptep, pgste); - return dirty; - } - return dirty; -} - -/* - * Get (and clear) the user referenced bit for a pte. - */ -static inline int ptep_test_and_clear_user_young(struct mm_struct *mm, - pte_t *ptep) -{ - pgste_t pgste; - int young = 0; - - if (mm_has_pgste(mm)) { - pgste = pgste_get_lock(ptep); - pgste = pgste_update_young(ptep, pgste, mm); - young = !!(pgste_val(pgste) & PGSTE_HR_BIT); - pgste_val(pgste) &= ~PGSTE_HR_BIT; - pgste_set_unlock(ptep, pgste); - } - return young; -} - static inline void __ptep_ipte(unsigned long address, pte_t *ptep) { unsigned long pto = (unsigned long) ptep; @@ -1131,6 +1078,36 @@ static inline void ptep_flush_lazy(struct mm_struct *mm, atomic_sub(0x10000, &mm->context.attach_count); } +/* + * Get (and clear) the user dirty bit for a pte. + */ +static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm, + unsigned long addr, + pte_t *ptep) +{ + pgste_t pgste; + pte_t pte; + int dirty; + + if (!mm_has_pgste(mm)) + return 0; + pgste = pgste_get_lock(ptep); + dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT); + pgste_val(pgste) &= ~PGSTE_UC_BIT; + pte = *ptep; + if (dirty && (pte_val(pte) & _PAGE_PRESENT)) { + pgste = pgste_ipte_notify(mm, ptep, pgste); + __ptep_ipte(addr, ptep); + if (MACHINE_HAS_ESOP || !(pte_val(pte) & _PAGE_WRITE)) + pte_val(pte) |= _PAGE_PROTECT; + else + pte_val(pte) |= _PAGE_INVALID; + *ptep = pte; + } + pgste_set_unlock(ptep, pgste); + return dirty; +} + #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) @@ -1150,7 +1127,7 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, pte = pte_mkold(pte); if (mm_has_pgste(vma->vm_mm)) { - pgste_set_pte(ptep, pte); + pgste = pgste_set_pte(ptep, pgste, pte); pgste_set_unlock(ptep, pgste); } else *ptep = pte; @@ -1233,7 +1210,7 @@ static inline void ptep_modify_prot_commit(struct mm_struct *mm, if (mm_has_pgste(mm)) { pgste = pgste_get(ptep); pgste_set_key(ptep, pgste, pte, mm); - pgste_set_pte(ptep, pte); + pgste = pgste_set_pte(ptep, pgste, pte); pgste_set_unlock(ptep, pgste); } else *ptep = pte; @@ -1314,7 +1291,7 @@ static inline pte_t ptep_set_wrprotect(struct mm_struct *mm, pte = pte_wrprotect(pte); if (mm_has_pgste(mm)) { - pgste_set_pte(ptep, pte); + pgste = pgste_set_pte(ptep, pgste, pte); pgste_set_unlock(ptep, pgste); } else *ptep = pte; @@ -1339,7 +1316,7 @@ static inline int ptep_set_access_flags(struct vm_area_struct *vma, ptep_flush_direct(vma->vm_mm, address, ptep); if (mm_has_pgste(vma->vm_mm)) { - pgste_set_pte(ptep, entry); + pgste = pgste_set_pte(ptep, pgste, entry); pgste_set_unlock(ptep, pgste); } else *ptep = entry; diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 02a8607bbeb5..1ddf975352a0 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -832,6 +832,7 @@ void gmap_do_ipte_notify(struct mm_struct *mm, pte_t *pte) } spin_unlock(&gmap_notifier_lock); } +EXPORT_SYMBOL_GPL(gmap_do_ipte_notify); static inline int page_table_with_pgste(struct page *page) { @@ -864,8 +865,7 @@ static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm, atomic_set(&page->_mapcount, 0); table = (unsigned long *) page_to_phys(page); clear_table(table, _PAGE_INVALID, PAGE_SIZE/2); - clear_table(table + PTRS_PER_PTE, PGSTE_HR_BIT | PGSTE_HC_BIT, - PAGE_SIZE/2); + clear_table(table + PTRS_PER_PTE, 0, PAGE_SIZE/2); return table; } @@ -1005,7 +1005,7 @@ int set_guest_storage_key(struct mm_struct *mm, unsigned long addr, /* changing the guest storage key is considered a change of the page */ if ((pgste_val(new) ^ pgste_val(old)) & (PGSTE_ACC_BITS | PGSTE_FP_BIT | PGSTE_GR_BIT | PGSTE_GC_BIT)) - pgste_val(new) |= PGSTE_HC_BIT; + pgste_val(new) |= PGSTE_UC_BIT; pgste_set_unlock(ptep, new); pte_unmap_unlock(*ptep, ptl); -- cgit v1.2.3 From a0bf4f149bbfa2e31b5f4172c817afdb7b986733 Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Mon, 24 Mar 2014 14:27:58 +0100 Subject: KVM: s390/mm: new gmap_test_and_clear_dirty function For live migration kvm needs to test and clear the dirty bit of guest pages. That for is ptep_test_and_clear_user_dirty, to be sure we are not racing with other code, we protect the pte. This needs to be done within the architecture memory management code. Signed-off-by: Dominik Dingel Acked-by: Martin Schwidefsky Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/pgtable.h | 2 ++ arch/s390/mm/pgtable.c | 21 +++++++++++++++++++++ 2 files changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index b2c630df0ca5..fcba5e03839f 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -838,6 +838,8 @@ unsigned long __gmap_fault(unsigned long address, struct gmap *); unsigned long gmap_fault(unsigned long address, struct gmap *); void gmap_discard(unsigned long from, unsigned long to, struct gmap *); void __gmap_zap(unsigned long address, struct gmap *); +bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *); + void gmap_register_ipte_notifier(struct gmap_notifier *); void gmap_unregister_ipte_notifier(struct gmap_notifier *); diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 1ddf975352a0..ea4a31b95990 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c @@ -1401,6 +1401,27 @@ void s390_enable_skey(void) } EXPORT_SYMBOL_GPL(s390_enable_skey); +/* + * Test and reset if a guest page is dirty + */ +bool gmap_test_and_clear_dirty(unsigned long address, struct gmap *gmap) +{ + pte_t *pte; + spinlock_t *ptl; + bool dirty = false; + + pte = get_locked_pte(gmap->mm, address, &ptl); + if (unlikely(!pte)) + return false; + + if (ptep_test_and_clear_user_dirty(gmap->mm, address, pte)) + dirty = true; + + spin_unlock(ptl); + return dirty; +} +EXPORT_SYMBOL_GPL(gmap_test_and_clear_dirty); + #ifdef CONFIG_TRANSPARENT_HUGEPAGE int pmdp_clear_flush_young(struct vm_area_struct *vma, unsigned long address, pmd_t *pmdp) -- cgit v1.2.3 From 15f36ebd34b5b296c274ef67024f14c2d394a507 Mon Sep 17 00:00:00 2001 From: "Jason J. Herne" Date: Thu, 2 Aug 2012 10:10:17 -0400 Subject: KVM: s390: Add proper dirty bitmap support to S390 kvm. Replace the kvm_s390_sync_dirty_log() stub with code to construct the KVM dirty_bitmap from S390 memory change bits. Also add code to properly clear the dirty_bitmap size when clearing the bitmap. Signed-off-by: Jason J. Herne CC: Dominik Dingel [Dominik Dingel: use gmap_test_and_clear_dirty, locking fixes] Signed-off-by: Christian Borntraeger --- arch/s390/kvm/kvm-s390.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++- virt/kvm/kvm_main.c | 2 -- 2 files changed, 50 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index b767ec97368a..346a3478dd00 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -11,6 +11,7 @@ * Christian Borntraeger * Heiko Carstens * Christian Ehrhardt + * Jason J. Herne */ #include @@ -179,6 +180,25 @@ int kvm_dev_ioctl_check_extension(long ext) return r; } +static void kvm_s390_sync_dirty_log(struct kvm *kvm, + struct kvm_memory_slot *memslot) +{ + gfn_t cur_gfn, last_gfn; + unsigned long address; + struct gmap *gmap = kvm->arch.gmap; + + down_read(&gmap->mm->mmap_sem); + /* Loop over all guest pages */ + last_gfn = memslot->base_gfn + memslot->npages; + for (cur_gfn = memslot->base_gfn; cur_gfn <= last_gfn; cur_gfn++) { + address = gfn_to_hva_memslot(memslot, cur_gfn); + + if (gmap_test_and_clear_dirty(address, gmap)) + mark_page_dirty(kvm, cur_gfn); + } + up_read(&gmap->mm->mmap_sem); +} + /* Section: vm related */ /* * Get (and clear) the dirty memory log for a memory slot. @@ -186,7 +206,36 @@ int kvm_dev_ioctl_check_extension(long ext) int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) { - return 0; + int r; + unsigned long n; + struct kvm_memory_slot *memslot; + int is_dirty = 0; + + mutex_lock(&kvm->slots_lock); + + r = -EINVAL; + if (log->slot >= KVM_USER_MEM_SLOTS) + goto out; + + memslot = id_to_memslot(kvm->memslots, log->slot); + r = -ENOENT; + if (!memslot->dirty_bitmap) + goto out; + + kvm_s390_sync_dirty_log(kvm, memslot); + r = kvm_get_dirty_log(kvm, log, &is_dirty); + if (r) + goto out; + + /* Clear the dirty log */ + if (is_dirty) { + n = kvm_dirty_bitmap_bytes(memslot); + memset(memslot->dirty_bitmap, 0, n); + } + r = 0; +out: + mutex_unlock(&kvm->slots_lock); + return r; } static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 56baae8c2f56..7facdb1f1374 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -637,14 +637,12 @@ static int kvm_vm_release(struct inode *inode, struct file *filp) */ static int kvm_create_dirty_bitmap(struct kvm_memory_slot *memslot) { -#ifndef CONFIG_S390 unsigned long dirty_bytes = 2 * kvm_dirty_bitmap_bytes(memslot); memslot->dirty_bitmap = kvm_kvzalloc(dirty_bytes); if (!memslot->dirty_bitmap) return -ENOMEM; -#endif /* !CONFIG_S390 */ return 0; } -- cgit v1.2.3 From 3309a8e22d9ca4fa4dada687372b682bc6a12343 Mon Sep 17 00:00:00 2001 From: Matthew Leach Date: Fri, 14 Mar 2014 10:18:21 +0000 Subject: dts: ca5: add the global timer for the A5 The Cortex A5 contains a global timer: add the appropriate device tree node. Acked-by: Mark Rutland Signed-off-by: Matthew Leach Signed-off-by: Daniel Lezcano --- arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index c544a5504591..d2709b73316b 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -88,6 +88,14 @@ interrupts = <1 13 0x304>; }; + timer@2c000200 { + compatible = "arm,cortex-a5-global-timer", + "arm,cortex-a9-global-timer"; + reg = <0x2c000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&oscclk0>; + }; + watchdog@2c000620 { compatible = "arm,cortex-a5-twd-wdt"; reg = <0x2c000620 0x20>; @@ -120,7 +128,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0: osc@0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; -- cgit v1.2.3 From 7e13c654f446e3c9848ac0b725ae4daf25e10846 Mon Sep 17 00:00:00 2001 From: Matthew Leach Date: Fri, 14 Mar 2014 10:18:22 +0000 Subject: KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform The Cortex A5 now contains bindings for the global timer driver. Ensure that the driver is built with a vexpress platform. Signed-off-by: Matthew Leach Signed-off-by: Daniel Lezcano --- arch/arm/mach-vexpress/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 657d52d0391f..e9811a07829a 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -4,6 +4,7 @@ config ARCH_VEXPRESS select ARCH_SUPPORTS_BIG_ENDIAN select ARM_AMBA select ARM_GIC + select ARM_GLOBAL_TIMER select ARM_TIMER_SP804 select COMMON_CLK_VERSATILE select HAVE_ARM_SCU if SMP -- cgit v1.2.3 From f2061656209fb9a5d54bbb1999f0a633438504e7 Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Wed, 9 Apr 2014 13:13:00 +0200 Subject: KVM: s390: Per-vm kvm device controls We sometimes need to get/set attributes specific to a virtual machine and so need something else than ONE_REG. Let's copy the KVM_DEVICE approach, and define the respective ioctls for the vm file descriptor. Signed-off-by: Dominik Dingel Reviewed-by: Cornelia Huck Acked-by: Alexander Graf Signed-off-by: Christian Borntraeger --- Documentation/virtual/kvm/api.txt | 8 ++--- Documentation/virtual/kvm/devices/vm.txt | 10 ++++++ arch/s390/kvm/kvm-s390.c | 54 ++++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 1 + 4 files changed, 69 insertions(+), 4 deletions(-) create mode 100644 Documentation/virtual/kvm/devices/vm.txt (limited to 'arch') diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index a9380ba54c8e..2014ff12b492 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2314,8 +2314,8 @@ struct kvm_create_device { 4.80 KVM_SET_DEVICE_ATTR/KVM_GET_DEVICE_ATTR -Capability: KVM_CAP_DEVICE_CTRL -Type: device ioctl +Capability: KVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device +Type: device ioctl, vm ioctl Parameters: struct kvm_device_attr Returns: 0 on success, -1 on error Errors: @@ -2340,8 +2340,8 @@ struct kvm_device_attr { 4.81 KVM_HAS_DEVICE_ATTR -Capability: KVM_CAP_DEVICE_CTRL -Type: device ioctl +Capability: KVM_CAP_DEVICE_CTRL, KVM_CAP_VM_ATTRIBUTES for vm device +Type: device ioctl, vm ioctl Parameters: struct kvm_device_attr Returns: 0 on success, -1 on error Errors: diff --git a/Documentation/virtual/kvm/devices/vm.txt b/Documentation/virtual/kvm/devices/vm.txt new file mode 100644 index 000000000000..562bee6e600b --- /dev/null +++ b/Documentation/virtual/kvm/devices/vm.txt @@ -0,0 +1,10 @@ +Generic vm interface +==================================== + +The virtual machine "device" also accepts the ioctls KVM_SET_DEVICE_ATTR, +KVM_GET_DEVICE_ATTR, and KVM_HAS_DEVICE_ATTR. The interface uses the same +struct kvm_device_attr as other devices, but targets VM-wide settings +and controls. + +The groups and attributes per virtual machine, if any, are architecture +specific. diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 346a3478dd00..c335a2efa5de 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -162,6 +162,7 @@ int kvm_dev_ioctl_check_extension(long ext) case KVM_CAP_IOEVENTFD: case KVM_CAP_DEVICE_CTRL: case KVM_CAP_ENABLE_CAP_VM: + case KVM_CAP_VM_ATTRIBUTES: r = 1; break; case KVM_CAP_NR_VCPUS: @@ -257,11 +258,43 @@ static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) return r; } +static int kvm_s390_vm_set_attr(struct kvm *kvm, struct kvm_device_attr *attr) +{ + int ret; + + switch (attr->group) { + default: + ret = -ENXIO; + break; + } + + return ret; +} + +static int kvm_s390_vm_get_attr(struct kvm *kvm, struct kvm_device_attr *attr) +{ + return -ENXIO; +} + +static int kvm_s390_vm_has_attr(struct kvm *kvm, struct kvm_device_attr *attr) +{ + int ret; + + switch (attr->group) { + default: + ret = -ENXIO; + break; + } + + return ret; +} + long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) { struct kvm *kvm = filp->private_data; void __user *argp = (void __user *)arg; + struct kvm_device_attr attr; int r; switch (ioctl) { @@ -294,6 +327,27 @@ long kvm_arch_vm_ioctl(struct file *filp, } break; } + case KVM_SET_DEVICE_ATTR: { + r = -EFAULT; + if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) + break; + r = kvm_s390_vm_set_attr(kvm, &attr); + break; + } + case KVM_GET_DEVICE_ATTR: { + r = -EFAULT; + if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) + break; + r = kvm_s390_vm_get_attr(kvm, &attr); + break; + } + case KVM_HAS_DEVICE_ATTR: { + r = -EFAULT; + if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) + break; + r = kvm_s390_vm_has_attr(kvm, &attr); + break; + } default: r = -ENOTTY; } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index a8f4ee5d2e82..90acfe4966e7 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -743,6 +743,7 @@ struct kvm_ppc_smmu_info { #define KVM_CAP_IOAPIC_POLARITY_IGNORED 97 #define KVM_CAP_ENABLE_CAP_VM 98 #define KVM_CAP_S390_IRQCHIP 99 +#define KVM_CAP_VM_ATTRIBUTES 100 #ifdef KVM_CAP_IRQ_ROUTING -- cgit v1.2.3 From b31605c12f4edda7a40ad9f86985739666298c31 Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Tue, 25 Mar 2014 13:47:11 +0100 Subject: KVM: s390: make cmma usage conditionally When userspace reset the guest without notifying kvm, the CMMA state of the pages might be unused, resulting in guest data corruption. To avoid this, CMMA must be enabled only if userspace understands the implications. CMMA must be enabled before vCPU creation. It can't be switched off once enabled. All subsequently created vCPUs will be enabled for CMMA according to the CMMA state of the VM. Signed-off-by: Dominik Dingel Signed-off-by: Christian Borntraeger [remove now unnecessary calls to page_table_reset_pgste] --- arch/s390/include/asm/kvm_host.h | 1 + arch/s390/kvm/diag.c | 6 ---- arch/s390/kvm/kvm-s390.c | 59 +++++++++++++++++++++++++--------------- arch/s390/kvm/kvm-s390.h | 7 +++-- arch/s390/kvm/priv.c | 2 +- 5 files changed, 44 insertions(+), 31 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index a993b6f3429f..b61ac418b510 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -288,6 +288,7 @@ struct kvm_arch{ struct gmap *gmap; int css_support; int use_irqchip; + int use_cmma; struct s390_io_adapter *adapters[MAX_S390_IO_ADAPTERS]; }; diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index 44dcfa8860b5..ff768f1dd337 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -167,17 +167,11 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu) VCPU_EVENT(vcpu, 5, "diag ipl functions, subcode %lx", subcode); switch (subcode) { - case 0: - case 1: - page_table_reset_pgste(current->mm, 0, TASK_SIZE, false); - return -EOPNOTSUPP; case 3: vcpu->run->s390_reset_flags = KVM_S390_RESET_CLEAR; - page_table_reset_pgste(current->mm, 0, TASK_SIZE, false); break; case 4: vcpu->run->s390_reset_flags = 0; - page_table_reset_pgste(current->mm, 0, TASK_SIZE, false); break; default: return -EOPNOTSUPP; diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index c335a2efa5de..fc2fe49488c0 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -437,9 +437,8 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) if (kvm_is_ucontrol(vcpu->kvm)) gmap_free(vcpu->arch.gmap); - if (vcpu->arch.sie_block->cbrlo) - __free_page(__pfn_to_page( - vcpu->arch.sie_block->cbrlo >> PAGE_SHIFT)); + if (kvm_s390_cmma_enabled(vcpu->kvm)) + kvm_s390_vcpu_unsetup_cmma(vcpu); free_page((unsigned long)(vcpu->arch.sie_block)); kvm_vcpu_uninit(vcpu); @@ -553,9 +552,26 @@ int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) return 0; } +void kvm_s390_vcpu_unsetup_cmma(struct kvm_vcpu *vcpu) +{ + free_page(vcpu->arch.sie_block->cbrlo); + vcpu->arch.sie_block->cbrlo = 0; +} + +int kvm_s390_vcpu_setup_cmma(struct kvm_vcpu *vcpu) +{ + vcpu->arch.sie_block->cbrlo = get_zeroed_page(GFP_KERNEL); + if (!vcpu->arch.sie_block->cbrlo) + return -ENOMEM; + + vcpu->arch.sie_block->ecb2 |= 0x80; + vcpu->arch.sie_block->ecb2 &= ~0x08; + return 0; +} + int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) { - struct page *cbrl; + int rc = 0; atomic_set(&vcpu->arch.sie_block->cpuflags, CPUSTAT_ZARCH | CPUSTAT_SM | @@ -569,13 +585,10 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) vcpu->arch.sie_block->eca = 0xC1002001U; vcpu->arch.sie_block->fac = (int) (long) vfacilities; vcpu->arch.sie_block->ictl |= ICTL_ISKE | ICTL_SSKE | ICTL_RRBE; - if (kvm_enabled_cmma()) { - cbrl = alloc_page(GFP_KERNEL | __GFP_ZERO); - if (cbrl) { - vcpu->arch.sie_block->ecb2 |= 0x80; - vcpu->arch.sie_block->ecb2 &= ~0x08; - vcpu->arch.sie_block->cbrlo = page_to_phys(cbrl); - } + if (kvm_s390_cmma_enabled(vcpu->kvm)) { + rc = kvm_s390_vcpu_setup_cmma(vcpu); + if (rc) + return rc; } hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); tasklet_init(&vcpu->arch.tasklet, kvm_s390_tasklet, @@ -583,7 +596,7 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) vcpu->arch.ckc_timer.function = kvm_s390_idle_wakeup; get_cpu_id(&vcpu->arch.cpu_id); vcpu->arch.cpu_id.version = 0xff; - return 0; + return rc; } struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, @@ -890,6 +903,18 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, return -EINVAL; /* not implemented yet */ } +bool kvm_s390_cmma_enabled(struct kvm *kvm) +{ + if (!MACHINE_IS_LPAR) + return false; + /* only enable for z10 and later */ + if (!MACHINE_HAS_EDAT1) + return false; + if (!kvm->arch.use_cmma) + return false; + return true; +} + static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu) { /* @@ -1072,16 +1097,6 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason) return rc; } -bool kvm_enabled_cmma(void) -{ - if (!MACHINE_IS_LPAR) - return false; - /* only enable for z10 and later */ - if (!MACHINE_HAS_EDAT1) - return false; - return true; -} - static int __vcpu_run(struct kvm_vcpu *vcpu) { int rc, exit_reason; diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 3c1e2274d9ea..460ccd828bbb 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -158,8 +158,11 @@ void s390_vcpu_block(struct kvm_vcpu *vcpu); void s390_vcpu_unblock(struct kvm_vcpu *vcpu); void exit_sie(struct kvm_vcpu *vcpu); void exit_sie_sync(struct kvm_vcpu *vcpu); -/* are we going to support cmma? */ -bool kvm_enabled_cmma(void); +int kvm_s390_vcpu_setup_cmma(struct kvm_vcpu *vcpu); +void kvm_s390_vcpu_unsetup_cmma(struct kvm_vcpu *vcpu); +/* is cmma enabled */ +bool kvm_s390_cmma_enabled(struct kvm *kvm); + /* implemented in diag.c */ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu); diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 8a63e992936b..9a04d74c5fb4 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -656,7 +656,7 @@ static int handle_essa(struct kvm_vcpu *vcpu) VCPU_EVENT(vcpu, 5, "cmma release %d pages", entries); gmap = vcpu->arch.gmap; vcpu->stat.instruction_essa++; - if (!kvm_enabled_cmma() || !vcpu->arch.sie_block->cbrlo) + if (!kvm_s390_cmma_enabled(vcpu->kvm)) return kvm_s390_inject_program_int(vcpu, PGM_OPERATION); if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) -- cgit v1.2.3 From 4f718eab262868aeab83774ec4ce25e6a9906657 Mon Sep 17 00:00:00 2001 From: Dominik Dingel Date: Wed, 9 Apr 2014 13:13:00 +0200 Subject: KVM: s390: Exploiting generic userspace interface for cmma To enable CMMA and to reset its state we use the vm kvm_device ioctls, encapsulating attributes within the KVM_S390_VM_MEM_CTRL group. Signed-off-by: Dominik Dingel Signed-off-by: Christian Borntraeger --- Documentation/virtual/kvm/devices/vm.txt | 16 ++++++++++++ arch/s390/include/uapi/asm/kvm.h | 7 ++++++ arch/s390/kvm/kvm-s390.c | 43 ++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) (limited to 'arch') diff --git a/Documentation/virtual/kvm/devices/vm.txt b/Documentation/virtual/kvm/devices/vm.txt index 562bee6e600b..0d16f96c0eac 100644 --- a/Documentation/virtual/kvm/devices/vm.txt +++ b/Documentation/virtual/kvm/devices/vm.txt @@ -8,3 +8,19 @@ and controls. The groups and attributes per virtual machine, if any, are architecture specific. + +1. GROUP: KVM_S390_VM_MEM_CTRL +Architectures: s390 + +1.1. ATTRIBUTE: KVM_S390_VM_MEM_CTRL +Parameters: none +Returns: -EBUSY if already a vcpus is defined, otherwise 0 + +Enables CMMA for the virtual machine + +1.2. ATTRIBUTE: KVM_S390_VM_CLR_CMMA +Parameteres: none +Returns: 0 + +Clear the CMMA status for all guest pages, so any pages the guest marked +as unused are again used any may not be reclaimed by the host. diff --git a/arch/s390/include/uapi/asm/kvm.h b/arch/s390/include/uapi/asm/kvm.h index c003c6a73b1e..e35c79821d29 100644 --- a/arch/s390/include/uapi/asm/kvm.h +++ b/arch/s390/include/uapi/asm/kvm.h @@ -54,6 +54,13 @@ struct kvm_s390_io_adapter_req { __u64 addr; }; +/* kvm attr_group on vm fd */ +#define KVM_S390_VM_MEM_CTRL 0 + +/* kvm attributes for mem_ctrl */ +#define KVM_S390_VM_MEM_ENABLE_CMMA 0 +#define KVM_S390_VM_MEM_CLR_CMMA 1 + /* for KVM_GET_REGS and KVM_SET_REGS */ struct kvm_regs { /* general purpose regs for s390 */ diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index fc2fe49488c0..fe2396cc0856 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -258,11 +258,43 @@ static int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) return r; } +static int kvm_s390_mem_control(struct kvm *kvm, struct kvm_device_attr *attr) +{ + int ret; + unsigned int idx; + switch (attr->attr) { + case KVM_S390_VM_MEM_ENABLE_CMMA: + ret = -EBUSY; + mutex_lock(&kvm->lock); + if (atomic_read(&kvm->online_vcpus) == 0) { + kvm->arch.use_cmma = 1; + ret = 0; + } + mutex_unlock(&kvm->lock); + break; + case KVM_S390_VM_MEM_CLR_CMMA: + mutex_lock(&kvm->lock); + idx = srcu_read_lock(&kvm->srcu); + page_table_reset_pgste(kvm->arch.gmap->mm, 0, TASK_SIZE, false); + srcu_read_unlock(&kvm->srcu, idx); + mutex_unlock(&kvm->lock); + ret = 0; + break; + default: + ret = -ENXIO; + break; + } + return ret; +} + static int kvm_s390_vm_set_attr(struct kvm *kvm, struct kvm_device_attr *attr) { int ret; switch (attr->group) { + case KVM_S390_VM_MEM_CTRL: + ret = kvm_s390_mem_control(kvm, attr); + break; default: ret = -ENXIO; break; @@ -281,6 +313,17 @@ static int kvm_s390_vm_has_attr(struct kvm *kvm, struct kvm_device_attr *attr) int ret; switch (attr->group) { + case KVM_S390_VM_MEM_CTRL: + switch (attr->attr) { + case KVM_S390_VM_MEM_ENABLE_CMMA: + case KVM_S390_VM_MEM_CLR_CMMA: + ret = 0; + break; + default: + ret = -ENXIO; + break; + } + break; default: ret = -ENXIO; break; -- cgit v1.2.3 From bcd846837c43ccccc932036d5a634bee48f1ff4f Mon Sep 17 00:00:00 2001 From: Jens Freimann Date: Tue, 11 Feb 2014 11:07:05 +0100 Subject: KVM: s390: allow injecting every kind of interrupt Add a new data structure and function that allows to inject all kinds of interrupt as defined in the PoP Signed-off-by: Jens Freimann Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 59 +++++++++++++++++++++++++++++++++++----- arch/s390/kvm/interrupt.c | 25 +++++++++++++++++ arch/s390/kvm/kvm-s390.h | 3 ++ 3 files changed, 80 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index b61ac418b510..90905ca93725 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -186,13 +186,58 @@ struct kvm_vcpu_stat { u32 diagnose_9c; }; -#define PGM_OPERATION 0x01 -#define PGM_PRIVILEGED_OP 0x02 -#define PGM_EXECUTE 0x03 -#define PGM_PROTECTION 0x04 -#define PGM_ADDRESSING 0x05 -#define PGM_SPECIFICATION 0x06 -#define PGM_DATA 0x07 +#define PGM_OPERATION 0x01 +#define PGM_PRIVILEGED_OP 0x02 +#define PGM_EXECUTE 0x03 +#define PGM_PROTECTION 0x04 +#define PGM_ADDRESSING 0x05 +#define PGM_SPECIFICATION 0x06 +#define PGM_DATA 0x07 +#define PGM_FIXED_POINT_OVERFLOW 0x08 +#define PGM_FIXED_POINT_DIVIDE 0x09 +#define PGM_DECIMAL_OVERFLOW 0x0a +#define PGM_DECIMAL_DIVIDE 0x0b +#define PGM_HFP_EXPONENT_OVERFLOW 0x0c +#define PGM_HFP_EXPONENT_UNDERFLOW 0x0d +#define PGM_HFP_SIGNIFICANCE 0x0e +#define PGM_HFP_DIVIDE 0x0f +#define PGM_SEGMENT_TRANSLATION 0x10 +#define PGM_PAGE_TRANSLATION 0x11 +#define PGM_TRANSLATION_SPEC 0x12 +#define PGM_SPECIAL_OPERATION 0x13 +#define PGM_OPERAND 0x15 +#define PGM_TRACE_TABEL 0x16 +#define PGM_SPACE_SWITCH 0x1c +#define PGM_HFP_SQUARE_ROOT 0x1d +#define PGM_PC_TRANSLATION_SPEC 0x1f +#define PGM_AFX_TRANSLATION 0x20 +#define PGM_ASX_TRANSLATION 0x21 +#define PGM_LX_TRANSLATION 0x22 +#define PGM_EX_TRANSLATION 0x23 +#define PGM_PRIMARY_AUTHORITY 0x24 +#define PGM_SECONDARY_AUTHORITY 0x25 +#define PGM_LFX_TRANSLATION 0x26 +#define PGM_LSX_TRANSLATION 0x27 +#define PGM_ALET_SPECIFICATION 0x28 +#define PGM_ALEN_TRANSLATION 0x29 +#define PGM_ALE_SEQUENCE 0x2a +#define PGM_ASTE_VALIDITY 0x2b +#define PGM_ASTE_SEQUENCE 0x2c +#define PGM_EXTENDED_AUTHORITY 0x2d +#define PGM_LSTE_SEQUENCE 0x2e +#define PGM_ASTE_INSTANCE 0x2f +#define PGM_STACK_FULL 0x30 +#define PGM_STACK_EMPTY 0x31 +#define PGM_STACK_SPECIFICATION 0x32 +#define PGM_STACK_TYPE 0x33 +#define PGM_STACK_OPERATION 0x34 +#define PGM_ASCE_TYPE 0x38 +#define PGM_REGION_FIRST_TRANS 0x39 +#define PGM_REGION_SECOND_TRANS 0x3a +#define PGM_REGION_THIRD_TRANS 0x3b +#define PGM_MONITOR 0x40 +#define PGM_PER 0x80 +#define PGM_CRYPTO_OPERATION 0x119 struct kvm_s390_interrupt_info { struct list_head list; diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index 200a8f9390b6..a44c68990cf4 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -660,6 +660,31 @@ int kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code) return 0; } +int kvm_s390_inject_prog_irq(struct kvm_vcpu *vcpu, + struct kvm_s390_pgm_info *pgm_info) +{ + struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int; + struct kvm_s390_interrupt_info *inti; + + inti = kzalloc(sizeof(*inti), GFP_KERNEL); + if (!inti) + return -ENOMEM; + + VCPU_EVENT(vcpu, 3, "inject: prog irq %d (from kernel)", + pgm_info->code); + trace_kvm_s390_inject_vcpu(vcpu->vcpu_id, KVM_S390_PROGRAM_INT, + pgm_info->code, 0, 1); + + inti->type = KVM_S390_PROGRAM_INT; + memcpy(&inti->pgm, pgm_info, sizeof(inti->pgm)); + spin_lock_bh(&li->lock); + list_add(&inti->list, &li->list); + atomic_set(&li->active, 1); + BUG_ON(waitqueue_active(li->wq)); + spin_unlock_bh(&li->lock); + return 0; +} + struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm, u64 cr6, u64 schid) { diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 460ccd828bbb..25a8b8478918 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -165,6 +165,9 @@ bool kvm_s390_cmma_enabled(struct kvm *kvm); /* implemented in diag.c */ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu); +/* implemented in interrupt.c */ +int kvm_s390_inject_prog_irq(struct kvm_vcpu *vcpu, + struct kvm_s390_pgm_info *pgm_info); /* implemented in interrupt.c */ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); -- cgit v1.2.3 From 280ef0f1f982e4bd9a22ee3627ca06dccde59a64 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 17 Dec 2013 09:08:28 +0100 Subject: KVM: s390: export test_vfacility() Make test_vfacility() available for other files. This is needed for the new guest access functions, which test if certain facilities are available for a guest. Signed-off-by: Heiko Carstens Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/kvm-s390.c | 2 +- arch/s390/kvm/kvm-s390.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index fe2396cc0856..4b1df682e5c3 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -91,7 +91,7 @@ unsigned long *vfacilities; static struct gmap_notifier gmap_notifier; /* test availability of vfacility */ -static inline int test_vfacility(unsigned long nr) +int test_vfacility(unsigned long nr) { return __test_facility(nr, (void *) vfacilities); } diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 25a8b8478918..f3ab9fcad496 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -162,6 +162,7 @@ int kvm_s390_vcpu_setup_cmma(struct kvm_vcpu *vcpu); void kvm_s390_vcpu_unsetup_cmma(struct kvm_vcpu *vcpu); /* is cmma enabled */ bool kvm_s390_cmma_enabled(struct kvm *kvm); +int test_vfacility(unsigned long nr); /* implemented in diag.c */ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu); -- cgit v1.2.3 From 1365632bdeb42e5e252566bb08c0d7d68640edd3 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:08:06 +0100 Subject: s390/ptrace: add struct psw and accessor function Introduce a 'struct psw' which makes it easier to decode and test if certain bits in a psw are set or are not set. In addition also add a 'psw_bits()' helper define which allows to directly modify and test a psw_t structure. E.g. psw_t psw; psw_bits(psw).t = 1; /* set dat bit */ Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/ptrace.h | 44 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h index f4783c0b7b43..6e7708f3d866 100644 --- a/arch/s390/include/asm/ptrace.h +++ b/arch/s390/include/asm/ptrace.h @@ -16,6 +16,50 @@ PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_MCHECK | \ PSW_MASK_PSTATE | PSW_ASC_PRIMARY) +struct psw_bits { + unsigned long long : 1; + unsigned long long r : 1; /* PER-Mask */ + unsigned long long : 3; + unsigned long long t : 1; /* DAT Mode */ + unsigned long long i : 1; /* Input/Output Mask */ + unsigned long long e : 1; /* External Mask */ + unsigned long long key : 4; /* PSW Key */ + unsigned long long : 1; + unsigned long long m : 1; /* Machine-Check Mask */ + unsigned long long w : 1; /* Wait State */ + unsigned long long p : 1; /* Problem State */ + unsigned long long as : 2; /* Address Space Control */ + unsigned long long cc : 2; /* Condition Code */ + unsigned long long pm : 4; /* Program Mask */ + unsigned long long ri : 1; /* Runtime Instrumentation */ + unsigned long long : 6; + unsigned long long eaba : 2; /* Addressing Mode */ +#ifdef CONFIG_64BIT + unsigned long long : 31; + unsigned long long ia : 64;/* Instruction Address */ +#else + unsigned long long ia : 31;/* Instruction Address */ +#endif +}; + +enum { + PSW_AMODE_24BIT = 0, + PSW_AMODE_31BIT = 1, + PSW_AMODE_64BIT = 3 +}; + +enum { + PSW_AS_PRIMARY = 0, + PSW_AS_ACCREG = 1, + PSW_AS_SECONDARY = 2, + PSW_AS_HOME = 3 +}; + +#define psw_bits(__psw) (*({ \ + typecheck(psw_t, __psw); \ + &(*(struct psw_bits *)(&(__psw))); \ +})) + /* * The pt_regs struct defines the way the registers are stored on * the stack during a system call. -- cgit v1.2.3 From 5f4e87a227757198f4cf0495f7fd6c47a28aacb6 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:08:37 +0100 Subject: s390/ctl_reg: add union type for control register 0 Add 'union ctlreg0_bits' to easily allow setting and testing bits of control register 0 bits. This patch only adds the bits needed for the new guest access functions. Other bits and control registers can be added when needed. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/ctl_reg.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/asm/ctl_reg.h b/arch/s390/include/asm/ctl_reg.h index 4e63f1a13600..31ab9f346d7e 100644 --- a/arch/s390/include/asm/ctl_reg.h +++ b/arch/s390/include/asm/ctl_reg.h @@ -57,6 +57,20 @@ static inline void __ctl_clear_bit(unsigned int cr, unsigned int bit) void smp_ctl_set_bit(int cr, int bit); void smp_ctl_clear_bit(int cr, int bit); +union ctlreg0 { + unsigned long val; + struct { +#ifdef CONFIG_64BIT + unsigned long : 32; +#endif + unsigned long : 3; + unsigned long lap : 1; /* Low-address-protection control */ + unsigned long : 4; + unsigned long edat : 1; /* Enhanced-DAT-enablement control */ + unsigned long : 23; + }; +}; + #ifdef CONFIG_SMP # define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit) # define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit) -- cgit v1.2.3 From 072c9878eedc2f1ef2f0d19ac7680beeee97bf05 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:21:47 +0100 Subject: KVM: s390: add kvm_s390_logical_to_effective() helper Add kvm_s390_logical_to_effective() helper which converts a guest vcpu's logical storage address to a guest vcpu effective address by applying the rules of the vcpu's addressing mode defined by PSW bits 31 and 32 (extendended and basic addressing mode). Depending on the vcpu's addressing mode the upper 40 bits (24 bit addressing mode), 33 bits (31 bit addressing mode) or no bits (64 bit addressing mode) will be zeroed and the remaining bits will be returned. Signed-off-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/kvm/gaccess.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index 374a439ccc60..ae3cb638f220 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -30,6 +30,31 @@ static inline unsigned long kvm_s390_real_to_abs(struct kvm_vcpu *vcpu, return gaddr; } +/** + * kvm_s390_logical_to_effective - convert guest logical to effective address + * @vcpu: guest virtual cpu + * @ga: guest logical address + * + * Convert a guest vcpu logical address to a guest vcpu effective address by + * applying the rules of the vcpu's addressing mode defined by PSW bits 31 + * and 32 (extendended/basic addressing mode). + * + * Depending on the vcpu's addressing mode the upper 40 bits (24 bit addressing + * mode), 33 bits (31 bit addressing mode) or no bits (64 bit addressing mode) + * of @ga will be zeroed and the remaining bits will be returned. + */ +static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu, + unsigned long ga) +{ + psw_t *psw = &vcpu->arch.sie_block->gpsw; + + if (psw_bits(*psw).eaba == PSW_AMODE_64BIT) + return ga; + if (psw_bits(*psw).eaba == PSW_AMODE_31BIT) + return ga & ((1UL << 31) - 1); + return ga & ((1UL << 24) - 1); +} + static inline void __user *__gptr_to_uptr(struct kvm_vcpu *vcpu, void __user *gptr, int prefixing) -- cgit v1.2.3 From 1b0462e574f5238bb1ee811f014d629092c160cb Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:31:49 +0100 Subject: KVM: s390: add 'pgm' member to kvm_vcpu_arch and helper function Add a 'struct kvm_s390_pgm_info pgm' member to kvm_vcpu_arch. This structure will be used if during instruction emulation in the context of a vcpu exception data needs to be stored somewhere. Also add a helper function kvm_s390_inject_prog_cond() which can inject vcpu's last exception if needed. Signed-off-by: Heiko Carstens Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 1 + arch/s390/kvm/kvm-s390.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index 90905ca93725..c290d443d2c1 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -286,6 +286,7 @@ struct kvm_vcpu_arch { struct kvm_s390_local_interrupt local_int; struct hrtimer ckc_timer; struct tasklet_struct tasklet; + struct kvm_s390_pgm_info pgm; union { struct cpuid cpu_id; u64 stidp_data; diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index f3ab9fcad496..11ed0a596b5a 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -170,6 +170,39 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu); int kvm_s390_inject_prog_irq(struct kvm_vcpu *vcpu, struct kvm_s390_pgm_info *pgm_info); +/** + * kvm_s390_inject_prog_cond - conditionally inject a program check + * @vcpu: virtual cpu + * @rc: original return/error code + * + * This function is supposed to be used after regular guest access functions + * failed, to conditionally inject a program check to a vcpu. The typical + * pattern would look like + * + * rc = write_guest(vcpu, addr, data, len); + * if (rc) + * return kvm_s390_inject_prog_cond(vcpu, rc); + * + * A negative return code from guest access functions implies an internal error + * like e.g. out of memory. In these cases no program check should be injected + * to the guest. + * A positive value implies that an exception happened while accessing a guest's + * memory. In this case all data belonging to the corresponding program check + * has been stored in vcpu->arch.pgm and can be injected with + * kvm_s390_inject_prog_irq(). + * + * Returns: - the original @rc value if @rc was negative (internal error) + * - zero if @rc was already zero + * - zero or error code from injecting if @rc was positive + * (program check injected to @vcpu) + */ +static inline int kvm_s390_inject_prog_cond(struct kvm_vcpu *vcpu, int rc) +{ + if (rc <= 0) + return rc; + return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); +} + /* implemented in interrupt.c */ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); int psw_extint_disabled(struct kvm_vcpu *vcpu); -- cgit v1.2.3 From d95fb12ff4d73e897126043bb5d03a068997a2ef Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:23:29 +0100 Subject: KVM: s390: add lowcore access functions put_guest_lc, read_guest_lc and write_guest_lc are guest access functions which shall only be used to access the lowcore of a vcpu. These functions should be used for e.g. interrupt handlers where no guest memory access protection facilities, like key or low address protection, are applicable. At a later point guest vcpu lowcore access should happen via pinned prefix pages, so that these pages can be accessed directly via the kernel mapping. All of these *_lc functions can be removed then. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/gaccess.h | 95 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 93 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index ae3cb638f220..917aeaa04fff 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -1,7 +1,7 @@ /* * access guest memory * - * Copyright IBM Corp. 2008, 2009 + * Copyright IBM Corp. 2008, 2014 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License (version 2 only) @@ -15,7 +15,8 @@ #include #include -#include +#include +#include #include "kvm-s390.h" /* Convert real to absolute address by applying the prefix of the CPU */ @@ -136,4 +137,94 @@ static inline int __copy_guest(struct kvm_vcpu *vcpu, unsigned long to, #define copy_from_guest_absolute(vcpu, to, from, size) \ __copy_guest(vcpu, (unsigned long)to, from, size, 0, 0) +/* + * put_guest_lc, read_guest_lc and write_guest_lc are guest access functions + * which shall only be used to access the lowcore of a vcpu. + * These functions should be used for e.g. interrupt handlers where no + * guest memory access protection facilities, like key or low address + * protection, are applicable. + * At a later point guest vcpu lowcore access should happen via pinned + * prefix pages, so that these pages can be accessed directly via the + * kernel mapping. All of these *_lc functions can be removed then. + */ + +/** + * put_guest_lc - write a simple variable to a guest vcpu's lowcore + * @vcpu: virtual cpu + * @x: value to copy to guest + * @gra: vcpu's destination guest real address + * + * Copies a simple value from kernel space to a guest vcpu's lowcore. + * The size of the variable may be 1, 2, 4 or 8 bytes. The destination + * must be located in the vcpu's lowcore. Otherwise the result is undefined. + * + * Returns zero on success or -EFAULT on error. + * + * Note: an error indicates that either the kernel is out of memory or + * the guest memory mapping is broken. In any case the best solution + * would be to terminate the guest. + * It is wrong to inject a guest exception. + */ +#define put_guest_lc(vcpu, x, gra) \ +({ \ + struct kvm_vcpu *__vcpu = (vcpu); \ + __typeof__(*(gra)) __x = (x); \ + unsigned long __gpa; \ + \ + __gpa = (unsigned long)(gra); \ + __gpa += __vcpu->arch.sie_block->prefix; \ + kvm_write_guest(__vcpu->kvm, __gpa, &__x, sizeof(__x)); \ +}) + +/** + * write_guest_lc - copy data from kernel space to guest vcpu's lowcore + * @vcpu: virtual cpu + * @gra: vcpu's source guest real address + * @data: source address in kernel space + * @len: number of bytes to copy + * + * Copy data from kernel space to guest vcpu's lowcore. The entire range must + * be located within the vcpu's lowcore, otherwise the result is undefined. + * + * Returns zero on success or -EFAULT on error. + * + * Note: an error indicates that either the kernel is out of memory or + * the guest memory mapping is broken. In any case the best solution + * would be to terminate the guest. + * It is wrong to inject a guest exception. + */ +static inline __must_check +int write_guest_lc(struct kvm_vcpu *vcpu, unsigned long gra, void *data, + unsigned long len) +{ + unsigned long gpa = gra + vcpu->arch.sie_block->prefix; + + return kvm_write_guest(vcpu->kvm, gpa, data, len); +} + +/** + * read_guest_lc - copy data from guest vcpu's lowcore to kernel space + * @vcpu: virtual cpu + * @gra: vcpu's source guest real address + * @data: destination address in kernel space + * @len: number of bytes to copy + * + * Copy data from guest vcpu's lowcore to kernel space. The entire range must + * be located within the vcpu's lowcore, otherwise the result is undefined. + * + * Returns zero on success or -EFAULT on error. + * + * Note: an error indicates that either the kernel is out of memory or + * the guest memory mapping is broken. In any case the best solution + * would be to terminate the guest. + * It is wrong to inject a guest exception. + */ +static inline __must_check +int read_guest_lc(struct kvm_vcpu *vcpu, unsigned long gra, void *data, + unsigned long len) +{ + unsigned long gpa = gra + vcpu->arch.sie_block->prefix; + + return kvm_read_guest(vcpu->kvm, gpa, data, len); +} #endif /* __KVM_S390_GACCESS_H */ -- cgit v1.2.3 From 2293897805c2fea69e45aca31b3589d4590af89d Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:26:52 +0100 Subject: KVM: s390: add architecture compliant guest access functions The new guest memory access function write_guest() and read_guest() can be used to access guest memory in an architecture compliant way. These functions will look at the vcpu's PSW and select the correct address space for memory access and also perform correct address wrap around. In case DAT is turned on, page tables will be walked otherwise access will happen to real or absolute memory. Any access exception will be recognized and exception data will be stored in the vcpu's kvm_vcpu_arch.pgm member. Subsequently an exception can be injected if necessary. Missing are: - key protection checks - access register mode support - program event recording support This patch also adds write_guest_real(), read_guest_real(), write_guest_absolute() and read_guest_absolute() guest functions which can be used to access real and absolute storage. These functions currently do not perform any access checks, since there is no use case (yet?). Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/Makefile | 4 +- arch/s390/kvm/gaccess.c | 536 ++++++++++++++++++++++++++++++++++++++++++++++++ arch/s390/kvm/gaccess.h | 170 +++++++++++++++ 3 files changed, 709 insertions(+), 1 deletion(-) create mode 100644 arch/s390/kvm/gaccess.c (limited to 'arch') diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile index d3adb37e93a4..83a7a355befe 100644 --- a/arch/s390/kvm/Makefile +++ b/arch/s390/kvm/Makefile @@ -11,5 +11,7 @@ common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o $(KVM)/async_pf.o $(KVM)/irqch ccflags-y := -Ivirt/kvm -Iarch/s390/kvm -kvm-objs := $(common-objs) kvm-s390.o intercept.o interrupt.o priv.o sigp.o diag.o +kvm-objs := $(common-objs) kvm-s390.o intercept.o interrupt.o priv.o sigp.o +kvm-objs += diag.o gaccess.o + obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c new file mode 100644 index 000000000000..916e1ee1f8c9 --- /dev/null +++ b/arch/s390/kvm/gaccess.c @@ -0,0 +1,536 @@ +/* + * guest access functions + * + * Copyright IBM Corp. 2014 + * + */ + +#include +#include +#include +#include "kvm-s390.h" +#include "gaccess.h" + +union asce { + unsigned long val; + struct { + unsigned long origin : 52; /* Region- or Segment-Table Origin */ + unsigned long : 2; + unsigned long g : 1; /* Subspace Group Control */ + unsigned long p : 1; /* Private Space Control */ + unsigned long s : 1; /* Storage-Alteration-Event Control */ + unsigned long x : 1; /* Space-Switch-Event Control */ + unsigned long r : 1; /* Real-Space Control */ + unsigned long : 1; + unsigned long dt : 2; /* Designation-Type Control */ + unsigned long tl : 2; /* Region- or Segment-Table Length */ + }; +}; + +enum { + ASCE_TYPE_SEGMENT = 0, + ASCE_TYPE_REGION3 = 1, + ASCE_TYPE_REGION2 = 2, + ASCE_TYPE_REGION1 = 3 +}; + +union region1_table_entry { + unsigned long val; + struct { + unsigned long rto: 52;/* Region-Table Origin */ + unsigned long : 2; + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long : 1; + unsigned long tf : 2; /* Region-Second-Table Offset */ + unsigned long i : 1; /* Region-Invalid Bit */ + unsigned long : 1; + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long tl : 2; /* Region-Second-Table Length */ + }; +}; + +union region2_table_entry { + unsigned long val; + struct { + unsigned long rto: 52;/* Region-Table Origin */ + unsigned long : 2; + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long : 1; + unsigned long tf : 2; /* Region-Third-Table Offset */ + unsigned long i : 1; /* Region-Invalid Bit */ + unsigned long : 1; + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long tl : 2; /* Region-Third-Table Length */ + }; +}; + +struct region3_table_entry_fc0 { + unsigned long sto: 52;/* Segment-Table Origin */ + unsigned long : 1; + unsigned long fc : 1; /* Format-Control */ + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long : 1; + unsigned long tf : 2; /* Segment-Table Offset */ + unsigned long i : 1; /* Region-Invalid Bit */ + unsigned long cr : 1; /* Common-Region Bit */ + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long tl : 2; /* Segment-Table Length */ +}; + +struct region3_table_entry_fc1 { + unsigned long rfaa : 33; /* Region-Frame Absolute Address */ + unsigned long : 14; + unsigned long av : 1; /* ACCF-Validity Control */ + unsigned long acc: 4; /* Access-Control Bits */ + unsigned long f : 1; /* Fetch-Protection Bit */ + unsigned long fc : 1; /* Format-Control */ + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long co : 1; /* Change-Recording Override */ + unsigned long : 2; + unsigned long i : 1; /* Region-Invalid Bit */ + unsigned long cr : 1; /* Common-Region Bit */ + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long : 2; +}; + +union region3_table_entry { + unsigned long val; + struct region3_table_entry_fc0 fc0; + struct region3_table_entry_fc1 fc1; + struct { + unsigned long : 53; + unsigned long fc : 1; /* Format-Control */ + unsigned long : 4; + unsigned long i : 1; /* Region-Invalid Bit */ + unsigned long cr : 1; /* Common-Region Bit */ + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long : 2; + }; +}; + +struct segment_entry_fc0 { + unsigned long pto: 53;/* Page-Table Origin */ + unsigned long fc : 1; /* Format-Control */ + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long : 3; + unsigned long i : 1; /* Segment-Invalid Bit */ + unsigned long cs : 1; /* Common-Segment Bit */ + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long : 2; +}; + +struct segment_entry_fc1 { + unsigned long sfaa : 44; /* Segment-Frame Absolute Address */ + unsigned long : 3; + unsigned long av : 1; /* ACCF-Validity Control */ + unsigned long acc: 4; /* Access-Control Bits */ + unsigned long f : 1; /* Fetch-Protection Bit */ + unsigned long fc : 1; /* Format-Control */ + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long co : 1; /* Change-Recording Override */ + unsigned long : 2; + unsigned long i : 1; /* Segment-Invalid Bit */ + unsigned long cs : 1; /* Common-Segment Bit */ + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long : 2; +}; + +union segment_table_entry { + unsigned long val; + struct segment_entry_fc0 fc0; + struct segment_entry_fc1 fc1; + struct { + unsigned long : 53; + unsigned long fc : 1; /* Format-Control */ + unsigned long : 4; + unsigned long i : 1; /* Segment-Invalid Bit */ + unsigned long cs : 1; /* Common-Segment Bit */ + unsigned long tt : 2; /* Table-Type Bits */ + unsigned long : 2; + }; +}; + +enum { + TABLE_TYPE_SEGMENT = 0, + TABLE_TYPE_REGION3 = 1, + TABLE_TYPE_REGION2 = 2, + TABLE_TYPE_REGION1 = 3 +}; + +union page_table_entry { + unsigned long val; + struct { + unsigned long pfra : 52; /* Page-Frame Real Address */ + unsigned long z : 1; /* Zero Bit */ + unsigned long i : 1; /* Page-Invalid Bit */ + unsigned long p : 1; /* DAT-Protection Bit */ + unsigned long co : 1; /* Change-Recording Override */ + unsigned long : 8; + }; +}; + +/* + * vaddress union in order to easily decode a virtual address into its + * region first index, region second index etc. parts. + */ +union vaddress { + unsigned long addr; + struct { + unsigned long rfx : 11; + unsigned long rsx : 11; + unsigned long rtx : 11; + unsigned long sx : 11; + unsigned long px : 8; + unsigned long bx : 12; + }; + struct { + unsigned long rfx01 : 2; + unsigned long : 9; + unsigned long rsx01 : 2; + unsigned long : 9; + unsigned long rtx01 : 2; + unsigned long : 9; + unsigned long sx01 : 2; + unsigned long : 29; + }; +}; + +/* + * raddress union which will contain the result (real or absolute address) + * after a page table walk. The rfaa, sfaa and pfra members are used to + * simply assign them the value of a region, segment or page table entry. + */ +union raddress { + unsigned long addr; + unsigned long rfaa : 33; /* Region-Frame Absolute Address */ + unsigned long sfaa : 44; /* Segment-Frame Absolute Address */ + unsigned long pfra : 52; /* Page-Frame Real Address */ +}; + +static unsigned long get_vcpu_asce(struct kvm_vcpu *vcpu) +{ + switch (psw_bits(vcpu->arch.sie_block->gpsw).as) { + case PSW_AS_PRIMARY: + return vcpu->arch.sie_block->gcr[1]; + case PSW_AS_SECONDARY: + return vcpu->arch.sie_block->gcr[7]; + case PSW_AS_HOME: + return vcpu->arch.sie_block->gcr[13]; + } + return 0; +} + +static int deref_table(struct kvm *kvm, unsigned long gpa, unsigned long *val) +{ + return kvm_read_guest(kvm, gpa, val, sizeof(*val)); +} + +/** + * guest_translate - translate a guest virtual into a guest absolute address + * @vcpu: virtual cpu + * @gva: guest virtual address + * @gpa: points to where guest physical (absolute) address should be stored + * @write: indicates if access is a write access + * + * Translate a guest virtual address into a guest absolute address by means + * of dynamic address translation as specified by the architecuture. + * If the resulting absolute address is not available in the configuration + * an addressing exception is indicated and @gpa will not be changed. + * + * Returns: - zero on success; @gpa contains the resulting absolute address + * - a negative value if guest access failed due to e.g. broken + * guest mapping + * - a positve value if an access exception happened. In this case + * the returned value is the program interruption code as defined + * by the architecture + */ +static unsigned long guest_translate(struct kvm_vcpu *vcpu, unsigned long gva, + unsigned long *gpa, int write) +{ + union vaddress vaddr = {.addr = gva}; + union raddress raddr = {.addr = gva}; + union page_table_entry pte; + int dat_protection = 0; + union ctlreg0 ctlreg0; + unsigned long ptr; + int edat1, edat2; + union asce asce; + + ctlreg0.val = vcpu->arch.sie_block->gcr[0]; + edat1 = ctlreg0.edat && test_vfacility(8); + edat2 = edat1 && test_vfacility(78); + asce.val = get_vcpu_asce(vcpu); + if (asce.r) + goto real_address; + ptr = asce.origin * 4096; + switch (asce.dt) { + case ASCE_TYPE_REGION1: + if (vaddr.rfx01 > asce.tl) + return PGM_REGION_FIRST_TRANS; + ptr += vaddr.rfx * 8; + break; + case ASCE_TYPE_REGION2: + if (vaddr.rfx) + return PGM_ASCE_TYPE; + if (vaddr.rsx01 > asce.tl) + return PGM_REGION_SECOND_TRANS; + ptr += vaddr.rsx * 8; + break; + case ASCE_TYPE_REGION3: + if (vaddr.rfx || vaddr.rsx) + return PGM_ASCE_TYPE; + if (vaddr.rtx01 > asce.tl) + return PGM_REGION_THIRD_TRANS; + ptr += vaddr.rtx * 8; + break; + case ASCE_TYPE_SEGMENT: + if (vaddr.rfx || vaddr.rsx || vaddr.rtx) + return PGM_ASCE_TYPE; + if (vaddr.sx01 > asce.tl) + return PGM_SEGMENT_TRANSLATION; + ptr += vaddr.sx * 8; + break; + } + switch (asce.dt) { + case ASCE_TYPE_REGION1: { + union region1_table_entry rfte; + + if (kvm_is_error_gpa(vcpu->kvm, ptr)) + return PGM_ADDRESSING; + if (deref_table(vcpu->kvm, ptr, &rfte.val)) + return -EFAULT; + if (rfte.i) + return PGM_REGION_FIRST_TRANS; + if (rfte.tt != TABLE_TYPE_REGION1) + return PGM_TRANSLATION_SPEC; + if (vaddr.rsx01 < rfte.tf || vaddr.rsx01 > rfte.tl) + return PGM_REGION_SECOND_TRANS; + if (edat1) + dat_protection |= rfte.p; + ptr = rfte.rto * 4096 + vaddr.rsx * 8; + } + /* fallthrough */ + case ASCE_TYPE_REGION2: { + union region2_table_entry rste; + + if (kvm_is_error_gpa(vcpu->kvm, ptr)) + return PGM_ADDRESSING; + if (deref_table(vcpu->kvm, ptr, &rste.val)) + return -EFAULT; + if (rste.i) + return PGM_REGION_SECOND_TRANS; + if (rste.tt != TABLE_TYPE_REGION2) + return PGM_TRANSLATION_SPEC; + if (vaddr.rtx01 < rste.tf || vaddr.rtx01 > rste.tl) + return PGM_REGION_THIRD_TRANS; + if (edat1) + dat_protection |= rste.p; + ptr = rste.rto * 4096 + vaddr.rtx * 8; + } + /* fallthrough */ + case ASCE_TYPE_REGION3: { + union region3_table_entry rtte; + + if (kvm_is_error_gpa(vcpu->kvm, ptr)) + return PGM_ADDRESSING; + if (deref_table(vcpu->kvm, ptr, &rtte.val)) + return -EFAULT; + if (rtte.i) + return PGM_REGION_THIRD_TRANS; + if (rtte.tt != TABLE_TYPE_REGION3) + return PGM_TRANSLATION_SPEC; + if (rtte.cr && asce.p && edat2) + return PGM_TRANSLATION_SPEC; + if (rtte.fc && edat2) { + dat_protection |= rtte.fc1.p; + raddr.rfaa = rtte.fc1.rfaa; + goto absolute_address; + } + if (vaddr.sx01 < rtte.fc0.tf) + return PGM_SEGMENT_TRANSLATION; + if (vaddr.sx01 > rtte.fc0.tl) + return PGM_SEGMENT_TRANSLATION; + if (edat1) + dat_protection |= rtte.fc0.p; + ptr = rtte.fc0.sto * 4096 + vaddr.sx * 8; + } + /* fallthrough */ + case ASCE_TYPE_SEGMENT: { + union segment_table_entry ste; + + if (kvm_is_error_gpa(vcpu->kvm, ptr)) + return PGM_ADDRESSING; + if (deref_table(vcpu->kvm, ptr, &ste.val)) + return -EFAULT; + if (ste.i) + return PGM_SEGMENT_TRANSLATION; + if (ste.tt != TABLE_TYPE_SEGMENT) + return PGM_TRANSLATION_SPEC; + if (ste.cs && asce.p) + return PGM_TRANSLATION_SPEC; + if (ste.fc && edat1) { + dat_protection |= ste.fc1.p; + raddr.sfaa = ste.fc1.sfaa; + goto absolute_address; + } + dat_protection |= ste.fc0.p; + ptr = ste.fc0.pto * 2048 + vaddr.px * 8; + } + } + if (kvm_is_error_gpa(vcpu->kvm, ptr)) + return PGM_ADDRESSING; + if (deref_table(vcpu->kvm, ptr, &pte.val)) + return -EFAULT; + if (pte.i) + return PGM_PAGE_TRANSLATION; + if (pte.z) + return PGM_TRANSLATION_SPEC; + if (pte.co && !edat1) + return PGM_TRANSLATION_SPEC; + dat_protection |= pte.p; + raddr.pfra = pte.pfra; +real_address: + raddr.addr = kvm_s390_real_to_abs(vcpu, raddr.addr); +absolute_address: + if (write && dat_protection) + return PGM_PROTECTION; + if (kvm_is_error_gpa(vcpu->kvm, raddr.addr)) + return PGM_ADDRESSING; + *gpa = raddr.addr; + return 0; +} + +static inline int is_low_address(unsigned long ga) +{ + /* Check for address ranges 0..511 and 4096..4607 */ + return (ga & ~0x11fful) == 0; +} + +static int low_address_protection_enabled(struct kvm_vcpu *vcpu) +{ + union ctlreg0 ctlreg0 = {.val = vcpu->arch.sie_block->gcr[0]}; + psw_t *psw = &vcpu->arch.sie_block->gpsw; + union asce asce; + + if (!ctlreg0.lap) + return 0; + asce.val = get_vcpu_asce(vcpu); + if (psw_bits(*psw).t && asce.p) + return 0; + return 1; +} + +struct trans_exc_code_bits { + unsigned long addr : 52; /* Translation-exception Address */ + unsigned long fsi : 2; /* Access Exception Fetch/Store Indication */ + unsigned long : 7; + unsigned long b61 : 1; + unsigned long as : 2; /* ASCE Identifier */ +}; + +enum { + FSI_UNKNOWN = 0, /* Unknown wether fetch or store */ + FSI_STORE = 1, /* Exception was due to store operation */ + FSI_FETCH = 2 /* Exception was due to fetch operation */ +}; + +static int guest_page_range(struct kvm_vcpu *vcpu, unsigned long ga, + unsigned long *pages, unsigned long nr_pages, + int write) +{ + struct kvm_s390_pgm_info *pgm = &vcpu->arch.pgm; + psw_t *psw = &vcpu->arch.sie_block->gpsw; + struct trans_exc_code_bits *tec_bits; + int lap_enabled, rc; + + memset(pgm, 0, sizeof(*pgm)); + tec_bits = (struct trans_exc_code_bits *)&pgm->trans_exc_code; + tec_bits->fsi = write ? FSI_STORE : FSI_FETCH; + tec_bits->as = psw_bits(*psw).as; + lap_enabled = low_address_protection_enabled(vcpu); + while (nr_pages) { + ga = kvm_s390_logical_to_effective(vcpu, ga); + tec_bits->addr = ga >> PAGE_SHIFT; + if (write && lap_enabled && is_low_address(ga)) { + pgm->code = PGM_PROTECTION; + return pgm->code; + } + ga &= PAGE_MASK; + if (psw_bits(*psw).t) { + rc = guest_translate(vcpu, ga, pages, write); + if (rc < 0) + return rc; + if (rc == PGM_PROTECTION) + tec_bits->b61 = 1; + if (rc) + pgm->code = rc; + } else { + *pages = kvm_s390_real_to_abs(vcpu, ga); + if (kvm_is_error_gpa(vcpu->kvm, *pages)) + pgm->code = PGM_ADDRESSING; + } + if (pgm->code) + return pgm->code; + ga += PAGE_SIZE; + pages++; + nr_pages--; + } + return 0; +} + +int access_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, + unsigned long len, int write) +{ + psw_t *psw = &vcpu->arch.sie_block->gpsw; + unsigned long _len, nr_pages, gpa, idx; + unsigned long pages_array[2]; + unsigned long *pages; + int rc; + + if (!len) + return 0; + /* Access register mode is not supported yet. */ + if (psw_bits(*psw).t && psw_bits(*psw).as == PSW_AS_ACCREG) + return -EOPNOTSUPP; + nr_pages = (((ga & ~PAGE_MASK) + len - 1) >> PAGE_SHIFT) + 1; + pages = pages_array; + if (nr_pages > ARRAY_SIZE(pages_array)) + pages = vmalloc(nr_pages * sizeof(unsigned long)); + if (!pages) + return -ENOMEM; + rc = guest_page_range(vcpu, ga, pages, nr_pages, write); + for (idx = 0; idx < nr_pages && !rc; idx++) { + gpa = *(pages + idx) + (ga & ~PAGE_MASK); + _len = min(PAGE_SIZE - (gpa & ~PAGE_MASK), len); + if (write) + rc = kvm_write_guest(vcpu->kvm, gpa, data, _len); + else + rc = kvm_read_guest(vcpu->kvm, gpa, data, _len); + len -= _len; + ga += _len; + data += _len; + } + if (nr_pages > ARRAY_SIZE(pages_array)) + vfree(pages); + return rc; +} + +int access_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, + void *data, unsigned long len, int write) +{ + unsigned long _len, gpa; + int rc = 0; + + while (len && !rc) { + gpa = kvm_s390_real_to_abs(vcpu, gra); + _len = min(PAGE_SIZE - (gpa & ~PAGE_MASK), len); + if (write) + rc = write_guest_abs(vcpu, gpa, data, _len); + else + rc = read_guest_abs(vcpu, gpa, data, _len); + len -= _len; + gra += _len; + data += _len; + } + return rc; +} diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index 917aeaa04fff..21ee62cd948e 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -227,4 +227,174 @@ int read_guest_lc(struct kvm_vcpu *vcpu, unsigned long gra, void *data, return kvm_read_guest(vcpu->kvm, gpa, data, len); } + +int access_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, + unsigned long len, int write); + +int access_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, + void *data, unsigned long len, int write); + +/** + * write_guest - copy data from kernel space to guest space + * @vcpu: virtual cpu + * @ga: guest address + * @data: source address in kernel space + * @len: number of bytes to copy + * + * Copy @len bytes from @data (kernel space) to @ga (guest address). + * In order to copy data to guest space the PSW of the vcpu is inspected: + * If DAT is off data will be copied to guest real or absolute memory. + * If DAT is on data will be copied to the address space as specified by + * the address space bits of the PSW: + * Primary, secondory or home space (access register mode is currently not + * implemented). + * The addressing mode of the PSW is also inspected, so that address wrap + * around is taken into account for 24-, 31- and 64-bit addressing mode, + * if the to be copied data crosses page boundaries in guest address space. + * In addition also low address and DAT protection are inspected before + * copying any data (key protection is currently not implemented). + * + * This function modifies the 'struct kvm_s390_pgm_info pgm' member of @vcpu. + * In case of an access exception (e.g. protection exception) pgm will contain + * all data necessary so that a subsequent call to 'kvm_s390_inject_prog_vcpu()' + * will inject a correct exception into the guest. + * If no access exception happened, the contents of pgm are undefined when + * this function returns. + * + * Returns: - zero on success + * - a negative value if e.g. the guest mapping is broken or in + * case of out-of-memory. In this case the contents of pgm are + * undefined. Also parts of @data may have been copied to guest + * space. + * - a positive value if an access exception happened. In this case + * the returned value is the program interruption code and the + * contents of pgm may be used to inject an exception into the + * guest. No data has been copied to guest space. + * + * Note: in case an access exception is recognized no data has been copied to + * guest space (this is also true, if the to be copied data would cross + * one or more page boundaries in guest space). + * Therefore this function may be used for nullifying and suppressing + * instruction emulation. + * It may also be used for terminating instructions, if it is undefined + * if data has been changed in guest space in case of an exception. + */ +static inline __must_check +int write_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, + unsigned long len) +{ + return access_guest(vcpu, ga, data, len, 1); +} + +/** + * read_guest - copy data from guest space to kernel space + * @vcpu: virtual cpu + * @ga: guest address + * @data: destination address in kernel space + * @len: number of bytes to copy + * + * Copy @len bytes from @ga (guest address) to @data (kernel space). + * + * The behaviour of read_guest is identical to write_guest, except that + * data will be copied from guest space to kernel space. + */ +static inline __must_check +int read_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, + unsigned long len) +{ + return access_guest(vcpu, ga, data, len, 0); +} + +/** + * write_guest_abs - copy data from kernel space to guest space absolute + * @vcpu: virtual cpu + * @gpa: guest physical (absolute) address + * @data: source address in kernel space + * @len: number of bytes to copy + * + * Copy @len bytes from @data (kernel space) to @gpa (guest absolute address). + * It is up to the caller to ensure that the entire guest memory range is + * valid memory before calling this function. + * Guest low address and key protection are not checked. + * + * Returns zero on success or -EFAULT on error. + * + * If an error occurs data may have been copied partially to guest memory. + */ +static inline __must_check +int write_guest_abs(struct kvm_vcpu *vcpu, unsigned long gpa, void *data, + unsigned long len) +{ + return kvm_write_guest(vcpu->kvm, gpa, data, len); +} + +/** + * read_guest_abs - copy data from guest space absolute to kernel space + * @vcpu: virtual cpu + * @gpa: guest physical (absolute) address + * @data: destination address in kernel space + * @len: number of bytes to copy + * + * Copy @len bytes from @gpa (guest absolute address) to @data (kernel space). + * It is up to the caller to ensure that the entire guest memory range is + * valid memory before calling this function. + * Guest key protection is not checked. + * + * Returns zero on success or -EFAULT on error. + * + * If an error occurs data may have been copied partially to kernel space. + */ +static inline __must_check +int read_guest_abs(struct kvm_vcpu *vcpu, unsigned long gpa, void *data, + unsigned long len) +{ + return kvm_read_guest(vcpu->kvm, gpa, data, len); +} + +/** + * write_guest_real - copy data from kernel space to guest space real + * @vcpu: virtual cpu + * @gra: guest real address + * @data: source address in kernel space + * @len: number of bytes to copy + * + * Copy @len bytes from @data (kernel space) to @gra (guest real address). + * It is up to the caller to ensure that the entire guest memory range is + * valid memory before calling this function. + * Guest low address and key protection are not checked. + * + * Returns zero on success or -EFAULT on error. + * + * If an error occurs data may have been copied partially to guest memory. + */ +static inline __must_check +int write_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, void *data, + unsigned long len) +{ + return access_guest_real(vcpu, gra, data, len, 1); +} + +/** + * read_guest_real - copy data from guest space real to kernel space + * @vcpu: virtual cpu + * @gra: guest real address + * @data: destination address in kernel space + * @len: number of bytes to copy + * + * Copy @len bytes from @gra (guest real address) to @data (kernel space). + * It is up to the caller to ensure that the entire guest memory range is + * valid memory before calling this function. + * Guest key protection is not checked. + * + * Returns zero on success or -EFAULT on error. + * + * If an error occurs data may have been copied partially to kernel space. + */ +static inline __must_check +int read_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, void *data, + unsigned long len) +{ + return access_guest_real(vcpu, gra, data, len, 0); +} + #endif /* __KVM_S390_GACCESS_H */ -- cgit v1.2.3 From 217a440683b51463f53e397cfdda27d7e92bf275 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 30 Dec 2013 12:54:14 +0100 Subject: KVM: s390/sclp: correctly set eca siif bit Check if siif is available before setting. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/sclp.h | 7 ++++++- arch/s390/kvm/kvm-s390.c | 4 +++- drivers/s390/char/sclp_early.c | 22 +++++++++++++++++++++- 3 files changed, 30 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/sclp.h b/arch/s390/include/asm/sclp.h index 2f5e9932b4de..943d43451116 100644 --- a/arch/s390/include/asm/sclp.h +++ b/arch/s390/include/asm/sclp.h @@ -28,7 +28,11 @@ struct sclp_ipl_info { struct sclp_cpu_entry { u8 address; - u8 reserved0[13]; + u8 reserved0[2]; + u8 : 3; + u8 siif : 1; + u8 : 4; + u8 reserved2[10]; u8 type; u8 reserved1; } __attribute__((packed)); @@ -61,5 +65,6 @@ int sclp_pci_deconfigure(u32 fid); int memcpy_hsa(void *dest, unsigned long src, size_t count, int mode); unsigned long sclp_get_hsa_size(void); void sclp_early_detect(void); +int sclp_has_siif(void); #endif /* _ASM_S390_SCLP_H */ diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 4b1df682e5c3..927ba7361da9 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -625,7 +625,9 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) vcpu->arch.sie_block->ecb |= 0x10; vcpu->arch.sie_block->ecb2 = 8; - vcpu->arch.sie_block->eca = 0xC1002001U; + vcpu->arch.sie_block->eca = 0xC1002000U; + if (sclp_has_siif()) + vcpu->arch.sie_block->eca |= 1; vcpu->arch.sie_block->fac = (int) (long) vfacilities; vcpu->arch.sie_block->ictl |= ICTL_ISKE | ICTL_SSKE | ICTL_RRBE; if (kvm_s390_cmma_enabled(vcpu->kvm)) { diff --git a/drivers/s390/char/sclp_early.c b/drivers/s390/char/sclp_early.c index 14196ea0fdf3..b57fe0efb422 100644 --- a/drivers/s390/char/sclp_early.c +++ b/drivers/s390/char/sclp_early.c @@ -22,7 +22,8 @@ struct read_info_sccb { u8 rnsize; /* 10 */ u8 _reserved0[16 - 11]; /* 11-15 */ u16 ncpurl; /* 16-17 */ - u8 _reserved7[24 - 18]; /* 18-23 */ + u16 cpuoff; /* 18-19 */ + u8 _reserved7[24 - 20]; /* 20-23 */ u8 loadparm[8]; /* 24-31 */ u8 _reserved1[48 - 32]; /* 32-47 */ u64 facilities; /* 48-55 */ @@ -45,6 +46,7 @@ static unsigned int sclp_con_has_linemode __initdata; static unsigned long sclp_hsa_size; static unsigned int sclp_max_cpu; static struct sclp_ipl_info sclp_ipl_info; +static unsigned char sclp_siif; u64 sclp_facilities; u8 sclp_fac84; @@ -96,6 +98,9 @@ static int __init sclp_read_info_early(struct read_info_sccb *sccb) static void __init sclp_facilities_detect(struct read_info_sccb *sccb) { + struct sclp_cpu_entry *cpue; + u16 boot_cpu_address, cpu; + if (sclp_read_info_early(sccb)) return; @@ -116,6 +121,15 @@ static void __init sclp_facilities_detect(struct read_info_sccb *sccb) sclp_max_cpu = sccb->hcpua + 1; } + boot_cpu_address = stap(); + cpue = (void *)sccb + sccb->cpuoff; + for (cpu = 0; cpu < sccb->ncpurl; cpue++, cpu++) { + if (boot_cpu_address != cpue->address) + continue; + sclp_siif = cpue->siif; + break; + } + /* Save IPL information */ sclp_ipl_info.is_valid = 1; if (sccb->flags & 0x2) @@ -148,6 +162,12 @@ unsigned int sclp_get_max_cpu(void) return sclp_max_cpu; } +int sclp_has_siif(void) +{ + return sclp_siif; +} +EXPORT_SYMBOL(sclp_has_siif); + /* * This function will be called after sclp_facilities_detect(), which gets * called from early.c code. The sclp_facilities_detect() function retrieves -- cgit v1.2.3 From 8a242234b4bfed37f7fbd9b0b16f8088f31ca140 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Fri, 10 Jan 2014 14:33:28 +0100 Subject: KVM: s390: make use of ipte lock Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 12 ++++- arch/s390/kvm/gaccess.c | 109 +++++++++++++++++++++++++++++++++++++++ arch/s390/kvm/gaccess.h | 2 + arch/s390/kvm/kvm-s390.c | 2 + arch/s390/kvm/priv.c | 18 +++++++ 5 files changed, 142 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index c290d443d2c1..f1ed7bdba733 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -39,9 +39,17 @@ struct sca_entry { __u64 reserved2[2]; } __attribute__((packed)); +union ipte_control { + unsigned long val; + struct { + unsigned long k : 1; + unsigned long kh : 31; + unsigned long kg : 32; + }; +}; struct sca_block { - __u64 ipte_control; + union ipte_control ipte_control; __u64 reserved[5]; __u64 mcn; __u64 reserved2; @@ -167,6 +175,7 @@ struct kvm_vcpu_stat { u32 instruction_stpx; u32 instruction_stap; u32 instruction_storage_key; + u32 instruction_ipte_interlock; u32 instruction_stsch; u32 instruction_chsc; u32 instruction_stsi; @@ -336,6 +345,7 @@ struct kvm_arch{ int use_irqchip; int use_cmma; struct s390_io_adapter *adapters[MAX_S390_IO_ADAPTERS]; + wait_queue_head_t ipte_wq; }; #define KVM_HVA_ERR_BAD (-1UL) diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c index 916e1ee1f8c9..691fdb776c90 100644 --- a/arch/s390/kvm/gaccess.c +++ b/arch/s390/kvm/gaccess.c @@ -207,6 +207,107 @@ union raddress { unsigned long pfra : 52; /* Page-Frame Real Address */ }; +static int ipte_lock_count; +static DEFINE_MUTEX(ipte_mutex); + +int ipte_lock_held(struct kvm_vcpu *vcpu) +{ + union ipte_control *ic = &vcpu->kvm->arch.sca->ipte_control; + + if (vcpu->arch.sie_block->eca & 1) + return ic->kh != 0; + return ipte_lock_count != 0; +} + +static void ipte_lock_simple(struct kvm_vcpu *vcpu) +{ + union ipte_control old, new, *ic; + + mutex_lock(&ipte_mutex); + ipte_lock_count++; + if (ipte_lock_count > 1) + goto out; + ic = &vcpu->kvm->arch.sca->ipte_control; + do { + old = ACCESS_ONCE(*ic); + while (old.k) { + cond_resched(); + old = ACCESS_ONCE(*ic); + } + new = old; + new.k = 1; + } while (cmpxchg(&ic->val, old.val, new.val) != old.val); +out: + mutex_unlock(&ipte_mutex); +} + +static void ipte_unlock_simple(struct kvm_vcpu *vcpu) +{ + union ipte_control old, new, *ic; + + mutex_lock(&ipte_mutex); + ipte_lock_count--; + if (ipte_lock_count) + goto out; + ic = &vcpu->kvm->arch.sca->ipte_control; + do { + new = old = ACCESS_ONCE(*ic); + new.k = 0; + } while (cmpxchg(&ic->val, old.val, new.val) != old.val); + if (!ipte_lock_count) + wake_up(&vcpu->kvm->arch.ipte_wq); +out: + mutex_unlock(&ipte_mutex); +} + +static void ipte_lock_siif(struct kvm_vcpu *vcpu) +{ + union ipte_control old, new, *ic; + + ic = &vcpu->kvm->arch.sca->ipte_control; + do { + old = ACCESS_ONCE(*ic); + while (old.kg) { + cond_resched(); + old = ACCESS_ONCE(*ic); + } + new = old; + new.k = 1; + new.kh++; + } while (cmpxchg(&ic->val, old.val, new.val) != old.val); +} + +static void ipte_unlock_siif(struct kvm_vcpu *vcpu) +{ + union ipte_control old, new, *ic; + + ic = &vcpu->kvm->arch.sca->ipte_control; + do { + new = old = ACCESS_ONCE(*ic); + new.kh--; + if (!new.kh) + new.k = 0; + } while (cmpxchg(&ic->val, old.val, new.val) != old.val); + if (!new.kh) + wake_up(&vcpu->kvm->arch.ipte_wq); +} + +static void ipte_lock(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.sie_block->eca & 1) + ipte_lock_siif(vcpu); + else + ipte_lock_simple(vcpu); +} + +static void ipte_unlock(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.sie_block->eca & 1) + ipte_unlock_siif(vcpu); + else + ipte_unlock_simple(vcpu); +} + static unsigned long get_vcpu_asce(struct kvm_vcpu *vcpu) { switch (psw_bits(vcpu->arch.sie_block->gpsw).as) { @@ -485,6 +586,8 @@ int access_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, unsigned long _len, nr_pages, gpa, idx; unsigned long pages_array[2]; unsigned long *pages; + int need_ipte_lock; + union asce asce; int rc; if (!len) @@ -498,6 +601,10 @@ int access_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, pages = vmalloc(nr_pages * sizeof(unsigned long)); if (!pages) return -ENOMEM; + asce.val = get_vcpu_asce(vcpu); + need_ipte_lock = psw_bits(*psw).t && !asce.r; + if (need_ipte_lock) + ipte_lock(vcpu); rc = guest_page_range(vcpu, ga, pages, nr_pages, write); for (idx = 0; idx < nr_pages && !rc; idx++) { gpa = *(pages + idx) + (ga & ~PAGE_MASK); @@ -510,6 +617,8 @@ int access_guest(struct kvm_vcpu *vcpu, unsigned long ga, void *data, ga += _len; data += _len; } + if (need_ipte_lock) + ipte_unlock(vcpu); if (nr_pages > ARRAY_SIZE(pages_array)) vfree(pages); return rc; diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index 21ee62cd948e..f46e764c5b43 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -397,4 +397,6 @@ int read_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, void *data, return access_guest_real(vcpu, gra, data, len, 0); } +int ipte_lock_held(struct kvm_vcpu *vcpu); + #endif /* __KVM_S390_GACCESS_H */ diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 927ba7361da9..e1dfe2461d4b 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -67,6 +67,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { "instruction_stpx", VCPU_STAT(instruction_stpx) }, { "instruction_stap", VCPU_STAT(instruction_stap) }, { "instruction_storage_key", VCPU_STAT(instruction_storage_key) }, + { "instruction_ipte_interlock", VCPU_STAT(instruction_ipte_interlock) }, { "instruction_stsch", VCPU_STAT(instruction_stsch) }, { "instruction_chsc", VCPU_STAT(instruction_chsc) }, { "instruction_essa", VCPU_STAT(instruction_essa) }, @@ -437,6 +438,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) spin_lock_init(&kvm->arch.float_int.lock); INIT_LIST_HEAD(&kvm->arch.float_int.list); + init_waitqueue_head(&kvm->arch.ipte_wq); debug_register_view(kvm->arch.dbf, &debug_sprintf_view); VM_EVENT(kvm, 3, "%s", "vm created"); diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 9a04d74c5fb4..4792f1df921a 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -173,6 +173,19 @@ static int handle_skey(struct kvm_vcpu *vcpu) return 0; } +static int handle_ipte_interlock(struct kvm_vcpu *vcpu) +{ + psw_t *psw = &vcpu->arch.sie_block->gpsw; + + vcpu->stat.instruction_ipte_interlock++; + if (psw_bits(*psw).p) + return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); + wait_event(vcpu->kvm->arch.ipte_wq, !ipte_lock_held(vcpu)); + psw->addr = __rewind_psw(*psw, 4); + VCPU_EVENT(vcpu, 4, "%s", "retrying ipte interlock operation"); + return 0; +} + static int handle_test_block(struct kvm_vcpu *vcpu) { unsigned long hva; @@ -509,6 +522,7 @@ static const intercept_handler_t b2_handlers[256] = { [0x10] = handle_set_prefix, [0x11] = handle_store_prefix, [0x12] = handle_store_cpu_address, + [0x21] = handle_ipte_interlock, [0x29] = handle_skey, [0x2a] = handle_skey, [0x2b] = handle_skey, @@ -526,6 +540,7 @@ static const intercept_handler_t b2_handlers[256] = { [0x3a] = handle_io_inst, [0x3b] = handle_io_inst, [0x3c] = handle_io_inst, + [0x50] = handle_ipte_interlock, [0x5f] = handle_io_inst, [0x74] = handle_io_inst, [0x76] = handle_io_inst, @@ -686,7 +701,10 @@ static int handle_essa(struct kvm_vcpu *vcpu) } static const intercept_handler_t b9_handlers[256] = { + [0x8a] = handle_ipte_interlock, [0x8d] = handle_epsw, + [0x8e] = handle_ipte_interlock, + [0x8f] = handle_ipte_interlock, [0xab] = handle_essa, [0xaf] = handle_pfmf, }; -- cgit v1.2.3 From 7988276df75e8314e2dbbf75fb419f9c7a8e82f4 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 2 Jan 2014 10:59:41 +0100 Subject: KVM: s390: convert __do_deliver_interrupt() Convert __do_deliver_interrupt() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/interrupt.c | 82 +++++++++++++++++++++++++---------------------- 1 file changed, 44 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index a44c68990cf4..cb782e30ee4f 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -213,13 +213,14 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, vcpu->stat.deliver_service_signal++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, inti->ext.ext_params, 0); - rc = put_guest(vcpu, 0x2401, (u16 __user *)__LC_EXT_INT_CODE); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, + rc = put_guest_lc(vcpu, 0x2401, (u16 *)__LC_EXT_INT_CODE); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); - rc |= put_guest(vcpu, inti->ext.ext_params, - (u32 __user *)__LC_EXT_PARAMS); + rc |= put_guest_lc(vcpu, inti->ext.ext_params, + (u32 *)__LC_EXT_PARAMS); break; case KVM_S390_INT_PFAULT_INIT: trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0, @@ -236,14 +237,15 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, case KVM_S390_INT_PFAULT_DONE: trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0, inti->ext.ext_params2); - rc = put_guest(vcpu, 0x2603, (u16 __user *) __LC_EXT_INT_CODE); - rc |= put_guest(vcpu, 0x0680, (u16 __user *) __LC_EXT_CPU_ADDR); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, + rc = put_guest_lc(vcpu, 0x2603, (u16 *)__LC_EXT_INT_CODE); + rc |= put_guest_lc(vcpu, 0x0680, (u16 *)__LC_EXT_CPU_ADDR); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); - rc |= put_guest(vcpu, inti->ext.ext_params2, - (u64 __user *) __LC_EXT_PARAMS2); + rc |= put_guest_lc(vcpu, inti->ext.ext_params2, + (u64 *)__LC_EXT_PARAMS2); break; case KVM_S390_INT_VIRTIO: VCPU_EVENT(vcpu, 4, "interrupt: virtio parm:%x,parm64:%llx", @@ -252,16 +254,17 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, inti->ext.ext_params, inti->ext.ext_params2); - rc = put_guest(vcpu, 0x2603, (u16 __user *)__LC_EXT_INT_CODE); - rc |= put_guest(vcpu, 0x0d00, (u16 __user *)__LC_EXT_CPU_ADDR); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, + rc = put_guest_lc(vcpu, 0x2603, (u16 *)__LC_EXT_INT_CODE); + rc |= put_guest_lc(vcpu, 0x0d00, (u16 *)__LC_EXT_CPU_ADDR); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); - rc |= put_guest(vcpu, inti->ext.ext_params, - (u32 __user *)__LC_EXT_PARAMS); - rc |= put_guest(vcpu, inti->ext.ext_params2, - (u64 __user *)__LC_EXT_PARAMS2); + rc |= put_guest_lc(vcpu, inti->ext.ext_params, + (u32 *)__LC_EXT_PARAMS); + rc |= put_guest_lc(vcpu, inti->ext.ext_params2, + (u64 *)__LC_EXT_PARAMS2); break; case KVM_S390_SIGP_STOP: VCPU_EVENT(vcpu, 4, "%s", "interrupt: cpu stop"); @@ -317,11 +320,12 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, inti->mchk.mcic); rc = kvm_s390_vcpu_store_status(vcpu, KVM_S390_STORE_STATUS_PREFIXED); - rc |= put_guest(vcpu, inti->mchk.mcic, (u64 __user *) __LC_MCCK_CODE); - rc |= copy_to_guest(vcpu, __LC_MCK_OLD_PSW, + rc |= put_guest_lc(vcpu, inti->mchk.mcic, (u64 *)__LC_MCCK_CODE); + rc |= write_guest_lc(vcpu, __LC_MCK_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_MCK_NEW_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_MCK_NEW_PSW, sizeof(psw_t)); break; case KVM_S390_INT_IO_MIN...KVM_S390_INT_IO_MAX: @@ -334,18 +338,20 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, vcpu->stat.deliver_io_int++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, param0, param1); - rc = put_guest(vcpu, inti->io.subchannel_id, - (u16 __user *) __LC_SUBCHANNEL_ID); - rc |= put_guest(vcpu, inti->io.subchannel_nr, - (u16 __user *) __LC_SUBCHANNEL_NR); - rc |= put_guest(vcpu, inti->io.io_int_parm, - (u32 __user *) __LC_IO_INT_PARM); - rc |= put_guest(vcpu, inti->io.io_int_word, - (u32 __user *) __LC_IO_INT_WORD); - rc |= copy_to_guest(vcpu, __LC_IO_OLD_PSW, - &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_IO_NEW_PSW, sizeof(psw_t)); + rc = put_guest_lc(vcpu, inti->io.subchannel_id, + (u16 *)__LC_SUBCHANNEL_ID); + rc |= put_guest_lc(vcpu, inti->io.subchannel_nr, + (u16 *)__LC_SUBCHANNEL_NR); + rc |= put_guest_lc(vcpu, inti->io.io_int_parm, + (u32 *)__LC_IO_INT_PARM); + rc |= put_guest_lc(vcpu, inti->io.io_int_word, + (u32 *)__LC_IO_INT_WORD); + rc |= write_guest_lc(vcpu, __LC_IO_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_IO_NEW_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); break; } default: -- cgit v1.2.3 From 1a03b764229a5b368fd728fe25485b2510a4eeac Mon Sep 17 00:00:00 2001 From: Jens Freimann Date: Wed, 12 Feb 2014 14:05:38 +0100 Subject: KVM: s390: convert local irqs in __do_deliver_interrupt() Convert local irqs in __do_deliver_interrupt() to new guest access functions. Signed-off-by: Jens Freimann Signed-off-by: Christian Borntraeger --- arch/s390/kvm/interrupt.c | 81 +++++++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index cb782e30ee4f..a1403ba75bfc 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -186,26 +186,28 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, vcpu->stat.deliver_emergency_signal++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, inti->emerg.code, 0); - rc = put_guest(vcpu, 0x1201, (u16 __user *)__LC_EXT_INT_CODE); - rc |= put_guest(vcpu, inti->emerg.code, - (u16 __user *)__LC_EXT_CPU_ADDR); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, + rc = put_guest_lc(vcpu, 0x1201, (u16 *)__LC_EXT_INT_CODE); + rc |= put_guest_lc(vcpu, inti->emerg.code, + (u16 *)__LC_EXT_CPU_ADDR); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); break; case KVM_S390_INT_EXTERNAL_CALL: VCPU_EVENT(vcpu, 4, "%s", "interrupt: sigp ext call"); vcpu->stat.deliver_external_call++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, inti->extcall.code, 0); - rc = put_guest(vcpu, 0x1202, (u16 __user *)__LC_EXT_INT_CODE); - rc |= put_guest(vcpu, inti->extcall.code, - (u16 __user *)__LC_EXT_CPU_ADDR); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, - &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); + rc = put_guest_lc(vcpu, 0x1202, (u16 *)__LC_EXT_INT_CODE); + rc |= put_guest_lc(vcpu, inti->extcall.code, + (u16 *)__LC_EXT_CPU_ADDR); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); break; case KVM_S390_INT_SERVICE: VCPU_EVENT(vcpu, 4, "interrupt: sclp parm:%x", @@ -225,14 +227,14 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, case KVM_S390_INT_PFAULT_INIT: trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0, inti->ext.ext_params2); - rc = put_guest(vcpu, 0x2603, (u16 __user *) __LC_EXT_INT_CODE); - rc |= put_guest(vcpu, 0x0600, (u16 __user *) __LC_EXT_CPU_ADDR); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, + rc = put_guest_lc(vcpu, 0x2603, (u16 *) __LC_EXT_INT_CODE); + rc |= put_guest_lc(vcpu, 0x0600, (u16 *) __LC_EXT_CPU_ADDR); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); - rc |= put_guest(vcpu, inti->ext.ext_params2, - (u64 __user *) __LC_EXT_PARAMS2); + rc |= put_guest_lc(vcpu, inti->ext.ext_params2, + (u64 *) __LC_EXT_PARAMS2); break; case KVM_S390_INT_PFAULT_DONE: trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0, @@ -288,12 +290,12 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, vcpu->stat.deliver_restart_signal++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, 0, 0); - rc = copy_to_guest(vcpu, - offsetof(struct _lowcore, restart_old_psw), - &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - offsetof(struct _lowcore, restart_psw), - sizeof(psw_t)); + rc = write_guest_lc(vcpu, + offsetof(struct _lowcore, restart_old_psw), + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= read_guest_lc(vcpu, offsetof(struct _lowcore, restart_psw), + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); break; case KVM_S390_PROGRAM_INT: @@ -303,13 +305,15 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, vcpu->stat.deliver_program_int++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, inti->pgm.code, 0); - rc = put_guest(vcpu, inti->pgm.code, (u16 __user *)__LC_PGM_INT_CODE); - rc |= put_guest(vcpu, table[vcpu->arch.sie_block->ipa >> 14], - (u16 __user *)__LC_PGM_ILC); - rc |= copy_to_guest(vcpu, __LC_PGM_OLD_PSW, - &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_PGM_NEW_PSW, sizeof(psw_t)); + rc = put_guest_lc(vcpu, inti->pgm.code, + (u16 __user *)__LC_PGM_INT_CODE); + rc |= put_guest_lc(vcpu, table[vcpu->arch.sie_block->ipa >> 14], + (u16 __user *)__LC_PGM_ILC); + rc |= write_guest_lc(vcpu, __LC_PGM_OLD_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_PGM_NEW_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); break; case KVM_S390_MCHK: @@ -372,11 +376,12 @@ static int __try_deliver_ckc_interrupt(struct kvm_vcpu *vcpu) return 0; if (!(vcpu->arch.sie_block->gcr[0] & 0x800ul)) return 0; - rc = put_guest(vcpu, 0x1004, (u16 __user *)__LC_EXT_INT_CODE); - rc |= copy_to_guest(vcpu, __LC_EXT_OLD_PSW, - &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= copy_from_guest(vcpu, &vcpu->arch.sie_block->gpsw, - __LC_EXT_NEW_PSW, sizeof(psw_t)); + rc = put_guest_lc(vcpu, 0x1004, (u16 __user *)__LC_EXT_INT_CODE); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); if (rc) { printk("kvm: The guest lowcore is not mapped during interrupt " "delivery, killing userspace\n"); -- cgit v1.2.3 From 0f9701c6c2b39588971f4634dfcb10199941ce7a Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:56:41 +0100 Subject: KVM: s390: convert handle_stfl() Convert handle_stfl() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 4792f1df921a..7066fc5bf48a 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -318,10 +318,10 @@ static int handle_stfl(struct kvm_vcpu *vcpu) if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); - rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list), - vfacilities, 4); + rc = write_guest_lc(vcpu, offsetof(struct _lowcore, stfl_fac_list), + vfacilities, 4); if (rc) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + return rc; VCPU_EVENT(vcpu, 5, "store facility list value %x", *(unsigned int *) vfacilities); trace_kvm_s390_handle_stfl(vcpu, *(unsigned int *) vfacilities); -- cgit v1.2.3 From 81480cc19c56efb573c63d89c46797d34fe58f27 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:36:07 +0100 Subject: KVM: s390: convert pfault code Convert pfault code to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Dominik Dingel Signed-off-by: Christian Borntraeger --- arch/s390/kvm/diag.c | 9 ++++----- arch/s390/kvm/kvm-s390.c | 5 +++-- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index ff768f1dd337..5521ace8b60d 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -64,12 +64,12 @@ static int __diag_page_ref_service(struct kvm_vcpu *vcpu) int rc; u16 rx = (vcpu->arch.sie_block->ipa & 0xf0) >> 4; u16 ry = (vcpu->arch.sie_block->ipa & 0x0f); - unsigned long hva_token = KVM_HVA_ERR_BAD; if (vcpu->run->s.regs.gprs[rx] & 7) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - if (copy_from_guest(vcpu, &parm, vcpu->run->s.regs.gprs[rx], sizeof(parm))) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = read_guest(vcpu, vcpu->run->s.regs.gprs[rx], &parm, sizeof(parm)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); if (parm.parm_version != 2 || parm.parm_len < 5 || parm.code != 0x258) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); @@ -89,8 +89,7 @@ static int __diag_page_ref_service(struct kvm_vcpu *vcpu) parm.token_addr & 7 || parm.zarch != 0x8000000000000000ULL) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - hva_token = gfn_to_hva(vcpu->kvm, gpa_to_gfn(parm.token_addr)); - if (kvm_is_error_hva(hva_token)) + if (kvm_is_error_gpa(vcpu->kvm, parm.token_addr)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); vcpu->arch.pfault_token = parm.token_addr; diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index e1dfe2461d4b..6cee19c7ad74 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -1058,8 +1058,9 @@ static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu) if (!vcpu->arch.gmap->pfault_enabled) return 0; - hva = gmap_fault(current->thread.gmap_addr, vcpu->arch.gmap); - if (copy_from_guest(vcpu, &arch.pfault_token, vcpu->arch.pfault_token, 8)) + hva = gfn_to_hva(vcpu->kvm, gpa_to_gfn(current->thread.gmap_addr)); + hva += current->thread.gmap_addr & ~PAGE_MASK; + if (read_guest_real(vcpu, vcpu->arch.pfault_token, &arch.pfault_token, 8)) return 0; rc = kvm_setup_async_pf(vcpu, current->thread.gmap_addr, hva, &arch); -- cgit v1.2.3 From 0040e7d20fe467a4bcdb8a6c284631b80efffa8b Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:37:47 +0100 Subject: KVM: s390: convert handle_prog() Convert handle_prog() to new guest access functions. Also make the code a bit more readable and look at the return code of write_guest_lc() which was missing before. Signed-off-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/kvm/intercept.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index eeb1ac7d8fa4..a8d8da84005b 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -111,18 +111,22 @@ static int handle_instruction(struct kvm_vcpu *vcpu) static int handle_prog(struct kvm_vcpu *vcpu) { + struct kvm_s390_itdb *itdb; + int rc; + vcpu->stat.exit_program_interruption++; /* Restore ITDB to Program-Interruption TDB in guest memory */ - if (IS_TE_ENABLED(vcpu) && - !(current->thread.per_flags & PER_FLAG_NO_TE) && - IS_ITDB_VALID(vcpu)) { - copy_to_guest(vcpu, TDB_ADDR, vcpu->arch.sie_block->itdba, - sizeof(struct kvm_s390_itdb)); - memset((void *) vcpu->arch.sie_block->itdba, 0, - sizeof(struct kvm_s390_itdb)); - } - + if (!IS_TE_ENABLED(vcpu) || !IS_ITDB_VALID(vcpu)) + goto skip_itdb; + if (current->thread.per_flags & PER_FLAG_NO_TE) + goto skip_itdb; + itdb = (struct kvm_s390_itdb *)vcpu->arch.sie_block->itdba; + rc = write_guest_lc(vcpu, TDB_ADDR, itdb, sizeof(*itdb)); + if (rc) + return rc; + memset(itdb, 0, sizeof(*itdb)); +skip_itdb: trace_kvm_s390_intercept_prog(vcpu, vcpu->arch.sie_block->iprcc); return kvm_s390_inject_program_int(vcpu, vcpu->arch.sie_block->iprcc); } -- cgit v1.2.3 From d0bce6054a1759f1b2c86bf553801c77dcaca745 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:45:58 +0100 Subject: KVM: s390: convert kvm_s390_store_status_unloaded() Convert kvm_s390_store_status_unloaded() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/kvm-s390.c | 95 ++++++++++++++++-------------------------------- 1 file changed, 31 insertions(+), 64 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 6cee19c7ad74..ae7c1265fcc1 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -1249,83 +1249,50 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) return rc; } -static int __guestcopy(struct kvm_vcpu *vcpu, u64 guestdest, void *from, - unsigned long n, int prefix) -{ - if (prefix) - return copy_to_guest(vcpu, guestdest, from, n); - else - return copy_to_guest_absolute(vcpu, guestdest, from, n); -} - /* * store status at address * we use have two special cases: * KVM_S390_STORE_STATUS_NOADDR: -> 0x1200 on 64 bit * KVM_S390_STORE_STATUS_PREFIXED: -> prefix */ -int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr) +int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long gpa) { unsigned char archmode = 1; - int prefix; u64 clkcomp; + int rc; - if (addr == KVM_S390_STORE_STATUS_NOADDR) { - if (copy_to_guest_absolute(vcpu, 163ul, &archmode, 1)) + if (gpa == KVM_S390_STORE_STATUS_NOADDR) { + if (write_guest_abs(vcpu, 163, &archmode, 1)) return -EFAULT; - addr = SAVE_AREA_BASE; - prefix = 0; - } else if (addr == KVM_S390_STORE_STATUS_PREFIXED) { - if (copy_to_guest(vcpu, 163ul, &archmode, 1)) + gpa = SAVE_AREA_BASE; + } else if (gpa == KVM_S390_STORE_STATUS_PREFIXED) { + if (write_guest_real(vcpu, 163, &archmode, 1)) return -EFAULT; - addr = SAVE_AREA_BASE; - prefix = 1; - } else - prefix = 0; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, fp_regs), - vcpu->arch.guest_fpregs.fprs, 128, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, gp_regs), - vcpu->run->s.regs.gprs, 128, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, psw), - &vcpu->arch.sie_block->gpsw, 16, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, pref_reg), - &vcpu->arch.sie_block->prefix, 4, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, - addr + offsetof(struct save_area, fp_ctrl_reg), - &vcpu->arch.guest_fpregs.fpc, 4, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, tod_reg), - &vcpu->arch.sie_block->todpr, 4, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, timer), - &vcpu->arch.sie_block->cputm, 8, prefix)) - return -EFAULT; - + gpa = kvm_s390_real_to_abs(vcpu, SAVE_AREA_BASE); + } + rc = write_guest_abs(vcpu, gpa + offsetof(struct save_area, fp_regs), + vcpu->arch.guest_fpregs.fprs, 128); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, gp_regs), + vcpu->run->s.regs.gprs, 128); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, psw), + &vcpu->arch.sie_block->gpsw, 16); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, pref_reg), + &vcpu->arch.sie_block->prefix, 4); + rc |= write_guest_abs(vcpu, + gpa + offsetof(struct save_area, fp_ctrl_reg), + &vcpu->arch.guest_fpregs.fpc, 4); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, tod_reg), + &vcpu->arch.sie_block->todpr, 4); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, timer), + &vcpu->arch.sie_block->cputm, 8); clkcomp = vcpu->arch.sie_block->ckc >> 8; - if (__guestcopy(vcpu, addr + offsetof(struct save_area, clk_cmp), - &clkcomp, 8, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, addr + offsetof(struct save_area, acc_regs), - &vcpu->run->s.regs.acrs, 64, prefix)) - return -EFAULT; - - if (__guestcopy(vcpu, - addr + offsetof(struct save_area, ctrl_regs), - &vcpu->arch.sie_block->gcr, 128, prefix)) - return -EFAULT; - return 0; + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, clk_cmp), + &clkcomp, 8); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, acc_regs), + &vcpu->run->s.regs.acrs, 64); + rc |= write_guest_abs(vcpu, gpa + offsetof(struct save_area, ctrl_regs), + &vcpu->arch.sie_block->gcr, 128); + return rc ? -EFAULT : 0; } int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr) -- cgit v1.2.3 From 665170cb47acbddc202df0d8487ca867b64e1604 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:47:12 +0100 Subject: KVM: s390: convert __sigp_set_prefix()/handle_set_prefix() Convert __sigp_set_prefix() and handle_set_prefix() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 20 ++++++++++++-------- arch/s390/kvm/sigp.c | 12 +++++++----- 2 files changed, 19 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 7066fc5bf48a..dd6ad8445608 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -65,8 +65,8 @@ static int handle_set_clock(struct kvm_vcpu *vcpu) static int handle_set_prefix(struct kvm_vcpu *vcpu) { u64 operand2; - u32 address = 0; - u8 tmp; + u32 address; + int rc; vcpu->stat.instruction_spx++; @@ -80,14 +80,18 @@ static int handle_set_prefix(struct kvm_vcpu *vcpu) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); /* get the value */ - if (get_guest(vcpu, address, (u32 __user *) operand2)) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = read_guest(vcpu, operand2, &address, sizeof(address)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); - address = address & 0x7fffe000u; + address &= 0x7fffe000u; - /* make sure that the new value is valid memory */ - if (copy_from_guest_absolute(vcpu, &tmp, address, 1) || - (copy_from_guest_absolute(vcpu, &tmp, address + PAGE_SIZE, 1))) + /* + * Make sure the new value is valid memory. We only need to check the + * first page, since address is 8k aligned and memory pieces are always + * at least 1MB aligned and have at least a size of 1MB. + */ + if (kvm_is_error_gpa(vcpu->kvm, address)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); kvm_s390_set_prefix(vcpu, address); diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c index 26caeb530a78..c0b99e0f6b63 100644 --- a/arch/s390/kvm/sigp.c +++ b/arch/s390/kvm/sigp.c @@ -235,7 +235,6 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address, struct kvm_vcpu *dst_vcpu = NULL; struct kvm_s390_interrupt_info *inti; int rc; - u8 tmp; if (cpu_addr < KVM_MAX_VCPUS) dst_vcpu = kvm_get_vcpu(vcpu->kvm, cpu_addr); @@ -243,10 +242,13 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address, return SIGP_CC_NOT_OPERATIONAL; li = &dst_vcpu->arch.local_int; - /* make sure that the new value is valid memory */ - address = address & 0x7fffe000u; - if (copy_from_guest_absolute(vcpu, &tmp, address, 1) || - copy_from_guest_absolute(vcpu, &tmp, address + PAGE_SIZE, 1)) { + /* + * Make sure the new value is valid memory. We only need to check the + * first page, since address is 8k aligned and memory pieces are always + * at least 1MB aligned and have at least a size of 1MB. + */ + address &= 0x7fffe000u; + if (kvm_is_error_gpa(vcpu->kvm, address)) { *reg &= 0xffffffff00000000UL; *reg |= SIGP_STATUS_INVALID_PARAMETER; return SIGP_CC_STATUS_STORED; -- cgit v1.2.3 From 0e7a3f9405d327bdc55ef1cdca7b63486b1916a0 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:50:11 +0100 Subject: KVM: s390: convert handle_set_clock() Convert handle_set_clock() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index dd6ad8445608..9648504d7818 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -35,8 +35,8 @@ static int handle_set_clock(struct kvm_vcpu *vcpu) { struct kvm_vcpu *cpup; s64 hostclk, val; + int i, rc; u64 op2; - int i; if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); @@ -44,8 +44,9 @@ static int handle_set_clock(struct kvm_vcpu *vcpu) op2 = kvm_s390_get_base_disp_s(vcpu); if (op2 & 7) /* Operand must be on a doubleword boundary */ return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - if (get_guest(vcpu, val, (u64 __user *) op2)) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = read_guest(vcpu, op2, &val, sizeof(val)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); if (store_tod_clock(&hostclk)) { kvm_s390_set_psw_cc(vcpu, 3); -- cgit v1.2.3 From f748f4a7ec549febb76e86082d9445beff1e9b01 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:52:47 +0100 Subject: KVM: s390: convert handle_store_prefix() Convert handle_store_prefix() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 9648504d7818..306caa27b962 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -106,6 +106,7 @@ static int handle_store_prefix(struct kvm_vcpu *vcpu) { u64 operand2; u32 address; + int rc; vcpu->stat.instruction_stpx++; @@ -122,8 +123,9 @@ static int handle_store_prefix(struct kvm_vcpu *vcpu) address = address & 0x7fffe000u; /* get the value */ - if (put_guest(vcpu, address, (u32 __user *)operand2)) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = write_guest(vcpu, operand2, &address, sizeof(address)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); VCPU_EVENT(vcpu, 5, "storing prefix to %x", address); trace_kvm_s390_handle_prefix(vcpu, 0, address); -- cgit v1.2.3 From 8b96de0e0359b731b1e5ec897f217f8bf7e5903f Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:53:27 +0100 Subject: KVM: s390: convert handle_store_cpu_address() Convert handle_store_cpu_address() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 306caa27b962..36c34cf22889 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -134,23 +134,26 @@ static int handle_store_prefix(struct kvm_vcpu *vcpu) static int handle_store_cpu_address(struct kvm_vcpu *vcpu) { - u64 useraddr; + u16 vcpu_id = vcpu->vcpu_id; + u64 ga; + int rc; vcpu->stat.instruction_stap++; if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); - useraddr = kvm_s390_get_base_disp_s(vcpu); + ga = kvm_s390_get_base_disp_s(vcpu); - if (useraddr & 1) + if (ga & 1) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - if (put_guest(vcpu, vcpu->vcpu_id, (u16 __user *)useraddr)) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = write_guest(vcpu, ga, &vcpu_id, sizeof(vcpu_id)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); - VCPU_EVENT(vcpu, 5, "storing cpu address to %llx", useraddr); - trace_kvm_s390_handle_stap(vcpu, useraddr); + VCPU_EVENT(vcpu, 5, "storing cpu address to %llx", ga); + trace_kvm_s390_handle_stap(vcpu, ga); return 0; } -- cgit v1.2.3 From ef23e7790e148041d159c1f710bee2b7b2f0d8cd Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:53:49 +0100 Subject: KVM: s390: convert handle_test_block() Convert handle_test_block() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 36c34cf22889..5abfd531a8f1 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -198,7 +198,6 @@ static int handle_ipte_interlock(struct kvm_vcpu *vcpu) static int handle_test_block(struct kvm_vcpu *vcpu) { - unsigned long hva; gpa_t addr; int reg2; @@ -209,14 +208,13 @@ static int handle_test_block(struct kvm_vcpu *vcpu) addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; addr = kvm_s390_real_to_abs(vcpu, addr); - hva = gfn_to_hva(vcpu->kvm, gpa_to_gfn(addr)); - if (kvm_is_error_hva(hva)) + if (kvm_is_error_gpa(vcpu->kvm, addr)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); /* * We don't expect errors on modern systems, and do not care * about storage keys (yet), so let's just clear the page. */ - if (clear_user((void __user *)hva, PAGE_SIZE) != 0) + if (kvm_clear_guest(vcpu->kvm, addr, PAGE_SIZE)) return -EFAULT; kvm_s390_set_psw_cc(vcpu, 0); vcpu->run->s.regs.gprs[0] = 0; -- cgit v1.2.3 From 4799b557c9aa3a7b540121f2bece719f22229a21 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:55:48 +0100 Subject: KVM: s390: convert handle_tpi() Convert handle_tpi() to new guest access functions. The code now sets up a structure which is copied with a single call to guest space instead of issuing several separate guest access calls. This is necessary since the to be copied data may cross a page boundary. If a protection exception happens while accessing any of the pages, the instruction is suppressed and may not have modified any memory contents. Signed-off-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 5abfd531a8f1..4f6bc165d79b 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -224,9 +224,12 @@ static int handle_test_block(struct kvm_vcpu *vcpu) static int handle_tpi(struct kvm_vcpu *vcpu) { struct kvm_s390_interrupt_info *inti; + unsigned long len; + u32 tpi_data[3]; + int cc, rc; u64 addr; - int cc; + rc = 0; addr = kvm_s390_get_base_disp_s(vcpu); if (addr & 3) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); @@ -235,30 +238,33 @@ static int handle_tpi(struct kvm_vcpu *vcpu) if (!inti) goto no_interrupt; cc = 1; + tpi_data[0] = inti->io.subchannel_id << 16 | inti->io.subchannel_nr; + tpi_data[1] = inti->io.io_int_parm; + tpi_data[2] = inti->io.io_int_word; if (addr) { /* * Store the two-word I/O interruption code into the * provided area. */ - if (put_guest(vcpu, inti->io.subchannel_id, (u16 __user *)addr) - || put_guest(vcpu, inti->io.subchannel_nr, (u16 __user *)(addr + 2)) - || put_guest(vcpu, inti->io.io_int_parm, (u32 __user *)(addr + 4))) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + len = sizeof(tpi_data) - 4; + rc = write_guest(vcpu, addr, &tpi_data, len); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); } else { /* * Store the three-word I/O interruption code into * the appropriate lowcore area. */ - put_guest(vcpu, inti->io.subchannel_id, (u16 __user *) __LC_SUBCHANNEL_ID); - put_guest(vcpu, inti->io.subchannel_nr, (u16 __user *) __LC_SUBCHANNEL_NR); - put_guest(vcpu, inti->io.io_int_parm, (u32 __user *) __LC_IO_INT_PARM); - put_guest(vcpu, inti->io.io_int_word, (u32 __user *) __LC_IO_INT_WORD); + len = sizeof(tpi_data); + if (write_guest_lc(vcpu, __LC_SUBCHANNEL_ID, &tpi_data, len)) + rc = -EFAULT; } kfree(inti); no_interrupt: /* Set condition code and we're done. */ - kvm_s390_set_psw_cc(vcpu, cc); - return 0; + if (!rc) + kvm_s390_set_psw_cc(vcpu, cc); + return rc ? -EFAULT : 0; } static int handle_tsch(struct kvm_vcpu *vcpu) -- cgit v1.2.3 From 2f32d4ea280c35d5f3a43fe7724020cb4824fffa Mon Sep 17 00:00:00 2001 From: Cornelia Huck Date: Wed, 8 Jan 2014 18:07:54 +0100 Subject: KVM: s390: reinject io interrupt on tpi failure The tpi instruction should be suppressed on addressing and protection exceptions, so we need to re-inject the dequeued io interrupt in that case. Signed-off-by: Cornelia Huck Signed-off-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/kvm/interrupt.c | 6 ++++++ arch/s390/kvm/kvm-s390.h | 2 ++ arch/s390/kvm/priv.c | 10 +++++++++- 3 files changed, 17 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index a1403ba75bfc..1c74bb92329b 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -846,6 +846,12 @@ int kvm_s390_inject_vm(struct kvm *kvm, return __inject_vm(kvm, inti); } +void kvm_s390_reinject_io_int(struct kvm *kvm, + struct kvm_s390_interrupt_info *inti) +{ + __inject_vm(kvm, inti); +} + int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu, struct kvm_s390_interrupt *s390int) { diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 11ed0a596b5a..dc506f3782ea 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -137,6 +137,8 @@ int __must_check kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu, int __must_check kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code); struct kvm_s390_interrupt_info *kvm_s390_get_io_int(struct kvm *kvm, u64 cr6, u64 schid); +void kvm_s390_reinject_io_int(struct kvm *kvm, + struct kvm_s390_interrupt_info *inti); int kvm_s390_mask_adapter(struct kvm *kvm, unsigned int id, bool masked); /* implemented in priv.c */ diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 4f6bc165d79b..f4451f09b9ed 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -259,7 +259,15 @@ static int handle_tpi(struct kvm_vcpu *vcpu) if (write_guest_lc(vcpu, __LC_SUBCHANNEL_ID, &tpi_data, len)) rc = -EFAULT; } - kfree(inti); + /* + * If we encounter a problem storing the interruption code, the + * instruction is suppressed from the guest's view: reinject the + * interrupt. + */ + if (!rc) + kfree(inti); + else + kvm_s390_reinject_io_int(vcpu->kvm, inti); no_interrupt: /* Set condition code and we're done. */ if (!rc) -- cgit v1.2.3 From 2d8bcaeda1576ddd970629a6afb9a188c83cd409 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:57:42 +0100 Subject: KVM: s390: convert handle_lpsw[e]() Convert handle_lpsw[e]() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index f4451f09b9ed..2de74543bd07 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -381,6 +381,7 @@ int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu) psw_t *gpsw = &vcpu->arch.sie_block->gpsw; psw_compat_t new_psw; u64 addr; + int rc; if (gpsw->mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); @@ -388,8 +389,10 @@ int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu) addr = kvm_s390_get_base_disp_s(vcpu); if (addr & 7) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - if (copy_from_guest(vcpu, &new_psw, addr, sizeof(new_psw))) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + + rc = read_guest(vcpu, addr, &new_psw, sizeof(new_psw)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); if (!(new_psw.mask & PSW32_MASK_BASE)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); gpsw->mask = (new_psw.mask & ~PSW32_MASK_BASE) << 32; @@ -405,6 +408,7 @@ static int handle_lpswe(struct kvm_vcpu *vcpu) { psw_t new_psw; u64 addr; + int rc; if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); @@ -412,8 +416,9 @@ static int handle_lpswe(struct kvm_vcpu *vcpu) addr = kvm_s390_get_base_disp_s(vcpu); if (addr & 7) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - if (copy_from_guest(vcpu, &new_psw, addr, sizeof(new_psw))) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = read_guest(vcpu, addr, &new_psw, sizeof(new_psw)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); vcpu->arch.sie_block->gpsw = new_psw; if (!is_valid_psw(&vcpu->arch.sie_block->gpsw)) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); -- cgit v1.2.3 From 7d777d78241d98bbd75886a8d09a3c793eafc807 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:58:16 +0100 Subject: KVM: s390: convert handle_stidp() Convert handle_stidp() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 2de74543bd07..bc969722a293 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -428,7 +428,9 @@ static int handle_lpswe(struct kvm_vcpu *vcpu) static int handle_stidp(struct kvm_vcpu *vcpu) { + u64 stidp_data = vcpu->arch.stidp_data; u64 operand2; + int rc; vcpu->stat.instruction_stidp++; @@ -440,8 +442,9 @@ static int handle_stidp(struct kvm_vcpu *vcpu) if (operand2 & 7) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - if (put_guest(vcpu, vcpu->arch.stidp_data, (u64 __user *)operand2)) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + rc = write_guest(vcpu, operand2, &stidp_data, sizeof(stidp_data)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); VCPU_EVENT(vcpu, 5, "%s", "store cpu id"); return 0; -- cgit v1.2.3 From f987a3eef03092c895be5de7ac38ebf3558d5113 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:59:21 +0100 Subject: KVM: s390: convert handle lctl[g]() Convert handle lctl[g]() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index bc969722a293..44ff22007052 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -755,32 +755,31 @@ int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu) { int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; int reg3 = vcpu->arch.sie_block->ipa & 0x000f; - u64 useraddr; u32 val = 0; int reg, rc; + u64 ga; vcpu->stat.instruction_lctl++; if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); - useraddr = kvm_s390_get_base_disp_rs(vcpu); + ga = kvm_s390_get_base_disp_rs(vcpu); - if (useraddr & 3) + if (ga & 3) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); - VCPU_EVENT(vcpu, 5, "lctl r1:%x, r3:%x, addr:%llx", reg1, reg3, - useraddr); - trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, useraddr); + VCPU_EVENT(vcpu, 5, "lctl r1:%x, r3:%x, addr:%llx", reg1, reg3, ga); + trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, ga); reg = reg1; do { - rc = get_guest(vcpu, val, (u32 __user *) useraddr); + rc = read_guest(vcpu, ga, &val, sizeof(val)); if (rc) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + return kvm_s390_inject_prog_cond(vcpu, rc); vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul; vcpu->arch.sie_block->gcr[reg] |= val; - useraddr += 4; + ga += 4; if (reg == reg3) break; reg = (reg + 1) % 16; @@ -793,7 +792,7 @@ static int handle_lctlg(struct kvm_vcpu *vcpu) { int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; int reg3 = vcpu->arch.sie_block->ipa & 0x000f; - u64 useraddr; + u64 ga, val; int reg, rc; vcpu->stat.instruction_lctlg++; @@ -801,23 +800,22 @@ static int handle_lctlg(struct kvm_vcpu *vcpu) if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); - useraddr = kvm_s390_get_base_disp_rsy(vcpu); + ga = kvm_s390_get_base_disp_rsy(vcpu); - if (useraddr & 7) + if (ga & 7) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); reg = reg1; - VCPU_EVENT(vcpu, 5, "lctlg r1:%x, r3:%x, addr:%llx", reg1, reg3, - useraddr); - trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, useraddr); + VCPU_EVENT(vcpu, 5, "lctlg r1:%x, r3:%x, addr:%llx", reg1, reg3, ga); + trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, ga); do { - rc = get_guest(vcpu, vcpu->arch.sie_block->gcr[reg], - (u64 __user *) useraddr); + rc = read_guest(vcpu, ga, &val, sizeof(val)); if (rc) - return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); - useraddr += 8; + return kvm_s390_inject_prog_cond(vcpu, rc); + vcpu->arch.sie_block->gcr[reg] = val; + ga += 8; if (reg == reg3) break; reg = (reg + 1) % 16; -- cgit v1.2.3 From 645c5bc1d5b1253bf3df849edc339ec09b43371a Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:58:59 +0100 Subject: KVM: s390: convert handle_stsi() Convert handle_stsi() to new guest access functions. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 44ff22007052..5fb503a6c443 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -530,9 +530,10 @@ static int handle_stsi(struct kvm_vcpu *vcpu) break; } - if (copy_to_guest_absolute(vcpu, operand2, (void *) mem, PAGE_SIZE)) { - rc = kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); - goto out_exception; + rc = write_guest(vcpu, operand2, (void *)mem, PAGE_SIZE); + if (rc) { + rc = kvm_s390_inject_prog_cond(vcpu, rc); + goto out; } trace_kvm_s390_handle_stsi(vcpu, fc, sel1, sel2, operand2); free_page(mem); @@ -541,7 +542,7 @@ static int handle_stsi(struct kvm_vcpu *vcpu) return 0; out_no_data: kvm_s390_set_psw_cc(vcpu, 3); -out_exception: +out: free_page(mem); return rc; } -- cgit v1.2.3 From 3263bd163720807e68045370b70aaf38acde1598 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 2 Jan 2014 10:46:01 +0100 Subject: KVM: s390: remove old guest access functions Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/gaccess.h | 81 ------------------------------------------------- 1 file changed, 81 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index f46e764c5b43..ed4749ecef8b 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -56,87 +56,6 @@ static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu, return ga & ((1UL << 24) - 1); } -static inline void __user *__gptr_to_uptr(struct kvm_vcpu *vcpu, - void __user *gptr, - int prefixing) -{ - unsigned long gaddr = (unsigned long) gptr; - unsigned long uaddr; - - if (prefixing) - gaddr = kvm_s390_real_to_abs(vcpu, gaddr); - uaddr = gmap_fault(gaddr, vcpu->arch.gmap); - if (IS_ERR_VALUE(uaddr)) - uaddr = -EFAULT; - return (void __user *)uaddr; -} - -#define get_guest(vcpu, x, gptr) \ -({ \ - __typeof__(gptr) __uptr = __gptr_to_uptr(vcpu, gptr, 1);\ - int __mask = sizeof(__typeof__(*(gptr))) - 1; \ - int __ret; \ - \ - if (IS_ERR((void __force *)__uptr)) { \ - __ret = PTR_ERR((void __force *)__uptr); \ - } else { \ - BUG_ON((unsigned long)__uptr & __mask); \ - __ret = get_user(x, __uptr); \ - } \ - __ret; \ -}) - -#define put_guest(vcpu, x, gptr) \ -({ \ - __typeof__(gptr) __uptr = __gptr_to_uptr(vcpu, gptr, 1);\ - int __mask = sizeof(__typeof__(*(gptr))) - 1; \ - int __ret; \ - \ - if (IS_ERR((void __force *)__uptr)) { \ - __ret = PTR_ERR((void __force *)__uptr); \ - } else { \ - BUG_ON((unsigned long)__uptr & __mask); \ - __ret = put_user(x, __uptr); \ - } \ - __ret; \ -}) - -static inline int __copy_guest(struct kvm_vcpu *vcpu, unsigned long to, - unsigned long from, unsigned long len, - int to_guest, int prefixing) -{ - unsigned long _len, rc; - void __user *uptr; - - while (len) { - uptr = to_guest ? (void __user *)to : (void __user *)from; - uptr = __gptr_to_uptr(vcpu, uptr, prefixing); - if (IS_ERR((void __force *)uptr)) - return -EFAULT; - _len = PAGE_SIZE - ((unsigned long)uptr & (PAGE_SIZE - 1)); - _len = min(_len, len); - if (to_guest) - rc = copy_to_user((void __user *) uptr, (void *)from, _len); - else - rc = copy_from_user((void *)to, (void __user *)uptr, _len); - if (rc) - return -EFAULT; - len -= _len; - from += _len; - to += _len; - } - return 0; -} - -#define copy_to_guest(vcpu, to, from, size) \ - __copy_guest(vcpu, to, (unsigned long)from, size, 1, 1) -#define copy_from_guest(vcpu, to, from, size) \ - __copy_guest(vcpu, (unsigned long)to, from, size, 0, 1) -#define copy_to_guest_absolute(vcpu, to, from, size) \ - __copy_guest(vcpu, to, (unsigned long)from, size, 1, 0) -#define copy_from_guest_absolute(vcpu, to, from, size) \ - __copy_guest(vcpu, (unsigned long)to, from, size, 0, 0) - /* * put_guest_lc, read_guest_lc and write_guest_lc are guest access functions * which shall only be used to access the lowcore of a vcpu. -- cgit v1.2.3 From e497a96ae8eda8b693bebc8f464712cd788d641f Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Wed, 1 Jan 2014 16:19:55 +0100 Subject: KVM: s390: cleanup kvm_s390_real_to_abs() Add kerneldoc comment to kvm_s390_real_to_abs() and change the code so it matches the coding style of the rest of gaccess.h. Signed-off-by: Heiko Carstens Reviewed-by: Thomas Huth Signed-off-by: Christian Borntraeger --- arch/s390/kvm/gaccess.h | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index ed4749ecef8b..1079c8fc6d0d 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -19,16 +19,24 @@ #include #include "kvm-s390.h" -/* Convert real to absolute address by applying the prefix of the CPU */ +/** + * kvm_s390_real_to_abs - convert guest real address to guest absolute address + * @vcpu - guest virtual cpu + * @gra - guest real address + * + * Returns the guest absolute address that corresponds to the passed guest real + * address @gra of a virtual guest cpu by applying its prefix. + */ static inline unsigned long kvm_s390_real_to_abs(struct kvm_vcpu *vcpu, - unsigned long gaddr) + unsigned long gra) { - unsigned long prefix = vcpu->arch.sie_block->prefix; - if (gaddr < 2 * PAGE_SIZE) - gaddr += prefix; - else if (gaddr >= prefix && gaddr < prefix + 2 * PAGE_SIZE) - gaddr -= prefix; - return gaddr; + unsigned long prefix = vcpu->arch.sie_block->prefix; + + if (gra < 2 * PAGE_SIZE) + gra += prefix; + else if (gra >= prefix && gra < prefix + 2 * PAGE_SIZE) + gra -= prefix; + return gra; } /** -- cgit v1.2.3 From 3d53b46ce8b1b873cf8501bac251b8c0cf489d4f Mon Sep 17 00:00:00 2001 From: Jens Freimann Date: Mon, 10 Feb 2014 10:55:37 +0100 Subject: s390: fix name of lowcore field at offset 0xa3 According to the Principles of Operation, at offset 0xA3 in the lowcore we have the "Architectural-Mode identification", not an "access identification". Signed-off-by: Jens Freimann Acked-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/lowcore.h | 4 ++-- arch/s390/kernel/asm-offsets.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h index bbf8141408cd..edfa89b67e78 100644 --- a/arch/s390/include/asm/lowcore.h +++ b/arch/s390/include/asm/lowcore.h @@ -62,7 +62,7 @@ struct _lowcore { __u8 exc_access_id; /* 0x00a0 */ __u8 per_access_id; /* 0x00a1 */ __u8 op_access_id; /* 0x00a2 */ - __u8 ar_access_id; /* 0x00a3 */ + __u8 ar_mode_id; /* 0x00a3 */ __u8 pad_0x00a4[0x00b8-0x00a4]; /* 0x00a4 */ __u16 subchannel_id; /* 0x00b8 */ __u16 subchannel_nr; /* 0x00ba */ @@ -201,7 +201,7 @@ struct _lowcore { __u8 exc_access_id; /* 0x00a0 */ __u8 per_access_id; /* 0x00a1 */ __u8 op_access_id; /* 0x00a2 */ - __u8 ar_access_id; /* 0x00a3 */ + __u8 ar_mode_id; /* 0x00a3 */ __u8 pad_0x00a4[0x00a8-0x00a4]; /* 0x00a4 */ __u64 trans_exc_code; /* 0x00a8 */ __u64 monitor_code; /* 0x00b0 */ diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index cc10cdd4d6a2..94c18d482ce7 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -92,7 +92,7 @@ int main(void) DEFINE(__LC_PER_CAUSE, offsetof(struct _lowcore, per_perc_atmid)); DEFINE(__LC_PER_ADDRESS, offsetof(struct _lowcore, per_address)); DEFINE(__LC_PER_PAID, offsetof(struct _lowcore, per_access_id)); - DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_access_id)); + DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_mode_id)); DEFINE(__LC_SUBCHANNEL_ID, offsetof(struct _lowcore, subchannel_id)); DEFINE(__LC_SUBCHANNEL_NR, offsetof(struct _lowcore, subchannel_nr)); DEFINE(__LC_IO_INT_PARM, offsetof(struct _lowcore, io_int_parm)); -- cgit v1.2.3 From 21ee7ffd176a238cf185c142bd4c20d0152eda4f Mon Sep 17 00:00:00 2001 From: Jens Freimann Date: Wed, 26 Feb 2014 16:32:46 +0100 Subject: s390: rename and split lowcore field per_perc_atmid per_perc_atmid is currently a two-byte field that combines two fields, the PER code and the PER Addressing-and-Translation-Mode Identification (ATMID) Let's make them accessible indepently and also rename per_cause to per_code. Signed-off-by: Jens Freimann Acked-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/lowcore.h | 6 ++++-- arch/s390/kernel/asm-offsets.c | 5 +++-- arch/s390/kernel/entry.S | 4 ++-- arch/s390/kernel/entry64.S | 4 ++-- 4 files changed, 11 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h index edfa89b67e78..e88cb8c54130 100644 --- a/arch/s390/include/asm/lowcore.h +++ b/arch/s390/include/asm/lowcore.h @@ -56,7 +56,8 @@ struct _lowcore { __u16 pgm_code; /* 0x008e */ __u32 trans_exc_code; /* 0x0090 */ __u16 mon_class_num; /* 0x0094 */ - __u16 per_perc_atmid; /* 0x0096 */ + __u8 per_code; /* 0x0096 */ + __u8 per_atmid; /* 0x0097 */ __u32 per_address; /* 0x0098 */ __u32 monitor_code; /* 0x009c */ __u8 exc_access_id; /* 0x00a0 */ @@ -196,7 +197,8 @@ struct _lowcore { __u16 pgm_code; /* 0x008e */ __u32 data_exc_code; /* 0x0090 */ __u16 mon_class_num; /* 0x0094 */ - __u16 per_perc_atmid; /* 0x0096 */ + __u8 per_code; /* 0x0096 */ + __u8 per_atmid; /* 0x0097 */ __u64 per_address; /* 0x0098 */ __u8 exc_access_id; /* 0x00a0 */ __u8 per_access_id; /* 0x00a1 */ diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index 94c18d482ce7..31e4ba4aaf17 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -89,9 +89,10 @@ int main(void) DEFINE(__LC_PGM_ILC, offsetof(struct _lowcore, pgm_ilc)); DEFINE(__LC_PGM_INT_CODE, offsetof(struct _lowcore, pgm_code)); DEFINE(__LC_TRANS_EXC_CODE, offsetof(struct _lowcore, trans_exc_code)); - DEFINE(__LC_PER_CAUSE, offsetof(struct _lowcore, per_perc_atmid)); + DEFINE(__LC_PER_CODE, offsetof(struct _lowcore, per_code)); + DEFINE(__LC_PER_ATMID, offsetof(struct _lowcore, per_atmid)); DEFINE(__LC_PER_ADDRESS, offsetof(struct _lowcore, per_address)); - DEFINE(__LC_PER_PAID, offsetof(struct _lowcore, per_access_id)); + DEFINE(__LC_PER_ACCESS_ID, offsetof(struct _lowcore, per_access_id)); DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_mode_id)); DEFINE(__LC_SUBCHANNEL_ID, offsetof(struct _lowcore, subchannel_id)); DEFINE(__LC_SUBCHANNEL_NR, offsetof(struct _lowcore, subchannel_nr)); diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S index 1662038516c0..e66f046b9c43 100644 --- a/arch/s390/kernel/entry.S +++ b/arch/s390/kernel/entry.S @@ -391,8 +391,8 @@ ENTRY(pgm_check_handler) jz pgm_kprobe oi __TI_flags+3(%r12),_TIF_PER_TRAP mvc __THREAD_per_address(4,%r1),__LC_PER_ADDRESS - mvc __THREAD_per_cause(2,%r1),__LC_PER_CAUSE - mvc __THREAD_per_paid(1,%r1),__LC_PER_PAID + mvc __THREAD_per_cause(2,%r1),__LC_PER_CODE + mvc __THREAD_per_paid(1,%r1),__LC_PER_ACCESS_ID 0: REENABLE_IRQS xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) l %r1,BASED(.Ljump_table) diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S index 5963e43618bb..3c34753de6ad 100644 --- a/arch/s390/kernel/entry64.S +++ b/arch/s390/kernel/entry64.S @@ -423,8 +423,8 @@ ENTRY(pgm_check_handler) jz pgm_kprobe oi __TI_flags+7(%r12),_TIF_PER_TRAP mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS - mvc __THREAD_per_cause(2,%r14),__LC_PER_CAUSE - mvc __THREAD_per_paid(1,%r14),__LC_PER_PAID + mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE + mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID 0: REENABLE_IRQS xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15) larl %r1,pgm_check_table -- cgit v1.2.3 From da7cf2570c5fa29a02a3e8026bfff89620706d2f Mon Sep 17 00:00:00 2001 From: Jens Freimann Date: Wed, 26 Feb 2014 17:03:29 +0100 Subject: s390: add fields to lowcore definition This patch adds fields which are currently missing but needed for the correct injection of interrupts. This is based on a patch by David Hildenbrand Signed-off-by: Jens Freimann Acked-by: Heiko Carstens Signed-off-by: Christian Borntraeger --- arch/s390/kernel/asm-offsets.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index 31e4ba4aaf17..859a7ed36c4b 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c @@ -89,17 +89,22 @@ int main(void) DEFINE(__LC_PGM_ILC, offsetof(struct _lowcore, pgm_ilc)); DEFINE(__LC_PGM_INT_CODE, offsetof(struct _lowcore, pgm_code)); DEFINE(__LC_TRANS_EXC_CODE, offsetof(struct _lowcore, trans_exc_code)); + DEFINE(__LC_MON_CLASS_NR, offsetof(struct _lowcore, mon_class_num)); DEFINE(__LC_PER_CODE, offsetof(struct _lowcore, per_code)); DEFINE(__LC_PER_ATMID, offsetof(struct _lowcore, per_atmid)); DEFINE(__LC_PER_ADDRESS, offsetof(struct _lowcore, per_address)); + DEFINE(__LC_EXC_ACCESS_ID, offsetof(struct _lowcore, exc_access_id)); DEFINE(__LC_PER_ACCESS_ID, offsetof(struct _lowcore, per_access_id)); + DEFINE(__LC_OP_ACCESS_ID, offsetof(struct _lowcore, op_access_id)); DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_mode_id)); + DEFINE(__LC_MON_CODE, offsetof(struct _lowcore, monitor_code)); DEFINE(__LC_SUBCHANNEL_ID, offsetof(struct _lowcore, subchannel_id)); DEFINE(__LC_SUBCHANNEL_NR, offsetof(struct _lowcore, subchannel_nr)); DEFINE(__LC_IO_INT_PARM, offsetof(struct _lowcore, io_int_parm)); DEFINE(__LC_IO_INT_WORD, offsetof(struct _lowcore, io_int_word)); DEFINE(__LC_STFL_FAC_LIST, offsetof(struct _lowcore, stfl_fac_list)); DEFINE(__LC_MCCK_CODE, offsetof(struct _lowcore, mcck_interruption_code)); + DEFINE(__LC_MCCK_EXT_DAM_CODE, offsetof(struct _lowcore, external_damage_code)); DEFINE(__LC_RST_OLD_PSW, offsetof(struct _lowcore, restart_old_psw)); DEFINE(__LC_EXT_OLD_PSW, offsetof(struct _lowcore, external_old_psw)); DEFINE(__LC_SVC_OLD_PSW, offsetof(struct _lowcore, svc_old_psw)); @@ -157,6 +162,8 @@ int main(void) #ifdef CONFIG_32BIT DEFINE(SAVE_AREA_BASE, offsetof(struct _lowcore, extended_save_area_addr)); #else /* CONFIG_32BIT */ + DEFINE(__LC_DATA_EXC_CODE, offsetof(struct _lowcore, data_exc_code)); + DEFINE(__LC_MCCK_FAIL_STOR_ADDR, offsetof(struct _lowcore, failing_storage_address)); DEFINE(__LC_EXT_PARAMS2, offsetof(struct _lowcore, ext_params2)); DEFINE(SAVE_AREA_BASE, offsetof(struct _lowcore, floating_pt_save_area)); DEFINE(__LC_PASTE, offsetof(struct _lowcore, paste)); -- cgit v1.2.3 From 439716a5cab30e930bd1ec0f8fd66cbbaa319250 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Mon, 3 Mar 2014 10:54:33 +0100 Subject: KVM: s390: extract irq parameters of intercepted program irqs Whenever a program interrupt is intercepted, some parameters are stored in the sie control block. These parameters have to be extracted in order to be reinjected correctly. This patch also takes care of intercepted PER events which can occurr in addition to any program interrupt. Signed-off-by: David Hildenbrand Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 18 +++++++++-- arch/s390/kvm/intercept.c | 65 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 79 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index f1ed7bdba733..b8c808192893 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -120,9 +120,21 @@ struct kvm_s390_sie_block { psw_t gpsw; /* 0x0090 */ __u64 gg14; /* 0x00a0 */ __u64 gg15; /* 0x00a8 */ - __u8 reservedb0[30]; /* 0x00b0 */ - __u16 iprcc; /* 0x00ce */ - __u8 reservedd0[48]; /* 0x00d0 */ + __u8 reservedb0[28]; /* 0x00b0 */ + __u16 pgmilc; /* 0x00cc */ + __u16 iprcc; /* 0x00ce */ + __u32 dxc; /* 0x00d0 */ + __u16 mcn; /* 0x00d4 */ + __u8 perc; /* 0x00d6 */ + __u8 peratmid; /* 0x00d7 */ + __u64 peraddr; /* 0x00d8 */ + __u8 eai; /* 0x00e0 */ + __u8 peraid; /* 0x00e1 */ + __u8 oai; /* 0x00e2 */ + __u8 armid; /* 0x00e3 */ + __u8 reservede4[4]; /* 0x00e4 */ + __u64 tecmc; /* 0x00e8 */ + __u8 reservedf0[16]; /* 0x00f0 */ __u64 gcr[16]; /* 0x0100 */ __u64 gbea; /* 0x0180 */ __u8 reserved188[24]; /* 0x0188 */ diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index a8d8da84005b..4c3311e41727 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -109,8 +109,69 @@ static int handle_instruction(struct kvm_vcpu *vcpu) return -EOPNOTSUPP; } +static void __extract_prog_irq(struct kvm_vcpu *vcpu, + struct kvm_s390_pgm_info *pgm_info) +{ + memset(pgm_info, 0, sizeof(struct kvm_s390_pgm_info)); + pgm_info->code = vcpu->arch.sie_block->iprcc; + + switch (vcpu->arch.sie_block->iprcc & ~PGM_PER) { + case PGM_AFX_TRANSLATION: + case PGM_ASX_TRANSLATION: + case PGM_EX_TRANSLATION: + case PGM_LFX_TRANSLATION: + case PGM_LSTE_SEQUENCE: + case PGM_LSX_TRANSLATION: + case PGM_LX_TRANSLATION: + case PGM_PRIMARY_AUTHORITY: + case PGM_SECONDARY_AUTHORITY: + case PGM_SPACE_SWITCH: + pgm_info->trans_exc_code = vcpu->arch.sie_block->tecmc; + break; + case PGM_ALEN_TRANSLATION: + case PGM_ALE_SEQUENCE: + case PGM_ASTE_INSTANCE: + case PGM_ASTE_SEQUENCE: + case PGM_ASTE_VALIDITY: + case PGM_EXTENDED_AUTHORITY: + pgm_info->exc_access_id = vcpu->arch.sie_block->eai; + break; + case PGM_ASCE_TYPE: + case PGM_PAGE_TRANSLATION: + case PGM_REGION_FIRST_TRANS: + case PGM_REGION_SECOND_TRANS: + case PGM_REGION_THIRD_TRANS: + case PGM_SEGMENT_TRANSLATION: + pgm_info->trans_exc_code = vcpu->arch.sie_block->tecmc; + pgm_info->exc_access_id = vcpu->arch.sie_block->eai; + pgm_info->op_access_id = vcpu->arch.sie_block->oai; + break; + case PGM_MONITOR: + pgm_info->mon_class_nr = vcpu->arch.sie_block->mcn; + pgm_info->mon_code = vcpu->arch.sie_block->tecmc; + break; + case PGM_DATA: + pgm_info->data_exc_code = vcpu->arch.sie_block->dxc; + break; + case PGM_PROTECTION: + pgm_info->trans_exc_code = vcpu->arch.sie_block->tecmc; + pgm_info->exc_access_id = vcpu->arch.sie_block->eai; + break; + default: + break; + } + + if (vcpu->arch.sie_block->iprcc & PGM_PER) { + pgm_info->per_code = vcpu->arch.sie_block->perc; + pgm_info->per_atmid = vcpu->arch.sie_block->peratmid; + pgm_info->per_address = vcpu->arch.sie_block->peraddr; + pgm_info->per_access_id = vcpu->arch.sie_block->peraid; + } +} + static int handle_prog(struct kvm_vcpu *vcpu) { + struct kvm_s390_pgm_info pgm_info; struct kvm_s390_itdb *itdb; int rc; @@ -128,7 +189,9 @@ static int handle_prog(struct kvm_vcpu *vcpu) memset(itdb, 0, sizeof(*itdb)); skip_itdb: trace_kvm_s390_intercept_prog(vcpu, vcpu->arch.sie_block->iprcc); - return kvm_s390_inject_program_int(vcpu, vcpu->arch.sie_block->iprcc); + __extract_prog_irq(vcpu, &pgm_info); + + return kvm_s390_inject_prog_irq(vcpu, &pgm_info); } static int handle_instruction_and_prog(struct kvm_vcpu *vcpu) -- cgit v1.2.3 From 8712836b30cef5d49bc3bb8bc3da88a40e11e574 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Mon, 3 Mar 2014 10:55:13 +0100 Subject: KVM: s390: deliver program irq parameters and use correct ilc When a program interrupt was to be delivered until now, no program interrupt parameters were stored in the low-core of the target vcpu. This patch enables the delivery of those program interrupt parameters, takes care of concurrent PER events which can be injected in addition to any program interrupt and uses the correct instruction length code (depending on the interception code) for the injection of program interrupts. Signed-off-by: David Hildenbrand Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 6 +++ arch/s390/kvm/interrupt.c | 110 +++++++++++++++++++++++++++++++++++---- 2 files changed, 107 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index b8c808192893..5e5a14db8c21 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -102,6 +102,12 @@ struct kvm_s390_sie_block { #define ICTL_RRBE 0x00001000 __u32 ictl; /* 0x0048 */ __u32 eca; /* 0x004c */ +#define ICPT_INST 0x04 +#define ICPT_PROGI 0x08 +#define ICPT_INSTPROGI 0x0C +#define ICPT_OPEREXC 0x2C +#define ICPT_PARTEXEC 0x38 +#define ICPT_IOINST 0x40 __u8 icptcode; /* 0x0050 */ __u8 reserved51; /* 0x0051 */ __u16 ihcpu; /* 0x0052 */ diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index 1c74bb92329b..c49b4d4d310a 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -174,6 +174,106 @@ static void __set_intercept_indicator(struct kvm_vcpu *vcpu, } } +static int __deliver_prog_irq(struct kvm_vcpu *vcpu, + struct kvm_s390_pgm_info *pgm_info) +{ + const unsigned short table[] = { 2, 4, 4, 6 }; + int rc = 0; + + switch (pgm_info->code & ~PGM_PER) { + case PGM_AFX_TRANSLATION: + case PGM_ASX_TRANSLATION: + case PGM_EX_TRANSLATION: + case PGM_LFX_TRANSLATION: + case PGM_LSTE_SEQUENCE: + case PGM_LSX_TRANSLATION: + case PGM_LX_TRANSLATION: + case PGM_PRIMARY_AUTHORITY: + case PGM_SECONDARY_AUTHORITY: + case PGM_SPACE_SWITCH: + rc = put_guest_lc(vcpu, pgm_info->trans_exc_code, + (u64 *)__LC_TRANS_EXC_CODE); + break; + case PGM_ALEN_TRANSLATION: + case PGM_ALE_SEQUENCE: + case PGM_ASTE_INSTANCE: + case PGM_ASTE_SEQUENCE: + case PGM_ASTE_VALIDITY: + case PGM_EXTENDED_AUTHORITY: + rc = put_guest_lc(vcpu, pgm_info->exc_access_id, + (u8 *)__LC_EXC_ACCESS_ID); + break; + case PGM_ASCE_TYPE: + case PGM_PAGE_TRANSLATION: + case PGM_REGION_FIRST_TRANS: + case PGM_REGION_SECOND_TRANS: + case PGM_REGION_THIRD_TRANS: + case PGM_SEGMENT_TRANSLATION: + rc = put_guest_lc(vcpu, pgm_info->trans_exc_code, + (u64 *)__LC_TRANS_EXC_CODE); + rc |= put_guest_lc(vcpu, pgm_info->exc_access_id, + (u8 *)__LC_EXC_ACCESS_ID); + rc |= put_guest_lc(vcpu, pgm_info->op_access_id, + (u8 *)__LC_OP_ACCESS_ID); + break; + case PGM_MONITOR: + rc = put_guest_lc(vcpu, pgm_info->mon_class_nr, + (u64 *)__LC_MON_CLASS_NR); + rc |= put_guest_lc(vcpu, pgm_info->mon_code, + (u64 *)__LC_MON_CODE); + break; + case PGM_DATA: + rc = put_guest_lc(vcpu, pgm_info->data_exc_code, + (u32 *)__LC_DATA_EXC_CODE); + break; + case PGM_PROTECTION: + rc = put_guest_lc(vcpu, pgm_info->trans_exc_code, + (u64 *)__LC_TRANS_EXC_CODE); + rc |= put_guest_lc(vcpu, pgm_info->exc_access_id, + (u8 *)__LC_EXC_ACCESS_ID); + break; + } + + if (pgm_info->code & PGM_PER) { + rc |= put_guest_lc(vcpu, pgm_info->per_code, + (u8 *) __LC_PER_CODE); + rc |= put_guest_lc(vcpu, pgm_info->per_atmid, + (u8 *)__LC_PER_ATMID); + rc |= put_guest_lc(vcpu, pgm_info->per_address, + (u64 *) __LC_PER_ADDRESS); + rc |= put_guest_lc(vcpu, pgm_info->per_access_id, + (u8 *) __LC_PER_ACCESS_ID); + } + + switch (vcpu->arch.sie_block->icptcode) { + case ICPT_INST: + case ICPT_INSTPROGI: + case ICPT_OPEREXC: + case ICPT_PARTEXEC: + case ICPT_IOINST: + /* last instruction only stored for these icptcodes */ + rc |= put_guest_lc(vcpu, table[vcpu->arch.sie_block->ipa >> 14], + (u16 *) __LC_PGM_ILC); + break; + case ICPT_PROGI: + rc |= put_guest_lc(vcpu, vcpu->arch.sie_block->pgmilc, + (u16 *) __LC_PGM_ILC); + break; + default: + rc |= put_guest_lc(vcpu, 0, + (u16 *) __LC_PGM_ILC); + } + + rc |= put_guest_lc(vcpu, pgm_info->code, + (u16 *)__LC_PGM_INT_CODE); + rc |= write_guest_lc(vcpu, __LC_PGM_OLD_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_PGM_NEW_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + + return rc; +} + static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, struct kvm_s390_interrupt_info *inti) { @@ -305,15 +405,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, vcpu->stat.deliver_program_int++; trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, inti->pgm.code, 0); - rc = put_guest_lc(vcpu, inti->pgm.code, - (u16 __user *)__LC_PGM_INT_CODE); - rc |= put_guest_lc(vcpu, table[vcpu->arch.sie_block->ipa >> 14], - (u16 __user *)__LC_PGM_ILC); - rc |= write_guest_lc(vcpu, __LC_PGM_OLD_PSW, - &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - rc |= read_guest_lc(vcpu, __LC_PGM_NEW_PSW, - &vcpu->arch.sie_block->gpsw, - sizeof(psw_t)); + rc = __deliver_prog_irq(vcpu, &inti->pgm); break; case KVM_S390_MCHK: -- cgit v1.2.3 From aba0750889d012f84a719112997abb7be11bba4b Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 23 Jan 2014 10:47:13 +0100 Subject: KVM: s390: emulate stctl and stctg Introduce the methods to emulate the stctl and stctg instruction. Added tracing code. Signed-off-by: David Hildenbrand Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 2 ++ arch/s390/kvm/intercept.c | 1 + arch/s390/kvm/kvm-s390.c | 2 ++ arch/s390/kvm/kvm-s390.h | 1 + arch/s390/kvm/priv.c | 73 ++++++++++++++++++++++++++++++++++++++++ arch/s390/kvm/trace.h | 25 ++++++++++++++ 6 files changed, 104 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index 5e5a14db8c21..5d9648925a8e 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -175,6 +175,8 @@ struct kvm_vcpu_stat { u32 exit_instruction; u32 instruction_lctl; u32 instruction_lctlg; + u32 instruction_stctl; + u32 instruction_stctg; u32 exit_program_interruption; u32 exit_instr_and_program; u32 deliver_external_call; diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index 4c3311e41727..c0e6b49191ba 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -29,6 +29,7 @@ static const intercept_handler_t instruction_handlers[256] = { [0x83] = kvm_s390_handle_diag, [0xae] = kvm_s390_handle_sigp, [0xb2] = kvm_s390_handle_b2, + [0xb6] = kvm_s390_handle_stctl, [0xb7] = kvm_s390_handle_lctl, [0xb9] = kvm_s390_handle_b9, [0xe5] = kvm_s390_handle_e5, diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index ae7c1265fcc1..7ae8c26065fb 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -52,6 +52,8 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { "exit_instr_and_program_int", VCPU_STAT(exit_instr_and_program) }, { "instruction_lctlg", VCPU_STAT(instruction_lctlg) }, { "instruction_lctl", VCPU_STAT(instruction_lctl) }, + { "instruction_stctl", VCPU_STAT(instruction_stctl) }, + { "instruction_stctg", VCPU_STAT(instruction_stctg) }, { "deliver_emergency_signal", VCPU_STAT(deliver_emergency_signal) }, { "deliver_external_call", VCPU_STAT(deliver_external_call) }, { "deliver_service_signal", VCPU_STAT(deliver_service_signal) }, diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index dc506f3782ea..5f00fc1e9785 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -147,6 +147,7 @@ int kvm_s390_handle_e5(struct kvm_vcpu *vcpu); int kvm_s390_handle_01(struct kvm_vcpu *vcpu); int kvm_s390_handle_b9(struct kvm_vcpu *vcpu); int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu); +int kvm_s390_handle_stctl(struct kvm_vcpu *vcpu); int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu); int kvm_s390_handle_eb(struct kvm_vcpu *vcpu); diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 5fb503a6c443..27f9051a78f8 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -789,6 +789,42 @@ int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu) return 0; } +int kvm_s390_handle_stctl(struct kvm_vcpu *vcpu) +{ + int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; + int reg3 = vcpu->arch.sie_block->ipa & 0x000f; + u64 ga; + u32 val; + int reg, rc; + + vcpu->stat.instruction_stctl++; + + if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) + return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); + + ga = kvm_s390_get_base_disp_rs(vcpu); + + if (ga & 3) + return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); + + VCPU_EVENT(vcpu, 5, "stctl r1:%x, r3:%x, addr:%llx", reg1, reg3, ga); + trace_kvm_s390_handle_stctl(vcpu, 0, reg1, reg3, ga); + + reg = reg1; + do { + val = vcpu->arch.sie_block->gcr[reg] & 0x00000000fffffffful; + rc = write_guest(vcpu, ga, &val, sizeof(val)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); + ga += 4; + if (reg == reg3) + break; + reg = (reg + 1) % 16; + } while (1); + + return 0; +} + static int handle_lctlg(struct kvm_vcpu *vcpu) { int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; @@ -825,8 +861,45 @@ static int handle_lctlg(struct kvm_vcpu *vcpu) return 0; } +static int handle_stctg(struct kvm_vcpu *vcpu) +{ + int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; + int reg3 = vcpu->arch.sie_block->ipa & 0x000f; + u64 ga, val; + int reg, rc; + + vcpu->stat.instruction_stctg++; + + if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE) + return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP); + + ga = kvm_s390_get_base_disp_rsy(vcpu); + + if (ga & 7) + return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); + + reg = reg1; + + VCPU_EVENT(vcpu, 5, "stctg r1:%x, r3:%x, addr:%llx", reg1, reg3, ga); + trace_kvm_s390_handle_stctl(vcpu, 1, reg1, reg3, ga); + + do { + val = vcpu->arch.sie_block->gcr[reg]; + rc = write_guest(vcpu, ga, &val, sizeof(val)); + if (rc) + return kvm_s390_inject_prog_cond(vcpu, rc); + ga += 8; + if (reg == reg3) + break; + reg = (reg + 1) % 16; + } while (1); + + return 0; +} + static const intercept_handler_t eb_handlers[256] = { [0x2f] = handle_lctlg, + [0x25] = handle_stctg, }; int kvm_s390_handle_eb(struct kvm_vcpu *vcpu) diff --git a/arch/s390/kvm/trace.h b/arch/s390/kvm/trace.h index a4bf7d78a0db..abf6ba52769e 100644 --- a/arch/s390/kvm/trace.h +++ b/arch/s390/kvm/trace.h @@ -315,6 +315,31 @@ TRACE_EVENT(kvm_s390_handle_lctl, __entry->reg1, __entry->reg3, __entry->addr) ); +TRACE_EVENT(kvm_s390_handle_stctl, + TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr), + TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr), + + TP_STRUCT__entry( + VCPU_FIELD_COMMON + __field(int, g) + __field(int, reg1) + __field(int, reg3) + __field(u64, addr) + ), + + TP_fast_assign( + VCPU_ASSIGN_COMMON + __entry->g = g; + __entry->reg1 = reg1; + __entry->reg3 = reg3; + __entry->addr = addr; + ), + + VCPU_TP_PRINTK("%s: storing cr %x-%x to %016llx", + __entry->g ? "stctg" : "stctl", + __entry->reg1, __entry->reg3, __entry->addr) + ); + TRACE_EVENT(kvm_s390_handle_prefix, TP_PROTO(VCPU_PROTO_COMMON, int set, u32 address), TP_ARGS(VCPU_ARGS_COMMON, set, address), -- cgit v1.2.3 From af1827e773c983f1d601d674447aea89efdb1acb Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 23 Jan 2014 11:03:51 +0100 Subject: KVM: s390: kernel header addition for guest debugging This patch adds the structs to the kernel headers needed to pass information from/to userspace in order to debug a guest on s390 with hardware support. Signed-off-by: David Hildenbrand Signed-off-by: Christian Borntraeger --- arch/s390/include/uapi/asm/kvm.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/s390/include/uapi/asm/kvm.h b/arch/s390/include/uapi/asm/kvm.h index e35c79821d29..b8c0f07a0e08 100644 --- a/arch/s390/include/uapi/asm/kvm.h +++ b/arch/s390/include/uapi/asm/kvm.h @@ -79,11 +79,31 @@ struct kvm_fpu { __u64 fprs[16]; }; +#define KVM_GUESTDBG_USE_HW_BP 0x00010000 + +#define KVM_HW_BP 1 +#define KVM_HW_WP_WRITE 2 +#define KVM_SINGLESTEP 4 + struct kvm_debug_exit_arch { + __u64 addr; + __u8 type; + __u8 pad[7]; /* Should be set to 0 */ +}; + +struct kvm_hw_breakpoint { + __u64 addr; + __u64 phys_addr; + __u64 len; + __u8 type; + __u8 pad[7]; /* Should be set to 0 */ }; /* for KVM_SET_GUEST_DEBUG */ struct kvm_guest_debug_arch { + __u32 nr_hw_bp; + __u32 pad; /* Should be set to 0 */ + struct kvm_hw_breakpoint __user *hw_bp; }; #define KVM_SYNC_PREFIX (1UL << 0) -- cgit v1.2.3 From 27291e2165b6de70c476b7b675308113edd69a60 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 23 Jan 2014 12:26:52 +0100 Subject: KVM: s390: hardware support for guest debugging This patch adds support to debug the guest using the PER facility on s390. Single-stepping, hardware breakpoints and hardware watchpoints are supported. In order to use the PER facility of the guest without it noticing it, the control registers of the guest have to be patched and access to them has to be intercepted(stctl, stctg, lctl, lctlg). All PER program interrupts have to be intercepted and only the relevant PER interrupts for the guest have to be given back. Special care has to be taken about repeated exits on the same hardware breakpoint. The intervention of the host in the guests PER configuration is not fully transparent. PER instruction nullification can not be used by the guest and too many storage alteration events may be reported to the guest (if it is activated for special address ranges only) when the host concurrently debugging it. Signed-off-by: David Hildenbrand Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 53 ++++- arch/s390/include/uapi/asm/kvm.h | 1 + arch/s390/kvm/Makefile | 2 +- arch/s390/kvm/guestdbg.c | 479 +++++++++++++++++++++++++++++++++++++++ arch/s390/kvm/intercept.c | 9 + arch/s390/kvm/interrupt.c | 8 +- arch/s390/kvm/kvm-s390.c | 53 ++++- arch/s390/kvm/kvm-s390.h | 10 + 8 files changed, 607 insertions(+), 8 deletions(-) create mode 100644 arch/s390/kvm/guestdbg.c (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index 5d9648925a8e..0d45f6fe734f 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -93,13 +93,18 @@ struct kvm_s390_sie_block { __u8 reserved40[4]; /* 0x0040 */ #define LCTL_CR0 0x8000 #define LCTL_CR6 0x0200 +#define LCTL_CR9 0x0040 +#define LCTL_CR10 0x0020 +#define LCTL_CR11 0x0010 #define LCTL_CR14 0x0002 __u16 lctl; /* 0x0044 */ __s16 icpua; /* 0x0046 */ -#define ICTL_LPSW 0x00400000 -#define ICTL_ISKE 0x00004000 -#define ICTL_SSKE 0x00002000 -#define ICTL_RRBE 0x00001000 +#define ICTL_PINT 0x20000000 +#define ICTL_LPSW 0x00400000 +#define ICTL_STCTL 0x00040000 +#define ICTL_ISKE 0x00004000 +#define ICTL_SSKE 0x00002000 +#define ICTL_RRBE 0x00001000 __u32 ictl; /* 0x0048 */ __u32 eca; /* 0x004c */ #define ICPT_INST 0x04 @@ -306,6 +311,45 @@ struct kvm_s390_float_interrupt { unsigned int irq_count; }; +struct kvm_hw_wp_info_arch { + unsigned long addr; + unsigned long phys_addr; + int len; + char *old_data; +}; + +struct kvm_hw_bp_info_arch { + unsigned long addr; + int len; +}; + +/* + * Only the upper 16 bits of kvm_guest_debug->control are arch specific. + * Further KVM_GUESTDBG flags which an be used from userspace can be found in + * arch/s390/include/uapi/asm/kvm.h + */ +#define KVM_GUESTDBG_EXIT_PENDING 0x10000000 + +#define guestdbg_enabled(vcpu) \ + (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) +#define guestdbg_sstep_enabled(vcpu) \ + (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) +#define guestdbg_hw_bp_enabled(vcpu) \ + (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) +#define guestdbg_exit_pending(vcpu) (guestdbg_enabled(vcpu) && \ + (vcpu->guest_debug & KVM_GUESTDBG_EXIT_PENDING)) + +struct kvm_guestdbg_info_arch { + unsigned long cr0; + unsigned long cr9; + unsigned long cr10; + unsigned long cr11; + struct kvm_hw_bp_info_arch *hw_bp_info; + struct kvm_hw_wp_info_arch *hw_wp_info; + int nr_hw_bp; + int nr_hw_wp; + unsigned long last_bp; +}; struct kvm_vcpu_arch { struct kvm_s390_sie_block *sie_block; @@ -321,6 +365,7 @@ struct kvm_vcpu_arch { u64 stidp_data; }; struct gmap *gmap; + struct kvm_guestdbg_info_arch guestdbg; #define KVM_S390_PFAULT_TOKEN_INVALID (-1UL) unsigned long pfault_token; unsigned long pfault_select; diff --git a/arch/s390/include/uapi/asm/kvm.h b/arch/s390/include/uapi/asm/kvm.h index b8c0f07a0e08..0fc26430a1e5 100644 --- a/arch/s390/include/uapi/asm/kvm.h +++ b/arch/s390/include/uapi/asm/kvm.h @@ -15,6 +15,7 @@ #include #define __KVM_S390 +#define __KVM_HAVE_GUEST_DEBUG /* Device control API: s390-specific devices */ #define KVM_DEV_FLIC_GET_ALL_IRQS 1 diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile index 83a7a355befe..b3b553469650 100644 --- a/arch/s390/kvm/Makefile +++ b/arch/s390/kvm/Makefile @@ -12,6 +12,6 @@ common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o $(KVM)/async_pf.o $(KVM)/irqch ccflags-y := -Ivirt/kvm -Iarch/s390/kvm kvm-objs := $(common-objs) kvm-s390.o intercept.o interrupt.o priv.o sigp.o -kvm-objs += diag.o gaccess.o +kvm-objs += diag.o gaccess.o guestdbg.o obj-$(CONFIG_KVM) += kvm.o diff --git a/arch/s390/kvm/guestdbg.c b/arch/s390/kvm/guestdbg.c new file mode 100644 index 000000000000..100e99d1030d --- /dev/null +++ b/arch/s390/kvm/guestdbg.c @@ -0,0 +1,479 @@ +/* + * kvm guest debug support + * + * Copyright IBM Corp. 2014 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License (version 2 only) + * as published by the Free Software Foundation. + * + * Author(s): David Hildenbrand + */ +#include +#include +#include "kvm-s390.h" +#include "gaccess.h" + +/* + * Extends the address range given by *start and *stop to include the address + * range starting with estart and the length len. Takes care of overflowing + * intervals and tries to minimize the overall intervall size. + */ +static void extend_address_range(u64 *start, u64 *stop, u64 estart, int len) +{ + u64 estop; + + if (len > 0) + len--; + else + len = 0; + + estop = estart + len; + + /* 0-0 range represents "not set" */ + if ((*start == 0) && (*stop == 0)) { + *start = estart; + *stop = estop; + } else if (*start <= *stop) { + /* increase the existing range */ + if (estart < *start) + *start = estart; + if (estop > *stop) + *stop = estop; + } else { + /* "overflowing" interval, whereby *stop > *start */ + if (estart <= *stop) { + if (estop > *stop) + *stop = estop; + } else if (estop > *start) { + if (estart < *start) + *start = estart; + } + /* minimize the range */ + else if ((estop - *stop) < (*start - estart)) + *stop = estop; + else + *start = estart; + } +} + +#define MAX_INST_SIZE 6 + +static void enable_all_hw_bp(struct kvm_vcpu *vcpu) +{ + unsigned long start, len; + u64 *cr9 = &vcpu->arch.sie_block->gcr[9]; + u64 *cr10 = &vcpu->arch.sie_block->gcr[10]; + u64 *cr11 = &vcpu->arch.sie_block->gcr[11]; + int i; + + if (vcpu->arch.guestdbg.nr_hw_bp <= 0 || + vcpu->arch.guestdbg.hw_bp_info == NULL) + return; + + /* + * If the guest is not interrested in branching events, we can savely + * limit them to the PER address range. + */ + if (!(*cr9 & PER_EVENT_BRANCH)) + *cr9 |= PER_CONTROL_BRANCH_ADDRESS; + *cr9 |= PER_EVENT_IFETCH | PER_EVENT_BRANCH; + + for (i = 0; i < vcpu->arch.guestdbg.nr_hw_bp; i++) { + start = vcpu->arch.guestdbg.hw_bp_info[i].addr; + len = vcpu->arch.guestdbg.hw_bp_info[i].len; + + /* + * The instruction in front of the desired bp has to + * report instruction-fetching events + */ + if (start < MAX_INST_SIZE) { + len += start; + start = 0; + } else { + start -= MAX_INST_SIZE; + len += MAX_INST_SIZE; + } + + extend_address_range(cr10, cr11, start, len); + } +} + +static void enable_all_hw_wp(struct kvm_vcpu *vcpu) +{ + unsigned long start, len; + u64 *cr9 = &vcpu->arch.sie_block->gcr[9]; + u64 *cr10 = &vcpu->arch.sie_block->gcr[10]; + u64 *cr11 = &vcpu->arch.sie_block->gcr[11]; + int i; + + if (vcpu->arch.guestdbg.nr_hw_wp <= 0 || + vcpu->arch.guestdbg.hw_wp_info == NULL) + return; + + /* if host uses storage alternation for special address + * spaces, enable all events and give all to the guest */ + if (*cr9 & PER_EVENT_STORE && *cr9 & PER_CONTROL_ALTERATION) { + *cr9 &= ~PER_CONTROL_ALTERATION; + *cr10 = 0; + *cr11 = PSW_ADDR_INSN; + } else { + *cr9 &= ~PER_CONTROL_ALTERATION; + *cr9 |= PER_EVENT_STORE; + + for (i = 0; i < vcpu->arch.guestdbg.nr_hw_wp; i++) { + start = vcpu->arch.guestdbg.hw_wp_info[i].addr; + len = vcpu->arch.guestdbg.hw_wp_info[i].len; + + extend_address_range(cr10, cr11, start, len); + } + } +} + +void kvm_s390_backup_guest_per_regs(struct kvm_vcpu *vcpu) +{ + vcpu->arch.guestdbg.cr0 = vcpu->arch.sie_block->gcr[0]; + vcpu->arch.guestdbg.cr9 = vcpu->arch.sie_block->gcr[9]; + vcpu->arch.guestdbg.cr10 = vcpu->arch.sie_block->gcr[10]; + vcpu->arch.guestdbg.cr11 = vcpu->arch.sie_block->gcr[11]; +} + +void kvm_s390_restore_guest_per_regs(struct kvm_vcpu *vcpu) +{ + vcpu->arch.sie_block->gcr[0] = vcpu->arch.guestdbg.cr0; + vcpu->arch.sie_block->gcr[9] = vcpu->arch.guestdbg.cr9; + vcpu->arch.sie_block->gcr[10] = vcpu->arch.guestdbg.cr10; + vcpu->arch.sie_block->gcr[11] = vcpu->arch.guestdbg.cr11; +} + +void kvm_s390_patch_guest_per_regs(struct kvm_vcpu *vcpu) +{ + /* + * TODO: if guest psw has per enabled, otherwise 0s! + * This reduces the amount of reported events. + * Need to intercept all psw changes! + */ + + if (guestdbg_sstep_enabled(vcpu)) { + vcpu->arch.sie_block->gcr[9] |= PER_EVENT_IFETCH; + vcpu->arch.sie_block->gcr[10] = 0; + vcpu->arch.sie_block->gcr[11] = PSW_ADDR_INSN; + } + + if (guestdbg_hw_bp_enabled(vcpu)) { + enable_all_hw_bp(vcpu); + enable_all_hw_wp(vcpu); + } + + /* TODO: Instruction-fetching-nullification not allowed for now */ + if (vcpu->arch.sie_block->gcr[9] & PER_EVENT_NULLIFICATION) + vcpu->arch.sie_block->gcr[9] &= ~PER_EVENT_NULLIFICATION; +} + +#define MAX_WP_SIZE 100 + +static int __import_wp_info(struct kvm_vcpu *vcpu, + struct kvm_hw_breakpoint *bp_data, + struct kvm_hw_wp_info_arch *wp_info) +{ + int ret = 0; + wp_info->len = bp_data->len; + wp_info->addr = bp_data->addr; + wp_info->phys_addr = bp_data->phys_addr; + wp_info->old_data = NULL; + + if (wp_info->len < 0 || wp_info->len > MAX_WP_SIZE) + return -EINVAL; + + wp_info->old_data = kmalloc(bp_data->len, GFP_KERNEL); + if (!wp_info->old_data) + return -ENOMEM; + /* try to backup the original value */ + ret = read_guest(vcpu, wp_info->phys_addr, wp_info->old_data, + wp_info->len); + if (ret) { + kfree(wp_info->old_data); + wp_info->old_data = NULL; + } + + return ret; +} + +#define MAX_BP_COUNT 50 + +int kvm_s390_import_bp_data(struct kvm_vcpu *vcpu, + struct kvm_guest_debug *dbg) +{ + int ret = 0, nr_wp = 0, nr_bp = 0, i, size; + struct kvm_hw_breakpoint *bp_data = NULL; + struct kvm_hw_wp_info_arch *wp_info = NULL; + struct kvm_hw_bp_info_arch *bp_info = NULL; + + if (dbg->arch.nr_hw_bp <= 0 || !dbg->arch.hw_bp) + return 0; + else if (dbg->arch.nr_hw_bp > MAX_BP_COUNT) + return -EINVAL; + + size = dbg->arch.nr_hw_bp * sizeof(struct kvm_hw_breakpoint); + bp_data = kmalloc(size, GFP_KERNEL); + if (!bp_data) { + ret = -ENOMEM; + goto error; + } + + ret = copy_from_user(bp_data, dbg->arch.hw_bp, size); + if (ret) + goto error; + + for (i = 0; i < dbg->arch.nr_hw_bp; i++) { + switch (bp_data[i].type) { + case KVM_HW_WP_WRITE: + nr_wp++; + break; + case KVM_HW_BP: + nr_bp++; + break; + default: + break; + } + } + + size = nr_wp * sizeof(struct kvm_hw_wp_info_arch); + if (size > 0) { + wp_info = kmalloc(size, GFP_KERNEL); + if (!wp_info) { + ret = -ENOMEM; + goto error; + } + } + size = nr_bp * sizeof(struct kvm_hw_bp_info_arch); + if (size > 0) { + bp_info = kmalloc(size, GFP_KERNEL); + if (!bp_info) { + ret = -ENOMEM; + goto error; + } + } + + for (nr_wp = 0, nr_bp = 0, i = 0; i < dbg->arch.nr_hw_bp; i++) { + switch (bp_data[i].type) { + case KVM_HW_WP_WRITE: + ret = __import_wp_info(vcpu, &bp_data[i], + &wp_info[nr_wp]); + if (ret) + goto error; + nr_wp++; + break; + case KVM_HW_BP: + bp_info[nr_bp].len = bp_data[i].len; + bp_info[nr_bp].addr = bp_data[i].addr; + nr_bp++; + break; + } + } + + vcpu->arch.guestdbg.nr_hw_bp = nr_bp; + vcpu->arch.guestdbg.hw_bp_info = bp_info; + vcpu->arch.guestdbg.nr_hw_wp = nr_wp; + vcpu->arch.guestdbg.hw_wp_info = wp_info; + return 0; +error: + kfree(bp_data); + kfree(wp_info); + kfree(bp_info); + return ret; +} + +void kvm_s390_clear_bp_data(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_hw_wp_info_arch *hw_wp_info = NULL; + + for (i = 0; i < vcpu->arch.guestdbg.nr_hw_wp; i++) { + hw_wp_info = &vcpu->arch.guestdbg.hw_wp_info[i]; + kfree(hw_wp_info->old_data); + hw_wp_info->old_data = NULL; + } + kfree(vcpu->arch.guestdbg.hw_wp_info); + vcpu->arch.guestdbg.hw_wp_info = NULL; + + kfree(vcpu->arch.guestdbg.hw_bp_info); + vcpu->arch.guestdbg.hw_bp_info = NULL; + + vcpu->arch.guestdbg.nr_hw_wp = 0; + vcpu->arch.guestdbg.nr_hw_bp = 0; +} + +static inline int in_addr_range(u64 addr, u64 a, u64 b) +{ + if (a <= b) + return (addr >= a) && (addr <= b); + else + /* "overflowing" interval */ + return (addr <= a) && (addr >= b); +} + +#define end_of_range(bp_info) (bp_info->addr + bp_info->len - 1) + +static struct kvm_hw_bp_info_arch *find_hw_bp(struct kvm_vcpu *vcpu, + unsigned long addr) +{ + struct kvm_hw_bp_info_arch *bp_info = vcpu->arch.guestdbg.hw_bp_info; + int i; + + if (vcpu->arch.guestdbg.nr_hw_bp == 0) + return NULL; + + for (i = 0; i < vcpu->arch.guestdbg.nr_hw_bp; i++) { + /* addr is directly the start or in the range of a bp */ + if (addr == bp_info->addr) + goto found; + if (bp_info->len > 0 && + in_addr_range(addr, bp_info->addr, end_of_range(bp_info))) + goto found; + + bp_info++; + } + + return NULL; +found: + return bp_info; +} + +static struct kvm_hw_wp_info_arch *any_wp_changed(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_hw_wp_info_arch *wp_info = NULL; + void *temp = NULL; + + if (vcpu->arch.guestdbg.nr_hw_wp == 0) + return NULL; + + for (i = 0; i < vcpu->arch.guestdbg.nr_hw_wp; i++) { + wp_info = &vcpu->arch.guestdbg.hw_wp_info[i]; + if (!wp_info || !wp_info->old_data || wp_info->len <= 0) + continue; + + temp = kmalloc(wp_info->len, GFP_KERNEL); + if (!temp) + continue; + + /* refetch the wp data and compare it to the old value */ + if (!read_guest(vcpu, wp_info->phys_addr, temp, + wp_info->len)) { + if (memcmp(temp, wp_info->old_data, wp_info->len)) { + kfree(temp); + return wp_info; + } + } + kfree(temp); + temp = NULL; + } + + return NULL; +} + +void kvm_s390_prepare_debug_exit(struct kvm_vcpu *vcpu) +{ + vcpu->run->exit_reason = KVM_EXIT_DEBUG; + vcpu->guest_debug &= ~KVM_GUESTDBG_EXIT_PENDING; +} + +#define per_bp_event(code) \ + (code & (PER_EVENT_IFETCH | PER_EVENT_BRANCH)) +#define per_write_wp_event(code) \ + (code & (PER_EVENT_STORE | PER_EVENT_STORE_REAL)) + +static int debug_exit_required(struct kvm_vcpu *vcpu) +{ + u32 perc = (vcpu->arch.sie_block->perc << 24); + struct kvm_debug_exit_arch *debug_exit = &vcpu->run->debug.arch; + struct kvm_hw_wp_info_arch *wp_info = NULL; + struct kvm_hw_bp_info_arch *bp_info = NULL; + unsigned long addr = vcpu->arch.sie_block->gpsw.addr; + unsigned long peraddr = vcpu->arch.sie_block->peraddr; + + if (guestdbg_hw_bp_enabled(vcpu)) { + if (per_write_wp_event(perc) && + vcpu->arch.guestdbg.nr_hw_wp > 0) { + wp_info = any_wp_changed(vcpu); + if (wp_info) { + debug_exit->addr = wp_info->addr; + debug_exit->type = KVM_HW_WP_WRITE; + goto exit_required; + } + } + if (per_bp_event(perc) && + vcpu->arch.guestdbg.nr_hw_bp > 0) { + bp_info = find_hw_bp(vcpu, addr); + /* remove duplicate events if PC==PER address */ + if (bp_info && (addr != peraddr)) { + debug_exit->addr = addr; + debug_exit->type = KVM_HW_BP; + vcpu->arch.guestdbg.last_bp = addr; + goto exit_required; + } + /* breakpoint missed */ + bp_info = find_hw_bp(vcpu, peraddr); + if (bp_info && vcpu->arch.guestdbg.last_bp != peraddr) { + debug_exit->addr = peraddr; + debug_exit->type = KVM_HW_BP; + goto exit_required; + } + } + } + if (guestdbg_sstep_enabled(vcpu) && per_bp_event(perc)) { + debug_exit->addr = addr; + debug_exit->type = KVM_SINGLESTEP; + goto exit_required; + } + + return 0; +exit_required: + return 1; +} + +#define guest_per_enabled(vcpu) \ + (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PER) + +static void filter_guest_per_event(struct kvm_vcpu *vcpu) +{ + u32 perc = vcpu->arch.sie_block->perc << 24; + u64 peraddr = vcpu->arch.sie_block->peraddr; + u64 addr = vcpu->arch.sie_block->gpsw.addr; + u64 cr9 = vcpu->arch.sie_block->gcr[9]; + u64 cr10 = vcpu->arch.sie_block->gcr[10]; + u64 cr11 = vcpu->arch.sie_block->gcr[11]; + /* filter all events, demanded by the guest */ + u32 guest_perc = perc & cr9 & PER_EVENT_MASK; + + if (!guest_per_enabled(vcpu)) + guest_perc = 0; + + /* filter "successful-branching" events */ + if (guest_perc & PER_EVENT_BRANCH && + cr9 & PER_CONTROL_BRANCH_ADDRESS && + !in_addr_range(addr, cr10, cr11)) + guest_perc &= ~PER_EVENT_BRANCH; + + /* filter "instruction-fetching" events */ + if (guest_perc & PER_EVENT_IFETCH && + !in_addr_range(peraddr, cr10, cr11)) + guest_perc &= ~PER_EVENT_IFETCH; + + /* All other PER events will be given to the guest */ + /* TODO: Check alterated address/address space */ + + vcpu->arch.sie_block->perc = guest_perc >> 24; + + if (!guest_perc) + vcpu->arch.sie_block->iprcc &= ~PGM_PER; +} + +void kvm_s390_handle_per_event(struct kvm_vcpu *vcpu) +{ + if (debug_exit_required(vcpu)) + vcpu->guest_debug |= KVM_GUESTDBG_EXIT_PENDING; + + filter_guest_per_event(vcpu); +} diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index c0e6b49191ba..f61c800a2d2c 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -170,6 +170,8 @@ static void __extract_prog_irq(struct kvm_vcpu *vcpu, } } +#define per_event(vcpu) (vcpu->arch.sie_block->iprcc & PGM_PER) + static int handle_prog(struct kvm_vcpu *vcpu) { struct kvm_s390_pgm_info pgm_info; @@ -178,6 +180,13 @@ static int handle_prog(struct kvm_vcpu *vcpu) vcpu->stat.exit_program_interruption++; + if (guestdbg_enabled(vcpu) && per_event(vcpu)) { + kvm_s390_handle_per_event(vcpu); + /* the interrupt might have been filtered out completely */ + if (vcpu->arch.sie_block->iprcc == 0) + return 0; + } + /* Restore ITDB to Program-Interruption TDB in guest memory */ if (!IS_TE_ENABLED(vcpu) || !IS_ITDB_VALID(vcpu)) goto skip_itdb; diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index c49b4d4d310a..f331014dd766 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -131,7 +131,13 @@ static void __reset_intercept_indicators(struct kvm_vcpu *vcpu) CPUSTAT_IO_INT | CPUSTAT_EXT_INT | CPUSTAT_STOP_INT, &vcpu->arch.sie_block->cpuflags); vcpu->arch.sie_block->lctl = 0x0000; - vcpu->arch.sie_block->ictl &= ~ICTL_LPSW; + vcpu->arch.sie_block->ictl &= ~(ICTL_LPSW | ICTL_STCTL | ICTL_PINT); + + if (guestdbg_enabled(vcpu)) { + vcpu->arch.sie_block->lctl |= (LCTL_CR0 | LCTL_CR9 | + LCTL_CR10 | LCTL_CR11); + vcpu->arch.sie_block->ictl |= (ICTL_STCTL | ICTL_PINT); + } } static void __set_cpuflag(struct kvm_vcpu *vcpu, u32 flag) diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 7ae8c26065fb..e6bbfe1a9474 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -934,10 +934,40 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, return -EINVAL; /* not implemented yet */ } +#define VALID_GUESTDBG_FLAGS (KVM_GUESTDBG_SINGLESTEP | \ + KVM_GUESTDBG_USE_HW_BP | \ + KVM_GUESTDBG_ENABLE) + int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) { - return -EINVAL; /* not implemented yet */ + int rc = 0; + + vcpu->guest_debug = 0; + kvm_s390_clear_bp_data(vcpu); + + if (vcpu->guest_debug & ~VALID_GUESTDBG_FLAGS) + return -EINVAL; + + if (dbg->control & KVM_GUESTDBG_ENABLE) { + vcpu->guest_debug = dbg->control; + /* enforce guest PER */ + atomic_set_mask(CPUSTAT_P, &vcpu->arch.sie_block->cpuflags); + + if (dbg->control & KVM_GUESTDBG_USE_HW_BP) + rc = kvm_s390_import_bp_data(vcpu, dbg); + } else { + atomic_clear_mask(CPUSTAT_P, &vcpu->arch.sie_block->cpuflags); + vcpu->arch.guestdbg.last_bp = 0; + } + + if (rc) { + vcpu->guest_debug = 0; + kvm_s390_clear_bp_data(vcpu); + atomic_clear_mask(CPUSTAT_P, &vcpu->arch.sie_block->cpuflags); + } + + return rc; } int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, @@ -1095,6 +1125,11 @@ static int vcpu_pre_run(struct kvm_vcpu *vcpu) if (rc) return rc; + if (guestdbg_enabled(vcpu)) { + kvm_s390_backup_guest_per_regs(vcpu); + kvm_s390_patch_guest_per_regs(vcpu); + } + vcpu->arch.sie_block->icptcode = 0; cpuflags = atomic_read(&vcpu->arch.sie_block->cpuflags); VCPU_EVENT(vcpu, 6, "entering sie flags %x", cpuflags); @@ -1111,6 +1146,9 @@ static int vcpu_post_run(struct kvm_vcpu *vcpu, int exit_reason) vcpu->arch.sie_block->icptcode); trace_kvm_s390_sie_exit(vcpu, vcpu->arch.sie_block->icptcode); + if (guestdbg_enabled(vcpu)) + kvm_s390_restore_guest_per_regs(vcpu); + if (exit_reason >= 0) { rc = 0; } else if (kvm_is_ucontrol(vcpu->kvm)) { @@ -1176,7 +1214,7 @@ static int __vcpu_run(struct kvm_vcpu *vcpu) vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu); rc = vcpu_post_run(vcpu, exit_reason); - } while (!signal_pending(current) && !rc); + } while (!signal_pending(current) && !guestdbg_exit_pending(vcpu) && !rc); srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); return rc; @@ -1187,6 +1225,11 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) int rc; sigset_t sigsaved; + if (guestdbg_exit_pending(vcpu)) { + kvm_s390_prepare_debug_exit(vcpu); + return 0; + } + if (vcpu->sigset_active) sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); @@ -1199,6 +1242,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) case KVM_EXIT_S390_RESET: case KVM_EXIT_S390_UCONTROL: case KVM_EXIT_S390_TSCH: + case KVM_EXIT_DEBUG: break; default: BUG(); @@ -1224,6 +1268,11 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) rc = -EINTR; } + if (guestdbg_exit_pending(vcpu) && !rc) { + kvm_s390_prepare_debug_exit(vcpu); + rc = 0; + } + if (rc == -EOPNOTSUPP) { /* intercept cannot be handled in-kernel, prepare kvm-run */ kvm_run->exit_reason = KVM_EXIT_S390_SIEIC; diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 5f00fc1e9785..be8ae0d68ab6 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -211,4 +211,14 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); int psw_extint_disabled(struct kvm_vcpu *vcpu); void kvm_s390_destroy_adapters(struct kvm *kvm); +/* implemented in guestdbg.c */ +void kvm_s390_backup_guest_per_regs(struct kvm_vcpu *vcpu); +void kvm_s390_restore_guest_per_regs(struct kvm_vcpu *vcpu); +void kvm_s390_patch_guest_per_regs(struct kvm_vcpu *vcpu); +int kvm_s390_import_bp_data(struct kvm_vcpu *vcpu, + struct kvm_guest_debug *dbg); +void kvm_s390_clear_bp_data(struct kvm_vcpu *vcpu); +void kvm_s390_prepare_debug_exit(struct kvm_vcpu *vcpu); +void kvm_s390_handle_per_event(struct kvm_vcpu *vcpu); + #endif -- cgit v1.2.3 From bb78c5ec9161561586f8d81d53258b251aab324a Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Tue, 18 Mar 2014 10:03:26 +0100 Subject: KVM: s390: move timer interrupt checks into own functions This patch moves the checks for enabled timer (clock-comparator) interrupts and pending timer interrupts into own functions, making the code better readable and easier to maintain. The method kvm_cpu_has_pending_timer is filled with life. Signed-off-by: David Hildenbrand Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/interrupt.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index f331014dd766..0165f1b089ac 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -56,6 +56,14 @@ static int psw_interrupts_disabled(struct kvm_vcpu *vcpu) return 1; } +static int ckc_interrupts_enabled(struct kvm_vcpu *vcpu) +{ + if (psw_extint_disabled(vcpu) || + !(vcpu->arch.sie_block->gcr[0] & 0x800ul)) + return 0; + return 1; +} + static u64 int_word_to_isc_bits(u32 int_word) { u8 isc = (int_word & 0x38000000) >> 27; @@ -466,14 +474,10 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, } } -static int __try_deliver_ckc_interrupt(struct kvm_vcpu *vcpu) +static void deliver_ckc_interrupt(struct kvm_vcpu *vcpu) { int rc; - if (psw_extint_disabled(vcpu)) - return 0; - if (!(vcpu->arch.sie_block->gcr[0] & 0x800ul)) - return 0; rc = put_guest_lc(vcpu, 0x1004, (u16 __user *)__LC_EXT_INT_CODE); rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); @@ -485,7 +489,6 @@ static int __try_deliver_ckc_interrupt(struct kvm_vcpu *vcpu) "delivery, killing userspace\n"); do_exit(SIGKILL); } - return 1; } int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu) @@ -515,19 +518,20 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu) spin_unlock(&fi->lock); } - if ((!rc) && (vcpu->arch.sie_block->ckc < - get_tod_clock_fast() + vcpu->arch.sie_block->epoch)) { - if ((!psw_extint_disabled(vcpu)) && - (vcpu->arch.sie_block->gcr[0] & 0x800ul)) - rc = 1; - } + if (!rc && kvm_cpu_has_pending_timer(vcpu)) + rc = 1; return rc; } int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) { - return 0; + if (!(vcpu->arch.sie_block->ckc < + get_tod_clock_fast() + vcpu->arch.sie_block->epoch)) + return 0; + if (!ckc_interrupts_enabled(vcpu)) + return 0; + return 1; } int kvm_s390_handle_wait(struct kvm_vcpu *vcpu) @@ -550,8 +554,7 @@ int kvm_s390_handle_wait(struct kvm_vcpu *vcpu) return -EOPNOTSUPP; /* disabled wait */ } - if (psw_extint_disabled(vcpu) || - (!(vcpu->arch.sie_block->gcr[0] & 0x800ul))) { + if (!ckc_interrupts_enabled(vcpu)) { VCPU_EVENT(vcpu, 3, "%s", "enabled wait w/o timer"); goto no_timer; } @@ -663,9 +666,8 @@ void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu) } while (deliver); } - if ((vcpu->arch.sie_block->ckc < - get_tod_clock_fast() + vcpu->arch.sie_block->epoch)) - __try_deliver_ckc_interrupt(vcpu); + if (kvm_cpu_has_pending_timer(vcpu)) + deliver_ckc_interrupt(vcpu); if (atomic_read(&fi->active)) { do { -- cgit v1.2.3 From f71d0dc5084b4de761b5be1aef1a855136cecd15 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Tue, 18 Mar 2014 10:06:14 +0100 Subject: KVM: s390: no timer interrupts when single-stepping a guest When a guest is single-stepped, we want to disable timer interrupts. Otherwise, the guest will continuously execute the external interrupt handler and make debugging of code where timer interrupts are enabled almost impossible. The delivery of timer interrupts can be enforced in such sections by setting a breakpoint and continuing execution. In order to disable timer interrupts, they are disabled in the control register of the guest just before SIE entry and are suppressed in the interrupt check/delivery methods. Signed-off-by: David Hildenbrand Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/guestdbg.c | 2 ++ arch/s390/kvm/interrupt.c | 3 +++ 2 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/s390/kvm/guestdbg.c b/arch/s390/kvm/guestdbg.c index 100e99d1030d..757ccef62fd5 100644 --- a/arch/s390/kvm/guestdbg.c +++ b/arch/s390/kvm/guestdbg.c @@ -155,6 +155,8 @@ void kvm_s390_patch_guest_per_regs(struct kvm_vcpu *vcpu) */ if (guestdbg_sstep_enabled(vcpu)) { + /* disable timer (clock-comparator) interrupts */ + vcpu->arch.sie_block->gcr[0] &= ~0x800ul; vcpu->arch.sie_block->gcr[9] |= PER_EVENT_IFETCH; vcpu->arch.sie_block->gcr[10] = 0; vcpu->arch.sie_block->gcr[11] = PSW_ADDR_INSN; diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index 0165f1b089ac..d020c5f8eabb 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -61,6 +61,9 @@ static int ckc_interrupts_enabled(struct kvm_vcpu *vcpu) if (psw_extint_disabled(vcpu) || !(vcpu->arch.sie_block->gcr[0] & 0x800ul)) return 0; + if (guestdbg_enabled(vcpu) && guestdbg_sstep_enabled(vcpu)) + /* No timer interrupts when single stepping */ + return 0; return 1; } -- cgit v1.2.3 From 67335e63c9ef59e97b45a08b4a6a93767762031d Mon Sep 17 00:00:00 2001 From: Christian Borntraeger Date: Tue, 25 Mar 2014 17:09:08 +0100 Subject: KVM: s390: Drop pending interrupts on guest exit On hard exits (abort, sigkill) we have have some kvm_s390_interrupt_info structures hanging around. Delete those on exit to avoid memory leaks. Signed-off-by: Christian Borntraeger CC: stable@vger.kernel.org Reviewed-by: Thomas Huth --- arch/s390/kvm/interrupt.c | 4 ++-- arch/s390/kvm/kvm-s390.c | 2 ++ arch/s390/kvm/kvm-s390.h | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index d020c5f8eabb..077e4738ebdc 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -1045,7 +1045,7 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu, return 0; } -static void clear_floating_interrupts(struct kvm *kvm) +void kvm_s390_clear_float_irqs(struct kvm *kvm) { struct kvm_s390_float_interrupt *fi; struct kvm_s390_interrupt_info *n, *inti = NULL; @@ -1391,7 +1391,7 @@ static int flic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) break; case KVM_DEV_FLIC_CLEAR_IRQS: r = 0; - clear_floating_interrupts(dev->kvm); + kvm_s390_clear_float_irqs(dev->kvm); break; case KVM_DEV_FLIC_APF_ENABLE: dev->kvm->arch.gmap->pfault_enabled = 1; diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index e6bbfe1a9474..b32c42cbc706 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -471,6 +471,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) { VCPU_EVENT(vcpu, 3, "%s", "free cpu"); trace_kvm_s390_destroy_vcpu(vcpu->vcpu_id); + kvm_s390_clear_local_irqs(vcpu); kvm_clear_async_pf_completion_queue(vcpu); if (!kvm_is_ucontrol(vcpu->kvm)) { clear_bit(63 - vcpu->vcpu_id, @@ -520,6 +521,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm) if (!kvm_is_ucontrol(kvm)) gmap_free(kvm->arch.gmap); kvm_s390_destroy_adapters(kvm); + kvm_s390_clear_float_irqs(kvm); } /* Section: vcpu related */ diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index be8ae0d68ab6..c93ed5fabfbc 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -130,6 +130,7 @@ void kvm_s390_tasklet(unsigned long parm); void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu); void kvm_s390_deliver_pending_machine_checks(struct kvm_vcpu *vcpu); void kvm_s390_clear_local_irqs(struct kvm_vcpu *vcpu); +void kvm_s390_clear_float_irqs(struct kvm *kvm); int __must_check kvm_s390_inject_vm(struct kvm *kvm, struct kvm_s390_interrupt *s390int); int __must_check kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu, -- cgit v1.2.3 From a86dcc2482cf29ffcf6fbc174ce55e4f5f18cd8b Mon Sep 17 00:00:00 2001 From: Michael Mueller Date: Thu, 13 Mar 2014 19:29:09 +0100 Subject: KVM: s390: replace TDB_ADDR by __LC_PGM_TDB The generically assembled low core labels already contain the address for the TDB. Signed-off-by: Michael Mueller Acked-by: Christian Borntraeger Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/intercept.c | 3 ++- arch/s390/kvm/kvm-s390.h | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index f61c800a2d2c..f39160406efa 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -16,6 +16,7 @@ #include #include +#include #include "kvm-s390.h" #include "gaccess.h" @@ -193,7 +194,7 @@ static int handle_prog(struct kvm_vcpu *vcpu) if (current->thread.per_flags & PER_FLAG_NO_TE) goto skip_itdb; itdb = (struct kvm_s390_itdb *)vcpu->arch.sie_block->itdba; - rc = write_guest_lc(vcpu, TDB_ADDR, itdb, sizeof(*itdb)); + rc = write_guest_lc(vcpu, __LC_PGM_TDB, itdb, sizeof(*itdb)); if (rc) return rc; memset(itdb, 0, sizeof(*itdb)); diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index c93ed5fabfbc..9b5680d1f6cc 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -28,7 +28,6 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu); /* Transactional Memory Execution related macros */ #define IS_TE_ENABLED(vcpu) ((vcpu->arch.sie_block->ecb & 0x10)) -#define TDB_ADDR 0x1800UL #define TDB_FORMAT1 1 #define IS_ITDB_VALID(vcpu) ((*(char *)vcpu->arch.sie_block->itdba == TDB_FORMAT1)) -- cgit v1.2.3 From e325fe69aa37b485635521568651642791d6d140 Mon Sep 17 00:00:00 2001 From: Michael Mueller Date: Thu, 13 Mar 2014 12:16:45 +0100 Subject: KVM: s390: Factor out handle_itdb to handle TX aborts Factor out the new function handle_itdb(), which copies the ITDB into guest lowcore to fully handle a TX abort. Signed-off-by: Michael Mueller Acked-by: Christian Borntraeger Signed-off-by: Christian Borntraeger --- arch/s390/kvm/intercept.c | 38 ++++++++++++++++++++++++++------------ 1 file changed, 26 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index f39160406efa..30e1c5eb726a 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -171,12 +171,33 @@ static void __extract_prog_irq(struct kvm_vcpu *vcpu, } } +/* + * restore ITDB to program-interruption TDB in guest lowcore + * and set TX abort indication if required +*/ +static int handle_itdb(struct kvm_vcpu *vcpu) +{ + struct kvm_s390_itdb *itdb; + int rc; + + if (!IS_TE_ENABLED(vcpu) || !IS_ITDB_VALID(vcpu)) + return 0; + if (current->thread.per_flags & PER_FLAG_NO_TE) + return 0; + itdb = (struct kvm_s390_itdb *)vcpu->arch.sie_block->itdba; + rc = write_guest_lc(vcpu, __LC_PGM_TDB, itdb, sizeof(*itdb)); + if (rc) + return rc; + memset(itdb, 0, sizeof(*itdb)); + + return 0; +} + #define per_event(vcpu) (vcpu->arch.sie_block->iprcc & PGM_PER) static int handle_prog(struct kvm_vcpu *vcpu) { struct kvm_s390_pgm_info pgm_info; - struct kvm_s390_itdb *itdb; int rc; vcpu->stat.exit_program_interruption++; @@ -188,20 +209,13 @@ static int handle_prog(struct kvm_vcpu *vcpu) return 0; } - /* Restore ITDB to Program-Interruption TDB in guest memory */ - if (!IS_TE_ENABLED(vcpu) || !IS_ITDB_VALID(vcpu)) - goto skip_itdb; - if (current->thread.per_flags & PER_FLAG_NO_TE) - goto skip_itdb; - itdb = (struct kvm_s390_itdb *)vcpu->arch.sie_block->itdba; - rc = write_guest_lc(vcpu, __LC_PGM_TDB, itdb, sizeof(*itdb)); + trace_kvm_s390_intercept_prog(vcpu, vcpu->arch.sie_block->iprcc); + + rc = handle_itdb(vcpu); if (rc) return rc; - memset(itdb, 0, sizeof(*itdb)); -skip_itdb: - trace_kvm_s390_intercept_prog(vcpu, vcpu->arch.sie_block->iprcc); - __extract_prog_irq(vcpu, &pgm_info); + __extract_prog_irq(vcpu, &pgm_info); return kvm_s390_inject_prog_irq(vcpu, &pgm_info); } -- cgit v1.2.3 From eb171a997de8b746f4d52b23108d64e9f88f0a09 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 10 Apr 2014 15:52:46 +0200 Subject: ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch The A31 SoC has PL and PM banks and thus increase the default ARCH_NR_GPIO. Signed-off-by: Boris BREZILLON Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ab438cb5af55..a7bb61e31b69 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1645,9 +1645,9 @@ config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX + default 416 if ARCH_SUNXI default 392 if ARCH_U8500 default 352 if ARCH_VT8500 - default 288 if ARCH_SUNXI default 264 if MACH_H4700 default 0 help -- cgit v1.2.3 From 8cffcb0ca33381e07cee4ebe1301d0794054fc97 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 11:06:46 +0200 Subject: ARM: sun6i: a31: Add support for the High Speed Timers The Allwinner A31 has support for four high speed timers. Apart for the number of timers (4 vs 2), it's basically the same logic than the high speed timers found in the sun5i chips. Now that we have a driver to support it, we can enable them in the device tree. Signed-off-by: Maxime Ripard Signed-off-by: Daniel Lezcano --- arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index d45efa74827c..8cee8a15b90b 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -428,6 +428,17 @@ status = "disabled"; }; + timer@01c60000 { + compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; + reg = <0x01c60000 0x1000>; + interrupts = <0 51 4>, + <0 52 4>, + <0 53 4>, + <0 54 4>; + clocks = <&ahb1_gates 19>; + resets = <&ahb1_rst 19>; + }; + spi0: spi@01c68000 { compatible = "allwinner,sun6i-a31-spi"; reg = <0x01c68000 0x1000>; -- cgit v1.2.3 From 7cf2af90cd515bf27f1b7183f3d6f91b151990ed Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 14 Apr 2014 14:41:57 +0300 Subject: arm: common: edma: Save the number of event queues/TCs For later use save the number of queues available for the CC. Signed-off-by: Peter Ujfalusi Acked-by: Joel Fernandes Reviewed-and-Tested-by: Joel Fernandes Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 41bca32409fc..999266bf69b9 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -1768,6 +1768,9 @@ static int edma_probe(struct platform_device *pdev) map_queue_tc(j, queue_tc_mapping[i][0], queue_tc_mapping[i][1]); + /* Save the number of TCs */ + edma_cc[j]->num_tc = i; + /* Event queue priority mapping */ for (i = 0; queue_priority_mapping[i][0] != -1; i++) assign_priority_to_queue(j, -- cgit v1.2.3 From 232b223d8281d33820053bb711f91864b8612d8e Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Mon, 14 Apr 2014 14:42:00 +0300 Subject: dmaengine: edma: Set DMA_CYCLIC capability flag Indicate that the edma dmaengine driver has support for cyclic mode. Signed-off-by: Peter Ujfalusi Acked-by: Joel Fernandes Reviewed-and-Tested-by: Joel Fernandes Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 1 + drivers/dma/edma.c | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 999266bf69b9..0b37f7734d0f 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -1574,6 +1574,7 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, return ERR_PTR(ret); dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); + dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap); of_dma_controller_register(dev->of_node, of_dma_simple_xlate, &edma_filter_info); diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index 35db3f282bdb..eef51644b69f 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -893,6 +893,7 @@ static int edma_probe(struct platform_device *pdev) dma_cap_zero(ecc->dma_slave.cap_mask); dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); + dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); -- cgit v1.2.3 From 55400f3a1f89e39761f45c19f6e4235a329c400b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 22 Apr 2014 14:15:52 -0500 Subject: ARM: mvebu: clean-up unneeded kconfig selects Multi-platform support implies all these options are already selected and individual platforms don't need to select them. Signed-off-by: Rob Herring Cc: Jason Cooper Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth --- arch/arm/mach-mvebu/Kconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 3f73eecbcfb0..bfc5af18e483 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -3,7 +3,6 @@ config ARCH_MVEBU select ARCH_SUPPORTS_BIG_ENDIAN select CLKSRC_MMIO select GENERIC_IRQ_CHIP - select IRQ_DOMAIN select PINCTRL select PLAT_ORION select MVEBU_MBUS @@ -11,7 +10,6 @@ config ARCH_MVEBU select ARCH_REQUIRE_GPIOLIB select MIGHT_HAVE_PCI select PCI_QUIRKS if PCI - select OF_ADDRESS_PCI if ARCH_MVEBU @@ -38,7 +36,6 @@ config MACH_ARMADA_375 select ARM_ERRATA_753970 select ARM_GIC select ARMADA_375_CLK - select CPU_V7 select MACH_MVEBU_V7 select PINCTRL_ARMADA_375 help @@ -51,7 +48,6 @@ config MACH_ARMADA_38X select ARM_ERRATA_753970 select ARM_GIC select ARMADA_38X_CLK - select CPU_V7 select MACH_MVEBU_V7 select PINCTRL_ARMADA_38X help @@ -86,13 +82,11 @@ config MACH_KIRKWOOD select ARCH_REQUIRE_GPIOLIB select CPU_FEROCEON select KIRKWOOD_CLK - select OF_IRQ select ORION_IRQCHIP select ORION_TIMER select PCI select PCI_QUIRKS select PINCTRL_KIRKWOOD - select USE_OF help Say 'Y' here if you want your kernel to support boards based on the Marvell Kirkwood device tree. -- cgit v1.2.3 From 9f0db8b9c466e0e5f3bc86a1389c790ca16643a8 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 22 Apr 2014 14:29:01 -0500 Subject: ARM: bcm: clean-up unneeded kconfig selects Multi-platform support implies all these options are already selected and individual platforms don't need to select them. Signed-off-by: Rob Herring Cc: Christian Daudt Cc: Matt Porter Cc: bcm-kernel-feedback-list@broadcom.com --- arch/arm/mach-bcm/Kconfig | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 49c914cd9c7a..9f19636fea2f 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -11,7 +11,6 @@ menu "Broadcom SoC Selection" config ARCH_BCM_MOBILE bool "Broadcom Mobile SoC" if ARCH_MULTI_V7 - depends on MMU select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP @@ -33,10 +32,7 @@ config ARCH_BCM2835 select ARM_AMBA select ARM_ERRATA_411920 select ARM_TIMER_SP804 - select CLKDEV_LOOKUP select CLKSRC_OF - select CPU_V6 - select GENERIC_CLOCKEVENTS select PINCTRL select PINCTRL_BCM2835 help @@ -45,14 +41,10 @@ config ARCH_BCM2835 config ARCH_BCM_5301X bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7 - depends on MMU select ARM_GIC select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP - select HAVE_SMP - select COMMON_CLK - select GENERIC_CLOCKEVENTS select ARM_GLOBAL_TIMER select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK select MIGHT_HAVE_PCI -- cgit v1.2.3 From e7062b101537a0c4f4a8d725321772eb78100074 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 22 Apr 2014 14:29:01 -0500 Subject: ARM: qcom: clean-up unneeded kconfig selects Multi-platform support implies all these options are already selected and individual platforms don't need to select them. Signed-off-by: Rob Herring Cc: Kumar Gala Cc: David Brown Cc: linux-arm-msm@vger.kernel.org --- arch/arm/mach-qcom/Kconfig | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index a028be234334..6aa22147cace 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -3,8 +3,6 @@ config ARCH_QCOM select ARCH_REQUIRE_GPIOLIB select ARM_GIC select CLKSRC_OF - select GENERIC_CLOCKEVENTS - select HAVE_SMP select QCOM_SCM if SMP help Support for Qualcomm's devicetree based systems. -- cgit v1.2.3 From fd2a445a94d2ab6b39fb623dc02fee48d01a565a Mon Sep 17 00:00:00 2001 From: Huw Davies Date: Wed, 16 Apr 2014 10:02:51 +0100 Subject: KVM: VMX: Advance rip to after an ICEBP instruction When entering an exception after an ICEBP, the saved instruction pointer should point to after the instruction. This fixes the bug here: https://bugs.launchpad.net/qemu/+bug/1119686 Signed-off-by: Huw Davies Reviewed-by: Jan Kiszka Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/vmx.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index eb3f2b1b764c..8fb56e4cdf91 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -4841,6 +4841,9 @@ static int handle_exception(struct kvm_vcpu *vcpu) (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { vcpu->arch.dr6 &= ~15; vcpu->arch.dr6 |= dr6; + if (!(dr6 & ~DR6_RESERVED)) /* icebp */ + skip_emulated_instruction(vcpu); + kvm_queue_exception(vcpu, DB_VECTOR); return 1; } -- cgit v1.2.3 From 4b855078601fc422dbac3059f2215e776f49780f Mon Sep 17 00:00:00 2001 From: Bandan Das Date: Sat, 19 Apr 2014 18:17:44 -0400 Subject: KVM: nVMX: Don't advertise single context invalidation for invept For single context invalidation, we fall through to global invalidation in handle_invept() except for one case - when the operand supplied by L1 is different from what we have in vmcs12. However, typically hypervisors will only call invept for the currently loaded eptp, so the condition will never be true. Signed-off-by: Bandan Das Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/vmx.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 8fb56e4cdf91..f00a6e9021b0 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2353,12 +2353,11 @@ static __init void nested_vmx_setup_ctls_msrs(void) VMX_EPT_INVEPT_BIT; nested_vmx_ept_caps &= vmx_capability.ept; /* - * Since invept is completely emulated we support both global - * and context invalidation independent of what host cpu - * supports + * For nested guests, we don't do anything specific + * for single context invalidation. Hence, only advertise + * support for global context invalidation. */ - nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT | - VMX_EPT_EXTENT_CONTEXT_BIT; + nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT; } else nested_vmx_ept_caps = 0; @@ -6441,7 +6440,6 @@ static int handle_invept(struct kvm_vcpu *vcpu) struct { u64 eptp, gpa; } operand; - u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK; if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) || !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) { @@ -6481,16 +6479,13 @@ static int handle_invept(struct kvm_vcpu *vcpu) } switch (type) { - case VMX_EPT_EXTENT_CONTEXT: - if ((operand.eptp & eptp_mask) != - (nested_ept_get_cr3(vcpu) & eptp_mask)) - break; case VMX_EPT_EXTENT_GLOBAL: kvm_mmu_sync_roots(vcpu); kvm_mmu_flush_tlb(vcpu); nested_vmx_succeed(vcpu); break; default: + /* Trap single context invalidation invept calls */ BUG_ON(1); break; } -- cgit v1.2.3 From 77b0f5d67ff2781f36831cba79674c3e97bd7acf Mon Sep 17 00:00:00 2001 From: Bandan Das Date: Sat, 19 Apr 2014 18:17:45 -0400 Subject: KVM: nVMX: Ack and write vector info to intr_info if L1 asks us to This feature emulates the "Acknowledge interrupt on exit" behavior. We can safely emulate it for L1 to run L2 even if L0 itself has it disabled (to run L1). Signed-off-by: Bandan Das Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/irq.c | 1 + arch/x86/kvm/vmx.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c index 484bc874688b..bd0da433e6d7 100644 --- a/arch/x86/kvm/irq.c +++ b/arch/x86/kvm/irq.c @@ -113,6 +113,7 @@ int kvm_cpu_get_interrupt(struct kvm_vcpu *v) return kvm_get_apic_interrupt(v); /* APIC */ } +EXPORT_SYMBOL_GPL(kvm_cpu_get_interrupt); void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu) { diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index f00a6e9021b0..4378014a41a9 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -4526,6 +4526,16 @@ static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) PIN_BASED_EXT_INTR_MASK; } +/* + * In nested virtualization, check if L1 has set + * VM_EXIT_ACK_INTR_ON_EXIT + */ +static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu) +{ + return get_vmcs12(vcpu)->vm_exit_controls & + VM_EXIT_ACK_INTR_ON_EXIT; +} + static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu) { return get_vmcs12(vcpu)->pin_based_vm_exec_control & @@ -8563,6 +8573,14 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason, prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info, exit_qualification); + if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) + && nested_exit_intr_ack_set(vcpu)) { + int irq = kvm_cpu_get_interrupt(vcpu); + WARN_ON(irq < 0); + vmcs12->vm_exit_intr_info = irq | + INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR; + } + trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason, vmcs12->exit_qualification, vmcs12->idt_vectoring_info_field, -- cgit v1.2.3 From e0ba1a6ffcfe8dc95586943bbe56badb1459bf25 Mon Sep 17 00:00:00 2001 From: Bandan Das Date: Sat, 19 Apr 2014 18:17:46 -0400 Subject: KVM: nVMX: Advertise support for interrupt acknowledgement Some Type 1 hypervisors such as XEN won't enable VMX without it present Signed-off-by: Bandan Das Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/vmx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 4378014a41a9..72b8012991b9 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -2283,7 +2283,7 @@ static __init void nested_vmx_setup_ctls_msrs(void) rdmsr(MSR_IA32_VMX_EXIT_CTLS, nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high); nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR; - /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */ + nested_vmx_exit_ctls_high &= #ifdef CONFIG_X86_64 VM_EXIT_HOST_ADDR_SPACE_SIZE | @@ -2291,7 +2291,8 @@ static __init void nested_vmx_setup_ctls_msrs(void) VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT; nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR | VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER | - VM_EXIT_SAVE_VMX_PREEMPTION_TIMER; + VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT; + if (vmx_mpx_supported()) nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; -- cgit v1.2.3 From 603fb42a66499ab353466c7afa3d38beea20a8a9 Mon Sep 17 00:00:00 2001 From: Sebastian Capella Date: Tue, 25 Mar 2014 01:20:29 +0100 Subject: ARM: 8011/1: ARM hibernation / suspend-to-disk Enable hibernation for ARM architectures and provide ARM architecture specific calls used during hibernation. The swsusp hibernation framework depends on the platform first having functional suspend/resume. Then, in order to enable hibernation on a given platform, a platform_hibernation_ops structure may need to be registered with the system in order to save/restore any SoC-specific / cpu specific state needing (re)init over a suspend-to-disk/resume-from-disk cycle. For example: - "secure" SoCs that have different sets of control registers and/or different CR reg access patterns. - SoCs with L2 caches as the activation sequence there is SoC-dependent; a full off-on cycle for L2 is not done by the hibernation support code. - SoCs requiring steps on wakeup _before_ the "generic" parts done by cpu_suspend / cpu_resume can work correctly. - SoCs having persistent state which is maintained during suspend and resume, but will be lost during the power off cycle after suspend-to-disk. This is a rebase/rework of Frank Hofmann's v5 hibernation patchset. Acked-by: Russ Dill Cc: "Rafael J. Wysocki" Signed-off-by: Sebastian Capella Acked-by: Pavel Machek Reviewed-by: Lorenzo Pieralisi [fixed duplicate virt_to_pfn() definition --rmk] Signed-off-by: Russell King --- arch/arm/Kconfig | 5 +++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/hibernate.c | 107 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/suspend.h | 2 + 4 files changed, 115 insertions(+) create mode 100644 arch/arm/kernel/hibernate.c (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ab438cb5af55..58506175a3ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2294,6 +2294,11 @@ config ARCH_SUSPEND_POSSIBLE config ARM_CPU_SUSPEND def_bool PM_SLEEP +config ARCH_HIBERNATION_POSSIBLE + bool + depends on MMU + default y if ARCH_SUSPEND_POSSIBLE + endmenu source "net/Kconfig" diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index a766bcbaf8ad..10f0464206a2 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_ARTHUR) += arthur.o obj-$(CONFIG_ISA_DMA) += dma-isa.o obj-$(CONFIG_PCI) += bios32.o isa.o obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o +obj-$(CONFIG_HIBERNATION) += hibernate.o obj-$(CONFIG_SMP) += smp.o ifdef CONFIG_MMU obj-$(CONFIG_SMP) += smp_tlb.o diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c new file mode 100644 index 000000000000..bb8b79648643 --- /dev/null +++ b/arch/arm/kernel/hibernate.c @@ -0,0 +1,107 @@ +/* + * Hibernation support specific for ARM + * + * Derived from work on ARM hibernation support by: + * + * Ubuntu project, hibernation support for mach-dove + * Copyright (C) 2010 Nokia Corporation (Hiroshi Doyu) + * Copyright (C) 2010 Texas Instruments, Inc. (Teerth Reddy et al.) + * https://lkml.org/lkml/2010/6/18/4 + * https://lists.linux-foundation.org/pipermail/linux-pm/2010-June/027422.html + * https://patchwork.kernel.org/patch/96442/ + * + * Copyright (C) 2006 Rafael J. Wysocki + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include +#include +#include +#include +#include +#include + +extern const void __nosave_begin, __nosave_end; + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = virt_to_pfn(&__nosave_begin); + unsigned long nosave_end_pfn = virt_to_pfn(&__nosave_end - 1); + + return (pfn >= nosave_begin_pfn) && (pfn <= nosave_end_pfn); +} + +void notrace save_processor_state(void) +{ + WARN_ON(num_online_cpus() != 1); + local_fiq_disable(); +} + +void notrace restore_processor_state(void) +{ + local_fiq_enable(); +} + +/* + * Snapshot kernel memory and reset the system. + * + * swsusp_save() is executed in the suspend finisher so that the CPU + * context pointer and memory are part of the saved image, which is + * required by the resume kernel image to restart execution from + * swsusp_arch_suspend(). + * + * soft_restart is not technically needed, but is used to get success + * returned from cpu_suspend. + * + * When soft reboot completes, the hibernation snapshot is written out. + */ +static int notrace arch_save_image(unsigned long unused) +{ + int ret; + + ret = swsusp_save(); + if (ret == 0) + soft_restart(virt_to_phys(cpu_resume)); + return ret; +} + +/* + * Save the current CPU state before suspend / poweroff. + */ +int notrace swsusp_arch_suspend(void) +{ + return cpu_suspend(0, arch_save_image); +} + +/* + * Restore page contents for physical pages that were in use during loading + * hibernation image. Switch to idmap_pgd so the physical page tables + * are overwritten with the same contents. + */ +static void notrace arch_restore_image(void *unused) +{ + struct pbe *pbe; + + cpu_switch_mm(idmap_pgd, &init_mm); + for (pbe = restore_pblist; pbe; pbe = pbe->next) + copy_page(pbe->orig_address, pbe->address); + + soft_restart(virt_to_phys(cpu_resume)); +} + +static u64 resume_stack[PAGE_SIZE/2/sizeof(u64)] __nosavedata; + +/* + * Resume from the hibernation image. + * Due to the kernel heap / data restore, stack contents change underneath + * and that would make function calls impossible; switch to a temporary + * stack within the nosave region to avoid that problem. + */ +int swsusp_arch_resume(void) +{ + extern void call_with_stack(void (*fn)(void *), void *arg, void *sp); + call_with_stack(arch_restore_image, 0, + resume_stack + ARRAY_SIZE(resume_stack)); + return 0; +} diff --git a/include/linux/suspend.h b/include/linux/suspend.h index f73cabf59012..38bbf95109da 100644 --- a/include/linux/suspend.h +++ b/include/linux/suspend.h @@ -320,6 +320,8 @@ extern unsigned long get_safe_page(gfp_t gfp_mask); extern void hibernation_set_ops(const struct platform_hibernation_ops *ops); extern int hibernate(void); extern bool system_entering_hibernation(void); +asmlinkage int swsusp_save(void); +extern struct pbe *restore_pblist; #else /* CONFIG_HIBERNATION */ static inline void register_nosave_region(unsigned long b, unsigned long e) {} static inline void register_nosave_region_late(unsigned long b, unsigned long e) {} -- cgit v1.2.3 From a672917ab8964228f83ac1f0728468b309d6ea19 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Thu, 3 Apr 2014 18:46:45 +0100 Subject: ARM: 8022/1: ftrace: work with CONFIG_DEBUG_SET_MODULE_RONX Make ftrace work with CONFIG_DEBUG_SET_MODULE_RONX by making module text writable around the place where ftrace does its work, like it is done on x86 in the patch which introduced CONFIG_DEBUG_SET_MODULE_RONX, 84e1c6bb38eb ("x86: Add RO/NX protection for loadable kernel modules"). Tested-by: Mitchel Humpherys Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/kernel/ftrace.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index c108ddcb9ba4..af9a8a927a4e 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -14,6 +14,7 @@ #include #include +#include #include #include @@ -63,6 +64,18 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr) } #endif +int ftrace_arch_code_modify_prepare(void) +{ + set_all_modules_text_rw(); + return 0; +} + +int ftrace_arch_code_modify_post_process(void) +{ + set_all_modules_text_ro(); + return 0; +} + static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) { return arm_gen_branch_link(pc, addr); -- cgit v1.2.3 From 64d3b6a3f480154b6727dd2187f5f2b58c15da77 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 9 Apr 2014 21:24:02 +0100 Subject: ARM: 8023/1: remove remnants of the static DMA mapping It looks like the static mapping area for DMA was replaced by dynamic allocation into the vmalloc area by commit e9da6e9905e6 but the information in Documentation/arm/memory.txt was not removed accordingly. CONSISTENT_END in arch/arm/include/asm/memory.h has no more users and can be removed as well. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- Documentation/arm/memory.txt | 7 ------- arch/arm/include/asm/memory.h | 2 -- 2 files changed, 9 deletions(-) (limited to 'arch') diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index 4bfb9ffbdbc1..d74e8a5901fc 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt @@ -44,13 +44,6 @@ fffe0000 fffe7fff ITCM mapping area for platforms with fff00000 fffdffff Fixmap mapping region. Addresses provided by fix_to_virt() will be located here. -ffc00000 ffefffff DMA memory mapping region. Memory returned - by the dma_alloc_xxx functions will be - dynamically mapped here. - -ff000000 ffbfffff Reserved for future expansion of DMA - mapping region. - fee00000 feffffff Mapping of PCI I/O space. This is a static mapping within the vmalloc space. diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 02fa2558f662..2b751464d6ff 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -83,8 +83,6 @@ */ #define IOREMAP_MAX_ORDER 24 -#define CONSISTENT_END (0xffe00000UL) - #else /* CONFIG_MMU */ /* -- cgit v1.2.3 From 16c79a3776c17965dedab4732d925f6098df91c1 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 28 Mar 2014 12:21:16 +0100 Subject: ARM: 8013/1: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B PJ4B needs extra instructions for suspend and resume, so instead of using the armv7 version, this commit introduces specific versions for PJ4B. Signed-off-by: Gregory CLEMENT Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 195731d3813b..b74ea60891d5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -169,9 +169,31 @@ ENDPROC(cpu_pj4b_do_idle) globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle #endif globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area - globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend - globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume - globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size +#ifdef CONFIG_ARM_CPU_SUSPEND +ENTRY(cpu_pj4b_do_suspend) + stmfd sp!, {r6 - r10} + mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features + mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0 + mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2 + mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1 + mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC + stmia r0!, {r6 - r10} + ldmfd sp!, {r6 - r10} + b cpu_v7_do_suspend +ENDPROC(cpu_pj4b_do_suspend) + +ENTRY(cpu_pj4b_do_resume) + ldmia r0!, {r6 - r10} + mcr p15, 1, r6, c15, c1, 0 @ save CP15 - extra features + mcr p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0 + mcr p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2 + mcr p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1 + mcr p15, 0, r10, c9, c14, 0 @ save CP15 - PMC + b cpu_v7_do_resume +ENDPROC(cpu_pj4b_do_resume) +#endif +.globl cpu_pj4b_suspend_size +.equ cpu_pj4b_suspend_size, 4 * 14 #endif -- cgit v1.2.3 From 4221e2e6b3160e4b558df14fa79f025c0e277935 Mon Sep 17 00:00:00 2001 From: Liu Hua Date: Fri, 18 Apr 2014 09:27:01 +0100 Subject: ARM: 8031/1: fixmap: remove FIX_KMAP_BEGIN and FIX_KMAP_END It seems that these two macros are not used by non architecture specific code. And on ARM FIX_KMAP_BEGIN equals zero. This patch removes these two macros. Instead, using FIX_KMAP_NR_PTES to tell the pte number belonged to fixmap mapping region. The code will become clearer when I introduce a bugfix on fixmap mapping region. Reviewed-by: Nicolas Pitre Signed-off-by: Liu Hua Signed-off-by: Russell King --- arch/arm/include/asm/fixmap.h | 5 ++--- arch/arm/mm/highmem.c | 6 +++--- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h index bbae919bceb4..be55ebc08ed4 100644 --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -17,8 +17,7 @@ #define FIXADDR_TOP 0xfffe0000UL #define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START) -#define FIX_KMAP_BEGIN 0 -#define FIX_KMAP_END (FIXADDR_SIZE >> PAGE_SHIFT) +#define FIX_KMAP_NR_PTES (FIXADDR_SIZE >> PAGE_SHIFT) #define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT)) #define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT) @@ -27,7 +26,7 @@ extern void __this_fixmap_does_not_exist(void); static inline unsigned long fix_to_virt(const unsigned int idx) { - if (idx >= FIX_KMAP_END) + if (idx >= FIX_KMAP_NR_PTES) __this_fixmap_does_not_exist(); return __fix_to_virt(idx); } diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index 21b9e1bf9b77..e05e8ad26ba5 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -63,7 +63,7 @@ void *kmap_atomic(struct page *page) type = kmap_atomic_idx_push(); idx = type + KM_TYPE_NR * smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); + vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM /* * With debugging enabled, kunmap_atomic forces that entry to 0. @@ -94,7 +94,7 @@ void __kunmap_atomic(void *kvaddr) if (cache_is_vivt()) __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); #ifdef CONFIG_DEBUG_HIGHMEM - BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); + BUG_ON(vaddr != __fix_to_virt(idx)); set_top_pte(vaddr, __pte(0)); #else (void) idx; /* to kill a warning */ @@ -117,7 +117,7 @@ void *kmap_atomic_pfn(unsigned long pfn) type = kmap_atomic_idx_push(); idx = type + KM_TYPE_NR * smp_processor_id(); - vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); + vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM BUG_ON(!pte_none(get_top_pte(vaddr))); #endif -- cgit v1.2.3 From a05e54c103b0b8e1dab5d04b411f1d48387c4903 Mon Sep 17 00:00:00 2001 From: Liu Hua Date: Fri, 18 Apr 2014 09:43:32 +0100 Subject: ARM: 8031/2: change fixmap mapping region to support 32 CPUs In 32-bit ARM systems, the fixmap mapping region can support no more than 14 CPUs(total: 896k; one CPU: 64K). And we can configure NR_CPUS up to 32. So there is a mismatch. This patch moves fixmapping region downwards to region 0xffc00000- 0xffe00000. Then the fixmap mapping region can support up to 32 CPUs. Reviewed-by: Nicolas Pitre Signed-off-by: Liu Hua Signed-off-by: Russell King --- Documentation/arm/memory.txt | 2 +- arch/arm/include/asm/fixmap.h | 16 ++-------------- arch/arm/include/asm/highmem.h | 1 + arch/arm/mm/highmem.c | 27 +++++++++++++++++++++------ arch/arm/mm/mmu.c | 4 ++++ 5 files changed, 29 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index d74e8a5901fc..256c5e067fb1 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt @@ -41,7 +41,7 @@ fffe8000 fffeffff DTCM mapping area for platforms with fffe0000 fffe7fff ITCM mapping area for platforms with ITCM mounted inside the CPU. -fff00000 fffdffff Fixmap mapping region. Addresses provided +fffc0000 ffdfffff Fixmap mapping region. Addresses provided by fix_to_virt() will be located here. fee00000 feffffff Mapping of PCI I/O space. This is a static diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h index be55ebc08ed4..74124b0d0d79 100644 --- a/arch/arm/include/asm/fixmap.h +++ b/arch/arm/include/asm/fixmap.h @@ -1,20 +1,8 @@ #ifndef _ASM_FIXMAP_H #define _ASM_FIXMAP_H -/* - * Nothing too fancy for now. - * - * On ARM we already have well known fixed virtual addresses imposed by - * the architecture such as the vector page which is located at 0xffff0000, - * therefore a second level page table is already allocated covering - * 0xfff00000 upwards. - * - * The cache flushing code in proc-xscale.S uses the virtual area between - * 0xfffe0000 and 0xfffeffff. - */ - -#define FIXADDR_START 0xfff00000UL -#define FIXADDR_TOP 0xfffe0000UL +#define FIXADDR_START 0xffc00000UL +#define FIXADDR_TOP 0xffe00000UL #define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START) #define FIX_KMAP_NR_PTES (FIXADDR_SIZE >> PAGE_SHIFT) diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h index 91b99abe7a95..535579511ed0 100644 --- a/arch/arm/include/asm/highmem.h +++ b/arch/arm/include/asm/highmem.h @@ -18,6 +18,7 @@ } while (0) extern pte_t *pkmap_page_table; +extern pte_t *fixmap_page_table; extern void *kmap_high(struct page *page); extern void kunmap_high(struct page *page); diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c index e05e8ad26ba5..45aeaaca9052 100644 --- a/arch/arm/mm/highmem.c +++ b/arch/arm/mm/highmem.c @@ -18,6 +18,21 @@ #include #include "mm.h" +pte_t *fixmap_page_table; + +static inline void set_fixmap_pte(int idx, pte_t pte) +{ + unsigned long vaddr = __fix_to_virt(idx); + set_pte_ext(fixmap_page_table + idx, pte, 0); + local_flush_tlb_kernel_page(vaddr); +} + +static inline pte_t get_fixmap_pte(unsigned long vaddr) +{ + unsigned long idx = __virt_to_fix(vaddr); + return *(fixmap_page_table + idx); +} + void *kmap(struct page *page) { might_sleep(); @@ -69,14 +84,14 @@ void *kmap_atomic(struct page *page) * With debugging enabled, kunmap_atomic forces that entry to 0. * Make sure it was indeed properly unmapped. */ - BUG_ON(!pte_none(get_top_pte(vaddr))); + BUG_ON(!pte_none(*(fixmap_page_table + idx))); #endif /* * When debugging is off, kunmap_atomic leaves the previous mapping * in place, so the contained TLB flush ensures the TLB is updated * with the new mapping. */ - set_top_pte(vaddr, mk_pte(page, kmap_prot)); + set_fixmap_pte(idx, mk_pte(page, kmap_prot)); return (void *)vaddr; } @@ -95,7 +110,7 @@ void __kunmap_atomic(void *kvaddr) __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); #ifdef CONFIG_DEBUG_HIGHMEM BUG_ON(vaddr != __fix_to_virt(idx)); - set_top_pte(vaddr, __pte(0)); + set_fixmap_pte(idx, __pte(0)); #else (void) idx; /* to kill a warning */ #endif @@ -119,9 +134,9 @@ void *kmap_atomic_pfn(unsigned long pfn) idx = type + KM_TYPE_NR * smp_processor_id(); vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM - BUG_ON(!pte_none(get_top_pte(vaddr))); + BUG_ON(!pte_none(*(fixmap_page_table + idx))); #endif - set_top_pte(vaddr, pfn_pte(pfn, kmap_prot)); + set_fixmap_pte(idx, pfn_pte(pfn, kmap_prot)); return (void *)vaddr; } @@ -133,5 +148,5 @@ struct page *kmap_atomic_to_page(const void *ptr) if (vaddr < FIXADDR_START) return virt_to_page(ptr); - return pte_page(get_top_pte(vaddr)); + return pte_page(get_fixmap_pte(vaddr)); } diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index b68c6b22e1c8..09c0a16165dc 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "mm.h" #include "tcm.h" @@ -1359,6 +1360,9 @@ static void __init kmap_init(void) #ifdef CONFIG_HIGHMEM pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), PKMAP_BASE, _PAGE_KERNEL_TABLE); + + fixmap_page_table = early_pte_alloc(pmd_off_k(FIXADDR_START), + FIXADDR_START, _PAGE_KERNEL_TABLE); #endif } -- cgit v1.2.3 From 218e18a3728507ee82ed2eb10c789671a00e34bd Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 22 Apr 2014 22:46:35 +0200 Subject: ASoC: qi_lb60: Use GPIO descriptor API The new GPIO descriptor API is now the preferred way for handling GPIOs. It also allows us to separate the platform depended code from the platform independent code (Which will make it possible to increase build test coverage of the platform independent code). Signed-off-by: Lars-Peter Clausen Acked-by: Ralf Baechle Signed-off-by: Mark Brown --- arch/mips/jz4740/board-qi_lb60.c | 11 ++++++++ sound/soc/jz4740/qi_lb60.c | 54 +++++++++++++++++++++------------------- 2 files changed, 39 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index c01900e5d078..088e92a79ae6 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -425,6 +425,15 @@ static struct platform_device qi_lb60_audio_device = { .id = -1, }; +static struct gpiod_lookup_table qi_lb60_audio_gpio_table = { + .dev_id = "qi-lb60-audio", + .table = { + GPIO_LOOKUP("Bank B", 29, "snd", 0), + GPIO_LOOKUP("Bank D", 4, "amp", 0), + { }, + }, +}; + static struct platform_device *jz_platform_devices[] __initdata = { &jz4740_udc_device, &jz4740_udc_xceiv_device, @@ -461,6 +470,8 @@ static int __init qi_lb60_init_platform_devices(void) jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata; jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata; + gpiod_add_lookup_table(&qi_lb60_audio_gpio_table); + jz4740_serial_device_register(); spi_register_board_info(qi_lb60_spi_board_info, diff --git a/sound/soc/jz4740/qi_lb60.c b/sound/soc/jz4740/qi_lb60.c index be0a437f0888..5cb91f9e8626 100644 --- a/sound/soc/jz4740/qi_lb60.c +++ b/sound/soc/jz4740/qi_lb60.c @@ -19,18 +19,21 @@ #include #include #include -#include +#include -#define QI_LB60_SND_GPIO JZ_GPIO_PORTB(29) -#define QI_LB60_AMP_GPIO JZ_GPIO_PORTD(4) +struct qi_lb60 { + struct gpio_desc *snd_gpio; + struct gpio_desc *amp_gpio; +}; static int qi_lb60_spk_event(struct snd_soc_dapm_widget *widget, struct snd_kcontrol *ctrl, int event) { + struct qi_lb60 *qi_lb60 = snd_soc_card_get_drvdata(widget->dapm->card); int on = !SND_SOC_DAPM_EVENT_OFF(event); - gpio_set_value(QI_LB60_SND_GPIO, on); - gpio_set_value(QI_LB60_AMP_GPIO, on); + gpiod_set_value_cansleep(qi_lb60->snd_gpio, on); + gpiod_set_value_cansleep(qi_lb60->amp_gpio, on); return 0; } @@ -57,7 +60,7 @@ static struct snd_soc_dai_link qi_lb60_dai = { SND_SOC_DAIFMT_CBM_CFM, }; -static struct snd_soc_card qi_lb60 = { +static struct snd_soc_card qi_lb60_card = { .name = "QI LB60", .owner = THIS_MODULE, .dai_link = &qi_lb60_dai, @@ -70,35 +73,35 @@ static struct snd_soc_card qi_lb60 = { .fully_routed = true, }; -static const struct gpio qi_lb60_gpios[] = { - { QI_LB60_SND_GPIO, GPIOF_OUT_INIT_LOW, "SND" }, - { QI_LB60_AMP_GPIO, GPIOF_OUT_INIT_LOW, "AMP" }, -}; - static int qi_lb60_probe(struct platform_device *pdev) { - struct snd_soc_card *card = &qi_lb60; + struct qi_lb60 *qi_lb60; + struct snd_soc_card *card = &qi_lb60_card; int ret; - ret = gpio_request_array(qi_lb60_gpios, ARRAY_SIZE(qi_lb60_gpios)); + qi_lb60 = devm_kzalloc(&pdev->dev, sizeof(*qi_lb60), GFP_KERNEL); + if (!qi_lb60) + return -ENOMEM; + + qi_lb60->snd_gpio = devm_gpiod_get(&pdev->dev, "snd"); + if (IS_ERR(qi_lb60->snd_gpio)) + return PTR_ERR(qi_lb60->snd_gpio); + ret = gpiod_direction_output(qi_lb60->snd_gpio, 0); + if (ret) + return ret; + + qi_lb60->amp_gpio = devm_gpiod_get(&pdev->dev, "amp"); + if (IS_ERR(qi_lb60->amp_gpio)) + return PTR_ERR(qi_lb60->amp_gpio); + ret = gpiod_direction_output(qi_lb60->amp_gpio, 0); if (ret) return ret; card->dev = &pdev->dev; - ret = devm_snd_soc_register_card(&pdev->dev, card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - gpio_free_array(qi_lb60_gpios, ARRAY_SIZE(qi_lb60_gpios)); - } - return ret; -} + snd_soc_card_set_drvdata(card, qi_lb60); -static int qi_lb60_remove(struct platform_device *pdev) -{ - gpio_free_array(qi_lb60_gpios, ARRAY_SIZE(qi_lb60_gpios)); - return 0; + return devm_snd_soc_register_card(&pdev->dev, card); } static struct platform_driver qi_lb60_driver = { @@ -107,7 +110,6 @@ static struct platform_driver qi_lb60_driver = { .owner = THIS_MODULE, }, .probe = qi_lb60_probe, - .remove = qi_lb60_remove, }; module_platform_driver(qi_lb60_driver); -- cgit v1.2.3 From 0aa2a15a7b5ca861b02379a7dcb2d7bf427c62cc Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 22 Apr 2014 22:46:36 +0200 Subject: ASoC: jz4740: Improve build test coverage Allow the jz4740 audio drivers to be build when CONFIG_COMPILE_TEST is selected. This should improve the build test coverage. There is one small piece of platform dependent code in the jz4740-i2s driver. It uses the DMA request type constants which are defined in a platform specific header. We can solve this by moving them from the platform specific header to the I2S driver. Signed-off-by: Lars-Peter Clausen Acked-by: Ralf Baechle Signed-off-by: Mark Brown --- arch/mips/include/asm/mach-jz4740/dma.h | 2 -- sound/soc/jz4740/Kconfig | 11 ++++++++--- sound/soc/jz4740/jz4740-i2s.c | 5 +++-- 3 files changed, 11 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h index 509cd5828044..14ecc5313d2d 100644 --- a/arch/mips/include/asm/mach-jz4740/dma.h +++ b/arch/mips/include/asm/mach-jz4740/dma.h @@ -22,8 +22,6 @@ enum jz4740_dma_request_type { JZ4740_DMA_TYPE_UART_RECEIVE = 21, JZ4740_DMA_TYPE_SPI_TRANSMIT = 22, JZ4740_DMA_TYPE_SPI_RECEIVE = 23, - JZ4740_DMA_TYPE_AIC_TRANSMIT = 24, - JZ4740_DMA_TYPE_AIC_RECEIVE = 25, JZ4740_DMA_TYPE_MMC_TRANSMIT = 26, JZ4740_DMA_TYPE_MMC_RECEIVE = 27, JZ4740_DMA_TYPE_TCU = 28, diff --git a/sound/soc/jz4740/Kconfig b/sound/soc/jz4740/Kconfig index 29f76af5d963..1a354a6b6e87 100644 --- a/sound/soc/jz4740/Kconfig +++ b/sound/soc/jz4740/Kconfig @@ -1,24 +1,29 @@ config SND_JZ4740_SOC tristate "SoC Audio for Ingenic JZ4740 SoC" - depends on MACH_JZ4740 && SND_SOC + depends on MACH_JZ4740 || COMPILE_TEST select SND_SOC_GENERIC_DMAENGINE_PCM help Say Y or M if you want to add support for codecs attached to the JZ4740 I2S interface. You will also need to select the audio interfaces to support below. +if SND_JZ4740_SOC + config SND_JZ4740_SOC_I2S - depends on SND_JZ4740_SOC tristate "SoC Audio (I2S protocol) for Ingenic JZ4740 SoC" + depends on HAS_IOMEM help Say Y if you want to use I2S protocol and I2S codec on Ingenic JZ4740 based boards. config SND_JZ4740_SOC_QI_LB60 tristate "SoC Audio support for Qi LB60" - depends on SND_JZ4740_SOC && JZ4740_QI_LB60 + depends on HAS_IOMEM + depends on JZ4740_QI_LB60 || COMPILE_TEST select SND_JZ4740_SOC_I2S select SND_SOC_JZ4740_CODEC help Say Y if you want to add support for ASoC audio on the Qi LB60 board a.k.a Qi Ben NanoNote. + +endif diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 8f220009e0f6..3f9c3a9ae36f 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -31,10 +31,11 @@ #include #include -#include - #include "jz4740-i2s.h" +#define JZ4740_DMA_TYPE_AIC_TRANSMIT 24 +#define JZ4740_DMA_TYPE_AIC_RECEIVE 25 + #define JZ_REG_AIC_CONF 0x00 #define JZ_REG_AIC_CTRL 0x04 #define JZ_REG_AIC_I2S_FMT 0x10 -- cgit v1.2.3 From 28240d27d6c6ab1e3c20ec038a7e29a80f6ed614 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 10:29:35 +0200 Subject: ARM: sun6i: Sort the NMI node by physical address The DT are supposed to be ordered by physical address. Move the NMI node where it belongs. Signed-off-by: Maxime Ripard Acked-by: Arnd Bergmann --- arch/arm/boot/dts/sun6i-a31.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index bc46814d2ff0..5ebf963464b9 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -237,14 +237,6 @@ #size-cells = <1>; ranges; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; - interrupts = <0 32 4>; - }; - pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -479,6 +471,14 @@ interrupts = <1 9 0xf04>; }; + nmi_intc: interrupt-controller@01f00c0c { + compatible = "allwinner,sun6i-a31-sc-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01f00c0c 0x38>; + interrupts = <0 32 4>; + }; + prcm@01f01400 { compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; -- cgit v1.2.3 From d2d878c45371b57a55ac7d51c19a1a4b05ddd40e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 30 Jan 2014 15:41:23 +0100 Subject: ARM: sun6i: dt: Add A31 DMA controller to DTSI Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the controller and the devices supported that can use DMA. Signed-off-by: Maxime Ripard Acked-by: Arnd Bergmann --- arch/arm/boot/dts/sun6i-a31.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 5ebf963464b9..b28a55fdf3ce 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -237,6 +237,15 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun6i-a31-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb1_gates 6>; + resets = <&ahb1_rst 6>; + #dma-cells = <1>; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; @@ -322,6 +331,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 16>; resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -333,6 +344,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 17>; resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -344,6 +357,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 18>; resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -355,6 +370,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 19>; resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -366,6 +383,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 20>; resets = <&apb2_rst 20>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -377,6 +396,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 21>; resets = <&apb2_rst 21>; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -426,6 +447,8 @@ interrupts = <0 65 4>; clocks = <&ahb1_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 20>; status = "disabled"; }; @@ -436,6 +459,8 @@ interrupts = <0 66 4>; clocks = <&ahb1_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 21>; status = "disabled"; }; @@ -446,6 +471,8 @@ interrupts = <0 67 4>; clocks = <&ahb1_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 25>, <&dma 25>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 22>; status = "disabled"; }; @@ -456,6 +483,8 @@ interrupts = <0 68 4>; clocks = <&ahb1_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 26>, <&dma 26>; + dma-names = "rx", "tx"; resets = <&ahb1_rst 23>; status = "disabled"; }; -- cgit v1.2.3 From a613b739b8c08eab811e677810045cc0522fc3e6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 10 Apr 2014 16:47:18 -0700 Subject: mfd: twl-core: Fix idle mode signaling for omaps when booted with device tree I noticed a regression where the omap sys_clkreq signal will never trigger for omap3 when booted with device tree while it triggers when booted in legacy mode. This means voltage scaling does not do anything when booted with device tree. Turns out the reason is we fail to initialize the SmartReflex enable bit in twl4030 with the following error: twl: not initialized And that happens because we are wrongly tinkering with the twl4030 registers in arch/arm/mach-omap2/omap_twl.c before the driver is initialized. Looking at the the SmartReflex bit enable code in omap_twl.c, we need to always set it. So let's fix the issue by always enabling the twl4030 SmartReflex bit in the drivers/mfd/twl-core.c probe, and drop the related code in omap_twl.c. Note that we still have some twl4030 tinkering left in omap_twl.c for the twl6030 case, but that's a different patch. Signed-off-by: Tony Lindgren Signed-off-by: Lee Jones --- arch/arm/mach-omap2/omap_twl.c | 60 ------------------------------------------ drivers/mfd/twl-core.c | 15 +++++++++++ 2 files changed, 15 insertions(+), 60 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index 615e5b1fb025..6bf626700557 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -46,15 +46,8 @@ static bool is_offset_valid; static u8 smps_offset; -/* - * Flag to ensure Smartreflex bit in TWL - * being cleared in board file is not overwritten. - */ -static bool __initdata twl_sr_enable_autoinit; -#define TWL4030_DCDC_GLOBAL_CFG 0x06 #define REG_SMPS_OFFSET 0xE0 -#define SMARTREFLEX_ENABLE BIT(3) static unsigned long twl4030_vsel_to_uv(const u8 vsel) { @@ -251,18 +244,6 @@ int __init omap3_twl_init(void) if (!cpu_is_omap34xx()) return -ENODEV; - /* - * The smartreflex bit on twl4030 specifies if the setting of voltage - * is done over the I2C_SR path. Since this setting is independent of - * the actual usage of smartreflex AVS module, we enable TWL SR bit - * by default irrespective of whether smartreflex AVS module is enabled - * on the OMAP side or not. This is because without this bit enabled, - * the voltage scaling through vp forceupdate/bypass mechanism of - * voltage scaling will not function on TWL over I2C_SR. - */ - if (!twl_sr_enable_autoinit) - omap3_twl_set_sr_bit(true); - voltdm = voltdm_lookup("mpu_iva"); omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic); @@ -271,44 +252,3 @@ int __init omap3_twl_init(void) return 0; } - -/** - * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL - * @enable: enable SR mode in twl or not - * - * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure - * voltage scaling through OMAP SR works. Else, the smartreflex bit - * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but - * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct - * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages, - * in those scenarios this bit is to be cleared (enable = false). - * - * Returns 0 on success, error is returned if I2C read/write fails. - */ -int __init omap3_twl_set_sr_bit(bool enable) -{ - u8 temp; - int ret; - if (twl_sr_enable_autoinit) - pr_warning("%s: unexpected multiple calls\n", __func__); - - ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp, - TWL4030_DCDC_GLOBAL_CFG); - if (ret) - goto err; - - if (enable) - temp |= SMARTREFLEX_ENABLE; - else - temp &= ~SMARTREFLEX_ENABLE; - - ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp, - TWL4030_DCDC_GLOBAL_CFG); - if (!ret) { - twl_sr_enable_autoinit = true; - return 0; - } -err: - pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret); - return ret; -} diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c index ed718328eff1..ad7d04f95dd1 100644 --- a/drivers/mfd/twl-core.c +++ b/drivers/mfd/twl-core.c @@ -98,7 +98,11 @@ #define TWL4030_BASEADD_BACKUP 0x0014 #define TWL4030_BASEADD_INT 0x002E #define TWL4030_BASEADD_PM_MASTER 0x0036 + #define TWL4030_BASEADD_PM_RECEIVER 0x005B +#define TWL4030_DCDC_GLOBAL_CFG 0x06 +#define SMARTREFLEX_ENABLE BIT(3) + #define TWL4030_BASEADD_RTC 0x001C #define TWL4030_BASEADD_SECURED_REG 0x0000 @@ -1204,6 +1208,11 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id) * Disable TWL4030/TWL5030 I2C Pull-up on I2C1 and I2C4(SR) interface. * Program I2C_SCL_CTRL_PU(bit 0)=0, I2C_SDA_CTRL_PU (bit 2)=0, * SR_I2C_SCL_CTRL_PU(bit 4)=0 and SR_I2C_SDA_CTRL_PU(bit 6)=0. + * + * Also, always enable SmartReflex bit as that's needed for omaps to + * to do anything over I2C4 for voltage scaling even if SmartReflex + * is disabled. Without the SmartReflex bit omap sys_clkreq idle + * signal will never trigger for retention idle. */ if (twl_class_is_4030()) { u8 temp; @@ -1212,6 +1221,12 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id) temp &= ~(SR_I2C_SDA_CTRL_PU | SR_I2C_SCL_CTRL_PU | \ I2C_SDA_CTRL_PU | I2C_SCL_CTRL_PU); twl_i2c_write_u8(TWL4030_MODULE_INTBR, temp, REG_GPPUPDCTR1); + + twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp, + TWL4030_DCDC_GLOBAL_CFG); + temp |= SMARTREFLEX_ENABLE; + twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp, + TWL4030_DCDC_GLOBAL_CFG); } if (node) { -- cgit v1.2.3 From 671bd9934a861288a248b051751061b11654aef9 Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 18 Apr 2014 03:35:08 +0300 Subject: KVM: x86: Fix wrong/stuck PMU when guest does not use PMI If a guest enables a performance counter but does not enable PMI, the hypervisor currently does not reprogram the performance counter once it overflows. As a result the host performance counter is kept with the original sampling period which was configured according to the value of the guest's counter when the counter was enabled. Such behaviour can cause very bad consequences. The most distrubing one can cause the guest not to make any progress at all, and keep exiting due to host PMI before any guest instructions is exeucted. This situation occurs when the performance counter holds a very high value when the guest enables the performance counter. As a result the host's sampling period is configured to be very short. The host then never reconfigures the sampling period and get stuck at entry->PMI->exit loop. We encountered such a scenario in our experiments. The solution is to reprogram the counter even if the guest does not use PMI. Signed-off-by: Nadav Amit Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/pmu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 5c4f63151b4d..cbecaa90399c 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -108,7 +108,10 @@ static void kvm_perf_overflow(struct perf_event *perf_event, { struct kvm_pmc *pmc = perf_event->overflow_handler_context; struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu; - __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); + if (!test_and_set_bit(pmc->idx, (unsigned long *)&pmu->reprogram_pmi)) { + __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); + kvm_make_request(KVM_REQ_PMU, pmc->vcpu); + } } static void kvm_perf_overflow_intr(struct perf_event *perf_event, @@ -117,7 +120,7 @@ static void kvm_perf_overflow_intr(struct perf_event *perf_event, struct kvm_pmc *pmc = perf_event->overflow_handler_context; struct kvm_pmu *pmu = &pmc->vcpu->arch.pmu; if (!test_and_set_bit(pmc->idx, (unsigned long *)&pmu->reprogram_pmi)) { - kvm_perf_overflow(perf_event, data, regs); + __set_bit(pmc->idx, (unsigned long *)&pmu->global_status); kvm_make_request(KVM_REQ_PMU, pmc->vcpu); /* * Inject PMI. If vcpu was in a guest mode during NMI PMI -- cgit v1.2.3 From 346874c9507a2582d0c00021f848de6e115f276c Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 18 Apr 2014 03:35:09 +0300 Subject: KVM: x86: Fix CR3 reserved bits According to Intel specifications, PAE and non-PAE does not have any reserved bits. In long-mode, regardless to PCIDE, only the high bits (above the physical address) are reserved. Signed-off-by: Nadav Amit Signed-off-by: Marcelo Tosatti --- arch/x86/include/asm/kvm_host.h | 6 +----- arch/x86/kvm/emulate.c | 4 ---- arch/x86/kvm/x86.c | 25 +++++-------------------- 3 files changed, 6 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 7de069afb382..e21aee98a5c2 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -50,11 +50,7 @@ | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) -#define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) -#define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) -#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL -#define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ - 0xFFFFFF0000000000ULL) +#define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL #define CR4_RESERVED_BITS \ (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 0dec502d20be..f3834bbca1d7 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -3388,10 +3388,6 @@ static int check_cr_write(struct x86_emulate_ctxt *ctxt) ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); if (efer & EFER_LMA) rsvd = CR3_L_MODE_RESERVED_BITS; - else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) - rsvd = CR3_PAE_RESERVED_BITS; - else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) - rsvd = CR3_NONPAE_RESERVED_BITS; if (new_val & rsvd) return emulate_gp(ctxt, 0); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index bc4aaf68190c..e4ccc6cf4108 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -701,26 +701,11 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) return 0; } - if (is_long_mode(vcpu)) { - if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) { - if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS) - return 1; - } else - if (cr3 & CR3_L_MODE_RESERVED_BITS) - return 1; - } else { - if (is_pae(vcpu)) { - if (cr3 & CR3_PAE_RESERVED_BITS) - return 1; - if (is_paging(vcpu) && - !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) - return 1; - } - /* - * We don't check reserved bits in nonpae mode, because - * this isn't enforced, and VMware depends on this. - */ - } + if (is_long_mode(vcpu) && (cr3 & CR3_L_MODE_RESERVED_BITS)) + return 1; + if (is_pae(vcpu) && is_paging(vcpu) && + !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) + return 1; vcpu->arch.cr3 = cr3; __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail); -- cgit v1.2.3 From e6e39f0438bc4b0da9334ca42337775c7a00db21 Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 18 Apr 2014 03:35:10 +0300 Subject: KVM: x86: IN instruction emulation should ignore REP-prefix The IN instruction is not be affected by REP-prefix as INS is. Therefore, the emulation should ignore the REP prefix as well. The current emulator implementation tries to perform writeback when IN instruction with REP-prefix is emulated. This causes it to perform wrong memory write or spurious #GP exception to be injected to the guest. Signed-off-by: Nadav Amit Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/emulate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index f3834bbca1d7..e8a58409b5ac 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -1324,7 +1324,8 @@ static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, rc->end = n * size; } - if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) { + if (ctxt->rep_prefix && (ctxt->d & String) && + !(ctxt->eflags & EFLG_DF)) { ctxt->dst.data = rc->data + rc->pos; ctxt->dst.type = OP_MEM_STR; ctxt->dst.count = (rc->end - rc->pos) / size; -- cgit v1.2.3 From 42bf549f3c672006ba18e97152cbc563315ba4e6 Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Fri, 18 Apr 2014 07:11:34 +0300 Subject: KVM: x86: Processor mode may be determined incorrectly If EFER.LMA is off, cs.l does not determine execution mode. Currently, the emulation engine assumes differently. Signed-off-by: Nadav Amit Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e4ccc6cf4108..7cc646626afd 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4888,7 +4888,7 @@ static void init_emulate_ctxt(struct kvm_vcpu *vcpu) ctxt->eip = kvm_rip_read(vcpu); ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : - cs_l ? X86EMUL_MODE_PROT64 : + (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : cs_db ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; ctxt->guest_mode = is_guest_mode(vcpu); -- cgit v1.2.3 From a086f6a1ebc9d8d2d028b99e779ce0dbd9691dea Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Thu, 17 Apr 2014 17:06:12 +0800 Subject: Revert "KVM: Simplify kvm->tlbs_dirty handling" This reverts commit 5befdc385ddb2d5ae8995ad89004529a3acf58fc. Since we will allow flush tlb out of mmu-lock in the later patch Signed-off-by: Xiao Guangrong Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/paging_tmpl.h | 7 +++---- include/linux/kvm_host.h | 4 +--- virt/kvm/kvm_main.c | 5 ++++- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h index 123efd3ec29f..410776528265 100644 --- a/arch/x86/kvm/paging_tmpl.h +++ b/arch/x86/kvm/paging_tmpl.h @@ -913,8 +913,7 @@ static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr, * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't * used by guest then tlbs are not flushed, so guest is allowed to access the * freed pages. - * We set tlbs_dirty to let the notifier know this change and delay the flush - * until such a case actually happens. + * And we increase kvm->tlbs_dirty to delay tlbs flush in this case. */ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) { @@ -943,7 +942,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) return -EINVAL; if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) { - vcpu->kvm->tlbs_dirty = true; + vcpu->kvm->tlbs_dirty++; continue; } @@ -958,7 +957,7 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) if (gfn != sp->gfns[i]) { drop_spte(vcpu->kvm, &sp->spt[i]); - vcpu->kvm->tlbs_dirty = true; + vcpu->kvm->tlbs_dirty++; continue; } diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 32d263f683dc..820fc2e1d9df 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -411,9 +411,7 @@ struct kvm { unsigned long mmu_notifier_seq; long mmu_notifier_count; #endif - /* Protected by mmu_lock */ - bool tlbs_dirty; - + long tlbs_dirty; struct list_head devices; }; diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index ea46d64c8e75..fa70c6e642b4 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -186,9 +186,12 @@ static bool make_all_cpus_request(struct kvm *kvm, unsigned int req) void kvm_flush_remote_tlbs(struct kvm *kvm) { + long dirty_count = kvm->tlbs_dirty; + + smp_mb(); if (make_all_cpus_request(kvm, KVM_REQ_TLB_FLUSH)) ++kvm->stat.remote_tlb_flush; - kvm->tlbs_dirty = false; + cmpxchg(&kvm->tlbs_dirty, dirty_count, 0); } EXPORT_SYMBOL_GPL(kvm_flush_remote_tlbs); -- cgit v1.2.3 From 92a476cbfc476c63ee982dd33d15a8c88b4d51b9 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Thu, 17 Apr 2014 17:06:13 +0800 Subject: KVM: MMU: properly check last spte in fast_page_fault() Using sp->role.level instead of @level since @level is not got from the page table hierarchy There is no issue in current code since the fast page fault currently only fixes the fault caused by dirty-log that is always on the last level (level = 1) This patch makes the code more readable and avoids potential issue in the further development Reviewed-by: Marcelo Tosatti Signed-off-by: Xiao Guangrong Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/mmu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 668ae5916de9..63107049249d 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -2802,9 +2802,9 @@ static bool page_fault_can_be_fast(u32 error_code) } static bool -fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte) +fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, + u64 *sptep, u64 spte) { - struct kvm_mmu_page *sp = page_header(__pa(sptep)); gfn_t gfn; WARN_ON(!sp->role.direct); @@ -2830,6 +2830,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, u32 error_code) { struct kvm_shadow_walk_iterator iterator; + struct kvm_mmu_page *sp; bool ret = false; u64 spte = 0ull; @@ -2853,7 +2854,8 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, goto exit; } - if (!is_last_spte(spte, level)) + sp = page_header(__pa(iterator.sptep)); + if (!is_last_spte(spte, sp->role.level)) goto exit; /* @@ -2879,7 +2881,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, * the gfn is not stable for indirect shadow page. * See Documentation/virtual/kvm/locking.txt to get more detail. */ - ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte); + ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte); exit: trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, spte, ret); -- cgit v1.2.3 From c126d94f2c90ed9daee24a94f1c67aff7e9bf387 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Thu, 17 Apr 2014 17:06:14 +0800 Subject: KVM: MMU: lazily drop large spte Currently, kvm zaps the large spte if write-protected is needed, the later read can fault on that spte. Actually, we can make the large spte readonly instead of making them un-present, the page fault caused by read access can be avoided The idea is from Avi: | As I mentioned before, write-protecting a large spte is a good idea, | since it moves some work from protect-time to fault-time, so it reduces | jitter. This removes the need for the return value. This version has fixed the issue reported in 6b73a9606, the reason of that issue is that fast_page_fault() directly sets the readonly large spte to writable but only dirty the first page into the dirty-bitmap that means other pages are missed. Fixed it by only the normal sptes (on the PT_PAGE_TABLE_LEVEL level) can be fast fixed Reviewed-by: Marcelo Tosatti Signed-off-by: Xiao Guangrong Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/mmu.c | 34 ++++++++++++++++++---------------- arch/x86/kvm/x86.c | 8 ++++++-- 2 files changed, 24 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 63107049249d..ddf06963a74c 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -1176,8 +1176,7 @@ static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) /* * Write-protect on the specified @sptep, @pt_protect indicates whether - * spte writ-protection is caused by protecting shadow page table. - * @flush indicates whether tlb need be flushed. + * spte write-protection is caused by protecting shadow page table. * * Note: write protection is difference between drity logging and spte * protection: @@ -1186,10 +1185,9 @@ static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) * - for spte protection, the spte can be writable only after unsync-ing * shadow page. * - * Return true if the spte is dropped. + * Return true if tlb need be flushed. */ -static bool -spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) +static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect) { u64 spte = *sptep; @@ -1199,17 +1197,11 @@ spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect) rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); - if (__drop_large_spte(kvm, sptep)) { - *flush |= true; - return true; - } - if (pt_protect) spte &= ~SPTE_MMU_WRITEABLE; spte = spte & ~PT_WRITABLE_MASK; - *flush |= mmu_spte_update(sptep, spte); - return false; + return mmu_spte_update(sptep, spte); } static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, @@ -1221,11 +1213,8 @@ static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, for (sptep = rmap_get_first(*rmapp, &iter); sptep;) { BUG_ON(!(*sptep & PT_PRESENT_MASK)); - if (spte_write_protect(kvm, sptep, &flush, pt_protect)) { - sptep = rmap_get_first(*rmapp, &iter); - continue; - } + flush |= spte_write_protect(kvm, sptep, pt_protect); sptep = rmap_get_next(&iter); } @@ -2876,6 +2865,19 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, if (!spte_is_locklessly_modifiable(spte)) goto exit; + /* + * Do not fix write-permission on the large spte since we only dirty + * the first page into the dirty-bitmap in fast_pf_fix_direct_spte() + * that means other pages are missed if its slot is dirty-logged. + * + * Instead, we let the slow page fault path create a normal spte to + * fix the access. + * + * See the comments in kvm_arch_commit_memory_region(). + */ + if (sp->role.level > PT_PAGE_TABLE_LEVEL) + goto exit; + /* * Currently, fast page fault only works for direct mapping since * the gfn is not stable for indirect shadow page. diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7cc646626afd..63a828d206c5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -7315,8 +7315,12 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); /* * Write protect all pages for dirty logging. - * Existing largepage mappings are destroyed here and new ones will - * not be created until the end of the logging. + * + * All the sptes including the large sptes which point to this + * slot are set to readonly. We can not create any new large + * spte on this slot until the end of the logging. + * + * See the comments in fast_page_fault(). */ if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES)) kvm_mmu_slot_remove_write_access(kvm, mem->slot); -- cgit v1.2.3 From 7f31c9595e3c87f68dc54b3269e900f3017ed405 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Thu, 17 Apr 2014 17:06:15 +0800 Subject: KVM: MMU: flush tlb if the spte can be locklessly modified Relax the tlb flush condition since we will write-protect the spte out of mmu lock. Note lockless write-protection only marks the writable spte to readonly and the spte can be writable only if both SPTE_HOST_WRITEABLE and SPTE_MMU_WRITEABLE are set (that are tested by spte_is_locklessly_modifiable) This patch is used to avoid this kind of race: VCPU 0 VCPU 1 lockless wirte protection: set spte.w = 0 lock mmu-lock write protection the spte to sync shadow page, see spte.w = 0, then without flush tlb unlock mmu-lock !!! At this point, the shadow page can still be writable due to the corrupt tlb entry Flush all TLB Reviewed-by: Marcelo Tosatti Signed-off-by: Xiao Guangrong Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/mmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index ddf06963a74c..388a2ef83911 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -595,7 +595,8 @@ static bool mmu_spte_update(u64 *sptep, u64 new_spte) * we always atomicly update it, see the comments in * spte_has_volatile_bits(). */ - if (is_writable_pte(old_spte) && !is_writable_pte(new_spte)) + if (spte_is_locklessly_modifiable(old_spte) && + !is_writable_pte(new_spte)) ret = true; if (!shadow_accessed_mask) -- cgit v1.2.3 From 198c74f43f0f5473f99967aead30ddc622804bc1 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Thu, 17 Apr 2014 17:06:16 +0800 Subject: KVM: MMU: flush tlb out of mmu lock when write-protect the sptes Now we can flush all the TLBs out of the mmu lock without TLB corruption when write-proect the sptes, it is because: - we have marked large sptes readonly instead of dropping them that means we just change the spte from writable to readonly so that we only need to care the case of changing spte from present to present (changing the spte from present to nonpresent will flush all the TLBs immediately), in other words, the only case we need to care is mmu_spte_update() - in mmu_spte_update(), we haved checked SPTE_HOST_WRITEABLE | PTE_MMU_WRITEABLE instead of PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK anymore Acked-by: Marcelo Tosatti Signed-off-by: Xiao Guangrong Signed-off-by: Marcelo Tosatti --- arch/x86/kvm/mmu.c | 25 +++++++++++++++++++++---- arch/x86/kvm/mmu.h | 33 +++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.c | 12 ++++++++++-- 3 files changed, 64 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 388a2ef83911..65f2400b8268 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -4309,15 +4309,32 @@ void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot) if (*rmapp) __rmap_write_protect(kvm, rmapp, false); - if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { - kvm_flush_remote_tlbs(kvm); + if (need_resched() || spin_needbreak(&kvm->mmu_lock)) cond_resched_lock(&kvm->mmu_lock); - } } } - kvm_flush_remote_tlbs(kvm); spin_unlock(&kvm->mmu_lock); + + /* + * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() + * which do tlb flush out of mmu-lock should be serialized by + * kvm->slots_lock otherwise tlb flush would be missed. + */ + lockdep_assert_held(&kvm->slots_lock); + + /* + * We can flush all the TLBs out of the mmu lock without TLB + * corruption since we just change the spte from writable to + * readonly so that we only need to care the case of changing + * spte from present to present (changing the spte from present + * to nonpresent will flush all the TLBs immediately), in other + * words, the only case we care is mmu_spte_update() where we + * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE + * instead of PT_WRITABLE_MASK, that means it does not depend + * on PT_WRITABLE_MASK anymore. + */ + kvm_flush_remote_tlbs(kvm); } #define BATCH_ZAP_PAGES 10 diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 3842e70bdb7c..b982112d2ca5 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -104,6 +104,39 @@ static inline int is_present_gpte(unsigned long pte) return pte & PT_PRESENT_MASK; } +/* + * Currently, we have two sorts of write-protection, a) the first one + * write-protects guest page to sync the guest modification, b) another one is + * used to sync dirty bitmap when we do KVM_GET_DIRTY_LOG. The differences + * between these two sorts are: + * 1) the first case clears SPTE_MMU_WRITEABLE bit. + * 2) the first case requires flushing tlb immediately avoiding corrupting + * shadow page table between all vcpus so it should be in the protection of + * mmu-lock. And the another case does not need to flush tlb until returning + * the dirty bitmap to userspace since it only write-protects the page + * logged in the bitmap, that means the page in the dirty bitmap is not + * missed, so it can flush tlb out of mmu-lock. + * + * So, there is the problem: the first case can meet the corrupted tlb caused + * by another case which write-protects pages but without flush tlb + * immediately. In order to making the first case be aware this problem we let + * it flush tlb if we try to write-protect a spte whose SPTE_MMU_WRITEABLE bit + * is set, it works since another case never touches SPTE_MMU_WRITEABLE bit. + * + * Anyway, whenever a spte is updated (only permission and status bits are + * changed) we need to check whether the spte with SPTE_MMU_WRITEABLE becomes + * readonly, if that happens, we need to flush tlb. Fortunately, + * mmu_spte_update() has already handled it perfectly. + * + * The rules to use SPTE_MMU_WRITEABLE and PT_WRITABLE_MASK: + * - if we want to see if it has writable tlb entry or if the spte can be + * writable on the mmu mapping, check SPTE_MMU_WRITEABLE, this is the most + * case, otherwise + * - if we fix page fault on the spte or do write-protection by dirty logging, + * check PT_WRITABLE_MASK. + * + * TODO: introduce APIs to split these two cases. + */ static inline int is_writable_pte(unsigned long pte) { return pte & PT_WRITABLE_MASK; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 63a828d206c5..c5582c385bc0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3632,11 +3632,19 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) offset = i * BITS_PER_LONG; kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask); } - if (is_dirty) - kvm_flush_remote_tlbs(kvm); spin_unlock(&kvm->mmu_lock); + /* See the comments in kvm_mmu_slot_remove_write_access(). */ + lockdep_assert_held(&kvm->slots_lock); + + /* + * All the TLBs can be flushed out of mmu lock, see the comments in + * kvm_mmu_slot_remove_write_access(). + */ + if (is_dirty) + kvm_flush_remote_tlbs(kvm); + r = -EFAULT; if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n)) goto out; -- cgit v1.2.3 From 56a705a48eae9c474ba7f82af5c4ff5cf306f654 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Tue, 4 Mar 2014 18:51:47 +0100 Subject: ARM: mvebu: Add a SOC bus device entry Add the SoC Family, device ID and revision to /sys/bus/soc. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1393955507-26436-1-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/mvebu-soc-id.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 3f73eecbcfb0..475cf8a6d165 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -6,6 +6,7 @@ config ARCH_MVEBU select IRQ_DOMAIN select PINCTRL select PLAT_ORION + select SOC_BUS select MVEBU_MBUS select ZONE_DMA if ARM_LPAE select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c index f3d4cf53f746..874a7504818e 100644 --- a/arch/arm/mach-mvebu/mvebu-soc-id.c +++ b/arch/arm/mach-mvebu/mvebu-soc-id.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include #include "mvebu-soc-id.h" #define PCIE_DEV_ID_OFF 0x0 @@ -118,3 +120,31 @@ clk_err: } core_initcall(mvebu_soc_id_init); +static int __init mvebu_soc_device(void) +{ + struct soc_device_attribute *soc_dev_attr; + struct soc_device *soc_dev; + + /* Also protects against running on non-mvebu systems */ + if (!is_id_valid) + return 0; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = kasprintf(GFP_KERNEL, "Marvell"); + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", soc_rev); + soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%X", soc_dev_id); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->family); + kfree(soc_dev_attr->revision); + kfree(soc_dev_attr->soc_id); + kfree(soc_dev_attr); + } + + return 0; +} +postcore_initcall(mvebu_soc_device); -- cgit v1.2.3 From 983cd5238dd7b83651084ca6fe5274d1cc36ffa2 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 3 Apr 2014 12:30:13 -0300 Subject: ARM: mvebu: Enable nfsroot in the defconfig NFSroot is very frequently used by developers to boot, so let's make our lives simpler and enable it by default. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1396539014-8673-1-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/configs/mvebu_v7_defconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index a34713d8db9f..bfcc36204e03 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -29,6 +29,9 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_VFP=y CONFIG_NET=y CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y CONFIG_BT=y CONFIG_BT_MRVL=y CONFIG_BT_MRVL_SDIO=y @@ -103,6 +106,8 @@ CONFIG_UDF_FS=m CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y -- cgit v1.2.3 From ff0403f33b2e62f15109f40460e09401e553e6f5 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 3 Apr 2014 12:30:14 -0300 Subject: ARM: mvebu: enable fhandle in the defconfigs CONFIG_FHANDLE is required by systemd >= 210 to spawn a serial TTY. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1396539014-8673-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/configs/mvebu_v5_defconfig | 1 + arch/arm/configs/mvebu_v7_defconfig | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig index 36484a37a1ca..5d8ec15aefef 100644 --- a/arch/arm/configs/mvebu_v5_defconfig +++ b/arch/arm/configs/mvebu_v5_defconfig @@ -1,4 +1,5 @@ CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=19 diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index bfcc36204e03..b1e514e81134 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -1,5 +1,6 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y +CONFIG_FHANDLE=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 -- cgit v1.2.3 From 655220960f2256df5b86c21224518d05e6cc4f84 Mon Sep 17 00:00:00 2001 From: Adam Baker Date: Sun, 6 Apr 2014 22:42:47 +0100 Subject: ARM: kirkwood: Move NSA310 common parts to include file Move definitions that are common to both nsa-310.dts and nsa310a.dts and that will also be used in nsa320 into kirkwood-nsa310-common.dtsi. Also rename the USB Regulator to remove the word off from its name as the state of a regulator shouldn't be part of its name. Signed-off-by: Adam Baker Link: https://lkml.kernel.org/r/1396820569-3841-1-git-send-email-linux@baker-net.org.uk Reviewed-by: Andrew Lunn Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-nsa310-common.dtsi | 58 +++++++++++++++++++++++++-- arch/arm/boot/dts/kirkwood-nsa310.dts | 48 ---------------------- arch/arm/boot/dts/kirkwood-nsa310a.dts | 52 ------------------------ 3 files changed, 54 insertions(+), 104 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi index aa78c2d11fe7..843b8b561e5e 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi @@ -7,15 +7,40 @@ ocp@f1000000 { pinctrl: pinctrl@10000 { - pmx_usb_power_off: pmx-usb-power-off { + pmx_usb_power: pmx-usb-power { marvell,pins = "mpp21"; marvell,function = "gpio"; }; + pmx_pwr_off: pmx-pwr-off { marvell,pins = "mpp48"; marvell,function = "gpio"; }; + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_btn_copy: pmx-btn-copy { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_btn_power: pmx-btn-power { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_copy_green: pmx-led-copy-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_led_copy_red: pmx-led-copy-red { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; }; serial@12000 { @@ -43,17 +68,42 @@ gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; + + button@1 { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + button@2 { + label = "Copy Button"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + button@3 { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; + + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power_off>; + pinctrl-0 = <&pmx_usb_power>; pinctrl-names = "default"; - usb0_power_off: regulator@1 { + usb0_power: regulator@1 { compatible = "regulator-fixed"; reg = <1>; - regulator-name = "USB Power Off"; + regulator-name = "USB Power"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 03fa24cf3344..372f701d5338 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -59,26 +59,6 @@ marvell,function = "gpio"; }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_hdd_green: pmx-led-hdd-green { marvell,pins = "mpp41"; marvell,function = "gpio"; @@ -94,10 +74,6 @@ marvell,function = "gpio"; }; - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; }; i2c@11000 { @@ -110,30 +86,6 @@ }; }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - button@1 { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - gpio-leds { compatible = "gpio-leds"; pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index a5e779452867..ead7a36d1089 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -38,11 +38,6 @@ marvell,function = "gpio"; }; - pmx_usb_power_off: pmx-usb-power-off { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - pmx_led_sys_green: pmx-led-sys-green { marvell,pins = "mpp28"; marvell,function = "gpio"; @@ -53,26 +48,6 @@ marvell,function = "gpio"; }; - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - pmx_led_hdd_green: pmx-led-hdd-green { marvell,pins = "mpp41"; marvell,function = "gpio"; @@ -83,11 +58,6 @@ marvell,function = "gpio"; }; - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - }; i2c@11000 { @@ -100,28 +70,6 @@ }; }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - - button@1 { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - gpio-leds { compatible = "gpio-leds"; -- cgit v1.2.3 From be3d7d023b870d050eaec4ebaa3293fef432dc4b Mon Sep 17 00:00:00 2001 From: Adam Baker Date: Sun, 6 Apr 2014 22:42:48 +0100 Subject: ARM: kirkwood: Add DTS file for NSA320 Add a new DTS file to support the Zyxel NSA320 dual bay NAS Drive. This DTS just describes the features that work with the current kernel drivers. New drivers still need writing to support the temperature sensor, the power on behaviour control and the buzzer. Signed-off-by: Adam Baker Link: https://lkml.kernel.org/r/1396820569-3841-2-git-send-email-linux@baker-net.org.uk Reviewed-by: Andrew Lunn Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-nsa320.dts | 214 ++++++++++++++++++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-nsa320.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts new file mode 100644 index 000000000000..6c8f6923f5d7 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -0,0 +1,214 @@ +/* Device tree file for the Zyxel NSA 320 NAS box. + * + * Copyright (c) 2014, Adam Baker + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Based upon the board setup file created by Peter Schildmann */ + +/dts-v1/; + +#include "kirkwood-nsa310-common.dtsi" + +/ { + model = "Zyxel NSA320"; + compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + pinctrl-names = "default"; + + /* SATA Activity and Present pins are not connected */ + pmx_sata0: pmx-sata0 { + marvell,pins ; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins ; + marvell,function = "sata1"; + }; + + pmx_led_hdd2_green: pmx-led-hdd2-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_hdd2_red: pmx-led-hdd2-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_mcu_data: pmx-mcu-data { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_mcu_clk: pmx-mcu-clk { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_mcu_act: pmx-mcu-act { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_orange: pmx-led-sys-orange { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_green: pmx-led-hdd1-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_red: pmx-led-hdd1-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_htp: pmx-htp { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + /* Buzzer needs to be switched at around 1kHz so is + not compatible with the gpio-beeper driver. */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_vid_b1: pmx-vid-b1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_resume_data: pmx-power-resume-data { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_power_resume_clk: pmx-power-resume-clk { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + }; + + i2c@11000 { + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + regulators { + usb0_power: regulator@1 { + enable-active-high; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red + &pmx_led_usb_green + &pmx_led_sys_green &pmx_led_sys_orange + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa320:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + orange-sys { + label = "nsa320:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa320:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd1 { + label = "nsa320:red:hdd1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-hdd2 { + label = "nsa320:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-hdd2 { + label = "nsa320:red:hdd2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa320:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa320:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa320:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + }; + + /* The following pins are currently not assigned to a driver, + some of them should be configured as inputs. + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act + &pmx_htp &pmx_vid_b1 + &pmx_power_resume_data &pmx_power_resume_clk>; */ +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; -- cgit v1.2.3 From 76a93dc923e8e3441d03ecb89dfd080f259b9f8f Mon Sep 17 00:00:00 2001 From: Adam Baker Date: Tue, 8 Apr 2014 23:34:32 +0100 Subject: ARM: kirkwood: rename kirwood-nsa310-common to 3x0-common Rename the include file kirkwood-nsa310-common.dtsi as it is now also used for NSA320. There is also an NSA325 but that appears not to be as similar so is unlikely to want to share an include file. Signed-off-by: Adam Baker Link: https://lkml.kernel.org/r/53447978.2020206@baker-net.org.uk Acked-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-nsa310-common.dtsi | 157 -------------------------- arch/arm/boot/dts/kirkwood-nsa310.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa310a.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa320.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi | 157 ++++++++++++++++++++++++++ 5 files changed, 160 insertions(+), 160 deletions(-) delete mode 100644 arch/arm/boot/dts/kirkwood-nsa310-common.dtsi create mode 100644 arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi deleted file mode 100644 index 843b8b561e5e..000000000000 --- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi +++ /dev/null @@ -1,157 +0,0 @@ -#include "kirkwood.dtsi" -#include "kirkwood-6281.dtsi" - -/ { - model = "ZyXEL NSA310"; - - ocp@f1000000 { - pinctrl: pinctrl@10000 { - - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp21"; - marvell,function = "gpio"; - }; - - pmx_pwr_off: pmx-pwr-off { - marvell,pins = "mpp48"; - marvell,function = "gpio"; - }; - - pmx_btn_reset: pmx-btn-reset { - marvell,pins = "mpp36"; - marvell,function = "gpio"; - }; - - pmx_btn_copy: pmx-btn-copy { - marvell,pins = "mpp37"; - marvell,function = "gpio"; - }; - - pmx_btn_power: pmx-btn-power { - marvell,pins = "mpp46"; - marvell,function = "gpio"; - }; - - pmx_led_copy_green: pmx-led-copy-green { - marvell,pins = "mpp39"; - marvell,function = "gpio"; - }; - - pmx_led_copy_red: pmx-led-copy-red { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "ok"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - pinctrl-0 = <&pmx_pwr_off>; - pinctrl-names = "default"; - gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - }; - - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; - pinctrl-names = "default"; - - button@1 { - label = "Power Button"; - linux,code = ; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - button@2 { - label = "Copy Button"; - linux,code = ; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - }; - button@3 { - label = "Reset Button"; - linux,code = ; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - }; - }; - - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb0_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&nand { - status = "okay"; - chip-delay = <35>; - - partition@0 { - label = "uboot"; - reg = <0x0000000 0x0100000>; - read-only; - }; - partition@100000 { - label = "uboot_env"; - reg = <0x0100000 0x0080000>; - }; - partition@180000 { - label = "key_store"; - reg = <0x0180000 0x0080000>; - }; - partition@200000 { - label = "info"; - reg = <0x0200000 0x0080000>; - }; - partition@280000 { - label = "etc"; - reg = <0x0280000 0x0a00000>; - }; - partition@c80000 { - label = "kernel_1"; - reg = <0x0c80000 0x0a00000>; - }; - partition@1680000 { - label = "rootfs1"; - reg = <0x1680000 0x2fc0000>; - }; - partition@4640000 { - label = "kernel_2"; - reg = <0x4640000 0x0a00000>; - }; - partition@5040000 { - label = "rootfs2"; - reg = <0x5040000 0x2fc0000>; - }; -}; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 372f701d5338..989846ac6577 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "kirkwood-nsa310-common.dtsi" +#include "kirkwood-nsa3x0-common.dtsi" / { compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index ead7a36d1089..d0a602578f5b 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -1,6 +1,6 @@ /dts-v1/; -#include "kirkwood-nsa310-common.dtsi" +#include "kirkwood-nsa3x0-common.dtsi" /* * There are at least two different NSA310 designs. This variant does diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts index 6c8f6923f5d7..fc20baf0eade 100644 --- a/arch/arm/boot/dts/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -11,7 +11,7 @@ /dts-v1/; -#include "kirkwood-nsa310-common.dtsi" +#include "kirkwood-nsa3x0-common.dtsi" / { model = "Zyxel NSA320"; diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi new file mode 100644 index 000000000000..843b8b561e5e --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -0,0 +1,157 @@ +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "ZyXEL NSA310"; + + ocp@f1000000 { + pinctrl: pinctrl@10000 { + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_pwr_off: pmx-pwr-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_btn_copy: pmx-btn-copy { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_btn_power: pmx-btn-power { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_copy_green: pmx-led-copy-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_led_copy_red: pmx-led-copy-red { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "ok"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; + + button@1 { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + button@2 { + label = "Copy Button"; + linux,code = ; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + button@3 { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; + + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + usb0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x0100000>; + read-only; + }; + partition@100000 { + label = "uboot_env"; + reg = <0x0100000 0x0080000>; + }; + partition@180000 { + label = "key_store"; + reg = <0x0180000 0x0080000>; + }; + partition@200000 { + label = "info"; + reg = <0x0200000 0x0080000>; + }; + partition@280000 { + label = "etc"; + reg = <0x0280000 0x0a00000>; + }; + partition@c80000 { + label = "kernel_1"; + reg = <0x0c80000 0x0a00000>; + }; + partition@1680000 { + label = "rootfs1"; + reg = <0x1680000 0x2fc0000>; + }; + partition@4640000 { + label = "kernel_2"; + reg = <0x4640000 0x0a00000>; + }; + partition@5040000 { + label = "rootfs2"; + reg = <0x5040000 0x2fc0000>; + }; +}; -- cgit v1.2.3 From 13dacc562239b870e55daae89106f509d6ae9bda Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 14 Apr 2014 10:23:31 -0300 Subject: ARM: mvebu: Enable Armada 375 watchdog in the devicetree Add the DT nodes to enable the watchdog support available on Armada 375 SoC. Reviewed-by: Guenter Roeck Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1397481813-4962-8-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 3877693fb2d8..0bfa57b12434 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -320,6 +320,12 @@ clocks = <&coreclk 0>; }; + watchdog@20300 { + compatible = "marvell,armada-375-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; + clocks = <&coreclk 0>; + }; + xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 -- cgit v1.2.3 From 153a964a792beff01f38c041fb5c51433b0e0111 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 14 Apr 2014 10:23:32 -0300 Subject: ARM: mvebu: Enable Armada 380/385 watchdog in the devicetree Add the DT nodes to enable the watchdog support available on Armada 380/385 SoC. Reviewed-by: Guenter Roeck Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1397481813-4962-9-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index a064f59da02d..9a941967ab72 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -267,6 +267,13 @@ clock-names = "nbclk", "fixed"; }; + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; -- cgit v1.2.3 From 924d38f404936495b59ef7fa3ff232d978d64b18 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:46:59 +0200 Subject: ARM: mvebu: prepare coherency code to support more SOCs The code that handles the coherency fabric of Armada 370 and Armada XP in arch/arm/mach-mvebu/coherency.c made the assumption that there was only one type of coherency fabric. Unfortunately, it turns out that upcoming SoCs have a slightly different coherency unit. In preparation to the introduction of the coherency support for more SoCs, this commit: * Introduces a data associated to the compatible string in the compatible string match table, so that the code can differantiate the variant of coherency unit being used. * Separates the coherency unit initialization code into its own function. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../devicetree/bindings/arm/coherency-fabric.txt | 5 ++- arch/arm/mach-mvebu/coherency.c | 47 +++++++++++++++------- 2 files changed, 37 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt index 17d8cd107559..f0bfa37edfc6 100644 --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt @@ -4,7 +4,10 @@ Available on Marvell SOCs: Armada 370 and Armada XP Required properties: -- compatible: "marvell,coherency-fabric" +- compatible: the possible values are: + + * "marvell,coherency-fabric", to be used for the coherency fabric of + the Armada 370 and Armada XP. - reg: Should contain coherency fabric registers location and length. First pair for the coherency fabric registers, second pair diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 4e9d58148ca7..434cf5f90a80 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -38,8 +38,13 @@ static void __iomem *coherency_cpu_base; #define IO_SYNC_BARRIER_CTL_OFFSET 0x0 +enum { + COHERENCY_FABRIC_TYPE_ARMADA_370_XP, +}; + static struct of_device_id of_coherency_table[] = { - {.compatible = "marvell,coherency-fabric"}, + {.compatible = "marvell,coherency-fabric", + .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP }, { /* end of list */ }, }; @@ -121,26 +126,40 @@ static struct notifier_block mvebu_hwcc_platform_nb = { .notifier_call = mvebu_hwcc_platform_notifier, }; +static void __init armada_370_coherency_init(struct device_node *np) +{ + struct resource res; + + of_address_to_resource(np, 0, &res); + coherency_phys_base = res.start; + /* + * Ensure secondary CPUs will see the updated value, + * which they read before they join the coherency + * fabric, and therefore before they are coherent with + * the boot CPU cache. + */ + sync_cache_w(&coherency_phys_base); + coherency_base = of_iomap(np, 0); + coherency_cpu_base = of_iomap(np, 1); + set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); +} + int __init coherency_init(void) { struct device_node *np; np = of_find_matching_node(NULL, of_coherency_table); if (np) { - struct resource res; + const struct of_device_id *match = + of_match_node(of_coherency_table, np); + int type; + + type = (int) match->data; pr_info("Initializing Coherency fabric\n"); - of_address_to_resource(np, 0, &res); - coherency_phys_base = res.start; - /* - * Ensure secondary CPUs will see the updated value, - * which they read before they join the coherency - * fabric, and therefore before they are coherent with - * the boot CPU cache. - */ - sync_cache_w(&coherency_phys_base); - coherency_base = of_iomap(np, 0); - coherency_cpu_base = of_iomap(np, 1); - set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); + + if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) + armada_370_coherency_init(np); + of_node_put(np); } -- cgit v1.2.3 From 501f928e009760f4987d4630265bb9fff28a6ecc Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:00 +0200 Subject: ARM: mvebu: add a coherency_available() call This commit extends the coherency fabric code to provide a coherency_available()function that the SoC code can call to be told whether coherency support is available or not. On Armada 370/XP, coherency support is available as soon as the relevant DT node is present. On some upcoming SoCs, the DT node needs to be present *and* the system running with CONFIG_SMP enabled. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/coherency.c | 30 ++++++++++++++++++++++-------- arch/arm/mach-mvebu/coherency.h | 1 + 2 files changed, 23 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 434cf5f90a80..296cf14f08a4 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -39,6 +39,7 @@ static void __iomem *coherency_cpu_base; #define IO_SYNC_BARRIER_CTL_OFFSET 0x0 enum { + COHERENCY_FABRIC_TYPE_NONE, COHERENCY_FABRIC_TYPE_ARMADA_370_XP, }; @@ -144,7 +145,7 @@ static void __init armada_370_coherency_init(struct device_node *np) set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); } -int __init coherency_init(void) +static int coherency_type(void) { struct device_node *np; @@ -155,27 +156,40 @@ int __init coherency_init(void) int type; type = (int) match->data; - pr_info("Initializing Coherency fabric\n"); + /* Armada 370/XP coherency works in both UP and SMP */ if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) - armada_370_coherency_init(np); + return type; of_node_put(np); } - return 0; + return COHERENCY_FABRIC_TYPE_NONE; } -static int __init coherency_late_init(void) +int coherency_available(void) { + return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; +} + +int __init coherency_init(void) +{ + int type = coherency_type(); struct device_node *np; np = of_find_matching_node(NULL, of_coherency_table); - if (np) { + + if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) + armada_370_coherency_init(np); + + return 0; +} + +static int __init coherency_late_init(void) +{ + if (coherency_available()) bus_register_notifier(&platform_bus_type, &mvebu_hwcc_platform_nb); - of_node_put(np); - } return 0; } diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index 760226c41353..02f7ec34ced2 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -18,5 +18,6 @@ extern unsigned long coherency_phys_base; int set_cpu_coherent(unsigned int cpu_id, int smp_group_id); int coherency_init(void); +int coherency_available(void); #endif /* __MACH_370_XP_COHERENCY_H */ -- cgit v1.2.3 From 5686a1e5aa436c49187a60052d5885fb1f541ce6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:01 +0200 Subject: bus: mvebu: pass the coherency availability information at init time Until now, the mvebu-mbus was guessing by itself whether hardware I/O coherency was available or not by poking into the Device Tree to see if the coherency fabric Device Tree node was present or not. However, on some upcoming SoCs, the presence or absence of the coherency fabric DT node isn't sufficient: in CONFIG_SMP, the coherency can be enabled, but not in !CONFIG_SMP. In order to clean this up, the mvebu_mbus_dt_init() function is extended to get a boolean argument telling whether coherency is enabled or not. Therefore, the logic to decide whether coherency is available or not now belongs to the core SoC code instead of the mvebu-mbus driver itself, which is much better. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-kirkwood/board-dt.c | 2 +- arch/arm/mach-mvebu/board-v7.c | 2 +- arch/arm/mach-mvebu/dove.c | 2 +- arch/arm/mach-mvebu/kirkwood.c | 2 +- drivers/bus/mvebu-mbus.c | 11 +++-------- include/linux/mbus.h | 2 +- 6 files changed, 8 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 2801da49e2a3..ff18ff20f71f 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -195,7 +195,7 @@ static void __init kirkwood_dt_init(void) { kirkwood_disable_mbus_error_propagation(); - BUG_ON(mvebu_mbus_dt_init()); + BUG_ON(mvebu_mbus_dt_init(false)); #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_of_init(); diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index 333fca8fdc41..1730e0cdb6f6 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -58,7 +58,7 @@ static void __init mvebu_timer_and_clk_init(void) of_clk_init(NULL); clocksource_of_init(); coherency_init(); - BUG_ON(mvebu_mbus_dt_init()); + BUG_ON(mvebu_mbus_dt_init(coherency_available())); #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c index 5e5a43624237..b50464ec1130 100644 --- a/arch/arm/mach-mvebu/dove.c +++ b/arch/arm/mach-mvebu/dove.c @@ -23,7 +23,7 @@ static void __init dove_init(void) #ifdef CONFIG_CACHE_TAUROS2 tauros2_init(0); #endif - BUG_ON(mvebu_mbus_dt_init()); + BUG_ON(mvebu_mbus_dt_init(false)); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c index 120207fc36f1..a77e0bae9c55 100644 --- a/arch/arm/mach-mvebu/kirkwood.c +++ b/arch/arm/mach-mvebu/kirkwood.c @@ -169,7 +169,7 @@ static void __init kirkwood_dt_init(void) { kirkwood_disable_mbus_error_propagation(); - BUG_ON(mvebu_mbus_dt_init()); + BUG_ON(mvebu_mbus_dt_init(false)); #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_of_init(); diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index 293e2e0a0a87..ff02fc90fc21 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c @@ -694,7 +694,6 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, phys_addr_t sdramwins_phys_base, size_t sdramwins_size) { - struct device_node *np; int win; mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size); @@ -707,12 +706,6 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus, return -ENOMEM; } - np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"); - if (np) { - mbus->hw_io_coherency = 1; - of_node_put(np); - } - for (win = 0; win < mbus->soc->num_wins; win++) mvebu_mbus_disable_window(mbus, win); @@ -882,7 +875,7 @@ static void __init mvebu_mbus_get_pcie_resources(struct device_node *np, } } -int __init mvebu_mbus_dt_init(void) +int __init mvebu_mbus_dt_init(bool is_coherent) { struct resource mbuswins_res, sdramwins_res; struct device_node *np, *controller; @@ -920,6 +913,8 @@ int __init mvebu_mbus_dt_init(void) return -EINVAL; } + mbus_state.hw_io_coherency = is_coherent; + /* Get optional pcie-{mem,io}-aperture properties */ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture, &mbus_state.pcie_io_aperture); diff --git a/include/linux/mbus.h b/include/linux/mbus.h index 345b8c53b897..550c88fb0267 100644 --- a/include/linux/mbus.h +++ b/include/linux/mbus.h @@ -73,6 +73,6 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size); int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base, size_t mbus_size, phys_addr_t sdram_phys_base, size_t sdram_size); -int mvebu_mbus_dt_init(void); +int mvebu_mbus_dt_init(bool is_coherent); #endif /* __LINUX_MBUS_H */ -- cgit v1.2.3 From 5fbba0805165a4883c60cf159f272dd0d7205c44 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:02 +0200 Subject: ARM: mvebu: ARM: mvebu: use of_find_matching_node_and_match() in coherency.c In the mach-mvebu coherency code, instead of using of_find_matching_node() and then of_match_node(), directly use the of_find_matching_node_and_match() which does both at once. We take this opportunity to also simplify the initialization of the "type" variable. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/coherency.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 296cf14f08a4..862100f7c836 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -148,14 +148,11 @@ static void __init armada_370_coherency_init(struct device_node *np) static int coherency_type(void) { struct device_node *np; + const struct of_device_id *match; - np = of_find_matching_node(NULL, of_coherency_table); + np = of_find_matching_node_and_match(NULL, of_coherency_table, &match); if (np) { - const struct of_device_id *match = - of_match_node(of_coherency_table, np); - int type; - - type = (int) match->data; + int type = (int) match->data; /* Armada 370/XP coherency works in both UP and SMP */ if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) -- cgit v1.2.3 From 8e6ac20338228dc77c8f3538efb5a3aba712e0e5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:03 +0200 Subject: ARM: mvebu: enable the ARM SCU on Armada 375 and Armada 38x Contrary to the Armada 370 and XP that used the PJ4B Marvell cores, the Armada 375 and Armada 38x use the ARM Cortex-A9. A consequence of this is that the unit responsible for the coherency between CPUs is now the ARM SCU, and not the Marvell coherency unit (which is still present to do coherency with I/O devices). Therefore this commit: * Ensures that the selection of the Armada 375 or Armada 38x SoC support enables the ARM SCU support in the kernel. * Make sure to initialize the SCU at boot time. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 2 ++ arch/arm/mach-mvebu/board-v7.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 475cf8a6d165..736bd2cbc1f0 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -40,6 +40,7 @@ config MACH_ARMADA_375 select ARM_GIC select ARMADA_375_CLK select CPU_V7 + select HAVE_ARM_SCU select MACH_MVEBU_V7 select PINCTRL_ARMADA_375 help @@ -53,6 +54,7 @@ config MACH_ARMADA_38X select ARM_GIC select ARMADA_38X_CLK select CPU_V7 + select HAVE_ARM_SCU select MACH_MVEBU_V7 select PINCTRL_ARMADA_38X help diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index 1730e0cdb6f6..85f964e55bf3 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -27,11 +27,29 @@ #include #include #include +#include #include "armada-370-xp.h" #include "common.h" #include "coherency.h" #include "mvebu-soc-id.h" +/* + * Enables the SCU when available. Obviously, this is only useful on + * Cortex-A based SOCs, not on PJ4B based ones. + */ +static void __init mvebu_scu_enable(void) +{ + void __iomem *scu_base; + + struct device_node *np = + of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (np) { + scu_base = of_iomap(np, 0); + scu_enable(scu_base); + of_node_put(np); + } +} + /* * Early versions of Armada 375 SoC have a bug where the BootROM * leaves an external data abort pending. The kernel is hit by this @@ -57,6 +75,7 @@ static void __init mvebu_timer_and_clk_init(void) { of_clk_init(NULL); clocksource_of_init(); + mvebu_scu_enable(); coherency_init(); BUG_ON(mvebu_mbus_dt_init(coherency_available())); #ifdef CONFIG_CACHE_L2X0 -- cgit v1.2.3 From 77fa4b9ab0aafc0a06976814ad62aeff990dfd2c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:04 +0200 Subject: ARM: mvebu: add Armada 375 support to the coherency code The Armada 375, like the Armada 370 and Armada XP, has a coherency unit. However, unlike the coherency unit of 370/XP which does both CPU and I/O coherency, the one on Armada 735 only does I/O coherency. Therefore, instead of having two sets of registers (the first one being used mainly to register each CPU in the coherency fabric, the second one being used for the I/O coherency barrier), it has only one set of register (for the I/O coherency barrier). This commit adds a new "marvell,armada-375-coherency-fabric" compatible string for this variant of the coherency fabric. The custom DMA operations, and the way of triggering an I/O barrier is the same as Armada 370/XP, so the code changes are minimal. However, the set_cpu_coherent() function is not needed on Armada 375 and will not work. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../devicetree/bindings/arm/coherency-fabric.txt | 22 ++++++++++++++++++---- arch/arm/mach-mvebu/coherency.c | 14 ++++++++++++++ 2 files changed, 32 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt index f0bfa37edfc6..dcd80d6e0471 100644 --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt @@ -1,6 +1,6 @@ Coherency fabric ---------------- -Available on Marvell SOCs: Armada 370 and Armada XP +Available on Marvell SOCs: Armada 370, Armada 375 and Armada XP Required properties: @@ -9,11 +9,20 @@ Required properties: * "marvell,coherency-fabric", to be used for the coherency fabric of the Armada 370 and Armada XP. + * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency + fabric. + - reg: Should contain coherency fabric registers location and - length. First pair for the coherency fabric registers, second pair - for the per-CPU fabric registers registers. + length. + + * For "marvell,coherency-fabric", the first pair for the coherency + fabric registers, second pair for the per-CPU fabric registers. + + * For "marvell,armada-375-coherency-fabric", only one pair is needed + for the per-CPU fabric registers. -Example: + +Examples: coherency-fabric@d0020200 { compatible = "marvell,coherency-fabric"; @@ -22,3 +31,8 @@ coherency-fabric@d0020200 { }; +coherency-fabric@21810 { + compatible = "marvell,armada-375-coherency-fabric"; + reg = <0x21810 0x1c>; +}; + diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 862100f7c836..7ccaf87fd772 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -41,11 +41,14 @@ static void __iomem *coherency_cpu_base; enum { COHERENCY_FABRIC_TYPE_NONE, COHERENCY_FABRIC_TYPE_ARMADA_370_XP, + COHERENCY_FABRIC_TYPE_ARMADA_375, }; static struct of_device_id of_coherency_table[] = { {.compatible = "marvell,coherency-fabric", .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP }, + {.compatible = "marvell,armada-375-coherency-fabric", + .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 }, { /* end of list */ }, }; @@ -145,6 +148,11 @@ static void __init armada_370_coherency_init(struct device_node *np) set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); } +static void __init armada_375_coherency_init(struct device_node *np) +{ + coherency_cpu_base = of_iomap(np, 0); +} + static int coherency_type(void) { struct device_node *np; @@ -158,6 +166,10 @@ static int coherency_type(void) if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) return type; + /* Armada 375 coherency works only on SMP */ + else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp()) + return type; + of_node_put(np); } @@ -178,6 +190,8 @@ int __init coherency_init(void) if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) armada_370_coherency_init(np); + else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) + armada_375_coherency_init(np); return 0; } -- cgit v1.2.3 From 5ab5afd8ba837560f76f8ee527271d2e819bcaef Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:05 +0200 Subject: ARM: mvebu: implement Armada 375 coherency workaround The early revisions of Armada 375 SOCs (Z1 stepping) have a bug in the I/O coherency unit that prevents using the normal method for the I/O coherency barrier. The recommended workaround is to use a XOR memset transfer to act as the I/O coherency barrier. This involves "borrowing" a XOR engine, which gets disabled in the Device Tree so the normal XOR driver doesn't use it. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/coherency.c | 168 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 165 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 7ccaf87fd772..75db33ef93ee 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -17,6 +17,8 @@ * supplies basic routines for configuring and controlling hardware coherency */ +#define pr_fmt(fmt) "mvebu-coherency: " fmt + #include #include #include @@ -24,6 +26,9 @@ #include #include #include +#include +#include +#include #include #include #include "armada-370-xp.h" @@ -66,8 +71,157 @@ int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id) return ll_set_cpu_coherent(coherency_base, hw_cpu_id); } +/* + * The below code implements the I/O coherency workaround on Armada + * 375. This workaround consists in using the two channels of the + * first XOR engine to trigger a XOR transaction that serves as the + * I/O coherency barrier. + */ + +static void __iomem *xor_base, *xor_high_base; +static dma_addr_t coherency_wa_buf_phys[CONFIG_NR_CPUS]; +static void *coherency_wa_buf[CONFIG_NR_CPUS]; +static bool coherency_wa_enabled; + +#define XOR_CONFIG(chan) (0x10 + (chan * 4)) +#define XOR_ACTIVATION(chan) (0x20 + (chan * 4)) +#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2)) +#define WINDOW_BASE(w) (0x250 + ((w) << 2)) +#define WINDOW_SIZE(w) (0x270 + ((w) << 2)) +#define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2)) +#define WINDOW_OVERRIDE_CTRL(chan) (0x2A0 + ((chan) << 2)) +#define XOR_DEST_POINTER(chan) (0x2B0 + (chan * 4)) +#define XOR_BLOCK_SIZE(chan) (0x2C0 + (chan * 4)) +#define XOR_INIT_VALUE_LOW 0x2E0 +#define XOR_INIT_VALUE_HIGH 0x2E4 + +static inline void mvebu_hwcc_armada375_sync_io_barrier_wa(void) +{ + int idx = smp_processor_id(); + + /* Write '1' to the first word of the buffer */ + writel(0x1, coherency_wa_buf[idx]); + + /* Wait until the engine is idle */ + while ((readl(xor_base + XOR_ACTIVATION(idx)) >> 4) & 0x3) + ; + + dmb(); + + /* Trigger channel */ + writel(0x1, xor_base + XOR_ACTIVATION(idx)); + + /* Poll the data until it is cleared by the XOR transaction */ + while (readl(coherency_wa_buf[idx])) + ; +} + +static void __init armada_375_coherency_init_wa(void) +{ + const struct mbus_dram_target_info *dram; + struct device_node *xor_node; + struct property *xor_status; + struct clk *xor_clk; + u32 win_enable = 0; + int i; + + pr_warn("enabling coherency workaround for Armada 375 Z1, one XOR engine disabled\n"); + + /* + * Since the workaround uses one XOR engine, we grab a + * reference to its Device Tree node first. + */ + xor_node = of_find_compatible_node(NULL, NULL, "marvell,orion-xor"); + BUG_ON(!xor_node); + + /* + * Then we mark it as disabled so that the real XOR driver + * will not use it. + */ + xor_status = kzalloc(sizeof(struct property), GFP_KERNEL); + BUG_ON(!xor_status); + + xor_status->value = kstrdup("disabled", GFP_KERNEL); + BUG_ON(!xor_status->value); + + xor_status->length = 8; + xor_status->name = kstrdup("status", GFP_KERNEL); + BUG_ON(!xor_status->name); + + of_update_property(xor_node, xor_status); + + /* + * And we remap the registers, get the clock, and do the + * initial configuration of the XOR engine. + */ + xor_base = of_iomap(xor_node, 0); + xor_high_base = of_iomap(xor_node, 1); + + xor_clk = of_clk_get_by_name(xor_node, NULL); + BUG_ON(!xor_clk); + + clk_prepare_enable(xor_clk); + + dram = mv_mbus_dram_info(); + + for (i = 0; i < 8; i++) { + writel(0, xor_base + WINDOW_BASE(i)); + writel(0, xor_base + WINDOW_SIZE(i)); + if (i < 4) + writel(0, xor_base + WINDOW_REMAP_HIGH(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel((cs->base & 0xffff0000) | + (cs->mbus_attr << 8) | + dram->mbus_dram_target_id, xor_base + WINDOW_BASE(i)); + writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i)); + + win_enable |= (1 << i); + win_enable |= 3 << (16 + (2 * i)); + } + + writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0)); + writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1)); + writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0)); + writel(0, xor_base + WINDOW_OVERRIDE_CTRL(1)); + + for (i = 0; i < CONFIG_NR_CPUS; i++) { + coherency_wa_buf[i] = kzalloc(PAGE_SIZE, GFP_KERNEL); + BUG_ON(!coherency_wa_buf[i]); + + /* + * We can't use the DMA mapping API, since we don't + * have a valid 'struct device' pointer + */ + coherency_wa_buf_phys[i] = + virt_to_phys(coherency_wa_buf[i]); + BUG_ON(!coherency_wa_buf_phys[i]); + + /* + * Configure the XOR engine for memset operation, with + * a 128 bytes block size + */ + writel(0x444, xor_base + XOR_CONFIG(i)); + writel(128, xor_base + XOR_BLOCK_SIZE(i)); + writel(coherency_wa_buf_phys[i], + xor_base + XOR_DEST_POINTER(i)); + } + + writel(0x0, xor_base + XOR_INIT_VALUE_LOW); + writel(0x0, xor_base + XOR_INIT_VALUE_HIGH); + + coherency_wa_enabled = true; +} + static inline void mvebu_hwcc_sync_io_barrier(void) { + if (coherency_wa_enabled) { + mvebu_hwcc_armada375_sync_io_barrier_wa(); + return; + } + writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET); while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1); } @@ -198,9 +352,17 @@ int __init coherency_init(void) static int __init coherency_late_init(void) { - if (coherency_available()) - bus_register_notifier(&platform_bus_type, - &mvebu_hwcc_platform_nb); + int type = coherency_type(); + + if (type == COHERENCY_FABRIC_TYPE_NONE) + return 0; + + if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) + armada_375_coherency_init_wa(); + + bus_register_notifier(&platform_bus_type, + &mvebu_hwcc_platform_nb); + return 0; } -- cgit v1.2.3 From d0de9323822fada543f2f244eb67f520aa21ed77 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:06 +0200 Subject: ARM: mvebu: add Armada 38x support to the coherency code The Armada 38x has a coherency unit that is similar to the one of the Armada 375 SoC, except that it does not have the bug of the Armada 375 coherency unit that requires the XOR based workaround. This commit therefore extends the Marvell EBU coherency code with a new compatible string to support the Armada 38x coherency unit. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- Documentation/devicetree/bindings/arm/coherency-fabric.txt | 7 ++++++- arch/arm/mach-mvebu/coherency.c | 14 +++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt index dcd80d6e0471..8dd46617c889 100644 --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt @@ -1,6 +1,6 @@ Coherency fabric ---------------- -Available on Marvell SOCs: Armada 370, Armada 375 and Armada XP +Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP Required properties: @@ -12,6 +12,9 @@ Required properties: * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency fabric. + * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency + fabric. + - reg: Should contain coherency fabric registers location and length. @@ -21,6 +24,8 @@ Required properties: * For "marvell,armada-375-coherency-fabric", only one pair is needed for the per-CPU fabric registers. + * For "marvell,armada-380-coherency-fabric", only one pair is needed + for the per-CPU fabric registers. Examples: diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 75db33ef93ee..489edd157cfb 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -47,6 +47,7 @@ enum { COHERENCY_FABRIC_TYPE_NONE, COHERENCY_FABRIC_TYPE_ARMADA_370_XP, COHERENCY_FABRIC_TYPE_ARMADA_375, + COHERENCY_FABRIC_TYPE_ARMADA_380, }; static struct of_device_id of_coherency_table[] = { @@ -54,6 +55,8 @@ static struct of_device_id of_coherency_table[] = { .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP }, {.compatible = "marvell,armada-375-coherency-fabric", .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 }, + {.compatible = "marvell,armada-380-coherency-fabric", + .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 }, { /* end of list */ }, }; @@ -302,7 +305,7 @@ static void __init armada_370_coherency_init(struct device_node *np) set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); } -static void __init armada_375_coherency_init(struct device_node *np) +static void __init armada_375_380_coherency_init(struct device_node *np) { coherency_cpu_base = of_iomap(np, 0); } @@ -324,6 +327,10 @@ static int coherency_type(void) else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp()) return type; + /* Armada 380 coherency works only on SMP */ + else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp()) + return type; + of_node_put(np); } @@ -344,8 +351,9 @@ int __init coherency_init(void) if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) armada_370_coherency_init(np); - else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) - armada_375_coherency_init(np); + else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 || + type == COHERENCY_FABRIC_TYPE_ARMADA_380) + armada_375_380_coherency_init(np); return 0; } -- cgit v1.2.3 From 6a8a57f2f06c3d2e1381767861ebfe9bd93ca2b9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:07 +0200 Subject: ARM: mvebu: enable the coherency fabric on Armada 375 This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 375. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 0bfa57b12434..782ba4d56a26 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -128,6 +128,11 @@ cache-level = <2>; }; + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; @@ -326,6 +331,11 @@ clocks = <&coreclk 0>; }; + coherency-fabric@21010 { + compatible = "marvell,armada-375-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 -- cgit v1.2.3 From 964a6156d305c31e71a3041ffc13f460d58b2e7f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:08 +0200 Subject: ARM: mvebu: enable the coherency fabric on Armada 38x This commit adds the necessary Device Tree information to enable the coherency fabric on Armada 38x. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 9a941967ab72..a123ef614468 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -108,6 +108,11 @@ cache-level = <2>; }; + scu@c000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc000 0x58>; + }; + timer@c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xc600 0x20>; @@ -274,6 +279,11 @@ clock-names = "nbclk", "fixed"; }; + coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; -- cgit v1.2.3 From 3f20fb1153b374737acd40d42cb3cab2ae5dae35 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:50:28 +0200 Subject: ARM: mvebu: introduce CPU reset code The Armada 370 and Armada XP have registers that allow to reset the CPUs, which is particularly useful to take the secondary CPUs out of reset in the context of the SMP support. Unfortunately, an implementation mistake was originally made and the support for these registers was integrated into the PMSU driver, which is in fact completely unrelated. And it turns out that the Armada 375 has the same CPU reset registers, but does not have the PMSU registers. Therefore, this commit creates a small CPU reset driver. All it does is provide a simple mvebu_cpu_reset_deassert() function that the SMP support code can call to take secondary CPUs out of reset. As of this commit, the driver isn't being used, it will be used through changes in the following commits. Note that we initially planned to use the 'reset controller' framework, but it requires the addition of "resets" properties in the Device Tree, which are causing too many problems if we want to keep the Device Tree backward compatibility. Moreover, the 'reset controller' framework is mainly useful when a device driver needs to request a reset of its device from a separate reset controller. In our case, the CPU reset handling and the SMP core code are both located in arch/arm/mach-mvebu/ and are tightly linked together, so there's no real benefit in going through a separate framework. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483433-25836-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../devicetree/bindings/arm/armada-cpu-reset.txt | 14 ++++ arch/arm/mach-mvebu/Makefile | 2 +- arch/arm/mach-mvebu/common.h | 1 + arch/arm/mach-mvebu/cpu-reset.c | 82 ++++++++++++++++++++++ 4 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/armada-cpu-reset.txt create mode 100644 arch/arm/mach-mvebu/cpu-reset.c (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt b/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt new file mode 100644 index 000000000000..b63a7b6ab998 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt @@ -0,0 +1,14 @@ +Marvell Armada CPU reset controller +=================================== + +Required properties: + +- compatible: Should be "marvell,armada-370-cpu-reset". + +- reg: should be register base and length as documented in the + datasheet for the CPU reset registers + +cpurst: cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x20>; +}; diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index a63e43b6b451..f9cfab05c5f9 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -3,7 +3,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a -obj-y += system-controller.o mvebu-soc-id.o +obj-y += system-controller.o mvebu-soc-id.o cpu-reset.o obj-$(CONFIG_MACH_MVEBU_V7) += board-v7.o obj-$(CONFIG_MACH_DOVE) += dove.o obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index 55449c487c9e..cfb129b144c0 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -18,6 +18,7 @@ #include void mvebu_restart(enum reboot_mode mode, const char *cmd); +int mvebu_cpu_reset_deassert(int cpu); void armada_xp_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c new file mode 100644 index 000000000000..4ff4ce77f8b6 --- /dev/null +++ b/arch/arm/mach-mvebu/cpu-reset.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2014 Marvell + * + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define pr_fmt(fmt) "mvebu-cpureset: " fmt + +#include +#include +#include +#include +#include +#include "armada-370-xp.h" + +static void __iomem *cpu_reset_base; +static size_t cpu_reset_size; + +#define CPU_RESET_OFFSET(cpu) (cpu * 0x8) +#define CPU_RESET_ASSERT BIT(0) + +int mvebu_cpu_reset_deassert(int cpu) +{ + u32 reg; + + if (!cpu_reset_base) + return -ENODEV; + + if (CPU_RESET_OFFSET(cpu) >= cpu_reset_size) + return -EINVAL; + + reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu)); + reg &= ~CPU_RESET_ASSERT; + writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu)); + + return 0; +} + +static int __init mvebu_cpu_reset_init(void) +{ + struct device_node *np; + struct resource res; + int ret = 0; + + np = of_find_compatible_node(NULL, NULL, + "marvell,armada-370-cpu-reset"); + if (!np) + return 0; + + if (of_address_to_resource(np, 0, &res)) { + pr_err("unable to get resource\n"); + ret = -ENOENT; + goto out; + } + + if (!request_mem_region(res.start, resource_size(&res), + np->full_name)) { + pr_err("unable to request region\n"); + ret = -EBUSY; + goto out; + } + + cpu_reset_base = ioremap(res.start, resource_size(&res)); + if (!cpu_reset_base) { + pr_err("unable to map registers\n"); + release_mem_region(res.start, resource_size(&res)); + ret = -ENOMEM; + goto out; + } + + cpu_reset_size = resource_size(&res); + +out: + of_node_put(np); + return ret; +} + +early_initcall(mvebu_cpu_reset_init); -- cgit v1.2.3 From 49754ffef5dca1d212e5fea5957a2a164585e92c Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:50:29 +0200 Subject: ARM: mvebu: start using the CPU reset driver This commit changes the PMSU driver to no longer map itself the CPU reset registers, and instead call into the CPU reset driver to deassert the secondary CPUs for SMP booting. In order to provide Device Tree backward compatibility, the CPU reset driver is extended to not only support its official compatible string "marvell,armada-370-cpu-reset", but to also look at the PMSU compatible string "marvell,armada-370-xp-pmsu" to find the CPU reset registers address. This allows old Device Tree to work correctly with newer kernel versions. Therefore, the CPU reset driver implements the following logic: * If one of the normal compatible strings "marvell,armada-370-cpu-reset" is found, then we map its first memory resource as the CPU reset registers. * Otherwise, if none of the normal compatible strings have been found, we look for the "marvell,armada-370-xp-pmsu" compatible string, and we map the second memory as the CPU reset registers. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483433-25836-3-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/cpu-reset.c | 53 ++++++++++++++++++++++++++++------------- arch/arm/mach-mvebu/pmsu.c | 20 ++++++++-------- 2 files changed, 47 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c index 4ff4ce77f8b6..4a8f9eebebea 100644 --- a/arch/arm/mach-mvebu/cpu-reset.c +++ b/arch/arm/mach-mvebu/cpu-reset.c @@ -40,42 +40,63 @@ int mvebu_cpu_reset_deassert(int cpu) return 0; } -static int __init mvebu_cpu_reset_init(void) +static int mvebu_cpu_reset_map(struct device_node *np, int res_idx) { - struct device_node *np; struct resource res; - int ret = 0; - - np = of_find_compatible_node(NULL, NULL, - "marvell,armada-370-cpu-reset"); - if (!np) - return 0; - if (of_address_to_resource(np, 0, &res)) { + if (of_address_to_resource(np, res_idx, &res)) { pr_err("unable to get resource\n"); - ret = -ENOENT; - goto out; + return -ENOENT; } if (!request_mem_region(res.start, resource_size(&res), np->full_name)) { pr_err("unable to request region\n"); - ret = -EBUSY; - goto out; + return -EBUSY; } cpu_reset_base = ioremap(res.start, resource_size(&res)); if (!cpu_reset_base) { pr_err("unable to map registers\n"); release_mem_region(res.start, resource_size(&res)); - ret = -ENOMEM; - goto out; + return -ENOMEM; } cpu_reset_size = resource_size(&res); -out: + return 0; +} + +int __init mvebu_cpu_reset_init(void) +{ + struct device_node *np; + int res_idx; + int ret; + + np = of_find_compatible_node(NULL, NULL, + "marvell,armada-370-cpu-reset"); + if (np) { + res_idx = 0; + } else { + /* + * This code is kept for backward compatibility with + * old Device Trees. + */ + np = of_find_compatible_node(NULL, NULL, + "marvell,armada-370-xp-pmsu"); + if (np) { + pr_warn(FW_WARN "deprecated pmsu binding\n"); + res_idx = 1; + } + } + + /* No reset node found */ + if (!np) + return -ENODEV; + + ret = mvebu_cpu_reset_map(np, res_idx); of_node_put(np); + return ret; } diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index d71ef53107c4..1807639173b1 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -21,14 +21,14 @@ #include #include #include +#include #include +#include "common.h" #include "pmsu.h" static void __iomem *pmsu_mp_base; -static void __iomem *pmsu_reset_base; #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x24) -#define PMSU_RESET_CTL_OFFSET(cpu) (cpu * 0x8) static struct of_device_id of_pmsu_table[] = { {.compatible = "marvell,armada-370-xp-pmsu"}, @@ -38,11 +38,11 @@ static struct of_device_id of_pmsu_table[] = { #ifdef CONFIG_SMP int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) { - int reg, hw_cpu; + int hw_cpu, ret; - if (!pmsu_mp_base || !pmsu_reset_base) { + if (!pmsu_mp_base) { pr_warn("Can't boot CPU. PMSU is uninitialized\n"); - return 1; + return -ENODEV; } hw_cpu = cpu_logical_map(cpu_id); @@ -50,10 +50,11 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) writel(virt_to_phys(boot_addr), pmsu_mp_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); - /* Release CPU from reset by clearing reset bit*/ - reg = readl(pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu)); - reg &= (~0x1); - writel(reg, pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu)); + ret = mvebu_cpu_reset_deassert(hw_cpu); + if (ret) { + pr_warn("unable to boot CPU: %d\n", ret); + return ret; + } return 0; } @@ -67,7 +68,6 @@ static int __init armada_370_xp_pmsu_init(void) if (np) { pr_info("Initializing Power Management Service Unit\n"); pmsu_mp_base = of_iomap(np, 0); - pmsu_reset_base = of_iomap(np, 1); of_node_put(np); } -- cgit v1.2.3 From bd045a1ebb48e5901508574188404d9bd3bdd72f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:50:30 +0200 Subject: ARM: mvebu: improve PMSU driver to request its resource Until now, the PMSU driver was using of_iomap() to map its registers, but of_iomap() doesn't call request_mem_region(). This commit fixes the memory mapping code of the PMSU to do so, which will also be useful for a later commit since we will need to adjust the resource base address and size for Device Tree backward compatibility. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483433-25836-4-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Gregory CLEMENT Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/pmsu.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 1807639173b1..b337fe56bae5 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -16,6 +16,8 @@ * other SOC units */ +#define pr_fmt(fmt) "mvebu-pmsu: " fmt + #include #include #include @@ -63,15 +65,39 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) static int __init armada_370_xp_pmsu_init(void) { struct device_node *np; + struct resource res; + int ret = 0; np = of_find_matching_node(NULL, of_pmsu_table); - if (np) { - pr_info("Initializing Power Management Service Unit\n"); - pmsu_mp_base = of_iomap(np, 0); - of_node_put(np); + if (!np) + return 0; + + pr_info("Initializing Power Management Service Unit\n"); + + if (of_address_to_resource(np, 0, &res)) { + pr_err("unable to get resource\n"); + ret = -ENOENT; + goto out; } - return 0; + if (!request_mem_region(res.start, resource_size(&res), + np->full_name)) { + pr_err("unable to request region\n"); + ret = -EBUSY; + goto out; + } + + pmsu_mp_base = ioremap(res.start, resource_size(&res)); + if (!pmsu_mp_base) { + pr_err("unable to map registers\n"); + release_mem_region(res.start, resource_size(&res)); + ret = -ENOMEM; + goto out; + } + + out: + of_node_put(np); + return ret; } early_initcall(armada_370_xp_pmsu_init); -- cgit v1.2.3 From 0c3acc746d2cd84c3654b6cc07eda2411584f4af Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 14 Apr 2014 15:50:31 +0200 Subject: ARM: mvebu: extend the PMSU registers The initial binding for PMSU was wrong, as it didn't take into account all the registers from the PMSU and moreover it referred to the CPU reset registers which are not part of PMSU. The Power Management Unit Service block also controls the Coherency Fabric subsystem. These registers are needed for the CPU idle implementation for the Armada 370/XP, it allows to enter a deep CPU idle state where the Coherency Fabric and the L2 cache are powered down. This commit adds support for a new compatible for the PMSU node which includes the registers related to the coherency fabric. It also keeps compatibility with the old compatible string. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397483433-25836-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483433-25836-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../devicetree/bindings/arm/armada-370-xp-pmsu.txt | 14 ++++++-------- arch/arm/mach-mvebu/pmsu.c | 14 ++++++++++++-- 2 files changed, 18 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt index 926b4d6aae7e..976188770079 100644 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt @@ -4,17 +4,15 @@ Available on Marvell SOCs: Armada 370 and Armada XP Required properties: -- compatible: "marvell,armada-370-xp-pmsu" +- compatible: should be "marvell,armada-370-pmsu", whereas + "marvell,armada-370-xp-pmsu" is deprecated and will be removed -- reg: Should contain PMSU registers location and length. First pair - for the per-CPU SW Reset Control registers, second pair for the - Power Management Service Unit. +- reg: Should contain PMSU registers location and length. Example: -armada-370-xp-pmsu@d0022000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0xd0022100 0x430>, - <0xd0020800 0x20>; +armada-370-xp-pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; }; diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index b337fe56bae5..4ae3ea1af7c3 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -30,10 +30,14 @@ static void __iomem *pmsu_mp_base; -#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x24) +#define PMSU_BASE_OFFSET 0x100 +#define PMSU_REG_SIZE 0x1000 + +#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) static struct of_device_id of_pmsu_table[] = { - {.compatible = "marvell,armada-370-xp-pmsu"}, + { .compatible = "marvell,armada-370-pmsu", }, + { .compatible = "marvell,armada-370-xp-pmsu", }, { /* end of list */ }, }; @@ -80,6 +84,12 @@ static int __init armada_370_xp_pmsu_init(void) goto out; } + if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) { + pr_warn(FW_WARN "deprecated pmsu binding\n"); + res.start = res.start - PMSU_BASE_OFFSET; + res.end = res.start + PMSU_REG_SIZE - 1; + } + if (!request_mem_region(res.start, resource_size(&res), np->full_name)) { pr_err("unable to request region\n"); -- cgit v1.2.3 From 02e7b06795fc129e45ed39983673efbb05d69506 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 14 Apr 2014 15:50:33 +0200 Subject: ARM: mvebu: use a separate function to set the boot address of CPUs Setting the start (or boot) address of a CPU is no more used only during SMP bring up on Armada 370/XP, but it will also be used by the CPU idle function of Armada XP, and by the Armada 38x SMP support. Therefore this commit creates a separate PMSU function to set the boot address of a CPU with the PMSU. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397483433-25836-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483433-25836-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/pmsu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 4ae3ea1af7c3..8361281f9180 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -41,6 +41,12 @@ static struct of_device_id of_pmsu_table[] = { { /* end of list */ }, }; +static void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) +{ + writel(virt_to_phys(boot_addr), pmsu_mp_base + + PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); +} + #ifdef CONFIG_SMP int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) { @@ -53,8 +59,7 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) hw_cpu = cpu_logical_map(cpu_id); - writel(virt_to_phys(boot_addr), pmsu_mp_base + - PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); + mvebu_pmsu_set_cpu_boot_addr(hw_cpu, boot_addr); ret = mvebu_cpu_reset_deassert(hw_cpu); if (ret) { -- cgit v1.2.3 From b6249d4b36874915c65827d90b942786f72d80b3 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 14 Apr 2014 15:50:32 +0200 Subject: ARM: mvebu: switch to the new PMSU binding in Armada 370/XP Device Tree Following the introduction of the new PMSU Device Tree binding, as well as the separate CPU reset binding, this commit switches the Armada 370 and Armada XP Device Trees to use them. The PMSU node is moved from the Armada XP specific armada-xp.dtsi to the common Armada 370/XP armada-370-xp.dtsi because the PMSU is in fact available at the same location on both SOCs. The CPU reset node is then added on both Armada 370 and Armada XP, with a different compatible string. On Armada 370, the CPU reset driver is not really needed as Armada 370 is single core and the only use of the CPU reset driver is to boot secondary processors, but it still makes sense to have this CPU reset register described in the Device Tree. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397483433-25836-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483433-25836-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++ arch/arm/boot/dts/armada-370.dtsi | 5 +++++ arch/arm/boot/dts/armada-xp.dtsi | 6 +++--- 3 files changed, 13 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index bbb40f62037d..10d778605ea7 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -203,6 +203,11 @@ reg = <0x20300 0x34>, <0x20704 0x4>; }; + pmsu@22000 { + compatible = "marvell,armada-370-pmsu"; + reg = <0x22000 0x1000>; + }; + usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x500>; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index af1f11e9e5a0..21b588b6f6bd 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -220,6 +220,11 @@ clocks = <&coreclk 2>; }; + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x8>; + }; + audio_controller: audio-controller@30000 { compatible = "marvell,armada370-audio"; reg = <0x30000 0x4000>; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index abb9f9dcc525..0a7dff6519ce 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -117,9 +117,9 @@ clock-names = "nbclk", "fixed"; }; - armada-370-xp-pmsu@22000 { - compatible = "marvell,armada-370-xp-pmsu"; - reg = <0x22100 0x400>, <0x20800 0x20>; + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x20>; }; eth2: ethernet@30000 { -- cgit v1.2.3 From 231578565d865e30fa175256f6c9fcd5d6f00808 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:54:00 +0200 Subject: ARM: mvebu: add enable-method property for CPUs This commit updates the Armada XP Device Trees (for the three variants of Armada XP) to declare the "enable-method" property for the CPUs, which helps operating systems find the appropriate logic to manage the CPUs, especially to boot secondary CPUs. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483648-26611-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-mv78230.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 1 + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 98335fb34b7a..1257ff1ed278 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -27,6 +27,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 9480cf891f8c..3396b25b39e1 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -29,6 +29,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 31ba6d8fbadf..6da84bf40aaf 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -30,6 +30,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-xp-smp"; cpu@0 { device_type = "cpu"; -- cgit v1.2.3 From 42eae5a41fdaea1f50ea610f769c147158bc5f6e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 14 Apr 2014 15:54:07 +0200 Subject: ARM: mvebu: add SMP support in the Armada 375 device tree Improve the Armada 375 Device Tree to add the CPU reset Device Tree node and declare the enabling method for CPUs, both of which are necessary to get SMP working. Signed-off-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397483648-26611-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483648-26611-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 782ba4d56a26..a7e0d543dff1 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -39,6 +39,8 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-375-smp"; + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; @@ -331,6 +333,11 @@ clocks = <&coreclk 0>; }; + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + coherency-fabric@21010 { compatible = "marvell,armada-375-coherency-fabric"; reg = <0x21010 0x1c>; -- cgit v1.2.3 From 19b06d7fd0716a4011a9c46d594c1ecf6e2548b1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:54:08 +0200 Subject: ARM: mvebu: add SMP support in the Armada 38x device tree This commit improves the Armada 38x Device Tree to add the CPU reset and PMSU Device Tree nodes as well as the declaration of the enabling method for the CPUs. These are needed to get SMP working on Armada 38x platforms. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483648-26611-12-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-380.dtsi | 2 ++ arch/arm/boot/dts/armada-385.dtsi | 2 ++ arch/arm/boot/dts/armada-38x.dtsi | 10 ++++++++++ 3 files changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index 068031f0f263..aa71718b549d 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -21,6 +21,8 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index e2919f02e1d4..2c7990d6efa2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -21,6 +21,8 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index a123ef614468..2e1661f1c30e 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -279,11 +279,21 @@ clock-names = "nbclk", "fixed"; }; + cpurst@20800 { + compatible = "marvell,armada-370-cpu-reset"; + reg = <0x20800 0x10>; + }; + coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>; }; + pmsu@22000 { + compatible = "marvell,armada-380-pmsu"; + reg = <0x22000 0x1000>; + }; + eth1: ethernet@30000 { compatible = "marvell,armada-370-neta"; reg = <0x30000 0x4000>; -- cgit v1.2.3 From 5e40704ed2c69425bcb076fb1890417ef137e6c8 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 17 Apr 2014 13:57:37 +0100 Subject: arm: xen: implement multicall hypercall support. As part of this make the usual change to xen_ulong_t in place of unsigned long. This change has no impact on x86. The Linux definition of struct multicall_entry.result differs from the Xen definition, I think for good reasons, and used a long rather than an unsigned long. Therefore introduce a xen_long_t, which is a long on x86 architectures and a signed 64-bit integer on ARM. Use uint32_t nr_calls on x86 for consistency with the ARM definition. Build tested on amd64 and i386 builds. Runtime tested on ARM. Signed-off-by: Ian Campbell Cc: Stefano Stabellini Cc: Konrad Rzeszutek Wilk Cc: Boris Ostrovsky Signed-off-by: David Vrabel --- arch/arm/include/asm/xen/hypercall.h | 6 +----- arch/arm/include/asm/xen/interface.h | 2 ++ arch/arm/xen/hypercall.S | 1 + arch/arm64/xen/hypercall.S | 1 + arch/x86/include/asm/xen/hypercall.h | 2 +- arch/x86/include/asm/xen/interface.h | 3 +++ include/xen/interface/xen.h | 6 +++--- 7 files changed, 12 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h index 7704e28c3483..7658150488d6 100644 --- a/arch/arm/include/asm/xen/hypercall.h +++ b/arch/arm/include/asm/xen/hypercall.h @@ -48,6 +48,7 @@ int HYPERVISOR_memory_op(unsigned int cmd, void *arg); int HYPERVISOR_physdev_op(int cmd, void *arg); int HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args); int HYPERVISOR_tmem_op(void *arg); +int HYPERVISOR_multicall(struct multicall_entry *calls, uint32_t nr); static inline void MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, @@ -63,9 +64,4 @@ MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req, BUG(); } -static inline int -HYPERVISOR_multicall(void *call_list, int nr_calls) -{ - BUG(); -} #endif /* _ASM_ARM_XEN_HYPERCALL_H */ diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h index 1151188bcd83..50066006e6bd 100644 --- a/arch/arm/include/asm/xen/interface.h +++ b/arch/arm/include/asm/xen/interface.h @@ -40,6 +40,8 @@ typedef uint64_t xen_pfn_t; #define PRI_xen_pfn "llx" typedef uint64_t xen_ulong_t; #define PRI_xen_ulong "llx" +typedef int64_t xen_long_t; +#define PRI_xen_long "llx" /* Guest handles for primitive C types. */ __DEFINE_GUEST_HANDLE(uchar, unsigned char); __DEFINE_GUEST_HANDLE(uint, unsigned int); diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S index d1cf7b7c2200..44e3a5f10c4c 100644 --- a/arch/arm/xen/hypercall.S +++ b/arch/arm/xen/hypercall.S @@ -89,6 +89,7 @@ HYPERCALL2(memory_op); HYPERCALL2(physdev_op); HYPERCALL3(vcpu_op); HYPERCALL1(tmem_op); +HYPERCALL2(multicall); ENTRY(privcmd_call) stmdb sp!, {r4} diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S index 531342ec4bcf..8bbe9401f4f0 100644 --- a/arch/arm64/xen/hypercall.S +++ b/arch/arm64/xen/hypercall.S @@ -80,6 +80,7 @@ HYPERCALL2(memory_op); HYPERCALL2(physdev_op); HYPERCALL3(vcpu_op); HYPERCALL1(tmem_op); +HYPERCALL2(multicall); ENTRY(privcmd_call) mov x16, x0 diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h index e709884d0ef9..ca08a27b90b3 100644 --- a/arch/x86/include/asm/xen/hypercall.h +++ b/arch/x86/include/asm/xen/hypercall.h @@ -343,7 +343,7 @@ HYPERVISOR_memory_op(unsigned int cmd, void *arg) } static inline int -HYPERVISOR_multicall(void *call_list, int nr_calls) +HYPERVISOR_multicall(void *call_list, uint32_t nr_calls) { return _hypercall2(int, multicall, call_list, nr_calls); } diff --git a/arch/x86/include/asm/xen/interface.h b/arch/x86/include/asm/xen/interface.h index fd9cb7695b5f..3400dbaec3c3 100644 --- a/arch/x86/include/asm/xen/interface.h +++ b/arch/x86/include/asm/xen/interface.h @@ -54,6 +54,9 @@ typedef unsigned long xen_pfn_t; #define PRI_xen_pfn "lx" typedef unsigned long xen_ulong_t; #define PRI_xen_ulong "lx" +typedef long xen_long_t; +#define PRI_xen_long "lx" + /* Guest handles for primitive C types. */ __DEFINE_GUEST_HANDLE(uchar, unsigned char); __DEFINE_GUEST_HANDLE(uint, unsigned int); diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h index 0cd5ca333fac..de082130ba4b 100644 --- a/include/xen/interface/xen.h +++ b/include/xen/interface/xen.h @@ -275,9 +275,9 @@ DEFINE_GUEST_HANDLE_STRUCT(mmu_update); * NB. The fields are natural register size for this architecture. */ struct multicall_entry { - unsigned long op; - long result; - unsigned long args[6]; + xen_ulong_t op; + xen_long_t result; + xen_ulong_t args[6]; }; DEFINE_GUEST_HANDLE_STRUCT(multicall_entry); -- cgit v1.2.3 From adc01864eb543097bfa23d3191a0733145662bac Mon Sep 17 00:00:00 2001 From: Julien Grall Date: Fri, 18 Apr 2014 16:54:34 +0100 Subject: arm/xen: Remove definiition of virt_to_pfn in asm/xen/page.h virt_to_pfn has been defined in asm/memory.h by the commit e26a9e0 "ARM: Better virt_to_page() handling" This will result of a compilation warning when CONFIG_XEN is enabled. arch/arm/include/asm/xen/page.h:80:0: warning: "virt_to_pfn" redefined [enabled by default] #define virt_to_pfn(v) (PFN_DOWN(__pa(v))) ^ In file included from arch/arm/include/asm/page.h:163:0, from arch/arm/include/asm/xen/page.h:4, from include/xen/page.h:4, from arch/arm/xen/grant-table.c:33: The definition in memory.h is nearly the same (it directly expand PFN_DOWN), so we can safely drop virt_to_pfn in xen include. Signed-off-by: Julien Grall Signed-off-by: David Vrabel --- arch/arm/include/asm/xen/page.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h index cf4f3e867395..ded062f9b358 100644 --- a/arch/arm/include/asm/xen/page.h +++ b/arch/arm/include/asm/xen/page.h @@ -77,7 +77,6 @@ static inline xpaddr_t machine_to_phys(xmaddr_t machine) } /* VIRT <-> MACHINE conversion */ #define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) -#define virt_to_pfn(v) (PFN_DOWN(__pa(v))) #define virt_to_mfn(v) (pfn_to_mfn(virt_to_pfn(v))) #define mfn_to_virt(m) (__va(mfn_to_pfn(m) << PAGE_SHIFT)) -- cgit v1.2.3 From 541e00ae0c1e1fd1e9e2bf2cf010c26d0a1ed0a0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 16 Apr 2014 18:00:12 +0200 Subject: ARM: pxa: zeus: Replace OHCI init/exit functions with a regulator Signed-off-by: Laurent Pinchart Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-pxa/zeus.c | 89 ++++++++++++++++++++++++++---------------------- 1 file changed, 48 insertions(+), 41 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index b19d1c361cab..205f9bf3821e 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -413,7 +413,7 @@ static struct fixed_voltage_config can_regulator_pdata = { static struct platform_device can_regulator_device = { .name = "reg-fixed-volage", - .id = -1, + .id = 0, .dev = { .platform_data = &can_regulator_pdata, }, @@ -510,18 +510,6 @@ struct platform_device zeus_max6369_device = { .num_resources = 1, }; -static struct platform_device *zeus_devices[] __initdata = { - &zeus_serial_device, - &zeus_mtd_devices[0], - &zeus_dm9k0_device, - &zeus_dm9k1_device, - &zeus_sram_device, - &zeus_leds_device, - &zeus_pcmcia_device, - &zeus_max6369_device, - &can_regulator_device, -}; - /* AC'97 */ static pxa2xx_audio_ops_t zeus_ac97_info = { .reset_gpio = 95, @@ -532,44 +520,50 @@ static pxa2xx_audio_ops_t zeus_ac97_info = { * USB host */ -static int zeus_ohci_init(struct device *dev) -{ - int err; - - /* Switch on port 2. */ - if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) { - dev_err(dev, "Can't request USB2_PWREN\n"); - return err; - } - - if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) { - gpio_free(ZEUS_USB2_PWREN_GPIO); - dev_err(dev, "Can't enable USB2_PWREN\n"); - return err; - } +static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = { + REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"), +}; - /* Port 2 is shared between host and client interface. */ - UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; +static struct regulator_init_data zeus_ohci_regulator_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies), + .consumer_supplies = zeus_ohci_regulator_supplies, +}; - return 0; -} +static struct fixed_voltage_config zeus_ohci_regulator_config = { + .supply_name = "vbus2", + .microvolts = 5000000, /* 5.0V */ + .gpio = ZEUS_USB2_PWREN_GPIO, + .enable_high = 1, + .startup_delay = 0, + .init_data = &zeus_ohci_regulator_data, +}; -static void zeus_ohci_exit(struct device *dev) -{ - /* Power-off port 2 */ - gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0); - gpio_free(ZEUS_USB2_PWREN_GPIO); -} +static struct platform_device zeus_ohci_regulator_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zeus_ohci_regulator_config, + }, +}; static struct pxaohci_platform_data zeus_ohci_platform_data = { .port_mode = PMM_NPS_MODE, /* Clear Power Control Polarity Low and set Power Sense * Polarity Low. Supply power to USB ports. */ .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW, - .init = zeus_ohci_init, - .exit = zeus_ohci_exit, }; +static void zeus_register_ohci(void) +{ + /* Port 2 is shared between host and client interface. */ + UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + + pxa_set_ohci_info(&zeus_ohci_platform_data); +} + /* * Flat Panel */ @@ -677,6 +671,19 @@ static struct pxa2xx_udc_mach_info zeus_udc_info = { .udc_command = zeus_udc_command, }; +static struct platform_device *zeus_devices[] __initdata = { + &zeus_serial_device, + &zeus_mtd_devices[0], + &zeus_dm9k0_device, + &zeus_dm9k1_device, + &zeus_sram_device, + &zeus_leds_device, + &zeus_pcmcia_device, + &zeus_max6369_device, + &can_regulator_device, + &zeus_ohci_regulator_device, +}; + #ifdef CONFIG_PM static void zeus_power_off(void) { @@ -847,7 +854,7 @@ static void __init zeus_init(void) platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices)); - pxa_set_ohci_info(&zeus_ohci_platform_data); + zeus_register_ohci(); if (zeus_setup_fb_gpios()) pr_err("Failed to setup fb gpios\n"); -- cgit v1.2.3 From d20642f0a32575605f152a1cb7753bdfca5fc94b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 18 Apr 2014 17:19:54 -0500 Subject: x86: move FIX_EARLYCON_MEM kconfig into x86 In preparation to support FIX_EARLYCON_MEM on other arches, make the option per arch. Signed-off-by: Rob Herring Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: Jiri Slaby Signed-off-by: Greg Kroah-Hartman --- arch/x86/Kconfig | 3 +++ drivers/tty/serial/8250/Kconfig | 5 ----- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 25d2c6f7325e..0fb6cfd50e75 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -261,6 +261,9 @@ config ARCH_HWEIGHT_CFLAGS config ARCH_SUPPORTS_UPROBES def_bool y +config FIX_EARLYCON_MEM + def_bool y + source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index 23329918f229..91f1d8332b86 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -90,11 +90,6 @@ config SERIAL_8250_CONSOLE If unsure, say N. -config FIX_EARLYCON_MEM - bool - depends on X86 - default y - config SERIAL_8250_GSC tristate depends on SERIAL_8250 && GSC -- cgit v1.2.3 From 92cc15fcb543a8ab9af5682a2011944e6f48fd4c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 18 Apr 2014 17:19:59 -0500 Subject: arm64: enable FIX_EARLYCON_MEM kconfig In order to support earlycon on arm64, we need to enable earlycon fixmap support. Signed-off-by: Rob Herring Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Greg Kroah-Hartman --- arch/arm64/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e6e4d3749a6e..22d13976b9e0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -112,6 +112,9 @@ config IOMMU_HELPER config KERNEL_MODE_NEON def_bool y +config FIX_EARLYCON_MEM + def_bool y + source "init/Kconfig" source "kernel/Kconfig.freezer" -- cgit v1.2.3 From 8ef0ed95ee040a5cd25325dddcb8292c34bec33e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 18 Apr 2014 17:20:00 -0500 Subject: arm64: remove arch specific earlyprintk Now that we have equivalent earlycon support, arm64's earlyprintk code can be removed. Signed-off-by: Rob Herring Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Greg Kroah-Hartman --- arch/arm64/Kconfig.debug | 9 --- arch/arm64/kernel/Makefile | 1 - arch/arm64/kernel/early_printk.c | 158 --------------------------------------- 3 files changed, 168 deletions(-) delete mode 100644 arch/arm64/kernel/early_printk.c (limited to 'arch') diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug index d10ec334c93b..1c1b75629842 100644 --- a/arch/arm64/Kconfig.debug +++ b/arch/arm64/Kconfig.debug @@ -20,15 +20,6 @@ config STRICT_DEVMEM If in doubt, say Y. -config EARLY_PRINTK - bool "Early printk support" - default y - help - Say Y here if you want to have an early console using the - earlyprintk=[,][,] kernel parameter. It - is assumed that the early console device has been initialised - by the boot loader prior to starting the Linux kernel. - config PID_IN_CONTEXTIDR bool "Write the current PID to the CONTEXTIDR register" help diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 7d811d9522bc..7a6fce5167e9 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -18,7 +18,6 @@ arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o -arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o diff --git a/arch/arm64/kernel/early_printk.c b/arch/arm64/kernel/early_printk.c deleted file mode 100644 index ffbbdde7aba1..000000000000 --- a/arch/arm64/kernel/early_printk.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Earlyprintk support. - * - * Copyright (C) 2012 ARM Ltd. - * Author: Catalin Marinas - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -static void __iomem *early_base; -static void (*printch)(char ch); - -/* - * PL011 single character TX. - */ -static void pl011_printch(char ch) -{ - while (readl_relaxed(early_base + UART01x_FR) & UART01x_FR_TXFF) - ; - writeb_relaxed(ch, early_base + UART01x_DR); - while (readl_relaxed(early_base + UART01x_FR) & UART01x_FR_BUSY) - ; -} - -/* - * Semihosting-based debug console - */ -static void smh_printch(char ch) -{ - asm volatile("mov x1, %0\n" - "mov x0, #3\n" - "hlt 0xf000\n" - : : "r" (&ch) : "x0", "x1", "memory"); -} - -/* - * 8250/16550 (8-bit aligned registers) single character TX. - */ -static void uart8250_8bit_printch(char ch) -{ - while (!(readb_relaxed(early_base + UART_LSR) & UART_LSR_THRE)) - ; - writeb_relaxed(ch, early_base + UART_TX); -} - -/* - * 8250/16550 (32-bit aligned registers) single character TX. - */ -static void uart8250_32bit_printch(char ch) -{ - while (!(readl_relaxed(early_base + (UART_LSR << 2)) & UART_LSR_THRE)) - ; - writel_relaxed(ch, early_base + (UART_TX << 2)); -} - -struct earlycon_match { - const char *name; - void (*printch)(char ch); -}; - -static const struct earlycon_match earlycon_match[] __initconst = { - { .name = "pl011", .printch = pl011_printch, }, - { .name = "smh", .printch = smh_printch, }, - { .name = "uart8250-8bit", .printch = uart8250_8bit_printch, }, - { .name = "uart8250-32bit", .printch = uart8250_32bit_printch, }, - {} -}; - -static void early_write(struct console *con, const char *s, unsigned n) -{ - while (n-- > 0) { - if (*s == '\n') - printch('\r'); - printch(*s); - s++; - } -} - -static struct console early_console_dev = { - .name = "earlycon", - .write = early_write, - .flags = CON_PRINTBUFFER | CON_BOOT, - .index = -1, -}; - -/* - * Parse earlyprintk=... parameter in the format: - * - * [,][,] - * - * and register the early console. It is assumed that the UART has been - * initialised by the bootloader already. - */ -static int __init setup_early_printk(char *buf) -{ - const struct earlycon_match *match = earlycon_match; - phys_addr_t paddr = 0; - - if (!buf) { - pr_warning("No earlyprintk arguments passed.\n"); - return 0; - } - - while (match->name) { - size_t len = strlen(match->name); - if (!strncmp(buf, match->name, len)) { - buf += len; - break; - } - match++; - } - if (!match->name) { - pr_warning("Unknown earlyprintk arguments: %s\n", buf); - return 0; - } - - /* I/O address */ - if (!strncmp(buf, ",0x", 3)) { - char *e; - paddr = simple_strtoul(buf + 1, &e, 16); - buf = e; - } - /* no options parsing yet */ - - if (paddr) { - set_fixmap_io(FIX_EARLYCON_MEM_BASE, paddr); - early_base = (void __iomem *)fix_to_virt(FIX_EARLYCON_MEM_BASE); - } - - printch = match->printch; - early_console = &early_console_dev; - register_console(&early_console_dev); - - return 0; -} - -early_param("earlyprintk", setup_early_printk); -- cgit v1.2.3 From ab496b9d259e754f5d646219e4f032b274b9fffe Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 11 Apr 2014 17:26:41 +0200 Subject: ARM: shmobile: Ignore callbacks for subsys generic_pm_domain_data There are no active users of these callbacks, thus there are no benefit of trying to invoke them. Cc: Simon Horman Cc: Magnus Damm Signed-off-by: Ulf Hansson Signed-off-by: Simon Horman --- arch/arm/mach-shmobile/pm-rmobile.c | 38 +++---------------------------------- 1 file changed, 3 insertions(+), 35 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index 1fc05d9453d0..f710235aff2f 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c @@ -99,39 +99,7 @@ static int rmobile_pd_power_up(struct generic_pm_domain *genpd) static bool rmobile_pd_active_wakeup(struct device *dev) { - bool (*active_wakeup)(struct device *dev); - - active_wakeup = dev_gpd_data(dev)->ops.active_wakeup; - return active_wakeup ? active_wakeup(dev) : true; -} - -static int rmobile_pd_stop_dev(struct device *dev) -{ - int (*stop)(struct device *dev); - - stop = dev_gpd_data(dev)->ops.stop; - if (stop) { - int ret = stop(dev); - if (ret) - return ret; - } - return pm_clk_suspend(dev); -} - -static int rmobile_pd_start_dev(struct device *dev) -{ - int (*start)(struct device *dev); - int ret; - - ret = pm_clk_resume(dev); - if (ret) - return ret; - - start = dev_gpd_data(dev)->ops.start; - if (start) - ret = start(dev); - - return ret; + return true; } static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) @@ -140,8 +108,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd) struct dev_power_governor *gov = rmobile_pd->gov; pm_genpd_init(genpd, gov ? : &simple_qos_governor, false); - genpd->dev_ops.stop = rmobile_pd_stop_dev; - genpd->dev_ops.start = rmobile_pd_start_dev; + genpd->dev_ops.stop = pm_clk_suspend; + genpd->dev_ops.start = pm_clk_resume; genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup; genpd->dev_irq_safe = true; genpd->power_off = rmobile_pd_power_down; -- cgit v1.2.3 From 4b37ab033e6f8c9750f98fefe9bdc341b6943268 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 25 Apr 2014 02:42:41 +0400 Subject: ARM: shmobile: henninger: initial device tree Add the initial device tree for the R8A7791 SoC based Henninger board. SCIF0 serial port support is included, so that the serial console can work. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7791-henninger.dts | 50 +++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7791-henninger.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..2e9b6e08ebd9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ sh7372-mackerel.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ r7s72100-genmai-reference.dtb \ + r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ r8a7790-lager.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts new file mode 100644 index 000000000000..0053f52bc969 --- /dev/null +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -0,0 +1,50 @@ +/* + * Device Tree Source for the Henninger board + * + * Copyright (C) 2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7791.dtsi" + +/ { + model = "Henninger"; + compatible = "renesas,henninger", "renesas,r8a7791"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "console=ttySC0,38400 ignore_loglevel"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; +}; + +&pfc { + scif0_pins: serial0 { + renesas,groups = "scif0_data_d"; + renesas,function = "scif0"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3 From 26b0d2cf73cb5091962c81598a36346d05e9ba83 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 25 Apr 2014 02:44:12 +0400 Subject: ARM: shmobile: henninger: add Ether DT support Define the Henninger board dependent part of the Ether device node. Enable DHCP and NFS root for the kernel booting. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index 0053f52bc969..f82f306c074d 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "console=ttySC0,38400 ignore_loglevel"; + bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; }; memory@40000000 { @@ -40,6 +40,16 @@ renesas,groups = "scif0_data_d"; renesas,function = "scif0"; }; + + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq0"; + renesas,function = "intc"; + }; }; &scif0 { @@ -48,3 +58,19 @@ status = "okay"; }; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "ok"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; -- cgit v1.2.3 From 431a84b1a4f7d1a0085d5b91330c5053cc8e8b12 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 22 Apr 2014 16:14:27 +0100 Subject: ARM: 8034/1: Disable preemption in iwmmxt_task_enable() This patch is in preparation for calling the iwmmxt_task_enable() function with interrupts enabled. Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/iwmmxt.S | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index a08783823b32..fcb33a70a35f 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -18,6 +18,7 @@ #include #include #include +#include #if defined(CONFIG_CPU_PJ4) #define PJ4(code...) code @@ -65,13 +66,14 @@ */ ENTRY(iwmmxt_task_enable) + inc_preempt_count r10, r3 XSC(mrc p15, 0, r2, c15, c1, 0) PJ4(mrc p15, 0, r2, c1, c0, 2) @ CP0 and CP1 accessible? XSC(tst r2, #0x3) PJ4(tst r2, #0xf) - movne pc, lr @ if so no business here + bne 4f @ if so no business here @ enable access to CP0 and CP1 XSC(orr r2, r2, #0x3) XSC(mcr p15, 0, r2, c15, c1, 0) @@ -132,7 +134,7 @@ concan_dump: wstrd wR15, [r1, #MMX_WR15] 2: teq r0, #0 @ anything to load? - moveq pc, lr + beq 3f concan_load: @@ -165,8 +167,14 @@ concan_load: @ clear CUP/MUP (only if r1 != 0) teq r1, #0 mov r2, #0 - moveq pc, lr + beq 3f tmcr wCon, r2 + +3: +#ifdef CONFIG_PREEMPT_COUNT + get_thread_info r10 +#endif +4: dec_preempt_count r10, r3 mov pc, lr /* -- cgit v1.2.3 From bc94081c6ac823c4723d8e36e9604c6cf3eba0ef Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 22 Apr 2014 16:14:28 +0100 Subject: ARM: 8035/1: Disable preemption in crunch_task_enable() This patch is in preparation for calling the crunch_task_enable() function with interrupts enabled. Signed-off-by: Catalin Marinas Cc: Hartley Sweeten Cc: Ryan Mallon Signed-off-by: Russell King --- arch/arm/mach-ep93xx/crunch-bits.S | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S index 0ec9bb48fab9..eaa5e34729d3 100644 --- a/arch/arm/mach-ep93xx/crunch-bits.S +++ b/arch/arm/mach-ep93xx/crunch-bits.S @@ -16,6 +16,7 @@ #include #include #include +#include #include /* @@ -65,11 +66,13 @@ * called from prefetch exception handler with interrupts disabled */ ENTRY(crunch_task_enable) + inc_preempt_count r10, r3 + ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr ldr r1, [r8, #0x80] tst r1, #0x00800000 @ access to crunch enabled? - movne pc, lr @ if so no business here + bne 2f @ if so no business here mov r3, #0xaa @ unlock syscon swlock str r3, [r8, #0xc0] orr r1, r1, #0x00800000 @ enable access to crunch @@ -142,7 +145,7 @@ crunch_save: teq r0, #0 @ anything to load? cfldr64eq mvdx0, [r1, #CRUNCH_MVDX0] @ mvdx0 was clobbered - moveq pc, lr + beq 1f crunch_load: cfldr64 mvdx0, [r0, #CRUNCH_DSPSC] @ load status word @@ -190,6 +193,11 @@ crunch_load: cfldr64 mvdx14, [r0, #CRUNCH_MVDX14] cfldr64 mvdx15, [r0, #CRUNCH_MVDX15] +1: +#ifdef CONFIG_PREEMPT_COUNT + get_thread_info r10 +#endif +2: dec_preempt_count r10, r3 mov pc, lr /* -- cgit v1.2.3 From 1417a6b8dc4db73055be9a3aa288b050e9dc06ab Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Tue, 22 Apr 2014 16:14:29 +0100 Subject: ARM: 8036/1: Enable IRQs before attempting to read user space in __und_usr The Undef abort handler in the kernel reads the undefined instruction from user space. If the page table was modified from another CPU, the user access could fail and do_page_fault() will be executed with interrupts disabled. This can potentially deadlock on ARM11MPCore or on Cortex-A15 with erratum 798181 workaround enabled (both implying IPI for TLB maintenance with page table lock held). This patch enables the IRQs in __und_usr before attempting to read the instruction from user space. Signed-off-by: Catalin Marinas Tested-by: Arun KS Cc: Hartley Sweeten Cc: Ryan Mallon Signed-off-by: Russell King --- arch/arm/kernel/entry-armv.S | 11 +++++++---- arch/arm/kernel/iwmmxt.S | 2 +- arch/arm/mach-ep93xx/crunch-bits.S | 2 +- arch/arm/vfp/entry.S | 3 +-- 4 files changed, 10 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 1879e8dd2acc..5fc897cf409b 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -413,6 +413,11 @@ __und_usr: @ adr r9, BSYM(ret_from_exception) + @ IRQs must be enabled before attempting to read the instruction from + @ user space since that could cause a page/translation fault if the + @ page table was modified by another CPU. + enable_irq + tst r3, #PSR_T_BIT @ Thumb mode? bne __und_usr_thumb sub r4, r2, #4 @ ARM instr at LR - 4 @@ -517,7 +522,7 @@ ENDPROC(__und_usr) * r9 = normal "successful" return address * r10 = this threads thread_info structure * lr = unrecognised instruction return address - * IRQs disabled, FIQs enabled. + * IRQs enabled, FIQs enabled. */ @ @ Fall-through from Thumb-2 __und_usr @@ -624,7 +629,6 @@ call_fpe: #endif do_fpe: - enable_irq ldr r4, .LCfp add r10, r10, #TI_FPSTATE @ r10 = workspace ldr pc, [r4] @ Call FP module USR entry point @@ -652,8 +656,7 @@ __und_usr_fault_32: b 1f __und_usr_fault_16: mov r1, #2 -1: enable_irq - mov r0, sp +1: mov r0, sp adr lr, BSYM(ret_from_exception) b __und_fault ENDPROC(__und_usr_fault_32) diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S index fcb33a70a35f..4bb029ea8917 100644 --- a/arch/arm/kernel/iwmmxt.S +++ b/arch/arm/kernel/iwmmxt.S @@ -62,7 +62,7 @@ * r9 = ret_from_exception * lr = undefined instr exit * - * called from prefetch exception handler with interrupts disabled + * called from prefetch exception handler with interrupts enabled */ ENTRY(iwmmxt_task_enable) diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S index eaa5e34729d3..e96923a3017b 100644 --- a/arch/arm/mach-ep93xx/crunch-bits.S +++ b/arch/arm/mach-ep93xx/crunch-bits.S @@ -63,7 +63,7 @@ * r9 = ret_from_exception * lr = undefined instr exit * - * called from prefetch exception handler with interrupts disabled + * called from prefetch exception handler with interrupts enabled */ ENTRY(crunch_task_enable) inc_preempt_count r10, r3 diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index f0759e70fb86..fe6ca574d093 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -22,11 +22,10 @@ @ r9 = normal "successful" return address @ r10 = this threads thread_info structure @ lr = unrecognised instruction return address -@ IRQs disabled. +@ IRQs enabled. @ ENTRY(do_vfp) inc_preempt_count r10, r4 - enable_irq ldr r4, .LCvfp ldr r11, [r10, #TI_CPU] @ CPU number add r10, r10, #TI_VFPSTATE @ r10 = workspace -- cgit v1.2.3 From 86f40622af7329375e38f282f6c0aab95f3e5f72 Mon Sep 17 00:00:00 2001 From: Jianguo Wu Date: Thu, 24 Apr 2014 03:45:56 +0100 Subject: ARM: 8037/1: mm: support big-endian page tables When enable LPAE and big-endian in a hisilicon board, while specify mem=384M mem=512M@7680M, will get bad page state: Freeing unused kernel memory: 180K (c0466000 - c0493000) BUG: Bad page state in process init pfn:fa442 page:c7749840 count:0 mapcount:-1 mapping: (null) index:0x0 page flags: 0x40000400(reserved) Modules linked in: CPU: 0 PID: 1 Comm: init Not tainted 3.10.27+ #66 [] (unwind_backtrace+0x0/0x11c) from [] (show_stack+0x10/0x14) [] (show_stack+0x10/0x14) from [] (bad_page+0xd4/0x104) [] (bad_page+0xd4/0x104) from [] (free_pages_prepare+0xa8/0x14c) [] (free_pages_prepare+0xa8/0x14c) from [] (free_hot_cold_page+0x18/0xf0) [] (free_hot_cold_page+0x18/0xf0) from [] (handle_pte_fault+0xcf4/0xdc8) [] (handle_pte_fault+0xcf4/0xdc8) from [] (handle_mm_fault+0xf4/0x120) [] (handle_mm_fault+0xf4/0x120) from [] (do_page_fault+0xfc/0x354) [] (do_page_fault+0xfc/0x354) from [] (do_DataAbort+0x2c/0x90) [] (do_DataAbort+0x2c/0x90) from [] (__dabt_usr+0x34/0x40) The bad pfn:fa442 is not system memory(mem=384M mem=512M@7680M), after debugging, I find in page fault handler, will get wrong pfn from pte just after set pte, as follow: do_anonymous_page() { ... set_pte_at(mm, address, page_table, entry); //debug code pfn = pte_pfn(entry); pr_info("pfn:0x%lx, pte:0x%llxn", pfn, pte_val(entry)); //read out the pte just set new_pte = pte_offset_map(pmd, address); new_pfn = pte_pfn(*new_pte); pr_info("new pfn:0x%lx, new pte:0x%llxn", pfn, pte_val(entry)); ... } pfn: 0x1fa4f5, pte:0xc00001fa4f575f new_pfn:0xfa4f5, new_pte:0xc00000fa4f5f5f //new pfn/pte is wrong. The bug is happened in cpu_v7_set_pte_ext(ptep, pte): An LPAE PTE is a 64bit quantity, passed to cpu_v7_set_pte_ext in the r2 and r3 registers. On an LE kernel, r2 contains the LSB of the PTE, and r3 the MSB. On a BE kernel, the assignment is reversed. Unfortunately, the current code always assumes the LE case, leading to corruption of the PTE when clearing/setting bits. This patch fixes this issue much like it has been done already in the cpu_v7_switch_mm case. CC stable Signed-off-by: Jianguo Wu Acked-by: Marc Zyngier Acked-by: Will Deacon Signed-off-by: Russell King --- arch/arm/mm/proc-v7-3level.S | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 01a719e18bb0..22e3ad63500c 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -64,6 +64,14 @@ ENTRY(cpu_v7_switch_mm) mov pc, lr ENDPROC(cpu_v7_switch_mm) +#ifdef __ARMEB__ +#define rl r3 +#define rh r2 +#else +#define rl r2 +#define rh r3 +#endif + /* * cpu_v7_set_pte_ext(ptep, pte) * @@ -73,13 +81,13 @@ ENDPROC(cpu_v7_switch_mm) */ ENTRY(cpu_v7_set_pte_ext) #ifdef CONFIG_MMU - tst r2, #L_PTE_VALID + tst rl, #L_PTE_VALID beq 1f - tst r3, #1 << (57 - 32) @ L_PTE_NONE - bicne r2, #L_PTE_VALID + tst rh, #1 << (57 - 32) @ L_PTE_NONE + bicne rl, #L_PTE_VALID bne 1f - tst r3, #1 << (55 - 32) @ L_PTE_DIRTY - orreq r2, #L_PTE_RDONLY + tst rh, #1 << (55 - 32) @ L_PTE_DIRTY + orreq rl, #L_PTE_RDONLY 1: strd r2, r3, [r0] ALT_SMP(W(nop)) ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte -- cgit v1.2.3 From 1892bbcdd41b5e2582000ab21e9f6b734d005a71 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Tue, 15 Apr 2014 07:37:19 -0500 Subject: ARM: bcm: clean up config and build targets Currently CONFIG_ARCH_BCM_MOBILE is used to select all (both) Broadcom mobile SoC families. Instead, use that only as a config menu switch, and define specific symbols like ARCH_BCM_281XX to select a particular SoC family. If ARCH_BCM_MOBILE is selected, all of the SoCs will be selected by default, but this way each can be disabled individually as well. Note that BCM281xx and BCM21664 both require the SMC and L2 cache control code, so that code will be built based on ARCH_BCM_MOBILE. Signed-off-by: Alex Elder [mporter: added ARM: to the description] Signed-off-by: Matt Porter --- arch/arm/mach-bcm/Kconfig | 28 ++++++++++++++++++++++++---- arch/arm/mach-bcm/Makefile | 15 ++++++++++++--- 2 files changed, 36 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 49c914cd9c7a..5f5740fc334f 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -10,7 +10,7 @@ if ARCH_BCM menu "Broadcom SoC Selection" config ARCH_BCM_MOBILE - bool "Broadcom Mobile SoC" if ARCH_MULTI_V7 + bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7 depends on MMU select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_754322 @@ -23,9 +23,29 @@ config ARCH_BCM_MOBILE select PINCTRL help This enables support for systems based on Broadcom mobile SoCs. - It currently supports the 'BCM281XX' family, which includes - BCM11130, BCM11140, BCM11351, BCM28145 and - BCM28155 variants. + +if ARCH_BCM_MOBILE + +menu "Broadcom Mobile SoC Selection" + +config ARCH_BCM_281XX + bool "Broadcom BCM281XX SoC family" + default y + help + Enable support for the the BCM281XX family, which includes + BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155 + variants. + +config ARCH_BCM_21664 + bool "Broadcom BCM21664 SoC family" + default y + help + Enable support for the the BCM21664 family, which includes + BCM21663 and BCM21664 variants. + +endmenu + +endif config ARCH_BCM2835 bool "Broadcom BCM2835 family" if ARCH_MULTI_V6 diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index a326b28c4406..7fb9b0402204 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -10,10 +10,19 @@ # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -obj-$(CONFIG_ARCH_BCM_MOBILE) := board_bcm281xx.o board_bcm21664.o \ - bcm_kona_smc.o bcm_kona_smc_asm.o kona.o -obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o +# BCM281XX +obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o + +# BCM21664 +obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o +# BCM281XX and BCM21664 L2 cache control +obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm_kona_smc.o bcm_kona_smc_asm.o kona.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) + +# BCM2835 +obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o + +# BCM5301X obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o -- cgit v1.2.3 From e80eef33f4596a247fdcf7d67d54d95d9dfaf7d3 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:02 -0500 Subject: ARM: bcm: use memory accessors for ioremapped area The pointer used to pass parameters to an "smc" call is produced through a call to ioremap(). As such, we should be using functions like writel() to access it. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/bcm_kona_smc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index 5e31e918f325..d881c72ee878 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -79,11 +79,11 @@ static void __bcm_kona_smc(void *info) /* Check map in the bounce area */ BUG_ON(!bridge_data.initialized); - /* Copy one 32 bit word into the bounce area */ - args[0] = data->arg0; - args[1] = data->arg1; - args[2] = data->arg2; - args[3] = data->arg3; + /* Copy the four 32 bit argument values into the bounce area */ + writel_relaxed(data->arg0, args++); + writel_relaxed(data->arg1, args++); + writel_relaxed(data->arg2, args++); + writel(data->arg3, args); /* Flush caches for input data passed to Secure Monitor */ if (data->service_id != SSAPI_BRCM_START_VC_CORE) -- cgit v1.2.3 From 5c4cee2fe8de7c14e60502b02e7c3bc7acba0530 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:03 -0500 Subject: ARM: bcm: err, don't BUG() on SMC init failures Several conditions in bcm_kona_smc_init() are handled with BUG_ON(). That function is capable of returning an error, so do that instead. Also, don't assume of_get_address() returns a valid pointer. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/bcm_kona_smc.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index d881c72ee878..ddc2f17217ee 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -45,6 +45,7 @@ static const struct of_device_id bcm_kona_smc_ids[] __initconst = { int __init bcm_kona_smc_init(void) { struct device_node *node; + const __be32 *prop_val; /* Read buffer addr and size from the device tree node */ node = of_find_matching_node(NULL, bcm_kona_smc_ids); @@ -52,12 +53,17 @@ int __init bcm_kona_smc_init(void) return -ENODEV; /* Don't care about size or flags of the DT node */ - bridge_data.buffer_addr = - be32_to_cpu(*of_get_address(node, 0, NULL, NULL)); - BUG_ON(!bridge_data.buffer_addr); + prop_val = of_get_address(node, 0, NULL, NULL); + if (!prop_val) + return -EINVAL; + + bridge_data.buffer_addr = be32_to_cpu(*prop_val); + if (!bridge_data.buffer_addr) + return -EINVAL; bridge_data.bounce = of_iomap(node, 0); - BUG_ON(!bridge_data.bounce); + if (!bridge_data.bounce) + return -ENOMEM; bridge_data.initialized = 1; -- cgit v1.2.3 From c64756cca2fb4da96fcc71e376d712297aedc4a2 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:04 -0500 Subject: ARM: bcm: clean up SMC code This patch just does some simple cleanup in "bcm_kona_smc.c": - Get rid of the secure_bridge_data structure. Instead, just define two globals that record the physical and virtual addresses of the SMC arguments buffer. Use "buffer" instead of "bounce" in their names. Drop of the erroneous __iomem annotation for the physical address. - Get rid of the initialized flag and just use a non-null buffer address to indicate that. - Get the size of the memory region when fetching the SMC arguments buffer location from the device tree. Use it to call ioremap() directly rather than requiring of_iomap() to go look it up again. - Do some additional validation on that memory region size. - Flush caches unconditionally in __bcm_kona_smc(); nothing supplies SSAPI_BRCM_START_VC_CORE as a service id. - Drop a needless initialization of "rc" in __bcm_kona_smc(). It also deletes most of the content of "bcm_kona_smc.h" because it's never actually used and is of questionable value anyway. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/bcm_kona_smc.c | 45 +++++++++++++++++++-------------------- arch/arm/mach-bcm/bcm_kona_smc.h | 46 ++-------------------------------------- 2 files changed, 24 insertions(+), 67 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index ddc2f17217ee..0d2bfe2bcfa8 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -21,11 +21,8 @@ #include "bcm_kona_smc.h" -struct secure_bridge_data { - void __iomem *bounce; /* virtual address */ - u32 __iomem buffer_addr; /* physical address */ - int initialized; -} bridge_data; +static u32 bcm_smc_buffer_phys; /* physical address */ +static void __iomem *bcm_smc_buffer; /* virtual address */ struct bcm_kona_smc_data { unsigned service_id; @@ -41,31 +38,37 @@ static const struct of_device_id bcm_kona_smc_ids[] __initconst = { {}, }; -/* Map in the bounce area */ +/* Map in the args buffer area */ int __init bcm_kona_smc_init(void) { struct device_node *node; const __be32 *prop_val; + u64 prop_size = 0; + unsigned long buffer_size; + u32 buffer_phys; /* Read buffer addr and size from the device tree node */ node = of_find_matching_node(NULL, bcm_kona_smc_ids); if (!node) return -ENODEV; - /* Don't care about size or flags of the DT node */ - prop_val = of_get_address(node, 0, NULL, NULL); + prop_val = of_get_address(node, 0, &prop_size, NULL); if (!prop_val) return -EINVAL; - bridge_data.buffer_addr = be32_to_cpu(*prop_val); - if (!bridge_data.buffer_addr) + /* We assume space for four 32-bit arguments */ + if (prop_size < 4 * sizeof(u32) || prop_size > (u64)ULONG_MAX) return -EINVAL; + buffer_size = (unsigned long)prop_size; - bridge_data.bounce = of_iomap(node, 0); - if (!bridge_data.bounce) - return -ENOMEM; + buffer_phys = be32_to_cpup(prop_val); + if (!buffer_phys) + return -EINVAL; - bridge_data.initialized = 1; + bcm_smc_buffer = ioremap(buffer_phys, buffer_size); + if (!bcm_smc_buffer) + return -ENOMEM; + bcm_smc_buffer_phys = buffer_phys; pr_info("Kona Secure API initialized\n"); @@ -76,14 +79,11 @@ int __init bcm_kona_smc_init(void) static void __bcm_kona_smc(void *info) { struct bcm_kona_smc_data *data = info; - u32 *args = bridge_data.bounce; - int rc = 0; + u32 *args = bcm_smc_buffer; + int rc; - /* Must run on CPU 0 */ BUG_ON(smp_processor_id() != 0); - - /* Check map in the bounce area */ - BUG_ON(!bridge_data.initialized); + BUG_ON(!args); /* Copy the four 32 bit argument values into the bounce area */ writel_relaxed(data->arg0, args++); @@ -92,11 +92,10 @@ static void __bcm_kona_smc(void *info) writel(data->arg3, args); /* Flush caches for input data passed to Secure Monitor */ - if (data->service_id != SSAPI_BRCM_START_VC_CORE) - flush_cache_all(); + flush_cache_all(); /* Trap into Secure Monitor */ - rc = bcm_kona_smc_asm(data->service_id, bridge_data.buffer_addr); + rc = bcm_kona_smc_asm(data->service_id, bcm_smc_buffer_phys); if (rc != SEC_ROM_RET_OK) pr_err("Secure Monitor call failed (0x%x)!\n", rc); diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h index d098a7e76744..629e64a89982 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.h +++ b/arch/arm/mach-bcm/bcm_kona_smc.h @@ -15,54 +15,12 @@ #define BCM_KONA_SMC_H #include -#define FLAGS (SEC_ROM_ICACHE_ENABLE_MASK | SEC_ROM_DCACHE_ENABLE_MASK | \ - SEC_ROM_IRQ_ENABLE_MASK | SEC_ROM_FIQ_ENABLE_MASK) -/*! - * Definitions for IRQ & FIQ Mask for ARM - */ - -#define FIQ_IRQ_MASK 0xC0 -#define FIQ_MASK 0x40 -#define IRQ_MASK 0x80 - -/*! - * Secure Mode FLAGs - */ - -/* When set, enables ICache within the secure mode */ -#define SEC_ROM_ICACHE_ENABLE_MASK 0x00000001 - -/* When set, enables DCache within the secure mode */ -#define SEC_ROM_DCACHE_ENABLE_MASK 0x00000002 - -/* When set, enables IRQ within the secure mode */ -#define SEC_ROM_IRQ_ENABLE_MASK 0x00000004 - -/* When set, enables FIQ within the secure mode */ -#define SEC_ROM_FIQ_ENABLE_MASK 0x00000008 - -/* When set, enables Unified L2 cache within the secure mode */ -#define SEC_ROM_UL2_CACHE_ENABLE_MASK 0x00000010 - -/* Broadcom Secure Service API Service IDs */ -#define SSAPI_DORMANT_ENTRY_SERV 0x01000000 -#define SSAPI_PUBLIC_OTP_SERV 0x01000001 -#define SSAPI_ENABLE_L2_CACHE 0x01000002 -#define SSAPI_DISABLE_L2_CACHE 0x01000003 -#define SSAPI_WRITE_SCU_STATUS 0x01000004 -#define SSAPI_WRITE_PWR_GATE 0x01000005 - -/* Broadcom Secure Service API Return Codes */ +/* Broadcom Secure Service API service IDs, return codes, and exit codes */ +#define SSAPI_ENABLE_L2_CACHE 0x01000002 #define SEC_ROM_RET_OK 0x00000001 -#define SEC_ROM_RET_FAIL 0x00000009 - -#define SSAPI_RET_FROM_INT_SERV 0x4 #define SEC_EXIT_NORMAL 0x1 -#define SSAPI_ROW_AES 0x0E000006 -#define SSAPI_BRCM_START_VC_CORE 0x0E000008 - #ifndef __ASSEMBLY__ extern int __init bcm_kona_smc_init(void); -- cgit v1.2.3 From 6c90f10864d1f7492ebe4c90465a9c9797ce649e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:05 -0500 Subject: ARM: bcm: have bcm_kona_smc() return request result Currently it is assumed that SEC_ROM_RET_OK is the only valid "good" result of a secure monitor request. However the values that can be returned by a secure monitor request are dependent on which service id was provided. We therefore should handle the result in a request-dependent way. The most natural way to do that is to have the initiator of the request--where bcm_kona_smc() is called--handle the result in a way appropriate to the request. An "smc" operation must be performed only on core 0, while the request can be initiated from any core. To pass back the request result, we add a new field to the bcm_kona_smc_data structure, and have bcm_kona_smc() return that value rather than 0. There's only one caller right now. Move the existing check of the result out of __bcm_kona_smc() and into the kona_l2_cache_init() where the SSAPI_ENABLE_L2_CACHE request is initiated. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/bcm_kona_smc.c | 12 +++++------- arch/arm/mach-bcm/kona.c | 8 +++++++- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index 0d2bfe2bcfa8..47cf360f985b 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -30,6 +30,7 @@ struct bcm_kona_smc_data { unsigned arg1; unsigned arg2; unsigned arg3; + unsigned result; }; static const struct of_device_id bcm_kona_smc_ids[] __initconst = { @@ -80,7 +81,6 @@ static void __bcm_kona_smc(void *info) { struct bcm_kona_smc_data *data = info; u32 *args = bcm_smc_buffer; - int rc; BUG_ON(smp_processor_id() != 0); BUG_ON(!args); @@ -94,11 +94,8 @@ static void __bcm_kona_smc(void *info) /* Flush caches for input data passed to Secure Monitor */ flush_cache_all(); - /* Trap into Secure Monitor */ - rc = bcm_kona_smc_asm(data->service_id, bcm_smc_buffer_phys); - - if (rc != SEC_ROM_RET_OK) - pr_err("Secure Monitor call failed (0x%x)!\n", rc); + /* Trap into Secure Monitor and record the request result */ + data->result = bcm_kona_smc_asm(data->service_id, bcm_smc_buffer_phys); } unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1, @@ -111,6 +108,7 @@ unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1, data.arg1 = arg1; data.arg2 = arg2; data.arg3 = arg3; + data.result = 0; /* * Due to a limitation of the secure monitor, we must use the SMP @@ -123,5 +121,5 @@ unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1, put_cpu(); - return 0; + return data.result; } diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c index 768bc2837bf5..ecdd71340a46 100644 --- a/arch/arm/mach-bcm/kona.c +++ b/arch/arm/mach-bcm/kona.c @@ -19,6 +19,7 @@ void __init kona_l2_cache_init(void) { + unsigned int result; int ret; if (!IS_ENABLED(CONFIG_CACHE_L2X0)) @@ -31,7 +32,12 @@ void __init kona_l2_cache_init(void) return; } - bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); + result = bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); + if (result != SEC_ROM_RET_OK) { + pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n", + result); + return; + } /* * The aux_val and aux_mask have no effect since L2 cache is already -- cgit v1.2.3 From 35138d52f18c3f757f12d54c0962a755bcf218f3 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:06 -0500 Subject: ARM: bcm: don't special-case CPU 0 in bcm_kona_smc() There's logic in bcm_kona_smc() to ensure __bcm_kona_smc() gets called on CPU 0; if already executing on CPU 0, that function is called directly. The direct call is not protected from interrupts, however, which is not safe. Note that smp_call_function_single() is designed to handle the case where the target cpu is the current one. It also gets a reference to the CPU and disables IRQs across the call. So we can simplify things and at the same time be protected against interrupts by calling smp_call_function_single() unconditionally. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/bcm_kona_smc.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index 47cf360f985b..6fdcf96ca54e 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -114,12 +114,7 @@ unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1, * Due to a limitation of the secure monitor, we must use the SMP * infrastructure to forward all secure monitor calls to Core 0. */ - if (get_cpu() != 0) - smp_call_function_single(0, __bcm_kona_smc, (void *)&data, 1); - else - __bcm_kona_smc(&data); - - put_cpu(); + smp_call_function_single(0, __bcm_kona_smc, &data, 1); return data.result; } -- cgit v1.2.3 From 7b5fe9c9115c92b7e6297216c789268961a19f98 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:07 -0500 Subject: ARM: bcm: config option for l2 cache support Add a new config option ARCH_BCM_MOBILE_L2_CACHE that allows support for level-2 cache to be enabled or disabled at build time for BCM218XX and BCM21664 family SoCs. Build support for SMC only if it's required (currently it's only required for to support level 2 cache control). If arch/arm/mach-bcm/kona.c gets compiled, ARCH_BCM_MOBILE_L2_CACHE must have been selected, which implies CONFIG_CACHE_L2X0 is set. There is therefore no need to check CONFIG_CACHE_L2X0 at the top of kona_l2_cache_init(), so get rid of that check. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/Kconfig | 12 +++++++++++- arch/arm/mach-bcm/Makefile | 5 ++++- arch/arm/mach-bcm/kona.c | 3 --- arch/arm/mach-bcm/kona.h | 5 +++++ 4 files changed, 20 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 5f5740fc334f..28f90a01e3ac 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -18,7 +18,6 @@ config ARCH_BCM_MOBILE select ARM_GIC select GPIO_BCM_KONA select TICK_ONESHOT - select CACHE_L2X0 select HAVE_ARM_ARCH_TIMER select PINCTRL help @@ -43,6 +42,17 @@ config ARCH_BCM_21664 Enable support for the the BCM21664 family, which includes BCM21663 and BCM21664 variants. +config ARCH_BCM_MOBILE_L2_CACHE + bool "Broadcom mobile SoC level 2 cache support" + depends on (ARCH_BCM_281XX || ARCH_BCM_21664) + default y + select CACHE_L2X0 + select ARCH_BCM_MOBILE_SMC + +config ARCH_BCM_MOBILE_SMC + bool + depends on ARCH_BCM_281XX || ARCH_BCM_21664 + endmenu endif diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 7fb9b0402204..51549814f7cd 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -17,7 +17,10 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o # BCM281XX and BCM21664 L2 cache control -obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm_kona_smc.o bcm_kona_smc_asm.o kona.o +obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona.o + +# Support for secure monitor traps +obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o bcm_kona_smc_asm.o plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c index ecdd71340a46..60b5dd5c866c 100644 --- a/arch/arm/mach-bcm/kona.c +++ b/arch/arm/mach-bcm/kona.c @@ -22,9 +22,6 @@ void __init kona_l2_cache_init(void) unsigned int result; int ret; - if (!IS_ENABLED(CONFIG_CACHE_L2X0)) - return; - ret = bcm_kona_smc_init(); if (ret) { pr_info("Secure API not available (%d). Skipping L2 init.\n", diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h index 3a7a017c29cd..110185f7aad3 100644 --- a/arch/arm/mach-bcm/kona.h +++ b/arch/arm/mach-bcm/kona.h @@ -11,4 +11,9 @@ * GNU General Public License for more details. */ +#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE + void __init kona_l2_cache_init(void); +#else +#define kona_l2_cache_init() ((void)0) +#endif -- cgit v1.2.3 From d5c627b5751ed44c0eff6c12e658097edf6338de Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:08 -0500 Subject: ARM: bcm: tidy up a few includes Clean up a few header file includes, eliminating a few that are not really needed and putting in their place some that are. Signed-off-by: Alex Elder Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/board_bcm21664.c | 3 +-- arch/arm/mach-bcm/kona.c | 5 +++-- arch/arm/mach-bcm/kona.h | 3 +-- 3 files changed, 5 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c index acc1573fd005..1091637638f1 100644 --- a/arch/arm/mach-bcm/board_bcm21664.c +++ b/arch/arm/mach-bcm/board_bcm21664.c @@ -11,13 +11,12 @@ * GNU General Public License for more details. */ -#include #include #include +#include #include -#include "bcm_kona_smc.h" #include "kona.h" #define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr" diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c index 60b5dd5c866c..b31970377c20 100644 --- a/arch/arm/mach-bcm/kona.c +++ b/arch/arm/mach-bcm/kona.c @@ -11,11 +11,12 @@ * GNU General Public License for more details. */ -#include + +#include +#include #include #include "bcm_kona_smc.h" -#include "kona.h" void __init kona_l2_cache_init(void) { diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h index 110185f7aad3..46f84a95ab1c 100644 --- a/arch/arm/mach-bcm/kona.h +++ b/arch/arm/mach-bcm/kona.h @@ -12,8 +12,7 @@ */ #ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE - -void __init kona_l2_cache_init(void); +void kona_l2_cache_init(void); #else #define kona_l2_cache_init() ((void)0) #endif -- cgit v1.2.3 From 8b9c550e37ff4e4d0de2890a835f44a7813e3423 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:09 -0500 Subject: ARM: bcm: use inline assembly for "smc" request Move the code that implements the "smc" call into a C function that uses inline assembly. This allows us to make that function private, and enables us to get rid of "arch/arm/mach-bcm/bcm_kona_smc_asm.S". Rename what had been the "buffer_addr" argument to be "buffer_phys" so it's consistent with other usage in this file. Since it's now easy to do, verify that r12 contains SEC_EXIT_NORMAL upon completion of the SMC. There really isn't a good way to handle the abnormal completion of a secure monitor request. Since "bcm_kona_smc.h" is now only included from C files, eliminate the #ifndef __ASSEMBLY__. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/Makefile | 7 +++--- arch/arm/mach-bcm/bcm_kona_smc.c | 46 +++++++++++++++++++++++++++++++++++- arch/arm/mach-bcm/bcm_kona_smc.h | 6 ----- arch/arm/mach-bcm/bcm_kona_smc_asm.S | 41 -------------------------------- 4 files changed, 49 insertions(+), 51 deletions(-) delete mode 100644 arch/arm/mach-bcm/bcm_kona_smc_asm.S (limited to 'arch') diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 51549814f7cd..d5b60feda8ad 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -20,9 +20,10 @@ obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona.o # Support for secure monitor traps -obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o bcm_kona_smc_asm.o -plus_sec := $(call as-instr,.arch_extension sec,+sec) -AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) +obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o +ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec) +CFLAGS_bcm_kona_smc.o += -Wa,-march=armv7-a+sec -DREQUIRES_SEC +endif # BCM2835 obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index 6fdcf96ca54e..cc81c86f24b5 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -76,6 +76,50 @@ int __init bcm_kona_smc_init(void) return 0; } +/* + * Since interrupts are disabled in the open mode, we must keep + * interrupts disabled in secure mode by setting R5=0x3. If interrupts + * are enabled in open mode, we can set R5=0x0 to allow interrupts in + * secure mode. If we did this, the secure monitor would return back + * control to the open mode to handle the interrupt prior to completing + * the secure service. If this happened, R12 would not be + * SEC_EXIT_NORMAL and we would need to call SMC again after resetting + * R5 (it gets clobbered by the secure monitor) and setting R4 to + * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor + * to finish up the previous uncompleted secure service. + */ +static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys) +{ + register u32 ip asm("ip"); /* Also called r12 */ + register u32 r0 asm("r0"); + register u32 r4 asm("r4"); + register u32 r5 asm("r5"); + register u32 r6 asm("r6"); + + r4 = service_id; + r5 = 0x3; /* Keep IRQ and FIQ off in SM */ + r6 = buffer_phys; + + asm volatile ( + /* Make sure we got the registers we want */ + __asmeq("%0", "ip") + __asmeq("%1", "r0") + __asmeq("%2", "r4") + __asmeq("%3", "r5") + __asmeq("%4", "r6") +#ifdef REQUIRES_SEC + ".arch_extension sec\n" +#endif + " smc #0\n" + : "=r" (ip), "=r" (r0) + : "r" (r4), "r" (r5), "r" (r6) + : "r1", "r2", "r3", "r7", "lr"); + + BUG_ON(ip != SEC_EXIT_NORMAL); + + return r0; +} + /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */ static void __bcm_kona_smc(void *info) { @@ -95,7 +139,7 @@ static void __bcm_kona_smc(void *info) flush_cache_all(); /* Trap into Secure Monitor and record the request result */ - data->result = bcm_kona_smc_asm(data->service_id, bcm_smc_buffer_phys); + data->result = bcm_kona_do_smc(data->service_id, bcm_smc_buffer_phys); } unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1, diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h index 629e64a89982..2e29ec67e414 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.h +++ b/arch/arm/mach-bcm/bcm_kona_smc.h @@ -21,7 +21,6 @@ #define SEC_ROM_RET_OK 0x00000001 #define SEC_EXIT_NORMAL 0x1 -#ifndef __ASSEMBLY__ extern int __init bcm_kona_smc_init(void); extern unsigned bcm_kona_smc(unsigned service_id, @@ -30,9 +29,4 @@ extern unsigned bcm_kona_smc(unsigned service_id, unsigned arg2, unsigned arg3); -extern int bcm_kona_smc_asm(u32 service_id, - u32 buffer_addr); - -#endif /* __ASSEMBLY__ */ - #endif /* BCM_KONA_SMC_H */ diff --git a/arch/arm/mach-bcm/bcm_kona_smc_asm.S b/arch/arm/mach-bcm/bcm_kona_smc_asm.S deleted file mode 100644 index a1608480d60d..000000000000 --- a/arch/arm/mach-bcm/bcm_kona_smc_asm.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2013 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "bcm_kona_smc.h" - -/* - * int bcm_kona_smc_asm(u32 service_id, u32 buffer_addr) - */ - -ENTRY(bcm_kona_smc_asm) - stmfd sp!, {r4-r12, lr} - mov r4, r0 @ service_id - mov r5, #3 @ Keep IRQ and FIQ off in SM - /* - * Since interrupts are disabled in the open mode, we must keep - * interrupts disabled in secure mode by setting R5=0x3. If interrupts - * are enabled in open mode, we can set R5=0x0 to allow interrupts in - * secure mode. If we did this, the secure monitor would return back - * control to the open mode to handle the interrupt prior to completing - * the secure service. If this happened, R12 would not be - * SEC_EXIT_NORMAL and we would need to call SMC again after resetting - * R5 (it gets clobbered by the secure monitor) and setting R4 to - * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor - * to finish up the previous uncompleted secure service. - */ - mov r6, r1 @ buffer_addr - smc #0 - /* Check r12 for SEC_EXIT_NORMAL here if interrupts are enabled */ - ldmfd sp!, {r4-r12, pc} -ENDPROC(bcm_kona_smc_asm) -- cgit v1.2.3 From ed24f446ab82e3f39c4a45357186ca76368301e4 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:10 -0500 Subject: ARM: bcm: rewrite commentary for bcm_kona_do_smc() The block of comments in bcm_kona_do_smc() are somewhat confusing. This patch attempts to clarify what's going on. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/bcm_kona_smc.c | 38 ++++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c index cc81c86f24b5..a55a7ecf146a 100644 --- a/arch/arm/mach-bcm/bcm_kona_smc.c +++ b/arch/arm/mach-bcm/bcm_kona_smc.c @@ -77,16 +77,34 @@ int __init bcm_kona_smc_init(void) } /* - * Since interrupts are disabled in the open mode, we must keep - * interrupts disabled in secure mode by setting R5=0x3. If interrupts - * are enabled in open mode, we can set R5=0x0 to allow interrupts in - * secure mode. If we did this, the secure monitor would return back - * control to the open mode to handle the interrupt prior to completing - * the secure service. If this happened, R12 would not be - * SEC_EXIT_NORMAL and we would need to call SMC again after resetting - * R5 (it gets clobbered by the secure monitor) and setting R4 to - * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor - * to finish up the previous uncompleted secure service. + * int bcm_kona_do_smc(u32 service_id, u32 buffer_addr) + * + * Only core 0 can run the secure monitor code. If an "smc" request + * is initiated on a different core it must be redirected to core 0 + * for execution. We rely on the caller to handle this. + * + * Each "smc" request supplies a service id and the address of a + * buffer containing parameters related to the service to be + * performed. A flags value defines the behavior of the level 2 + * cache and interrupt handling while the secure monitor executes. + * + * Parameters to the "smc" request are passed in r4-r6 as follows: + * r4 service id + * r5 flags (SEC_ROM_*) + * r6 physical address of buffer with other parameters + * + * Execution of an "smc" request produces two distinct results. + * + * First, the secure monitor call itself (regardless of the specific + * service request) can succeed, or can produce an error. When an + * "smc" request completes this value is found in r12; it should + * always be SEC_EXIT_NORMAL. + * + * In addition, the particular service performed produces a result. + * The values that should be expected depend on the service. We + * therefore return this value to the caller, so it can handle the + * request result appropriately. This result value is found in r0 + * when the "smc" request completes. */ static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys) { -- cgit v1.2.3 From eeda4cb92ee0fb63a5917738e107b0bc8168079e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:53:11 -0500 Subject: ARM: bcm: rename "kona.h" and "kona.c" These source files contain only level-2 cache initialization code, so rename them to make that fact more obvious. Signed-off-by: Alex Elder Reviewed-by: Tim Kryger Reviewed-by: Markus Mayer Reviewed-by: Matt Porter Signed-off-by: Matt Porter --- arch/arm/mach-bcm/Makefile | 2 +- arch/arm/mach-bcm/board_bcm21664.c | 2 +- arch/arm/mach-bcm/board_bcm281xx.c | 2 +- arch/arm/mach-bcm/kona.c | 47 -------------------------------------- arch/arm/mach-bcm/kona.h | 18 --------------- arch/arm/mach-bcm/kona_l2_cache.c | 47 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-bcm/kona_l2_cache.h | 18 +++++++++++++++ 7 files changed, 68 insertions(+), 68 deletions(-) delete mode 100644 arch/arm/mach-bcm/kona.c delete mode 100644 arch/arm/mach-bcm/kona.h create mode 100644 arch/arm/mach-bcm/kona_l2_cache.c create mode 100644 arch/arm/mach-bcm/kona_l2_cache.h (limited to 'arch') diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index d5b60feda8ad..731292114975 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o # BCM281XX and BCM21664 L2 cache control -obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona.o +obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o # Support for secure monitor traps obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c index 1091637638f1..f0521cc0640d 100644 --- a/arch/arm/mach-bcm/board_bcm21664.c +++ b/arch/arm/mach-bcm/board_bcm21664.c @@ -17,7 +17,7 @@ #include -#include "kona.h" +#include "kona_l2_cache.h" #define RSTMGR_DT_STRING "brcm,bcm21664-resetmgr" diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c index 6be54c10f8cb..1ac59fc0cb15 100644 --- a/arch/arm/mach-bcm/board_bcm281xx.c +++ b/arch/arm/mach-bcm/board_bcm281xx.c @@ -17,7 +17,7 @@ #include -#include "kona.h" +#include "kona_l2_cache.h" #define SECWDOG_OFFSET 0x00000000 #define SECWDOG_RESERVED_MASK 0xe2000000 diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c deleted file mode 100644 index b31970377c20..000000000000 --- a/arch/arm/mach-bcm/kona.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2012-2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include -#include -#include - -#include "bcm_kona_smc.h" - -void __init kona_l2_cache_init(void) -{ - unsigned int result; - int ret; - - ret = bcm_kona_smc_init(); - if (ret) { - pr_info("Secure API not available (%d). Skipping L2 init.\n", - ret); - return; - } - - result = bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); - if (result != SEC_ROM_RET_OK) { - pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n", - result); - return; - } - - /* - * The aux_val and aux_mask have no effect since L2 cache is already - * enabled. Pass 0s for aux_val and 1s for aux_mask for default value. - */ - ret = l2x0_of_init(0, ~0); - if (ret) - pr_err("Couldn't enable L2 cache: %d\n", ret); -} diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h deleted file mode 100644 index 46f84a95ab1c..000000000000 --- a/arch/arm/mach-bcm/kona.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2012-2014 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE -void kona_l2_cache_init(void); -#else -#define kona_l2_cache_init() ((void)0) -#endif diff --git a/arch/arm/mach-bcm/kona_l2_cache.c b/arch/arm/mach-bcm/kona_l2_cache.c new file mode 100644 index 000000000000..b31970377c20 --- /dev/null +++ b/arch/arm/mach-bcm/kona_l2_cache.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012-2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include + +#include "bcm_kona_smc.h" + +void __init kona_l2_cache_init(void) +{ + unsigned int result; + int ret; + + ret = bcm_kona_smc_init(); + if (ret) { + pr_info("Secure API not available (%d). Skipping L2 init.\n", + ret); + return; + } + + result = bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); + if (result != SEC_ROM_RET_OK) { + pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n", + result); + return; + } + + /* + * The aux_val and aux_mask have no effect since L2 cache is already + * enabled. Pass 0s for aux_val and 1s for aux_mask for default value. + */ + ret = l2x0_of_init(0, ~0); + if (ret) + pr_err("Couldn't enable L2 cache: %d\n", ret); +} diff --git a/arch/arm/mach-bcm/kona_l2_cache.h b/arch/arm/mach-bcm/kona_l2_cache.h new file mode 100644 index 000000000000..46f84a95ab1c --- /dev/null +++ b/arch/arm/mach-bcm/kona_l2_cache.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2012-2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE +void kona_l2_cache_init(void); +#else +#define kona_l2_cache_init() ((void)0) +#endif -- cgit v1.2.3 From fd33615897a03985d29536dbeb1e4f6cb39a43e4 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Tue, 1 Apr 2014 12:26:19 +0400 Subject: ARM: bcm: Restrict ARCH_BCM selection to ARCH_MULTI_V6_V7 Currently, Broadcom SoC options are shown whenever ARCH_MULTIPLATFORM is enabled. Restrict this so they are only seen when ARCH_MULTI_V6_V7 variants are enabled. Signed-off-by: Alexander Shiyan [mporter: added commit log message] Signed-off-by: Matt Porter --- arch/arm/mach-bcm/Kconfig | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 28f90a01e3ac..7f6ed6c3d367 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -1,13 +1,10 @@ config ARCH_BCM - bool "Broadcom SoC Support" - depends on ARCH_MULTIPLATFORM + bool "Broadcom SoC Support" if ARCH_MULTI_V6_V7 help - This enables support for Broadcom ARM based SoC - chips - -if ARCH_BCM + This enables support for Broadcom ARM based SoC chips menu "Broadcom SoC Selection" + depends on ARCH_BCM config ARCH_BCM_MOBILE bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7 @@ -100,5 +97,3 @@ config ARCH_BCM_5301X network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx endmenu - -endif -- cgit v1.2.3 From ffc1086a5512c9b6b3dacc2648cc8ba7fa530cb9 Mon Sep 17 00:00:00 2001 From: Scott Branden Date: Fri, 18 Apr 2014 10:13:20 -0700 Subject: ARM: mach-bcm: add ARM_ERRATA_775420 ARM_ERRATA_775420 needs to be enabled. A data cache maintenance operation which aborts, followed by an ISB, without any DSB in-between, might lead to deadlock. Affects: bug present in Cortex-A9 r3p0 and earlier. Fixed in r4p0. Cortex-A9 r3p0 is used in a multitude of Broadcom parts including the bcm21664, bcm281xx, 5301x families of devices. Signed-off-by: Scott Branden Tested-by: Markus Mayer Reviewed-by: Markus Mayer Reviewed-by: Alex Elder Signed-off-by: Matt Porter --- arch/arm/mach-bcm/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 7f6ed6c3d367..daead394b75c 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -12,6 +12,7 @@ config ARCH_BCM_MOBILE select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_775420 select ARM_GIC select GPIO_BCM_KONA select TICK_ONESHOT -- cgit v1.2.3 From 0b2d70764bb39242dcc49c0ebd10fcb8258ce5fa Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 25 Apr 2014 11:01:08 -0600 Subject: x86/PCI: Fix Broadcom CNB20LE unintended sign extension In the expression "word1 << 16", word1 starts as u16, but is promoted to a signed int, then sign-extended to resource_size_t, which is probably not what was intended. Cast to resource_size_t to avoid the sign extension. Found by Coverity (CID 138749, 138750). Signed-off-by: Bjorn Helgaas --- arch/x86/pci/broadcom_bus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c index 614392ced7d6..bb461cfd01ab 100644 --- a/arch/x86/pci/broadcom_bus.c +++ b/arch/x86/pci/broadcom_bus.c @@ -60,8 +60,8 @@ static void __init cnb20le_res(u8 bus, u8 slot, u8 func) word1 = read_pci_config_16(bus, slot, func, 0xc4); word2 = read_pci_config_16(bus, slot, func, 0xc6); if (word1 != word2) { - res.start = (word1 << 16) | 0x0000; - res.end = (word2 << 16) | 0xffff; + res.start = ((resource_size_t) word1 << 16) | 0x0000; + res.end = ((resource_size_t) word2 << 16) | 0xffff; res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; update_res(info, res.start, res.end, res.flags, 0); } -- cgit v1.2.3 From 4e4ba9441fb431f3996de2454522342e0b1d9263 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 14 Apr 2014 15:30:09 -0600 Subject: x86/PCI: Don't try to move IORESOURCE_PCI_FIXED resources Don't attempt to move resource marked IORESOURCE_PCI_FIXED, even if pci_claim_resource() fails. In some cases, these are legacy resources that cannot be moved. Signed-off-by: Bjorn Helgaas --- arch/x86/pci/i386.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index db6b1ab43255..6db58d68feb5 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -271,11 +271,16 @@ static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass) "BAR %d: reserving %pr (d=%d, p=%d)\n", idx, r, disabled, pass); if (pci_claim_resource(dev, idx) < 0) { - /* We'll assign a new address later */ - pcibios_save_fw_addr(dev, - idx, r->start); - r->end -= r->start; - r->start = 0; + if (r->flags & IORESOURCE_PCI_FIXED) { + dev_info(&dev->dev, "BAR %d %pR is immovable\n", + idx, r); + } else { + /* We'll assign a new address later */ + pcibios_save_fw_addr(dev, + idx, r->start); + r->end -= r->start; + r->start = 0; + } } } } -- cgit v1.2.3 From 44c8bdbe32aa51fe673c7a86b1e8f45b952d7759 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 14 Apr 2014 15:35:21 -0600 Subject: x86/PCI: Mark ATI SBx00 HPET BAR as IORESOURCE_PCI_FIXED Bodo reported that on the Asrock M3A UCC, v3.12.6 hangs during boot unless he uses "pci=nocrs". This regression was caused by 7bc5e3f2be32 ("x86/PCI: use host bridge _CRS info by default on 2008 and newer machines"), which appeared in v2.6.34. The reason is that the HPET address appears in a PCI device BAR, and this address is not contained in any of the host bridge windows. Linux moves the PCI BAR into a window, but the original address was published via the HPET table and an ACPI device, so changing the BAR is a bad idea. Here's the dmesg info: ACPI: HPET id: 0x43538301 base: 0xfed00000 pci_root PNP0A03:00: host bridge window [mem 0xd0000000-0xdfffffff] pci_root PNP0A03:00: host bridge window [mem 0xf0000000-0xfebfffff] pci 0000:00:14.0: [1002:4385] type 0 class 0x000c05 pci 0000:00:14.0: reg 14: [mem 0xfed00000-0xfed003ff] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 pnp 00:06: Plug and Play ACPI device, IDs PNP0103 (active) pnp 00:06: [mem 0xfed00000-0xfed003ff] When we notice the BAR is not in a host bridge window, we try to move it, but that causes a hang shortly thereafter: pci 0000:00:14.0: no compatible bridge window for [mem 0xfed00000-0xfed003ff] pci 0000:00:14.0: BAR 1: assigned [mem 0xf0000000-0xf00003ff] This patch marks the BAR as IORESOURCE_PCI_FIXED to prevent Linux from moving it. This depends on a previous patch ("x86/PCI: Don't try to move IORESOURCE_PCI_FIXED resources") to check for this flag when pci_claim_resource() fails. Link: https://bugzilla.kernel.org/show_bug.cgi?id=68591 Reported-and-tested-by: Bodo Eggert <7eggert@gmx.de> Signed-off-by: Bjorn Helgaas --- arch/x86/pci/fixup.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 94ae9ae9574f..ef334a003f3c 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include static void pci_fixup_i450nx(struct pci_dev *d) @@ -526,6 +527,19 @@ static void sb600_disable_hpet_bar(struct pci_dev *dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar); +#ifdef CONFIG_HPET_TIMER +static void sb600_hpet_quirk(struct pci_dev *dev) +{ + struct resource *r = &dev->resource[1]; + + if (r->flags & IORESOURCE_MEM && r->start == hpet_address) { + r->flags |= IORESOURCE_PCI_FIXED; + dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n"); + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk); +#endif + /* * Twinhead H12Y needs us to block out a region otherwise we map devices * there and any access kills the box. -- cgit v1.2.3 From 6eccc52b448e4bd5cfba4752cc678bed168f401a Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 16:41:16 +0200 Subject: ARM: mvebu: enable the SDHCI interface on Armada 385 In commit "mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller", the sdhci-pxav3 driver has been extended to also be usable on Armada 38x platforms. Therefore, this commit adds the necessary Device Tree informations to declare this SDHCI interface in the Armada 38x SoC, and also in the Armada 385 Development Board. Signed-off-by: Thomas Petazzoni Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1397486478-16991-2-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-385-db.dts | 8 ++++++++ arch/arm/boot/dts/armada-38x.dtsi | 9 +++++++++ 2 files changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 6828d77696a6..959aeedc22d3 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -101,6 +101,14 @@ reg = <0x1000000 0x3f000000>; }; }; + + sdhci@d8000 { + clock-frequency = <200000000>; + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + }; }; pcie-controller { diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 2e1661f1c30e..7e1b2434b10c 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -382,6 +382,15 @@ clocks = <&coredivclk 0>; status = "disabled"; }; + + sdhci@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg = <0xd8000 0x1000>, <0xdc000 0x100>; + interrupts = <0 25 0x4>; + clocks = <&gateclk 17>; + mrvl,clk-delay-cycles = <0x1F>; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 313340d53298465a3f18859b0aff096c3fafaa8f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 16:41:17 +0200 Subject: ARM: configs: add CONFIG_MMC_SDHCI_PXAV3 to the mvebu_v7_defconfig The Marvell Armada 38x platform has a SDHCI interface managed by the sdhci-pxav3 MMC host driver. It therefore makes sense to enable this driver in mvebu_v7_defconfig. Signed-off-by: Thomas Petazzoni Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1397486478-16991-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/configs/mvebu_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index b1e514e81134..04348ee3e33e 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -83,6 +83,7 @@ CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_STORAGE=y CONFIG_USB_XHCI_HCD=y CONFIG_MMC=y +CONFIG_MMC_SDHCI_PXAV3=y CONFIG_MMC_MVSDIO=y CONFIG_NEW_LEDS=y CONFIG_LEDS_GPIO=y -- cgit v1.2.3 From d175b6e494298b84f383aaec8c16215d17bdbe28 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 15 Apr 2014 17:00:04 +0200 Subject: ARM: mvebu: add Device Tree description of AHCI interfaces on Armada 38x The Marvell Armada 38x processors contain two AHCI compatible interfaces. This commit adds the Device Tree description of those interfaces at the SoC level, and also enables them on the Armada 385 DB platform, which allows access to both interfaces through SATA ports. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397574006-5868-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-385-db.dts | 8 ++++++++ arch/arm/boot/dts/armada-38x.dtsi | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 959aeedc22d3..1ad988b3a75c 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -81,6 +81,14 @@ }; }; + sata@a8000 { + status = "okay"; + }; + + sata@e0000 { + status = "okay"; + }; + flash@d0000 { status = "okay"; num-cs = <1>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 7e1b2434b10c..7c3f3ddd9096 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -365,6 +365,22 @@ reg = <0x72004 0x4>; }; + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = ; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = ; + clocks = <&gateclk 30>; + status = "disabled"; + }; + coredivclk: clock@e4250 { compatible = "marvell,armada-380-corediv-clock"; reg = <0xe4250 0xc>; -- cgit v1.2.3 From 6bc4b91d751e2eccf1f9742e8ecf11c78c8d88c9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 15 Apr 2014 17:00:05 +0200 Subject: ARM: configs: add ahci_mvebu to mvebu_v7_defconfig The Marvell Armada 38x platform needs the ahci_mvebu driver enabled for the AHCI interfaces, so this commit enables the corresponding Kconfig option in mvebu_v7_defconfig. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397574006-5868-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/configs/mvebu_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index 04348ee3e33e..2485a5ef9c4c 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -40,6 +40,7 @@ CONFIG_CFG80211=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_SD=y CONFIG_ATA=y +CONFIG_AHCI_MVEBU=y CONFIG_SATA_MV=y CONFIG_NETDEVICES=y CONFIG_MVNETA=y -- cgit v1.2.3 From 64939dc5bf264c34d02b3c51296e10730065f5d1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 18 Apr 2014 09:41:46 +0200 Subject: ARM: mvebu: use clocks property for serial ports Back when the Armada 370 and Armada XP initial support was introduced, the only way to pass the clock frequency to the of_serial driver was through a clock-frequency Device Tree property. Thanks to 0bbeb3c3e84bc963d1c66661e082d207023b0e5c ('of serial port driver - add clk_get_rate() support'), it is possible to use the standard 'clocks' DT property to reference the clock used for a particular UART controller. This clock is then used by the of_serial driver to retrieve the clock rate. This commit modifies the SoC-level Device Tree files of Armada 370, Armada XP, Armada 375 and Armada 38x to use this possibility. Since there is no gatable clock for the UART controllers, we simply reference the TCLK, which is the main SoC clock for the peripherals. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397806908-7550-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-xp.dtsi | 2 ++ arch/arm/boot/dts/armada-375.dtsi | 2 ++ arch/arm/boot/dts/armada-38x.dtsi | 2 ++ arch/arm/boot/dts/armada-xp.dtsi | 2 ++ 4 files changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 10d778605ea7..46aaee7f8df2 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -157,6 +157,7 @@ reg-shift = <2>; interrupts = <41>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; serial@12100 { @@ -165,6 +166,7 @@ reg-shift = <2>; interrupts = <42>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index a7e0d543dff1..6a3b7410817e 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -201,6 +201,7 @@ reg-shift = <2>; interrupts = ; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -210,6 +211,7 @@ reg-shift = <2>; interrupts = ; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 7c3f3ddd9096..0796cde504e7 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -179,6 +179,7 @@ reg-shift = <2>; interrupts = ; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; @@ -188,6 +189,7 @@ reg-shift = <2>; interrupts = ; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 0a7dff6519ce..5902e8359c91 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -58,6 +58,7 @@ reg-shift = <2>; interrupts = <43>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; serial@12300 { @@ -66,6 +67,7 @@ reg-shift = <2>; interrupts = <44>; reg-io-width = <1>; + clocks = <&coreclk 0>; status = "disabled"; }; -- cgit v1.2.3 From 0d9179fb3369646362fc04c5fb57cd0043f2c647 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 18 Apr 2014 09:41:47 +0200 Subject: ARM: mvebu: remove clock-frequency of serial port Device Tree nodes Now that the Armada 370/375/38x/XP SoC-level Device Tree files have the proper "clocks" property in their UART controllers node, it is no longer useful to have the clock-frequency property defined in the board-level Device Tree files. Therefore, this commit gets rid of all the useless 'clock-frequency' properties. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397806908-7550-5-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-370-db.dts | 1 - arch/arm/boot/dts/armada-370-mirabox.dts | 1 - arch/arm/boot/dts/armada-370-netgear-rn102.dts | 1 - arch/arm/boot/dts/armada-370-netgear-rn104.dts | 1 - arch/arm/boot/dts/armada-370-rd.dts | 1 - arch/arm/boot/dts/armada-375-db.dts | 1 - arch/arm/boot/dts/armada-385-db.dts | 1 - arch/arm/boot/dts/armada-385-rd.dts | 1 - arch/arm/boot/dts/armada-xp-axpwifiap.dts | 2 -- arch/arm/boot/dts/armada-xp-db.dts | 4 ---- arch/arm/boot/dts/armada-xp-gp.dts | 4 ---- arch/arm/boot/dts/armada-xp-matrix.dts | 4 ---- arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 -- 13 files changed, 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 82f238a9063f..ba1a43118f8f 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -35,7 +35,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; sata@a0000 { diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 2354fe023ee0..097df7d8f0f6 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -47,7 +47,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; timer@20300 { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index 651aeb5ef439..d6d572e5af32 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -50,7 +50,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 4e27587667bf..c5fe8b5dcdc7 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -50,7 +50,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 3e2c857d6000..4169f4096ea3 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -51,7 +51,6 @@ internal-regs { serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; sata@a0000 { diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts index 9378d3136b41..2f26b963eee9 100644 --- a/arch/arm/boot/dts/armada-375-db.dts +++ b/arch/arm/boot/dts/armada-375-db.dts @@ -68,7 +68,6 @@ }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 1ad988b3a75c..7fcbc0d2a85f 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -55,7 +55,6 @@ }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts index 45250c88814b..4b39bed4ed07 100644 --- a/arch/arm/boot/dts/armada-385-rd.dts +++ b/arch/arm/boot/dts/armada-385-rd.dts @@ -51,7 +51,6 @@ }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index d83d7d69ac01..a55a97a70505 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -95,12 +95,10 @@ }; serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 448373c4b0e5..2b598ef32285 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -106,19 +106,15 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; serial@12200 { - clock-frequency = <250000000>; status = "okay"; }; serial@12300 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 61bda687f782..eb0013f000b0 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -104,19 +104,15 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; serial@12200 { - clock-frequency = <250000000>; status = "okay"; }; serial@12300 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index c2242745b9b8..25674fe81f70 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -37,19 +37,15 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; serial@12200 { - clock-frequency = <250000000>; status = "okay"; }; serial@12300 { - clock-frequency = <250000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 985948ce67b3..cf26d1313d5f 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -72,11 +72,9 @@ internal-regs { serial@12000 { - clock-frequency = <250000000>; status = "okay"; }; serial@12100 { - clock-frequency = <250000000>; status = "okay"; }; pinctrl { -- cgit v1.2.3 From 953f9c5d7cabc3dcd436fd11d50910565230f7cc Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 18 Apr 2014 09:41:48 +0200 Subject: ARM: mvebu: don't use clocks property in UART node for Netgear RN2120 The Netgear RN2120 was not using the same strategy as the other Armada 370/375/38x/XP boards: it was using a 'clocks' property and not the 'clock-frequency' property in its UART controller Device Tree node. However, now that this clock reference is present at the SoC-level, there is no point in duplicating it at the board-level. Signed-off-by: Thomas Petazzoni Acked-by: Gregory CLEMENT Link: https://lkml.kernel.org/r/1397806908-7550-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-xp-netgear-rn2120.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index ff049ee862eb..0cf999abc4ed 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -138,7 +138,6 @@ }; serial@12000 { - clocks = <&coreclk 0>; status = "okay"; }; -- cgit v1.2.3 From f672e4817fd1ffb7c3aeb9338f8110b8149db933 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 24 Apr 2014 17:23:23 -0300 Subject: ARM: mvebu: Enable the thermal sensor in Armada 375 SoC This commit enables the thermal sensor found in Armada 375 SoCs. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1398371004-15807-10-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-375.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 6a3b7410817e..3b6de4c0e379 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -416,6 +416,12 @@ status = "disabled"; }; + thermal@e8078 { + compatible = "marvell,armada375-thermal"; + reg = <0xe8078 0x4>, <0xe807c 0x8>; + status = "okay"; + }; + coreclk: mvebu-sar@e8204 { compatible = "marvell,armada-375-core-clock"; reg = <0xe8204 0x04>; -- cgit v1.2.3 From 0fb28811dd6ff30aec3cd386745309aa63d1d106 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:14 +0200 Subject: ARM: orion5x: move interrupt controller node into ocp The interrupt controller node was located outside of the ocp@f1000000 node, which doesn't make much sense: like any other device, the interrupt controller has registers located in the "Internal Registers Window", so it is much more logical to have it under the ocp@f1000000 node. It is even more important as we are going to move Orion5x to use the Device Tree binding of the mvebu-mbus driver. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-11-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 174d89241f70..da57fb9f87b9 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -17,13 +17,6 @@ gpio0 = &gpio0; }; - intc: interrupt-controller { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf1020200 0x08>; - }; - ocp@f1000000 { compatible = "simple-bus"; ranges = <0x00000000 0xf1000000 0x4000000 @@ -79,6 +72,13 @@ status = "disabled"; }; + intc: interrupt-controller@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x08>; + }; + wdt@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; -- cgit v1.2.3 From 48be9707b4d4e85c950fc9c3ae4ed574a453c060 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:15 +0200 Subject: ARM: orion5x: switch to preprocessor includes in DT This commit switches the Orion5x Device Tree files to use C preprocessor based includes, as it will allow us to use definitions from header files in future commits. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-12-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 3 ++- arch/arm/boot/dts/orion5x.dtsi | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 5ed6c1376901..0245bb3a4cb6 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -7,7 +7,8 @@ */ /dts-v1/; -/include/ "orion5x.dtsi" + +#include "orion5x.dtsi" / { model = "LaCie Ethernet Disk mini V2"; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index da57fb9f87b9..2364e3dbc33c 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -6,7 +6,7 @@ * warranty of any kind, whether express or implied. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { model = "Marvell Orion5x SoC"; -- cgit v1.2.3 From 2a93474299e5c9e39678596ff69fd5dbf1914769 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:16 +0200 Subject: ARM: orion5x: use existing dt-bindings include for Device Tree files The orion5x-lacie-ethernet-disk-mini-v2.dts can benefit from using gpio.h and input.h dt-bindings headers to replace hardcoded values by more meaningful macros. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-13-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 0245bb3a4cb6..24f1ce7c9c10 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -8,6 +8,8 @@ /dts-v1/; +#include +#include #include "orion5x.dtsi" / { @@ -40,8 +42,8 @@ #size-cells = <0>; button@1 { label = "Power-on Switch"; - linux,code = <116>; /* KEY_POWER */ - gpios = <&gpio0 18 0>; + linux,code = ; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; }; }; @@ -50,7 +52,7 @@ led@1 { label = "power:blue"; - gpios = <&gpio0 16 1>; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; }; }; -- cgit v1.2.3 From 5c697664858945b7a67e74e9c196a8f705c9e88f Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:17 +0200 Subject: ARM: orion5x: convert DT to use the mvebu-mbus driver This commit switches the Orion5x Device Tree files to use the DT representation and probing for the mvebu-mbus driver. The changes are mainly: * Re-organize the DT to follow the same organization as the one used on Armada 370/XP, which is needed for mvebu-mbus to work: a top-level soc { ... } node, which corresponds to the MBus bus, and a sub-node internal-regs { ... } for all peripherals whose register sit only in the "Internal Register Window". This change re-indents by one level the definition of all nodes in the Device Tree, which explains the large change. * Use custom functions orion5x_dt_init_early() and orion5x_dt_init_time() instead of orion5x_init_early() and orion5x_timer_init() as we now want the MBus driver to be probed from the Device Tree. We still use the old-style timer initialization, but that will be changed in a followup commit. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-14-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 23 +- arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 24 ++ arch/arm/boot/dts/orion5x.dtsi | 245 +++++++++++---------- arch/arm/mach-orion5x/board-dt.c | 20 +- 4 files changed, 182 insertions(+), 130 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-mv88f5182.dtsi (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 24f1ce7c9c10..d66d2fa6a290 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -10,7 +10,7 @@ #include #include -#include "orion5x.dtsi" +#include "orion5x-mv88f5182.dtsi" / { model = "LaCie Ethernet Disk mini V2"; @@ -24,15 +24,20 @@ bootargs = "console=ttyS0,115200n8 earlyprintk"; }; - ocp@f1000000 { - serial@12000 { - clock-frequency = <166666667>; - status = "okay"; - }; + soc { + ranges = , + ; + + internal-regs { + serial@12000 { + clock-frequency = <166666667>; + status = "okay"; + }; - sata@80000 { - status = "okay"; - nr-ports = <2>; + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; }; }; diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi new file mode 100644 index 000000000000..ddfb4d17ff4c --- /dev/null +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "orion5x.dtsi" + +/ { + compatible = "marvell,orion5x-88f5182", "marvell,orion5x"; + + soc { + compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; + + internal-regs { + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x1500 0x20>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 2364e3dbc33c..31d46e6dbf51 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -8,6 +8,8 @@ #include "skeleton.dtsi" +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) + / { model = "Marvell Orion5x SoC"; compatible = "marvell,orion5x"; @@ -17,149 +19,154 @@ gpio0 = &gpio0; }; - ocp@f1000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0xf1000000 0x4000000 - 0xf2200000 0xf2200000 0x0000800>; - #address-cells = <1>; + soc { + #address-cells = <2>; #size-cells = <1>; + controller = <&mbusc>; - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpios = <32>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <6>, <7>, <8>, <9>; - }; - - spi@10600 { - compatible = "marvell,orion-spi"; + internal-regs { + compatible = "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - reg = <0x10600 0x28>; - status = "disabled"; - }; - - i2c@11000 { - compatible = "marvell,mv64xxx-i2c"; - reg = <0x11000 0x20>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <5>; - clock-frequency = <100000>; - status = "disabled"; - }; + #size-cells = <1>; + ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + + gpio0: gpio@10100 { + compatible = "marvell,orion-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x10100 0x40>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <6>, <7>, <8>, <9>; + }; - serial@12000 { - compatible = "ns16550a"; - reg = <0x12000 0x100>; - reg-shift = <2>; - interrupts = <3>; - /* set clock-frequency in board dts */ - status = "disabled"; - }; + spi@10600 { + compatible = "marvell,orion-spi"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + reg = <0x10600 0x28>; + status = "disabled"; + }; - serial@12100 { - compatible = "ns16550a"; - reg = <0x12100 0x100>; - reg-shift = <2>; - interrupts = <4>; - /* set clock-frequency in board dts */ - status = "disabled"; - }; + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11000 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <5>; + clock-frequency = <100000>; + status = "disabled"; + }; - intc: interrupt-controller@20200 { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x20200 0x08>; - }; + serial@12000 { + compatible = "ns16550a"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = <3>; + /* set clock-frequency in board dts */ + status = "disabled"; + }; - wdt@20300 { - compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>; - status = "okay"; - }; + serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <4>; + /* set clock-frequency in board dts */ + status = "disabled"; + }; - ehci@50000 { - compatible = "marvell,orion-ehci"; - reg = <0x50000 0x1000>; - interrupts = <17>; - status = "disabled"; - }; + intc: interrupt-controller@20200 { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20200 0x08>; + }; - xor@60900 { - compatible = "marvell,orion-xor"; - reg = <0x60900 0x100 - 0x60b00 0x100>; - status = "okay"; + wdt@20300 { + compatible = "marvell,orion-wdt"; + reg = <0x20300 0x28>; + status = "okay"; + }; - xor00 { - interrupts = <30>; - dmacap,memcpy; - dmacap,xor; + ehci@50000 { + compatible = "marvell,orion-ehci"; + reg = <0x50000 0x1000>; + interrupts = <17>; + status = "disabled"; }; - xor01 { - interrupts = <31>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + + xor@60900 { + compatible = "marvell,orion-xor"; + reg = <0x60900 0x100 + 0x60b00 0x100>; + status = "okay"; + + xor00 { + interrupts = <30>; + dmacap,memcpy; + dmacap,xor; + }; + xor01 { + interrupts = <31>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; + }; }; - }; - eth: ethernet-controller@72000 { - compatible = "marvell,orion-eth"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72000 0x4000>; - marvell,tx-checksum-limit = <1600>; - status = "disabled"; - - ethernet-port@0 { - compatible = "marvell,orion-eth-port"; - reg = <0>; - /* overwrite MAC address in bootloader */ - local-mac-address = [00 00 00 00 00 00]; - /* set phy-handle property in board file */ + eth: ethernet-controller@72000 { + compatible = "marvell,orion-eth"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72000 0x4000>; + marvell,tx-checksum-limit = <1600>; + status = "disabled"; + + ethernet-port@0 { + compatible = "marvell,orion-eth-port"; + reg = <0>; + /* overwrite MAC address in bootloader */ + local-mac-address = [00 00 00 00 00 00]; + /* set phy-handle property in board file */ + }; }; - }; - mdio: mdio-bus@72004 { - compatible = "marvell,orion-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72004 0x84>; - interrupts = <22>; - status = "disabled"; + mdio: mdio-bus@72004 { + compatible = "marvell,orion-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72004 0x84>; + interrupts = <22>; + status = "disabled"; - /* add phy nodes in board file */ - }; + /* add phy nodes in board file */ + }; + + sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <29>; + status = "disabled"; + }; - sata@80000 { - compatible = "marvell,orion-sata"; - reg = <0x80000 0x5000>; - interrupts = <29>; - status = "disabled"; + ehci@a0000 { + compatible = "marvell,orion-ehci"; + reg = <0xa0000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; }; crypto@90000 { compatible = "marvell,orion-crypto"; - reg = <0x90000 0x10000>, - <0xf2200000 0x800>; + reg = , + ; reg-names = "regs", "sram"; interrupts = <28>; status = "okay"; }; - - ehci@a0000 { - compatible = "marvell,orion-ehci"; - reg = <0xa0000 0x1000>; - interrupts = <12>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index c134a826070a..7f00897f0dd2 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -15,10 +15,14 @@ #include #include #include +#include #include #include +#include #include +#include #include +#include #include "common.h" static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { @@ -31,6 +35,16 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { {}, }; +static void orion5x_dt_init_early(void) +{ + orion_time_set_base(TIMER_VIRT_BASE); +} + +static void orion5x_dt_init_time(void) +{ + orion5x_timer_init(); +} + static void __init orion5x_dt_init(void) { char *dev_name; @@ -39,6 +53,8 @@ static void __init orion5x_dt_init(void) orion5x_id(&dev, &rev, &dev_name); printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); + BUG_ON(mvebu_mbus_dt_init()); + /* * Setup Orion address map */ @@ -71,9 +87,9 @@ static const char *orion5x_dt_compat[] = { DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)") /* Maintainer: Thomas Petazzoni */ .map_io = orion5x_map_io, - .init_early = orion5x_init_early, + .init_early = orion5x_dt_init_early, .init_irq = orion_dt_init_irq, - .init_time = orion5x_timer_init, + .init_time = orion5x_dt_init_time, .init_machine = orion5x_dt_init, .restart = orion5x_restart, .dt_compat = orion5x_dt_compat, -- cgit v1.2.3 From 2958316dd46fb37aeab229e94aa1837115074b39 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:18 +0200 Subject: ARM: orion5x: add node labels in Orion5x SoC Device Tree file In order to ease identification of devices, it is useful to have Device Tree labels on all devices. This commit adds such labels to the Orion5x SoC Device Tree file. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-15-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 31d46e6dbf51..aef5d17fe396 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -41,7 +41,7 @@ interrupts = <6>, <7>, <8>, <9>; }; - spi@10600 { + spi: spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; @@ -50,7 +50,7 @@ status = "disabled"; }; - i2c@11000 { + i2c: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; @@ -60,7 +60,7 @@ status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; @@ -69,7 +69,7 @@ status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; @@ -85,20 +85,20 @@ reg = <0x20200 0x08>; }; - wdt@20300 { + wdt: wdt@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; status = "okay"; }; - ehci@50000 { + ehci0: ehci@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x1000>; interrupts = <17>; status = "disabled"; }; - xor@60900 { + xor: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; @@ -125,7 +125,7 @@ marvell,tx-checksum-limit = <1600>; status = "disabled"; - ethernet-port@0 { + ethport: ethernet-port@0 { compatible = "marvell,orion-eth-port"; reg = <0>; /* overwrite MAC address in bootloader */ @@ -145,14 +145,14 @@ /* add phy nodes in board file */ }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <29>; status = "disabled"; }; - ehci@a0000 { + ehci1: ehci@a0000 { compatible = "marvell,orion-ehci"; reg = <0xa0000 0x1000>; interrupts = <12>; @@ -160,7 +160,7 @@ }; }; - crypto@90000 { + cesa: crypto@90000 { compatible = "marvell,orion-crypto"; reg = , ; -- cgit v1.2.3 From 7ca63532b50127773696619b7b17f79b919fc6a1 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:19 +0200 Subject: ARM: orion5x: use gpio-keys and gpio-leds instead of gpio_keys/gpio_leds in edmini_v2 As noted by Sebastian Hesselbarth, the Device Tree nodes for GPIO keys and LEDs should be named gpio-keys and gpio-leds. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-16-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index d66d2fa6a290..d85a206aaee8 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -41,7 +41,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; @@ -52,7 +52,7 @@ }; }; - gpio_leds { + gpio-leds { compatible = "gpio-leds"; led@1 { -- cgit v1.2.3 From 1fca8a2802810011e0f82e5ca5aca8ec5b62b400 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:20 +0200 Subject: ARM: orion5x: add linux,stdout-path to edmini_v2 This commit adds the new linux,stdout-path to the edmini_v2 platform, pointing to the serial device use for the console. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-17-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index d85a206aaee8..df53d25668bb 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -22,6 +22,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; }; soc { -- cgit v1.2.3 From 7e0878fccc0954f1a4f63da05f9ecaa390bd1c12 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:21 +0200 Subject: ARM: orion5x: use node labels for UART and SATA on edmini_v2 This commit converts the existing devices described in the edmini_v2 Device Tree to use node labels: the UART and SATA device. Also, it reorders the eth and mdio node label references to be sorted alphabetically. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-18-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 30 ++++++++++------------ 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index df53d25668bb..83f45a722055 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -28,18 +28,6 @@ soc { ranges = , ; - - internal-regs { - serial@12000 { - clock-frequency = <166666667>; - status = "okay"; - }; - - sata@80000 { - status = "okay"; - nr-ports = <2>; - }; - }; }; gpio-keys { @@ -63,6 +51,14 @@ }; }; +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + &mdio { status = "okay"; @@ -71,10 +67,12 @@ }; }; -ð { +&sata { status = "okay"; + nr-ports = <2>; +}; - ethernet-port@0 { - phy-handle = <ðphy>; - }; +&uart0 { + clock-frequency = <166666667>; + status = "okay"; }; -- cgit v1.2.3 From 984d37c44e6f8fd6d1781c6750cab6fe8100df39 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:22 +0200 Subject: ARM: orion5x: rename XOR node to dma-controller@
This commit renames the XOR engine Device Tree node to dma-controller@, to conform with the standard node name proposed by the ePAPR. Suggested-by: Sebastian Hesselbarth Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-19-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index aef5d17fe396..3802d4f04d42 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -98,7 +98,7 @@ status = "disabled"; }; - xor: xor@60900 { + xor: dma-controller@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60b00 0x100>; -- cgit v1.2.3 From 2864ed64ec884cfdd61430c9f1b975f9d410c1df Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:23 +0200 Subject: ARM: orion5x: add interrupt for Ethernet in Device Tree For some reason, the Ethernet interrupt was missing in the Orion5x Device Tree definition. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-20-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 3802d4f04d42..ad23ff40e0d1 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -128,6 +128,7 @@ ethport: ethernet-port@0 { compatible = "marvell,orion-eth-port"; reg = <0>; + interrupts = <21>; /* overwrite MAC address in bootloader */ local-mac-address = [00 00 00 00 00 00]; /* set phy-handle property in board file */ -- cgit v1.2.3 From 98d4db263ebcd32af128ed69acd713113ac16e9b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:24 +0200 Subject: ARM: orion5x: switch to use the clock driver for DT platforms This commit moves the Orion5x platforms using the Device Tree to use the recently introduced clock driver for Orion5x. To achieve that, it: * Adds the necessary DT description of the clock. * Selects ORION_CLK to enable the compilation of the clock driver. * Call of_clk_init() instead of the Orion5x-specific clock initialization function. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-21-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 6 ++++++ arch/arm/mach-orion5x/Kconfig | 1 + arch/arm/mach-orion5x/board-dt.c | 5 ++--- 3 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi index ddfb4d17ff4c..a56f9c88efd0 100644 --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi @@ -15,6 +15,12 @@ compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; internal-regs { + core_clk: core-clocks@10030 { + compatible = "marvell,mv88f5182-core-clock"; + reg = <0x10010 0x4>; + #clock-cells = <1>; + }; + mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; reg = <0x20000 0x100>, <0x1500 0x20>; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 14f2cae4109c..4f5113279352 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -5,6 +5,7 @@ menu "Orion Implementations" config ARCH_ORION5X_DT bool "Marvell Orion5x Flattened Device Tree" select USE_OF + select ORION_CLK help Say 'Y' here if you want your kernel to support the Marvell Orion5x using flattened device tree. diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 7f00897f0dd2..34286ef16320 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ static void orion5x_dt_init_early(void) static void orion5x_dt_init_time(void) { orion5x_timer_init(); + of_clk_init(NULL); } static void __init orion5x_dt_init(void) @@ -60,9 +62,6 @@ static void __init orion5x_dt_init(void) */ orion5x_setup_wins(); - /* Setup root of clk tree */ - clk_init(); - /* * Don't issue "Wait for Interrupt" instruction if we are * running on D0 5281 silicon. -- cgit v1.2.3 From 0180ed45da5198e0e7362c56b3a107d3278666f6 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:25 +0200 Subject: ARM: orion5x: convert to use 'clocks' property for UART controllers Until the previous commit, the Orion5x clocks were not described in the Device Tree. Now that they are described in the Device Tree, we can replace the manual 'clock-frequency' property in the UART nodes by a nicer 'clocks' reference in those UART nodes. This commit consequently removes the 'clock-frequency' property from the LaCie edmini_v2 board, which is at this point the only Orion5x board converted to the Device Tree. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-22-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 1 - arch/arm/boot/dts/orion5x.dtsi | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 83f45a722055..ba43197d0873 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -73,6 +73,5 @@ }; &uart0 { - clock-frequency = <166666667>; status = "okay"; }; diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index ad23ff40e0d1..88df8a811ad3 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -65,7 +65,7 @@ reg = <0x12000 0x100>; reg-shift = <2>; interrupts = <3>; - /* set clock-frequency in board dts */ + clocks = <&core_clk 0>; status = "disabled"; }; @@ -74,7 +74,7 @@ reg = <0x12100 0x100>; reg-shift = <2>; interrupts = <4>; - /* set clock-frequency in board dts */ + clocks = <&core_clk 0>; status = "disabled"; }; -- cgit v1.2.3 From deac3d874ea1e1ef50604cec33ddfb01edb0c976 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:26 +0200 Subject: ARM: orion: switch to a per-platform handle_irq() function Moving to the Device Tree implies having CONFIG_MULTI_IRQ_HANDLER enabled, even for non-DT platforms (if we want both DT and non-DT platforms to be supported in a single kernel). However, the common CONFIG_MULTI_IRQ_HANDLER handler for non-DT platforms in plat-orion/irq.c doesn't match the needs of Orion5x. Also, it doesn't make much sense for orion_irq_init() to register the multi-IRQ handler: orion_irq_init() is called once for each IRQ cause/mask tuple, while the multi-IRQ handler only needs to be registered once. To solve this problem, we move the multi-IRQ handle in per-platform code: mach-kirkwood/irq.c and mach-dove/irq.c. The Orion5x variant will be introduced in a followup commit. Of course, this code will ultimately be completely removed once all boards are converted to the Device Tree. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-23-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-dove/irq.c | 36 +++++++++++++++++++++++++++++++++++ arch/arm/mach-kirkwood/irq.c | 37 ++++++++++++++++++++++++++++++++++++ arch/arm/plat-orion/irq.c | 45 -------------------------------------------- 3 files changed, 73 insertions(+), 45 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index bc4344aa1009..4a5a7aedcb76 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -108,6 +108,38 @@ static int __initdata gpio2_irqs[4] = { 0, }; +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + */ + +static void __iomem *dove_irq_base = IRQ_VIRT_BASE; + +static asmlinkage void +__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} +#endif + void __init dove_init_irq(void) { int i; @@ -115,6 +147,10 @@ void __init dove_init_irq(void) orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(dove_legacy_handle_irq); +#endif + /* * Initialize gpiolib for GPIOs 0-71. */ diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index 2a97a2e4163c..2c47a8ad0e27 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c @@ -7,6 +7,7 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ +#include #include #include #include @@ -30,11 +31,47 @@ static int __initdata gpio1_irqs[4] = { 0, }; +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + */ + +static void __iomem *kirkwood_irq_base = IRQ_VIRT_BASE; + +asmlinkage void +__exception_irq_entry kirkwood_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} +#endif + void __init kirkwood_init_irq(void) { orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(kirkwood_legacy_handle_irq); +#endif + /* * Initialize gpiolib for GPIOs 0-49. */ diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 807df142444b..27ec18b53595 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -20,47 +20,6 @@ #include #include -#ifdef CONFIG_MULTI_IRQ_HANDLER -/* - * Compiling with both non-DT and DT support enabled, will - * break asm irq handler used by non-DT boards. Therefore, - * we provide a C-style irq handler even for non-DT boards, - * if MULTI_IRQ_HANDLER is set. - * - * Notes: - * - this is prepared for Kirkwood and Dove only, update - * accordingly if you add Orion5x or MV78x00. - * - Orion5x uses different macro names and has only one - * set of CAUSE/MASK registers. - * - MV78x00 uses the same macro names but has a third - * set of CAUSE/MASK registers. - * - */ - -static void __iomem *orion_irq_base = IRQ_VIRT_BASE; - -asmlinkage void -__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs) -{ - u32 stat; - - stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF); - stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF); - if (stat) { - unsigned int hwirq = __fls(stat); - handle_IRQ(hwirq, regs); - return; - } - stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF); - stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF); - if (stat) { - unsigned int hwirq = 32 + __fls(stat); - handle_IRQ(hwirq, regs); - return; - } -} -#endif - void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { struct irq_chip_generic *gc; @@ -78,10 +37,6 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) ct->chip.irq_unmask = irq_gc_mask_set_bit; irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); - -#ifdef CONFIG_MULTI_IRQ_HANDLER - set_handle_irq(orion_legacy_handle_irq); -#endif } #ifdef CONFIG_OF -- cgit v1.2.3 From ab5ab9dbe6bd480d17f23b3a33510ae33e6ab280 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:27 +0200 Subject: ARM: orion5x: switch to DT interrupts and timer This commit switches the Orion5x platforms described through DT to use a DT-defined interrupt controller and timer. This involves: * Describing in the DT the bridge interrupt controller, which is a child interrupt controller to the main one, which is used for timer and watchdog interrupts. * Describing in the DT the timer. * Adding in the DT the interrupt specifications for the watchdog. * Selecting the ORION_IRQCHIP and ORION_TIMER drivers to be compiled. * Change board-dt.c to no longer have an ->init_time() callback, since the default callback will work fine: it calls clocksource_of_init() and of_clk_init(), as needed. * Implement a multi-IRQ handler for non-DT platforms in mach-orion5x/irq.c. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-24-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 19 +++++++++++++++++++ arch/arm/mach-orion5x/Kconfig | 2 ++ arch/arm/mach-orion5x/board-dt.c | 15 +-------------- arch/arm/mach-orion5x/irq.c | 28 ++++++++++++++++++++++++++++ 4 files changed, 50 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 88df8a811ad3..b4c2234fda1e 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -78,6 +78,15 @@ status = "disabled"; }; + bridge_intc: bridge-interrupt-ctrl@20110 { + compatible = "marvell,orion-bridge-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20110 0x8>; + interrupts = <0>; + marvell,#interrupts = <4>; + }; + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; @@ -85,9 +94,19 @@ reg = <0x20200 0x08>; }; + timer: timer@20300 { + compatible = "marvell,orion-timer"; + reg = <0x20300 0x20>; + interrupt-parent = <&bridge_intc>; + interrupts = <1>, <2>; + clocks = <&core_clk 0>; + }; + wdt: wdt@20300 { compatible = "marvell,orion-wdt"; reg = <0x20300 0x28>; + interrupt-parent = <&bridge_intc>; + interrupts = <3>; status = "okay"; }; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 4f5113279352..bd65872f5e04 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -6,6 +6,8 @@ config ARCH_ORION5X_DT bool "Marvell Orion5x Flattened Device Tree" select USE_OF select ORION_CLK + select ORION_IRQCHIP + select ORION_TIMER help Say 'Y' here if you want your kernel to support the Marvell Orion5x using flattened device tree. diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 34286ef16320..6dc4846519ec 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -36,17 +37,6 @@ static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { {}, }; -static void orion5x_dt_init_early(void) -{ - orion_time_set_base(TIMER_VIRT_BASE); -} - -static void orion5x_dt_init_time(void) -{ - orion5x_timer_init(); - of_clk_init(NULL); -} - static void __init orion5x_dt_init(void) { char *dev_name; @@ -86,9 +76,6 @@ static const char *orion5x_dt_compat[] = { DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)") /* Maintainer: Thomas Petazzoni */ .map_io = orion5x_map_io, - .init_early = orion5x_dt_init_early, - .init_irq = orion_dt_init_irq, - .init_time = orion5x_dt_init_time, .init_machine = orion5x_dt_init, .restart = orion5x_restart, .dt_compat = orion5x_dt_compat, diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 9654b0cc5892..cd4bac4d7e43 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "common.h" static int __initdata gpio0_irqs[4] = { @@ -25,10 +26,37 @@ static int __initdata gpio0_irqs[4] = { IRQ_ORION5X_GPIO_24_31, }; +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + */ + +asmlinkage void +__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(MAIN_IRQ_CAUSE); + stat &= readl_relaxed(MAIN_IRQ_MASK); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} +#endif + void __init orion5x_init_irq(void) { orion_irq_init(0, MAIN_IRQ_MASK); +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(orion5x_legacy_handle_irq); +#endif + /* * Initialize gpiolib for GPIOs 0-31. */ -- cgit v1.2.3 From 4e7bb110d73f1100d95c23c5a33c79fa17031dff Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:28 +0200 Subject: ARM: orion5x: enable pinctrl driver at SoC level This commit declares the pinctrl device in the Orion5x 5182 Device Tree files, and ensures that the Orion pinctrl driver is compiled. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-25-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 5 +++++ arch/arm/mach-orion5x/Kconfig | 2 ++ 2 files changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi index a56f9c88efd0..8c71b6b9ec29 100644 --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi @@ -15,6 +15,11 @@ compatible = "marvell,orion5x-88f5182-mbus", "simple-bus"; internal-regs { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f5182-pinctrl"; + reg = <0x10000 0x8>, <0x10050 0x4>; + }; + core_clk: core-clocks@10030 { compatible = "marvell,mv88f5182-core-clock"; reg = <0x10010 0x4>; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index bd65872f5e04..3c69a3c0ab46 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -8,6 +8,8 @@ config ARCH_ORION5X_DT select ORION_CLK select ORION_IRQCHIP select ORION_TIMER + select PINCTRL + select PINCTRL_ORION help Say 'Y' here if you want your kernel to support the Marvell Orion5x using flattened device tree. -- cgit v1.2.3 From 4bae02dd65b475ff7a3097ce028b9e5efbbdf891 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:29 +0200 Subject: ARM: orion5x: update I2C description at SoC level This commit fixes the Orion5x SoC definition to: * Not define a clock-frequency, as it should be described on a per-board basis. * Declare the appropriate clock reference, so that the driver can do correct divisors calculations for the I2C bus. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-26-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index b4c2234fda1e..203edde5cfc4 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -56,7 +56,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <5>; - clock-frequency = <100000>; + clocks = <&core_clk 0>; status = "disabled"; }; -- cgit v1.2.3 From e7e9ac1dcc9568110751408c97a910cd842211d8 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:30 +0200 Subject: ARM: orion5x: add Device Bus description at SoC level This commit adds the necessary SoC-level Device Tree definitions to describe the Device Bus of Orion5x SOCs. The Device Bus is mainly used to connect NOR flashes to the system. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-27-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index 203edde5cfc4..75cd01bd6024 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -24,6 +24,46 @@ #size-cells = <1>; controller = <&mbusc>; + devbus_bootcs: devbus-bootcs { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + devbus_cs0: devbus-cs0 { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + devbus_cs1: devbus-cs1 { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + + devbus_cs2: devbus-cs2 { + compatible = "marvell,orion-devbus"; + reg = ; + ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&core_clk 0>; + status = "disabled"; + }; + internal-regs { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3 From a55f9b61d80d0a373a4b78c2e18158511ebe428a Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:31 +0200 Subject: ARM: orion5x: add standard pinctrl configs for sata0 and sata1 Several platforms will most likely use similar pinctrl configurations for SATA0 and SATA1, so we declare those common configurations in the Orion5x DT file. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-28-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi index 8c71b6b9ec29..d1ed71c60209 100644 --- a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi +++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi @@ -18,6 +18,16 @@ pinctrl: pinctrl@10000 { compatible = "marvell,88f5182-pinctrl"; reg = <0x10000 0x8>, <0x10050 0x4>; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp12", "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp13", "mpp15"; + marvell,function = "sata1"; + }; }; core_clk: core-clocks@10030 { -- cgit v1.2.3 From 43be7e02f634422f105217e82559e3b716b3351d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:32 +0200 Subject: ARM: orion5x: convert edmini_v2 to DT pinctrl This commit converts the already partially DT-converted edmini_v2 platform to use the Device Tree for pinctrl. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-29-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 31 ++++++++++++++++++++++ arch/arm/mach-orion5x/edmini_v2-setup.c | 28 ------------------- 2 files changed, 31 insertions(+), 28 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index ba43197d0873..aa74b00d68e2 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -32,6 +32,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-0 = <&pmx_power_button>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; button@1 { @@ -43,6 +45,8 @@ gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led>; + pinctrl-names = "default"; led@1 { label = "power:blue"; @@ -67,7 +71,34 @@ }; }; +&pinctrl { + pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>; + pinctrl-names = "default"; + + pmx_power_button: pmx-power-button { + marvell,pins = "mpp18"; + marvell,function = "gpio"; + }; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_power_led_ctrl: pmx-power-led-ctrl { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; +}; + &sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; status = "okay"; nr-ports = <2>; }; diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index f66c1b2ee8c1..c50469e978de 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -109,37 +109,9 @@ static struct i2c_board_info __initdata edmini_v2_i2c_rtc = { /***************************************************************************** * General Setup ****************************************************************************/ -static unsigned int edminiv2_mpp_modes[] __initdata = { - MPP0_UNUSED, - MPP1_UNUSED, - MPP2_UNUSED, - MPP3_GPIO, /* RTC interrupt */ - MPP4_UNUSED, - MPP5_UNUSED, - MPP6_UNUSED, - MPP7_UNUSED, - MPP8_UNUSED, - MPP9_UNUSED, - MPP10_UNUSED, - MPP11_UNUSED, - MPP12_SATA_LED, /* SATA 0 presence */ - MPP13_SATA_LED, /* SATA 1 presence */ - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - /* 16: Power LED control (0 = On, 1 = Off) */ - MPP16_GPIO, - /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ - MPP17_GPIO, - /* 18: Power button status (0 = Released, 1 = Pressed) */ - MPP18_GPIO, - MPP19_UNUSED, - 0, -}; void __init edmini_v2_init(void) { - orion5x_mpp_conf(edminiv2_mpp_modes); - /* * Configure peripherals. */ -- cgit v1.2.3 From 39eabec14c05ec67e9afe56711b040728de1d533 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:33 +0200 Subject: ARM: orion5x: use DT to describe I2C devices on edmini_v2 This commit converts the already partially DT-converted edmini_v2 platform to use the Device Tree for I2C bus and devices. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-30-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 14 +++++++++++++ arch/arm/mach-orion5x/edmini_v2-setup.c | 24 ---------------------- 2 files changed, 14 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index aa74b00d68e2..41b2ab567bf5 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -10,6 +10,7 @@ #include #include +#include #include "orion5x-mv88f5182.dtsi" / { @@ -63,6 +64,19 @@ }; }; +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372a"; + reg = <0x32>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &mdio { status = "okay"; diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index c50469e978de..75648abbee92 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -95,17 +95,6 @@ static struct platform_device edmini_v2_nor_flash = { .resource = &edmini_v2_nor_flash_resource, }; -/***************************************************************************** - * RTC 5C372a on I2C bus - ****************************************************************************/ - -#define EDMINIV2_RTC_GPIO 3 - -static struct i2c_board_info __initdata edmini_v2_i2c_rtc = { - I2C_BOARD_INFO("rs5c372a", 0x32), - .irq = 0, -}; - /***************************************************************************** * General Setup ****************************************************************************/ @@ -125,17 +114,4 @@ void __init edmini_v2_init(void) pr_notice("edmini_v2: USB device port, flash write and power-off " "are not yet supported.\n"); - - /* Get RTC IRQ and register the chip */ - if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) { - if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0) - edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO); - else - gpio_free(EDMINIV2_RTC_GPIO); - } - - if (edmini_v2_i2c_rtc.irq == 0) - pr_warning("edmini_v2: failed to get RTC IRQ\n"); - - i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1); } -- cgit v1.2.3 From a665fce3e7fe1c7d1a77e99293257f2d008b1488 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:34 +0200 Subject: ARM: orion5x: use DT to describe EHCI on edmini_v2 This commit converts the already partially DT-converted edmini_v2 platform to use the Device Tree for USB. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-31-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 4 ++++ arch/arm/mach-orion5x/edmini_v2-setup.c | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 41b2ab567bf5..f0f2bcc68150 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -56,6 +56,10 @@ }; }; +&ehci0 { + status = "okay"; +}; + ð { status = "okay"; diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index 75648abbee92..2eebc0c345d8 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -104,8 +104,6 @@ void __init edmini_v2_init(void) /* * Configure peripherals. */ - orion5x_ehci0_init(); - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, ORION_MBUS_DEVBUS_BOOT_ATTR, EDMINI_V2_NOR_BOOT_BASE, -- cgit v1.2.3 From a54cd73b842b615f1e98bb2aa1b963e17d0ca127 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:35 +0200 Subject: ARM: orion5x: use DT to describe NOR on edmini_v2 This commit converts the already partially DT-converted edmini_v2 platform to use the Device Tree for NOR flash, using the Device Bus. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-32-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- .../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 43 ++++++++++++++- arch/arm/mach-orion5x/edmini_v2-setup.c | 62 ---------------------- 2 files changed, 42 insertions(+), 63 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index f0f2bcc68150..1ecddbe655e1 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -28,7 +28,8 @@ soc { ranges = , - ; + , + ; }; gpio-keys { @@ -56,6 +57,46 @@ }; }; +&devbus_bootcs { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full512Kb"; + reg = <0 0x80000>; + read-only; + }; + }; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c index 2eebc0c345d8..6bef2d50e16d 100644 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ b/arch/arm/mach-orion5x/edmini_v2-setup.c @@ -42,74 +42,12 @@ * EDMINI_V2 Info ****************************************************************************/ -/* - * 512KB NOR flash Device bus boot chip select - */ - -#define EDMINI_V2_NOR_BOOT_BASE 0xfff80000 -#define EDMINI_V2_NOR_BOOT_SIZE SZ_512K - -/***************************************************************************** - * 512KB NOR Flash on BOOT Device - ****************************************************************************/ - -/* - * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom - * -type device. This could cause risks of accidentally erasing critical - * flash sectors. We thus define a single, write-protected partition covering - * the whole flash. - * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD - * code, break this into at least three partitions: 'u-boot code', 'u-boot - * environment' and 'whatever is left'. - */ - -static struct mtd_partition edmini_v2_partitions[] = { - { - .name = "Full512kb", - .size = 0x00080000, - .offset = 0x00000000, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct physmap_flash_data edmini_v2_nor_flash_data = { - .width = 1, - .parts = edmini_v2_partitions, - .nr_parts = ARRAY_SIZE(edmini_v2_partitions), -}; - -static struct resource edmini_v2_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = EDMINI_V2_NOR_BOOT_BASE, - .end = EDMINI_V2_NOR_BOOT_BASE - + EDMINI_V2_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device edmini_v2_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &edmini_v2_nor_flash_data, - }, - .num_resources = 1, - .resource = &edmini_v2_nor_flash_resource, -}; - /***************************************************************************** * General Setup ****************************************************************************/ void __init edmini_v2_init(void) { - /* - * Configure peripherals. - */ - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - EDMINI_V2_NOR_BOOT_BASE, - EDMINI_V2_NOR_BOOT_SIZE); - platform_device_register(&edmini_v2_nor_flash); - pr_notice("edmini_v2: USB device port, flash write and power-off " "are not yet supported.\n"); } -- cgit v1.2.3 From 9c4d82e5c2aad09becd1b370c9ead7bc087ce406 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:36 +0200 Subject: ARM: orion5x: keep TODO list in edmini_v2 DT In preparation to the complete removal of non-DT support for edmini_v2, this commit copies the TODO list of things to support from the old-style board file into the Device Tree of edmini_v2. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-33-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts index 1ecddbe655e1..89ff404a528c 100644 --- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -6,6 +6,13 @@ * warranty of any kind, whether express or implied. */ +/* + * TODO: add Orion USB device port init when kernel.org support is added. + * TODO: add flash write support: see below. + * TODO: add power-off support. + * TODO: add I2C EEPROM support. + */ + /dts-v1/; #include -- cgit v1.2.3 From aeba6964788d0d8ac0a32113ffecdfdb0db7c786 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:37 +0200 Subject: ARM: orion5x: remove unneeded code for edmini_v2 The edmini_v2 platform is now fully converted to the Device Tree, so we can get rid of the old style board-file and the related Kconfig option. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1398202002-28530-34-git-send-email-thomas.petazzoni@free-electrons.com Acked-by: Sebastian Hesselbarth Signed-off-by: Jason Cooper --- arch/arm/mach-orion5x/Kconfig | 8 ----- arch/arm/mach-orion5x/Makefile | 1 - arch/arm/mach-orion5x/board-dt.c | 3 -- arch/arm/mach-orion5x/common.h | 7 ----- arch/arm/mach-orion5x/edmini_v2-setup.c | 53 --------------------------------- 5 files changed, 72 deletions(-) delete mode 100644 arch/arm/mach-orion5x/edmini_v2-setup.c (limited to 'arch') diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 3c69a3c0ab46..928f4cbdb7f3 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -107,14 +107,6 @@ config MACH_MV2120 Say 'Y' here if you want your kernel to support the HP Media Vault mv2120 or mv5100. -config MACH_EDMINI_V2_DT - bool "LaCie Ethernet Disk mini V2 (Flattened Device Tree)" - select I2C_BOARDINFO - select ARCH_ORION5X_DT - help - Say 'Y' here if you want your kernel to support the - LaCie Ethernet Disk mini V2 (Flattened Device Tree). - config MACH_D2NET bool "LaCie d2 Network" select I2C_BOARDINFO diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 45da805fb236..e8fdbdd02e95 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -23,4 +23,3 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o -obj-$(CONFIG_MACH_EDMINI_V2_DT) += edmini_v2-setup.o diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 6dc4846519ec..78d2e528f982 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -61,9 +61,6 @@ static void __init orion5x_dt_init(void) cpu_idle_poll_ctrl(true); } - if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2")) - edmini_v2_init(); - of_platform_populate(NULL, of_default_bus_match_table, orion5x_auxdata_lookup, NULL); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index f565f9944af2..7d64a17a3943 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -64,13 +64,6 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -/* board init functions for boards not fully converted to fdt */ -#ifdef CONFIG_MACH_EDMINI_V2_DT -void edmini_v2_init(void); -#else -static inline void edmini_v2_init(void) {}; -#endif - struct meminfo; struct tag; extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *); diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c deleted file mode 100644 index 6bef2d50e16d..000000000000 --- a/arch/arm/mach-orion5x/edmini_v2-setup.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-orion5x/edmini_v2-setup.c - * - * LaCie Ethernet Disk mini V2 Setup - * - * Copyright (C) 2008 Christopher Moore - * Copyright (C) 2008 Albert Aribaud - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* - * TODO: add Orion USB device port init when kernel.org support is added. - * TODO: add flash write support: see below. - * TODO: add power-off support. - * TODO: add I2C EEPROM support. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -/***************************************************************************** - * EDMINI_V2 Info - ****************************************************************************/ - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -void __init edmini_v2_init(void) -{ - pr_notice("edmini_v2: USB device port, flash write and power-off " - "are not yet supported.\n"); -} -- cgit v1.2.3 From 065194a06b4187f9c1f4a37951904534291fb85b Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:38 +0200 Subject: ARM: orion5x: convert RD-88F5182 to Device Tree This commit converts the RD-88F5182 platform to the Device Tree. All devices except the PCI are converted to the Device Tree. It is worth noting that: * The PCI description for the DT case is kept in board-rd88f5182.c. * The existing non-DT support in rd88f5182-setup.c is kept as is, in order to allow testing of a given platform in both DT and non-DT cases. It will ultimately be removed, once we no longer care about non-DT support for Orion5x. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-35-git-send-email-thomas.petazzoni@free-electrons.com Cc: Ronen Shitrit Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 177 ++++++++++++++++++++++++++++ arch/arm/mach-orion5x/Kconfig | 8 ++ arch/arm/mach-orion5x/Makefile | 1 + arch/arm/mach-orion5x/board-rd88f5182.c | 116 ++++++++++++++++++ 5 files changed, 304 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/orion5x-rd88f5182-nas.dts create mode 100644 arch/arm/mach-orion5x/board-rd88f5182.c (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..f7943a8d3764 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am43x-epos-evm.dtb \ am437x-gp-evm.dtb \ dra7-evm.dtb -dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb +dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts new file mode 100644 index 000000000000..6fb052507b36 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Marvell Reference Design 88F5182 NAS"; + compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = , + , + , + ; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_debug_led>; + pinctrl-names = "default"; + + led@0 { + label = "rd88f5182:cpu"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + }; +}; + +&devbus_cs1 { + status = "okay"; + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <90000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <186000>; + devbus,acc-next-ps = <186000>; + + /* Write parameters */ + devbus,wr-high-ps = <90000>; + devbus,wr-low-ps = <90000>; + devbus,ale-wr-ps = <90000>; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x1000000>; + bank-width = <1>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@68 { + pinctrl-0 = <&pmx_rtc>; + pinctrl-names = "default"; + compatible = "dallas,ds1338"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios + &pmx_pci_gpios>; + pinctrl-names = "default"; + + /* + * MPP[20] PCI Clock to MV88F5182 + * MPP[21] PCI Clock to mini PCI CON11 + * MPP[22] USB 0 over current indication + * MPP[23] USB 1 over current indication + * MPP[24] USB 1 over current enable + * MPP[25] USB 0 over current enable + */ + + pmx_debug_led: pmx-debug_led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_switch: pmx-reset-switch { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_misc_gpios: pmx-misc-gpios { + marvell,pins = "mpp4", "mpp5"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp6", "mpp7"; + marvell,function = "gpio"; + }; +}; + +&sata { + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 928f4cbdb7f3..11b0c7ea44a2 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -28,6 +28,14 @@ config MACH_RD88F5182 Say 'Y' here if you want your kernel to support the Marvell Orion-NAS (88F5182) RD2 +config MACH_RD88F5182_DT + bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)" + select ARCH_ORION5X_DT + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the Marvell + Orion-NAS (88F5182) RD2, Flattened Device Tree. + config MACH_KUROBOX_PRO bool "KuroBox Pro" select I2C_BOARDINFO diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index e8fdbdd02e95..f40589466805 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o +obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c new file mode 100644 index 000000000000..270824b0e50f --- /dev/null +++ b/arch/arm/mach-orion5x/board-rd88f5182.c @@ -0,0 +1,116 @@ +/* + * arch/arm/mach-orion5x/rd88f5182-setup.c + * + * Marvell Orion-NAS Reference Design Setup + * + * Maintainer: Ronen Shitrit + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * RD-88F5182 Info + ****************************************************************************/ + +/* + * PCI + */ + +#define RD88F5182_PCI_SLOT0_OFFS 7 +#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 +#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 + +/***************************************************************************** + * PCI + ****************************************************************************/ + +static void __init rd88f5182_pci_preinit(void) +{ + int pin; + + /* + * Configure PCI GPIO IRQ pins + */ + pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; + if (gpio_request(pin, "PCI IntA") == 0) { + if (gpio_direction_input(pin) == 0) { + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); + } + + pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; + if (gpio_request(pin, "PCI IntB") == 0) { + if (gpio_direction_input(pin) == 0) { + irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to " + "set_irq_type pin %d\n", pin); + gpio_free(pin); + } + } else { + printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); + } +} + +static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, + u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + /* + * PCI IRQs are connected via GPIOs + */ + switch (slot - RD88F5182_PCI_SLOT0_OFFS) { + case 0: + if (pin == 1) + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); + else + return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); + default: + return -1; + } +} + +static struct hw_pci rd88f5182_pci __initdata = { + .nr_controllers = 2, + .preinit = rd88f5182_pci_preinit, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = rd88f5182_pci_map_irq, +}; + +static int __init rd88f5182_pci_init(void) +{ + if (of_machine_is_compatible("marvell,rd-88f5182-nas")) + pci_common_init(&rd88f5182_pci); + + return 0; +} + +subsys_initcall(rd88f5182_pci_init); -- cgit v1.2.3 From 94b0bd366e36379c994bdaa84f18355702212eb4 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:39 +0200 Subject: ARM: orion5x: convert d2net to Device Tree This commit converts the LaCie d2 Network platform to the Device Tree. All devices except LEDs are converted, because the LED code needs a non-LED GPIO to be set to a given value for the LEDs to work, and this cannot yet be easily represented in DT. Also, references to the LaCie Big Disk Network platform are lost, because this platform apparently has exactly the same hardware support as the LaCie d2 Network, so their Device Tree files would be identical. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-36-git-send-email-thomas.petazzoni@free-electrons.com Cc: Simon Guinot Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 236 ++++++++++++++++ arch/arm/mach-orion5x/Kconfig | 13 +- arch/arm/mach-orion5x/Makefile | 3 +- arch/arm/mach-orion5x/board-d2net.c | 109 ++++++++ arch/arm/mach-orion5x/d2net-setup.c | 365 ------------------------- 6 files changed, 351 insertions(+), 378 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-lacie-d2-network.dts create mode 100644 arch/arm/mach-orion5x/board-d2net.c delete mode 100644 arch/arm/mach-orion5x/d2net-setup.c (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f7943a8d3764..59397c267382 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -289,7 +289,8 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ am43x-epos-evm.dtb \ am437x-gp-evm.dtb \ dra7-evm.dtb -dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb \ +dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ + orion5x-lacie-ethernet-disk-mini-v2.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts new file mode 100644 index 000000000000..c701e8d16bbb --- /dev/null +++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni + * Copyright (C) 2009 Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include +#include +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "LaCie d2 Network"; + compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + front_button { + label = "Front Push Button"; + linux,code = ; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + }; + + power_rocker_sw_on { + label = "Power rocker switch (on|auto)"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + }; + + power_rocker_sw_off { + label = "Power rocker switch (auto|off)"; + linux,input-type = <5>; /* EV_SW */ + linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>; + pinctrl-names = "default"; + + sata0_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "SATA0 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x80000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Full512Kb"; + reg = <0 0x80000>; + read-only; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@32 { + compatible = "ricoh,rs5c372b"; + reg = <0x32>; + }; + + fan@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + + /* Not enough HW info */ + status = "disabled"; + }; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>; + pinctrl-names = "default"; + + pmx_board_id: pmx-board-id { + marvell,pins = "mpp0", "mpp1", "mpp2"; + marvell,function = "gpio"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp8", "mpp9", "mpp18"; + marvell,function = "gpio"; + }; + + pmx_fan_fail: pmx-fan-fail { + marvell,pins = "mpp5"; + marvell,function = "gpio"; + }; + + /* + * MPP6: Red front LED + * MPP16: Blue front LED blink control + */ + pmx_leds: pmx-leds { + marvell,pins = "mpp6", "mpp16"; + marvell,function = "gpio"; + }; + + pmx_sata0_led_active: pmx-sata0-led-active { + marvell,pins = "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata0_power: pmx-sata0-power { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_sata1_led_active: pmx-sata1-led-active { + marvell,pins = "mpp15"; + marvell,function = "sata1"; + }; + + pmx_sata1_power: pmx-sata1-power { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + /* + * Non MPP GPIOs: + * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) + * GPIO 23: Blue front LED off + * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) + */ +}; + +&sata { + pinctrl-0 = <&pmx_sata0_led_active + &pmx_sata1_led_active>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 11b0c7ea44a2..3c4ad83c782a 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -115,20 +115,13 @@ config MACH_MV2120 Say 'Y' here if you want your kernel to support the HP Media Vault mv2120 or mv5100. -config MACH_D2NET - bool "LaCie d2 Network" - select I2C_BOARDINFO +config MACH_D2NET_DT + bool "LaCie d2 Network / Big Disk Network (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the LaCie d2 Network NAS. -config MACH_BIGDISK - bool "LaCie Big Disk Network" - select I2C_BOARDINFO - help - Say 'Y' here if you want your kernel to support the - LaCie Big Disk Network NAS. - config MACH_NET2BIG bool "LaCie 2Big Network" select I2C_BOARDINFO diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index f40589466805..787dcee96806 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -12,8 +12,6 @@ obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o -obj-$(CONFIG_MACH_D2NET) += d2net-setup.o -obj-$(CONFIG_MACH_BIGDISK) += d2net-setup.o obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o obj-$(CONFIG_MACH_MSS2) += mss2-setup.o obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o @@ -23,4 +21,5 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o +obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c new file mode 100644 index 000000000000..8a7284124153 --- /dev/null +++ b/arch/arm/mach-orion5x/board-d2net.c @@ -0,0 +1,109 @@ +/* + * arch/arm/mach-orion5x/board-d2net.c + * + * LaCie d2Network and Big Disk Network NAS setup + * + * Copyright (C) 2009 Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * LaCie d2 Network Info + ****************************************************************************/ + +/***************************************************************************** + * GPIO LED's + ****************************************************************************/ + +/* + * The blue front LED is wired to the CPLD and can blink in relation with the + * SATA activity. + * + * The following array detail the different LED registers and the combination + * of their possible values: + * + * led_off | blink_ctrl | SATA active | LED state + * | | | + * 1 | x | x | off + * 0 | 0 | 0 | off + * 0 | 1 | 0 | blink (rate 300ms) + * 0 | x | 1 | on + * + * Notes: The blue and the red front LED's can't be on at the same time. + * Red LED have priority. + */ + +#define D2NET_GPIO_RED_LED 6 +#define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16 +#define D2NET_GPIO_BLUE_LED_OFF 23 + +static struct gpio_led d2net_leds[] = { + { + .name = "d2net:blue:sata", + .default_trigger = "default-on", + .gpio = D2NET_GPIO_BLUE_LED_OFF, + .active_low = 1, + }, + { + .name = "d2net:red:fail", + .gpio = D2NET_GPIO_RED_LED, + }, +}; + +static struct gpio_led_platform_data d2net_led_data = { + .num_leds = ARRAY_SIZE(d2net_leds), + .leds = d2net_leds, +}; + +static struct platform_device d2net_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &d2net_led_data, + }, +}; + +static void __init d2net_gpio_leds_init(void) +{ + int err; + + /* Configure register blink_ctrl to allow SATA activity LED blinking. */ + err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink"); + if (err == 0) { + err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1); + if (err) + gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL); + } + if (err) + pr_err("d2net: failed to configure blue LED blink GPIO\n"); + + platform_device_register(&d2net_gpio_leds); +} + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +void __init d2net_init(void) +{ + d2net_gpio_leds_init(); + + pr_notice("d2net: Flash write are not yet supported.\n"); +} diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c deleted file mode 100644 index 8f68b745c1d5..000000000000 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * arch/arm/mach-orion5x/d2net-setup.c - * - * LaCie d2Network and Big Disk Network NAS setup - * - * Copyright (C) 2009 Simon Guinot - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -/***************************************************************************** - * LaCie d2 Network Info - ****************************************************************************/ - -/* - * 512KB NOR flash Device bus boot chip select - */ - -#define D2NET_NOR_BOOT_BASE 0xfff80000 -#define D2NET_NOR_BOOT_SIZE SZ_512K - -/***************************************************************************** - * 512KB NOR Flash on Boot Device - ****************************************************************************/ - -/* - * TODO: Check write support on flash MX29LV400CBTC-70G - */ - -static struct mtd_partition d2net_partitions[] = { - { - .name = "Full512kb", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct physmap_flash_data d2net_nor_flash_data = { - .width = 1, - .parts = d2net_partitions, - .nr_parts = ARRAY_SIZE(d2net_partitions), -}; - -static struct resource d2net_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = D2NET_NOR_BOOT_BASE, - .end = D2NET_NOR_BOOT_BASE - + D2NET_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device d2net_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &d2net_nor_flash_data, - }, - .num_resources = 1, - .resource = &d2net_nor_flash_resource, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data d2net_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -/* - * i2c addr | chip | description - * 0x32 | Ricoh 5C372b | RTC - * 0x3e | GMT G762 | PWM fan controller - * 0x50 | HT24LC08 | eeprom (1kB) - * - * TODO: Add G762 support to the g760a driver. - */ -static struct i2c_board_info __initdata d2net_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372b", 0x32), - }, { - I2C_BOARD_INFO("24c08", 0x50), - }, -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data d2net_sata_data = { - .n_ports = 2, -}; - -#define D2NET_GPIO_SATA0_POWER 3 -#define D2NET_GPIO_SATA1_POWER 12 - -static void __init d2net_sata_power_init(void) -{ - int err; - - err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power"); - if (err == 0) { - err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1); - if (err) - gpio_free(D2NET_GPIO_SATA0_POWER); - } - if (err) - pr_err("d2net: failed to configure SATA0 power GPIO\n"); - - err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power"); - if (err == 0) { - err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1); - if (err) - gpio_free(D2NET_GPIO_SATA1_POWER); - } - if (err) - pr_err("d2net: failed to configure SATA1 power GPIO\n"); -} - -/***************************************************************************** - * GPIO LED's - ****************************************************************************/ - -/* - * The blue front LED is wired to the CPLD and can blink in relation with the - * SATA activity. - * - * The following array detail the different LED registers and the combination - * of their possible values: - * - * led_off | blink_ctrl | SATA active | LED state - * | | | - * 1 | x | x | off - * 0 | 0 | 0 | off - * 0 | 1 | 0 | blink (rate 300ms) - * 0 | x | 1 | on - * - * Notes: The blue and the red front LED's can't be on at the same time. - * Red LED have priority. - */ - -#define D2NET_GPIO_RED_LED 6 -#define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16 -#define D2NET_GPIO_BLUE_LED_OFF 23 - -static struct gpio_led d2net_leds[] = { - { - .name = "d2net:blue:sata", - .default_trigger = "default-on", - .gpio = D2NET_GPIO_BLUE_LED_OFF, - .active_low = 1, - }, - { - .name = "d2net:red:fail", - .gpio = D2NET_GPIO_RED_LED, - }, -}; - -static struct gpio_led_platform_data d2net_led_data = { - .num_leds = ARRAY_SIZE(d2net_leds), - .leds = d2net_leds, -}; - -static struct platform_device d2net_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &d2net_led_data, - }, -}; - -static void __init d2net_gpio_leds_init(void) -{ - int err; - - /* Configure GPIO over MPP max number. */ - orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1); - - /* Configure register blink_ctrl to allow SATA activity LED blinking. */ - err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink"); - if (err == 0) { - err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1); - if (err) - gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL); - } - if (err) - pr_err("d2net: failed to configure blue LED blink GPIO\n"); - - platform_device_register(&d2net_gpio_leds); -} - -/**************************************************************************** - * GPIO keys - ****************************************************************************/ - -#define D2NET_GPIO_PUSH_BUTTON 18 -#define D2NET_GPIO_POWER_SWITCH_ON 8 -#define D2NET_GPIO_POWER_SWITCH_OFF 9 - -#define D2NET_SWITCH_POWER_ON 0x1 -#define D2NET_SWITCH_POWER_OFF 0x2 - -static struct gpio_keys_button d2net_buttons[] = { - { - .type = EV_SW, - .code = D2NET_SWITCH_POWER_OFF, - .gpio = D2NET_GPIO_POWER_SWITCH_OFF, - .desc = "Power rocker switch (auto|off)", - .active_low = 0, - }, - { - .type = EV_SW, - .code = D2NET_SWITCH_POWER_ON, - .gpio = D2NET_GPIO_POWER_SWITCH_ON, - .desc = "Power rocker switch (on|auto)", - .active_low = 0, - }, - { - .type = EV_KEY, - .code = KEY_POWER, - .gpio = D2NET_GPIO_PUSH_BUTTON, - .desc = "Front Push Button", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data d2net_button_data = { - .buttons = d2net_buttons, - .nbuttons = ARRAY_SIZE(d2net_buttons), -}; - -static struct platform_device d2net_gpio_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &d2net_button_data, - }, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static unsigned int d2net_mpp_modes[] __initdata = { - MPP0_GPIO, /* Board ID (bit 0) */ - MPP1_GPIO, /* Board ID (bit 1) */ - MPP2_GPIO, /* Board ID (bit 2) */ - MPP3_GPIO, /* SATA 0 power */ - MPP4_UNUSED, - MPP5_GPIO, /* Fan fail detection */ - MPP6_GPIO, /* Red front LED */ - MPP7_UNUSED, - MPP8_GPIO, /* Rear power switch (on|auto) */ - MPP9_GPIO, /* Rear power switch (auto|off) */ - MPP10_UNUSED, - MPP11_UNUSED, - MPP12_GPIO, /* SATA 1 power */ - MPP13_UNUSED, - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - MPP16_GPIO, /* Blue front LED blink control */ - MPP17_UNUSED, - MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */ - MPP19_UNUSED, - 0, - /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ - /* 23: Blue front LED off */ - /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ -}; - -#define D2NET_GPIO_INHIBIT_POWER_OFF 24 - -static void __init d2net_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(d2net_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&d2net_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - - d2net_sata_power_init(); - orion5x_sata_init(&d2net_sata_data); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - D2NET_NOR_BOOT_BASE, - D2NET_NOR_BOOT_SIZE); - platform_device_register(&d2net_nor_flash); - - platform_device_register(&d2net_gpio_buttons); - - d2net_gpio_leds_init(); - - pr_notice("d2net: Flash write are not yet supported.\n"); - - i2c_register_board_info(0, d2net_i2c_devices, - ARRAY_SIZE(d2net_i2c_devices)); - - orion_gpio_set_valid(D2NET_GPIO_INHIBIT_POWER_OFF, 1); -} - -/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ - -#ifdef CONFIG_MACH_D2NET -MACHINE_START(D2NET, "LaCie d2 Network") - .atag_offset = 0x100, - .init_machine = d2net_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_BIGDISK -MACHINE_START(BIGDISK, "LaCie Big Disk Network") - .atag_offset = 0x100, - .init_machine = d2net_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -#endif - -- cgit v1.2.3 From fbf04d814d0a57b0eead41efd70b3fbe903201d9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:40 +0200 Subject: ARM: orion5x: convert Maxtor Shared Storage II to the Device Tree This commit converts the Maxtor Shared Storage II Orion5x platform to the Device Tree. The only remaining things not converted are PCI and the special power off method. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-37-git-send-email-thomas.petazzoni@free-electrons.com Cc: Sylver Bruneau Signed-off-by: Jason Cooper --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/orion5x-maxtor-shared-storage-2.dts | 178 +++++++++++++ arch/arm/mach-orion5x/Kconfig | 5 +- arch/arm/mach-orion5x/Makefile | 2 +- arch/arm/mach-orion5x/board-dt.c | 3 + arch/arm/mach-orion5x/board-mss2.c | 90 +++++++ arch/arm/mach-orion5x/common.h | 6 + arch/arm/mach-orion5x/mss2-setup.c | 274 --------------------- 8 files changed, 282 insertions(+), 277 deletions(-) create mode 100644 arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts create mode 100644 arch/arm/mach-orion5x/board-mss2.c delete mode 100644 arch/arm/mach-orion5x/mss2-setup.c (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59397c267382..629eee22e606 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -291,6 +291,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ + orion5x-maxtor-shared-storage-2.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts new file mode 100644 index 000000000000..ff3484904294 --- /dev/null +++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2014 Thomas Petazzoni + * Copyright (C) Sylver Bruneau + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include +#include +#include +#include "orion5x-mv88f5182.dtsi" + +/ { + model = "Maxtor Shared Storage II"; + compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x"; + + memory { + reg = <0x00000000 0x4000000>; /* 64 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + linux,stdout-path = &uart0; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + power { + label = "Power"; + linux,code = ; + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + /* + * Currently the MTD code does not recognize the MX29LV400CBCT + * as a bottom-type device. This could cause risks of + * accidentally erasing critical flash sectors. We thus define + * a single, write-protected partition covering the whole + * flash. TODO: once the flash part TOP/BOTTOM detection + * issue is sorted out in the MTD code, break this into at + * least three partitions: 'u-boot code', 'u-boot environment' + * and 'whatever is left'. + */ + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x40000>; + bank-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&mdio { + status = "okay"; + + ethphy: ethernet-phy { + reg = <8>; + }; +}; + +&ehci0 { + status = "okay"; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; + +&i2c { + status = "okay"; + clock-frequency = <100000>; + #address-cells = <1>; + + rtc@68 { + compatible = "st,m41t81"; + reg = <0x68>; + pinctrl-0 = <&pmx_rtc>; + pinctrl-names = "default"; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_leds &pmx_misc>; + pinctrl-names = "default"; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp11", "mpp12"; + marvell,function = "gpio"; + }; + + /* + * MPP0: Power LED + * MPP1: Error LED + */ + pmx_leds: pmx-leds { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "gpio"; + }; + + /* + * MPP4: HDD ind. (Single/Dual) + * MPP5: HD0 5V control + * MPP6: HD0 12V control + * MPP7: HD1 5V control + * MPP8: HD1 12V control + */ + pmx_misc: pmx-misc { + marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10"; + marvell,function = "gpio"; + }; + + pmx_rtc: pmx-rtc { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_sata0_led_active: pmx-sata0-led-active { + marvell,pins = "mpp14"; + marvell,function = "sata0"; + }; + + pmx_sata1_led_active: pmx-sata1-led-active { + marvell,pins = "mpp15"; + marvell,function = "sata1"; + }; + + /* + * Non MPP GPIOs: + * GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok) + * GPIO 23: Blue front LED off + * GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled) + */ +}; + +&sata { + pinctrl-0 = <&pmx_sata0_led_active + &pmx_sata1_led_active>; + pinctrl-names = "default"; + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 3c4ad83c782a..2412efb6cdd9 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -129,8 +129,9 @@ config MACH_NET2BIG Say 'Y' here if you want your kernel to support the LaCie 2Big Network NAS. -config MACH_MSS2 - bool "Maxtor Shared Storage II" +config MACH_MSS2_DT + bool "Maxtor Shared Storage II (Flattened Device Tree)" + select ARCH_ORION5X_DT help Say 'Y' here if you want your kernel to support the Maxtor Shared Storage II platform. diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 787dcee96806..a40b5c9a58c4 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o -obj-$(CONFIG_MACH_MSS2) += mss2-setup.o obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o @@ -22,4 +21,5 @@ obj-$(CONFIG_MACH_LINKSTATION_LSCHL) += ls-chl-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o +obj-$(CONFIG_MACH_MSS2_DT) += board-mss2.o obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 78d2e528f982..35d418faf8f1 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -61,6 +61,9 @@ static void __init orion5x_dt_init(void) cpu_idle_poll_ctrl(true); } + if (of_machine_is_compatible("maxtor,shared-storage-2")) + mss2_init(); + of_platform_populate(NULL, of_default_bus_match_table, orion5x_auxdata_lookup, NULL); } diff --git a/arch/arm/mach-orion5x/board-mss2.c b/arch/arm/mach-orion5x/board-mss2.c new file mode 100644 index 000000000000..66f9c3ba86cc --- /dev/null +++ b/arch/arm/mach-orion5x/board-mss2.c @@ -0,0 +1,90 @@ +/* + * Maxtor Shared Storage II Board Setup + * + * Maintainer: Sylver Bruneau + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * Maxtor Shared Storage II Info + ****************************************************************************/ + +/**************************************************************************** + * PCI setup + ****************************************************************************/ +static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + /* + * Check for devices with hard-wired IRQs. + */ + irq = orion5x_pci_map_irq(dev, slot, pin); + if (irq != -1) + return irq; + + return -1; +} + +static struct hw_pci mss2_pci __initdata = { + .nr_controllers = 2, + .setup = orion5x_pci_sys_setup, + .scan = orion5x_pci_sys_scan_bus, + .map_irq = mss2_pci_map_irq, +}; + +static int __init mss2_pci_init(void) +{ + if (machine_is_mss2()) + pci_common_init(&mss2_pci); + + return 0; +} +subsys_initcall(mss2_pci_init); + +/***************************************************************************** + * MSS2 power off method + ****************************************************************************/ +/* + * On the Maxtor Shared Storage II, the shutdown process is the following : + * - Userland modifies U-boot env to tell U-boot to go idle at next boot + * - The board reboots + * - U-boot starts and go into an idle mode until the user press "power" + */ +static void mss2_power_off(void) +{ + u32 reg; + + /* + * Enable and issue soft reset + */ + reg = readl(RSTOUTn_MASK); + reg |= 1 << 2; + writel(reg, RSTOUTn_MASK); + + reg = readl(CPU_SOFT_RESET); + reg |= 1; + writel(reg, CPU_SOFT_RESET); +} + +void __init mss2_init(void) +{ + /* register mss2 specific power-off method */ + pm_power_off = mss2_power_off; +} diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index 7d64a17a3943..db7e056493a0 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -68,6 +68,12 @@ struct meminfo; struct tag; extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *); +#ifdef CONFIG_MACH_MSS2_DT +extern void mss2_init(void); +#else +static inline void mss2_init(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c deleted file mode 100644 index e105130ba51c..000000000000 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Maxtor Shared Storage II Board Setup - * - * Maintainer: Sylver Bruneau - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -#define MSS2_NOR_BOOT_BASE 0xff800000 -#define MSS2_NOR_BOOT_SIZE SZ_256K - -/***************************************************************************** - * Maxtor Shared Storage II Info - ****************************************************************************/ - -/* - * Maxtor Shared Storage II hardware : - * - Marvell 88F5182-A2 C500 - * - Marvell 88E1111 Gigabit Ethernet PHY - * - RTC M41T81 (@0x68) on I2C bus - * - 256KB NOR flash - * - 64MB of RAM - */ - -/***************************************************************************** - * 256KB NOR Flash on BOOT Device - ****************************************************************************/ - -static struct physmap_flash_data mss2_nor_flash_data = { - .width = 1, -}; - -static struct resource mss2_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = MSS2_NOR_BOOT_BASE, - .end = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device mss2_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mss2_nor_flash_data, - }, - .resource = &mss2_nor_flash_resource, - .num_resources = 1, -}; - -/**************************************************************************** - * PCI setup - ****************************************************************************/ -static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - return -1; -} - -static struct hw_pci mss2_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = mss2_pci_map_irq, -}; - -static int __init mss2_pci_init(void) -{ - if (machine_is_mss2()) - pci_common_init(&mss2_pci); - - return 0; -} -subsys_initcall(mss2_pci_init); - - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data mss2_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data mss2_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * GPIO buttons - ****************************************************************************/ - -#define MSS2_GPIO_KEY_RESET 12 -#define MSS2_GPIO_KEY_POWER 11 - -static struct gpio_keys_button mss2_buttons[] = { - { - .code = KEY_POWER, - .gpio = MSS2_GPIO_KEY_POWER, - .desc = "Power", - .active_low = 1, - }, { - .code = KEY_RESTART, - .gpio = MSS2_GPIO_KEY_RESET, - .desc = "Reset", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data mss2_button_data = { - .buttons = mss2_buttons, - .nbuttons = ARRAY_SIZE(mss2_buttons), -}; - -static struct platform_device mss2_button_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &mss2_button_data, - }, -}; - -/***************************************************************************** - * RTC m41t81 on I2C bus - ****************************************************************************/ - -#define MSS2_GPIO_RTC_IRQ 3 - -static struct i2c_board_info __initdata mss2_i2c_rtc = { - I2C_BOARD_INFO("m41t81", 0x68), -}; - -/***************************************************************************** - * MSS2 power off method - ****************************************************************************/ -/* - * On the Maxtor Shared Storage II, the shutdown process is the following : - * - Userland modifies U-boot env to tell U-boot to go idle at next boot - * - The board reboots - * - U-boot starts and go into an idle mode until the user press "power" - */ -static void mss2_power_off(void) -{ - u32 reg; - - /* - * Enable and issue soft reset - */ - reg = readl(RSTOUTn_MASK); - reg |= 1 << 2; - writel(reg, RSTOUTn_MASK); - - reg = readl(CPU_SOFT_RESET); - reg |= 1; - writel(reg, CPU_SOFT_RESET); -} - -/**************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int mss2_mpp_modes[] __initdata = { - MPP0_GPIO, /* Power LED */ - MPP1_GPIO, /* Error LED */ - MPP2_UNUSED, - MPP3_GPIO, /* RTC interrupt */ - MPP4_GPIO, /* HDD ind. (Single/Dual)*/ - MPP5_GPIO, /* HD0 5V control */ - MPP6_GPIO, /* HD0 12V control */ - MPP7_GPIO, /* HD1 5V control */ - MPP8_GPIO, /* HD1 12V control */ - MPP9_UNUSED, - MPP10_GPIO, /* Fan control */ - MPP11_GPIO, /* Power button */ - MPP12_GPIO, /* Reset button */ - MPP13_UNUSED, - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static void __init mss2_init(void) -{ - /* Setup basic Orion functions. Need to be called early. */ - orion5x_init(); - - orion5x_mpp_conf(mss2_mpp_modes); - - /* - * MPP[20] Unused - * MPP[21] PCI clock - * MPP[22] USB 0 over current - * MPP[23] USB 1 over current - */ - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&mss2_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&mss2_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - MSS2_NOR_BOOT_BASE, - MSS2_NOR_BOOT_SIZE); - platform_device_register(&mss2_nor_flash); - - platform_device_register(&mss2_button_device); - - if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) { - if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0) - mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ); - else - gpio_free(MSS2_GPIO_RTC_IRQ); - } - i2c_register_board_info(0, &mss2_i2c_rtc, 1); - - /* register mss2 specific power-off method */ - pm_power_off = mss2_power_off; -} - -MACHINE_START(MSS2, "Maxtor Shared Storage II") - /* Maintainer: Sylver Bruneau */ - .atag_offset = 0x100, - .init_machine = mss2_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END -- cgit v1.2.3 From 880ff3e2255c05bac0d2010719da42a26fdbb185 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:41 +0200 Subject: ARM: orion: remove no longer needed DT IRQ code Following the move of the Orion5x Device Tree support to use irqchip_init() for the interrupt controller probing, the plat-orion/irq.c code for DT-probing of the interrupt controller is no longer necessary, so we can get rid of it. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-38-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/plat-orion/include/plat/irq.h | 1 - arch/arm/plat-orion/irq.c | 32 -------------------------------- 2 files changed, 33 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/include/plat/irq.h b/arch/arm/plat-orion/include/plat/irq.h index 50547e417936..96be19e9bd93 100644 --- a/arch/arm/plat-orion/include/plat/irq.h +++ b/arch/arm/plat-orion/include/plat/irq.h @@ -12,5 +12,4 @@ #define __PLAT_IRQ_H void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr); -void __init orion_dt_init_irq(void); #endif diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 27ec18b53595..8c1fc06007c0 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -38,35 +38,3 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); } - -#ifdef CONFIG_OF -static int __init orion_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - int i = 0; - void __iomem *base; - - do { - base = of_iomap(np, i); - if (base) { - orion_irq_init(i * 32, base + 0x04); - i++; - } - } while (base); - - irq_domain_add_legacy(np, i * 32, 0, 0, - &irq_domain_simple_ops, NULL); - return 0; -} - -static const struct of_device_id orion_irq_match[] = { - { .compatible = "marvell,orion-intc", - .data = orion_add_irq_domain, }, - {}, -}; - -void __init orion_dt_init_irq(void) -{ - of_irq_init(orion_irq_match); -} -#endif -- cgit v1.2.3 From 19e00f20e90e349cdeef3d7b63e6179215c9ff9d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 22 Apr 2014 23:26:42 +0200 Subject: ARM: orion: remove no longer needed gpio DT code Following the move to pure DT-based probing of the GPIO controllers on Orion5x, some code in plat-orion/orion-gpio.c can be removed as it is no longer used. Signed-off-by: Thomas Petazzoni Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1398202002-28530-39-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/plat-orion/gpio.c | 48 --------------------------- arch/arm/plat-orion/include/plat/orion-gpio.h | 1 - 2 files changed, 49 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 6816192a7561..b61a3bcc2fa8 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -597,51 +597,3 @@ void __init orion_gpio_init(struct device_node *np, orion_gpio_chip_count++; } - -#ifdef CONFIG_OF -static void __init orion_gpio_of_init_one(struct device_node *np, - int irq_gpio_base) -{ - int ngpio, gpio_base, mask_offset; - void __iomem *base; - int ret, i; - int irqs[4]; - int secondary_irq_base; - - ret = of_property_read_u32(np, "ngpio", &ngpio); - if (ret) - goto out; - ret = of_property_read_u32(np, "mask-offset", &mask_offset); - if (ret == -EINVAL) - mask_offset = 0; - else - goto out; - base = of_iomap(np, 0); - if (!base) - goto out; - - secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count); - gpio_base = 32 * orion_gpio_chip_count; - - /* Get the interrupt numbers. Each chip can have up to 4 - * interrupt handlers, with each handler dealing with 8 GPIO - * pins. */ - - for (i = 0; i < 4; i++) - irqs[i] = irq_of_parse_and_map(np, i); - - orion_gpio_init(np, gpio_base, ngpio, base, mask_offset, - secondary_irq_base, irqs); - return; -out: - pr_err("%s: %s: missing mandatory property\n", __func__, np->name); -} - -void __init orion_gpio_of_init(int irq_gpio_base) -{ - struct device_node *np; - - for_each_compatible_node(np, NULL, "marvell,orion-gpio") - orion_gpio_of_init_one(np, irq_gpio_base); -} -#endif diff --git a/arch/arm/plat-orion/include/plat/orion-gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h index 614dcac9dc52..e763988b04b9 100644 --- a/arch/arm/plat-orion/include/plat/orion-gpio.h +++ b/arch/arm/plat-orion/include/plat/orion-gpio.h @@ -33,5 +33,4 @@ void __init orion_gpio_init(struct device_node *np, int secondary_irq_base, int irq[4]); -void __init orion_gpio_of_init(int irq_gpio_base); #endif -- cgit v1.2.3 From 5a62ec57004f1a434bfd3feed43e447b5780baf6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 26 Apr 2014 02:51:27 +0400 Subject: ARM: shmobile: henninger: enable SATA0 Enable SATA0 device for the Henninger board. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index f82f306c074d..6e67cea3104c 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -74,3 +74,7 @@ micrel,led-mode = <1>; }; }; + +&sata0 { + status = "okay"; +}; -- cgit v1.2.3 From f8e3e4d15c0d06d61a1866b389f1af34aa0e777d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 11 Apr 2014 16:59:37 +0200 Subject: ARM: dts: zynq: drop address cells from GIC node This is likely a copy-and-paste error from the ARM GIC documentation, that has already been fixed. address-cells should have been set to 0, as with the size cells. As having those properties set to 0 is the same thing as not specifying them, drop them completely. Signed-off-by: Lucas Stach Acked-by: Rob Herring Signed-off-by: Michal Simek --- arch/arm/boot/dts/zynq-7000.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index c1176abc34d9..34dff3856e99 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -80,7 +80,6 @@ intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; - #address-cells = <1>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; -- cgit v1.2.3 From 387468d190f0ba72e239c11e9663cfeaeaf9ae2d Mon Sep 17 00:00:00 2001 From: Tim Kryger Date: Fri, 25 Apr 2014 11:31:15 -0700 Subject: ARM: bcm_defconfig: Enable PWM and Backlight Enable PWM drivers and the PWM-based backlight driver. Signed-off-by: Tim Kryger Reviewed-by: Alex Elder Reviewed-by: Markus Mayer Signed-off-by: Matt Porter --- arch/arm/configs/bcm_defconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig index 3df3f3a79ef4..9d13dae99125 100644 --- a/arch/arm/configs/bcm_defconfig +++ b/arch/arm/configs/bcm_defconfig @@ -91,6 +91,7 @@ CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y @@ -104,6 +105,8 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_PWM=y +CONFIG_PWM_BCM_KONA=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -- cgit v1.2.3 From cc33e42d3f7dd5341d032db7d452c52ae39d65ec Mon Sep 17 00:00:00 2001 From: Tim Kryger Date: Fri, 25 Apr 2014 11:31:13 -0700 Subject: ARM: dts: Declare the PWM for bcm11351 (bcm281xx) Add the device tree node for the PWM on bcm11351 SoCs. Signed-off-by: Tim Kryger Reviewed-by: Alex Elder Reviewed-by: Markus Mayer Signed-off-by: Matt Porter --- arch/arm/boot/dts/bcm11351.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 64d069bcc409..6b05ae6d476f 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -193,6 +193,14 @@ status = "disabled"; }; + pwm: pwm@3e01a000 { + compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; + reg = <0x3e01a000 0xcc>; + clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 8411ca1f7d636338b184c74f4c09ec00a454e5f9 Mon Sep 17 00:00:00 2001 From: Tim Kryger Date: Fri, 25 Apr 2014 11:31:14 -0700 Subject: ARM: dts: Enable the PWM for bcm28155 AP board Mark the PWM as enabled on the bcm28155 AP board. Signed-off-by: Tim Kryger Reviewed-by: Alex Elder Reviewed-by: Markus Mayer Signed-off-by: Matt Porter --- arch/arm/boot/dts/bcm28155-ap.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index af3da55eef49..9ce91dd60cb6 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -69,6 +69,10 @@ status = "okay"; }; + pwm: pwm@3e01a000 { + status = "okay"; + }; + usbotg: usb@3f120000 { vusb_d-supply = <&usbldo_reg>; vusb_a-supply = <&iosr1_reg>; -- cgit v1.2.3 From 9dd604dfb8ac78621e975a7b9ec66c37f24544ab Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:45 +0200 Subject: ARM: tegra: Add Tegra124 HDMI support Add a device node for the HDMI controller found on Tegra124. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index cf45a1a39483..197e8481a659 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -51,6 +51,18 @@ nvidia,head = <1>; }; + hdmi@0,54280000 { + compatible = "nvidia,tegra124-hdmi"; + reg = <0x0 0x54280000 0x0 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; + clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; + status = "disabled"; + }; + sor@0,54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; -- cgit v1.2.3 From 329c39f877323564ba9abee30decac1421636052 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:46 +0200 Subject: ARM: tegra: venice2 - Enable HDMI Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller. Enable the HDMI device, provide the power supplies as well as the DDC adapter and use the standard pin (PN7) for hotplug detection. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 37 ++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 6770e2bdf226..84a6ec039e1d 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -17,6 +17,18 @@ }; host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + sor@0,54540000 { status = "okay"; @@ -601,7 +613,7 @@ clock-frequency = <100000>; }; - i2c@0,7000c700 { + hdmi_ddc: i2c@0,7000c700 { status = "okay"; clock-frequency = <100000>; }; @@ -700,7 +712,7 @@ regulator-boot-on; }; - sd4 { + vdd_1v05_run: sd4 { regulator-name = "+1.05V_RUN"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -1147,6 +1159,27 @@ enable-active-high; vin-supply = <&vdd_3v3_sys>; }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; }; sound { -- cgit v1.2.3 From 6054dd39de8abf9dba36cc27d53b64f6fd31c524 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:47 +0200 Subject: ARM: tegra: jetson-tk1 - Enable HDMI support Add HDMI +5V, VDD and PLL regulators and enable the DDC I2C controller. Enable the HDMI device, provide the power supplies as well as the DDC adapter and use pin the standard pin (PN7) for hotplug detection. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 39 +++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index dd3076d94727..e30a5778f675 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -16,6 +16,20 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + vdd-supply = <&vdd_3v3_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + pinmux: pinmux@0,70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1382,7 +1396,7 @@ }; /* HDMI DDC */ - i2c@0,7000c700 { + hdmi_ddc: i2c@0,7000c700 { status = "okay"; clock-frequency = <100000>; }; @@ -1477,7 +1491,7 @@ regulator-boot-on; }; - sd4 { + vdd_1v05_run: sd4 { regulator-name = "+1.05V_RUN"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -1765,6 +1779,27 @@ enable-active-high; vin-supply = <&vdd_3v3_sys>; }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; }; sound { -- cgit v1.2.3 From ad0acf782d0ecedfbae2ae8f5f6c25bb3b6e97b6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:48 +0200 Subject: ARM: tegra: harmony - Add +5V HDMI supply This supply controls the +5V pin on the HDMI connector, which in turn is used by attached sinks to return the hotplug detect signal. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-harmony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 3fb1f50f6d46..f45aad688d9b 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -28,6 +28,7 @@ hdmi@54280000 { status = "okay"; + hdmi-supply = <&vdd_5v0_hdmi>; vdd-supply = <&hdmi_vdd_reg>; pll-supply = <&hdmi_pll_reg>; @@ -724,6 +725,17 @@ gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + vdd_5v0_hdmi: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; }; sound { -- cgit v1.2.3 From 597eb8e187c4902d21536fed3edd98bf24696d1d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:49 +0200 Subject: ARM: tegra: beaver - Add +5V HDMI supply This supply controls the +5V pin on the HDMI connector, which in turn is used by attached sinks to return the hotplug detect signal. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-beaver.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index e93fe45b7803..3189791a9289 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -40,6 +40,7 @@ hdmi@54280000 { status = "okay"; + hdmi-supply = <&vdd_5v0_hdmi>; vdd-supply = <&sys_3v3_reg>; pll-supply = <&vio_reg>; @@ -478,6 +479,17 @@ gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>; vin-supply = <&sys_3v3_reg>; }; + + vdd_5v0_hdmi: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+VDD_5V_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&sys_3v3_reg>; + }; }; sound { -- cgit v1.2.3 From 4adb123d335ecfc0da304585b3b5a4582f9db5dd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:50 +0200 Subject: ARM: tegra: dalmore - Add +5V HDMI supply This supply controls the +5V pin on the HDMI connector, which in turn is used by attached sinks to return the hotplug detect signal. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a288a12823ed..a95a75145a96 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -25,6 +25,7 @@ hdmi@54280000 { status = "okay"; + hdmi-supply = <&vdd_5v0_hdmi>; vdd-supply = <&vdd_hdmi_reg>; pll-supply = <&palmas_smps3_reg>; @@ -1231,8 +1232,6 @@ regulator-name = "vdd_hdmi_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; vin-supply = <&tps65090_dcdc1_reg>; }; @@ -1245,6 +1244,17 @@ enable-active-high; gpio = <&palmas_gpio 6 0>; }; + + vdd_5v0_hdmi: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "VDD_5V0_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&tps65090_dcdc1_reg>; + }; }; sound { -- cgit v1.2.3 From 87ab35330c899f5ef3e11fe7d0fc463634f808cb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 25 Apr 2014 17:44:51 +0200 Subject: ARM: tegra: dalmore - Add DSI power supply The 1.2V supply for CSI and DSI was previously marked always-on. This is suboptimal because it prevents the supply from being disabled when there is no activity in the display or capture paths that it powers. Hook up the regulator to the DSI output and mark it as not always-on, so that it will only be enabled when DSI actually needs it. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index a95a75145a96..35a2ee71a970 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -37,6 +37,8 @@ dsi@54300000 { status = "okay"; + avdd-dsi-csi-supply = <&avdd_1v2_reg>; + panel@0 { compatible = "panasonic,vvx10f004b00", "simple-panel"; @@ -983,12 +985,10 @@ regulator-max-microvolt = <2800000>; }; - ldo3 { + avdd_1v2_reg: ldo3 { regulator-name = "avdd-dsi-csi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; }; ldo4 { -- cgit v1.2.3 From 98de744e901f41c1662dd9054b51af811b23c8fd Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 25 Apr 2014 10:12:42 -0600 Subject: ARM: tegra: use correct audio CODEC on Jetson TK1 Jetson TK1 contains an RT5639 not an RT5640. While the two are extremely similar and mostly compatible, we should still use the correct device name in the device tree. I had meant to fix this before applying the initial DT, but this issue slipped my mind. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index e30a5778f675..fbc34933cf69 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1360,8 +1360,8 @@ status = "okay"; clock-frequency = <100000>; - rt5640: audio-codec@1c { - compatible = "realtek,rt5640"; + rt5639: audio-codec@1c { + compatible = "realtek,rt5639"; reg = <0x1c>; interrupt-parent = <&gpio>; interrupts = ; @@ -1814,7 +1814,7 @@ "IN2P", "Mic Jack"; nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&rt5640>; + nvidia,audio-codec = <&rt5639>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From e29ea4d3b2a4c3ae77cffe0658e70cd58de5dc46 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 21:54:41 +0200 Subject: ARM: sun7i: Add ARM PMU in A20 DTSI Enable the performance monitoring unit found in the A20 SoCs. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun7i-a20.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 88171f419e35..fe626ec579f2 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -57,6 +57,12 @@ <1 10 0xf08>; }; + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From b5a10b769962072eecf638fda94906fe656036d3 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 17 Apr 2014 21:54:41 +0200 Subject: ARM: sun6i: Add ARM PMU in A31 DTSI Enable the performance monitoring unit found in the A31 SoCs. Signed-off-by: Maxime Ripard Reviewed-by: Hans de Goede --- arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b28a55fdf3ce..22f63e01166e 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -59,6 +59,14 @@ reg = <0x40000000 0x80000000>; }; + pmu { + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; + interrupts = <0 120 4>, + <0 121 4>, + <0 122 4>, + <0 123 4>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From c630829a98bb5bfef38bab2cafcff2206765ffdc Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Thu, 24 Apr 2014 17:23:24 -0300 Subject: ARM: mvebu: Enable the thermal sensor in Armada 380/385 SoC This commit enables the thermal sensor found in Armada 380/385 SoCs. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1398371004-15807-11-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/armada-38x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 0796cde504e7..cd60738e912e 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -391,6 +391,12 @@ clock-output-names = "nand"; }; + thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4074 0x4>; + status = "okay"; + }; + flash@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; -- cgit v1.2.3 From 1d5726e9df9c377e65c6c01ee663bea813043c53 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:10 +0200 Subject: ARM: sun4i: dt: add pinmux configuration for the PWM Add the pinctrl descriptions for both PWM channels of the Allwinner A10. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index fe845ebc27be..8810ce459c0f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -477,6 +477,20 @@ #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; -- cgit v1.2.3 From fd7898a2b06a270d97fef0d5dc7bb46be0c3c971 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:12 +0200 Subject: ARM: sun7i: dt: add pinmux configuration for the PWM Add the pinctrl descriptions for both PWM channels of the Allwinner A20. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index fe626ec579f2..3ac8926bde27 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -546,6 +546,20 @@ #size-cells = <0>; #gpio-cells = <3>; + pwm0_pins_a: pwm0@0 { + allwinner,pins = "PB2"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + pwm1_pins_a: pwm1@0 { + allwinner,pins = "PI3"; + allwinner,function = "pwm"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PB22", "PB23"; allwinner,function = "uart0"; -- cgit v1.2.3 From 4b57a3959cd2b9f7dab949504651cca33c1c35f3 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:11 +0200 Subject: ARM: sun4i: dt: add PWM support Add the PWM bindings for the Allwinner A10. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 8810ce459c0f..4dc376170dd0 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -563,6 +563,14 @@ interrupts = <24>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun4i-a10-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; -- cgit v1.2.3 From 8ec40c25139d45e9df385b60b50e5cd36c732464 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:13 +0200 Subject: ARM: sun7i: dt: add PWM support Add the PWM bindings for the Allwinner A20. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 3ac8926bde27..ea62839a5e2f 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -698,6 +698,14 @@ interrupts = <0 24 4>; }; + pwm: pwm@01c20e00 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c20e00 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; -- cgit v1.2.3 From 96ac3b343d40957b253bbbf8fc81efbdbed9f25d Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Mon, 28 Apr 2014 18:17:14 +0200 Subject: ARM: sunxi: dt: add PWM support for the cubietruck Enable the PWM for both PWM channels on the cubietruck. They can be found on connector CN8. Signed-off-by: Alexandre Belloni Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index cb25d3c8da58..0c3bd127a5fd 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -63,6 +63,12 @@ }; }; + pwm: pwm@01c20e00 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; -- cgit v1.2.3 From 6da50f13a7153c4d55ee8e3ab9d5f7248ff8e3fc Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 26 Apr 2014 12:16:12 +0200 Subject: ARM: dts: sun5i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 7 +++++++ 2 files changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 79989ed5658d..9493b2129886 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -451,6 +451,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; + allwinner,function = "mmc1"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index d0836d43c28d..dda9df69e033 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -415,6 +415,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.2.3 From 9797eb83c85d553dbc062b2953597fb1086649e9 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 26 Apr 2014 12:16:16 +0200 Subject: ARM: dts: sun6i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 22f63e01166e..30138cd935d4 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -295,6 +295,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { -- cgit v1.2.3 From 9a558ee3ccb8afcf43c8d9d4d206ab6de4aa30a2 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Mon, 3 Feb 2014 10:42:30 +0100 Subject: KVM: s390: Handle MVPG partial execution interception When the guest executes the MVPG instruction with DAT disabled, and the source or destination page is not mapped in the host, the so-called partial execution interception occurs. We need to handle this event by setting up a mapping for the corresponding user pages. Signed-off-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/intercept.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index 30e1c5eb726a..54313fe6e8d4 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -1,7 +1,7 @@ /* * in-kernel handling for sie intercepts * - * Copyright IBM Corp. 2008, 2009 + * Copyright IBM Corp. 2008, 2014 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License (version 2 only) @@ -234,6 +234,58 @@ static int handle_instruction_and_prog(struct kvm_vcpu *vcpu) return rc2; } +/** + * Handle MOVE PAGE partial execution interception. + * + * This interception can only happen for guests with DAT disabled and + * addresses that are currently not mapped in the host. Thus we try to + * set up the mappings for the corresponding user pages here (or throw + * addressing exceptions in case of illegal guest addresses). + */ +static int handle_mvpg_pei(struct kvm_vcpu *vcpu) +{ + unsigned long hostaddr, srcaddr, dstaddr; + psw_t *psw = &vcpu->arch.sie_block->gpsw; + struct mm_struct *mm = current->mm; + int reg1, reg2, rc; + + kvm_s390_get_regs_rre(vcpu, ®1, ®2); + srcaddr = kvm_s390_real_to_abs(vcpu, vcpu->run->s.regs.gprs[reg2]); + dstaddr = kvm_s390_real_to_abs(vcpu, vcpu->run->s.regs.gprs[reg1]); + + /* Make sure that the source is paged-in */ + hostaddr = gmap_fault(srcaddr, vcpu->arch.gmap); + if (IS_ERR_VALUE(hostaddr)) + return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + down_read(&mm->mmap_sem); + rc = get_user_pages(current, mm, hostaddr, 1, 0, 0, NULL, NULL); + up_read(&mm->mmap_sem); + if (rc < 0) + return rc; + + /* Make sure that the destination is paged-in */ + hostaddr = gmap_fault(dstaddr, vcpu->arch.gmap); + if (IS_ERR_VALUE(hostaddr)) + return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); + down_read(&mm->mmap_sem); + rc = get_user_pages(current, mm, hostaddr, 1, 1, 0, NULL, NULL); + up_read(&mm->mmap_sem); + if (rc < 0) + return rc; + + psw->addr = __rewind_psw(*psw, 4); + + return 0; +} + +static int handle_partial_execution(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.sie_block->ipa == 0xb254) /* MVPG */ + return handle_mvpg_pei(vcpu); + + return -EOPNOTSUPP; +} + static const intercept_handler_t intercept_funcs[] = { [0x00 >> 2] = handle_noop, [0x04 >> 2] = handle_instruction, @@ -245,6 +297,7 @@ static const intercept_handler_t intercept_funcs[] = { [0x1C >> 2] = kvm_s390_handle_wait, [0x20 >> 2] = handle_validity, [0x28 >> 2] = handle_stop, + [0x38 >> 2] = handle_partial_execution, }; int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu) -- cgit v1.2.3 From f8232c8cf720074c0eb0804202d424a2b7b4ee76 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Mon, 3 Mar 2014 23:34:42 +0100 Subject: KVM: s390: Add a function for checking the low-address protection The s390 architecture has a special protection mechanism that can be used to prevent write access to the vital data in the low-core memory area. This patch adds a new helper function that can be used to check for such write accesses and in case of protection, it also sets up the exception data accordingly. Signed-off-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/gaccess.c | 28 ++++++++++++++++++++++++++++ arch/s390/kvm/gaccess.h | 1 + 2 files changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/s390/kvm/gaccess.c b/arch/s390/kvm/gaccess.c index 691fdb776c90..db608c3f9303 100644 --- a/arch/s390/kvm/gaccess.c +++ b/arch/s390/kvm/gaccess.c @@ -643,3 +643,31 @@ int access_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, } return rc; } + +/** + * kvm_s390_check_low_addr_protection - check for low-address protection + * @ga: Guest address + * + * Checks whether an address is subject to low-address protection and set + * up vcpu->arch.pgm accordingly if necessary. + * + * Return: 0 if no protection exception, or PGM_PROTECTION if protected. + */ +int kvm_s390_check_low_addr_protection(struct kvm_vcpu *vcpu, unsigned long ga) +{ + struct kvm_s390_pgm_info *pgm = &vcpu->arch.pgm; + psw_t *psw = &vcpu->arch.sie_block->gpsw; + struct trans_exc_code_bits *tec_bits; + + if (!is_low_address(ga) || !low_address_protection_enabled(vcpu)) + return 0; + + memset(pgm, 0, sizeof(*pgm)); + tec_bits = (struct trans_exc_code_bits *)&pgm->trans_exc_code; + tec_bits->fsi = FSI_STORE; + tec_bits->as = psw_bits(*psw).as; + tec_bits->addr = ga >> PAGE_SHIFT; + pgm->code = PGM_PROTECTION; + + return pgm->code; +} diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h index 1079c8fc6d0d..68db43e4254f 100644 --- a/arch/s390/kvm/gaccess.h +++ b/arch/s390/kvm/gaccess.h @@ -325,5 +325,6 @@ int read_guest_real(struct kvm_vcpu *vcpu, unsigned long gra, void *data, } int ipte_lock_held(struct kvm_vcpu *vcpu); +int kvm_s390_check_low_addr_protection(struct kvm_vcpu *vcpu, unsigned long ga); #endif /* __KVM_S390_GACCESS_H */ -- cgit v1.2.3 From fb34c603655fafdd244227cb6b42d006469735fc Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Mon, 9 Sep 2013 17:58:38 +0200 Subject: KVM: s390: Fixes for PFMF Add a check for low-address protection to the PFMF handler and convert real-addresses to absolute if necessary, as it is defined in the Principles of Operations specification. Signed-off-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index 27f9051a78f8..a47157bca8a6 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -650,6 +650,11 @@ static int handle_pfmf(struct kvm_vcpu *vcpu) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; + if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { + if (kvm_s390_check_low_addr_protection(vcpu, start)) + return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); + } + switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { case 0x00000000: end = (start + (1UL << 12)) & ~((1UL << 12) - 1); @@ -665,10 +670,15 @@ static int handle_pfmf(struct kvm_vcpu *vcpu) return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION); } while (start < end) { - unsigned long useraddr; - - useraddr = gmap_translate(start, vcpu->arch.gmap); - if (IS_ERR((void *)useraddr)) + unsigned long useraddr, abs_addr; + + /* Translate guest address to host address */ + if ((vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) == 0) + abs_addr = kvm_s390_real_to_abs(vcpu, start); + else + abs_addr = start; + useraddr = gfn_to_hva(vcpu->kvm, gpa_to_gfn(abs_addr)); + if (kvm_is_error_hva(useraddr)) return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING); if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { -- cgit v1.2.3 From e45efa28e578758d3c5ef0d7d3f88aadb9a61515 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 7 Mar 2014 12:14:23 +0100 Subject: KVM: s390: Add low-address protection to TEST BLOCK TEST BLOCK is also subject to the low-address protection, so we need to check the destination address in our handler. Signed-off-by: Thomas Huth Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/priv.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c index a47157bca8a6..07d0c1025cb9 100644 --- a/arch/s390/kvm/priv.c +++ b/arch/s390/kvm/priv.c @@ -206,6 +206,9 @@ static int handle_test_block(struct kvm_vcpu *vcpu) kvm_s390_get_regs_rre(vcpu, NULL, ®2); addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; + addr = kvm_s390_logical_to_effective(vcpu, addr); + if (kvm_s390_check_low_addr_protection(vcpu, addr)) + return kvm_s390_inject_prog_irq(vcpu, &vcpu->arch.pgm); addr = kvm_s390_real_to_abs(vcpu, addr); if (kvm_is_error_gpa(vcpu->kvm, addr)) -- cgit v1.2.3 From 6852d7b69b4949234c3a8ae1f279f6a4c6563662 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Fri, 14 Mar 2014 10:59:29 +0100 Subject: KVM: s390: introduce kvm_s390_vcpu_{start,stop} This patch introduces two new functions to set/clear the CPUSTAT_STOPPED bit and makes use of it at all applicable places. These functions prepare the additional execution of code when starting/stopping a vcpu. The CPUSTAT_STOPPED bit should not be touched outside of these functions. Signed-off-by: David Hildenbrand Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/kvm/diag.c | 2 +- arch/s390/kvm/intercept.c | 3 +-- arch/s390/kvm/interrupt.c | 2 +- arch/s390/kvm/kvm-s390.c | 16 ++++++++++++++-- arch/s390/kvm/kvm-s390.h | 2 ++ arch/s390/kvm/trace-s390.h | 21 +++++++++++++++++++++ 6 files changed, 40 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c index 5521ace8b60d..004d385d9519 100644 --- a/arch/s390/kvm/diag.c +++ b/arch/s390/kvm/diag.c @@ -176,7 +176,7 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu) return -EOPNOTSUPP; } - atomic_set_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); + kvm_s390_vcpu_stop(vcpu); vcpu->run->s390_reset_flags |= KVM_S390_RESET_SUBSYSTEM; vcpu->run->s390_reset_flags |= KVM_S390_RESET_IPL; vcpu->run->s390_reset_flags |= KVM_S390_RESET_CPU_INIT; diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index 54313fe6e8d4..99e4b76e3487 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -65,8 +65,7 @@ static int handle_stop(struct kvm_vcpu *vcpu) trace_kvm_s390_stop_request(vcpu->arch.local_int.action_bits); if (vcpu->arch.local_int.action_bits & ACTION_STOP_ON_STOP) { - atomic_set_mask(CPUSTAT_STOPPED, - &vcpu->arch.sie_block->cpuflags); + kvm_s390_vcpu_stop(vcpu); vcpu->arch.local_int.action_bits &= ~ACTION_STOP_ON_STOP; VCPU_EVENT(vcpu, 3, "%s", "cpu stopped"); rc = -EOPNOTSUPP; diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index 077e4738ebdc..d9526bb29194 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -413,7 +413,7 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, rc |= read_guest_lc(vcpu, offsetof(struct _lowcore, restart_psw), &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); - atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); + kvm_s390_vcpu_start(vcpu); break; case KVM_S390_PROGRAM_INT: VCPU_EVENT(vcpu, 4, "interrupt: pgm check code:%x, ilc:%x", diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index b32c42cbc706..6c972d229ace 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -592,7 +592,7 @@ static void kvm_s390_vcpu_initial_reset(struct kvm_vcpu *vcpu) vcpu->arch.sie_block->pp = 0; vcpu->arch.pfault_token = KVM_S390_PFAULT_TOKEN_INVALID; kvm_clear_async_pf_completion_queue(vcpu); - atomic_set_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); + kvm_s390_vcpu_stop(vcpu); kvm_s390_clear_local_irqs(vcpu); } @@ -1235,7 +1235,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) if (vcpu->sigset_active) sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); - atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); + kvm_s390_vcpu_start(vcpu); switch (kvm_run->exit_reason) { case KVM_EXIT_S390_SIEIC: @@ -1362,6 +1362,18 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr) return kvm_s390_store_status_unloaded(vcpu, addr); } +void kvm_s390_vcpu_start(struct kvm_vcpu *vcpu) +{ + trace_kvm_s390_vcpu_start_stop(vcpu->vcpu_id, 1); + atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); +} + +void kvm_s390_vcpu_stop(struct kvm_vcpu *vcpu) +{ + trace_kvm_s390_vcpu_start_stop(vcpu->vcpu_id, 0); + atomic_set_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); +} + static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, struct kvm_enable_cap *cap) { diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h index 9b5680d1f6cc..c28423a3acc0 100644 --- a/arch/s390/kvm/kvm-s390.h +++ b/arch/s390/kvm/kvm-s390.h @@ -157,6 +157,8 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu); /* implemented in kvm-s390.c */ int kvm_s390_store_status_unloaded(struct kvm_vcpu *vcpu, unsigned long addr); int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr); +void kvm_s390_vcpu_start(struct kvm_vcpu *vcpu); +void kvm_s390_vcpu_stop(struct kvm_vcpu *vcpu); void s390_vcpu_block(struct kvm_vcpu *vcpu); void s390_vcpu_unblock(struct kvm_vcpu *vcpu); void exit_sie(struct kvm_vcpu *vcpu); diff --git a/arch/s390/kvm/trace-s390.h b/arch/s390/kvm/trace-s390.h index 13f30f58a2df..34d4f8af3a1d 100644 --- a/arch/s390/kvm/trace-s390.h +++ b/arch/s390/kvm/trace-s390.h @@ -67,6 +67,27 @@ TRACE_EVENT(kvm_s390_destroy_vcpu, TP_printk("destroy cpu %d", __entry->id) ); +/* + * Trace point for start and stop of vpcus. + */ +TRACE_EVENT(kvm_s390_vcpu_start_stop, + TP_PROTO(unsigned int id, int state), + TP_ARGS(id, state), + + TP_STRUCT__entry( + __field(unsigned int, id) + __field(int, state) + ), + + TP_fast_assign( + __entry->id = id; + __entry->state = state; + ), + + TP_printk("%s cpu %d", __entry->state ? "starting" : "stopping", + __entry->id) + ); + /* * Trace points for injection of interrupts, either per machine or * per vcpu. -- cgit v1.2.3 From 8ad357551797b1edc184fb9f6a4f80a6fa626459 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Fri, 14 Mar 2014 11:00:21 +0100 Subject: KVM: s390: enable IBS for single running VCPUs This patch enables the IBS facility when a single VCPU is running. The facility is dynamically turned on/off as soon as other VCPUs enter/leave the stopped state. When this facility is operating, some instructions can be executed faster for single-cpu guests. Signed-off-by: David Hildenbrand Reviewed-by: Dominik Dingel Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 2 + arch/s390/kvm/kvm-s390.c | 123 ++++++++++++++++++++++++++++++++++++++- arch/s390/kvm/trace-s390.h | 22 +++++++ include/linux/kvm_host.h | 2 + 4 files changed, 147 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index 0d45f6fe734f..f0a1dc5e5d1f 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -72,6 +72,7 @@ struct sca_block { #define CPUSTAT_ZARCH 0x00000800 #define CPUSTAT_MCDS 0x00000100 #define CPUSTAT_SM 0x00000080 +#define CPUSTAT_IBS 0x00000040 #define CPUSTAT_G 0x00000008 #define CPUSTAT_GED 0x00000004 #define CPUSTAT_J 0x00000002 @@ -411,6 +412,7 @@ struct kvm_arch{ int use_cmma; struct s390_io_adapter *adapters[MAX_S390_IO_ADAPTERS]; wait_queue_head_t ipte_wq; + spinlock_t start_stop_lock; }; #define KVM_HVA_ERR_BAD (-1UL) diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 6c972d229ace..0a01744cbdd9 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -458,6 +458,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) kvm->arch.css_support = 0; kvm->arch.use_irqchip = 0; + spin_lock_init(&kvm->arch.start_stop_lock); + return 0; out_nogmap: debug_unregister(kvm->arch.dbf); @@ -996,8 +998,15 @@ bool kvm_s390_cmma_enabled(struct kvm *kvm) return true; } +static bool ibs_enabled(struct kvm_vcpu *vcpu) +{ + return atomic_read(&vcpu->arch.sie_block->cpuflags) & CPUSTAT_IBS; +} + static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu) { +retry: + s390_vcpu_unblock(vcpu); /* * We use MMU_RELOAD just to re-arm the ipte notifier for the * guest prefix page. gmap_ipte_notify will wait on the ptl lock. @@ -1005,15 +1014,34 @@ static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu) * already finished. We might race against a second unmapper that * wants to set the blocking bit. Lets just retry the request loop. */ - while (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) { + if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) { int rc; rc = gmap_ipte_notify(vcpu->arch.gmap, vcpu->arch.sie_block->prefix, PAGE_SIZE * 2); if (rc) return rc; - s390_vcpu_unblock(vcpu); + goto retry; + } + + if (kvm_check_request(KVM_REQ_ENABLE_IBS, vcpu)) { + if (!ibs_enabled(vcpu)) { + trace_kvm_s390_enable_disable_ibs(vcpu->vcpu_id, 1); + atomic_set_mask(CPUSTAT_IBS, + &vcpu->arch.sie_block->cpuflags); + } + goto retry; } + + if (kvm_check_request(KVM_REQ_DISABLE_IBS, vcpu)) { + if (ibs_enabled(vcpu)) { + trace_kvm_s390_enable_disable_ibs(vcpu->vcpu_id, 0); + atomic_clear_mask(CPUSTAT_IBS, + &vcpu->arch.sie_block->cpuflags); + } + goto retry; + } + return 0; } @@ -1362,16 +1390,107 @@ int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr) return kvm_s390_store_status_unloaded(vcpu, addr); } +static inline int is_vcpu_stopped(struct kvm_vcpu *vcpu) +{ + return atomic_read(&(vcpu)->arch.sie_block->cpuflags) & CPUSTAT_STOPPED; +} + +static void __disable_ibs_on_vcpu(struct kvm_vcpu *vcpu) +{ + kvm_check_request(KVM_REQ_ENABLE_IBS, vcpu); + kvm_make_request(KVM_REQ_DISABLE_IBS, vcpu); + exit_sie_sync(vcpu); +} + +static void __disable_ibs_on_all_vcpus(struct kvm *kvm) +{ + unsigned int i; + struct kvm_vcpu *vcpu; + + kvm_for_each_vcpu(i, vcpu, kvm) { + __disable_ibs_on_vcpu(vcpu); + } +} + +static void __enable_ibs_on_vcpu(struct kvm_vcpu *vcpu) +{ + kvm_check_request(KVM_REQ_DISABLE_IBS, vcpu); + kvm_make_request(KVM_REQ_ENABLE_IBS, vcpu); + exit_sie_sync(vcpu); +} + void kvm_s390_vcpu_start(struct kvm_vcpu *vcpu) { + int i, online_vcpus, started_vcpus = 0; + + if (!is_vcpu_stopped(vcpu)) + return; + trace_kvm_s390_vcpu_start_stop(vcpu->vcpu_id, 1); + /* Only one cpu at a time may enter/leave the STOPPED state. */ + spin_lock_bh(&vcpu->kvm->arch.start_stop_lock); + online_vcpus = atomic_read(&vcpu->kvm->online_vcpus); + + for (i = 0; i < online_vcpus; i++) { + if (!is_vcpu_stopped(vcpu->kvm->vcpus[i])) + started_vcpus++; + } + + if (started_vcpus == 0) { + /* we're the only active VCPU -> speed it up */ + __enable_ibs_on_vcpu(vcpu); + } else if (started_vcpus == 1) { + /* + * As we are starting a second VCPU, we have to disable + * the IBS facility on all VCPUs to remove potentially + * oustanding ENABLE requests. + */ + __disable_ibs_on_all_vcpus(vcpu->kvm); + } + atomic_clear_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); + /* + * Another VCPU might have used IBS while we were offline. + * Let's play safe and flush the VCPU at startup. + */ + vcpu->arch.sie_block->ihcpu = 0xffff; + spin_unlock_bh(&vcpu->kvm->arch.start_stop_lock); + return; } void kvm_s390_vcpu_stop(struct kvm_vcpu *vcpu) { + int i, online_vcpus, started_vcpus = 0; + struct kvm_vcpu *started_vcpu = NULL; + + if (is_vcpu_stopped(vcpu)) + return; + trace_kvm_s390_vcpu_start_stop(vcpu->vcpu_id, 0); + /* Only one cpu at a time may enter/leave the STOPPED state. */ + spin_lock_bh(&vcpu->kvm->arch.start_stop_lock); + online_vcpus = atomic_read(&vcpu->kvm->online_vcpus); + atomic_set_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags); + __disable_ibs_on_vcpu(vcpu); + + for (i = 0; i < online_vcpus; i++) { + if (!is_vcpu_stopped(vcpu->kvm->vcpus[i])) { + started_vcpus++; + started_vcpu = vcpu->kvm->vcpus[i]; + } + } + + if (started_vcpus == 1) { + /* + * As we only have one VCPU left, we want to enable the + * IBS facility for that VCPU to speed it up. + */ + __enable_ibs_on_vcpu(started_vcpu); + } + + spin_unlock_bh(&vcpu->kvm->arch.start_stop_lock); + return; } static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, diff --git a/arch/s390/kvm/trace-s390.h b/arch/s390/kvm/trace-s390.h index 34d4f8af3a1d..647e9d6a4818 100644 --- a/arch/s390/kvm/trace-s390.h +++ b/arch/s390/kvm/trace-s390.h @@ -244,6 +244,28 @@ TRACE_EVENT(kvm_s390_enable_css, __entry->kvm) ); +/* + * Trace point for enabling and disabling interlocking-and-broadcasting + * suppression. + */ +TRACE_EVENT(kvm_s390_enable_disable_ibs, + TP_PROTO(unsigned int id, int state), + TP_ARGS(id, state), + + TP_STRUCT__entry( + __field(unsigned int, id) + __field(int, state) + ), + + TP_fast_assign( + __entry->id = id; + __entry->state = state; + ), + + TP_printk("%s ibs on cpu %d", + __entry->state ? "enabling" : "disabling", __entry->id) + ); + #endif /* _TRACE_KVMS390_H */ diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 820fc2e1d9df..1e125b055327 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -134,6 +134,8 @@ static inline bool is_error_page(struct page *page) #define KVM_REQ_EPR_EXIT 20 #define KVM_REQ_SCAN_IOAPIC 21 #define KVM_REQ_GLOBAL_CLOCK_UPDATE 22 +#define KVM_REQ_ENABLE_IBS 23 +#define KVM_REQ_DISABLE_IBS 24 #define KVM_USERSPACE_IRQ_SOURCE_ID 0 #define KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID 1 -- cgit v1.2.3 From e4c9a5a17567f8ea975bdcfdd1bf9d63965de6c9 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Sat, 26 Apr 2014 22:30:23 -0300 Subject: KVM: x86: expose invariant tsc cpuid bit (v2) Invariant TSC is a property of TSC, no additional support code necessary. Signed-off-by: Marcelo Tosatti Signed-off-by: Paolo Bonzini --- arch/x86/kvm/cpuid.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index f47a104a749c..333b88db22fe 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -495,6 +495,13 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, entry->ecx &= kvm_supported_word6_x86_features; cpuid_mask(&entry->ecx, 6); break; + case 0x80000007: /* Advanced power management */ + /* invariant TSC is CPUID.80000007H:EDX[8] */ + entry->edx &= (1 << 8); + /* mask against host */ + entry->edx &= boot_cpu_data.x86_power; + entry->eax = entry->ebx = entry->ecx = 0; + break; case 0x80000008: { unsigned g_phys_as = (entry->eax >> 16) & 0xff; unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); @@ -525,7 +532,6 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, case 3: /* Processor serial number */ case 5: /* MONITOR/MWAIT */ case 6: /* Thermal management */ - case 0x80000007: /* Advanced power management */ case 0xC0000002: case 0xC0000003: case 0xC0000004: -- cgit v1.2.3 From 215f21c93e2c5568c0ba44890dd4539d7028a40e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 28 Apr 2014 11:05:57 -0600 Subject: ARM: tegra: add SD wp-gpios to Jetson TK1 DT Jetson TK1 can detect write-protect on the SD card. Add the required DT entries to allow this. Signed-off-by: Stephen Warren Tested-by: Thierry Reding --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index fbc34933cf69..e31fb61a81d3 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1624,6 +1624,7 @@ status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; vqmmc-supply = <&vddio_sdmmc3>; }; -- cgit v1.2.3 From cffb57e62394f6ae3f86b9dc1d9bb59d44a15a20 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 28 Apr 2014 12:50:50 -0600 Subject: ARM: tegra: add SD wp-gpios to Dalmore DT Dalmore can detect write-protect on the SD card. Add the required DT entries to allow this. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114-dalmore.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 35a2ee71a970..5c21d216515a 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1106,6 +1106,7 @@ sdhci@78000400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; bus-width = <4>; status = "okay"; }; -- cgit v1.2.3 From 499f8ad5ab8a3bd79e31d80469e509a5bcd86aa3 Mon Sep 17 00:00:00 2001 From: Stratos Karafotis Date: Fri, 25 Apr 2014 23:15:55 +0300 Subject: ARM: davinci: da850: Use cpufreq_for_each_entry macro for iteration The cpufreq core now supports the cpufreq_for_each_entry macro helper for iteration over the cpufreq_frequency_table, so use it. It should have no functional changes. Signed-off-by: Stratos Karafotis Acked-and-tested-by: Lad, Prabhakar Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki --- arch/arm/mach-davinci/da850.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 85399c98f84a..45ce065e7170 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -1092,20 +1092,21 @@ int da850_register_cpufreq(char *async_clk) static int da850_round_armrate(struct clk *clk, unsigned long rate) { - int i, ret = 0, diff; + int ret = 0, diff; unsigned int best = (unsigned int) -1; struct cpufreq_frequency_table *table = cpufreq_info.freq_table; + struct cpufreq_frequency_table *pos; rate /= 1000; /* convert to kHz */ - for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) { - diff = table[i].frequency - rate; + cpufreq_for_each_entry(pos, table) { + diff = pos->frequency - rate; if (diff < 0) diff = -diff; if (diff < best) { best = diff; - ret = table[i].frequency; + ret = pos->frequency; } } -- cgit v1.2.3 From 4966ee4037fedd80871659333172481073ec2fac Mon Sep 17 00:00:00 2001 From: Stratos Karafotis Date: Fri, 25 Apr 2014 23:16:25 +0300 Subject: mips: lemote 2f: Use cpufreq_for_each_entry macro for iteration The cpufreq core now supports the cpufreq_for_each_entry macro helper for iteration over the cpufreq_frequency_table, so use it. It should have no functional changes. Signed-off-by: Stratos Karafotis Acked-by: Viresh Kumar Signed-off-by: Rafael J. Wysocki --- arch/mips/loongson/lemote-2f/clock.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c index e1f427f4f5f3..1eed38e28b1e 100644 --- a/arch/mips/loongson/lemote-2f/clock.c +++ b/arch/mips/loongson/lemote-2f/clock.c @@ -91,9 +91,9 @@ EXPORT_SYMBOL(clk_put); int clk_set_rate(struct clk *clk, unsigned long rate) { + struct cpufreq_frequency_table *pos; int ret = 0; int regval; - int i; if (likely(clk->ops && clk->ops->set_rate)) { unsigned long flags; @@ -106,22 +106,16 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) propagate_rate(clk); - for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END; - i++) { - if (loongson2_clockmod_table[i].frequency == - CPUFREQ_ENTRY_INVALID) - continue; - if (rate == loongson2_clockmod_table[i].frequency) + cpufreq_for_each_valid_entry(pos, loongson2_clockmod_table) + if (rate == pos->frequency) break; - } - if (rate != loongson2_clockmod_table[i].frequency) + if (rate != pos->frequency) return -ENOTSUPP; clk->rate = rate; regval = LOONGSON_CHIPCFG0; - regval = (regval & ~0x7) | - (loongson2_clockmod_table[i].driver_data - 1); + regval = (regval & ~0x7) | (pos->driver_data - 1); LOONGSON_CHIPCFG0 = regval; return ret; -- cgit v1.2.3 From cdae05a0f0f7d15837dfd6f4200e8caea03c9cbf Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 28 Apr 2014 10:49:43 +0000 Subject: dmaengine: edma: Make reading the position of active channels work As Joel pointed out, edma_read_position() uses memcpy_fromio() to read the parameter ram. That's not synchronized with the internal update as it does a byte by byte copy. We need to do a 32bit read to get a consistent value. Further reading destination and source is pointless. In DEV_TO_MEM transfers we are only interested in the destination, in MEM_TO_DEV we care about the source. In MEM_TO_MEM it really does not matter which one you read. Simple solution: Remove the pointers, select dest/source via a bool and return the read value. Remove the export of this function while at it. The only potential user is the dmaengine and that's always builtin. Signed-off-by: Thomas Gleixner Acked-by: Sekhar Nori Signed-off-by: Joel Fernandes Signed-off-by: Vinod Koul --- arch/arm/common/edma.c | 24 +++++++++--------------- include/linux/platform_data/edma.h | 2 +- 2 files changed, 10 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c index 0b37f7734d0f..25fa735abc6c 100644 --- a/arch/arm/common/edma.c +++ b/arch/arm/common/edma.c @@ -994,29 +994,23 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port, EXPORT_SYMBOL(edma_set_dest); /** - * edma_get_position - returns the current transfer points + * edma_get_position - returns the current transfer point * @slot: parameter RAM slot being examined - * @src: pointer to source port position - * @dst: pointer to destination port position + * @dst: true selects the dest position, false the source * - * Returns current source and destination addresses for a particular - * parameter RAM slot. Its channel should not be active when this is called. + * Returns the position of the current active slot */ -void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) +dma_addr_t edma_get_position(unsigned slot, bool dst) { - struct edmacc_param temp; - unsigned ctlr; + u32 offs, ctlr = EDMA_CTLR(slot); - ctlr = EDMA_CTLR(slot); slot = EDMA_CHAN_SLOT(slot); - edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); - if (src != NULL) - *src = temp.src; - if (dst != NULL) - *dst = temp.dst; + offs = PARM_OFFSET(slot); + offs += dst ? PARM_DST : PARM_SRC; + + return edma_read(ctlr, offs); } -EXPORT_SYMBOL(edma_get_position); /** * edma_set_src_index - configure DMA source address indexing diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h index 923f8a3e4ce0..12f134b1493c 100644 --- a/include/linux/platform_data/edma.h +++ b/include/linux/platform_data/edma.h @@ -130,7 +130,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port, enum address_mode mode, enum fifo_width); void edma_set_dest(unsigned slot, dma_addr_t dest_port, enum address_mode mode, enum fifo_width); -void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst); +dma_addr_t edma_get_position(unsigned slot, bool dst); void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx); void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx); void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt, -- cgit v1.2.3 From 499c8bf5865926174abb722bbaf1a621c56cc899 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Wed, 15 Jan 2014 18:23:26 +0100 Subject: ARM: dts: mbimxsd35: Add sound support. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Eric Bénard Cc: Grant Likely Cc: Rob Herring Cc: Sascha Hauer Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 1bdec21f4533..71197b926353 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -46,6 +46,14 @@ linux,default-trigger = "heartbeat"; }; }; + + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx35-eukrea-tlv320aic23"; + ssi-controller = <&ssi1>; + fsl,mux-int-port = <1>; + fsl,mux-ext-port = <4>; + }; }; &audmux { @@ -124,6 +132,7 @@ }; &ssi1 { + codec-handle = <&tlv320aic23>; fsl,mode = "i2s-slave"; status = "okay"; }; -- cgit v1.2.3 From 22970070e027cbbb9b2878f8f7c31d0d7f29e94d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 28 Feb 2014 12:58:41 +0100 Subject: ARM: dts: imx: Add alias for ethernet controller Add alias for FEC ethernet on i.MX to allow bootloaders (like U-Boot) patch-in the MAC address for FEC using this alias. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 1 + arch/arm/boot/dts/imx27.dtsi | 1 + arch/arm/boot/dts/imx35.dtsi | 1 + arch/arm/boot/dts/imx50.dtsi | 1 + arch/arm/boot/dts/imx51.dtsi | 1 + arch/arm/boot/dts/imx53.dtsi | 1 + arch/arm/boot/dts/imx6qdl.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + 8 files changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index ea323f09dc78..413d8f0594cb 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -14,6 +14,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 137e010eab35..00cf66c1b8f3 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -16,6 +16,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 88b218f8f810..e59ccb4d98e3 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 9c89d1ca97c2..6a201cf54366 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -17,6 +17,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 150bb4e2f744..51b86700cd88 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -19,6 +19,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 9c2bff2252d0..04815c66fef4 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -18,6 +18,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index eca0971d4db1..02a6afca7530 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -16,6 +16,7 @@ / { aliases { + ethernet0 = &fec; can0 = &can1; can1 = &can2; gpio0 = &gpio1; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index d26b099260a3..2d4e5285f3f3 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -14,6 +14,7 @@ / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; -- cgit v1.2.3 From e8e8d621f90204d8293fd52bfdc3e957990cfa8f Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 2 Mar 2014 13:18:38 +0400 Subject: ARM: dts: imx27-phytec-phycore-rdk: Add missing pinctrl definition for SPI CS1 This patch adds missing pinctrl definition for SPI chipselect 1. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index df3b2e731835..86510ede7ee2 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -15,6 +15,7 @@ }; &cspi1 { + pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, <&gpio4 27 GPIO_ACTIVE_LOW>; @@ -36,6 +37,12 @@ &iomuxc { imx27_phycore_rdk { + pinctrl_cspi1cs1: cspi1cs1grp { + fsl,pins = < + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; + pinctrl_i2c1: i2c1grp { /* Add pullup to DATA line */ fsl,pins = < -- cgit v1.2.3 From 2c40568937dbdc726876d22e84e138e3090a8082 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Sun, 2 Mar 2014 13:18:39 +0400 Subject: ARM: dts: imx27-phytec-phycore-som: Enable SSI1 This patch adds pin group for Synchronous Serial Interface 1 (SSI1) for PCM-038 module and enables this interface. This change do nothing at the current stage but helps to continue develop sound support. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index cefaa6994623..8e10aeff946e 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -251,6 +251,15 @@ >; }; + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI1_FS__SSI1_FS 0x0 + MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 + MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 + MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 @@ -279,6 +288,13 @@ status = "okay"; }; +&ssi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssi1>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + &usbotg { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; -- cgit v1.2.3 From 702bfbef1c98c4ec15b311035ca74e713b68cf07 Mon Sep 17 00:00:00 2001 From: Vincent Stehlé Date: Wed, 5 Mar 2014 19:58:39 +0100 Subject: ARM: dts: imx6qdl-sabresd.dtsi: Add red led MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the red gpio led available to the user. This can be toggled with the sysfs for example, or used as a heartbeat or mmc activity light by changing the trigger. Signed-off-by: Vincent Stehlé Cc: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0d816d3be4b6..7a88d9ae8daa 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -105,6 +105,17 @@ default-brightness-level = <7>; status = "okay"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + red { + gpios = <&gpio1 2 0>; + default-state = "on"; + }; + }; }; &audmux { @@ -422,6 +433,14 @@ >; }; }; + + gpio_leds { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + >; + }; + }; }; &ldb { -- cgit v1.2.3 From 8617cb0b0fd836b208252b3636fc9861cd48cc0f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:35 -0300 Subject: ARM: dts: imx25-pdk: Sort the dt nodes Keep the dt nodes sorted for better readability. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index f607ce520eda..88267c5c3ef4 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -21,10 +21,6 @@ }; }; -&uart1 { - status = "okay"; -}; - &fec { phy-mode = "rmii"; status = "okay"; @@ -34,3 +30,7 @@ nand-on-flash-bbt; status = "okay"; }; + +&uart1 { + status = "okay"; +}; -- cgit v1.2.3 From 53ba9c70a48a28054ebfdaad43a6681b570e3380 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:36 -0300 Subject: ARM: dts: imx25-pdk: Add UART1 pins UART1 is the console port on mx25pdk board. Add the pin configuration for UART1 port and also pass 'fsl,uart-has-rtscts' to indicate that the port has RTS and CTS pins. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 88267c5c3ef4..d6429804cdb2 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -26,11 +26,27 @@ status = "okay"; }; +&iomuxc { + imx25-pdk { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; + }; +}; + &nfc { nand-on-flash-bbt; status = "okay"; }; &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; status = "okay"; }; -- cgit v1.2.3 From f0bd6881e8abc3660bb3e8e6b219ad9a21c88636 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:37 -0300 Subject: ARM: dts: imx25-pdk: Add FEC pins Instead of relying on the bootloader for configuring the FEC pins, pass the FEC pin configuration via device tree instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index d6429804cdb2..a97dd7305c46 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -23,11 +23,27 @@ &fec { phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; status = "okay"; }; &iomuxc { imx25-pdk { + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX25_PAD_UART1_RTS__UART1_RTS 0xe0 -- cgit v1.2.3 From 6e3ef2f66489d13e6ee3a26ed7bf9f920f97339b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:38 -0300 Subject: ARM: dts: imx25-pdk: Provide a regulator for Ethernet PHY GPIO2_3 controls the power to the Ethernet PHY, so provide a regulator node for this. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index a97dd7305c46..d15349e12df9 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -19,12 +19,29 @@ memory { reg = <0x80000000 0x4000000>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 3 0>; + enable-active-high; + }; + }; }; &fec { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_fec_3v3>; status = "okay"; }; @@ -41,6 +58,7 @@ MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + MX25_PAD_A17__GPIO_2_3 0x80000000 >; }; -- cgit v1.2.3 From c7b15c28250b209b0ef4aef650f8f216ad885448 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:39 -0300 Subject: ARM: dts: imx25-pdk: Provide an Ethernet PHY reset GPIO4_8 is connected to the Ethernet PHY reset line, so populate the 'phy-reset-gpios' property accordingly. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index d15349e12df9..9d14fbc155dc 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -42,6 +42,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 8 0>; status = "okay"; }; @@ -59,6 +60,7 @@ MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 MX25_PAD_A17__GPIO_2_3 0x80000000 + MX25_PAD_D12__GPIO_4_8 0x80000000 >; }; -- cgit v1.2.3 From 707e6906ee361f2385919e24058036f65655fd75 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 5 Mar 2014 17:30:40 -0300 Subject: ARM: dts: imx25-pdk: Add esdhc1 support Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-pdk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 9d14fbc155dc..7a6d21fb6e6e 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -37,6 +37,14 @@ }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio2 1 0>; + wp-gpios = <&gpio2 0 0>; + status = "okay"; +}; + &fec { phy-mode = "rmii"; pinctrl-names = "default"; @@ -48,6 +56,19 @@ &iomuxc { imx25-pdk { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 + MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 + MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 + MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 + MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 + MX25_PAD_A14__GPIO_2_0 0x80000000 + MX25_PAD_A15__GPIO_2_1 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 -- cgit v1.2.3 From 0517fe6aa8803e06b1e5984e79dbc70d29280899 Mon Sep 17 00:00:00 2001 From: Cosmin Stoica Date: Thu, 6 Mar 2014 18:40:34 +0200 Subject: ARM: dts: vf610-twr: Add support for sdhc1 The kernel was not able to boot from SD card because sdhc support was not present into the dts. A new entry for sdhc1 was added for vf610-twr board based on the compatible entry present on imx53. After applying these changes, the kernel is able to boot successfully from SD card. Signed-off-by: Cosmin Stoica Signed-off-by: Chircu Bogdan Signed-off-by: Eddy Petrisor Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-twr.dts | 19 +++++++++++++++++++ arch/arm/boot/dts/vf610.dtsi | 11 +++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index ded361075aab..a55f803ef9cb 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -113,6 +113,13 @@ }; }; +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + &fec0 { phy-mode = "rmii"; pinctrl-names = "default"; @@ -160,6 +167,18 @@ >; }; + pinctrl_esdhc1: esdhc1grp { + fsl,fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + pinctrl_fec0: fec0grp { fsl,pins = < VF610_PAD_PTA6__RMII_CLKIN 0x30d1 diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index b8ce0aa7b157..30286bcbe1d0 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -347,6 +347,17 @@ status = "disabled"; }; + esdhc1: esdhc@400b2000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b2000 0x4000>; + interrupts = <0 28 0x04>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC1>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + fec0: ethernet@400d0000 { compatible = "fsl,mvf600-fec"; reg = <0x400d0000 0x1000>; -- cgit v1.2.3 From 3937f66b9f7e728258d45b98853c7137e88e0cf8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Mar 2014 10:18:39 +0100 Subject: ARM: dts: mx25: USB block requires only one clock Like other imx SoCs only one USB clock is needed on mx25. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 413d8f0594cb..cc441ec11818 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -497,8 +497,7 @@ compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -507,8 +506,7 @@ compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4400 0x0200>; interrupts = <35>; - clocks = <&clks 9>, <&clks 70>, <&clks 8>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; -- cgit v1.2.3 From 056c5a598ffdf3812d026365b726b2bbdc28983a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Mar 2014 10:18:40 +0100 Subject: ARM: dts: mx35: USB block requires only one clock Like other imx SoCs only one USB clock is needed on mx35. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index e59ccb4d98e3..474a73d78912 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -296,8 +296,7 @@ compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 0>; status = "disabled"; }; @@ -306,8 +305,7 @@ compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4400 0x0200>; interrupts = <35>; - clocks = <&clks 9>, <&clks 73>, <&clks 28>; - clock-names = "ipg", "ahb", "per"; + clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 1>; status = "disabled"; }; -- cgit v1.2.3 From f415153c0ecaae1f4515df35d2c6d055ed97909c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 13 Mar 2014 10:18:42 +0100 Subject: ARM: dts: imx25.dtsi: Fix USB support. Signed-off-by: Fabio Estevam Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index cc441ec11818..9c092571d482 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -483,22 +483,13 @@ clocks = <&clks 99>; }; - usbphy1: usbphy@1 { - compatible = "nop-usbphy"; - status = "disabled"; - }; - - usbphy2: usbphy@2 { - compatible = "nop-usbphy"; - status = "disabled"; - }; - usbotg: usb@53ff4000 { compatible = "fsl,imx25-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; interrupts = <37>; clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -508,6 +499,7 @@ interrupts = <35>; clocks = <&clks 70>; fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -517,7 +509,6 @@ clocks = <&clks 9>, <&clks 70>, <&clks 8>; clock-names = "ipg", "ahb", "per"; reg = <0x53ff4600 0x00f>; - status = "disabled"; }; dryice@53ffc000 { @@ -549,4 +540,20 @@ }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + }; + }; }; -- cgit v1.2.3 From 3b7af8839b5f7be3c1feaedd5ed9ed893d377429 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:43 +0100 Subject: ARM: dts: mbimxsd25 baseboard: Add USB support Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 62fb3da50bdb..ad12da38fc92 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -172,3 +172,16 @@ fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; -- cgit v1.2.3 From ff348251442584135950d64d0b7d53d6e0870611 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:44 +0100 Subject: ARM: dts: i.MX35: Add USB support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 474a73d78912..4759abb49436 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -298,6 +298,7 @@ interrupts = <37>; clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; @@ -307,6 +308,7 @@ interrupts = <35>; clocks = <&clks 73>; fsl,usbmisc = <&usbmisc 1>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; @@ -355,4 +357,20 @@ }; }; }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usb-phy@0 { + reg = <0>; + compatible = "usb-nop-xceiv"; + }; + + usbphy1: usb-phy@1 { + reg = <1>; + compatible = "usb-nop-xceiv"; + }; + }; }; -- cgit v1.2.3 From 9afe7d9dadad9aaf3de03fba1bc72ddb69d696af Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:45 +0100 Subject: ARM: dts: mbimxsd35 baseboard: Add USB support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts index 71197b926353..f04ae91eea89 100644 --- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts @@ -150,3 +150,16 @@ fsl,uart-has-rtscts; status = "okay"; }; + +&usbhost1 { + phy_type = "serial"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi"; + dr_mode = "otg"; + external-vbus-divider; + status = "okay"; +}; -- cgit v1.2.3 From 477fbf1db8cb7b33ada578efb6dd8ce2f00de7f8 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Mon, 3 Mar 2014 22:37:44 +0400 Subject: ARM: i.MX: mx21ads: Replace direct handling of peripheral bits with GPIOs This patch replaces direct handling of peripheral bits with GPIOs by using basic-mmio-gpio driver. As a result this change eliminate some low-level code and removes custom io_map() from the board. Signed-off-by: Alexander Shiyan Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-mx21ads.c | 136 +++++++++++++++++++-------------------- 1 file changed, 66 insertions(+), 70 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index a06aa4dc37fc..87425949244a 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -17,51 +17,45 @@ #include #include #include +#include #include #include #include #include -#include #include "common.h" #include "devices-imx21.h" #include "hardware.h" #include "iomux-mx21.h" -/* - * Memory-mapped I/O on MX21ADS base board - */ -#define MX21ADS_MMIO_BASE_ADDR 0xf5000000 -#define MX21ADS_MMIO_SIZE 0xc00000 - -#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ - (MX21ADS_MMIO_BASE_ADDR + (offset)) +#define MX21ADS_CS8900A_REG (MX21_CS1_BASE_ADDR + 0x000000) +#define MX21ADS_ST16C255_IOBASE_REG (MX21_CS1_BASE_ADDR + 0x200000) +#define MX21ADS_VERSION_REG (MX21_CS1_BASE_ADDR + 0x400000) +#define MX21ADS_IO_REG (MX21_CS1_BASE_ADDR + 0x800000) -#define MX21ADS_CS8900A_MMIO_SIZE 0x200000 -#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11) -#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) -#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) -#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) +#define MX21ADS_MMC_CD IMX_GPIO_NR(4, 25) +#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11) +#define MX21ADS_MMGPIO_BASE (6 * 32) /* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP 0x0001 /* read */ -#define MX21ADS_IO_TP6 0x0001 /* write */ -#define MX21ADS_IO_SW_SEL 0x0002 /* read */ -#define MX21ADS_IO_TP7 0x0002 /* write */ -#define MX21ADS_IO_RESET_E_UART 0x0004 -#define MX21ADS_IO_RESET_BASE 0x0008 -#define MX21ADS_IO_CSI_CTL2 0x0010 -#define MX21ADS_IO_CSI_CTL1 0x0020 -#define MX21ADS_IO_CSI_CTL0 0x0040 -#define MX21ADS_IO_UART1_EN 0x0080 -#define MX21ADS_IO_UART4_EN 0x0100 -#define MX21ADS_IO_LCDON 0x0200 -#define MX21ADS_IO_IRDA_EN 0x0400 -#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 -#define MX21ADS_IO_IRDA_MD0_B 0x1000 -#define MX21ADS_IO_IRDA_MD1 0x2000 -#define MX21ADS_IO_LED4_ON 0x4000 -#define MX21ADS_IO_LED3_ON 0x8000 +#define MX21ADS_IO_SD_WP (MX21ADS_MMGPIO_BASE + 0) +#define MX21ADS_IO_TP6 (MX21ADS_IO_SD_WP) +#define MX21ADS_IO_SW_SEL (MX21ADS_MMGPIO_BASE + 1) +#define MX21ADS_IO_TP7 (MX21ADS_IO_SW_SEL) +#define MX21ADS_IO_RESET_E_UART (MX21ADS_MMGPIO_BASE + 2) +#define MX21ADS_IO_RESET_BASE (MX21ADS_MMGPIO_BASE + 3) +#define MX21ADS_IO_CSI_CTL2 (MX21ADS_MMGPIO_BASE + 4) +#define MX21ADS_IO_CSI_CTL1 (MX21ADS_MMGPIO_BASE + 5) +#define MX21ADS_IO_CSI_CTL0 (MX21ADS_MMGPIO_BASE + 6) +#define MX21ADS_IO_UART1_EN (MX21ADS_MMGPIO_BASE + 7) +#define MX21ADS_IO_UART4_EN (MX21ADS_MMGPIO_BASE + 8) +#define MX21ADS_IO_LCDON (MX21ADS_MMGPIO_BASE + 9) +#define MX21ADS_IO_IRDA_EN (MX21ADS_MMGPIO_BASE + 10) +#define MX21ADS_IO_IRDA_FIR_SEL (MX21ADS_MMGPIO_BASE + 11) +#define MX21ADS_IO_IRDA_MD0_B (MX21ADS_MMGPIO_BASE + 12) +#define MX21ADS_IO_IRDA_MD1 (MX21ADS_MMGPIO_BASE + 13) +#define MX21ADS_IO_LED4_ON (MX21ADS_MMGPIO_BASE + 14) +#define MX21ADS_IO_LED3_ON (MX21ADS_MMGPIO_BASE + 15) static const int mx21ads_pins[] __initconst = { @@ -160,7 +154,7 @@ static struct platform_device mx21ads_nor_mtd_device = { }; static struct resource mx21ads_cs8900_resources[] __initdata = { - DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), + DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, SZ_1K), /* irq number is run-time assigned */ DEFINE_RES_IRQ(-1), }; @@ -179,23 +173,39 @@ static const struct imxuart_platform_data uart_pdata_rts __initconst = { static const struct imxuart_platform_data uart_pdata_norts __initconst = { }; +static struct resource mx21ads_mmgpio_resource = + DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat"); + +static struct bgpio_pdata mx21ads_mmgpio_pdata = { + .base = MX21ADS_MMGPIO_BASE, + .ngpio = 16, +}; + +static struct platform_device mx21ads_mmgpio = { + .name = "basic-mmio-gpio", + .id = PLATFORM_DEVID_AUTO, + .resource = &mx21ads_mmgpio_resource, + .num_resources = 1, + .dev = { + .platform_data = &mx21ads_mmgpio_pdata, + }, +}; + static int mx21ads_fb_init(struct platform_device *pdev) { - u16 tmp; + int ret; - tmp = __raw_readw(MX21ADS_IO_REG); - tmp |= MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); - return 0; + ret = gpio_request(MX21ADS_IO_LCDON, "fb-lcdon"); + if (ret) + return ret; + + return gpio_direction_output(MX21ADS_IO_LCDON, 1); } static void mx21ads_fb_exit(struct platform_device *pdev) { - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp &= ~MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); + gpio_set_value(MX21ADS_IO_LCDON, 0); + gpio_free(MX21ADS_IO_LCDON); } /* @@ -236,19 +246,26 @@ static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { static int mx21ads_sdhc_get_ro(struct device *dev) { - return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; + return gpio_get_value(MX21ADS_IO_SD_WP); } static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, void *data) { - return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); + int ret; + + ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro"); + if (ret) + return ret; + + return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq, + IRQF_TRIGGER_FALLING, "mmc-detect", data); } static void mx21ads_sdhc_exit(struct device *dev, void *data) { - free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data); + free_irq(gpio_to_irq(MX21ADS_MMC_CD), data); + gpio_free(MX21ADS_IO_SD_WP); } static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { @@ -264,29 +281,8 @@ mx21ads_nand_board_info __initconst = { .hw_ecc = 1, }; -static struct map_desc mx21ads_io_desc[] __initdata = { - /* - * Memory-mapped I/O on MX21ADS Base board: - * - CS8900A Ethernet controller - * - ST16C2552CJ UART - * - CPU and Base board version - * - Base board I/O register - */ - { - .virtual = MX21ADS_MMIO_BASE_ADDR, - .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR), - .length = MX21ADS_MMIO_SIZE, - .type = MT_DEVICE, - }, -}; - -static void __init mx21ads_map_io(void) -{ - mx21_map_io(); - iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc)); -} - static struct platform_device *platform_devices[] __initdata = { + &mx21ads_mmgpio, &mx21ads_nor_mtd_device, }; @@ -321,7 +317,7 @@ static void __init mx21ads_timer_init(void) MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ .atag_offset = 0x100, - .map_io = mx21ads_map_io, + .map_io = mx21_map_io, .init_early = imx21_init_early, .init_irq = mx21_init_irq, .handle_irq = imx21_handle_irq, -- cgit v1.2.3 From cfdb7d564c03a06e00f76a5e9b3929f802c1040b Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 5 Mar 2014 23:07:48 +0100 Subject: ARM: vf610: add UART choice for low-level debug Add choice for low-level debug UART. Similar to i.MX6, there is a numeric configuration, valid choices are 0 to 3. Note that the kernel assumes that the boot loader initialized clock properly. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/Kconfig.debug | 9 +++++++++ arch/arm/include/debug/vf.S | 15 +++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index eab8ecbe69c1..00c69503da22 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -942,6 +942,15 @@ config DEBUG_IMX_UART_PORT Choose UART port on which kernel low-level debug messages should be output. +config DEBUG_VF_UART_PORT + int "Vybrid Debug UART Port Selection" if DEBUG_VF_UART + default 1 + range 0 3 + depends on SOC_VF610 + help + Choose UART port on which kernel low-level debug messages + should be output. + config DEBUG_TEGRA_UART bool depends on ARCH_TEGRA diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S index ba12cc44b2cb..b88933849a17 100644 --- a/arch/arm/include/debug/vf.S +++ b/arch/arm/include/debug/vf.S @@ -7,9 +7,20 @@ * */ +#define VF_UART0_BASE_ADDR 0x40027000 +#define VF_UART1_BASE_ADDR 0x40028000 +#define VF_UART2_BASE_ADDR 0x40029000 +#define VF_UART3_BASE_ADDR 0x4002a000 +#define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR +#define VF_UART_BASE(n) VF_UART_BASE_ADDR(n) +#define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT) + +#define VF_UART_VIRTUAL_BASE 0xfe000000 + .macro addruart, rp, rv, tmp - ldr \rp, =0x40028000 @ physical - ldr \rv, =0xfe028000 @ virtual + ldr \rp, =VF_UART_PHYSICAL_BASE @ physical + and \rv, \rp, #0xffffff @ offset within 16MB section + add \rv, \rv, #VF_UART_VIRTUAL_BASE .endm .macro senduart, rd, rx -- cgit v1.2.3 From 6b961bad80c6d41f177df9256ff1d2794d3849de Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Thu, 6 Mar 2014 20:23:32 +0400 Subject: ARM: i.MX: mx21ads: Use fixed voltage regulator for LCD power Instead of using init() and exit() hooks from framebuffer driver to control power of LCD, introduce fixed voltage regulator for this purpose. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-mx21ads.c | 45 +++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 87425949244a..0b8e63fdbca0 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -191,22 +193,32 @@ static struct platform_device mx21ads_mmgpio = { }, }; -static int mx21ads_fb_init(struct platform_device *pdev) -{ - int ret; +static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer = + REGULATOR_SUPPLY("lcd", "imx-fb.0"); - ret = gpio_request(MX21ADS_IO_LCDON, "fb-lcdon"); - if (ret) - return ret; +static struct regulator_init_data mx21ads_lcd_regulator_init_data = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .consumer_supplies = &mx21ads_lcd_regulator_consumer, + .num_consumer_supplies = 1, +}; - return gpio_direction_output(MX21ADS_IO_LCDON, 1); -} +static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = { + .supply_name = "LCD", + .microvolts = 3300000, + .gpio = MX21ADS_IO_LCDON, + .enable_high = 1, + .init_data = &mx21ads_lcd_regulator_init_data, +}; -static void mx21ads_fb_exit(struct platform_device *pdev) -{ - gpio_set_value(MX21ADS_IO_LCDON, 0); - gpio_free(MX21ADS_IO_LCDON); -} +static struct platform_device mx21ads_lcd_regulator = { + .name = "reg-fixed-voltage", + .id = PLATFORM_DEVID_AUTO, + .dev = { + .platform_data = &mx21ads_lcd_regulator_pdata, + }, +}; /* * Connected is a portrait Sharp-QVGA display @@ -239,9 +251,6 @@ static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { .pwmr = 0x00a903ff, .lscr1 = 0x00120300, .dmacr = 0x00020008, - - .init = mx21ads_fb_init, - .exit = mx21ads_fb_exit, }; static int mx21ads_sdhc_get_ro(struct device *dev) @@ -283,6 +292,7 @@ mx21ads_nand_board_info __initconst = { static struct platform_device *platform_devices[] __initdata = { &mx21ads_mmgpio, + &mx21ads_lcd_regulator, &mx21ads_nor_mtd_device, }; @@ -296,12 +306,13 @@ static void __init mx21ads_board_init(void) imx21_add_imx_uart0(&uart_pdata_rts); imx21_add_imx_uart2(&uart_pdata_norts); imx21_add_imx_uart3(&uart_pdata_rts); - imx21_add_imx_fb(&mx21ads_fb_data); imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); imx21_add_mxc_nand(&mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + imx21_add_imx_fb(&mx21ads_fb_data); + mx21ads_cs8900_resources[1].start = gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO); mx21ads_cs8900_resources[1].end = -- cgit v1.2.3 From ddeef94e3a27aedb0364b869ad9e0fd8ed098c6c Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Thu, 6 Mar 2014 20:23:33 +0400 Subject: ARM: i.MX: mx21ads: Cleanup board - Remove unused inclusion. - Use predefined constant for CS8900A base address. - Use DEFINE_RES_MEM() macro for NOR flash resource. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-mx21ads.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 0b8e63fdbca0..30c30fdae53f 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -23,7 +23,6 @@ #include #include #include -#include #include "common.h" #include "devices-imx21.h" @@ -139,11 +138,8 @@ static struct physmap_flash_data mx21ads_flash_data = { .width = 4, }; -static struct resource mx21ads_flash_resource = { - .start = MX21_CS0_BASE_ADDR, - .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, - .flags = IORESOURCE_MEM, -}; +static struct resource mx21ads_flash_resource = + DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M); static struct platform_device mx21ads_nor_mtd_device = { .name = "physmap-flash", @@ -156,7 +152,7 @@ static struct platform_device mx21ads_nor_mtd_device = { }; static struct resource mx21ads_cs8900_resources[] __initdata = { - DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, SZ_1K), + DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K), /* irq number is run-time assigned */ DEFINE_RES_IRQ(-1), }; -- cgit v1.2.3 From 61a3f6e7539531fe9183bac7130bd1571506ee84 Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Thu, 13 Mar 2014 10:18:46 +0100 Subject: ARM: imx_v4_v5_defconfig: Enable drivers for i.MX25/i.MX35 USB support. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v4_v5_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index f1aeb7d72712..ec9b36580952 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -80,6 +80,7 @@ CONFIG_MTD_UBI=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y CONFIG_ATA=y +CONFIG_BLK_DEV_SD=y CONFIG_PATA_IMX=y CONFIG_NETDEVICES=y CONFIG_CS89x0=y @@ -153,6 +154,11 @@ CONFIG_USB_HID=m CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MXC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_NOP_USB_XCEIV=y CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_SDHCI=y -- cgit v1.2.3 From 4849f2506917cb0d66ae244fb48ad2cd17ef19dd Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 19 Mar 2014 15:49:22 +0100 Subject: ARM: i.MX5: Remove outdated VPU clock lookups CODA7 clock lookups are now defined in the device tree. Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx51-imx53.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 568ef0a4de84..b409773cb6d8 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -436,7 +436,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); - clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0"); clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0"); clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0"); clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0"); @@ -561,7 +560,6 @@ static void __init mx53_clocks_init(struct device_node *np) mx5_clocks_common_init(0, 0, 0, 0); - clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0"); clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0"); clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0"); -- cgit v1.2.3 From bc02cd69821f3610422d26987f1cdef25c87a7b2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 4 Apr 2014 12:12:59 -0300 Subject: ARM: imx: Remove mx51_babbage board file The device tree version for the babbage board (imx51-babbage.dtb) has a more complete support than the board file version, so remove the board file source code. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/Kconfig | 15 -- arch/arm/mach-imx/Makefile | 1 - arch/arm/mach-imx/mach-mx51_babbage.c | 428 ---------------------------------- 3 files changed, 444 deletions(-) delete mode 100644 arch/arm/mach-imx/mach-mx51_babbage.c (limited to 'arch') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5740296dc429..d56eb1a001d8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -711,21 +711,6 @@ config MACH_IMX51_DT Include support for Freescale i.MX51 based platforms using the device tree for discovery -config MACH_MX51_BABBAGE - bool "Support MX51 BABBAGE platforms" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select SOC_IMX51 - help - Include support for MX51 Babbage platform, also known as MX51EVK in - u-boot. This includes specific configurations for the board and its - peripherals. - config MACH_EUKREA_CPUIMX51SD bool "Support Eukrea CPUIMX51SD module" select IMX_HAVE_PLATFORM_FSL_USB2_UDC diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index f4ed83032dd0..8dd377be88a6 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -109,7 +109,6 @@ endif obj-$(CONFIG_SOC_IMX6) += pm-imx6.o # i.MX5 based machines -obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c deleted file mode 100644 index f3d264a636fa..000000000000 --- a/arch/arm/mach-imx/mach-mx51_babbage.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "common.h" -#include "devices-imx51.h" -#include "hardware.h" -#include "iomux-mx51.h" - -#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) -#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) -#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5) -#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) -#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) -#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) -#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) -#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6) -#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5) - -/* USB_CTRL_1 */ -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) - -#define MX51_USB_PLLDIV_12_MHZ 0x00 -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 -#define MX51_USB_PLL_DIV_24_MHZ 0x02 - -static struct gpio_keys_button babbage_buttons[] = { - { - .gpio = BABBAGE_POWER_KEY, - .code = BTN_0, - .desc = "PWR", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data imx_button_data __initconst = { - .buttons = babbage_buttons, - .nbuttons = ARRAY_SIZE(babbage_buttons), -}; - -static iomux_v3_cfg_t mx51babbage_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - - /* UART3 */ - MX51_PAD_EIM_D25__UART3_RXD, - MX51_PAD_EIM_D26__UART3_TXD, - MX51_PAD_EIM_D27__UART3_RTS, - MX51_PAD_EIM_D24__UART3_CTS, - - /* I2C1 */ - MX51_PAD_EIM_D16__I2C1_SDA, - MX51_PAD_EIM_D19__I2C1_SCL, - - /* I2C2 */ - MX51_PAD_KEY_COL4__I2C2_SCL, - MX51_PAD_KEY_COL5__I2C2_SDA, - - /* HSI2C */ - MX51_PAD_I2C1_CLK__I2C1_CLK, - MX51_PAD_I2C1_DAT__I2C1_DAT, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - /* USB HUB reset line*/ - MX51_PAD_GPIO1_7__GPIO1_7, - - /* USB PHY reset line */ - MX51_PAD_EIM_D21__GPIO2_5, - - /* FEC */ - MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDATA1, - MX51_PAD_EIM_CS2__FEC_RDATA2, - MX51_PAD_EIM_CS3__FEC_RDATA3, - MX51_PAD_EIM_CS4__FEC_RX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RX_CLK, - MX51_PAD_NANDF_D9__FEC_RDATA0, - MX51_PAD_NANDF_D8__FEC_TDATA0, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDATA1, - MX51_PAD_NANDF_CS5__FEC_TDATA2, - MX51_PAD_NANDF_CS6__FEC_TDATA3, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - - /* FEC PHY reset line */ - MX51_PAD_EIM_A20__GPIO2_14, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - /* CD/WP from controller */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - /* CD/WP gpio */ - MX51_PAD_GPIO1_6__GPIO1_6, - MX51_PAD_GPIO1_5__GPIO1_5, - - /* eCSPI1 */ - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - - /* Audio */ - MX51_PAD_AUD3_BB_TXD__AUD3_TXD, - MX51_PAD_AUD3_BB_RXD__AUD3_RXD, - MX51_PAD_AUD3_BB_CK__AUD3_TXC, - MX51_PAD_AUD3_BB_FS__AUD3_TXFS, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data babbage_i2c_data __initconst = { - .bitrate = 100000, -}; - -static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = { - .bitrate = 400000, -}; - -static struct gpio mx51_babbage_usbh1_gpios[] = { - { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" }, - { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" }, -}; - -static int gpio_usbh1_active(void) -{ - iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27; - int ret; - - /* Set USBH1_STP to GPIO and toggle it */ - mxc_iomux_v3_setup_pad(usbh1stp_gpio); - ret = gpio_request_array(mx51_babbage_usbh1_gpios, - ARRAY_SIZE(mx51_babbage_usbh1_gpios)); - - if (ret) { - pr_debug("failed to get USBH1 pins: %d\n", ret); - return ret; - } - - msleep(100); - gpio_set_value(BABBAGE_USBH1_STP, 1); - gpio_set_value(BABBAGE_USB_PHY_RESET, 1); - gpio_free_array(mx51_babbage_usbh1_gpios, - ARRAY_SIZE(mx51_babbage_usbh1_gpios)); - return 0; -} - -static inline void babbage_usbhub_reset(void) -{ - int ret; - - /* Reset USB hub */ - ret = gpio_request_one(BABBAGE_USB_HUB_RESET, - GPIOF_OUT_INIT_LOW, "GPIO1_7"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); - return; - } - - msleep(2); - /* Deassert reset */ - gpio_set_value(BABBAGE_USB_HUB_RESET, 1); -} - -static inline void babbage_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request_one(BABBAGE_FEC_PHY_RESET, - GPIOF_OUT_INIT_LOW, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - msleep(1); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); -} - -/* This function is board specific as the bit mask for the plldiv will also -be different for other Freescale SoCs, thus a common bitmask is not -possible and cannot get place in /plat-mxc/ehci.c.*/ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* The clock for the USBH1 ULPI port will come externally from the PHY. */ - v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_ITC_NO_THRESHOLD); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -static const struct mxc_usbh_platform_data usbh1_config __initconst = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init babbage_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", babbage_otg_mode); - -static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = { - { - .modalias = "mtd_dataflash", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL, - }, -}; - -static int mx51_babbage_spi_cs[] = { - BABBAGE_ECSPI1_CS0, - BABBAGE_ECSPI1_CS1, -}; - -static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { - .chipselect = mx51_babbage_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), -}; - -static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { - .cd_gpio = BABBAGE_SD2_CD, - .wp_gpio = BABBAGE_SD2_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -void __init imx51_babbage_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, - ARRAY_SIZE(mx51babbage_pads)); -} - -/* - * Board specific initialization. - */ -static void __init mx51_babbage_init(void) -{ - iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, - PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH); - - imx51_soc_init(); - - imx51_babbage_common_init(); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); - - babbage_fec_reset(); - imx51_add_fec(NULL); - - /* Set the PAD settings for the pwr key. */ - mxc_iomux_v3_setup_pad(power_key); - imx_add_gpio_keys(&imx_button_data); - - imx51_add_imx_i2c(0, &babbage_i2c_data); - imx51_add_imx_i2c(1, &babbage_i2c_data); - imx51_add_hsi2c(&babbage_hsi2c_data); - - if (otg_mode_host) - imx51_add_mxc_ehci_otg(&dr_utmi_config); - else { - initialize_otg_port(NULL); - imx51_add_fsl_usb2_udc(&usb_pdata); - } - - gpio_usbh1_active(); - imx51_add_mxc_ehci_hs(1, &usbh1_config); - /* setback USBH1_STP to be function */ - mxc_iomux_v3_setup_pad(usbh1stp); - babbage_usbhub_reset(); - - imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); - imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); - - spi_register_board_info(mx51_babbage_spi_board_info, - ARRAY_SIZE(mx51_babbage_spi_board_info)); - imx51_add_ecspi(0, &mx51_babbage_spi_pdata); - imx51_add_imx2_wdt(0); -} - -static void __init mx51_babbage_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") - /* Maintainer: Amit Kucheria */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_time = mx51_babbage_timer_init, - .init_machine = mx51_babbage_init, - .init_late = imx51_init_late, - .restart = mxc_restart, -MACHINE_END -- cgit v1.2.3 From 876292d66791c0f635333bf8d31efd11701fe495 Mon Sep 17 00:00:00 2001 From: Gilles Chanteperdrix Date: Sat, 5 Apr 2014 17:57:45 +0200 Subject: ARM: imx: factor device tree timer initialization Signed-off-by: Gilles Chanteperdrix Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-imx25.c | 9 +-------- arch/arm/mach-imx/clk-imx51-imx53.c | 18 ++++-------------- arch/arm/mach-imx/clk-imx6q.c | 8 ++------ arch/arm/mach-imx/clk-imx6sl.c | 6 +----- arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/time.c | 15 +++++++++++++++ 6 files changed, 25 insertions(+), 33 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index dc36e6c2f1da..269c4d47630e 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -304,8 +304,6 @@ int __init mx25_clocks_init(void) int __init mx25_clocks_init_dt(void) { struct device_node *np; - void __iomem *base; - int irq; unsigned long osc_rate = 24000000; /* retrieve the freqency of fixed clocks from device tree */ @@ -325,12 +323,7 @@ int __init mx25_clocks_init_dt(void) __mx25_clocks_init(osc_rate); - np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - - mxc_timer_init(base, irq); + mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt")); return 0; } diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index b409773cb6d8..21d2b111c83d 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -322,9 +322,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, static void __init mx50_clocks_init(struct device_node *np) { - void __iomem *base; unsigned long r; - int i, irq; + int i; clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); @@ -372,11 +371,7 @@ static void __init mx50_clocks_init(struct device_node *np) r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); - np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); + mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt")); } CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); @@ -491,9 +486,8 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt); static void __init mx53_clocks_init(struct device_node *np) { - int i, irq; + int i; unsigned long r; - void __iomem *base; clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); @@ -590,10 +584,6 @@ static void __init mx53_clocks_init(struct device_node *np) r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); + mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt")); } CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 2b4d6acfa34a..d44d7c376492 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int i, irq; + int i; int ret; clk[dummy] = imx_clk_fixed("dummy", 0); @@ -489,10 +489,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); + mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt")); } CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index f7073c0782fb..21cf06cebade 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -169,7 +169,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; - int irq; int i; int ret; @@ -385,9 +384,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) imx6q_set_lpm(WAIT_CLOCKED); np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); + mxc_timer_init_dt(np); } CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index b5241ea76706..4facd01d1c75 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -17,6 +17,7 @@ struct irq_data; struct platform_device; struct pt_regs; struct clk; +struct device_node; enum mxc_cpu_pwr_mode; void mx1_map_io(void); @@ -56,6 +57,7 @@ void imx51_init_late(void); void imx53_init_late(void); void epit_timer_init(void __iomem *base, int irq); void mxc_timer_init(void __iomem *, int); +void mxc_timer_init_dt(struct device_node *); int mx1_clocks_init(unsigned long fref); int mx21_clocks_init(unsigned long lref, unsigned long fref); int mx25_clocks_init(void); diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 65222ea0df6d..bed081e58262 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -28,6 +28,9 @@ #include #include #include +#include +#include +#include #include @@ -328,3 +331,15 @@ void __init mxc_timer_init(void __iomem *base, int irq) /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); } + +void __init mxc_timer_init_dt(struct device_node *np) +{ + void __iomem *base; + int irq; + + base = of_iomap(np, 0); + WARN_ON(!base); + irq = irq_of_parse_and_map(np, 0); + + mxc_timer_init(base, irq); +} -- cgit v1.2.3 From 84ffe9c0edbddf4515b3a47c112b93a1dafd46de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 5 Apr 2014 15:45:28 -0300 Subject: ARM: mxs_defconfig: Select CONFIG_CRYPTO_DEV_MXS_DCP Let CONFIG_CRYPTO_DEV_MXS_DCP driver to be built by default. Generated by doing: make mxs_defconfig Manually selected the CONFIG_CRYPTO_DEV_MXS_DCP driver make savedefconfig cp defconfig arch/arm/configs/mxs_defconfig Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm/configs/mxs_defconfig | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig index 6150108e15de..40e87c412419 100644 --- a/arch/arm/configs/mxs_defconfig +++ b/arch/arm/configs/mxs_defconfig @@ -26,7 +26,6 @@ CONFIG_ARCH_MXS=y # CONFIG_ARM_THUMB is not set CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y -CONFIG_FPE_NWFPE=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -51,7 +50,6 @@ CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_M25P80=y -# CONFIG_M25PXX_USE_FAST_READ is not set CONFIG_MTD_SST25L=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_GPMI_NAND=y @@ -138,7 +136,6 @@ CONFIG_DMADEVICES=y CONFIG_MXS_DMA=y CONFIG_STAGING=y CONFIG_MXS_LRADC=y -CONFIG_COMMON_CLK_DEBUG=y CONFIG_IIO=y CONFIG_IIO_SYSFS_TRIGGER=y CONFIG_PWM=y @@ -180,7 +177,7 @@ CONFIG_BLK_DEV_IO_TRACE=y CONFIG_STRICT_DEVMEM=y CONFIG_DEBUG_USER=y # CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set +CONFIG_CRYPTO_DEV_MXS_DCP=y CONFIG_CRC_ITU_T=m CONFIG_CRC7=m CONFIG_FONTS=y -- cgit v1.2.3 From 656be7cfe5c14d63c9c80c7779959d9bb9f0f85f Mon Sep 17 00:00:00 2001 From: Denis Carikli Date: Mon, 7 Apr 2014 14:44:51 +0200 Subject: ARM: imx_v6_v7_defconfig: Add more drm drivers. The DRM_PANEL_SIMPLE is needed by the eukrea mbimxsd51's displays. Signed-off-by: Denis Carikli Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 09e974392fa1..0316926f44cd 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -183,6 +183,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_CODA=y CONFIG_SOC_CAMERA_OV2640=y CONFIG_DRM=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_L4F00242T03=y @@ -245,6 +246,7 @@ CONFIG_DRM_IMX_TVE=y CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_IPUV3_CORE=y CONFIG_DRM_IMX_IPUV3=y +CONFIG_DRM_IMX_HDMI=y CONFIG_COMMON_CLK_DEBUG=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_PWM=y -- cgit v1.2.3 From 8c97cec99033005cf1ede48a7b351e48a723749a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 2 Apr 2014 17:45:06 -0500 Subject: mips: octeon: convert to use unflatten_and_copy_device_tree The octeon FDT code can be simplified by using unflatten_and_copy_device_tree function. This removes all accesses to FDT header data by the arch code. Signed-off-by: Rob Herring Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Tested-by: Grant Likely --- arch/mips/cavium-octeon/setup.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 331b837cec57..f1bec00d5a85 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -1053,36 +1053,26 @@ void prom_free_prom_memory(void) int octeon_prune_device_tree(void); extern const char __dtb_octeon_3xxx_begin; -extern const char __dtb_octeon_3xxx_end; extern const char __dtb_octeon_68xx_begin; -extern const char __dtb_octeon_68xx_end; void __init device_tree_init(void) { - int dt_size; - struct boot_param_header *fdt; + const void *fdt; bool do_prune; if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { fdt = phys_to_virt(octeon_bootinfo->fdt_addr); if (fdt_check_header(fdt)) panic("Corrupt Device Tree passed to kernel."); - dt_size = be32_to_cpu(fdt->totalsize); do_prune = false; } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { - fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; - dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; + fdt = &__dtb_octeon_68xx_begin; do_prune = true; } else { - fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; - dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + fdt = &__dtb_octeon_3xxx_begin; do_prune = true; } - /* Copy the default tree from init memory. */ - initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); - if (initial_boot_params == NULL) - panic("Could not allocate initial_boot_params"); - memcpy(initial_boot_params, fdt, dt_size); + initial_boot_params = (void *)fdt; if (do_prune) { octeon_prune_device_tree(); @@ -1090,7 +1080,7 @@ void __init device_tree_init(void) } else { pr_info("Using passed Device Tree.\n"); } - unflatten_device_tree(); + unflatten_and_copy_device_tree(); } static int __initdata disable_octeon_edac_p; -- cgit v1.2.3 From 10fbdaab3f51359c5377495b1ab0698bb8e64df9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 2 Apr 2014 17:50:19 -0500 Subject: mips: lantiq: copy built-in DTB out of init section The existing code is buggy because built-in DTBs are in init memory. Fix this by using the unflatten_and_copy_device_tree function. This removes all accesses to FDT header data by the arch code. Signed-off-by: Rob Herring Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Tested-by: Grant Likely --- arch/mips/lantiq/prom.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 19686c5bc5ed..cdea687ad490 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -76,18 +76,7 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_bootmem(base, size, BOOTMEM_DEFAULT); - - unflatten_device_tree(); + unflatten_and_copy_device_tree(); } void __init prom_init(void) -- cgit v1.2.3 From e1b77baed6b170b190a72821b39a2e91a66f1e54 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 2 Apr 2014 17:52:43 -0500 Subject: mips: xlp: copy built-in DTB out of init section The existing code is buggy because built-in DTBs are in init memory. It is also broken because the reserved bootmem was then freed after unflattening, but the unflattened tree points to data in the flat tree. Fix this by using the unflatten_and_copy_device_tree function. This removes all accesses to FDT header data by the arch code. Signed-off-by: Rob Herring Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Tested-by: Grant Likely --- arch/mips/netlogic/xlp/dt.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c index 5754097b9cde..7f9615a712fb 100644 --- a/arch/mips/netlogic/xlp/dt.c +++ b/arch/mips/netlogic/xlp/dt.c @@ -87,22 +87,7 @@ void __init xlp_early_init_devtree(void) void __init device_tree_init(void) { - unsigned long base, size; - struct boot_param_header *fdtp = xlp_fdt_blob; - - if (!fdtp) - return; - - base = virt_to_phys(fdtp); - size = be32_to_cpu(fdtp->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_bootmem(base, size, BOOTMEM_DEFAULT); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_bootmem(base, size); + unflatten_and_copy_device_tree(); } static struct of_device_id __initdata xlp_ids[] = { -- cgit v1.2.3 From afb46f7996e91aeb36e07bc92cf96e8045bec00e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 2 Apr 2014 19:07:24 -0500 Subject: mips: ralink: convert to use unflatten_and_copy_device_tree The ralink FDT code can be simplified by using unflatten_and_copy_device_tree function. This removes all accesses to FDT header data by the arch code. Signed-off-by: Rob Herring Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Tested-by: Grant Likely --- arch/mips/ralink/of.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index eccc5526155e..0170d829d073 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -52,30 +52,7 @@ __iomem void *plat_of_remap_node(const char *node) void __init device_tree_init(void) { - unsigned long base, size; - void *fdt_copy; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_bootmem(base, size, BOOTMEM_DEFAULT); - - /* The strings in the flattened tree are referenced directly by the - * device tree, so copy the flattened device tree from init memory - * to regular memory. - */ - fdt_copy = alloc_bootmem(size); - memcpy(fdt_copy, initial_boot_params, size); - initial_boot_params = fdt_copy; - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_bootmem(base, size); + unflatten_and_copy_device_tree(); } void __init plat_mem_setup(void) -- cgit v1.2.3 From edba274cdeaa84e2cf8a9a34fe7583b0e01edbab Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 29 Apr 2014 13:16:50 -0500 Subject: powerpc: fix skipping call to early_init_fdt_scan_reserved_mem The call to early_init_fdt_scan_reserved_mem will be skipped if reserved-ranges is not found. Move the call earlier so that it is called unconditionally. Signed-off-by: Rob Herring Cc: Marek Szyprowski Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Tested-by: Stephen Chivers --- arch/powerpc/kernel/prom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 668aa4791fd7..d65754935652 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -567,6 +567,8 @@ static void __init early_reserve_mem_dt(void) unsigned long i, len, dt_root; const __be32 *prop; + early_init_fdt_scan_reserved_mem(); + dt_root = of_get_flat_dt_root(); prop = of_get_flat_dt_prop(dt_root, "reserved-ranges", &len); @@ -589,8 +591,6 @@ static void __init early_reserve_mem_dt(void) memblock_reserve(base, size); } } - - early_init_fdt_scan_reserved_mem(); } static void __init early_reserve_mem(void) -- cgit v1.2.3 From 1f809b4b1221f35cd2995b5605c006a8903c340c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 3 Apr 2014 13:13:46 -0500 Subject: ARM: dt: use default early_init_dt_alloc_memory_arch Now that ARM is using memblock instead of bootmem, the default version of early_init_dt_alloc_memory_arch can be used. Signed-off-by: Rob Herring Cc: Russell King Cc: linux-arm-kernel@lists.infradead.org Tested-by: Grant Likely --- arch/arm/kernel/devtree.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index c7419a585ddc..dff9cc0e9bd6 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -32,11 +32,6 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) arm_add_memory(base, size); } -void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) -{ - return memblock_virt_alloc(size, align); -} - void __init arm_dt_memblock_reserve(void) { u64 *reserve_map, base, size; -- cgit v1.2.3 From 01984a6f99cf1463a89592eff6e57af898743022 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 31 Mar 2014 15:09:34 -0500 Subject: c6x: convert fdt pointers to opaque pointers The architecture code does not need to access the internals of the FDT blob, so make the pointer to it void *. Signed-off-by: Rob Herring Cc: Mark Salter Cc: Aurelien Jacquiot Cc: linux-c6x-dev@linux-c6x.org Tested-by: Grant Likely --- arch/c6x/kernel/setup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/c6x/kernel/setup.c b/arch/c6x/kernel/setup.c index 731db4b9014d..757128868d43 100644 --- a/arch/c6x/kernel/setup.c +++ b/arch/c6x/kernel/setup.c @@ -265,8 +265,8 @@ int __init c6x_add_memory(phys_addr_t start, unsigned long size) */ notrace void __init machine_init(unsigned long dt_ptr) { - struct boot_param_header *dtb = __va(dt_ptr); - struct boot_param_header *fdt = (struct boot_param_header *)_fdt_start; + const void *dtb = __va(dt_ptr); + const void *fdt = _fdt_start; /* interrupts must be masked */ set_creg(IER, 2); -- cgit v1.2.3 From 0cdde839265d5f258b36b871b083324f62c1fbb9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 31 Mar 2014 15:13:07 -0500 Subject: mips: convert fdt pointers to opaque pointers The architecture code does not need to access the internals of the FDT blob directly, so make the pointers to it void * and use char arrays for section variables. Signed-off-by: Rob Herring Cc: Ralf Baechle Tested-by: Grant Likely --- arch/mips/include/asm/mips-boards/generic.h | 4 +--- arch/mips/include/asm/prom.h | 6 +++--- arch/mips/kernel/prom.c | 2 +- arch/mips/lantiq/prom.c | 2 +- arch/mips/lantiq/prom.h | 2 +- arch/mips/mti-sead3/sead3-setup.c | 8 ++++---- arch/mips/ralink/of.c | 4 ++-- 7 files changed, 13 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 48616816bcbc..b969491aa98d 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -67,9 +67,7 @@ extern int mips_revision_sconid; -#ifdef CONFIG_OF -extern struct boot_param_header __dtb_start; -#endif +extern char __dtb_start[]; #ifdef CONFIG_PCI extern void mips_pcibios_init(void); diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h index ccd2b75f152c..a9494c0141fb 100644 --- a/arch/mips/include/asm/prom.h +++ b/arch/mips/include/asm/prom.h @@ -21,13 +21,13 @@ extern void device_tree_init(void); struct boot_param_header; -extern void __dt_setup_arch(struct boot_param_header *bph); +extern void __dt_setup_arch(void *bph); #define dt_setup_arch(sym) \ ({ \ - extern struct boot_param_header __dtb_##sym##_begin; \ + extern char __dtb_##sym##_begin[]; \ \ - __dt_setup_arch(&__dtb_##sym##_begin); \ + __dt_setup_arch(__dtb_##sym##_begin); \ }) #else /* CONFIG_OF */ diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 3c3b0df8f48d..5d39bb85bf35 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -47,7 +47,7 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); } -void __init __dt_setup_arch(struct boot_param_header *bph) +void __init __dt_setup_arch(void *bph) { if (!early_init_dt_scan(bph)) return; diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index cdea687ad490..7447d322d14e 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -71,7 +71,7 @@ void __init plat_mem_setup(void) * Load the builtin devicetree. This causes the chosen node to be * parsed resulting in our memory appearing */ - __dt_setup_arch(&__dtb_start); + __dt_setup_arch(__dtb_start); } void __init device_tree_init(void) diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index 8e07b5f28ef1..69a4c582338d 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -26,6 +26,6 @@ struct ltq_soc_info { extern void ltq_soc_detect(struct ltq_soc_info *i); extern void ltq_soc_init(void); -extern struct boot_param_header __dtb_start; +extern char __dtb_start[]; #endif diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c index bf7fe48bf2f9..e43f4801a245 100644 --- a/arch/mips/mti-sead3/sead3-setup.c +++ b/arch/mips/mti-sead3/sead3-setup.c @@ -69,17 +69,17 @@ static void __init parse_memsize_param(void) if (!memsize) return; - offset = fdt_path_offset(&__dtb_start, "/memory"); + offset = fdt_path_offset(__dtb_start, "/memory"); if (offset > 0) { uint64_t new_value; /* * reg contains 2 32-bits BE values, offset and size. We just * want to replace the size value without affecting the offset */ - prop_value = fdt_getprop(&__dtb_start, offset, "reg", &prop_len); + prop_value = fdt_getprop(__dtb_start, offset, "reg", &prop_len); new_value = be64_to_cpu(*prop_value); new_value = (new_value & ~0xffffffffllu) | memsize; - fdt_setprop_inplace_u64(&__dtb_start, offset, "reg", new_value); + fdt_setprop_inplace_u64(__dtb_start, offset, "reg", new_value); } } @@ -92,7 +92,7 @@ void __init plat_mem_setup(void) * Load the builtin devicetree. This causes the chosen node to be * parsed resulting in our memory appearing */ - __dt_setup_arch(&__dtb_start); + __dt_setup_arch(__dtb_start); } void __init device_tree_init(void) diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 0170d829d073..91d7060d5aea 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -28,7 +28,7 @@ __iomem void *rt_sysc_membase; __iomem void *rt_memc_membase; -extern struct boot_param_header __dtb_start; +extern char __dtb_start[]; __iomem void *plat_of_remap_node(const char *node) { @@ -63,7 +63,7 @@ void __init plat_mem_setup(void) * Load the builtin devicetree. This causes the chosen node to be * parsed resulting in our memory appearing */ - __dt_setup_arch(&__dtb_start); + __dt_setup_arch(__dtb_start); if (soc_info.mem_size) add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M, -- cgit v1.2.3 From ccf3356e6b3d2802ea452c0091314605a9e7b7a0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 3 Apr 2014 13:38:32 -0500 Subject: of/fdt: consolidate built-in dtb section variables Unify the various architectures __dtb_start and __dtb_end definitions moving them into of_fdt.h. Signed-off-by: Rob Herring Acked-by: Vineet Gupta Acked-by: James Hogan Tested-by: Michal Simek Cc: Ralf Baechle Cc: Jonas Bonn Cc: Chris Zankel Cc: Max Filippov Cc: linux-metag@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux@lists.openrisc.net Cc: linux-xtensa@linux-xtensa.org Tested-by: Grant Likely Tested-by: Stephen Chivers --- arch/arc/include/asm/sections.h | 1 - arch/metag/kernel/setup.c | 4 ---- arch/mips/include/asm/mips-boards/generic.h | 2 -- arch/mips/lantiq/prom.h | 2 -- arch/mips/netlogic/xlp/dt.c | 2 +- arch/mips/ralink/of.c | 2 -- arch/openrisc/kernel/vmlinux.h | 2 -- arch/xtensa/kernel/setup.c | 1 - include/linux/of_fdt.h | 3 +++ 9 files changed, 4 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 764f1e3ba752..09db952e14bd 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -12,6 +12,5 @@ #include extern char __arc_dccm_base[]; -extern char __dtb_start[]; #endif diff --git a/arch/metag/kernel/setup.c b/arch/metag/kernel/setup.c index 129c7cdda1ce..31cf53d0eba2 100644 --- a/arch/metag/kernel/setup.c +++ b/arch/metag/kernel/setup.c @@ -105,10 +105,6 @@ extern char _heap_start[]; -#ifdef CONFIG_METAG_BUILTIN_DTB -extern u32 __dtb_start[]; -#endif - #ifdef CONFIG_DA_CONSOLE /* Our early channel based console driver */ extern struct console dash_console; diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index b969491aa98d..c904c24550f6 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -67,8 +67,6 @@ extern int mips_revision_sconid; -extern char __dtb_start[]; - #ifdef CONFIG_PCI extern void mips_pcibios_init(void); #else diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h index 69a4c582338d..bfd2d58c1d69 100644 --- a/arch/mips/lantiq/prom.h +++ b/arch/mips/lantiq/prom.h @@ -26,6 +26,4 @@ struct ltq_soc_info { extern void ltq_soc_detect(struct ltq_soc_info *i); extern void ltq_soc_init(void); -extern char __dtb_start[]; - #endif diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c index 7f9615a712fb..bdde33147bce 100644 --- a/arch/mips/netlogic/xlp/dt.c +++ b/arch/mips/netlogic/xlp/dt.c @@ -42,7 +42,7 @@ #include extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], - __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[], __dtb_start[]; + __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[]; static void *xlp_fdt_blob; void __init *xlp_dt_init(void *fdtp) diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 91d7060d5aea..251395210e23 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -28,8 +28,6 @@ __iomem void *rt_sysc_membase; __iomem void *rt_memc_membase; -extern char __dtb_start[]; - __iomem void *plat_of_remap_node(const char *node) { struct resource res; diff --git a/arch/openrisc/kernel/vmlinux.h b/arch/openrisc/kernel/vmlinux.h index 70b9ce41835c..bbcdf21b0b35 100644 --- a/arch/openrisc/kernel/vmlinux.h +++ b/arch/openrisc/kernel/vmlinux.h @@ -5,6 +5,4 @@ extern char __initrd_start, __initrd_end; #endif -extern u32 __dtb_start[]; - #endif diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 84fe931bb60e..89986e55d594 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -73,7 +73,6 @@ extern int initrd_below_start_ok; #endif #ifdef CONFIG_OF -extern u32 __dtb_start[]; void *dtb_start = __dtb_start; #endif diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index ddd7219af8ac..d4d0efe534b9 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -80,6 +80,9 @@ extern int __initdata dt_root_addr_cells; extern int __initdata dt_root_size_cells; extern struct boot_param_header *initial_boot_params; +extern char __dtb_start[]; +extern char __dtb_end[]; + /* For scanning the flat device-tree at boot time */ extern char *find_flat_dt_string(u32 offset); extern int of_scan_flat_dt(int (*it)(unsigned long node, const char *uname, -- cgit v1.2.3 From 9d0c4dfedd96ee54fc075b16d02f82499c8cc3a6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 1 Apr 2014 23:49:03 -0500 Subject: of/fdt: update of_get_flat_dt_prop in prep for libfdt Make of_get_flat_dt_prop arguments compatible with libfdt fdt_getprop call in preparation to convert FDT code to use libfdt. Make the return value const and the property length ptr type an int. Signed-off-by: Rob Herring Tested-by: Michal Simek Tested-by: Grant Likely Tested-by: Stephen Chivers --- arch/arc/kernel/devtree.c | 2 +- arch/arm/kernel/devtree.c | 2 +- arch/arm/mach-exynos/exynos.c | 2 +- arch/arm/mach-vexpress/platsmp.c | 2 +- arch/arm/plat-samsung/s5p-dev-mfc.c | 4 ++-- arch/microblaze/kernel/prom.c | 8 +++---- arch/powerpc/kernel/epapr_paravirt.c | 2 +- arch/powerpc/kernel/fadump.c | 4 ++-- arch/powerpc/kernel/prom.c | 24 +++++++++++---------- arch/powerpc/kernel/rtas.c | 2 +- arch/powerpc/mm/hash_utils_64.c | 22 +++++++++---------- arch/powerpc/platforms/52xx/efika.c | 4 ++-- arch/powerpc/platforms/chrp/setup.c | 4 ++-- arch/powerpc/platforms/powernv/opal.c | 12 +++++------ arch/powerpc/platforms/pseries/setup.c | 4 ++-- arch/xtensa/kernel/setup.c | 2 +- drivers/of/fdt.c | 39 +++++++++++++++++----------------- drivers/of/of_reserved_mem.c | 4 ++-- include/linux/of_fdt.h | 8 +++---- 19 files changed, 77 insertions(+), 74 deletions(-) (limited to 'arch') diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c index b6dc4e21fd32..0b3ef4025d89 100644 --- a/arch/arc/kernel/devtree.c +++ b/arch/arc/kernel/devtree.c @@ -42,7 +42,7 @@ const struct machine_desc * __init setup_machine_fdt(void *dt) const struct machine_desc *mdesc; unsigned long dt_root; void *clk; - unsigned long len; + int len; if (!early_init_dt_scan(dt)) return NULL; diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index dff9cc0e9bd6..38f4711b4995 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -247,7 +247,7 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) if (!mdesc) { const char *prop; - long size; + int size; unsigned long dt_root; early_print("\nError: unrecognized/unsupported " diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index b32a907d021d..77293d39dfc9 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -250,7 +250,7 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, { struct map_desc iodesc; __be32 *reg; - unsigned long len; + int len; if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") && !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock")) diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 993c9ae5dc5e..b4a5f0d8390d 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -53,7 +53,7 @@ static int __init vexpress_dt_find_scu(unsigned long node, { if (of_flat_dt_match(node, vexpress_dt_cortex_a9_match)) { phys_addr_t phys_addr; - __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL); + const __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL); if (WARN_ON(!reg)) return -EINVAL; diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c index 98087b655df0..469b86260fe3 100644 --- a/arch/arm/plat-samsung/s5p-dev-mfc.c +++ b/arch/arm/plat-samsung/s5p-dev-mfc.c @@ -125,8 +125,8 @@ device_initcall(s5p_mfc_memory_init); int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, int depth, void *data) { - __be32 *prop; - unsigned long len; + const __be32 *prop; + int len; struct s5p_mfc_dt_meminfo mfc_mem; if (!data) diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index abdfb10e7eca..c76630603058 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -43,13 +43,13 @@ #include #ifdef CONFIG_EARLY_PRINTK -static char *stdout; +static const char *stdout; static int __init early_init_dt_scan_chosen_serial(unsigned long node, const char *uname, int depth, void *data) { - unsigned long l; - char *p; + int l; + const char *p; pr_debug("%s: depth: %d, uname: %s\n", __func__, depth, uname); @@ -80,7 +80,7 @@ static int __init early_init_dt_scan_chosen_serial(unsigned long node, (strncmp(p, "xlnx,opb-uartlite", 17) == 0) || (strncmp(p, "xlnx,axi-uartlite", 17) == 0) || (strncmp(p, "xlnx,mdm", 8) == 0)) { - unsigned int *addrp; + const unsigned int *addrp; *(u32 *)data = UARTLITE; diff --git a/arch/powerpc/kernel/epapr_paravirt.c b/arch/powerpc/kernel/epapr_paravirt.c index 7898be90f2dc..d64e92b22dd8 100644 --- a/arch/powerpc/kernel/epapr_paravirt.c +++ b/arch/powerpc/kernel/epapr_paravirt.c @@ -36,7 +36,7 @@ static int __init early_init_dt_scan_epapr(unsigned long node, int depth, void *data) { const u32 *insts; - unsigned long len; + int len; int i; insts = of_get_flat_dt_prop(node, "hcall-instructions", &len); diff --git a/arch/powerpc/kernel/fadump.c b/arch/powerpc/kernel/fadump.c index 2230fd0ca3e4..7213d930918d 100644 --- a/arch/powerpc/kernel/fadump.c +++ b/arch/powerpc/kernel/fadump.c @@ -55,9 +55,9 @@ int crash_mem_ranges; int __init early_init_dt_scan_fw_dump(unsigned long node, const char *uname, int depth, void *data) { - __be32 *sections; + const __be32 *sections; int i, num_sections; - unsigned long size; + int size; const int *token; if (depth != 1 || strcmp(uname, "rtas") != 0) diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index d65754935652..483273e5c3e0 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -163,7 +163,7 @@ static struct ibm_pa_feature { {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0}, }; -static void __init scan_features(unsigned long node, unsigned char *ftrs, +static void __init scan_features(unsigned long node, const unsigned char *ftrs, unsigned long tablelen, struct ibm_pa_feature *fp, unsigned long ft_size) @@ -202,8 +202,8 @@ static void __init scan_features(unsigned long node, unsigned char *ftrs, static void __init check_cpu_pa_features(unsigned long node) { - unsigned char *pa_ftrs; - unsigned long tablelen; + const unsigned char *pa_ftrs; + int tablelen; pa_ftrs = of_get_flat_dt_prop(node, "ibm,pa-features", &tablelen); if (pa_ftrs == NULL) @@ -216,7 +216,7 @@ static void __init check_cpu_pa_features(unsigned long node) #ifdef CONFIG_PPC_STD_MMU_64 static void __init check_cpu_slb_size(unsigned long node) { - __be32 *slb_size_ptr; + const __be32 *slb_size_ptr; slb_size_ptr = of_get_flat_dt_prop(node, "slb-size", NULL); if (slb_size_ptr != NULL) { @@ -257,7 +257,7 @@ static struct feature_property { static inline void identical_pvr_fixup(unsigned long node) { unsigned int pvr; - char *model = of_get_flat_dt_prop(node, "model", NULL); + const char *model = of_get_flat_dt_prop(node, "model", NULL); /* * Since 440GR(x)/440EP(x) processors have the same pvr, @@ -295,11 +295,11 @@ static int __init early_init_dt_scan_cpus(unsigned long node, const char *uname, int depth, void *data) { - char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); const __be32 *prop; const __be32 *intserv; int i, nthreads; - unsigned long len; + int len; int found = -1; int found_thread = 0; @@ -392,7 +392,7 @@ static int __init early_init_dt_scan_cpus(unsigned long node, int __init early_init_dt_scan_chosen_ppc(unsigned long node, const char *uname, int depth, void *data) { - unsigned long *lprop; /* All these set by kernel, so no need to convert endian */ + const unsigned long *lprop; /* All these set by kernel, so no need to convert endian */ /* Use common scan routine to determine if this is the chosen node */ if (early_init_dt_scan_chosen(node, uname, depth, data) == 0) @@ -443,8 +443,9 @@ int __init early_init_dt_scan_chosen_ppc(unsigned long node, const char *uname, */ static int __init early_init_dt_scan_drconf_memory(unsigned long node) { - __be32 *dm, *ls, *usm; - unsigned long l, n, flags; + const __be32 *dm, *ls, *usm; + int l; + unsigned long n, flags; u64 base, size, memblock_size; unsigned int is_kexec_kdump = 0, rngs; @@ -564,7 +565,8 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) static void __init early_reserve_mem_dt(void) { - unsigned long i, len, dt_root; + unsigned long i, dt_root; + int len; const __be32 *prop; early_init_fdt_scan_reserved_mem(); diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index 8cd5ed049b5d..8b4c857c1421 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -1142,7 +1142,7 @@ void __init rtas_initialize(void) int __init early_init_dt_scan_rtas(unsigned long node, const char *uname, int depth, void *data) { - u32 *basep, *entryp, *sizep; + const u32 *basep, *entryp, *sizep; if (depth != 1 || strcmp(uname, "rtas") != 0) return 0; diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index d766d6ee33fe..59cc19a23a7a 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -265,9 +265,9 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node, const char *uname, int depth, void *data) { - char *type = of_get_flat_dt_prop(node, "device_type", NULL); - __be32 *prop; - unsigned long size = 0; + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const __be32 *prop; + int size = 0; /* We are scanning "cpu" nodes only */ if (type == NULL || strcmp(type, "cpu") != 0) @@ -320,9 +320,9 @@ static int __init htab_dt_scan_page_sizes(unsigned long node, const char *uname, int depth, void *data) { - char *type = of_get_flat_dt_prop(node, "device_type", NULL); - __be32 *prop; - unsigned long size = 0; + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const __be32 *prop; + int size = 0; /* We are scanning "cpu" nodes only */ if (type == NULL || strcmp(type, "cpu") != 0) @@ -402,9 +402,9 @@ static int __init htab_dt_scan_page_sizes(unsigned long node, static int __init htab_dt_scan_hugepage_blocks(unsigned long node, const char *uname, int depth, void *data) { - char *type = of_get_flat_dt_prop(node, "device_type", NULL); - __be64 *addr_prop; - __be32 *page_count_prop; + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const __be64 *addr_prop; + const __be32 *page_count_prop; unsigned int expected_pages; long unsigned int phys_addr; long unsigned int block_size; @@ -546,8 +546,8 @@ static int __init htab_dt_scan_pftsize(unsigned long node, const char *uname, int depth, void *data) { - char *type = of_get_flat_dt_prop(node, "device_type", NULL); - __be32 *prop; + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const __be32 *prop; /* We are scanning "cpu" nodes only */ if (type == NULL || strcmp(type, "cpu") != 0) diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c index 18c104820198..6e19b0ad5d26 100644 --- a/arch/powerpc/platforms/52xx/efika.c +++ b/arch/powerpc/platforms/52xx/efika.c @@ -199,8 +199,8 @@ static void __init efika_setup_arch(void) static int __init efika_probe(void) { - char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), - "model", NULL); + const char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), + "model", NULL); if (model == NULL) return 0; diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index c665d7de6c99..7044fd36197b 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c @@ -574,8 +574,8 @@ chrp_init2(void) static int __init chrp_probe(void) { - char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), - "device_type", NULL); + const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), + "device_type", NULL); if (dtype == NULL) return 0; if (strcmp(dtype, "chrp")) diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c index 49d2f00019e5..c1329846bfa3 100644 --- a/arch/powerpc/platforms/powernv/opal.c +++ b/arch/powerpc/platforms/powernv/opal.c @@ -61,7 +61,7 @@ int __init early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data) { const void *basep, *entryp, *sizep; - unsigned long basesz, entrysz, runtimesz; + int basesz, entrysz, runtimesz; if (depth != 1 || strcmp(uname, "ibm,opal") != 0) return 0; @@ -77,11 +77,11 @@ int __init early_init_dt_scan_opal(unsigned long node, opal.entry = of_read_number(entryp, entrysz/4); opal.size = of_read_number(sizep, runtimesz/4); - pr_debug("OPAL Base = 0x%llx (basep=%p basesz=%ld)\n", + pr_debug("OPAL Base = 0x%llx (basep=%p basesz=%d)\n", opal.base, basep, basesz); - pr_debug("OPAL Entry = 0x%llx (entryp=%p basesz=%ld)\n", + pr_debug("OPAL Entry = 0x%llx (entryp=%p basesz=%d)\n", opal.entry, entryp, entrysz); - pr_debug("OPAL Entry = 0x%llx (sizep=%p runtimesz=%ld)\n", + pr_debug("OPAL Entry = 0x%llx (sizep=%p runtimesz=%d)\n", opal.size, sizep, runtimesz); powerpc_firmware_features |= FW_FEATURE_OPAL; @@ -102,7 +102,7 @@ int __init early_init_dt_scan_opal(unsigned long node, int __init early_init_dt_scan_recoverable_ranges(unsigned long node, const char *uname, int depth, void *data) { - unsigned long i, psize, size; + int i, psize, size; const __be32 *prop; if (depth != 1 || strcmp(uname, "ibm,opal") != 0) @@ -359,7 +359,7 @@ int opal_get_chars(uint32_t vtermno, char *buf, int count) if ((be64_to_cpu(evt) & OPAL_EVENT_CONSOLE_INPUT) == 0) return 0; len = cpu_to_be64(count); - rc = opal_console_read(vtermno, &len, buf); + rc = opal_console_read(vtermno, &len, buf); if (rc == OPAL_SUCCESS) return be64_to_cpu(len); return 0; diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 2db8cc691bf4..099d2df976a2 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -665,7 +665,7 @@ static int __init pseries_probe_fw_features(unsigned long node, void *data) { const char *prop; - unsigned long len; + int len; static int hypertas_found; static int vec5_found; @@ -698,7 +698,7 @@ static int __init pseries_probe_fw_features(unsigned long node, static int __init pSeries_probe(void) { unsigned long root = of_get_flat_dt_root(); - char *dtype = of_get_flat_dt_prop(root, "device_type", NULL); + const char *dtype = of_get_flat_dt_prop(root, "device_type", NULL); if (dtype == NULL) return 0; diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 89986e55d594..1991a3d0b2f8 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -220,7 +220,7 @@ static int __init xtensa_dt_io_area(unsigned long node, const char *uname, int depth, void *data) { const __be32 *ranges; - unsigned long len; + int len; if (depth > 1) return 0; diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 9c8535291909..1d1582bb81fb 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -35,7 +35,7 @@ char *of_fdt_get_string(struct boot_param_header *blob, u32 offset) */ void *of_fdt_get_property(struct boot_param_header *blob, unsigned long node, const char *name, - unsigned long *size) + int *size) { unsigned long p = node; @@ -85,7 +85,8 @@ int of_fdt_is_compatible(struct boot_param_header *blob, unsigned long node, const char *compat) { const char *cp; - unsigned long cplen, l, score = 0; + int cplen; + unsigned long l, score = 0; cp = of_fdt_get_property(blob, node, "compatible", &cplen); if (cp == NULL) @@ -444,8 +445,8 @@ static int __init __reserved_mem_reserve_reg(unsigned long node, { int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32); phys_addr_t base, size; - unsigned long len; - __be32 *prop; + int len; + const __be32 *prop; int nomap, first = 1; prop = of_get_flat_dt_prop(node, "reg", &len); @@ -488,7 +489,7 @@ static int __init __reserved_mem_reserve_reg(unsigned long node, */ static int __init __reserved_mem_check_root(unsigned long node) { - __be32 *prop; + const __be32 *prop; prop = of_get_flat_dt_prop(node, "#size-cells", NULL); if (!prop || be32_to_cpup(prop) != dt_root_size_cells) @@ -638,8 +639,8 @@ unsigned long __init of_get_flat_dt_root(void) * This function can be used within scan_flattened_dt callback to get * access to properties */ -void *__init of_get_flat_dt_prop(unsigned long node, const char *name, - unsigned long *size) +const void *__init of_get_flat_dt_prop(unsigned long node, const char *name, + int *size) { return of_fdt_get_property(initial_boot_params, node, name, size); } @@ -710,7 +711,7 @@ const void * __init of_flat_dt_match_machine(const void *default_match, } if (!best_data) { const char *prop; - long size; + int size; pr_err("\n unrecognized device tree list:\n[ "); @@ -739,8 +740,8 @@ const void * __init of_flat_dt_match_machine(const void *default_match, static void __init early_init_dt_check_for_initrd(unsigned long node) { u64 start, end; - unsigned long len; - __be32 *prop; + int len; + const __be32 *prop; pr_debug("Looking for initrd properties... "); @@ -773,7 +774,7 @@ static inline void early_init_dt_check_for_initrd(unsigned long node) int __init early_init_dt_scan_root(unsigned long node, const char *uname, int depth, void *data) { - __be32 *prop; + const __be32 *prop; if (depth != 0) return 0; @@ -795,9 +796,9 @@ int __init early_init_dt_scan_root(unsigned long node, const char *uname, return 1; } -u64 __init dt_mem_next_cell(int s, __be32 **cellp) +u64 __init dt_mem_next_cell(int s, const __be32 **cellp) { - __be32 *p = *cellp; + const __be32 *p = *cellp; *cellp = p + s; return of_read_number(p, s); @@ -809,9 +810,9 @@ u64 __init dt_mem_next_cell(int s, __be32 **cellp) int __init early_init_dt_scan_memory(unsigned long node, const char *uname, int depth, void *data) { - char *type = of_get_flat_dt_prop(node, "device_type", NULL); - __be32 *reg, *endp; - unsigned long l; + const char *type = of_get_flat_dt_prop(node, "device_type", NULL); + const __be32 *reg, *endp; + int l; /* We are scanning "memory" nodes only */ if (type == NULL) { @@ -832,7 +833,7 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname, endp = reg + (l / sizeof(__be32)); - pr_debug("memory scan node %s, reg size %ld, data: %x %x %x %x,\n", + pr_debug("memory scan node %s, reg size %d, data: %x %x %x %x,\n", uname, l, reg[0], reg[1], reg[2], reg[3]); while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { @@ -855,8 +856,8 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname, int __init early_init_dt_scan_chosen(unsigned long node, const char *uname, int depth, void *data) { - unsigned long l; - char *p; + int l; + const char *p; pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname); diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c index daaaf935911d..e420eb52e5c9 100644 --- a/drivers/of/of_reserved_mem.c +++ b/drivers/of/of_reserved_mem.c @@ -95,8 +95,8 @@ static int __init __reserved_mem_alloc_size(unsigned long node, int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32); phys_addr_t start = 0, end = 0; phys_addr_t base = 0, align = 0, size; - unsigned long len; - __be32 *prop; + int len; + const __be32 *prop; int nomap; int ret; diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index 991ec74b4e11..b36a50d6af37 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -66,7 +66,7 @@ extern char *of_fdt_get_string(struct boot_param_header *blob, u32 offset); extern void *of_fdt_get_property(struct boot_param_header *blob, unsigned long node, const char *name, - unsigned long *size); + int *size); extern int of_fdt_is_compatible(struct boot_param_header *blob, unsigned long node, const char *compat); @@ -88,8 +88,8 @@ extern char *find_flat_dt_string(u32 offset); extern int of_scan_flat_dt(int (*it)(unsigned long node, const char *uname, int depth, void *data), void *data); -extern void *of_get_flat_dt_prop(unsigned long node, const char *name, - unsigned long *size); +extern const void *of_get_flat_dt_prop(unsigned long node, const char *name, + int *size); extern int of_flat_dt_is_compatible(unsigned long node, const char *name); extern int of_flat_dt_match(unsigned long node, const char *const *matches); extern unsigned long of_get_flat_dt_root(void); @@ -103,7 +103,7 @@ extern void early_init_dt_add_memory_arch(u64 base, u64 size); extern int early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size, bool no_map); extern void * early_init_dt_alloc_memory_arch(u64 size, u64 align); -extern u64 dt_mem_next_cell(int s, __be32 **cellp); +extern u64 dt_mem_next_cell(int s, const __be32 **cellp); /* Early flat tree scan hooks */ extern int early_init_dt_scan_root(unsigned long node, const char *uname, -- cgit v1.2.3 From b0a6fb36a49f720c93c3da0b3f040e49e42435ad Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 2 Apr 2014 16:56:48 -0500 Subject: of/fdt: create common debugfs Both powerpc and microblaze have the same FDT blob in debugfs feature. Move this to common location and remove the powerpc and microblaze implementations. This feature could become more useful when FDT overlay support is added. This changes the path of the blob from "$arch/flat-device-tree" to "device-tree/flat-device-tree". Signed-off-by: Rob Herring Tested-by: Michal Simek Cc: Michal Simek Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Tested-by: Grant Likely Tested-by: Stephen Chivers --- arch/microblaze/kernel/prom.c | 31 ------------------------------- arch/powerpc/kernel/prom.c | 21 --------------------- drivers/of/fdt.c | 24 ++++++++++++++++++++++++ 3 files changed, 24 insertions(+), 52 deletions(-) (limited to 'arch') diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c index c76630603058..68f099960ebc 100644 --- a/arch/microblaze/kernel/prom.c +++ b/arch/microblaze/kernel/prom.c @@ -114,34 +114,3 @@ void __init early_init_devtree(void *params) pr_debug(" <- early_init_devtree()\n"); } - -/******* - * - * New implementation of the OF "find" APIs, return a refcounted - * object, call of_node_put() when done. The device tree and list - * are protected by a rw_lock. - * - * Note that property management will need some locking as well, - * this isn't dealt with yet. - * - *******/ - -#if defined(CONFIG_DEBUG_FS) && defined(DEBUG) -static struct debugfs_blob_wrapper flat_dt_blob; - -static int __init export_flat_device_tree(void) -{ - struct dentry *d; - - flat_dt_blob.data = initial_boot_params; - flat_dt_blob.size = initial_boot_params->totalsize; - - d = debugfs_create_blob("flat-device-tree", S_IFREG | S_IRUSR, - of_debugfs_root, &flat_dt_blob); - if (!d) - return 1; - - return 0; -} -device_initcall(export_flat_device_tree); -#endif diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 483273e5c3e0..e5e2b6f63567 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -924,23 +923,3 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id) { return (int)phys_id == get_hard_smp_processor_id(cpu); } - -#if defined(CONFIG_DEBUG_FS) && defined(DEBUG) -static struct debugfs_blob_wrapper flat_dt_blob; - -static int __init export_flat_device_tree(void) -{ - struct dentry *d; - - flat_dt_blob.data = initial_boot_params; - flat_dt_blob.size = be32_to_cpu(initial_boot_params->totalsize); - - d = debugfs_create_blob("flat-device-tree", S_IFREG | S_IRUSR, - powerpc_debugfs_root, &flat_dt_blob); - if (!d) - return 1; - - return 0; -} -__initcall(export_flat_device_tree); -#endif diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 0b38a6aa8603..4129f7442244 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -20,6 +20,7 @@ #include #include #include +#include #include /* for COMMAND_LINE_SIZE */ #include @@ -916,4 +917,27 @@ void __init unflatten_and_copy_device_tree(void) unflatten_device_tree(); } +#if defined(CONFIG_DEBUG_FS) && defined(DEBUG) +static struct debugfs_blob_wrapper flat_dt_blob; + +static int __init of_flat_dt_debugfs_export_fdt(void) +{ + struct dentry *d = debugfs_create_dir("device-tree", NULL); + + if (!d) + return -ENOENT; + + flat_dt_blob.data = initial_boot_params; + flat_dt_blob.size = fdt_totalsize(initial_boot_params); + + d = debugfs_create_blob("flat-device-tree", S_IFREG | S_IRUSR, + d, &flat_dt_blob); + if (!d) + return -ENOENT; + + return 0; +} +module_init(of_flat_dt_debugfs_export_fdt); +#endif + #endif /* CONFIG_OF_EARLY_FLATTREE */ -- cgit v1.2.3 From d1552ce449eb0a8d2f0bd6599da3a8a3d7f77a84 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 1 Apr 2014 22:46:48 -0500 Subject: of/fdt: move memreserve and dtb memory reservations into core Move the /memreserve/ processing and dtb memory reservations into early_init_fdt_scan_reserved_mem. This converts arm, arm64, and powerpc as they are the only users of early_init_fdt_scan_reserved_mem. memblock_reserve is safe to call on the same region twice, so the reservation check for the dtb in powerpc 32-bit reservations is safe to remove. Signed-off-by: Rob Herring Tested-by: Michal Simek Cc: Russell King Cc: Catalin Marinas Cc: Will Deacon Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Tested-by: Grant Likely Tested-by: Stephen Chivers --- arch/arm/include/asm/prom.h | 2 -- arch/arm/kernel/devtree.c | 27 --------------------------- arch/arm/mm/init.c | 1 - arch/arm64/mm/init.c | 21 --------------------- arch/powerpc/kernel/prom.c | 22 ---------------------- drivers/of/fdt.c | 16 ++++++++++++++++ 6 files changed, 16 insertions(+), 73 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h index b681575ad3de..cd94ef2ef283 100644 --- a/arch/arm/include/asm/prom.h +++ b/arch/arm/include/asm/prom.h @@ -14,7 +14,6 @@ #ifdef CONFIG_OF extern const struct machine_desc *setup_machine_fdt(unsigned int dt_phys); -extern void arm_dt_memblock_reserve(void); extern void __init arm_dt_init_cpu_maps(void); #else /* CONFIG_OF */ @@ -24,7 +23,6 @@ static inline const struct machine_desc *setup_machine_fdt(unsigned int dt_phys) return NULL; } -static inline void arm_dt_memblock_reserve(void) { } static inline void arm_dt_init_cpu_maps(void) { } #endif /* CONFIG_OF */ diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 38f4711b4995..3e5a2056a466 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -32,33 +32,6 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) arm_add_memory(base, size); } -void __init arm_dt_memblock_reserve(void) -{ - u64 *reserve_map, base, size; - - if (!initial_boot_params) - return; - - /* Reserve the dtb region */ - memblock_reserve(virt_to_phys(initial_boot_params), - be32_to_cpu(initial_boot_params->totalsize)); - - /* - * Process the reserve map. This will probably overlap the initrd - * and dtb locations which are already reserved, but overlaping - * doesn't hurt anything - */ - reserve_map = ((void*)initial_boot_params) + - be32_to_cpu(initial_boot_params->off_mem_rsvmap); - while (1) { - base = be64_to_cpup(reserve_map++); - size = be64_to_cpup(reserve_map++); - if (!size) - break; - memblock_reserve(base, size); - } -} - #ifdef CONFIG_SMP extern struct of_cpu_method __cpu_method_of_table_begin[]; extern struct of_cpu_method __cpu_method_of_table_end[]; diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 2a77ba8796ae..928d596d9ab4 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -317,7 +317,6 @@ void __init arm_memblock_init(struct meminfo *mi, #endif arm_mm_memblock_reserve(); - arm_dt_memblock_reserve(); /* reserve any platform specific memblock areas */ if (mdesc->reserve) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 51d5352e6ad5..091d428d64ac 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -126,8 +126,6 @@ static void arm64_memory_present(void) void __init arm64_memblock_init(void) { - u64 *reserve_map, base, size; - /* Register the kernel text, kernel data and initrd with memblock */ memblock_reserve(__pa(_text), _end - _text); #ifdef CONFIG_BLK_DEV_INITRD @@ -142,25 +140,6 @@ void __init arm64_memblock_init(void) memblock_reserve(__pa(swapper_pg_dir), SWAPPER_DIR_SIZE); memblock_reserve(__pa(idmap_pg_dir), IDMAP_DIR_SIZE); - /* Reserve the dtb region */ - memblock_reserve(virt_to_phys(initial_boot_params), - be32_to_cpu(initial_boot_params->totalsize)); - - /* - * Process the reserve map. This will probably overlap the initrd - * and dtb locations which are already reserved, but overlapping - * doesn't hurt anything - */ - reserve_map = ((void*)initial_boot_params) + - be32_to_cpu(initial_boot_params->off_mem_rsvmap); - while (1) { - base = be64_to_cpup(reserve_map++); - size = be64_to_cpup(reserve_map++); - if (!size) - break; - memblock_reserve(base, size); - } - early_init_fdt_scan_reserved_mem(); dma_contiguous_reserve(0); diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index e5e2b6f63567..73b7e9b45054 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -596,19 +596,11 @@ static void __init early_reserve_mem_dt(void) static void __init early_reserve_mem(void) { - u64 base, size; __be64 *reserve_map; - unsigned long self_base; - unsigned long self_size; reserve_map = (__be64 *)(((unsigned long)initial_boot_params) + be32_to_cpu(initial_boot_params->off_mem_rsvmap)); - /* before we do anything, lets reserve the dt blob */ - self_base = __pa((unsigned long)initial_boot_params); - self_size = be32_to_cpu(initial_boot_params->totalsize); - memblock_reserve(self_base, self_size); - /* Look for the new "reserved-regions" property in the DT */ early_reserve_mem_dt(); @@ -637,26 +629,12 @@ static void __init early_reserve_mem(void) size_32 = be32_to_cpup(reserve_map_32++); if (size_32 == 0) break; - /* skip if the reservation is for the blob */ - if (base_32 == self_base && size_32 == self_size) - continue; DBG("reserving: %x -> %x\n", base_32, size_32); memblock_reserve(base_32, size_32); } return; } #endif - DBG("Processing reserve map\n"); - - /* Handle the reserve map in the fdt blob if it exists */ - while (1) { - base = be64_to_cpup(reserve_map++); - size = be64_to_cpup(reserve_map++); - if (size == 0) - break; - DBG("reserving: %llx -> %llx\n", base, size); - memblock_reserve(base, size); - } } void __init early_init_devtree(void *params) diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 4129f7442244..051be4ca25b9 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -492,9 +492,25 @@ static int __init __fdt_scan_reserved_mem(unsigned long node, const char *uname, */ void __init early_init_fdt_scan_reserved_mem(void) { + int n; + u64 base, size; + if (!initial_boot_params) return; + /* Reserve the dtb region */ + early_init_dt_reserve_memory_arch(__pa(initial_boot_params), + fdt_totalsize(initial_boot_params), + 0); + + /* Process header /memreserve/ fields */ + for (n = 0; ; n++) { + fdt_get_mem_rsv(initial_boot_params, n, &base, &size); + if (!size) + break; + early_init_dt_reserve_memory_arch(base, size, 0); + } + of_scan_flat_dt(__fdt_scan_reserved_mem, NULL); fdt_init_reserved_mem(); } -- cgit v1.2.3 From 060f78c2543a890626cab81796b0d6f7070bd989 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 31 Mar 2014 15:15:00 -0500 Subject: powerpc: use libfdt accessors for header data With libfdt support, we can take advantage of helper accessors in libfdt for accessing the FDT header data. This makes the code more readable and makes the FDT blob structure more opaque to the kernel. This also prepares for removing struct boot_param_header completely. Signed-off-by: Rob Herring Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Tested-by: Grant Likely Tested-by: Stephen Chivers --- arch/powerpc/kernel/Makefile | 1 + arch/powerpc/kernel/prom.c | 11 ++++++----- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index fcc9a89a4695..fab19ec25597 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -2,6 +2,7 @@ # Makefile for the linux kernel. # +CFLAGS_prom.o = -I$(src)/../../../scripts/dtc/libfdt CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"' subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 73b7e9b45054..613a860a203c 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -117,14 +118,14 @@ static void __init move_device_tree(void) DBG("-> move_device_tree\n"); start = __pa(initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); + size = fdt_totalsize(initial_boot_params); if ((memory_limit && (start + size) > PHYSICAL_START + memory_limit) || overlaps_crashkernel(start, size) || overlaps_initrd(start, size)) { p = __va(memblock_alloc(size, PAGE_SIZE)); memcpy(p, initial_boot_params, size); - initial_boot_params = (struct boot_param_header *)p; + initial_boot_params = p; DBG("Moved device tree to 0x%p\n", p); } @@ -324,9 +325,9 @@ static int __init early_init_dt_scan_cpus(unsigned long node, * version 2 of the kexec param format adds the phys cpuid of * booted proc. */ - if (be32_to_cpu(initial_boot_params->version) >= 2) { + if (fdt_version(initial_boot_params) >= 2) { if (be32_to_cpu(intserv[i]) == - be32_to_cpu(initial_boot_params->boot_cpuid_phys)) { + fdt_boot_cpuid_phys(initial_boot_params)) { found = boot_cpu_count; found_thread = i; } @@ -599,7 +600,7 @@ static void __init early_reserve_mem(void) __be64 *reserve_map; reserve_map = (__be64 *)(((unsigned long)initial_boot_params) + - be32_to_cpu(initial_boot_params->off_mem_rsvmap)); + fdt_off_mem_rsvmap(initial_boot_params)); /* Look for the new "reserved-regions" property in the DT */ early_reserve_mem_dt(); -- cgit v1.2.3 From 1bac1869947ee3866c6d687b99e4283d37bb499b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 31 Mar 2014 15:17:31 -0500 Subject: x86: use FDT accessors for FDT blob header data Remove the direct accesses to FDT header data using accessor function instead. This makes the code more readable and makes the FDT blob structure more opaque to the arch code. This also prepares for removing struct boot_param_header completely. Signed-off-by: Rob Herring Cc: Thomas Gleixner Cc: Ingo Molnar Cc: "H. Peter Anvin" Cc: x86@kernel.org Tested-by: Grant Likely --- arch/x86/kernel/devicetree.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index d35078ea1446..7db54b5d5f86 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -206,23 +206,21 @@ static void __init dtb_apic_setup(void) static void __init x86_flattree_get_config(void) { u32 size, map_len; - struct boot_param_header *dt; + void *dt; if (!initial_dtb) return; - map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), - (u64)sizeof(struct boot_param_header)); + map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128); - dt = early_memremap(initial_dtb, map_len); - size = be32_to_cpu(dt->totalsize); + initial_boot_params = dt = early_memremap(initial_dtb, map_len); + size = of_get_flat_dt_size(); if (map_len < size) { early_iounmap(dt, map_len); - dt = early_memremap(initial_dtb, size); + initial_boot_params = dt = early_memremap(initial_dtb, size); map_len = size; } - initial_boot_params = dt; unflatten_and_copy_device_tree(); early_iounmap(dt, map_len); } -- cgit v1.2.3 From c3fc952d2fbe3ec78defd70cf73d5d76d27092ec Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 1 Apr 2014 22:55:14 -0500 Subject: of: push struct boot_param_header and defines into powerpc Now powerpc is the only user of struct boot_param_header and FDT defines, so they can be moved into the powerpc architecture code. Signed-off-by: Rob Herring Acked-by: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Tested-by: Grant Likely Tested-by: Stephen Chivers --- arch/powerpc/include/asm/prom.h | 39 +++++++++++++++++++++++++++++++++++++++ include/linux/of_fdt.h | 37 ------------------------------------- 2 files changed, 39 insertions(+), 37 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h index d977b9b78696..74b79f07f041 100644 --- a/arch/powerpc/include/asm/prom.h +++ b/arch/powerpc/include/asm/prom.h @@ -26,6 +26,45 @@ #include #include +#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */ +#define OF_DT_END_NODE 0x2 /* End node */ +#define OF_DT_PROP 0x3 /* Property: name off, size, + * content */ +#define OF_DT_NOP 0x4 /* nop */ +#define OF_DT_END 0x9 + +#define OF_DT_VERSION 0x10 + +/* + * This is what gets passed to the kernel by prom_init or kexec + * + * The dt struct contains the device tree structure, full pathes and + * property contents. The dt strings contain a separate block with just + * the strings for the property names, and is fully page aligned and + * self contained in a page, so that it can be kept around by the kernel, + * each property name appears only once in this page (cheap compression) + * + * the mem_rsvmap contains a map of reserved ranges of physical memory, + * passing it here instead of in the device-tree itself greatly simplifies + * the job of everybody. It's just a list of u64 pairs (base/size) that + * ends when size is 0 + */ +struct boot_param_header { + __be32 magic; /* magic word OF_DT_HEADER */ + __be32 totalsize; /* total size of DT block */ + __be32 off_dt_struct; /* offset to structure */ + __be32 off_dt_strings; /* offset to strings */ + __be32 off_mem_rsvmap; /* offset to memory reserve map */ + __be32 version; /* format version */ + __be32 last_comp_version; /* last compatible version */ + /* version 2 fields below */ + __be32 boot_cpuid_phys; /* Physical CPU id we're booting on */ + /* version 3 fields below */ + __be32 dt_strings_size; /* size of the DT strings block */ + /* version 17 fields below */ + __be32 dt_struct_size; /* size of the DT structure block */ +}; + /* * OF address retreival & translation */ diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index 1f882e1da728..5c0ab057eecf 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -17,45 +17,8 @@ /* Definitions used by the flattened device tree */ #define OF_DT_HEADER 0xd00dfeed /* marker */ -#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */ -#define OF_DT_END_NODE 0x2 /* End node */ -#define OF_DT_PROP 0x3 /* Property: name off, size, - * content */ -#define OF_DT_NOP 0x4 /* nop */ -#define OF_DT_END 0x9 - -#define OF_DT_VERSION 0x10 #ifndef __ASSEMBLY__ -/* - * This is what gets passed to the kernel by prom_init or kexec - * - * The dt struct contains the device tree structure, full pathes and - * property contents. The dt strings contain a separate block with just - * the strings for the property names, and is fully page aligned and - * self contained in a page, so that it can be kept around by the kernel, - * each property name appears only once in this page (cheap compression) - * - * the mem_rsvmap contains a map of reserved ranges of physical memory, - * passing it here instead of in the device-tree itself greatly simplifies - * the job of everybody. It's just a list of u64 pairs (base/size) that - * ends when size is 0 - */ -struct boot_param_header { - __be32 magic; /* magic word OF_DT_HEADER */ - __be32 totalsize; /* total size of DT block */ - __be32 off_dt_struct; /* offset to structure */ - __be32 off_dt_strings; /* offset to strings */ - __be32 off_mem_rsvmap; /* offset to memory reserve map */ - __be32 version; /* format version */ - __be32 last_comp_version; /* last compatible version */ - /* version 2 fields below */ - __be32 boot_cpuid_phys; /* Physical CPU id we're booting on */ - /* version 3 fields below */ - __be32 dt_strings_size; /* size of the DT strings block */ - /* version 17 fields below */ - __be32 dt_struct_size; /* size of the DT structure block */ -}; #if defined(CONFIG_OF_FLATTREE) -- cgit v1.2.3 From 7d0f84aae9e231930985eaff63ac91b61aaa15d6 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:16 +0530 Subject: ARM/ARM64: KVM: Add base for PSCI v0.2 emulation Currently, the in-kernel PSCI emulation provides PSCI v0.1 interface to VCPUs. This patch extends current in-kernel PSCI emulation to provide PSCI v0.2 interface to VCPUs. By default, ARM/ARM64 KVM will always provide PSCI v0.1 interface for keeping the ABI backward-compatible. To select PSCI v0.2 interface for VCPUs, the user space (i.e. QEMU or KVMTOOL) will have to set KVM_ARM_VCPU_PSCI_0_2 feature when doing VCPU init using KVM_ARM_VCPU_INIT ioctl. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Acked-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_host.h | 2 +- arch/arm/include/asm/kvm_psci.h | 4 ++ arch/arm/include/uapi/asm/kvm.h | 10 +++-- arch/arm/kvm/psci.c | 93 ++++++++++++++++++++++++++++++++------- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/include/asm/kvm_psci.h | 4 ++ arch/arm64/include/uapi/asm/kvm.h | 10 +++-- 7 files changed, 99 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 09af14999c9b..193ceaf01bfd 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -36,7 +36,7 @@ #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 #define KVM_HAVE_ONE_REG -#define KVM_VCPU_MAX_FEATURES 1 +#define KVM_VCPU_MAX_FEATURES 2 #include diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h index 9a83d98bf170..4c0e3e1d1597 100644 --- a/arch/arm/include/asm/kvm_psci.h +++ b/arch/arm/include/asm/kvm_psci.h @@ -18,6 +18,10 @@ #ifndef __ARM_KVM_PSCI_H__ #define __ARM_KVM_PSCI_H__ +#define KVM_ARM_PSCI_0_1 1 +#define KVM_ARM_PSCI_0_2 2 + +int kvm_psci_version(struct kvm_vcpu *vcpu); bool kvm_psci_call(struct kvm_vcpu *vcpu); #endif /* __ARM_KVM_PSCI_H__ */ diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h index ef0c8785ba16..e6ebdd3471e5 100644 --- a/arch/arm/include/uapi/asm/kvm.h +++ b/arch/arm/include/uapi/asm/kvm.h @@ -20,6 +20,7 @@ #define __ARM_KVM_H__ #include +#include #include #define __KVM_HAVE_GUEST_DEBUG @@ -83,6 +84,7 @@ struct kvm_regs { #define KVM_VGIC_V2_CPU_SIZE 0x2000 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ +#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */ struct kvm_vcpu_init { __u32 target; @@ -201,9 +203,9 @@ struct kvm_arch_memory_slot { #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) -#define KVM_PSCI_RET_SUCCESS 0 -#define KVM_PSCI_RET_NI ((unsigned long)-1) -#define KVM_PSCI_RET_INVAL ((unsigned long)-2) -#define KVM_PSCI_RET_DENIED ((unsigned long)-3) +#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS +#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED +#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS +#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED #endif /* __ARM_KVM_H__ */ diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 448f60e8d23c..8c42596cdbdf 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -59,7 +59,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) * turned off. */ if (!vcpu || !vcpu->arch.pause) - return KVM_PSCI_RET_INVAL; + return PSCI_RET_INVALID_PARAMS; target_pc = *vcpu_reg(source_vcpu, 2); @@ -82,20 +82,60 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) wq = kvm_arch_vcpu_wq(vcpu); wake_up_interruptible(wq); - return KVM_PSCI_RET_SUCCESS; + return PSCI_RET_SUCCESS; } -/** - * kvm_psci_call - handle PSCI call if r0 value is in range - * @vcpu: Pointer to the VCPU struct - * - * Handle PSCI calls from guests through traps from HVC instructions. - * The calling convention is similar to SMC calls to the secure world where - * the function number is placed in r0 and this function returns true if the - * function number specified in r0 is withing the PSCI range, and false - * otherwise. - */ -bool kvm_psci_call(struct kvm_vcpu *vcpu) +int kvm_psci_version(struct kvm_vcpu *vcpu) +{ + if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) + return KVM_ARM_PSCI_0_2; + + return KVM_ARM_PSCI_0_1; +} + +static bool kvm_psci_0_2_call(struct kvm_vcpu *vcpu) +{ + unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0); + unsigned long val; + + switch (psci_fn) { + case PSCI_0_2_FN_PSCI_VERSION: + /* + * Bits[31:16] = Major Version = 0 + * Bits[15:0] = Minor Version = 2 + */ + val = 2; + break; + case PSCI_0_2_FN_CPU_OFF: + kvm_psci_vcpu_off(vcpu); + val = PSCI_RET_SUCCESS; + break; + case PSCI_0_2_FN_CPU_ON: + case PSCI_0_2_FN64_CPU_ON: + val = kvm_psci_vcpu_on(vcpu); + break; + case PSCI_0_2_FN_CPU_SUSPEND: + case PSCI_0_2_FN_AFFINITY_INFO: + case PSCI_0_2_FN_MIGRATE: + case PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: + case PSCI_0_2_FN_SYSTEM_OFF: + case PSCI_0_2_FN_SYSTEM_RESET: + case PSCI_0_2_FN64_CPU_SUSPEND: + case PSCI_0_2_FN64_AFFINITY_INFO: + case PSCI_0_2_FN64_MIGRATE: + case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU: + val = PSCI_RET_NOT_SUPPORTED; + break; + default: + return false; + } + + *vcpu_reg(vcpu, 0) = val; + return true; +} + +static bool kvm_psci_0_1_call(struct kvm_vcpu *vcpu) { unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0); unsigned long val; @@ -103,16 +143,15 @@ bool kvm_psci_call(struct kvm_vcpu *vcpu) switch (psci_fn) { case KVM_PSCI_FN_CPU_OFF: kvm_psci_vcpu_off(vcpu); - val = KVM_PSCI_RET_SUCCESS; + val = PSCI_RET_SUCCESS; break; case KVM_PSCI_FN_CPU_ON: val = kvm_psci_vcpu_on(vcpu); break; case KVM_PSCI_FN_CPU_SUSPEND: case KVM_PSCI_FN_MIGRATE: - val = KVM_PSCI_RET_NI; + val = PSCI_RET_NOT_SUPPORTED; break; - default: return false; } @@ -120,3 +159,25 @@ bool kvm_psci_call(struct kvm_vcpu *vcpu) *vcpu_reg(vcpu, 0) = val; return true; } + +/** + * kvm_psci_call - handle PSCI call if r0 value is in range + * @vcpu: Pointer to the VCPU struct + * + * Handle PSCI calls from guests through traps from HVC instructions. + * The calling convention is similar to SMC calls to the secure world where + * the function number is placed in r0 and this function returns true if the + * function number specified in r0 is withing the PSCI range, and false + * otherwise. + */ +bool kvm_psci_call(struct kvm_vcpu *vcpu) +{ + switch (kvm_psci_version(vcpu)) { + case KVM_ARM_PSCI_0_2: + return kvm_psci_0_2_call(vcpu); + case KVM_ARM_PSCI_0_1: + return kvm_psci_0_1_call(vcpu); + default: + return false; + }; +} diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 0a1d69751562..92242ce06309 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -39,7 +39,7 @@ #include #include -#define KVM_VCPU_MAX_FEATURES 2 +#define KVM_VCPU_MAX_FEATURES 3 struct kvm_vcpu; int kvm_target_cpu(void); diff --git a/arch/arm64/include/asm/kvm_psci.h b/arch/arm64/include/asm/kvm_psci.h index e301a4816355..e25c658a757b 100644 --- a/arch/arm64/include/asm/kvm_psci.h +++ b/arch/arm64/include/asm/kvm_psci.h @@ -18,6 +18,10 @@ #ifndef __ARM64_KVM_PSCI_H__ #define __ARM64_KVM_PSCI_H__ +#define KVM_ARM_PSCI_0_1 1 +#define KVM_ARM_PSCI_0_2 2 + +int kvm_psci_version(struct kvm_vcpu *vcpu); bool kvm_psci_call(struct kvm_vcpu *vcpu); #endif /* __ARM64_KVM_PSCI_H__ */ diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index eaf54a30bedc..e6471daf3fb5 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -31,6 +31,7 @@ #define KVM_NR_SPSR 5 #ifndef __ASSEMBLY__ +#include #include #include @@ -77,6 +78,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ +#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ struct kvm_vcpu_init { __u32 target; @@ -186,10 +188,10 @@ struct kvm_arch_memory_slot { #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) -#define KVM_PSCI_RET_SUCCESS 0 -#define KVM_PSCI_RET_NI ((unsigned long)-1) -#define KVM_PSCI_RET_INVAL ((unsigned long)-2) -#define KVM_PSCI_RET_DENIED ((unsigned long)-3) +#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS +#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED +#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS +#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED #endif -- cgit v1.2.3 From e8e7fcc5e2710b31ef842ee799db99c07986c364 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:18 +0530 Subject: ARM/ARM64: KVM: Make kvm_psci_call() return convention more flexible Currently, the kvm_psci_call() returns 'true' or 'false' based on whether the PSCI function call was handled successfully or not. This does not help us emulate system-level PSCI functions where the actual emulation work will be done by user space (QEMU or KVMTOOL). Examples of such system-level PSCI functions are: PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET. This patch updates kvm_psci_call() to return three types of values: 1) > 0 (success) 2) = 0 (success but exit to user space) 3) < 0 (errors) Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Reviewed-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/include/asm/kvm_psci.h | 2 +- arch/arm/kvm/handle_exit.c | 10 +++++++--- arch/arm/kvm/psci.c | 28 ++++++++++++++++------------ arch/arm64/include/asm/kvm_psci.h | 2 +- arch/arm64/kvm/handle_exit.c | 10 +++++++--- 5 files changed, 32 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h index 4c0e3e1d1597..6bda945d31fa 100644 --- a/arch/arm/include/asm/kvm_psci.h +++ b/arch/arm/include/asm/kvm_psci.h @@ -22,6 +22,6 @@ #define KVM_ARM_PSCI_0_2 2 int kvm_psci_version(struct kvm_vcpu *vcpu); -bool kvm_psci_call(struct kvm_vcpu *vcpu); +int kvm_psci_call(struct kvm_vcpu *vcpu); #endif /* __ARM_KVM_PSCI_H__ */ diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c index 0de91fc6de0f..4c979d466cc1 100644 --- a/arch/arm/kvm/handle_exit.c +++ b/arch/arm/kvm/handle_exit.c @@ -38,14 +38,18 @@ static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run) static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) { + int ret; + trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0), kvm_vcpu_hvc_get_imm(vcpu)); - if (kvm_psci_call(vcpu)) + ret = kvm_psci_call(vcpu); + if (ret < 0) { + kvm_inject_undefined(vcpu); return 1; + } - kvm_inject_undefined(vcpu); - return 1; + return ret; } static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 8c42596cdbdf..14e6fa6c8e35 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -93,7 +93,7 @@ int kvm_psci_version(struct kvm_vcpu *vcpu) return KVM_ARM_PSCI_0_1; } -static bool kvm_psci_0_2_call(struct kvm_vcpu *vcpu) +static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) { unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0); unsigned long val; @@ -128,14 +128,14 @@ static bool kvm_psci_0_2_call(struct kvm_vcpu *vcpu) val = PSCI_RET_NOT_SUPPORTED; break; default: - return false; + return -EINVAL; } *vcpu_reg(vcpu, 0) = val; - return true; + return 1; } -static bool kvm_psci_0_1_call(struct kvm_vcpu *vcpu) +static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) { unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0); unsigned long val; @@ -153,11 +153,11 @@ static bool kvm_psci_0_1_call(struct kvm_vcpu *vcpu) val = PSCI_RET_NOT_SUPPORTED; break; default: - return false; + return -EINVAL; } *vcpu_reg(vcpu, 0) = val; - return true; + return 1; } /** @@ -165,12 +165,16 @@ static bool kvm_psci_0_1_call(struct kvm_vcpu *vcpu) * @vcpu: Pointer to the VCPU struct * * Handle PSCI calls from guests through traps from HVC instructions. - * The calling convention is similar to SMC calls to the secure world where - * the function number is placed in r0 and this function returns true if the - * function number specified in r0 is withing the PSCI range, and false - * otherwise. + * The calling convention is similar to SMC calls to the secure world + * where the function number is placed in r0. + * + * This function returns: > 0 (success), 0 (success but exit to user + * space), and < 0 (errors) + * + * Errors: + * -EINVAL: Unrecognized PSCI function */ -bool kvm_psci_call(struct kvm_vcpu *vcpu) +int kvm_psci_call(struct kvm_vcpu *vcpu) { switch (kvm_psci_version(vcpu)) { case KVM_ARM_PSCI_0_2: @@ -178,6 +182,6 @@ bool kvm_psci_call(struct kvm_vcpu *vcpu) case KVM_ARM_PSCI_0_1: return kvm_psci_0_1_call(vcpu); default: - return false; + return -EINVAL; }; } diff --git a/arch/arm64/include/asm/kvm_psci.h b/arch/arm64/include/asm/kvm_psci.h index e25c658a757b..bc39e557c56c 100644 --- a/arch/arm64/include/asm/kvm_psci.h +++ b/arch/arm64/include/asm/kvm_psci.h @@ -22,6 +22,6 @@ #define KVM_ARM_PSCI_0_2 2 int kvm_psci_version(struct kvm_vcpu *vcpu); -bool kvm_psci_call(struct kvm_vcpu *vcpu); +int kvm_psci_call(struct kvm_vcpu *vcpu); #endif /* __ARM64_KVM_PSCI_H__ */ diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 7bc41eab4c64..182415e1a952 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -30,11 +30,15 @@ typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *); static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run) { - if (kvm_psci_call(vcpu)) + int ret; + + ret = kvm_psci_call(vcpu); + if (ret < 0) { + kvm_inject_undefined(vcpu); return 1; + } - kvm_inject_undefined(vcpu); - return 1; + return ret; } static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run) -- cgit v1.2.3 From 4b1238269ed340d59ef829fd9c30a39cfb2923a8 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:20 +0530 Subject: ARM/ARM64: KVM: Emulate PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET The PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET functions are system-level functions hence cannot be fully emulated by in-kernel PSCI emulation code. To tackle this, we forward PSCI v0.2 SYSTEM_OFF and SYSTEM_RESET function calls from vcpu to user space (i.e. QEMU or KVMTOOL) via kvm_run structure using KVM_EXIT_SYSTEM_EVENT exit reasons. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Reviewed-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/psci.c | 46 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 14e6fa6c8e35..59362131b79f 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -85,6 +85,23 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) return PSCI_RET_SUCCESS; } +static void kvm_prepare_system_event(struct kvm_vcpu *vcpu, u32 type) +{ + memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event)); + vcpu->run->system_event.type = type; + vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; +} + +static void kvm_psci_system_off(struct kvm_vcpu *vcpu) +{ + kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_SHUTDOWN); +} + +static void kvm_psci_system_reset(struct kvm_vcpu *vcpu) +{ + kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_RESET); +} + int kvm_psci_version(struct kvm_vcpu *vcpu) { if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features)) @@ -95,6 +112,7 @@ int kvm_psci_version(struct kvm_vcpu *vcpu) static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) { + int ret = 1; unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0); unsigned long val; @@ -114,13 +132,35 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) case PSCI_0_2_FN64_CPU_ON: val = kvm_psci_vcpu_on(vcpu); break; + case PSCI_0_2_FN_SYSTEM_OFF: + kvm_psci_system_off(vcpu); + /* + * We should'nt be going back to guest VCPU after + * receiving SYSTEM_OFF request. + * + * If user space accidently/deliberately resumes + * guest VCPU after SYSTEM_OFF request then guest + * VCPU should see internal failure from PSCI return + * value. To achieve this, we preload r0 (or x0) with + * PSCI return value INTERNAL_FAILURE. + */ + val = PSCI_RET_INTERNAL_FAILURE; + ret = 0; + break; + case PSCI_0_2_FN_SYSTEM_RESET: + kvm_psci_system_reset(vcpu); + /* + * Same reason as SYSTEM_OFF for preloading r0 (or x0) + * with PSCI return value INTERNAL_FAILURE. + */ + val = PSCI_RET_INTERNAL_FAILURE; + ret = 0; + break; case PSCI_0_2_FN_CPU_SUSPEND: case PSCI_0_2_FN_AFFINITY_INFO: case PSCI_0_2_FN_MIGRATE: case PSCI_0_2_FN_MIGRATE_INFO_TYPE: case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: - case PSCI_0_2_FN_SYSTEM_OFF: - case PSCI_0_2_FN_SYSTEM_RESET: case PSCI_0_2_FN64_CPU_SUSPEND: case PSCI_0_2_FN64_AFFINITY_INFO: case PSCI_0_2_FN64_MIGRATE: @@ -132,7 +172,7 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) } *vcpu_reg(vcpu, 0) = val; - return 1; + return ret; } static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu) -- cgit v1.2.3 From e6bc13c8a70eabc6a39098ccedf6129c734e3db3 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:21 +0530 Subject: ARM/ARM64: KVM: Emulate PSCI v0.2 AFFINITY_INFO This patch adds emulation of PSCI v0.2 AFFINITY_INFO function call for KVM ARM/ARM64. This is a VCPU-level function call which will be used to determine current state of given affinity level. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Reviewed-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/psci.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 59362131b79f..3b6a0cf25c7d 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -27,6 +27,16 @@ * as described in ARM document number ARM DEN 0022A. */ +#define AFFINITY_MASK(level) ~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1) + +static unsigned long psci_affinity_mask(unsigned long affinity_level) +{ + if (affinity_level <= 3) + return MPIDR_HWID_BITMASK & AFFINITY_MASK(affinity_level); + + return 0; +} + static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu) { vcpu->arch.pause = true; @@ -85,6 +95,42 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) return PSCI_RET_SUCCESS; } +static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu) +{ + int i; + unsigned long mpidr; + unsigned long target_affinity; + unsigned long target_affinity_mask; + unsigned long lowest_affinity_level; + struct kvm *kvm = vcpu->kvm; + struct kvm_vcpu *tmp; + + target_affinity = *vcpu_reg(vcpu, 1); + lowest_affinity_level = *vcpu_reg(vcpu, 2); + + /* Determine target affinity mask */ + target_affinity_mask = psci_affinity_mask(lowest_affinity_level); + if (!target_affinity_mask) + return PSCI_RET_INVALID_PARAMS; + + /* Ignore other bits of target affinity */ + target_affinity &= target_affinity_mask; + + /* + * If one or more VCPU matching target affinity are running + * then ON else OFF + */ + kvm_for_each_vcpu(i, tmp, kvm) { + mpidr = kvm_vcpu_get_mpidr(tmp); + if (((mpidr & target_affinity_mask) == target_affinity) && + !tmp->arch.pause) { + return PSCI_0_2_AFFINITY_LEVEL_ON; + } + } + + return PSCI_0_2_AFFINITY_LEVEL_OFF; +} + static void kvm_prepare_system_event(struct kvm_vcpu *vcpu, u32 type) { memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event)); @@ -132,6 +178,10 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) case PSCI_0_2_FN64_CPU_ON: val = kvm_psci_vcpu_on(vcpu); break; + case PSCI_0_2_FN_AFFINITY_INFO: + case PSCI_0_2_FN64_AFFINITY_INFO: + val = kvm_psci_vcpu_affinity_info(vcpu); + break; case PSCI_0_2_FN_SYSTEM_OFF: kvm_psci_system_off(vcpu); /* @@ -157,12 +207,10 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) ret = 0; break; case PSCI_0_2_FN_CPU_SUSPEND: - case PSCI_0_2_FN_AFFINITY_INFO: case PSCI_0_2_FN_MIGRATE: case PSCI_0_2_FN_MIGRATE_INFO_TYPE: case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: case PSCI_0_2_FN64_CPU_SUSPEND: - case PSCI_0_2_FN64_AFFINITY_INFO: case PSCI_0_2_FN64_MIGRATE: case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU: val = PSCI_RET_NOT_SUPPORTED; -- cgit v1.2.3 From bab0b43012a8ad64877fa46134370a7f5c6ce861 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:22 +0530 Subject: ARM/ARM64: KVM: Emulate PSCI v0.2 MIGRATE_INFO_TYPE and related functions This patch adds emulation of PSCI v0.2 MIGRATE, MIGRATE_INFO_TYPE, and MIGRATE_INFO_UP_CPU function calls for KVM ARM/ARM64. KVM ARM/ARM64 being a hypervisor (and not a Trusted OS), we cannot provide this functions hence we emulate these functions in following way: 1. MIGRATE - Returns "Not Supported" 2. MIGRATE_INFO_TYPE - Return 2 i.e. Trusted OS is not present 3. MIGRATE_INFO_UP_CPU - Returns "Not Supported" Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Reviewed-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/psci.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 3b6a0cf25c7d..cce901a510fa 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -182,6 +182,22 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) case PSCI_0_2_FN64_AFFINITY_INFO: val = kvm_psci_vcpu_affinity_info(vcpu); break; + case PSCI_0_2_FN_MIGRATE: + case PSCI_0_2_FN64_MIGRATE: + val = PSCI_RET_NOT_SUPPORTED; + break; + case PSCI_0_2_FN_MIGRATE_INFO_TYPE: + /* + * Trusted OS is MP hence does not require migration + * or + * Trusted OS is not present + */ + val = PSCI_0_2_TOS_MP; + break; + case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: + case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU: + val = PSCI_RET_NOT_SUPPORTED; + break; case PSCI_0_2_FN_SYSTEM_OFF: kvm_psci_system_off(vcpu); /* @@ -207,12 +223,7 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) ret = 0; break; case PSCI_0_2_FN_CPU_SUSPEND: - case PSCI_0_2_FN_MIGRATE: - case PSCI_0_2_FN_MIGRATE_INFO_TYPE: - case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU: case PSCI_0_2_FN64_CPU_SUSPEND: - case PSCI_0_2_FN64_MIGRATE: - case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU: val = PSCI_RET_NOT_SUPPORTED; break; default: -- cgit v1.2.3 From aa8aeefe5e567637bbec7d7a3031cc057e3af303 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:23 +0530 Subject: ARM/ARM64: KVM: Fix CPU_ON emulation for PSCI v0.2 As-per PSCI v0.2, the source CPU provides physical address of "entry point" and "context id" for starting a target CPU. Also, if target CPU is already running then we should return ALREADY_ON. Current emulation of CPU_ON function does not consider physical address of "context id" and returns INVALID_PARAMETERS if target CPU is already running. This patch updates kvm_psci_vcpu_on() such that it works for both PSCI v0.1 and PSCI v0.2. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Reviewed-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/psci.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index cce901a510fa..1067579c7336 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -48,6 +48,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) struct kvm_vcpu *vcpu = NULL, *tmp; wait_queue_head_t *wq; unsigned long cpu_id; + unsigned long context_id; unsigned long mpidr; phys_addr_t target_pc; int i; @@ -68,10 +69,17 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) * Make sure the caller requested a valid CPU and that the CPU is * turned off. */ - if (!vcpu || !vcpu->arch.pause) + if (!vcpu) return PSCI_RET_INVALID_PARAMS; + if (!vcpu->arch.pause) { + if (kvm_psci_version(source_vcpu) != KVM_ARM_PSCI_0_1) + return PSCI_RET_ALREADY_ON; + else + return PSCI_RET_INVALID_PARAMS; + } target_pc = *vcpu_reg(source_vcpu, 2); + context_id = *vcpu_reg(source_vcpu, 3); kvm_reset_vcpu(vcpu); @@ -86,6 +94,11 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu) kvm_vcpu_set_be(vcpu); *vcpu_pc(vcpu) = target_pc; + /* + * NOTE: We always update r0 (or x0) because for PSCI v0.1 + * the general puspose registers are undefined upon CPU_ON. + */ + *vcpu_reg(vcpu, 0) = context_id; vcpu->arch.pause = false; smp_mb(); /* Make sure the above is visible */ -- cgit v1.2.3 From b376d02b53b87f8684f91f13ba4ee43331850fcd Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:24 +0530 Subject: ARM/ARM64: KVM: Emulate PSCI v0.2 CPU_SUSPEND This patch adds emulation of PSCI v0.2 CPU_SUSPEND function call for KVM ARM/ARM64. This is a CPU-level function call which can suspend current CPU or current CPU cluster. We don't have VCPU clusters in KVM so we only suspend the current VCPU. The CPU_SUSPEND emulation is not tested much because currently there is no CPUIDLE driver in Linux kernel that uses PSCI CPU_SUSPEND. The PSCI CPU_SUSPEND implementation in ARM64 kernel was tested using a Simple CPUIDLE driver which is not published due to unstable DT-bindings for PSCI. (For more info, http://lwn.net/Articles/574950/) For simplicity, we implement CPU_SUSPEND emulation similar to WFI (Wait-for-interrupt) emulation and we also treat power-down request to be same as stand-by request. This is consistent with section 5.4.1 and section 5.4.2 of PSCI v0.2 specification. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Acked-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/psci.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c index 1067579c7336..09cf37737ee2 100644 --- a/arch/arm/kvm/psci.c +++ b/arch/arm/kvm/psci.c @@ -37,6 +37,26 @@ static unsigned long psci_affinity_mask(unsigned long affinity_level) return 0; } +static unsigned long kvm_psci_vcpu_suspend(struct kvm_vcpu *vcpu) +{ + /* + * NOTE: For simplicity, we make VCPU suspend emulation to be + * same-as WFI (Wait-for-interrupt) emulation. + * + * This means for KVM the wakeup events are interrupts and + * this is consistent with intended use of StateID as described + * in section 5.4.1 of PSCI v0.2 specification (ARM DEN 0022A). + * + * Further, we also treat power-down request to be same as + * stand-by request as-per section 5.4.2 clause 3 of PSCI v0.2 + * specification (ARM DEN 0022A). This means all suspend states + * for KVM will preserve the register state. + */ + kvm_vcpu_block(vcpu); + + return PSCI_RET_SUCCESS; +} + static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu) { vcpu->arch.pause = true; @@ -183,6 +203,10 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) */ val = 2; break; + case PSCI_0_2_FN_CPU_SUSPEND: + case PSCI_0_2_FN64_CPU_SUSPEND: + val = kvm_psci_vcpu_suspend(vcpu); + break; case PSCI_0_2_FN_CPU_OFF: kvm_psci_vcpu_off(vcpu); val = PSCI_RET_SUCCESS; @@ -235,10 +259,6 @@ static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu) val = PSCI_RET_INTERNAL_FAILURE; ret = 0; break; - case PSCI_0_2_FN_CPU_SUSPEND: - case PSCI_0_2_FN64_CPU_SUSPEND: - val = PSCI_RET_NOT_SUPPORTED; - break; default: return -EINVAL; } -- cgit v1.2.3 From 4447a208f7fc2e2dff8c6a8df2a1fd6dd72fb3e2 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Tue, 29 Apr 2014 11:24:25 +0530 Subject: ARM/ARM64: KVM: Advertise KVM_CAP_ARM_PSCI_0_2 to user space We have PSCI v0.2 emulation available in KVM ARM/ARM64 hence advertise this to user space (i.e. QEMU or KVMTOOL) via KVM_CHECK_EXTENSION ioctl. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Acked-by: Christoffer Dall Acked-by: Marc Zyngier Signed-off-by: Christoffer Dall --- arch/arm/kvm/arm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index f0e50a0f3a65..3c82b37c0f9e 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -197,6 +197,7 @@ int kvm_dev_ioctl_check_extension(long ext) case KVM_CAP_DESTROY_MEMORY_REGION_WORKS: case KVM_CAP_ONE_REG: case KVM_CAP_ARM_PSCI: + case KVM_CAP_ARM_PSCI_0_2: r = 1; break; case KVM_CAP_COALESCED_MMIO: -- cgit v1.2.3 From 971232cf7c7a71ad3cbf433f592eee3ae1a578ac Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Mon, 28 Apr 2014 16:34:11 +0300 Subject: usb: phy: msm: Replace custom enum usb_mode_type with enum usb_dr_mode Use enum usb_dr_mode and drop default usb_dr_mode from platform data. USB DT bindings states: dr_mode: "...In case this attribute isn't passed via DT, USB DRD controllers should default to OTG...", so remove redundand field. Signed-off-by: Ivan T. Ivanov Acked-by: David Brown Signed-off-by: Felipe Balbi --- arch/arm/mach-msm/board-msm7x30.c | 2 +- arch/arm/mach-msm/board-qsd8x50.c | 2 +- drivers/usb/phy/phy-msm-usb.c | 41 ++++++++++++++++----------------------- include/linux/usb/msm_hsusb.h | 20 +------------------ 4 files changed, 20 insertions(+), 45 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index 46de789ad3ae..0c4c200e1221 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -95,7 +95,7 @@ static int hsusb_phy_clk_reset(struct clk *phy_clk) static struct msm_otg_platform_data msm_otg_pdata = { .phy_init_seq = hsusb_phy_init_seq, - .mode = USB_PERIPHERAL, + .mode = USB_DR_MODE_PERIPHERAL, .otg_control = OTG_PHY_CONTROL, .link_clk_reset = hsusb_link_clk_reset, .phy_clk_reset = hsusb_phy_clk_reset, diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index 9169ec324a43..4c748616ef47 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -116,7 +116,7 @@ static int hsusb_phy_clk_reset(struct clk *phy_clk) static struct msm_otg_platform_data msm_otg_pdata = { .phy_init_seq = hsusb_phy_init_seq, - .mode = USB_PERIPHERAL, + .mode = USB_DR_MODE_PERIPHERAL, .otg_control = OTG_PHY_CONTROL, .link_clk_reset = hsusb_link_clk_reset, .phy_clk_reset = hsusb_phy_clk_reset, diff --git a/drivers/usb/phy/phy-msm-usb.c b/drivers/usb/phy/phy-msm-usb.c index 874c51a85683..7eb2abf3f874 100644 --- a/drivers/usb/phy/phy-msm-usb.c +++ b/drivers/usb/phy/phy-msm-usb.c @@ -348,10 +348,10 @@ static int msm_otg_reset(struct usb_phy *phy) if (pdata->otg_control == OTG_PHY_CONTROL) { val = readl(USB_OTGSC); - if (pdata->mode == USB_OTG) { + if (pdata->mode == USB_DR_MODE_OTG) { ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; val |= OTGSC_IDIE | OTGSC_BSVIE; - } else if (pdata->mode == USB_PERIPHERAL) { + } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) { ulpi_val = ULPI_INT_SESS_VALID; val |= OTGSC_BSVIE; } @@ -637,7 +637,7 @@ static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) * Fail host registration if this board can support * only peripheral configuration. */ - if (motg->pdata->mode == USB_PERIPHERAL) { + if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) { dev_info(otg->phy->dev, "Host mode is not supported\n"); return -ENODEV; } @@ -666,7 +666,7 @@ static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) * Kick the state machine work, if peripheral is not supported * or peripheral is already registered with us. */ - if (motg->pdata->mode == USB_HOST || otg->gadget) { + if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) { pm_runtime_get_sync(otg->phy->dev); schedule_work(&motg->sm_work); } @@ -710,7 +710,7 @@ static int msm_otg_set_peripheral(struct usb_otg *otg, * Fail peripheral registration if this board can support * only host configuration. */ - if (motg->pdata->mode == USB_HOST) { + if (motg->pdata->mode == USB_DR_MODE_HOST) { dev_info(otg->phy->dev, "Peripheral mode is not supported\n"); return -ENODEV; } @@ -735,7 +735,7 @@ static int msm_otg_set_peripheral(struct usb_otg *otg, * Kick the state machine work, if host is not supported * or host is already registered with us. */ - if (motg->pdata->mode == USB_PERIPHERAL || otg->host) { + if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) { pm_runtime_get_sync(otg->phy->dev); schedule_work(&motg->sm_work); } @@ -1056,7 +1056,7 @@ static void msm_otg_init_sm(struct msm_otg *motg) u32 otgsc = readl(USB_OTGSC); switch (pdata->mode) { - case USB_OTG: + case USB_DR_MODE_OTG: if (pdata->otg_control == OTG_PHY_CONTROL) { if (otgsc & OTGSC_ID) set_bit(ID, &motg->inputs); @@ -1068,21 +1068,14 @@ static void msm_otg_init_sm(struct msm_otg *motg) else clear_bit(B_SESS_VLD, &motg->inputs); } else if (pdata->otg_control == OTG_USER_CONTROL) { - if (pdata->default_mode == USB_HOST) { - clear_bit(ID, &motg->inputs); - } else if (pdata->default_mode == USB_PERIPHERAL) { - set_bit(ID, &motg->inputs); - set_bit(B_SESS_VLD, &motg->inputs); - } else { set_bit(ID, &motg->inputs); clear_bit(B_SESS_VLD, &motg->inputs); - } } break; - case USB_HOST: + case USB_DR_MODE_HOST: clear_bit(ID, &motg->inputs); break; - case USB_PERIPHERAL: + case USB_DR_MODE_PERIPHERAL: set_bit(ID, &motg->inputs); if (otgsc & OTGSC_BSV) set_bit(B_SESS_VLD, &motg->inputs); @@ -1258,7 +1251,7 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, char buf[16]; struct usb_otg *otg = motg->phy.otg; int status = count; - enum usb_mode_type req_mode; + enum usb_dr_mode req_mode; memset(buf, 0x00, sizeof(buf)); @@ -1268,18 +1261,18 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, } if (!strncmp(buf, "host", 4)) { - req_mode = USB_HOST; + req_mode = USB_DR_MODE_HOST; } else if (!strncmp(buf, "peripheral", 10)) { - req_mode = USB_PERIPHERAL; + req_mode = USB_DR_MODE_PERIPHERAL; } else if (!strncmp(buf, "none", 4)) { - req_mode = USB_NONE; + req_mode = USB_DR_MODE_UNKNOWN; } else { status = -EINVAL; goto out; } switch (req_mode) { - case USB_NONE: + case USB_DR_MODE_UNKNOWN: switch (otg->phy->state) { case OTG_STATE_A_HOST: case OTG_STATE_B_PERIPHERAL: @@ -1290,7 +1283,7 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, goto out; } break; - case USB_PERIPHERAL: + case USB_DR_MODE_PERIPHERAL: switch (otg->phy->state) { case OTG_STATE_B_IDLE: case OTG_STATE_A_HOST: @@ -1301,7 +1294,7 @@ static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, goto out; } break; - case USB_HOST: + case USB_DR_MODE_HOST: switch (otg->phy->state) { case OTG_STATE_B_IDLE: case OTG_STATE_B_PERIPHERAL: @@ -1511,7 +1504,7 @@ static int msm_otg_probe(struct platform_device *pdev) platform_set_drvdata(pdev, motg); device_init_wakeup(&pdev->dev, 1); - if (motg->pdata->mode == USB_OTG && + if (motg->pdata->mode == USB_DR_MODE_OTG && motg->pdata->otg_control == OTG_USER_CONTROL) { ret = msm_otg_debugfs_init(motg); if (ret) diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h index 8705b0164684..72c5830455bf 100644 --- a/include/linux/usb/msm_hsusb.h +++ b/include/linux/usb/msm_hsusb.h @@ -22,21 +22,6 @@ #include #include -/** - * Supported USB modes - * - * USB_PERIPHERAL Only peripheral mode is supported. - * USB_HOST Only host mode is supported. - * USB_OTG OTG mode is supported. - * - */ -enum usb_mode_type { - USB_NONE = 0, - USB_PERIPHERAL, - USB_HOST, - USB_OTG, -}; - /** * OTG control * @@ -121,8 +106,6 @@ enum usb_chg_type { * @power_budget: VBUS power budget in mA (0 will be treated as 500mA). * @mode: Supported mode (OTG/peripheral/host). * @otg_control: OTG switch controlled by user/Id pin - * @default_mode: Default operational mode. Applicable only if - * OTG switch is controller by user. * @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k * dfab_usb_hs_clk in case of 8660 and 8960. */ @@ -130,9 +113,8 @@ struct msm_otg_platform_data { int *phy_init_seq; void (*vbus_power)(bool on); unsigned power_budget; - enum usb_mode_type mode; + enum usb_dr_mode mode; enum otg_control_type otg_control; - enum usb_mode_type default_mode; enum msm_usb_phy_type phy_type; void (*setup_gpio)(enum usb_otg_state state); char *pclk_src_name; -- cgit v1.2.3 From d7ecbddf4caefbac1b99478dd2b679f83dfc2545 Mon Sep 17 00:00:00 2001 From: Mark Salter Date: Wed, 12 Mar 2014 12:28:06 -0400 Subject: arm64: Add function to create identity mappings At boot time, before switching to a virtual UEFI memory map, firmware expects UEFI memory and IO regions to be identity mapped whenever kernel makes runtime services calls. The existing early boot code creates an identity map of kernel text/data but this is not sufficient for UEFI. This patch adds a create_id_mapping() function which reuses the core code of the existing create_mapping(). Signed-off-by: Mark Salter [ Fixed error message formatting (%pa). ] Signed-off-by: Mark Rutland Signed-off-by: Leif Lindholm Acked-by: Catalin Marinas Signed-off-by: Matt Fleming --- arch/arm64/include/asm/mmu.h | 2 ++ arch/arm64/mm/mmu.c | 65 ++++++++++++++++++++++++++++++++------------ 2 files changed, 49 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index f600d400c07d..29ed1d865e13 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -28,5 +28,7 @@ extern void paging_init(void); extern void setup_mm_for_reboot(void); extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); extern void init_mem_pgprot(void); +/* create an identity mapping for memory (or io if map_io is true) */ +extern void create_id_mapping(phys_addr_t addr, phys_addr_t size, int map_io); #endif diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 6b7e89569a3a..971eb45e8bda 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -168,7 +168,8 @@ static void __init *early_alloc(unsigned long sz) } static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, - unsigned long end, unsigned long pfn) + unsigned long end, unsigned long pfn, + pgprot_t prot) { pte_t *pte; @@ -180,16 +181,28 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, pte = pte_offset_kernel(pmd, addr); do { - set_pte(pte, pfn_pte(pfn, PAGE_KERNEL_EXEC)); + set_pte(pte, pfn_pte(pfn, prot)); pfn++; } while (pte++, addr += PAGE_SIZE, addr != end); } static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, - unsigned long end, phys_addr_t phys) + unsigned long end, phys_addr_t phys, + int map_io) { pmd_t *pmd; unsigned long next; + pmdval_t prot_sect; + pgprot_t prot_pte; + + if (map_io) { + prot_sect = PMD_TYPE_SECT | PMD_SECT_AF | + PMD_ATTRINDX(MT_DEVICE_nGnRE); + prot_pte = __pgprot(PROT_DEVICE_nGnRE); + } else { + prot_sect = prot_sect_kernel; + prot_pte = PAGE_KERNEL_EXEC; + } /* * Check for initial section mappings in the pgd/pud and remove them. @@ -205,7 +218,7 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, /* try section mapping first */ if (((addr | next | phys) & ~SECTION_MASK) == 0) { pmd_t old_pmd =*pmd; - set_pmd(pmd, __pmd(phys | prot_sect_kernel)); + set_pmd(pmd, __pmd(phys | prot_sect)); /* * Check for previous table entries created during * boot (__create_page_tables) and flush them. @@ -213,21 +226,23 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, if (!pmd_none(old_pmd)) flush_tlb_all(); } else { - alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys)); + alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys), + prot_pte); } phys += next - addr; } while (pmd++, addr = next, addr != end); } static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, - unsigned long end, unsigned long phys) + unsigned long end, unsigned long phys, + int map_io) { pud_t *pud = pud_offset(pgd, addr); unsigned long next; do { next = pud_addr_end(addr, end); - alloc_init_pmd(pud, addr, next, phys); + alloc_init_pmd(pud, addr, next, phys, map_io); phys += next - addr; } while (pud++, addr = next, addr != end); } @@ -236,30 +251,44 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, * Create the page directory entries and any necessary page tables for the * mapping specified by 'md'. */ -static void __init create_mapping(phys_addr_t phys, unsigned long virt, - phys_addr_t size) +static void __init __create_mapping(pgd_t *pgd, phys_addr_t phys, + unsigned long virt, phys_addr_t size, + int map_io) { unsigned long addr, length, end, next; - pgd_t *pgd; - - if (virt < VMALLOC_START) { - pr_warning("BUG: not creating mapping for 0x%016llx at 0x%016lx - outside kernel range\n", - phys, virt); - return; - } addr = virt & PAGE_MASK; length = PAGE_ALIGN(size + (virt & ~PAGE_MASK)); - pgd = pgd_offset_k(addr); end = addr + length; do { next = pgd_addr_end(addr, end); - alloc_init_pud(pgd, addr, next, phys); + alloc_init_pud(pgd, addr, next, phys, map_io); phys += next - addr; } while (pgd++, addr = next, addr != end); } +static void __init create_mapping(phys_addr_t phys, unsigned long virt, + phys_addr_t size) +{ + if (virt < VMALLOC_START) { + pr_warn("BUG: not creating mapping for %pa at 0x%016lx - outside kernel range\n", + &phys, virt); + return; + } + __create_mapping(pgd_offset_k(virt & PAGE_MASK), phys, virt, size, 0); +} + +void __init create_id_mapping(phys_addr_t addr, phys_addr_t size, int map_io) +{ + if ((addr >> PGDIR_SHIFT) >= ARRAY_SIZE(idmap_pg_dir)) { + pr_warn("BUG: not creating id mapping for %pa\n", &addr); + return; + } + __create_mapping(&idmap_pg_dir[pgd_index(addr)], + addr, addr, size, map_io); +} + static void __init map_mem(void) { struct memblock_region *reg; -- cgit v1.2.3 From f84d02755f5a9f3b88e8d15d6384da25ad6dcf5e Mon Sep 17 00:00:00 2001 From: Mark Salter Date: Tue, 15 Apr 2014 21:59:30 -0400 Subject: arm64: add EFI runtime services This patch adds EFI runtime support for arm64. This runtime support allows the kernel to access various EFI runtime services provided by EFI firmware. Things like reboot, real time clock, EFI boot variables, and others. This functionality is supported for little endian kernels only. The UEFI firmware standard specifies that the firmware be little endian. A future patch is expected to add support for big endian kernels running with little endian firmware. Signed-off-by: Mark Salter [ Remove unnecessary cache/tlb maintenance. ] Signed-off-by: Mark Rutland Signed-off-by: Leif Lindholm Signed-off-by: Matt Fleming --- arch/arm64/Kconfig | 15 ++ arch/arm64/include/asm/efi.h | 14 ++ arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/efi.c | 466 +++++++++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/setup.c | 5 + 5 files changed, 501 insertions(+) create mode 100644 arch/arm64/include/asm/efi.h create mode 100644 arch/arm64/kernel/efi.c (limited to 'arch') diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e6e4d3749a6e..82e21de5db3b 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -280,6 +280,19 @@ config CMDLINE_FORCE This is useful if you cannot or don't want to change the command-line options your boot loader passes to the kernel. +config EFI + bool "UEFI runtime support" + depends on OF && !CPU_BIG_ENDIAN + select LIBFDT + select UCS2_STRING + select EFI_PARAMS_FROM_FDT + default y + help + This option provides support for runtime services provided + by UEFI firmware (such as non-volatile variables, realtime + clock, and platform reset). This is only useful on systems + that have UEFI firmware. + endmenu menu "Userspace binary formats" @@ -333,6 +346,8 @@ source "net/Kconfig" source "drivers/Kconfig" +source "drivers/firmware/Kconfig" + source "fs/Kconfig" source "arch/arm64/kvm/Kconfig" diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h new file mode 100644 index 000000000000..5a46c4e7f539 --- /dev/null +++ b/arch/arm64/include/asm/efi.h @@ -0,0 +1,14 @@ +#ifndef _ASM_EFI_H +#define _ASM_EFI_H + +#include + +#ifdef CONFIG_EFI +extern void efi_init(void); +extern void efi_idmap_init(void); +#else +#define efi_init() +#define efi_idmap_init() +#endif + +#endif /* _ASM_EFI_H */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 7d811d9522bc..f57ccd755886 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -22,6 +22,7 @@ arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o +arm64-obj-$(CONFIG_EFI) += efi.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c new file mode 100644 index 000000000000..7bfd65097210 --- /dev/null +++ b/arch/arm64/kernel/efi.c @@ -0,0 +1,466 @@ +/* + * Extensible Firmware Interface + * + * Based on Extensible Firmware Interface Specification version 2.4 + * + * Copyright (C) 2013, 2014 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct efi_memory_map memmap; + +static efi_runtime_services_t *runtime; + +static u64 efi_system_table; + +static int uefi_debug __initdata; +static int __init uefi_debug_setup(char *str) +{ + uefi_debug = 1; + + return 0; +} +early_param("uefi_debug", uefi_debug_setup); + +static int __init is_normal_ram(efi_memory_desc_t *md) +{ + if (md->attribute & EFI_MEMORY_WB) + return 1; + return 0; +} + +static void __init efi_setup_idmap(void) +{ + struct memblock_region *r; + efi_memory_desc_t *md; + u64 paddr, npages, size; + + for_each_memblock(memory, r) + create_id_mapping(r->base, r->size, 0); + + /* map runtime io spaces */ + for_each_efi_memory_desc(&memmap, md) { + if (!(md->attribute & EFI_MEMORY_RUNTIME) || is_normal_ram(md)) + continue; + paddr = md->phys_addr; + npages = md->num_pages; + memrange_efi_to_native(&paddr, &npages); + size = npages << PAGE_SHIFT; + create_id_mapping(paddr, size, 1); + } +} + +static int __init uefi_init(void) +{ + efi_char16_t *c16; + char vendor[100] = "unknown"; + int i, retval; + + efi.systab = early_memremap(efi_system_table, + sizeof(efi_system_table_t)); + if (efi.systab == NULL) { + pr_warn("Unable to map EFI system table.\n"); + return -ENOMEM; + } + + set_bit(EFI_BOOT, &efi.flags); + set_bit(EFI_64BIT, &efi.flags); + + /* + * Verify the EFI Table + */ + if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) { + pr_err("System table signature incorrect\n"); + return -EINVAL; + } + if ((efi.systab->hdr.revision >> 16) < 2) + pr_warn("Warning: EFI system table version %d.%02d, expected 2.00 or greater\n", + efi.systab->hdr.revision >> 16, + efi.systab->hdr.revision & 0xffff); + + /* Show what we know for posterity */ + c16 = early_memremap(efi.systab->fw_vendor, + sizeof(vendor)); + if (c16) { + for (i = 0; i < (int) sizeof(vendor) - 1 && *c16; ++i) + vendor[i] = c16[i]; + vendor[i] = '\0'; + } + + pr_info("EFI v%u.%.02u by %s\n", + efi.systab->hdr.revision >> 16, + efi.systab->hdr.revision & 0xffff, vendor); + + retval = efi_config_init(NULL); + if (retval == 0) + set_bit(EFI_CONFIG_TABLES, &efi.flags); + + early_memunmap(c16, sizeof(vendor)); + early_memunmap(efi.systab, sizeof(efi_system_table_t)); + + return retval; +} + +static __initdata char memory_type_name[][32] = { + {"Reserved"}, + {"Loader Code"}, + {"Loader Data"}, + {"Boot Code"}, + {"Boot Data"}, + {"Runtime Code"}, + {"Runtime Data"}, + {"Conventional Memory"}, + {"Unusable Memory"}, + {"ACPI Reclaim Memory"}, + {"ACPI Memory NVS"}, + {"Memory Mapped I/O"}, + {"MMIO Port Space"}, + {"PAL Code"}, +}; + +/* + * Return true for RAM regions we want to permanently reserve. + */ +static __init int is_reserve_region(efi_memory_desc_t *md) +{ + if (!is_normal_ram(md)) + return 0; + + if (md->attribute & EFI_MEMORY_RUNTIME) + return 1; + + if (md->type == EFI_ACPI_RECLAIM_MEMORY || + md->type == EFI_RESERVED_TYPE) + return 1; + + return 0; +} + +static __init void reserve_regions(void) +{ + efi_memory_desc_t *md; + u64 paddr, npages, size; + + if (uefi_debug) + pr_info("Processing EFI memory map:\n"); + + for_each_efi_memory_desc(&memmap, md) { + paddr = md->phys_addr; + npages = md->num_pages; + + if (uefi_debug) + pr_info(" 0x%012llx-0x%012llx [%s]", + paddr, paddr + (npages << EFI_PAGE_SHIFT) - 1, + memory_type_name[md->type]); + + memrange_efi_to_native(&paddr, &npages); + size = npages << PAGE_SHIFT; + + if (is_normal_ram(md)) + early_init_dt_add_memory_arch(paddr, size); + + if (is_reserve_region(md) || + md->type == EFI_BOOT_SERVICES_CODE || + md->type == EFI_BOOT_SERVICES_DATA) { + memblock_reserve(paddr, size); + if (uefi_debug) + pr_cont("*"); + } + + if (uefi_debug) + pr_cont("\n"); + } +} + + +static u64 __init free_one_region(u64 start, u64 end) +{ + u64 size = end - start; + + if (uefi_debug) + pr_info(" EFI freeing: 0x%012llx-0x%012llx\n", start, end - 1); + + free_bootmem_late(start, size); + return size; +} + +static u64 __init free_region(u64 start, u64 end) +{ + u64 map_start, map_end, total = 0; + + if (end <= start) + return total; + + map_start = (u64)memmap.phys_map; + map_end = PAGE_ALIGN(map_start + (memmap.map_end - memmap.map)); + map_start &= PAGE_MASK; + + if (start < map_end && end > map_start) { + /* region overlaps UEFI memmap */ + if (start < map_start) + total += free_one_region(start, map_start); + + if (map_end < end) + total += free_one_region(map_end, end); + } else + total += free_one_region(start, end); + + return total; +} + +static void __init free_boot_services(void) +{ + u64 total_freed = 0; + u64 keep_end, free_start, free_end; + efi_memory_desc_t *md; + + /* + * If kernel uses larger pages than UEFI, we have to be careful + * not to inadvertantly free memory we want to keep if there is + * overlap at the kernel page size alignment. We do not want to + * free is_reserve_region() memory nor the UEFI memmap itself. + * + * The memory map is sorted, so we keep track of the end of + * any previous region we want to keep, remember any region + * we want to free and defer freeing it until we encounter + * the next region we want to keep. This way, before freeing + * it, we can clip it as needed to avoid freeing memory we + * want to keep for UEFI. + */ + + keep_end = 0; + free_start = 0; + + for_each_efi_memory_desc(&memmap, md) { + u64 paddr, npages, size; + + if (is_reserve_region(md)) { + /* + * We don't want to free any memory from this region. + */ + if (free_start) { + /* adjust free_end then free region */ + if (free_end > md->phys_addr) + free_end -= PAGE_SIZE; + total_freed += free_region(free_start, free_end); + free_start = 0; + } + keep_end = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT); + continue; + } + + if (md->type != EFI_BOOT_SERVICES_CODE && + md->type != EFI_BOOT_SERVICES_DATA) { + /* no need to free this region */ + continue; + } + + /* + * We want to free memory from this region. + */ + paddr = md->phys_addr; + npages = md->num_pages; + memrange_efi_to_native(&paddr, &npages); + size = npages << PAGE_SHIFT; + + if (free_start) { + if (paddr <= free_end) + free_end = paddr + size; + else { + total_freed += free_region(free_start, free_end); + free_start = paddr; + free_end = paddr + size; + } + } else { + free_start = paddr; + free_end = paddr + size; + } + if (free_start < keep_end) { + free_start += PAGE_SIZE; + if (free_start >= free_end) + free_start = 0; + } + } + if (free_start) + total_freed += free_region(free_start, free_end); + + if (total_freed) + pr_info("Freed 0x%llx bytes of EFI boot services memory", + total_freed); +} + +void __init efi_init(void) +{ + struct efi_fdt_params params; + + /* Grab UEFI information placed in FDT by stub */ + if (!efi_get_fdt_params(¶ms, uefi_debug)) + return; + + efi_system_table = params.system_table; + + memblock_reserve(params.mmap & PAGE_MASK, + PAGE_ALIGN(params.mmap_size + (params.mmap & ~PAGE_MASK))); + memmap.phys_map = (void *)params.mmap; + memmap.map = early_memremap(params.mmap, params.mmap_size); + memmap.map_end = memmap.map + params.mmap_size; + memmap.desc_size = params.desc_size; + memmap.desc_version = params.desc_ver; + + if (uefi_init() < 0) + return; + + reserve_regions(); +} + +void __init efi_idmap_init(void) +{ + /* boot time idmap_pg_dir is incomplete, so fill in missing parts */ + efi_setup_idmap(); +} + +static int __init remap_region(efi_memory_desc_t *md, void **new) +{ + u64 paddr, vaddr, npages, size; + + paddr = md->phys_addr; + npages = md->num_pages; + memrange_efi_to_native(&paddr, &npages); + size = npages << PAGE_SHIFT; + + if (is_normal_ram(md)) + vaddr = (__force u64)ioremap_cache(paddr, size); + else + vaddr = (__force u64)ioremap(paddr, size); + + if (!vaddr) { + pr_err("Unable to remap 0x%llx pages @ %p\n", + npages, (void *)paddr); + return 0; + } + + /* adjust for any rounding when EFI and system pagesize differs */ + md->virt_addr = vaddr + (md->phys_addr - paddr); + + if (uefi_debug) + pr_info(" EFI remap 0x%012llx => %p\n", + md->phys_addr, (void *)md->virt_addr); + + memcpy(*new, md, memmap.desc_size); + *new += memmap.desc_size; + + return 1; +} + +/* + * Switch UEFI from an identity map to a kernel virtual map + */ +static int __init arm64_enter_virtual_mode(void) +{ + efi_memory_desc_t *md; + phys_addr_t virtmap_phys; + void *virtmap, *virt_md; + efi_status_t status; + u64 mapsize; + int count = 0; + unsigned long flags; + + if (!efi_enabled(EFI_BOOT)) { + pr_info("EFI services will not be available.\n"); + return -1; + } + + pr_info("Remapping and enabling EFI services.\n"); + + /* replace early memmap mapping with permanent mapping */ + mapsize = memmap.map_end - memmap.map; + early_memunmap(memmap.map, mapsize); + memmap.map = (__force void *)ioremap_cache((phys_addr_t)memmap.phys_map, + mapsize); + memmap.map_end = memmap.map + mapsize; + + efi.memmap = &memmap; + + /* Map the runtime regions */ + virtmap = kmalloc(mapsize, GFP_KERNEL); + if (!virtmap) { + pr_err("Failed to allocate EFI virtual memmap\n"); + return -1; + } + virtmap_phys = virt_to_phys(virtmap); + virt_md = virtmap; + + for_each_efi_memory_desc(&memmap, md) { + if (!(md->attribute & EFI_MEMORY_RUNTIME)) + continue; + if (remap_region(md, &virt_md)) + ++count; + } + + efi.systab = (__force void *)efi_lookup_mapped_addr(efi_system_table); + if (efi.systab) + set_bit(EFI_SYSTEM_TABLES, &efi.flags); + + local_irq_save(flags); + cpu_switch_mm(idmap_pg_dir, &init_mm); + + /* Call SetVirtualAddressMap with the physical address of the map */ + runtime = efi.systab->runtime; + efi.set_virtual_address_map = runtime->set_virtual_address_map; + + status = efi.set_virtual_address_map(count * memmap.desc_size, + memmap.desc_size, + memmap.desc_version, + (efi_memory_desc_t *)virtmap_phys); + cpu_set_reserved_ttbr0(); + flush_tlb_all(); + local_irq_restore(flags); + + kfree(virtmap); + + free_boot_services(); + + if (status != EFI_SUCCESS) { + pr_err("Failed to set EFI virtual address map! [%lx]\n", + status); + return -1; + } + + /* Set up runtime services function pointers */ + runtime = efi.systab->runtime; + efi.get_time = runtime->get_time; + efi.set_time = runtime->set_time; + efi.get_wakeup_time = runtime->get_wakeup_time; + efi.set_wakeup_time = runtime->set_wakeup_time; + efi.get_variable = runtime->get_variable; + efi.get_next_variable = runtime->get_next_variable; + efi.set_variable = runtime->set_variable; + efi.query_variable_info = runtime->query_variable_info; + efi.update_capsule = runtime->update_capsule; + efi.query_capsule_caps = runtime->query_capsule_caps; + efi.get_next_high_mono_count = runtime->get_next_high_mono_count; + efi.reset_system = runtime->reset_system; + + set_bit(EFI_RUNTIME_SERVICES, &efi.flags); + + return 0; +} +early_initcall(arm64_enter_virtual_mode); diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 720853f70b6b..0a14aaffc834 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -55,6 +56,7 @@ #include #include #include +#include unsigned int processor_id; EXPORT_SYMBOL(processor_id); @@ -366,11 +368,14 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); + efi_init(); arm64_memblock_init(); paging_init(); request_standard_resources(); + efi_idmap_init(); + unflatten_device_tree(); psci_init(); -- cgit v1.2.3 From 8d90c5aff3e8b128fda43aac83b4442048b51bad Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 21 Apr 2014 16:26:27 -0500 Subject: ARM: dts: use real clocks for bcm21664 Replace the "fake" fixed-rate clocks used previously for the bcm21664 family with "real" ones. Signed-off-by: Alex Elder Acked-by: Matt Porter Signed-off-by: Mike Turquette --- arch/arm/boot/dts/bcm21664.dtsi | 164 +++++++++++++++++++++++++--------------- 1 file changed, 105 insertions(+), 59 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 08a44d41b672..8b366822bb43 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -14,6 +14,8 @@ #include #include +#include "dt-bindings/clock/bcm21664.h" + #include "skeleton.dtsi" / { @@ -43,7 +45,7 @@ compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e000000 0x118>; - clocks = <&uartb_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -53,7 +55,7 @@ compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e001000 0x118>; - clocks = <&uartb2_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -63,7 +65,7 @@ compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e002000 0x118>; - clocks = <&uartb3_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; interrupts = ; reg-shift = <2>; reg-io-width = <4>; @@ -85,7 +87,7 @@ compatible = "brcm,kona-timer"; reg = <0x35006000 0x1c>; interrupts = ; - clocks = <&hub_timer_clk>; + clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; }; gpio: gpio@35003000 { @@ -106,7 +108,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f180000 0x801c>; interrupts = ; - clocks = <&sdio1_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; status = "disabled"; }; @@ -114,7 +116,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f190000 0x801c>; interrupts = ; - clocks = <&sdio2_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; status = "disabled"; }; @@ -122,7 +124,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f1a0000 0x801c>; interrupts = ; - clocks = <&sdio3_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; status = "disabled"; }; @@ -130,7 +132,7 @@ compatible = "brcm,kona-sdhci"; reg = <0x3f1b0000 0x801c>; interrupts = ; - clocks = <&sdio4_clk>; + clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; status = "disabled"; }; @@ -140,7 +142,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc1_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; status = "disabled"; }; @@ -150,7 +152,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc2_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; status = "disabled"; }; @@ -160,7 +162,7 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc3_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; status = "disabled"; }; @@ -170,105 +172,149 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - clocks = <&bsc4_clk>; + clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; status = "disabled"; }; clocks { - bsc1_clk: bsc1 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; - #clock-cells = <0>; - }; + #address-cells = <1>; + #size-cells = <1>; + ranges; - bsc2_clk: bsc2 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + /* + * Fixed clocks are defined before CCUs whose + * clocks may depend on them. + */ + + ref_32k_clk: ref_32k { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - bsc3_clk: bsc3 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + bbl_32k_clk: bbl_32k { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - bsc4_clk: bsc4 { + ref_13m_clk: ref_13m { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; - #clock-cells = <0>; }; - pmu_bsc_clk: pmu_bsc { + var_13m_clk: var_13m { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <13000000>; - #clock-cells = <0>; }; - hub_timer_clk: hub_timer { - compatible = "fixed-clock"; - clock-frequency = <32768>; + dft_19_5m_clk: dft_19_5m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19500000>; }; - pwm_clk: pwm { + ref_crystal_clk: ref_crystal { + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <26000000>; - #clock-cells = <0>; }; - sdio1_clk: sdio1 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + ref_52m_clk: ref_52m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio2_clk: sdio2 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + var_52m_clk: var_52m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio3_clk: sdio3 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + usb_otg_ahb_clk: usb_otg_ahb { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <52000000>; }; - sdio4_clk: sdio4 { - compatible = "fixed-clock"; - clock-frequency = <48000000>; + ref_96m_clk: ref_96m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; }; - tmon_1m_clk: tmon_1m { - compatible = "fixed-clock"; - clock-frequency = <1000000>; + var_96m_clk: var_96m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <96000000>; }; - uartb_clk: uartb { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + ref_104m_clk: ref_104m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; }; - uartb2_clk: uartb2 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + var_104m_clk: var_104m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104000000>; }; - uartb3_clk: uartb3 { - compatible = "fixed-clock"; - clock-frequency = <13000000>; + ref_156m_clk: ref_156m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; }; - usb_otg_ahb_clk: usb_otg_ahb { - compatible = "fixed-clock"; - clock-frequency = <52000000>; + var_156m_clk: var_156m { #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <156000000>; + }; + + root_ccu: root_ccu { + compatible = BCM21664_DT_ROOT_CCU_COMPAT; + reg = <0x35001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "frac_1m"; + }; + + aon_ccu: aon_ccu { + compatible = BCM21664_DT_AON_CCU_COMPAT; + reg = <0x35002000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "hub_timer"; + }; + + master_ccu: master_ccu { + compatible = BCM21664_DT_MASTER_CCU_COMPAT; + reg = <0x3f001000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "sdio1", + "sdio2", + "sdio3", + "sdio4", + "sdio1_sleep", + "sdio2_sleep", + "sdio3_sleep", + "sdio4_sleep"; + }; + + slave_ccu: slave_ccu { + compatible = BCM21664_DT_SLAVE_CCU_COMPAT; + reg = <0x3e011000 0x0f00>; + #clock-cells = <1>; + clock-output-names = "uartb", + "uartb2", + "uartb3", + "bsc1", + "bsc2", + "bsc3", + "bsc4"; }; }; -- cgit v1.2.3 From 3c7f255039a2ad6ee1e3890505caf0d029b22e29 Mon Sep 17 00:00:00 2001 From: Mark Salter Date: Tue, 15 Apr 2014 22:47:52 -0400 Subject: arm64: efi: add EFI stub This patch adds PE/COFF header fields to the start of the kernel Image so that it appears as an EFI application to UEFI firmware. An EFI stub is included to allow direct booting of the kernel Image. Signed-off-by: Mark Salter [Add support in PE/COFF header for signed images] Signed-off-by: Ard Biesheuvel Signed-off-by: Leif Lindholm Acked-by: Catalin Marinas Signed-off-by: Matt Fleming --- arch/arm64/Kconfig | 5 +- arch/arm64/kernel/Makefile | 4 +- arch/arm64/kernel/efi-entry.S | 109 ++++++++++++++++++ arch/arm64/kernel/efi-stub.c | 81 +++++++++++++ arch/arm64/kernel/head.S | 112 ++++++++++++++++++ drivers/firmware/efi/arm-stub.c | 247 ++++++++++++++++++++++++++++++++++++++++ 6 files changed, 555 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/kernel/efi-entry.S create mode 100644 arch/arm64/kernel/efi-stub.c create mode 100644 drivers/firmware/efi/arm-stub.c (limited to 'arch') diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 82e21de5db3b..6c71f122638d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -290,8 +290,9 @@ config EFI help This option provides support for runtime services provided by UEFI firmware (such as non-volatile variables, realtime - clock, and platform reset). This is only useful on systems - that have UEFI firmware. + clock, and platform reset). A UEFI stub is also provided to + allow the kernel to be booted as an EFI application. This + is only useful on systems that have UEFI firmware. endmenu diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index f57ccd755886..db63a0a25810 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -4,6 +4,8 @@ CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET) AFLAGS_head.o := -DTEXT_OFFSET=$(TEXT_OFFSET) +CFLAGS_efi-stub.o := -DTEXT_OFFSET=$(TEXT_OFFSET) \ + -I$(src)/../../../scripts/dtc/libfdt # Object file lists. arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ @@ -22,7 +24,7 @@ arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o arm64-obj-$(CONFIG_KGDB) += kgdb.o -arm64-obj-$(CONFIG_EFI) += efi.o +arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o obj-y += $(arm64-obj-y) vdso/ obj-m += $(arm64-obj-m) diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S new file mode 100644 index 000000000000..66716c9b9e5f --- /dev/null +++ b/arch/arm64/kernel/efi-entry.S @@ -0,0 +1,109 @@ +/* + * EFI entry point. + * + * Copyright (C) 2013, 2014 Red Hat, Inc. + * Author: Mark Salter + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include + +#include + +#define EFI_LOAD_ERROR 0x8000000000000001 + + __INIT + + /* + * We arrive here from the EFI boot manager with: + * + * * CPU in little-endian mode + * * MMU on with identity-mapped RAM + * * Icache and Dcache on + * + * We will most likely be running from some place other than where + * we want to be. The kernel image wants to be placed at TEXT_OFFSET + * from start of RAM. + */ +ENTRY(efi_stub_entry) + /* + * Create a stack frame to save FP/LR with extra space + * for image_addr variable passed to efi_entry(). + */ + stp x29, x30, [sp, #-32]! + + /* + * Call efi_entry to do the real work. + * x0 and x1 are already set up by firmware. Current runtime + * address of image is calculated and passed via *image_addr. + * + * unsigned long efi_entry(void *handle, + * efi_system_table_t *sys_table, + * unsigned long *image_addr) ; + */ + adrp x8, _text + add x8, x8, #:lo12:_text + add x2, sp, 16 + str x8, [x2] + bl efi_entry + cmn x0, #1 + b.eq efi_load_fail + + /* + * efi_entry() will have relocated the kernel image if necessary + * and we return here with device tree address in x0 and the kernel + * entry point stored at *image_addr. Save those values in registers + * which are callee preserved. + */ + mov x20, x0 // DTB address + ldr x0, [sp, #16] // relocated _text address + mov x21, x0 + + /* + * Flush dcache covering current runtime addresses + * of kernel text/data. Then flush all of icache. + */ + adrp x1, _text + add x1, x1, #:lo12:_text + adrp x2, _edata + add x2, x2, #:lo12:_edata + sub x1, x2, x1 + + bl __flush_dcache_area + ic ialluis + + /* Turn off Dcache and MMU */ + mrs x0, CurrentEL + cmp x0, #PSR_MODE_EL2t + ccmp x0, #PSR_MODE_EL2h, #0x4, ne + b.ne 1f + mrs x0, sctlr_el2 + bic x0, x0, #1 << 0 // clear SCTLR.M + bic x0, x0, #1 << 2 // clear SCTLR.C + msr sctlr_el2, x0 + isb + b 2f +1: + mrs x0, sctlr_el1 + bic x0, x0, #1 << 0 // clear SCTLR.M + bic x0, x0, #1 << 2 // clear SCTLR.C + msr sctlr_el1, x0 + isb +2: + /* Jump to kernel entry point */ + mov x0, x20 + mov x1, xzr + mov x2, xzr + mov x3, xzr + br x21 + +efi_load_fail: + mov x0, #EFI_LOAD_ERROR + ldp x29, x30, [sp], #32 + ret + +ENDPROC(efi_stub_entry) diff --git a/arch/arm64/kernel/efi-stub.c b/arch/arm64/kernel/efi-stub.c new file mode 100644 index 000000000000..60e98a639ac5 --- /dev/null +++ b/arch/arm64/kernel/efi-stub.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2013, 2014 Linaro Ltd; + * + * This file implements the EFI boot stub for the arm64 kernel. + * Adapted from ARM version by Mark Salter + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#include +#include +#include +#include +#include + +/* + * AArch64 requires the DTB to be 8-byte aligned in the first 512MiB from + * start of kernel and may not cross a 2MiB boundary. We set alignment to + * 2MiB so we know it won't cross a 2MiB boundary. + */ +#define EFI_FDT_ALIGN SZ_2M /* used by allocate_new_fdt_and_exit_boot() */ +#define MAX_FDT_OFFSET SZ_512M + +#define efi_call_early(f, ...) sys_table_arg->boottime->f(__VA_ARGS__) + +static void efi_char16_printk(efi_system_table_t *sys_table_arg, + efi_char16_t *str); + +static efi_status_t efi_open_volume(efi_system_table_t *sys_table, + void *__image, void **__fh); +static efi_status_t efi_file_close(void *handle); + +static efi_status_t +efi_file_read(void *handle, unsigned long *size, void *addr); + +static efi_status_t +efi_file_size(efi_system_table_t *sys_table, void *__fh, + efi_char16_t *filename_16, void **handle, u64 *file_sz); + +/* Include shared EFI stub code */ +#include "../../../drivers/firmware/efi/efi-stub-helper.c" +#include "../../../drivers/firmware/efi/fdt.c" +#include "../../../drivers/firmware/efi/arm-stub.c" + + +static efi_status_t handle_kernel_image(efi_system_table_t *sys_table, + unsigned long *image_addr, + unsigned long *image_size, + unsigned long *reserve_addr, + unsigned long *reserve_size, + unsigned long dram_base, + efi_loaded_image_t *image) +{ + efi_status_t status; + unsigned long kernel_size, kernel_memsize = 0; + + /* Relocate the image, if required. */ + kernel_size = _edata - _text; + if (*image_addr != (dram_base + TEXT_OFFSET)) { + kernel_memsize = kernel_size + (_end - _edata); + status = efi_relocate_kernel(sys_table, image_addr, + kernel_size, kernel_memsize, + dram_base + TEXT_OFFSET, + PAGE_SIZE); + if (status != EFI_SUCCESS) { + pr_efi_err(sys_table, "Failed to relocate kernel\n"); + return status; + } + if (*image_addr != (dram_base + TEXT_OFFSET)) { + pr_efi_err(sys_table, "Failed to alloc kernel memory\n"); + efi_free(sys_table, kernel_memsize, *image_addr); + return EFI_ERROR; + } + *image_size = kernel_memsize; + } + + + return EFI_SUCCESS; +} diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 0fd565000772..738291b5be29 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -108,8 +108,18 @@ /* * DO NOT MODIFY. Image header expected by Linux boot-loaders. */ +#ifdef CONFIG_EFI +efi_head: + /* + * This add instruction has no meaningful effect except that + * its opcode forms the magic "MZ" signature required by UEFI. + */ + add x13, x18, #0x16 + b stext +#else b stext // branch to kernel start, magic .long 0 // reserved +#endif .quad TEXT_OFFSET // Image load offset from start of RAM .quad 0 // reserved .quad 0 // reserved @@ -120,7 +130,109 @@ .byte 0x52 .byte 0x4d .byte 0x64 +#ifdef CONFIG_EFI + .long pe_header - efi_head // Offset to the PE header. +#else .word 0 // reserved +#endif + +#ifdef CONFIG_EFI + .align 3 +pe_header: + .ascii "PE" + .short 0 +coff_header: + .short 0xaa64 // AArch64 + .short 2 // nr_sections + .long 0 // TimeDateStamp + .long 0 // PointerToSymbolTable + .long 1 // NumberOfSymbols + .short section_table - optional_header // SizeOfOptionalHeader + .short 0x206 // Characteristics. + // IMAGE_FILE_DEBUG_STRIPPED | + // IMAGE_FILE_EXECUTABLE_IMAGE | + // IMAGE_FILE_LINE_NUMS_STRIPPED +optional_header: + .short 0x20b // PE32+ format + .byte 0x02 // MajorLinkerVersion + .byte 0x14 // MinorLinkerVersion + .long _edata - stext // SizeOfCode + .long 0 // SizeOfInitializedData + .long 0 // SizeOfUninitializedData + .long efi_stub_entry - efi_head // AddressOfEntryPoint + .long stext - efi_head // BaseOfCode + +extra_header_fields: + .quad 0 // ImageBase + .long 0x20 // SectionAlignment + .long 0x8 // FileAlignment + .short 0 // MajorOperatingSystemVersion + .short 0 // MinorOperatingSystemVersion + .short 0 // MajorImageVersion + .short 0 // MinorImageVersion + .short 0 // MajorSubsystemVersion + .short 0 // MinorSubsystemVersion + .long 0 // Win32VersionValue + + .long _edata - efi_head // SizeOfImage + + // Everything before the kernel image is considered part of the header + .long stext - efi_head // SizeOfHeaders + .long 0 // CheckSum + .short 0xa // Subsystem (EFI application) + .short 0 // DllCharacteristics + .quad 0 // SizeOfStackReserve + .quad 0 // SizeOfStackCommit + .quad 0 // SizeOfHeapReserve + .quad 0 // SizeOfHeapCommit + .long 0 // LoaderFlags + .long 0x6 // NumberOfRvaAndSizes + + .quad 0 // ExportTable + .quad 0 // ImportTable + .quad 0 // ResourceTable + .quad 0 // ExceptionTable + .quad 0 // CertificationTable + .quad 0 // BaseRelocationTable + + // Section table +section_table: + + /* + * The EFI application loader requires a relocation section + * because EFI applications must be relocatable. This is a + * dummy section as far as we are concerned. + */ + .ascii ".reloc" + .byte 0 + .byte 0 // end of 0 padding of section name + .long 0 + .long 0 + .long 0 // SizeOfRawData + .long 0 // PointerToRawData + .long 0 // PointerToRelocations + .long 0 // PointerToLineNumbers + .short 0 // NumberOfRelocations + .short 0 // NumberOfLineNumbers + .long 0x42100040 // Characteristics (section flags) + + + .ascii ".text" + .byte 0 + .byte 0 + .byte 0 // end of 0 padding of section name + .long _edata - stext // VirtualSize + .long stext - efi_head // VirtualAddress + .long _edata - stext // SizeOfRawData + .long stext - efi_head // PointerToRawData + + .long 0 // PointerToRelocations (0 for executables) + .long 0 // PointerToLineNumbers (0 for executables) + .short 0 // NumberOfRelocations (0 for executables) + .short 0 // NumberOfLineNumbers (0 for executables) + .long 0xe0500020 // Characteristics (section flags) + .align 5 +#endif ENTRY(stext) mov x21, x0 // x21=FDT diff --git a/drivers/firmware/efi/arm-stub.c b/drivers/firmware/efi/arm-stub.c new file mode 100644 index 000000000000..19239a9b7e29 --- /dev/null +++ b/drivers/firmware/efi/arm-stub.c @@ -0,0 +1,247 @@ +/* + * EFI stub implementation that is shared by arm and arm64 architectures. + * This should be #included by the EFI stub implementation files. + * + * Copyright (C) 2013,2014 Linaro Limited + * Roy Franz + * + * This file is part of the Linux kernel, and is made available under the + * terms of the GNU General Public License version 2. + * + */ + +static efi_status_t efi_open_volume(efi_system_table_t *sys_table_arg, + void *__image, void **__fh) +{ + efi_file_io_interface_t *io; + efi_loaded_image_t *image = __image; + efi_file_handle_t *fh; + efi_guid_t fs_proto = EFI_FILE_SYSTEM_GUID; + efi_status_t status; + void *handle = (void *)(unsigned long)image->device_handle; + + status = sys_table_arg->boottime->handle_protocol(handle, + &fs_proto, (void **)&io); + if (status != EFI_SUCCESS) { + efi_printk(sys_table_arg, "Failed to handle fs_proto\n"); + return status; + } + + status = io->open_volume(io, &fh); + if (status != EFI_SUCCESS) + efi_printk(sys_table_arg, "Failed to open volume\n"); + + *__fh = fh; + return status; +} +static efi_status_t efi_file_close(void *handle) +{ + efi_file_handle_t *fh = handle; + + return fh->close(handle); +} + +static efi_status_t +efi_file_read(void *handle, unsigned long *size, void *addr) +{ + efi_file_handle_t *fh = handle; + + return fh->read(handle, size, addr); +} + + +static efi_status_t +efi_file_size(efi_system_table_t *sys_table_arg, void *__fh, + efi_char16_t *filename_16, void **handle, u64 *file_sz) +{ + efi_file_handle_t *h, *fh = __fh; + efi_file_info_t *info; + efi_status_t status; + efi_guid_t info_guid = EFI_FILE_INFO_ID; + unsigned long info_sz; + + status = fh->open(fh, &h, filename_16, EFI_FILE_MODE_READ, (u64)0); + if (status != EFI_SUCCESS) { + efi_printk(sys_table_arg, "Failed to open file: "); + efi_char16_printk(sys_table_arg, filename_16); + efi_printk(sys_table_arg, "\n"); + return status; + } + + *handle = h; + + info_sz = 0; + status = h->get_info(h, &info_guid, &info_sz, NULL); + if (status != EFI_BUFFER_TOO_SMALL) { + efi_printk(sys_table_arg, "Failed to get file info size\n"); + return status; + } + +grow: + status = sys_table_arg->boottime->allocate_pool(EFI_LOADER_DATA, + info_sz, (void **)&info); + if (status != EFI_SUCCESS) { + efi_printk(sys_table_arg, "Failed to alloc mem for file info\n"); + return status; + } + + status = h->get_info(h, &info_guid, &info_sz, + info); + if (status == EFI_BUFFER_TOO_SMALL) { + sys_table_arg->boottime->free_pool(info); + goto grow; + } + + *file_sz = info->file_size; + sys_table_arg->boottime->free_pool(info); + + if (status != EFI_SUCCESS) + efi_printk(sys_table_arg, "Failed to get initrd info\n"); + + return status; +} + + + +static void efi_char16_printk(efi_system_table_t *sys_table_arg, + efi_char16_t *str) +{ + struct efi_simple_text_output_protocol *out; + + out = (struct efi_simple_text_output_protocol *)sys_table_arg->con_out; + out->output_string(out, str); +} + + +/* + * This function handles the architcture specific differences between arm and + * arm64 regarding where the kernel image must be loaded and any memory that + * must be reserved. On failure it is required to free all + * all allocations it has made. + */ +static efi_status_t handle_kernel_image(efi_system_table_t *sys_table, + unsigned long *image_addr, + unsigned long *image_size, + unsigned long *reserve_addr, + unsigned long *reserve_size, + unsigned long dram_base, + efi_loaded_image_t *image); +/* + * EFI entry point for the arm/arm64 EFI stubs. This is the entrypoint + * that is described in the PE/COFF header. Most of the code is the same + * for both archictectures, with the arch-specific code provided in the + * handle_kernel_image() function. + */ +unsigned long __init efi_entry(void *handle, efi_system_table_t *sys_table, + unsigned long *image_addr) +{ + efi_loaded_image_t *image; + efi_status_t status; + unsigned long image_size = 0; + unsigned long dram_base; + /* addr/point and size pairs for memory management*/ + unsigned long initrd_addr; + u64 initrd_size = 0; + unsigned long fdt_addr; /* Original DTB */ + u64 fdt_size = 0; /* We don't get size from configuration table */ + char *cmdline_ptr = NULL; + int cmdline_size = 0; + unsigned long new_fdt_addr; + efi_guid_t loaded_image_proto = LOADED_IMAGE_PROTOCOL_GUID; + unsigned long reserve_addr = 0; + unsigned long reserve_size = 0; + + /* Check if we were booted by the EFI firmware */ + if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE) + goto fail; + + pr_efi(sys_table, "Booting Linux Kernel...\n"); + + /* + * Get a handle to the loaded image protocol. This is used to get + * information about the running image, such as size and the command + * line. + */ + status = sys_table->boottime->handle_protocol(handle, + &loaded_image_proto, (void *)&image); + if (status != EFI_SUCCESS) { + pr_efi_err(sys_table, "Failed to get loaded image protocol\n"); + goto fail; + } + + dram_base = get_dram_base(sys_table); + if (dram_base == EFI_ERROR) { + pr_efi_err(sys_table, "Failed to find DRAM base\n"); + goto fail; + } + status = handle_kernel_image(sys_table, image_addr, &image_size, + &reserve_addr, + &reserve_size, + dram_base, image); + if (status != EFI_SUCCESS) { + pr_efi_err(sys_table, "Failed to relocate kernel\n"); + goto fail; + } + + /* + * Get the command line from EFI, using the LOADED_IMAGE + * protocol. We are going to copy the command line into the + * device tree, so this can be allocated anywhere. + */ + cmdline_ptr = efi_convert_cmdline(sys_table, image, &cmdline_size); + if (!cmdline_ptr) { + pr_efi_err(sys_table, "getting command line via LOADED_IMAGE_PROTOCOL\n"); + goto fail_free_image; + } + + /* Load a device tree from the configuration table, if present. */ + fdt_addr = (uintptr_t)get_fdt(sys_table); + if (!fdt_addr) { + status = handle_cmdline_files(sys_table, image, cmdline_ptr, + "dtb=", + ~0UL, (unsigned long *)&fdt_addr, + (unsigned long *)&fdt_size); + + if (status != EFI_SUCCESS) { + pr_efi_err(sys_table, "Failed to load device tree!\n"); + goto fail_free_cmdline; + } + } + + status = handle_cmdline_files(sys_table, image, cmdline_ptr, + "initrd=", dram_base + SZ_512M, + (unsigned long *)&initrd_addr, + (unsigned long *)&initrd_size); + if (status != EFI_SUCCESS) + pr_efi_err(sys_table, "Failed initrd from command line!\n"); + + new_fdt_addr = fdt_addr; + status = allocate_new_fdt_and_exit_boot(sys_table, handle, + &new_fdt_addr, dram_base + MAX_FDT_OFFSET, + initrd_addr, initrd_size, cmdline_ptr, + fdt_addr, fdt_size); + + /* + * If all went well, we need to return the FDT address to the + * calling function so it can be passed to kernel as part of + * the kernel boot protocol. + */ + if (status == EFI_SUCCESS) + return new_fdt_addr; + + pr_efi_err(sys_table, "Failed to update FDT and exit boot services\n"); + + efi_free(sys_table, initrd_size, initrd_addr); + efi_free(sys_table, fdt_size, fdt_addr); + +fail_free_cmdline: + efi_free(sys_table, cmdline_size, (unsigned long)cmdline_ptr); + +fail_free_image: + efi_free(sys_table, image_size, *image_addr); + efi_free(sys_table, reserve_size, reserve_addr); +fail: + return EFI_ERROR; +} -- cgit v1.2.3 From dfc73e7acd9925b434a355eeeed86d44cb435f9c Mon Sep 17 00:00:00 2001 From: Sebastian Ott Date: Thu, 17 Apr 2014 19:46:15 +0200 Subject: PCI: Move Open Firmware devspec attribute to PCI common code Move the devspec OF attribute to PCI common code's set of device attributes since it's not architecture dependent. As a side effect microblaze and powerpc no longer need to use pcibios_add_platform_entries(). [bhelgaas: fold in #include for compile error] Link: https://lkml.kernel.org/r/alpine.LFD.2.11.1404141101500.1529@denkbrett Signed-off-by: Sebastian Ott Signed-off-by: Bjorn Helgaas Acked-by: Benjamin Herrenschmidt --- arch/microblaze/pci/pci-common.c | 20 -------------------- arch/powerpc/kernel/pci-common.c | 20 -------------------- drivers/pci/pci-sysfs.c | 18 ++++++++++++++++++ 3 files changed, 18 insertions(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 70996cc66aa2..a59de1bc1ce0 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -168,26 +168,6 @@ struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node) return NULL; } -static ssize_t pci_show_devspec(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct pci_dev *pdev; - struct device_node *np; - - pdev = to_pci_dev(dev); - np = pci_device_to_OF_node(pdev); - if (np == NULL || np->full_name == NULL) - return 0; - return sprintf(buf, "%s", np->full_name); -} -static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); - -/* Add sysfs properties */ -int pcibios_add_platform_entries(struct pci_dev *pdev) -{ - return device_create_file(&pdev->dev, &dev_attr_devspec); -} - void pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index d9476c1fc959..24d342e91790 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -201,26 +201,6 @@ struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) return NULL; } -static ssize_t pci_show_devspec(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct pci_dev *pdev; - struct device_node *np; - - pdev = to_pci_dev (dev); - np = pci_device_to_OF_node(pdev); - if (np == NULL || np->full_name == NULL) - return 0; - return sprintf(buf, "%s", np->full_name); -} -static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); - -/* Add sysfs properties */ -int pcibios_add_platform_entries(struct pci_dev *pdev) -{ - return device_create_file(&pdev->dev, &dev_attr_devspec); -} - /* * Reads the interrupt pin to determine if interrupt is use by card. * If the interrupt is used, then gets the interrupt line from the diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 4e0acefb7565..3db1c7ff5dd3 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "pci.h" static int sysfs_initialized; /* = 0 */ @@ -416,6 +417,20 @@ static ssize_t d3cold_allowed_show(struct device *dev, static DEVICE_ATTR_RW(d3cold_allowed); #endif +#ifdef CONFIG_OF +static ssize_t devspec_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct device_node *np = pci_device_to_OF_node(pdev); + + if (np == NULL || np->full_name == NULL) + return 0; + return sprintf(buf, "%s", np->full_name); +} +static DEVICE_ATTR_RO(devspec); +#endif + #ifdef CONFIG_PCI_IOV static ssize_t sriov_totalvfs_show(struct device *dev, struct device_attribute *attr, @@ -520,6 +535,9 @@ static struct attribute *pci_dev_attrs[] = { &dev_attr_msi_bus.attr, #if defined(CONFIG_PM_RUNTIME) && defined(CONFIG_ACPI) &dev_attr_d3cold_allowed.attr, +#endif +#ifdef CONFIG_OF + &dev_attr_devspec.attr, #endif NULL, }; -- cgit v1.2.3 From 3891a04aafd668686239349ea58f3314ea2af86b Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Tue, 29 Apr 2014 16:46:09 -0700 Subject: x86-64, espfix: Don't leak bits 31:16 of %esp returning to 16-bit stack The IRET instruction, when returning to a 16-bit segment, only restores the bottom 16 bits of the user space stack pointer. This causes some 16-bit software to break, but it also leaks kernel state to user space. We have a software workaround for that ("espfix") for the 32-bit kernel, but it relies on a nonzero stack segment base which is not available in 64-bit mode. In checkin: b3b42ac2cbae x86-64, modify_ldt: Ban 16-bit segments on 64-bit kernels we "solved" this by forbidding 16-bit segments on 64-bit kernels, with the logic that 16-bit support is crippled on 64-bit kernels anyway (no V86 support), but it turns out that people are doing stuff like running old Win16 binaries under Wine and expect it to work. This works around this by creating percpu "ministacks", each of which is mapped 2^16 times 64K apart. When we detect that the return SS is on the LDT, we copy the IRET frame to the ministack and use the relevant alias to return to userspace. The ministacks are mapped readonly, so if IRET faults we promote #GP to #DF which is an IST vector and thus has its own stack; we then do the fixup in the #DF handler. (Making #GP an IST exception would make the msr_safe functions unsafe in NMI/MC context, and quite possibly have other effects.) Special thanks to: - Andy Lutomirski, for the suggestion of using very small stack slots and copy (as opposed to map) the IRET frame there, and for the suggestion to mark them readonly and let the fault promote to #DF. - Konrad Wilk for paravirt fixup and testing. - Borislav Petkov for testing help and useful comments. Reported-by: Brian Gerst Signed-off-by: H. Peter Anvin Link: http://lkml.kernel.org/r/1398816946-3351-1-git-send-email-hpa@linux.intel.com Cc: Konrad Rzeszutek Wilk Cc: Borislav Petkov Cc: Andrew Lutomriski Cc: Linus Torvalds Cc: Dirk Hohndel Cc: Arjan van de Ven Cc: comex Cc: Alexander van Heukelum Cc: Boris Ostrovsky Cc: # consider after upstream merge --- Documentation/x86/x86_64/mm.txt | 2 + arch/x86/include/asm/pgtable_64_types.h | 2 + arch/x86/include/asm/setup.h | 3 + arch/x86/kernel/Makefile | 1 + arch/x86/kernel/entry_64.S | 73 ++++++++++- arch/x86/kernel/espfix_64.c | 208 ++++++++++++++++++++++++++++++++ arch/x86/kernel/ldt.c | 11 -- arch/x86/kernel/smpboot.c | 7 ++ arch/x86/mm/dump_pagetables.c | 44 +++++-- init/main.c | 4 + 10 files changed, 329 insertions(+), 26 deletions(-) create mode 100644 arch/x86/kernel/espfix_64.c (limited to 'arch') diff --git a/Documentation/x86/x86_64/mm.txt b/Documentation/x86/x86_64/mm.txt index c584a51add15..afe68ddbe6a4 100644 --- a/Documentation/x86/x86_64/mm.txt +++ b/Documentation/x86/x86_64/mm.txt @@ -12,6 +12,8 @@ ffffc90000000000 - ffffe8ffffffffff (=45 bits) vmalloc/ioremap space ffffe90000000000 - ffffe9ffffffffff (=40 bits) hole ffffea0000000000 - ffffeaffffffffff (=40 bits) virtual memory map (1TB) ... unused hole ... +ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks +... unused hole ... ffffffff80000000 - ffffffffa0000000 (=512 MB) kernel text mapping, from phys 0 ffffffffa0000000 - ffffffffff5fffff (=1525 MB) module mapping space ffffffffff600000 - ffffffffffdfffff (=8 MB) vsyscalls diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index c883bf726398..7166e25ecb57 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h @@ -61,6 +61,8 @@ typedef struct { pteval_t pte; } pte_t; #define MODULES_VADDR (__START_KERNEL_map + KERNEL_IMAGE_SIZE) #define MODULES_END _AC(0xffffffffff000000, UL) #define MODULES_LEN (MODULES_END - MODULES_VADDR) +#define ESPFIX_PGD_ENTRY _AC(-2, UL) +#define ESPFIX_BASE_ADDR (ESPFIX_PGD_ENTRY << PGDIR_SHIFT) #define EARLY_DYNAMIC_PAGE_TABLES 64 diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index 9264f04a4c55..9e3be3329a7e 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -57,6 +57,9 @@ extern void x86_ce4100_early_setup(void); static inline void x86_ce4100_early_setup(void) { } #endif +extern void init_espfix_bsp(void); +extern void init_espfix_ap(void); + #ifndef _SETUP /* diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f4d96000d33a..1cc3789d99d9 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o obj-y += syscall_$(BITS).o vsyscall_gtod.o obj-$(CONFIG_X86_64) += vsyscall_64.o obj-$(CONFIG_X86_64) += vsyscall_emu_64.o +obj-$(CONFIG_X86_64) += espfix_64.o obj-$(CONFIG_SYSFS) += ksysfs.o obj-y += bootflag.o e820.o obj-y += pci-dma.o quirks.o topology.o kdebugfs.o diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index 1e96c3628bf2..bffaa986cafc 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -58,6 +58,7 @@ #include #include #include +#include #include /* Avoid __ASSEMBLER__'ifying just for this. */ @@ -1040,8 +1041,16 @@ restore_args: RESTORE_ARGS 1,8,1 irq_return: + /* + * Are we returning to a stack segment from the LDT? Note: in + * 64-bit mode SS:RSP on the exception stack is always valid. + */ + testb $4,(SS-RIP)(%rsp) + jnz irq_return_ldt + +irq_return_iret: INTERRUPT_RETURN - _ASM_EXTABLE(irq_return, bad_iret) + _ASM_EXTABLE(irq_return_iret, bad_iret) #ifdef CONFIG_PARAVIRT ENTRY(native_iret) @@ -1049,6 +1058,30 @@ ENTRY(native_iret) _ASM_EXTABLE(native_iret, bad_iret) #endif +irq_return_ldt: + pushq_cfi %rax + pushq_cfi %rdi + SWAPGS + movq PER_CPU_VAR(espfix_waddr),%rdi + movq %rax,(0*8)(%rdi) /* RAX */ + movq (2*8)(%rsp),%rax /* RIP */ + movq %rax,(1*8)(%rdi) + movq (3*8)(%rsp),%rax /* CS */ + movq %rax,(2*8)(%rdi) + movq (4*8)(%rsp),%rax /* RFLAGS */ + movq %rax,(3*8)(%rdi) + movq (6*8)(%rsp),%rax /* SS */ + movq %rax,(5*8)(%rdi) + movq (5*8)(%rsp),%rax /* RSP */ + movq %rax,(4*8)(%rdi) + andl $0xffff0000,%eax + popq_cfi %rdi + orq PER_CPU_VAR(espfix_stack),%rax + SWAPGS + movq %rax,%rsp + popq_cfi %rax + jmp irq_return_iret + .section .fixup,"ax" bad_iret: /* @@ -1110,9 +1143,41 @@ ENTRY(retint_kernel) call preempt_schedule_irq jmp exit_intr #endif - CFI_ENDPROC END(common_interrupt) + + /* + * If IRET takes a fault on the espfix stack, then we + * end up promoting it to a doublefault. In that case, + * modify the stack to make it look like we just entered + * the #GP handler from user space, similar to bad_iret. + */ + ALIGN +__do_double_fault: + XCPT_FRAME 1 RDI+8 + movq RSP(%rdi),%rax /* Trap on the espfix stack? */ + sarq $PGDIR_SHIFT,%rax + cmpl $ESPFIX_PGD_ENTRY,%eax + jne do_double_fault /* No, just deliver the fault */ + cmpl $__KERNEL_CS,CS(%rdi) + jne do_double_fault + movq RIP(%rdi),%rax + cmpq $irq_return_iret,%rax +#ifdef CONFIG_PARAVIRT + je 1f + cmpq $native_iret,%rax +#endif + jne do_double_fault /* This shouldn't happen... */ +1: + movq PER_CPU_VAR(kernel_stack),%rax + subq $(6*8-KERNEL_STACK_OFFSET),%rax /* Reset to original stack */ + movq %rax,RSP(%rdi) + movq $0,(%rax) /* Missing (lost) #GP error code */ + movq $general_protection,RIP(%rdi) + retq + CFI_ENDPROC +END(__do_double_fault) + /* * End of kprobes section */ @@ -1314,7 +1379,7 @@ zeroentry overflow do_overflow zeroentry bounds do_bounds zeroentry invalid_op do_invalid_op zeroentry device_not_available do_device_not_available -paranoiderrorentry double_fault do_double_fault +paranoiderrorentry double_fault __do_double_fault zeroentry coprocessor_segment_overrun do_coprocessor_segment_overrun errorentry invalid_TSS do_invalid_TSS errorentry segment_not_present do_segment_not_present @@ -1601,7 +1666,7 @@ error_sti: */ error_kernelspace: incl %ebx - leaq irq_return(%rip),%rcx + leaq irq_return_iret(%rip),%rcx cmpq %rcx,RIP+8(%rsp) je error_swapgs movl %ecx,%eax /* zero extend */ diff --git a/arch/x86/kernel/espfix_64.c b/arch/x86/kernel/espfix_64.c new file mode 100644 index 000000000000..8a64da36310f --- /dev/null +++ b/arch/x86/kernel/espfix_64.c @@ -0,0 +1,208 @@ +/* ----------------------------------------------------------------------- * + * + * Copyright 2014 Intel Corporation; author: H. Peter Anvin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * ----------------------------------------------------------------------- */ + +/* + * The IRET instruction, when returning to a 16-bit segment, only + * restores the bottom 16 bits of the user space stack pointer. This + * causes some 16-bit software to break, but it also leaks kernel state + * to user space. + * + * This works around this by creating percpu "ministacks", each of which + * is mapped 2^16 times 64K apart. When we detect that the return SS is + * on the LDT, we copy the IRET frame to the ministack and use the + * relevant alias to return to userspace. The ministacks are mapped + * readonly, so if the IRET fault we promote #GP to #DF which is an IST + * vector and thus has its own stack; we then do the fixup in the #DF + * handler. + * + * This file sets up the ministacks and the related page tables. The + * actual ministack invocation is in entry_64.S. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Note: we only need 6*8 = 48 bytes for the espfix stack, but round + * it up to a cache line to avoid unnecessary sharing. + */ +#define ESPFIX_STACK_SIZE (8*8UL) +#define ESPFIX_STACKS_PER_PAGE (PAGE_SIZE/ESPFIX_STACK_SIZE) + +/* There is address space for how many espfix pages? */ +#define ESPFIX_PAGE_SPACE (1UL << (PGDIR_SHIFT-PAGE_SHIFT-16)) + +#define ESPFIX_MAX_CPUS (ESPFIX_STACKS_PER_PAGE * ESPFIX_PAGE_SPACE) +#if CONFIG_NR_CPUS > ESPFIX_MAX_CPUS +# error "Need more than one PGD for the ESPFIX hack" +#endif + +#define PGALLOC_GFP (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO) + +/* This contains the *bottom* address of the espfix stack */ +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, espfix_stack); +DEFINE_PER_CPU_READ_MOSTLY(unsigned long, espfix_waddr); + +/* Initialization mutex - should this be a spinlock? */ +static DEFINE_MUTEX(espfix_init_mutex); + +/* Page allocation bitmap - each page serves ESPFIX_STACKS_PER_PAGE CPUs */ +#define ESPFIX_MAX_PAGES DIV_ROUND_UP(CONFIG_NR_CPUS, ESPFIX_STACKS_PER_PAGE) +static void *espfix_pages[ESPFIX_MAX_PAGES]; + +static __page_aligned_bss pud_t espfix_pud_page[PTRS_PER_PUD] + __aligned(PAGE_SIZE); + +static unsigned int page_random, slot_random; + +/* + * This returns the bottom address of the espfix stack for a specific CPU. + * The math allows for a non-power-of-two ESPFIX_STACK_SIZE, in which case + * we have to account for some amount of padding at the end of each page. + */ +static inline unsigned long espfix_base_addr(unsigned int cpu) +{ + unsigned long page, slot; + unsigned long addr; + + page = (cpu / ESPFIX_STACKS_PER_PAGE) ^ page_random; + slot = (cpu + slot_random) % ESPFIX_STACKS_PER_PAGE; + addr = (page << PAGE_SHIFT) + (slot * ESPFIX_STACK_SIZE); + addr = (addr & 0xffffUL) | ((addr & ~0xffffUL) << 16); + addr += ESPFIX_BASE_ADDR; + return addr; +} + +#define PTE_STRIDE (65536/PAGE_SIZE) +#define ESPFIX_PTE_CLONES (PTRS_PER_PTE/PTE_STRIDE) +#define ESPFIX_PMD_CLONES PTRS_PER_PMD +#define ESPFIX_PUD_CLONES (65536/(ESPFIX_PTE_CLONES*ESPFIX_PMD_CLONES)) + +#define PGTABLE_PROT ((_KERNPG_TABLE & ~_PAGE_RW) | _PAGE_NX) + +static void init_espfix_random(void) +{ + unsigned long rand; + + /* + * This is run before the entropy pools are initialized, + * but this is hopefully better than nothing. + */ + if (!arch_get_random_long(&rand)) { + /* The constant is an arbitrary large prime */ + rdtscll(rand); + rand *= 0xc345c6b72fd16123UL; + } + + slot_random = rand % ESPFIX_STACKS_PER_PAGE; + page_random = (rand / ESPFIX_STACKS_PER_PAGE) + & (ESPFIX_PAGE_SPACE - 1); +} + +void __init init_espfix_bsp(void) +{ + pgd_t *pgd_p; + pteval_t ptemask; + + ptemask = __supported_pte_mask; + + /* Install the espfix pud into the kernel page directory */ + pgd_p = &init_level4_pgt[pgd_index(ESPFIX_BASE_ADDR)]; + pgd_populate(&init_mm, pgd_p, (pud_t *)espfix_pud_page); + + /* Randomize the locations */ + init_espfix_random(); + + /* The rest is the same as for any other processor */ + init_espfix_ap(); +} + +void init_espfix_ap(void) +{ + unsigned int cpu, page; + unsigned long addr; + pud_t pud, *pud_p; + pmd_t pmd, *pmd_p; + pte_t pte, *pte_p; + int n; + void *stack_page; + pteval_t ptemask; + + /* We only have to do this once... */ + if (likely(this_cpu_read(espfix_stack))) + return; /* Already initialized */ + + cpu = smp_processor_id(); + addr = espfix_base_addr(cpu); + page = cpu/ESPFIX_STACKS_PER_PAGE; + + /* Did another CPU already set this up? */ + stack_page = ACCESS_ONCE(espfix_pages[page]); + if (likely(stack_page)) + goto done; + + mutex_lock(&espfix_init_mutex); + + /* Did we race on the lock? */ + stack_page = ACCESS_ONCE(espfix_pages[page]); + if (stack_page) + goto unlock_done; + + ptemask = __supported_pte_mask; + + pud_p = &espfix_pud_page[pud_index(addr)]; + pud = *pud_p; + if (!pud_present(pud)) { + pmd_p = (pmd_t *)__get_free_page(PGALLOC_GFP); + pud = __pud(__pa(pmd_p) | (PGTABLE_PROT & ptemask)); + paravirt_alloc_pud(&init_mm, __pa(pmd_p) >> PAGE_SHIFT); + for (n = 0; n < ESPFIX_PUD_CLONES; n++) + set_pud(&pud_p[n], pud); + } + + pmd_p = pmd_offset(&pud, addr); + pmd = *pmd_p; + if (!pmd_present(pmd)) { + pte_p = (pte_t *)__get_free_page(PGALLOC_GFP); + pmd = __pmd(__pa(pte_p) | (PGTABLE_PROT & ptemask)); + paravirt_alloc_pmd(&init_mm, __pa(pte_p) >> PAGE_SHIFT); + for (n = 0; n < ESPFIX_PMD_CLONES; n++) + set_pmd(&pmd_p[n], pmd); + } + + pte_p = pte_offset_kernel(&pmd, addr); + stack_page = (void *)__get_free_page(GFP_KERNEL); + pte = __pte(__pa(stack_page) | (__PAGE_KERNEL_RO & ptemask)); + paravirt_alloc_pte(&init_mm, __pa(stack_page) >> PAGE_SHIFT); + for (n = 0; n < ESPFIX_PTE_CLONES; n++) + set_pte(&pte_p[n*PTE_STRIDE], pte); + + /* Job is done for this CPU and any CPU which shares this page */ + ACCESS_ONCE(espfix_pages[page]) = stack_page; + +unlock_done: + mutex_unlock(&espfix_init_mutex); +done: + this_cpu_write(espfix_stack, addr); + this_cpu_write(espfix_waddr, (unsigned long)stack_page + + (addr & ~PAGE_MASK)); +} diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c index af1d14a9ebda..ebc987398923 100644 --- a/arch/x86/kernel/ldt.c +++ b/arch/x86/kernel/ldt.c @@ -229,17 +229,6 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode) } } - /* - * On x86-64 we do not support 16-bit segments due to - * IRET leaking the high bits of the kernel stack address. - */ -#ifdef CONFIG_X86_64 - if (!ldt_info.seg_32bit) { - error = -EINVAL; - goto out_unlock; - } -#endif - fill_ldt(&ldt, &ldt_info); if (oldmode) ldt.avl = 0; diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 34826934d4a7..61a5350850fb 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -243,6 +243,13 @@ static void notrace start_secondary(void *unused) */ check_tsc_sync_target(); + /* + * Enable the espfix hack for this CPU + */ +#ifdef CONFIG_X86_64 + init_espfix_ap(); +#endif + /* * We need to hold vector_lock so there the set of online cpus * does not change while we are assigning vectors to cpus. Holding diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c index 20621d753d5f..167ffcac16ed 100644 --- a/arch/x86/mm/dump_pagetables.c +++ b/arch/x86/mm/dump_pagetables.c @@ -30,12 +30,14 @@ struct pg_state { unsigned long start_address; unsigned long current_address; const struct addr_marker *marker; + unsigned long lines; bool to_dmesg; }; struct addr_marker { unsigned long start_address; const char *name; + unsigned long max_lines; }; /* indices for address_markers; keep sync'd w/ address_markers below */ @@ -46,6 +48,7 @@ enum address_markers_idx { LOW_KERNEL_NR, VMALLOC_START_NR, VMEMMAP_START_NR, + ESPFIX_START_NR, HIGH_KERNEL_NR, MODULES_VADDR_NR, MODULES_END_NR, @@ -68,6 +71,7 @@ static struct addr_marker address_markers[] = { { PAGE_OFFSET, "Low Kernel Mapping" }, { VMALLOC_START, "vmalloc() Area" }, { VMEMMAP_START, "Vmemmap" }, + { ESPFIX_BASE_ADDR, "ESPfix Area", 16 }, { __START_KERNEL_map, "High Kernel Mapping" }, { MODULES_VADDR, "Modules" }, { MODULES_END, "End Modules" }, @@ -182,7 +186,7 @@ static void note_page(struct seq_file *m, struct pg_state *st, pgprot_t new_prot, int level) { pgprotval_t prot, cur; - static const char units[] = "KMGTPE"; + static const char units[] = "BKMGTPE"; /* * If we have a "break" in the series, we need to flush the state that @@ -197,6 +201,7 @@ static void note_page(struct seq_file *m, struct pg_state *st, st->current_prot = new_prot; st->level = level; st->marker = address_markers; + st->lines = 0; pt_dump_seq_printf(m, st->to_dmesg, "---[ %s ]---\n", st->marker->name); } else if (prot != cur || level != st->level || @@ -208,17 +213,24 @@ static void note_page(struct seq_file *m, struct pg_state *st, /* * Now print the actual finished series */ - pt_dump_seq_printf(m, st->to_dmesg, "0x%0*lx-0x%0*lx ", - width, st->start_address, - width, st->current_address); - - delta = (st->current_address - st->start_address) >> 10; - while (!(delta & 1023) && unit[1]) { - delta >>= 10; - unit++; + if (!st->marker->max_lines || + st->lines < st->marker->max_lines) { + pt_dump_seq_printf(m, st->to_dmesg, + "0x%0*lx-0x%0*lx ", + width, st->start_address, + width, st->current_address); + + delta = st->current_address - st->start_address; + while (!(delta & 1023) && unit[1]) { + delta >>= 10; + unit++; + } + pt_dump_cont_printf(m, st->to_dmesg, "%9lu%c ", + delta, *unit); + printk_prot(m, st->current_prot, st->level, + st->to_dmesg); } - pt_dump_cont_printf(m, st->to_dmesg, "%9lu%c ", delta, *unit); - printk_prot(m, st->current_prot, st->level, st->to_dmesg); + st->lines++; /* * We print markers for special areas of address space, @@ -226,7 +238,17 @@ static void note_page(struct seq_file *m, struct pg_state *st, * This helps in the interpretation. */ if (st->current_address >= st->marker[1].start_address) { + if (st->marker->max_lines && + st->lines > st->marker->max_lines) { + unsigned long nskip = + st->lines - st->marker->max_lines; + pt_dump_seq_printf(m, st->to_dmesg, + "... %lu entr%s skipped ... \n", + nskip, + nskip == 1 ? "y" : "ies"); + } st->marker++; + st->lines = 0; pt_dump_seq_printf(m, st->to_dmesg, "---[ %s ]---\n", st->marker->name); } diff --git a/init/main.c b/init/main.c index 9c7fd4c9249f..70fc00e7db06 100644 --- a/init/main.c +++ b/init/main.c @@ -616,6 +616,10 @@ asmlinkage void __init start_kernel(void) #ifdef CONFIG_X86 if (efi_enabled(EFI_RUNTIME_SERVICES)) efi_enter_virtual_mode(); +#endif +#ifdef CONFIG_X86_64 + /* Should be run before the first non-init thread is created */ + init_espfix_bsp(); #endif thread_info_cache_init(); cred_init(); -- cgit v1.2.3 From 246f2d2ee1d715e1077fc47d61c394569c8ee692 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Wed, 30 Apr 2014 14:03:25 -0700 Subject: x86-32, espfix: Remove filter for espfix32 due to race It is not safe to use LAR to filter when to go down the espfix path, because the LDT is per-process (rather than per-thread) and another thread might change the descriptors behind our back. Fortunately it is always *safe* (if a bit slow) to go down the espfix path, and a 32-bit LDT stack segment is extremely rare. Signed-off-by: H. Peter Anvin Link: http://lkml.kernel.org/r/1398816946-3351-1-git-send-email-hpa@linux.intel.com Cc: # consider after upstream merge --- arch/x86/kernel/entry_32.S | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S index a2a4f4697889..2780b8f3b96c 100644 --- a/arch/x86/kernel/entry_32.S +++ b/arch/x86/kernel/entry_32.S @@ -551,11 +551,6 @@ ENTRY(iret_exc) CFI_RESTORE_STATE ldt_ss: - larl PT_OLDSS(%esp), %eax - jnz restore_nocheck - testl $0x00400000, %eax # returning to 32bit stack? - jnz restore_nocheck # allright, normal return - #ifdef CONFIG_PARAVIRT /* * The kernel can't run on a non-flat stack if paravirt mode -- cgit v1.2.3 From e1fe9ed8d2a4937510d0d60e20705035c2609aea Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Thu, 1 May 2014 14:12:23 -0700 Subject: x86, espfix: Move espfix definitions into a separate header file Sparse warns that the percpu variables aren't declared before they are defined. Rather than hacking around it, move espfix definitions into a proper header file. Reported-by: Fengguang Wu Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/espfix.h | 16 ++++++++++++++++ arch/x86/include/asm/setup.h | 5 ++--- arch/x86/kernel/espfix_64.c | 1 + 3 files changed, 19 insertions(+), 3 deletions(-) create mode 100644 arch/x86/include/asm/espfix.h (limited to 'arch') diff --git a/arch/x86/include/asm/espfix.h b/arch/x86/include/asm/espfix.h new file mode 100644 index 000000000000..729051c82b02 --- /dev/null +++ b/arch/x86/include/asm/espfix.h @@ -0,0 +1,16 @@ +#ifdef _ASM_X86_ESPFIX_H +#define _ASM_X86_ESPFIX_H + +#ifdef CONFIG_X86_64 + +#include + +DECLARE_PER_CPU_READ_MOSTLY(unsigned long, espfix_stack); +DECLARE_PER_CPU_READ_MOSTLY(unsigned long, espfix_waddr); + +extern void init_espfix_bsp(void); +extern void init_espfix_ap(void); + +#endif /* CONFIG_X86_64 */ + +#endif /* _ASM_X86_ESPFIX_H */ diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index 9e3be3329a7e..ff4e7b236e21 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -57,11 +57,10 @@ extern void x86_ce4100_early_setup(void); static inline void x86_ce4100_early_setup(void) { } #endif -extern void init_espfix_bsp(void); -extern void init_espfix_ap(void); - #ifndef _SETUP +#include + /* * This is set up by the setup-routine at boot-time */ diff --git a/arch/x86/kernel/espfix_64.c b/arch/x86/kernel/espfix_64.c index 8a64da36310f..6afbb16e9b79 100644 --- a/arch/x86/kernel/espfix_64.c +++ b/arch/x86/kernel/espfix_64.c @@ -40,6 +40,7 @@ #include #include #include +#include /* * Note: we only need 6*8 = 48 bytes for the espfix stack, but round -- cgit v1.2.3 From 2af0d93762e91d4496cc2e63761c70ae9f50f997 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 2 May 2014 02:56:33 +0400 Subject: ARM: shmobile: henninger: specify EXTAL frequency When creating the initial device tree for the Henninger board, I've overlooked that EXTAL frequency needs to be overridden there. The 'sh-sci' driver managed to work somehow but the SDHI driver that I've tried to enable just hanged with the default EXTAL frequency of 0... Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-henninger.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index 6e67cea3104c..0a655231d531 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -35,6 +35,10 @@ }; }; +&extal_clk { + clock-frequency = <20000000>; +}; + &pfc { scif0_pins: serial0 { renesas,groups = "scif0_data_d"; -- cgit v1.2.3 From 6f3df63ffb8b5d1634646fbeb3a018fcbb11e596 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Fri, 2 May 2014 16:59:08 +0900 Subject: ARM: tegra: add Tegra Note 7 device tree Tegra Note 7 is a consumer tablet embedding a Tegra 4 SoC with 1GB RAM and a 720p panel. The following hardware is enabled by this device tree: UART, eMMC, USB (needs external power), PMIC, backlight, DSI panel, keys. SD card, HDMI, charger, self-powered USB, audio, wifi, bluetooth are not yet supported but might be by future patches (likely in that order). Touch panel, sensors & cameras will probably never be supported. Pinctrl is not set yet, as the bootloader-provided values allow us to use the currently supported hardware. Initrd addresses are hardcoded to match the static values used by the bootloader, since it won't add them for us. All the same, a kernel command-line is provided to replace the one passed by the bootloader which is filled with garbage. Signed-off-by: Alexandre Courbot [treding@nvidia.com: DT fixes, DSI panel support] Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/tegra114-tn7.dts | 348 +++++++++++++++++++++++++++++++++++++ 2 files changed, 349 insertions(+) create mode 100644 arch/arm/boot/dts/tegra114-tn7.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d96b2c2ec429..d3281365a30a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -368,6 +368,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ tegra114-dalmore.dtb \ + tegra114-tn7.dtb \ tegra124-jetson-tk1.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts new file mode 100644 index 000000000000..963662145635 --- /dev/null +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -0,0 +1,348 @@ +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "Tegra Note 7"; + compatible = "nvidia,tn7", "nvidia,tegra114"; + + chosen { + /* TN7's bootloader's arguments need to be overridden */ + bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2"; + /* TN7's bootloader will place initrd at this address */ + linux,initrd-start = <0x82000000>; + linux,initrd-end = <0x82800000>; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + + memory { + /* memory >= 0x37e00000 is reserved for firmware usage */ + reg = <0x80000000 0x37e00000>; + }; + + host1x@50000000 { + dsi@54300000 { + status = "okay"; + + vdd-supply = <&vdd_1v2_ap>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + power-supply = <&vdd_lcd>; + backlight = <&backlight>; + }; + }; + }; + + serial@70006300 { + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + palmas: pmic@58 { + compatible = "ti,palmas"; + reg = <0x58>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmic { + compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; + + ldoln-in-supply = <&vdd_smps10_out2>; + + regulators { + smps123 { + regulator-name = "vd-cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45 { + regulator-name = "vd-soc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6 { + regulator-name = "va-lcd-hv"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7 { + regulator-name = "vd-ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: smps8 { + regulator-name = "vs-pmu-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_2v9_sys: smps9 { + regulator-name = "vs-sys-2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out1: smps10_out1 { + regulator-name = "vd-smps10-out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_smps10_out2: smps10_out2 { + regulator-name = "vd-smps10-out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1 { + regulator-name = "va-pllx"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v2_ap: ldo2 { + regulator-name = "va-ap-1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3 { + regulator-name = "vd-fuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4 { + regulator-name = "vd-ts-hv"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5 { + regulator-name = "va-cam2-hv"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo6 { + regulator-name = "va-sns-hv"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo7 { + regulator-name = "va-cam1-hv"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo8 { + regulator-name = "va-ap-rtc"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + ti,enable-ldo8-tracking; + regulator-always-on; + regulator-boot-on; + }; + + ldo9 { + regulator-name = "vi-sdcard"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + ldousb { + regulator-name = "avdd-usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln { + regulator-name = "va-hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 0>; + }; + + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + }; + + /* eMMC */ + sdhci@78000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vdd_1v8>; + non-removable; + }; + + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + interrupts = ; + /* Should be changed to "otg" once we have vbus_supply */ + /* As of now, USB devices need to be powered externally */ + dr_mode = "host"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 1 40000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + power-supply = <&lcd_bl_en>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + }; + + volume_down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume_up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* FIXME: output of BQ24192 */ + vs_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "VS_SYS"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + lcd_bl_en: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "VDD_LCD_BL"; + regulator-min-microvolt = <16500000>; + regulator-max-microvolt = <16500000>; + gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vs_sys>; + regulator-boot-on; + }; + + vdd_lcd: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "VD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_1v8>; + regulator-boot-on; + }; + }; +}; -- cgit v1.2.3 From 20b68535cd27183ebd3651ff313afb2b97dac941 Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Fri, 2 May 2014 11:33:51 -0700 Subject: x86, espfix: Fix broken header guard Header guard is #ifndef, not #ifdef... Reported-by: Fengguang Wu Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/espfix.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/include/asm/espfix.h b/arch/x86/include/asm/espfix.h index 729051c82b02..99efebb2f69d 100644 --- a/arch/x86/include/asm/espfix.h +++ b/arch/x86/include/asm/espfix.h @@ -1,4 +1,4 @@ -#ifdef _ASM_X86_ESPFIX_H +#ifndef _ASM_X86_ESPFIX_H #define _ASM_X86_ESPFIX_H #ifdef CONFIG_X86_64 -- cgit v1.2.3 From c81c8a1eeede61e92a15103748c23d100880cc8a Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Fri, 2 May 2014 11:18:41 -0700 Subject: x86, ioremap: Speed up check for RAM pages In __ioremap_caller() (the guts of ioremap), we loop over the range of pfns being remapped and checks each one individually with page_is_ram(). For large ioremaps, this can be very slow. For example, we have a device with a 256 GiB PCI BAR, and ioremapping this BAR can take 20+ seconds -- sometimes long enough to trigger the soft lockup detector! Internally, page_is_ram() calls walk_system_ram_range() on a single page. Instead, we can make a single call to walk_system_ram_range() from __ioremap_caller(), and do our further checks only for any RAM pages that we find. For the common case of MMIO, this saves an enormous amount of work, since the range being ioremapped doesn't intersect system RAM at all. With this change, ioremap on our 256 GiB BAR takes less than 1 second. Signed-off-by: Roland Dreier Link: http://lkml.kernel.org/r/1399054721-1331-1-git-send-email-roland@kernel.org Signed-off-by: H. Peter Anvin --- arch/x86/mm/ioremap.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 597ac155c91c..bc7527e109c8 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -50,6 +50,21 @@ int ioremap_change_attr(unsigned long vaddr, unsigned long size, return err; } +static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages, + void *arg) +{ + unsigned long i; + + for (i = 0; i < nr_pages; ++i) + if (pfn_valid(start_pfn + i) && + !PageReserved(pfn_to_page(start_pfn + i))) + return 1; + + WARN_ONCE(1, "ioremap on RAM pfn 0x%lx\n", start_pfn); + + return 0; +} + /* * Remap an arbitrary physical address space into the kernel virtual * address space. Needed when the kernel wants to access high addresses @@ -93,14 +108,11 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr, /* * Don't allow anybody to remap normal RAM that we're using.. */ + pfn = phys_addr >> PAGE_SHIFT; last_pfn = last_addr >> PAGE_SHIFT; - for (pfn = phys_addr >> PAGE_SHIFT; pfn <= last_pfn; pfn++) { - int is_ram = page_is_ram(pfn); - - if (is_ram && pfn_valid(pfn) && !PageReserved(pfn_to_page(pfn))) - return NULL; - WARN_ON_ONCE(is_ram); - } + if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL, + __ioremap_check_ram) == 1) + return NULL; /* * Mappings have to be page-aligned -- cgit v1.2.3 From 197725de65477bc8509b41388157c1a2283542bb Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Sun, 4 May 2014 10:00:49 -0700 Subject: x86, espfix: Make espfix64 a Kconfig option, fix UML Make espfix64 a hidden Kconfig option. This fixes the x86-64 UML build which had broken due to the non-existence of init_espfix_bsp() in UML: since UML uses its own Kconfig, this option does not appear in the UML build. This also makes it possible to make support for 16-bit segments a configuration option, for the people who want to minimize the size of the kernel. Reported-by: Ingo Molnar Signed-off-by: H. Peter Anvin Cc: Richard Weinberger Link: http://lkml.kernel.org/r/1398816946-3351-1-git-send-email-hpa@linux.intel.com --- arch/x86/Kconfig | 4 ++++ arch/x86/kernel/Makefile | 2 +- arch/x86/kernel/smpboot.c | 2 +- init/main.c | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 25d2c6f7325e..9a952a572585 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -914,6 +914,10 @@ config VM86 XFree86 to initialize some video cards via BIOS. Disabling this option saves about 6k. +config X86_ESPFIX64 + def_bool y + depends on X86_64 + config TOSHIBA tristate "Toshiba Laptop support" depends on X86_32 diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 1cc3789d99d9..491ef3e59850 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_X86_64) += sys_x86_64.o x8664_ksyms_64.o obj-y += syscall_$(BITS).o vsyscall_gtod.o obj-$(CONFIG_X86_64) += vsyscall_64.o obj-$(CONFIG_X86_64) += vsyscall_emu_64.o -obj-$(CONFIG_X86_64) += espfix_64.o +obj-$(CONFIG_X86_ESPFIX64) += espfix_64.o obj-$(CONFIG_SYSFS) += ksysfs.o obj-y += bootflag.o e820.o obj-y += pci-dma.o quirks.o topology.o kdebugfs.o diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 61a5350850fb..5d93ac1b72db 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -246,7 +246,7 @@ static void notrace start_secondary(void *unused) /* * Enable the espfix hack for this CPU */ -#ifdef CONFIG_X86_64 +#ifdef CONFIG_X86_ESPFIX64 init_espfix_ap(); #endif diff --git a/init/main.c b/init/main.c index 70fc00e7db06..58c132d7de4b 100644 --- a/init/main.c +++ b/init/main.c @@ -617,7 +617,7 @@ asmlinkage void __init start_kernel(void) if (efi_enabled(EFI_RUNTIME_SERVICES)) efi_enter_virtual_mode(); #endif -#ifdef CONFIG_X86_64 +#ifdef CONFIG_X86_ESPFIX64 /* Should be run before the first non-init thread is created */ init_espfix_bsp(); #endif -- cgit v1.2.3 From 34273f41d57ee8d854dcd2a1d754cbb546cb548f Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Sun, 4 May 2014 10:36:22 -0700 Subject: x86, espfix: Make it possible to disable 16-bit support Embedded systems, which may be very memory-size-sensitive, are extremely unlikely to ever encounter any 16-bit software, so make it a CONFIG_EXPERT option to turn off support for any 16-bit software whatsoever. Signed-off-by: H. Peter Anvin Link: http://lkml.kernel.org/r/1398816946-3351-1-git-send-email-hpa@linux.intel.com --- arch/x86/Kconfig | 23 ++++++++++++++++++----- arch/x86/kernel/entry_32.S | 12 ++++++++++++ arch/x86/kernel/entry_64.S | 8 ++++++++ arch/x86/kernel/ldt.c | 5 +++++ 4 files changed, 43 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 9a952a572585..956c7702471e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -909,14 +909,27 @@ config VM86 default y depends on X86_32 ---help--- - This option is required by programs like DOSEMU to run 16-bit legacy - code on X86 processors. It also may be needed by software like - XFree86 to initialize some video cards via BIOS. Disabling this - option saves about 6k. + This option is required by programs like DOSEMU to run + 16-bit real mode legacy code on x86 processors. It also may + be needed by software like XFree86 to initialize some video + cards via BIOS. Disabling this option saves about 6K. + +config X86_16BIT + bool "Enable support for 16-bit segments" if EXPERT + default y + ---help--- + This option is required by programs like Wine to run 16-bit + protected mode legacy code on x86 processors. Disabling + this option saves about 300 bytes on i386, or around 6K text + plus 16K runtime memory on x86-64, + +config X86_ESPFIX32 + def_bool y + depends on X86_16BIT && X86_32 config X86_ESPFIX64 def_bool y - depends on X86_64 + depends on X86_16BIT && X86_64 config TOSHIBA tristate "Toshiba Laptop support" diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S index 2780b8f3b96c..98313ffaae6a 100644 --- a/arch/x86/kernel/entry_32.S +++ b/arch/x86/kernel/entry_32.S @@ -527,6 +527,7 @@ syscall_exit: restore_all: TRACE_IRQS_IRET restore_all_notrace: +#ifdef CONFIG_X86_ESPFIX32 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS # Warning: PT_OLDSS(%esp) contains the wrong/random values if we # are returning to the kernel. @@ -537,6 +538,7 @@ restore_all_notrace: cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax CFI_REMEMBER_STATE je ldt_ss # returning to user-space with LDT SS +#endif restore_nocheck: RESTORE_REGS 4 # skip orig_eax/error_code irq_return: @@ -549,6 +551,7 @@ ENTRY(iret_exc) .previous _ASM_EXTABLE(irq_return,iret_exc) +#ifdef CONFIG_X86_ESPFIX32 CFI_RESTORE_STATE ldt_ss: #ifdef CONFIG_PARAVIRT @@ -592,6 +595,7 @@ ldt_ss: lss (%esp), %esp /* switch to espfix segment */ CFI_ADJUST_CFA_OFFSET -8 jmp restore_nocheck +#endif CFI_ENDPROC ENDPROC(system_call) @@ -699,6 +703,7 @@ END(syscall_badsys) * the high word of the segment base from the GDT and swiches to the * normal stack and adjusts ESP with the matching offset. */ +#ifdef CONFIG_X86_ESPFIX32 /* fixup the stack */ mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */ mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */ @@ -708,8 +713,10 @@ END(syscall_badsys) pushl_cfi %eax lss (%esp), %esp /* switch to the normal stack segment */ CFI_ADJUST_CFA_OFFSET -8 +#endif .endm .macro UNWIND_ESPFIX_STACK +#ifdef CONFIG_X86_ESPFIX32 movl %ss, %eax /* see if on espfix stack */ cmpw $__ESPFIX_SS, %ax @@ -720,6 +727,7 @@ END(syscall_badsys) /* switch to normal stack */ FIXUP_ESPFIX_STACK 27: +#endif .endm /* @@ -1350,11 +1358,13 @@ END(debug) ENTRY(nmi) RING0_INT_FRAME ASM_CLAC +#ifdef CONFIG_X86_ESPFIX32 pushl_cfi %eax movl %ss, %eax cmpw $__ESPFIX_SS, %ax popl_cfi %eax je nmi_espfix_stack +#endif cmpl $ia32_sysenter_target,(%esp) je nmi_stack_fixup pushl_cfi %eax @@ -1394,6 +1404,7 @@ nmi_debug_stack_check: FIX_STACK 24, nmi_stack_correct, 1 jmp nmi_stack_correct +#ifdef CONFIG_X86_ESPFIX32 nmi_espfix_stack: /* We have a RING0_INT_FRAME here. * @@ -1415,6 +1426,7 @@ nmi_espfix_stack: lss 12+4(%esp), %esp # back to espfix stack CFI_ADJUST_CFA_OFFSET -24 jmp irq_return +#endif CFI_ENDPROC END(nmi) diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index bffaa986cafc..da0b9bdcc32e 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S @@ -1045,8 +1045,10 @@ irq_return: * Are we returning to a stack segment from the LDT? Note: in * 64-bit mode SS:RSP on the exception stack is always valid. */ +#ifdef CONFIG_X86_ESPFIX64 testb $4,(SS-RIP)(%rsp) jnz irq_return_ldt +#endif irq_return_iret: INTERRUPT_RETURN @@ -1058,6 +1060,7 @@ ENTRY(native_iret) _ASM_EXTABLE(native_iret, bad_iret) #endif +#ifdef CONFIG_X86_ESPFIX64 irq_return_ldt: pushq_cfi %rax pushq_cfi %rdi @@ -1081,6 +1084,7 @@ irq_return_ldt: movq %rax,%rsp popq_cfi %rax jmp irq_return_iret +#endif .section .fixup,"ax" bad_iret: @@ -1152,6 +1156,7 @@ END(common_interrupt) * modify the stack to make it look like we just entered * the #GP handler from user space, similar to bad_iret. */ +#ifdef CONFIG_X86_ESPFIX64 ALIGN __do_double_fault: XCPT_FRAME 1 RDI+8 @@ -1177,6 +1182,9 @@ __do_double_fault: retq CFI_ENDPROC END(__do_double_fault) +#else +# define __do_double_fault do_double_fault +#endif /* * End of kprobes section diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c index ebc987398923..c37886d759cc 100644 --- a/arch/x86/kernel/ldt.c +++ b/arch/x86/kernel/ldt.c @@ -229,6 +229,11 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode) } } + if (!IS_ENABLED(CONFIG_X86_16BIT) && !ldt_info.seg_32bit) { + error = -EINVAL; + goto out_unlock; + } + fill_ldt(&ldt, &ldt_info); if (oldmode) ldt.avl = 0; -- cgit v1.2.3 From 7b36efd0868b8a9c1a51bc1c9117fcb50f44f7b8 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:29 +0200 Subject: ARM: dts: kirkwood: add node labels This adds missing node labels to Kirkwood common and SoC specific nodes to allow to reference them more easily. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-3-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6192.dtsi | 10 +++++----- arch/arm/boot/dts/kirkwood-6281.dtsi | 10 +++++----- arch/arm/boot/dts/kirkwood-6282.dtsi | 16 ++++++++-------- arch/arm/boot/dts/kirkwood.dtsi | 16 ++++++++-------- 4 files changed, 26 insertions(+), 26 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 3916937d6818..294a6fa0208c 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -1,6 +1,6 @@ / { mbus { - pcie-controller { + pciec: pcie-controller { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; @@ -15,7 +15,7 @@ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -76,14 +76,14 @@ }; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; clocks = <&gate_clk 7>; }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; @@ -92,7 +92,7 @@ status = "disabled"; }; - mvsdio@90000 { + sdio: mvsdio@90000 { compatible = "marvell,orion-sdio"; reg = <0x90000 0x200>; interrupts = <28>; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 416d96e1302f..2560cbbdb0b3 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -1,6 +1,6 @@ / { mbus { - pcie-controller { + pciec: pcie-controller { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; @@ -15,7 +15,7 @@ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -76,14 +76,14 @@ }; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; clocks = <&gate_clk 7>; }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; @@ -94,7 +94,7 @@ status = "disabled"; }; - mvsdio@90000 { + sdio: mvsdio@90000 { compatible = "marvell,orion-sdio"; reg = <0x90000 0x200>; interrupts = <28>; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 2902e0d7971d..f4b4786b9a01 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -1,6 +1,6 @@ / { mbus { - pcie-controller { + pciec: pcie-controller { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; @@ -19,7 +19,7 @@ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; - pcie@1,0 { + pcie0: pcie@1,0 { device_type = "pci"; assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; reg = <0x0800 0 0 0 0>; @@ -36,7 +36,7 @@ status = "disabled"; }; - pcie@2,0 { + pcie1: pcie@2,0 { device_type = "pci"; assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; reg = <0x1000 0 0 0 0>; @@ -104,20 +104,20 @@ }; }; - thermal@10078 { + thermal: thermal@10078 { compatible = "marvell,kirkwood-thermal"; reg = <0x10078 0x4>; status = "okay"; }; - rtc@10300 { + rtc: rtc@10300 { compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; reg = <0x10300 0x20>; interrupts = <53>; clocks = <&gate_clk 7>; }; - i2c@11100 { + i2c1: i2c@11100 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; @@ -128,7 +128,7 @@ status = "disabled"; }; - sata@80000 { + sata: sata@80000 { compatible = "marvell,orion-sata"; reg = <0x80000 0x5000>; interrupts = <21>; @@ -139,7 +139,7 @@ status = "disabled"; }; - mvsdio@90000 { + sdio: mvsdio@90000 { compatible = "marvell,orion-sdio"; reg = <0x90000 0x200>; interrupts = <28>; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 90384587c278..2570e0f1673f 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -40,7 +40,7 @@ pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ - crypto@0301 { + cesa: crypto@0301 { compatible = "marvell,orion-crypto"; reg = , ; @@ -77,7 +77,7 @@ #clock-cells = <1>; }; - spi@10600 { + spi0: spi@10600 { compatible = "marvell,orion-spi"; #address-cells = <1>; #size-cells = <0>; @@ -123,7 +123,7 @@ status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; reg-shift = <2>; @@ -132,7 +132,7 @@ status = "disabled"; }; - serial@12100 { + uart1: serial@12100 { compatible = "ns16550a"; reg = <0x12100 0x100>; reg-shift = <2>; @@ -146,7 +146,7 @@ reg = <0x20000 0x80>, <0x1500 0x20>; }; - system-controller@20000 { + sysc: system-controller@20000 { compatible = "marvell,orion-system-controller"; reg = <0x20000 0x120>; }; @@ -196,7 +196,7 @@ status = "okay"; }; - ehci@50000 { + usb0: ehci@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x1000>; interrupts = <19>; @@ -204,7 +204,7 @@ status = "okay"; }; - xor@60800 { + dma0: xor@60800 { compatible = "marvell,orion-xor"; reg = <0x60800 0x100 0x60A00 0x100>; @@ -224,7 +224,7 @@ }; }; - xor@60900 { + dma1: xor@60900 { compatible = "marvell,orion-xor"; reg = <0x60900 0x100 0x60B00 0x100>; -- cgit v1.2.3 From ab8336147b95336c5fc58433dcb8b2e6c8eb96e9 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:30 +0200 Subject: ARM: dts: kirkwood: add stdout-path property to all boards ePAPR allows to reference the device used for console output by stdout-path property. With node labels for Kirkwood UART0, now reference it on all Kirkwood boards that already have ttyS0 in their bootargs property. While at it, fix some whitespace issues on mplcec4's chosen node (there are more, but we only fix the chosen node now) Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-4-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-b3.dts | 1 + arch/arm/boot/dts/kirkwood-cloudbox.dts | 1 + arch/arm/boot/dts/kirkwood-db.dtsi | 1 + arch/arm/boot/dts/kirkwood-dns320.dts | 1 + arch/arm/boot/dts/kirkwood-dns325.dts | 1 + arch/arm/boot/dts/kirkwood-dockstar.dts | 1 + arch/arm/boot/dts/kirkwood-dreamplug.dts | 1 + arch/arm/boot/dts/kirkwood-ds109.dts | 1 + arch/arm/boot/dts/kirkwood-ds110jv10.dts | 1 + arch/arm/boot/dts/kirkwood-ds111.dts | 1 + arch/arm/boot/dts/kirkwood-ds112.dts | 1 + arch/arm/boot/dts/kirkwood-ds209.dts | 1 + arch/arm/boot/dts/kirkwood-ds210.dts | 1 + arch/arm/boot/dts/kirkwood-ds212.dts | 1 + arch/arm/boot/dts/kirkwood-ds212j.dts | 1 + arch/arm/boot/dts/kirkwood-ds409.dts | 1 + arch/arm/boot/dts/kirkwood-ds409slim.dts | 1 + arch/arm/boot/dts/kirkwood-ds411.dts | 1 + arch/arm/boot/dts/kirkwood-ds411j.dts | 1 + arch/arm/boot/dts/kirkwood-ds411slim.dts | 1 + arch/arm/boot/dts/kirkwood-goflexnet.dts | 1 + arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 1 + arch/arm/boot/dts/kirkwood-ib62x0.dts | 1 + arch/arm/boot/dts/kirkwood-iconnect.dts | 1 + arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 1 + arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 1 + arch/arm/boot/dts/kirkwood-laplug.dts | 1 + arch/arm/boot/dts/kirkwood-lsxl.dtsi | 1 + arch/arm/boot/dts/kirkwood-mplcec4.dts | 7 ++++--- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 1 + arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 1 + arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 1 + arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 1 + arch/arm/boot/dts/kirkwood-nsa310.dts | 1 + arch/arm/boot/dts/kirkwood-nsa310a.dts | 1 + arch/arm/boot/dts/kirkwood-nsa320.dts | 1 + arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 1 + arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 1 + arch/arm/boot/dts/kirkwood-rd88f6192.dts | 1 + arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 1 + arch/arm/boot/dts/kirkwood-rs212.dts | 1 + arch/arm/boot/dts/kirkwood-rs409.dts | 1 + arch/arm/boot/dts/kirkwood-rs411.dts | 1 + arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 1 + arch/arm/boot/dts/kirkwood-t5325.dts | 1 + arch/arm/boot/dts/kirkwood-topkick.dts | 1 + arch/arm/boot/dts/kirkwood-ts219.dtsi | 1 + 47 files changed, 50 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index 40791053106b..86073f4f31ac 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -30,6 +30,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 0e06fd3cee4d..61212692740e 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 02d1225ef99f..22df970df2a1 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -22,6 +22,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index bf7fe8ab88f4..3210daeb264c 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -13,6 +13,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts index cb9978c652f2..5e586ed04c58 100644 --- a/arch/arm/boot/dts/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/kirkwood-dns325.dts @@ -13,6 +13,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index f31312ebd0d6..d703f3eeef1c 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index ef3463e0ae19..8ed737e9aa2f 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts index 772092c94ca3..d4bcc1c7f6b3 100644 --- a/arch/arm/boot/dts/kirkwood-ds109.dts +++ b/arch/arm/boot/dts/kirkwood-ds109.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts index aabafbe0da4c..95bf83b91b4a 100644 --- a/arch/arm/boot/dts/kirkwood-ds110jv10.dts +++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts index 16ec7fbab573..61f47fbe44d0 100644 --- a/arch/arm/boot/dts/kirkwood-ds111.dts +++ b/arch/arm/boot/dts/kirkwood-ds111.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts index cff1b2388765..bf4143c6cb8f 100644 --- a/arch/arm/boot/dts/kirkwood-ds112.dts +++ b/arch/arm/boot/dts/kirkwood-ds112.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts index 330411993d38..6d25093a9ac4 100644 --- a/arch/arm/boot/dts/kirkwood-ds209.dts +++ b/arch/arm/boot/dts/kirkwood-ds209.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts index 6052eaa37d4f..2f1933efcac1 100644 --- a/arch/arm/boot/dts/kirkwood-ds210.dts +++ b/arch/arm/boot/dts/kirkwood-ds210.dts @@ -26,6 +26,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts index 7f76cd30e84e..99afd462f956 100644 --- a/arch/arm/boot/dts/kirkwood-ds212.dts +++ b/arch/arm/boot/dts/kirkwood-ds212.dts @@ -27,6 +27,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts index 1f83a00f1f74..f5c4213fc67c 100644 --- a/arch/arm/boot/dts/kirkwood-ds212j.dts +++ b/arch/arm/boot/dts/kirkwood-ds212j.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts index 0a573add44a2..e80a962ebba0 100644 --- a/arch/arm/boot/dts/kirkwood-ds409.dts +++ b/arch/arm/boot/dts/kirkwood-ds409.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-15-18 { diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts index 1848a6245fd3..cae5af4b88b5 100644 --- a/arch/arm/boot/dts/kirkwood-ds409slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-32-35 { diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts index a1737b4311c6..623cd4a37d71 100644 --- a/arch/arm/boot/dts/kirkwood-ds411.dts +++ b/arch/arm/boot/dts/kirkwood-ds411.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts index 0cde914eceae..3348e330f074 100644 --- a/arch/arm/boot/dts/kirkwood-ds411j.dts +++ b/arch/arm/boot/dts/kirkwood-ds411j.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-15-18 { diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts index aef0cadc2c78..a0a1fad8b4de 100644 --- a/arch/arm/boot/dts/kirkwood-ds411slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-1 { diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index eb9329420107..5e39cc3ca95e 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 2d51fce74a5a..db183455ff34 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index a1add3f215e3..810818b2bff6 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 8d8c80e3656d..7c4cd7e7535b 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; linux,initrd-start = <0x4500040>; linux,initrd-end = <0x4800000>; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 59e7a5adeedb..9a8d40a17938 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 04a1e44541b3..2213a20e7871 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index c9e82eff9bf2..6e83b13fc26a 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 1656653d339b..ed3cdfbb45bb 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -4,6 +4,7 @@ / { chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 73722c067501..b23abfe08d2f 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -12,9 +12,10 @@ reg = <0x00000000 0x20000000>; }; - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - }; + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; mbus { pcie-controller { diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 2cb0dc529165..e1dcb2b83f24 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -28,6 +28,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index 4838478019cc..b29cab304fd0 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 7c8a0d9d8d1f..4ef494231b78 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 743152f31a81..da8891bbeec8 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -4,6 +4,7 @@ / { chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 989846ac6577..cd68210b9f11 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -12,6 +12,7 @@ chosen { bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index d0a602578f5b..8fd72d49e43f 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -17,6 +17,7 @@ chosen { bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts index fc20baf0eade..817eaf02a346 100644 --- a/arch/arm/boot/dts/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index b88da9392c32..557b824f9c43 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index b2f7cae06839..b1f5e1180803 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -26,6 +26,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index e9dd85049297..8df800757175 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts @@ -26,6 +26,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index d6368c39102e..c573c204dbdb 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -22,6 +22,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts index 93ec3d00c6ab..3b19f1fd4cac 100644 --- a/arch/arm/boot/dts/kirkwood-rs212.dts +++ b/arch/arm/boot/dts/kirkwood-rs212.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-3 { diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts index 311df4e5aa28..921ca49e85a4 100644 --- a/arch/arm/boot/dts/kirkwood-rs409.dts +++ b/arch/arm/boot/dts/kirkwood-rs409.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-150-15-18 { diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts index f90da850bb31..02852b0c809f 100644 --- a/arch/arm/boot/dts/kirkwood-rs411.dts +++ b/arch/arm/boot/dts/kirkwood-rs411.dts @@ -24,6 +24,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; gpio-fan-100-15-35-3 { diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index 1ff848d570a9..bd01d306a754 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -17,6 +17,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index 7d1c7677a18f..df53176c9354 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -27,6 +27,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 5fc817c2cb87..a85025ef4c52 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -14,6 +14,7 @@ chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; }; ocp@f1000000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 911f3a8cee23..8f2226b8bd3d 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -9,6 +9,7 @@ chosen { bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; }; mbus { -- cgit v1.2.3 From e37e01112a4732406521116993aab9dbec8d7372 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:31 +0200 Subject: ARM: dts: kirkwood: remove clock-frequency properties from UART nodes UART devices found on Kirkwood SoCs derive their baudrate from TCLK. With proper clocks property in the SoCs serial node, boards do not need to overwrite it anymore. Remove the remaining clock-frequency property from all Kirkwood boards. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-5-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-cloudbox.dts | 1 - arch/arm/boot/dts/kirkwood-db.dtsi | 1 - arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 1 - arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 1 - arch/arm/boot/dts/kirkwood-ts219.dtsi | 2 -- 5 files changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 61212692740e..65ae6471d553 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -28,7 +28,6 @@ serial@12000 { pinctrl-0 = <&pmx_uart0>; pinctrl-names = "default"; - clock-frequency = <166666667>; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 22df970df2a1..68dfb3ad57dd 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -36,7 +36,6 @@ serial@12000 { pinctrl-0 = <&pmx_uart0>; pinctrl-names = "default"; - clock-frequency = <200000000>; status = "ok"; }; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index db183455ff34..3994a86f989e 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -37,7 +37,6 @@ }; }; serial@12000 { - clock-frequency = <200000000>; status = "ok"; }; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index e1dcb2b83f24..dee94021c8ae 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -67,7 +67,6 @@ serial@12000 { pinctrl-0 = <&pmx_uart0>; pinctrl-names = "default"; - clock-frequency = <200000000>; status = "ok"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 8f2226b8bd3d..414d2246b37c 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -35,13 +35,11 @@ }; }; serial@12000 { - clock-frequency = <200000000>; status = "okay"; pinctrl-0 = <&pmx_uart0>; pinctrl-names = "default"; }; serial@12100 { - clock-frequency = <200000000>; status = "okay"; pinctrl-0 = <&pmx_uart1>; pinctrl-names = "default"; -- cgit v1.2.3 From 7fd44dacdd803c0bbf38bf478d51d280902bb0f1 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sun, 4 May 2014 20:43:15 -0400 Subject: x86, x32: Use compat shims for io_{setup,submit} The io_setup takes a pointer to a context id of type aio_context_t. This in turn is typed to a __kernel_ulong_t. We could tweak the exported headers to define this as a 64bit quantity for specific ABIs, but since we already have a 32bit compat shim for the x86 ABI, let's just re-use that logic. The libaio package is also written to expect this as a pointer type, so a compat shim would simplify that. The io_submit func operates on an array of pointers to iocb structs. Padding out the array to be 64bit aligned is a huge pain, so convert it over to the existing compat shim too. We don't convert io_getevents to the compat func as its only purpose is to handle the timespec struct, and the x32 ABI uses 64bit times. With this change, the libaio package can now pass its testsuite when built for the x32 ABI. Signed-off-by: Mike Frysinger Link: http://lkml.kernel.org/r/1399250595-5005-1-git-send-email-vapier@gentoo.org Cc: H.J. Lu Signed-off-by: H. Peter Anvin Cc: # v3.4+ --- arch/x86/syscalls/syscall_64.tbl | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/syscalls/syscall_64.tbl b/arch/x86/syscalls/syscall_64.tbl index 04376ac3d9ef..ec255a1646d2 100644 --- a/arch/x86/syscalls/syscall_64.tbl +++ b/arch/x86/syscalls/syscall_64.tbl @@ -212,10 +212,10 @@ 203 common sched_setaffinity sys_sched_setaffinity 204 common sched_getaffinity sys_sched_getaffinity 205 64 set_thread_area -206 common io_setup sys_io_setup +206 64 io_setup sys_io_setup 207 common io_destroy sys_io_destroy 208 common io_getevents sys_io_getevents -209 common io_submit sys_io_submit +209 64 io_submit sys_io_submit 210 common io_cancel sys_io_cancel 211 64 get_thread_area 212 common lookup_dcookie sys_lookup_dcookie @@ -359,3 +359,5 @@ 540 x32 process_vm_writev compat_sys_process_vm_writev 541 x32 setsockopt compat_sys_setsockopt 542 x32 getsockopt compat_sys_getsockopt +543 x32 io_setup compat_sys_io_setup +544 x32 io_submit compat_sys_io_submit -- cgit v1.2.3 From a9483969815e90d6a5e25c7c941bb3d8d152f2bd Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:32 +0200 Subject: ARM: dts: kirkwood: rename pin-controller nodes To prepare pin-controller consolidation, first rename all pinctrl nodes to a more appropriate name regarding ePAPR recommended names. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-6-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6192.dtsi | 2 +- arch/arm/boot/dts/kirkwood-6281.dtsi | 2 +- arch/arm/boot/dts/kirkwood-6282.dtsi | 2 +- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 2 +- arch/arm/boot/dts/kirkwood-b3.dts | 2 +- arch/arm/boot/dts/kirkwood-cloudbox.dts | 2 +- arch/arm/boot/dts/kirkwood-db.dtsi | 2 +- arch/arm/boot/dts/kirkwood-dnskw.dtsi | 2 +- arch/arm/boot/dts/kirkwood-dockstar.dts | 2 +- arch/arm/boot/dts/kirkwood-dreamplug.dts | 2 +- arch/arm/boot/dts/kirkwood-goflexnet.dts | 2 +- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 2 +- arch/arm/boot/dts/kirkwood-ib62x0.dts | 2 +- arch/arm/boot/dts/kirkwood-iconnect.dts | 2 +- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 2 +- arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 2 +- arch/arm/boot/dts/kirkwood-laplug.dts | 2 +- arch/arm/boot/dts/kirkwood-lsxl.dtsi | 2 +- arch/arm/boot/dts/kirkwood-mplcec4.dts | 2 +- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 2 +- arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 2 +- arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 2 +- arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood-nsa310.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa310a.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa320.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 2 +- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 2 +- arch/arm/boot/dts/kirkwood-rd88f6192.dts | 2 +- arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 2 +- arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood-synology.dtsi | 2 +- arch/arm/boot/dts/kirkwood-t5325.dts | 2 +- arch/arm/boot/dts/kirkwood-topkick.dts | 2 +- arch/arm/boot/dts/kirkwood-ts219-6281.dts | 2 +- arch/arm/boot/dts/kirkwood-ts219-6282.dts | 2 +- arch/arm/boot/dts/kirkwood-ts419.dtsi | 2 +- 38 files changed, 38 insertions(+), 38 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 294a6fa0208c..4f1eef36a7ac 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -35,7 +35,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,88f6192-pinctrl"; reg = <0x10000 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 2560cbbdb0b3..d95a7a9cfd1e 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -35,7 +35,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,88f6281-pinctrl"; reg = <0x10000 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index f4b4786b9a01..523d6feeaf19 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -56,7 +56,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,88f6282-pinctrl"; reg = <0x10000 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 3271e4c8ea07..c59e7b75b169 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -1,6 +1,6 @@ / { ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { compatible = "marvell,98dx4122-pinctrl"; reg = <0x10000 0x20>; diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index 86073f4f31ac..c723ce7ad1b8 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -45,7 +45,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { marvell,pins = "mpp39"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 65ae6471d553..3f30475fea11 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_cloudbox_sata0: pmx-cloudbox-sata0 { marvell,pins = "mpp15"; marvell,function = "sata0"; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 68dfb3ad57dd..9b62f78b516b 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -26,7 +26,7 @@ }; ocp@f1000000 { - pinctrl@10000 { + pin-controller@10000 { pmx_sdio_gpios: pmx-sdio-gpios { marvell,pins = "mpp37", "mpp38"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index d5aa9564a287..bcc6e0f48571 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -50,7 +50,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0 &pmx_present_sata1 &pmx_fan_tacho diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index d703f3eeef1c..849736349511 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 8ed737e9aa2f..dd8d1a4611a8 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_bluetooth: pmx-led-bluetooth { marvell,pins = "mpp47"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 5e39cc3ca95e..aa60a0b049a7 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 3994a86f989e..871a5f8afb01 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_health_r: pmx-led-health-r { marvell,pins = "mpp46"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 810818b2bff6..6804638eb87e 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_os_red: pmx-led-os-red { marvell,pins = "mpp22"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 7c4cd7e7535b..38e31d15a62d 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -30,7 +30,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_reset: pmx-button-reset { marvell,pins = "mpp12"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 9a8d40a17938..05291f3990d0 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = < &pmx_led_sata_brt_ctrl_1 &pmx_led_sata_brt_ctrl_2 &pmx_led_backup_brt_ctrl_1 diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index 2213a20e7871..db14bd03b86b 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 6e83b13fc26a..4f7741184f98 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -55,7 +55,7 @@ }; }; - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp14"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index ed3cdfbb45bb..53484474df1f 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -8,7 +8,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_power_hdd: pmx-power-hdd { marvell,pins = "mpp10"; marvell,function = "gpo"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index b23abfe08d2f..414024c578e8 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -28,7 +28,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_led_health: pmx-led-health { marvell,pins = "mpp7"; marvell,function = "gpo"; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index dee94021c8ae..2f6c9988ed7d 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -32,7 +32,7 @@ }; ocp@f1000000 { - pinctrl@10000 { + pin-controller@10000 { pmx_usb_led: pmx-usb-led { marvell,pins = "mpp12"; marvell,function = "gpo"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index b29cab304fd0..c4741699605c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -39,7 +39,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { marvell,pins = "mpp47"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 4ef494231b78..8437f3e3b8d7 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -41,7 +41,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { marvell,pins = "mpp47"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index da8891bbeec8..46eb8f6b6243 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -8,7 +8,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_ns2_sata0: pmx-ns2-sata0 { marvell,pins = "mpp21"; marvell,function = "sata0"; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index cd68210b9f11..78bdf9c7f16b 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -26,7 +26,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_unknown>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts index 8fd72d49e43f..0788473f0447 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts @@ -21,7 +21,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-names = "default"; pmx_led_esata_green: pmx-led-esata-green { diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts index 817eaf02a346..24f686d1044d 100644 --- a/arch/arm/boot/dts/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -38,7 +38,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-names = "default"; /* SATA Activity and Present pins are not connected */ diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index 843b8b561e5e..9cb083b72404 100644 --- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -5,7 +5,7 @@ model = "ZyXEL NSA310"; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power: pmx-usb-power { marvell,pins = "mpp21"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 557b824f9c43..fd1c8b535e28 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -46,7 +46,7 @@ }; }; - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index b1f5e1180803..8c3d50c57fa0 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -58,7 +58,7 @@ }; }; - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index 8df800757175..30087b19efae 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts @@ -40,7 +40,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_usb_power>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index c573c204dbdb..26cf0e0ccefd 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -36,7 +36,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_sdio_cd>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index bd01d306a754..a015af4da9a2 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -21,7 +21,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_usb_power_enable: pmx-usb-power-enable { marvell,pins = "mpp29"; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 4227c974729d..e137bd4e26fd 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -25,7 +25,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pmx_alarmled_12: pmx-alarmled-12 { marvell,pins = "mpp12"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index df53176c9354..ae102abcab04 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -41,7 +41,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_i2s &pmx_sysrst>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index a85025ef4c52..5bc57efbee99 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -18,7 +18,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { /* * Switch positions * diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index c17ae45e19be..9767d73f3857 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -6,7 +6,7 @@ / { ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index 0713d072758a..bfc1a32d4e42 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -16,7 +16,7 @@ }; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_ram_size &pmx_board_id>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi index 1a9c624c7a92..30ab93bfb1e4 100644 --- a/arch/arm/boot/dts/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi @@ -14,7 +14,7 @@ compatible = "qnap,ts419", "marvell,kirkwood"; ocp@f1000000 { - pinctrl: pinctrl@10000 { + pinctrl: pin-controller@10000 { pinctrl-names = "default"; pmx_USB_copy_button: pmx-USB-copy-button { -- cgit v1.2.3 From 2ab516adb3489347331a89070a37eaf1907679d8 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:33 +0200 Subject: ARM: dts: kirkwood: add pinctrl node to common SoC include All Kirkwood SoCs have their pinctrl registers at the same address. Instead of replaying the same reg property on each SoC, have the reg property set in the common SoC file already. This also allows us to move common pinctrl settings to this node later on. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-7-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6192.dtsi | 1 - arch/arm/boot/dts/kirkwood-6281.dtsi | 1 - arch/arm/boot/dts/kirkwood-6282.dtsi | 1 - arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 1 - arch/arm/boot/dts/kirkwood.dtsi | 5 +++++ 5 files changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 4f1eef36a7ac..c008e9a877d5 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -37,7 +37,6 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { compatible = "marvell,88f6192-pinctrl"; - reg = <0x10000 0x20>; pmx_nand: pmx-nand { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index d95a7a9cfd1e..3674a9b9552e 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -37,7 +37,6 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { compatible = "marvell,88f6281-pinctrl"; - reg = <0x10000 0x20>; pmx_nand: pmx-nand { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 523d6feeaf19..89a6ba149ec2 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -58,7 +58,6 @@ pinctrl: pin-controller@10000 { compatible = "marvell,88f6282-pinctrl"; - reg = <0x10000 0x20>; pmx_nand: pmx-nand { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index c59e7b75b169..4a2d1b12d1ca 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -2,7 +2,6 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { compatible = "marvell,98dx4122-pinctrl"; - reg = <0x10000 0x20>; pmx_nand: pmx-nand { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 2570e0f1673f..028003e12111 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -71,6 +71,11 @@ #address-cells = <1>; #size-cells = <1>; + pinctrl: pin-controller@10000 { + /* set compatible property in SoC file */ + reg = <0x10000 0x20>; + }; + core_clk: core-clocks@10030 { compatible = "marvell,kirkwood-core-clock"; reg = <0x10030 0x4>; -- cgit v1.2.3 From 327e154289772870476b3787f125fc9618f81c7a Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:34 +0200 Subject: ARM: dts: kirkwood: consolidate common pinctrl settings All SoCs have the same pinctrl setting for NAND, UART0/1, SPI, TWSI0, and GBE1. Move it to the common pinctrl node that we now have. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-8-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6192.dtsi | 22 ------------------- arch/arm/boot/dts/kirkwood-6281.dtsi | 22 ------------------- arch/arm/boot/dts/kirkwood-6282.dtsi | 23 ------------------- arch/arm/boot/dts/kirkwood-98dx4122.dtsi | 22 ------------------- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 7 ------ arch/arm/boot/dts/kirkwood.dtsi | 33 ++++++++++++++++++++++++++++ 6 files changed, 33 insertions(+), 96 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index c008e9a877d5..dd81508b919b 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -38,12 +38,6 @@ pinctrl: pin-controller@10000 { compatible = "marvell,88f6192-pinctrl"; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", - "mpp19"; - marvell,function = "nand"; - }; pmx_sata0: pmx-sata0 { marvell,pins = "mpp5", "mpp21", "mpp23"; marvell,function = "sata0"; @@ -52,22 +46,6 @@ marvell,pins = "mpp4", "mpp20", "mpp22"; marvell,function = "sata1"; }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; pmx_sdio: pmx-sdio { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 3674a9b9552e..7dc7d6782e83 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -38,12 +38,6 @@ pinctrl: pin-controller@10000 { compatible = "marvell,88f6281-pinctrl"; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", - "mpp19"; - marvell,function = "nand"; - }; pmx_sata0: pmx-sata0 { marvell,pins = "mpp5", "mpp21", "mpp23"; marvell,function = "sata0"; @@ -52,22 +46,6 @@ marvell,pins = "mpp4", "mpp20", "mpp22"; marvell,function = "sata1"; }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; pmx_sdio: pmx-sdio { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 89a6ba149ec2..b869f48cac02 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -59,12 +59,6 @@ pinctrl: pin-controller@10000 { compatible = "marvell,88f6282-pinctrl"; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", "mpp19"; - marvell,function = "nand"; - }; - pmx_sata0: pmx-sata0 { marvell,pins = "mpp5", "mpp21", "mpp23"; marvell,function = "sata0"; @@ -73,29 +67,12 @@ marvell,pins = "mpp4", "mpp20", "mpp22"; marvell,function = "sata1"; }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; pmx_twsi1: pmx-twsi1 { marvell,pins = "mpp36", "mpp37"; marvell,function = "twsi1"; }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; pmx_sdio: pmx-sdio { marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16", "mpp17"; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 4a2d1b12d1ca..2e8e412b9db0 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -3,28 +3,6 @@ pinctrl: pin-controller@10000 { compatible = "marvell,98dx4122-pinctrl"; - pmx_nand: pmx-nand { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp18", - "mpp19"; - marvell,function = "nand"; - }; - pmx_spi: pmx-spi { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; - marvell,function = "spi"; - }; - pmx_twsi0: pmx-twsi0 { - marvell,pins = "mpp8", "mpp9"; - marvell,function = "twsi0"; - }; - pmx_uart0: pmx-uart0 { - marvell,pins = "mpp10", "mpp11"; - marvell,function = "uart0"; - }; - pmx_uart1: pmx-uart1 { - marvell,pins = "mpp13", "mpp14"; - marvell,function = "uart1"; - }; }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 8c3d50c57fa0..1a7f18d5530d 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -110,13 +110,6 @@ marvell,pins = "mpp41", "mpp42", "mpp43"; marvell,function = "gpio"; }; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", - "mpp24", "mpp25", "mpp26", "mpp27", - "mpp30", "mpp31", "mpp32", "mpp33"; - marvell,function = "ge1"; - }; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 028003e12111..5d412e71b9fb 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -74,6 +74,39 @@ pinctrl: pin-controller@10000 { /* set compatible property in SoC file */ reg = <0x10000 0x20>; + + pmx_ge1: pmx-ge1 { + marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", + "mpp24", "mpp25", "mpp26", "mpp27", + "mpp30", "mpp31", "mpp32", "mpp33"; + marvell,function = "ge1"; + }; + + pmx_nand: pmx-nand { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp18", "mpp19"; + marvell,function = "nand"; + }; + + pmx_spi: pmx-spi { + marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; + marvell,function = "spi"; + }; + + pmx_twsi0: pmx-twsi0 { + marvell,pins = "mpp8", "mpp9"; + marvell,function = "twsi0"; + }; + + pmx_uart0: pmx-uart0 { + marvell,pins = "mpp10", "mpp11"; + marvell,function = "uart0"; + }; + + pmx_uart1: pmx-uart1 { + marvell,pins = "mpp13", "mpp14"; + marvell,function = "uart1"; + }; }; core_clk: core-clocks@10030 { -- cgit v1.2.3 From 9dd85ad219328689b04d6406b942a6b17aa9242a Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:35 +0200 Subject: ARM: dts: kirkwood: set default pinctrl for GBE1 On Kirkwood, there is only one valid pinctrl setting for GBE1. With a common SoC pinctrl node, we can now set it in the node instead of in each board file. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-9-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 2 -- arch/arm/boot/dts/kirkwood.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 1a7f18d5530d..622a3ca12c2d 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -207,8 +207,6 @@ ð1 { status = "okay"; - pinctrl-0 = <&pmx_ge1>; - pinctrl-names = "default"; ethernet1-port@0 { phy-handle = <ðphy1>; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 5d412e71b9fb..fff28b71b474 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -320,6 +320,8 @@ reg = <0x76000 0x4000>; clocks = <&gate_clk 19>; marvell,tx-checksum-limit = <1600>; + pinctrl-0 = <&pmx_ge1>; + pinctrl-names = "default"; status = "disabled"; ethernet1-port@0 { -- cgit v1.2.3 From 9f2339a697212bb70b583b8b27d800eec7c05f49 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:36 +0200 Subject: ARM: dts: kirkwood: set default pinctrl for UART0/1 Most boards use the default UART0/1 pinctrl setting without RTS/CTS. Add the pinctrl setting to the toplevel SoC UART nodes and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Currently, both boards using a different UART pinctrl setting (Openblocks A6, A7) already overwrite the pinctrl node. While at it, also fix up some status = "ok" to "okay" and again whitespace issues on mplcec4 uart nodes. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-10-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-b3.dts | 2 -- arch/arm/boot/dts/kirkwood-cloudbox.dts | 2 -- arch/arm/boot/dts/kirkwood-db.dtsi | 4 +--- arch/arm/boot/dts/kirkwood-dns320.dts | 2 -- arch/arm/boot/dts/kirkwood-laplug.dts | 2 -- arch/arm/boot/dts/kirkwood-mplcec4.dts | 8 +++----- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 4 +--- arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts | 2 -- arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts | 2 -- arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 2 -- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 8 ++------ arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 8 ++------ arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 2 -- arch/arm/boot/dts/kirkwood-synology.dtsi | 4 ---- arch/arm/boot/dts/kirkwood-topkick.dts | 4 +--- arch/arm/boot/dts/kirkwood-ts219.dtsi | 4 ---- arch/arm/boot/dts/kirkwood.dtsi | 8 ++++++++ 17 files changed, 18 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index c723ce7ad1b8..38972b221089 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -114,8 +114,6 @@ * UART0_TX = Testpoint 66 * See the Excito Wiki for more details. */ - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 3f30475fea11..1ac6bd9f54de 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -26,8 +26,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 9b62f78b516b..2790f46d87e0 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -34,9 +34,7 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts index 3210daeb264c..d85ef0a91b50 100644 --- a/arch/arm/boot/dts/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/kirkwood-dns320.dts @@ -52,8 +52,6 @@ }; serial@12100 { - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 4f7741184f98..4c91fbb084c5 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -38,8 +38,6 @@ ocp@f1000000 { serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 414024c578e8..79796c8b9c4f 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -90,11 +90,9 @@ }; - serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - }; + serial@12000 { + status = "okay"; + }; rtc@10300 { status = "disabled"; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 2f6c9988ed7d..934f6b8906e3 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -65,9 +65,7 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; - status = "ok"; + status = "okay"; }; ehci@50000 { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index c4741699605c..fd733c63bc27 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -113,8 +113,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index 8437f3e3b8d7..b514d643fb6c 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -120,8 +120,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 46eb8f6b6243..696b208b676f 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -20,8 +20,6 @@ }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index fd1c8b535e28..1e056b3b1817 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -19,15 +19,11 @@ ocp@f1000000 { serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; + status = "okay"; }; serial@12100 { - status = "ok"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 622a3ca12c2d..07f6bf6aba91 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -31,15 +31,11 @@ ocp@f1000000 { serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; + status = "okay"; }; serial@12100 { - status = "ok"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index a015af4da9a2..e2c43aecc7b2 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -45,8 +45,6 @@ }; }; serial@12000 { - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index e137bd4e26fd..370af7f69319 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -277,14 +277,10 @@ serial@12000 { status = "okay"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; }; serial@12100 { status = "okay"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; }; poweroff@12100 { diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 5bc57efbee99..14b12189d464 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -86,9 +86,7 @@ }; serial@12000 { - status = "ok"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 414d2246b37c..21cb9aeb2455 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -36,13 +36,9 @@ }; serial@12000 { status = "okay"; - pinctrl-0 = <&pmx_uart0>; - pinctrl-names = "default"; }; serial@12100 { status = "okay"; - pinctrl-0 = <&pmx_uart1>; - pinctrl-names = "default"; }; poweroff@12100 { compatible = "qnap,power-off"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index fff28b71b474..f92c8c4e3908 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -98,6 +98,10 @@ marvell,function = "twsi0"; }; + /* + * Default UART pinctrl setting without RTS/CTS, + * overwrite marvell,pins on board level if required. + */ pmx_uart0: pmx-uart0 { marvell,pins = "mpp10", "mpp11"; marvell,function = "uart0"; @@ -167,6 +171,8 @@ reg-shift = <2>; interrupts = <33>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_uart0>; + pinctrl-names = "default"; status = "disabled"; }; @@ -176,6 +182,8 @@ reg-shift = <2>; interrupts = <34>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_uart1>; + pinctrl-names = "default"; status = "disabled"; }; -- cgit v1.2.3 From 929012010ae514c091096ba5cfa1bdbac44d67e7 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:37 +0200 Subject: ARM: dts: kirkwood: set default pinctrl for SPI0 Most Kirkwood boards use the default SPI0 pinctrl setting anyway. Add a default pinctrl setting to the toplevel SoC SPI0 node and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Currently, only T5325 is using a different setting and already overwrites the corresponding pinctrl node. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-11-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-b3.dts | 2 -- arch/arm/boot/dts/kirkwood-cloudbox.dts | 2 -- arch/arm/boot/dts/kirkwood-dreamplug.dts | 2 -- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 2 -- arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 2 -- arch/arm/boot/dts/kirkwood-rd88f6192.dts | 2 -- arch/arm/boot/dts/kirkwood-synology.dtsi | 2 -- arch/arm/boot/dts/kirkwood-t5325.dts | 6 ------ arch/arm/boot/dts/kirkwood-ts219.dtsi | 2 -- arch/arm/boot/dts/kirkwood.dtsi | 6 ++++++ 10 files changed, 6 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index 38972b221089..6678e0b318d5 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -70,8 +70,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p16@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 1ac6bd9f54de..e7a232eb28b0 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -37,8 +37,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index dd8d1a4611a8..af56cecc6c73 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -38,8 +38,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p40@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 934f6b8906e3..343dbb44b3d2 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -50,8 +50,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index 696b208b676f..c10ff0f5290b 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -24,8 +24,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index 30087b19efae..35a29dee8dd8 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts @@ -57,8 +57,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 370af7f69319..a21419f78bee 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -213,8 +213,6 @@ spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p80@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index ae102abcab04..289fc9e2afc2 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -65,10 +65,6 @@ marvell,function = "gpio"; }; - /* - * Redefined from kirkwood-6281.dtsi, because - * we don't use SPI CS on MPP0, but on MPP7. - */ pmx_spi: pmx-spi { marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7"; marvell,function = "spi"; @@ -87,8 +83,6 @@ }; spi@10600 { - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 21cb9aeb2455..539a2f80a3ad 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -47,8 +47,6 @@ }; spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; m25p128@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index f92c8c4e3908..0c8d8fa29926 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -88,6 +88,10 @@ marvell,function = "nand"; }; + /* + * Default SPI0 pinctrl setting with CSn on mpp0, + * overwrite marvell,pins on board level if required. + */ pmx_spi: pmx-spi { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; marvell,function = "spi"; @@ -127,6 +131,8 @@ interrupts = <23>; reg = <0x10600 0x28>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_spi>; + pinctrl-names = "default"; status = "disabled"; }; -- cgit v1.2.3 From cbfaea96acff4c687b0d9abf25325d9d5b073df1 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:38 +0200 Subject: ARM: dts: kirkwood: set default pinctrl for NAND There is only one valid pinctrl setting for NAND on Kirkwood. Now that we have the setting in the common SoC pinctrl, move it to the NAND controller node directly and remove it from the individual boards. While at it, also fix up status = "okay" to "ok" on one board's NAND node. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-12-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-db.dtsi | 2 -- arch/arm/boot/dts/kirkwood-dnskw.dtsi | 2 -- arch/arm/boot/dts/kirkwood-ib62x0.dts | 2 -- arch/arm/boot/dts/kirkwood-km_kirkwood.dts | 4 +--- arch/arm/boot/dts/kirkwood-laplug.dts | 1 - arch/arm/boot/dts/kirkwood-mplcec4.dts | 2 -- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 2 -- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 2 -- arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi | 2 -- arch/arm/boot/dts/kirkwood-topkick.dts | 2 -- arch/arm/boot/dts/kirkwood.dtsi | 2 ++ 11 files changed, 3 insertions(+), 20 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi index 2790f46d87e0..812df691ae3d 100644 --- a/arch/arm/boot/dts/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/kirkwood-db.dtsi @@ -57,8 +57,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; chip-delay = <25>; status = "okay"; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index bcc6e0f48571..113dcf056dcf 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -183,8 +183,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; status = "okay"; chip-delay = <35>; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index 6804638eb87e..bfa5edde179c 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -105,8 +105,6 @@ &nand { status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "u-boot"; diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts index db14bd03b86b..61139bf30985 100644 --- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts +++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts @@ -46,9 +46,7 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; - status = "ok"; + status = "okay"; chip-delay = <25>; }; diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 4c91fbb084c5..642755acf2fe 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -138,7 +138,6 @@ &nand { /* Total size : 512MB */ status = "okay"; - pinctrl-0 = <&pmx_nand>; partition@0 { label = "u-boot"; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index 79796c8b9c4f..f3a991837515 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -162,8 +162,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; status = "okay"; partition@0 { diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 1e056b3b1817..00c2e5a9d863 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -130,8 +130,6 @@ &nand { chip-delay = <25>; status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "uboot"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index 07f6bf6aba91..bc07aa5e6698 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -148,8 +148,6 @@ &nand { chip-delay = <25>; status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "uboot"; diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi index e2c43aecc7b2..7196c7f3e109 100644 --- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi @@ -71,8 +71,6 @@ }; &nand { - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; status = "okay"; partition@0 { diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index 14b12189d464..a4dd47acf98a 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -174,8 +174,6 @@ &nand { status = "okay"; - pinctrl-0 = <&pmx_nand>; - pinctrl-names = "default"; partition@0 { label = "u-boot"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 0c8d8fa29926..caafcde88f67 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -61,6 +61,8 @@ chip-delay = <25>; /* set partition map and/or chip-delay in board dts */ clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; status = "disabled"; }; }; -- cgit v1.2.3 From ce55b1f423b8a53e118593c2da2a2f246ff7c445 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:39 +0200 Subject: ARM: dts: kirkwood: set default pinctrl for I2C0 There is only one valid pinctrl setting for I2C0 on Kirkwood. Now that we have the setting in the common SoC pinctrl, move it to the I2C0 controller node directly and remove it from the individual boards. While at it, also fix up status = "okay" to "ok" on one board's I2C0 node. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-13-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-laplug.dts | 2 -- arch/arm/boot/dts/kirkwood-ns2-common.dtsi | 2 -- arch/arm/boot/dts/kirkwood-synology.dtsi | 2 -- arch/arm/boot/dts/kirkwood-topkick.dts | 4 +--- arch/arm/boot/dts/kirkwood-ts219.dtsi | 2 -- arch/arm/boot/dts/kirkwood.dtsi | 2 ++ 6 files changed, 3 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 642755acf2fe..92c2d3c16546 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -42,8 +42,6 @@ }; i2c@11000 { - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; status = "okay"; eeprom@50 { diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index c10ff0f5290b..e6863ed87d76 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -42,8 +42,6 @@ }; i2c@11000 { - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; status = "okay"; eeprom@50 { diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index a21419f78bee..811e0971fc58 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -257,8 +257,6 @@ i2c@11000 { status = "okay"; clock-frequency = <400000>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; rs5c372: rs5c372@32 { status = "disabled"; diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts index a4dd47acf98a..f5c8c0dd41dc 100644 --- a/arch/arm/boot/dts/kirkwood-topkick.dts +++ b/arch/arm/boot/dts/kirkwood-topkick.dts @@ -95,9 +95,7 @@ }; i2c@11000 { - status = "ok"; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; + status = "okay"; }; mvsdio@90000 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 539a2f80a3ad..df7f15276575 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -26,8 +26,6 @@ i2c@11000 { status = "okay"; clock-frequency = <400000>; - pinctrl-0 = <&pmx_twsi0>; - pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index caafcde88f67..0399a096e324 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -170,6 +170,8 @@ interrupts = <29>; clock-frequency = <100000>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi0>; + pinctrl-names = "default"; status = "disabled"; }; -- cgit v1.2.3 From d7e1c07630ed67942357c44dc975a5ce50f5966a Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:40 +0200 Subject: ARM: dts: kirkwood: set default pinctrl for I2C1 on 6282 Currently, the only 6282-based Kirkwood boards that use I2C1 are Openblocks A6/A7. Both use the same default I2C1 pinctrl setting from kirkwood-6282.dtsi. Move the pinctrl setting to the I2C1 node directly and put a note in front of the corresponding pinctrl node to overwrite the setting on board level. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-14-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-6282.dtsi | 6 ++++++ arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 2 -- arch/arm/boot/dts/kirkwood-openblocks_a7.dts | 2 -- 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index b869f48cac02..4680eec990f0 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -68,6 +68,10 @@ marvell,function = "sata1"; }; + /* + * Default I2C1 pinctrl setting on mpp36/mpp37, + * overwrite marvell,pins on board level if required. + */ pmx_twsi1: pmx-twsi1 { marvell,pins = "mpp36", "mpp37"; marvell,function = "twsi1"; @@ -101,6 +105,8 @@ interrupts = <32>; clock-frequency = <100000>; clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 00c2e5a9d863..3dcb5c26b78b 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -33,8 +33,6 @@ i2c@11100 { status = "okay"; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; s35390a: s35390a@30 { compatible = "s35390a"; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index bc07aa5e6698..4e10e92b7822 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -45,8 +45,6 @@ i2c@11100 { status = "okay"; - pinctrl-0 = <&pmx_twsi1>; - pinctrl-names = "default"; s24c02: s24c02@50 { compatible = "24c02"; -- cgit v1.2.3 From e862721c876227caf23e7e8d5bfed597b0e15f43 Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:41 +0200 Subject: ARM: dts: kirkwood: set Guruplug ethernet PHY compatible Ethernet PHY compatible shall be "ethernet-phy-ieee802.3-c22" and "ethernet-phy-idAAAA.BBBB" if PHY OUI id is known. We know it for the PHY found on Guruplug, so set it accordingly. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-15-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index 871a5f8afb01..f6f15e2910ed 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -101,12 +101,16 @@ status = "okay"; ethphy0: ethernet-phy@0 { - compatible = "marvell,88e1121"; + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; reg = <0>; }; ethphy1: ethernet-phy@1 { - compatible = "marvell,88e1121"; + /* Marvell 88E1121R */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; -- cgit v1.2.3 From eeb845459a72e792a959278b858f9c417e9995bd Mon Sep 17 00:00:00 2001 From: Sebastian Hesselbarth Date: Wed, 30 Apr 2014 14:56:42 +0200 Subject: ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id Ethernet PHYs found on Globalscale Guruplug are connected by RGMII-ID. Set the corresponding phy-connection-type property accordingly. Signed-off-by: Sebastian Hesselbarth Acked-by: Andrew Lunn Link: https://lkml.kernel.org/r/1398862602-29595-16-git-send-email-sebastian.hesselbarth@gmail.com Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index f6f15e2910ed..c5a1fc75c7a3 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -105,6 +105,7 @@ compatible = "ethernet-phy-id0141.0cb0", "ethernet-phy-ieee802.3-c22"; reg = <0>; + phy-connection-type = "rgmii-id"; }; ethphy1: ethernet-phy@1 { @@ -112,6 +113,7 @@ compatible = "ethernet-phy-id0141.0cb0", "ethernet-phy-ieee802.3-c22"; reg = <1>; + phy-connection-type = "rgmii-id"; }; }; -- cgit v1.2.3 From 809aa6f1b4ce8322e32725437837fb92c2eaf4c8 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 30 Apr 2014 23:26:43 -0700 Subject: ARM: mvebu: defconfig: add MTD_SPI_NOR (new dependency for M25P80) These defconfigs contain the CONFIG_M25P80 symbol, which is now dependent on the MTD_SPI_NOR symbol. Add CONFIG_MTD_SPI_NOR to satisfy the new dependency. At the same time, drop the now-nonexistent CONFIG_MTD_CHAR symbol. Signed-off-by: Brian Norris Cc: Jason Cooper Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Jason Cooper Acked-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1398925607-7482-9-git-send-email-computersforpeace@gmail.com Signed-off-by: Jason Cooper --- arch/arm/configs/dove_defconfig | 2 +- arch/arm/configs/kirkwood_defconfig | 1 + arch/arm/configs/mvebu_v5_defconfig | 1 + arch/arm/configs/mvebu_v7_defconfig | 1 + 4 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index f15955144175..701677f9248c 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -37,7 +37,6 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_JEDECPROBE=y @@ -48,6 +47,7 @@ CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_STAA=y CONFIG_MTD_PHYSMAP=y CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 2e762d94e94b..b9e480c10b10 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -61,6 +61,7 @@ CONFIG_MTD_PHYSMAP=y CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_EEPROM_AT24=y # CONFIG_SCSI_PROC_FS is not set diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig index 5d8ec15aefef..4a2baa9ea9fb 100644 --- a/arch/arm/configs/mvebu_v5_defconfig +++ b/arch/arm/configs/mvebu_v5_defconfig @@ -51,6 +51,7 @@ CONFIG_MTD_PHYSMAP=y CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ORION=y +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_EEPROM_AT24=y # CONFIG_SCSI_PROC_FS is not set diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig index 2485a5ef9c4c..b52a6f5c5225 100644 --- a/arch/arm/configs/mvebu_v7_defconfig +++ b/arch/arm/configs/mvebu_v7_defconfig @@ -58,6 +58,7 @@ CONFIG_I2C_MV64XXX=y CONFIG_MTD=y CONFIG_MTD_CHAR=y CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y CONFIG_MTD_CFI_AMDSTD=y -- cgit v1.2.3 From b715a3b0d434910aa01922b08f00d8d468fba377 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 3 May 2014 20:30:13 +0200 Subject: ARM: Kirkwood: Add node for audio codec Instantiate the audio codec via a DT node. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1399141819-23924-4-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-t5325.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index 289fc9e2afc2..291eff4fd353 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -126,6 +126,9 @@ alc5621: alc5621@1a { compatible = "realtek,alc5621"; reg = <0x1a>; + #sound-dai-cells = <0>; + add-ctrl = <0x3700>; + jack-det-ctrl = <0x4810>; }; }; -- cgit v1.2.3 From 1756c381580bc83d38bf3e338c14d1ee7ba31899 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 3 May 2014 20:30:14 +0200 Subject: ARM: Kirkwood: DT: Add missing #sound-dai-cells property The sound node is missing a #sound-dai-cells property. Add it, so that the sounds node can be used in combination with the simple-audio-card binding. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1399141819-23924-5-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 0399a096e324..afc640cd80c5 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -372,6 +372,7 @@ audio0: audio-controller@a0000 { compatible = "marvell,kirkwood-audio"; + #sound-dai-cells = <0>; reg = <0xa0000 0x2210>; interrupts = <24>; clocks = <&gate_clk 9>; -- cgit v1.2.3 From 191825c38eafeda033a73338f5a710fa6fd5b3d6 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 3 May 2014 20:30:17 +0200 Subject: ARM: Kirkwood: t5325: Use simple card to instantiate audio Add device tree nodes to instantiate the audio drivers on the HP T5325 device. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1399141819-23924-8-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper --- arch/arm/boot/dts/kirkwood-t5325.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index 291eff4fd353..610ec0f95858 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -187,6 +187,31 @@ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; }; + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,routing = + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "Speaker", "SPKOUT", + "Speaker", "SPKOUTN", + "MIC1", "Mic Jack", + "MIC2", "Mic Jack"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Speaker", "Speaker", + "Microphone", "Mic Jack"; + + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&audio>; + }; + + simple-audio-card,codec { + sound-dai = <&alc5621>; + }; + }; }; &mdio { -- cgit v1.2.3 From 474684809f76c76d87dcf8417fa9ce65dc01ac75 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 3 May 2014 20:30:18 +0200 Subject: ARM: mvebu_v5_defconfig: Enable sound modules needed for t5325 Enable simple-card and the CODEC. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1399141819-23924-9-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper --- arch/arm/configs/mvebu_v5_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig index 4a2baa9ea9fb..27c732fdf21e 100644 --- a/arch/arm/configs/mvebu_v5_defconfig +++ b/arch/arm/configs/mvebu_v5_defconfig @@ -12,7 +12,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MVEBU=y CONFIG_MACH_KIRKWOOD=y -CONFIG_MACH_T5325=y # CONFIG_CPU_FEROCEON_OLD_ID is not set CONFIG_PCI_MVEBU=y CONFIG_PREEMPT=y @@ -102,6 +101,8 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_KIRKWOOD_SOC=y CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_SND_SOC_ALC5623=y +CONFIG_SND_SIMPLE_CARD=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_HID_DRAGONRISE=y -- cgit v1.2.3 From 208f4e0d9bce775fbc7ab08c830d135d3da5777c Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Sat, 3 May 2014 20:30:19 +0200 Subject: ARM: multi_v5_defconfig: Enable sound modules needed for t5325 Enable simple-card and the CODEC. Signed-off-by: Andrew Lunn Link: https://lkml.kernel.org/r/1399141819-23924-10-git-send-email-andrew@lunn.ch Signed-off-by: Jason Cooper --- arch/arm/configs/multi_v5_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index aa3dfb084fed..5ebfa8bf8509 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -11,7 +11,6 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MVEBU=y CONFIG_MACH_KIRKWOOD=y -CONFIG_MACH_T5325=y CONFIG_ARCH_MXC=y CONFIG_MACH_IMX25_DT=y CONFIG_MACH_IMX27_DT=y @@ -108,6 +107,8 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_KIRKWOOD_SOC=y CONFIG_SND_KIRKWOOD_SOC_T5325=y +CONFIG_SND_SOC_ALC5623=y +CONFIG_SND_SIMPLE_CARD=y # CONFIG_ABX500_CORE is not set CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -- cgit v1.2.3 From 559482d1f950b7905728208d16cf5785cc6093ea Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 28 Apr 2014 16:03:20 -0700 Subject: ARM: sunxi: Split the various SoCs support in Kconfig This will allow to better isolate various options, and reduce the overall kernel size if we're interested in only one of the SoCs. Signed-off-by: Maxime Ripard --- arch/arm/mach-sunxi/Kconfig | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index b57d7d53b9d3..3aff96602868 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,14 +1,37 @@ -config ARCH_SUNXI - bool "Allwinner A1X SOCs" if ARCH_MULTI_V7 - select ARCH_HAS_RESET_CONTROLLER +menuconfig ARCH_SUNXI + bool "Allwinner SoCs" if ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB - select ARM_GIC - select ARM_PSCI select CLKSRC_MMIO select GENERIC_IRQ_CHIP - select HAVE_ARM_ARCH_TIMER select PINCTRL select PINCTRL_SUNXI - select RESET_CONTROLLER select SUN4I_TIMER + +if ARCH_SUNXI + +config MACH_SUN4I + bool "Allwinner A10 (sun4i) SoCs support" + default ARCH_SUNXI + +config MACH_SUN5I + bool "Allwinner A10s / A13 (sun5i) SoCs support" + default ARCH_SUNXI + select SUN5I_HSTIMER + +config MACH_SUN6I + bool "Allwinner A31 (sun6i) SoCs support" + default ARCH_SUNXI + select ARCH_HAS_RESET_CONTROLLER + select ARM_GIC + select RESET_CONTROLLER + select SUN5I_HSTIMER + +config MACH_SUN7I + bool "Allwinner A20 (sun7i) SoCs support" + default ARCH_SUNXI + select ARM_GIC + select ARM_PSCI + select HAVE_ARM_ARCH_TIMER select SUN5I_HSTIMER + +endif -- cgit v1.2.3 From b258b369e8ec4b6f544265aea52bb74476185b12 Mon Sep 17 00:00:00 2001 From: David Lanzendörfer Date: Fri, 2 May 2014 17:57:18 +0200 Subject: ARM: dts: sun4i: Add mmc controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes for the 4 mmc controllers found on A10 SoCs to arch/arm/boot/dts/sun4i-a10.dtsi. Signed-off-by: David Lanzendörfer Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 4dc376170dd0..aa7fcedb84aa 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -377,6 +377,42 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun4i-a10-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <35>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun4i-a10-usb-phy"; -- cgit v1.2.3 From b5f86a3a719d2defb6b4144f75bfd92342f01aaa Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:19 +0200 Subject: ARM: dts: sun4i: Add pin-muxing info for the mmc0 controller mmc0 is the only controller actually being used on boards, so limit the pin-muxing options to that. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index aa7fcedb84aa..c7b794ed337d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -579,6 +579,20 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; }; timer@01c20c00 { -- cgit v1.2.3 From c0955a86f4af4fef7965bfcd41a9642a3f67486b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:20 +0200 Subject: ARM: dts: sun4i: Enable mmc controller on various A10 boards Tested on a subset of these boards, for the others boards the settings match the ones of the tested boards according to the original firmware fex files. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 9 +++++++++ arch/arm/boot/dts/sun4i-a10-pcduino.dts | 9 +++++++++ 7 files changed, 63 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index fa746aea5e66..93af30699895 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -36,6 +36,15 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 4684cbe6843b..8581385d277e 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -34,6 +34,15 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index d7c17e46ce23..9dc7b1c1dd9e 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -36,6 +36,15 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index fe9272ee55c3..297b8f6b39a3 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -24,6 +24,15 @@ }; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index dd84a9e313b3..b7a4218ef2a4 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -20,6 +20,15 @@ compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index 66cf0c7cf5b7..4b7fd04ea488 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -33,6 +33,15 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 255b47e7019c..4d9c3cdddced 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -34,6 +34,15 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; -- cgit v1.2.3 From d3aed1dfbd2e66ff2eca14897fa141a989a36fb0 Mon Sep 17 00:00:00 2001 From: David Lanzendörfer Date: Fri, 2 May 2014 17:57:21 +0200 Subject: ARM: dts: sun5i: Add mmc controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc controllers found on A13 SoCs. Signed-off-by: David Lanzendörfer Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13.dtsi | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 9493b2129886..aa1dd59dc34a 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -338,6 +338,33 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <33>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index dda9df69e033..c9fdb7b3ecd9 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -320,6 +320,24 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <32>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <34>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun5i-a13-usb-phy"; -- cgit v1.2.3 From 31064bbd6dc3d49fe18f97d81e6ef2cb0358c9c8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:22 +0200 Subject: ARM: dts: sun5i: Enable mmc controller on various A10s and A13 boards The cd pin settings have been taken from the original firmware fex files, and have been confirmed to work on the actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 32 ++++++++++++++++++++++++ arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 16 ++++++++++++ arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 16 ++++++++++++ 3 files changed, 64 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index 23611b71d3aa..de9130848704 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -35,6 +35,24 @@ }; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>; + bus-width = <4>; + cd-gpios = <&pio 6 1 0>; /* PG1 */ + cd-inverted; + status = "okay"; + }; + + mmc1: mmc@01c10000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>; + bus-width = <4>; + cd-gpios = <&pio 6 13 0>; /* PG13 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -49,6 +67,20 @@ }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 { + allwinner,pins = "PG13"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PE3"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index 11169d5b5b86..8515f19477d2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -21,6 +21,15 @@ compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -35,6 +44,13 @@ }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxinom: led_pins@0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out"; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 7a9187bbeb28..51a943837cb2 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -20,6 +20,15 @@ compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; @@ -34,6 +43,13 @@ }; pinctrl@01c20800 { + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PG9"; allwinner,function = "gpio_out"; -- cgit v1.2.3 From adc54c858499436f049cc7252de617314e7bacf2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:23 +0200 Subject: ARM: dts: sun6i: Add mmc clocks Add clk-nodes for the mmc clocks. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 30138cd935d4..0cbb5404ff13 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -206,6 +206,38 @@ "apb2_uart4", "apb2_uart5"; }; + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2"; + }; + + mmc3_clk: clk@01c20094 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20094 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc3"; + }; + spi0_clk: clk@01c200a0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; -- cgit v1.2.3 From 5b753f0e27da2b0a29142be0833784475bc29366 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:24 +0200 Subject: ARM: dts: sun6i: Add mmc controller nodes Add nodes for the 4 mmc controllers found on A31 SoCs to arch/arm/boot/dts/sun6i-a31.dtsi. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 0cbb5404ff13..eec1afa257a5 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -286,6 +286,50 @@ #dma-cells = <1>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 9>; + reset-names = "ahb"; + interrupts = <0 61 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + interrupts = <0 62 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb1_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 11>; + reset-names = "ahb"; + interrupts = <0 63 4>; + status = "disabled"; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun6i-a31-pinctrl"; reg = <0x01c20800 0x400>; -- cgit v1.2.3 From 0ff1ffd3fe86840c80458ea45c2379014c86b660 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:25 +0200 Subject: ARM: dts: sun6i: Add new sun6i-a31-m9 dts file for Mele M9 Add a new sun6i-a31-m9 dts file for the Mele M9 / Mele A1000G Quad. These HTPCs use the same board in a different case, for more details see: http://linux-sunxi.org/Mele_M9 Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31-m9.dts | 48 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31-m9.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..1cd137dc69e5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -351,6 +351,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun6i-a31-colombus.dtb \ + sun6i-a31-m9.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ sun7i-a20-olinuxino-micro.dtb diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts new file mode 100644 index 000000000000..22eacf83997a --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2014 Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" + +/ { + model = "Mele M9 / A1000G Quad top set box"; + compatible = "mele,m9", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>; + bus-width = <4>; + cd-gpios = <&pio 7 22 0>; /* PH22 */ + cd-inverted; + status = "okay"; + }; + + pio: pinctrl@01c20800 { + mmc0_cd_pin_m9: mmc0_cd_pin@0 { + allwinner,pins = "PH22"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + }; +}; -- cgit v1.2.3 From dd29ce53b2a48bbb29eaa4a0c86a7a5f36c3d9c0 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:26 +0200 Subject: ARM: dts: sun7i: Add mmc controller nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add nodes for the 4 mmc controllers found on A20 SoCs to arch/arm/boot/dts/sun7i-a20.dtsi. Signed-off-by: David Lanzendörfer Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index ea62839a5e2f..e64aa4dd4f39 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -453,6 +453,42 @@ #size-cells = <0>; }; + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 32 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 33 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 34 4>; + status = "disabled"; + }; + + mmc3: mmc@01c12000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c12000 0x1000>; + clocks = <&ahb_gates 11>, <&mmc3_clk>; + clock-names = "ahb", "mmc"; + interrupts = <0 35 4>; + status = "disabled"; + }; + usbphy: phy@01c13400 { #phy-cells = <1>; compatible = "allwinner,sun7i-a20-usb-phy"; -- cgit v1.2.3 From 11fbedf4dd960db39b40aa59253bb7375df54241 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:27 +0200 Subject: ARM: dts: sun7i: Add pin-muxing info for the mmc controllers This adds pin-muxing info for the mmc controller / port combinations which are known to be used on actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index e64aa4dd4f39..56df970ffe25 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -709,6 +709,27 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + mmc3_pins_a: mmc3@0 { + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; + allwinner,function = "mmc3"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { -- cgit v1.2.3 From c621183c203affa526c15e46432c24f31afed997 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 2 May 2014 17:57:28 +0200 Subject: ARM: dts: sun7i: Enable mmc controller on various A20 boards The cd pin settings have been taken from the original firmware fex files, and have been confirmed to work on the actual boards. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 9 +++++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 9 +++++++++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 25 +++++++++++++++++++++++++ 3 files changed, 43 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index 68de89ffbdfa..3918e2f6e8ca 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -20,6 +20,15 @@ compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 0c3bd127a5fd..a39f08970b64 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -20,6 +20,15 @@ compatible = "cubietech,cubietruck", "allwinner,sun7i-a20"; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index eeadf76362fa..1bfef12cf9d1 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -31,6 +31,24 @@ status = "okay"; }; + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>; + bus-width = <4>; + cd-gpios = <&pio 7 11 0>; /* PH11 */ + cd-inverted; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -65,6 +83,13 @@ }; pinctrl@01c20800 { + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + led_pins_olinuxino: led_pins@0 { allwinner,pins = "PH2"; allwinner,function = "gpio_out"; -- cgit v1.2.3 From aad9061bf37e05d29a2a94ae8fe1e12d8808a0dd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 11 Mar 2014 11:23:39 +0100 Subject: arm64: mm: Remove superfluous "the" in comment Signed-off-by: Geert Uytterhoeven Cc: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Jiri Kosina --- arch/arm64/include/asm/pgtable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 90c811f05a2e..97c39bab06be 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -406,7 +406,7 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; /* * Ensure that there are not more swap files than can be encoded in the kernel - * the PTEs. + * PTEs. */ #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) -- cgit v1.2.3 From fba387a6162cf5cefba3610eb6f4f67cdbb4d2ca Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Thu, 10 Apr 2014 11:34:32 -0500 Subject: ARM: dts: DRA7: Use dra7-l3-noc instead of omap4-l3-noc We have currently marked the DRA7 L3 as being compatible with omap4-l3-noc This is not true considering the differences in data involved. Now that we have proper support for ti,dra7-l3-noc, add the clock modules clk1 and clk3 (clk2 submodule will be handled by the driver) and switch compatibility flag to use the proper data. Signed-off-by: Rajendra Nayak [nm@ti.com: map up full address range] Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/dra7.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1fd75aa4639d..8c62664149f0 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -94,13 +94,13 @@ * hierarchy. */ ocp { - compatible = "ti,omap4-l3-noc", "simple-bus"; + compatible = "ti,dra7-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>; + reg = <0x44000000 0x1000000>, + <0x45000000 0x1000>; interrupts = , ; -- cgit v1.2.3 From 2eeddb8a5356e088021a8dd84de870de89bf793d Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Mon, 2 Dec 2013 17:48:57 +0530 Subject: ARM: dts: AM4372: add l3-noc information AM4372 has two clk domains 100f and 200s. Provide register mapping, interrupt information and compatibility flags associated with it. Signed-off-by: Dave Gerlach Signed-off-by: Afzal Mohammed Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/am4372.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index c6bd4d986c29..032ba8777e85 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -61,11 +61,15 @@ }; ocp { - compatible = "simple-bus"; + compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; ti,hwmods = "l3_main"; + reg = <0x44000000 0x400000 + 0x44800000 0x400000>; + interrupts = , + ; prcm: prcm@44df0000 { compatible = "ti,am4-prcm"; -- cgit v1.2.3 From 73159fdcdb9be3eda61b846864352c29371baeb6 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:31 -0700 Subject: x86, mm: Ensure correct alignment of the fixmap The early_ioremap code requires that its buffers not span a PMD boundary. The logic for ensuring that only works if the fixmap is aligned, so assert that it's aligned correctly. To make this work reliably, reserve_top_address needs to be adjusted. Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/e59a5f4362661f75dd4841fa74e1f2448045e245.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/mm/ioremap.c | 6 ++++++ arch/x86/mm/pgtable.c | 6 +++--- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 597ac155c91c..6ef98c55a899 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c @@ -355,6 +355,12 @@ void __init early_ioremap_init(void) { pmd_t *pmd; +#ifdef CONFIG_X86_64 + BUILD_BUG_ON((fix_to_virt(0) + PAGE_SIZE) & ((1 << PMD_SHIFT) - 1)); +#else + WARN_ON((fix_to_virt(0) + PAGE_SIZE) & ((1 << PMD_SHIFT) - 1)); +#endif + early_ioremap_setup(); pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)); diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index c96314abd144..5f8bdda1d1ba 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -449,9 +449,9 @@ void __init reserve_top_address(unsigned long reserve) { #ifdef CONFIG_X86_32 BUG_ON(fixmaps_set > 0); - printk(KERN_INFO "Reserving virtual address space above 0x%08x\n", - (int)-reserve); - __FIXADDR_TOP = -reserve - PAGE_SIZE; + __FIXADDR_TOP = round_down(-reserve, 1 << PMD_SHIFT) - PAGE_SIZE; + printk(KERN_INFO "Reserving virtual address space above 0x%08lx (rounded to 0x%08lx)\n", + -reserve, __FIXADDR_TOP + PAGE_SIZE); #endif } -- cgit v1.2.3 From 3d7ee969bffcc984c8aeaffc6ac6816fd929ace1 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:32 -0700 Subject: x86, vdso: Clean up 32-bit vs 64-bit vdso params Rather than using 'vdso_enabled' and an awful #define, just call the parameters vdso32_enabled and vdso64_enabled. Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/87913de56bdcbae3d93917938302fc369b05caee.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/elf.h | 20 +++++++++++++------- arch/x86/um/vdso/vma.c | 2 +- arch/x86/vdso/vdso32-setup.c | 19 ++++++++----------- arch/x86/vdso/vma.c | 6 +++--- kernel/sysctl.c | 5 +++++ 5 files changed, 30 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h index 2c71182d30ef..e96df2c0dd69 100644 --- a/arch/x86/include/asm/elf.h +++ b/arch/x86/include/asm/elf.h @@ -75,7 +75,12 @@ typedef struct user_fxsr_struct elf_fpxregset_t; #include -extern unsigned int vdso_enabled; +#ifdef CONFIG_X86_64 +extern unsigned int vdso64_enabled; +#endif +#if defined(CONFIG_X86_32) || defined(CONFIG_COMPAT) +extern unsigned int vdso32_enabled; +#endif /* * This is used to ensure we don't load something for the wrong architecture. @@ -269,9 +274,9 @@ extern int force_personality32; struct task_struct; -#define ARCH_DLINFO_IA32(vdso_enabled) \ +#define ARCH_DLINFO_IA32 \ do { \ - if (vdso_enabled) { \ + if (vdso32_enabled) { \ NEW_AUX_ENT(AT_SYSINFO, VDSO_ENTRY); \ NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_CURRENT_BASE); \ } \ @@ -281,7 +286,7 @@ do { \ #define STACK_RND_MASK (0x7ff) -#define ARCH_DLINFO ARCH_DLINFO_IA32(vdso_enabled) +#define ARCH_DLINFO ARCH_DLINFO_IA32 /* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */ @@ -292,14 +297,15 @@ do { \ #define ARCH_DLINFO \ do { \ - if (vdso_enabled) \ + if (vdso64_enabled) \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ (unsigned long)current->mm->context.vdso); \ } while (0) +/* As a historical oddity, the x32 and x86_64 vDSOs are controlled together. */ #define ARCH_DLINFO_X32 \ do { \ - if (vdso_enabled) \ + if (vdso64_enabled) \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ (unsigned long)current->mm->context.vdso); \ } while (0) @@ -310,7 +316,7 @@ do { \ if (test_thread_flag(TIF_X32)) \ ARCH_DLINFO_X32; \ else \ - ARCH_DLINFO_IA32(sysctl_vsyscall32) + ARCH_DLINFO_IA32 #define COMPAT_ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x1000000) diff --git a/arch/x86/um/vdso/vma.c b/arch/x86/um/vdso/vma.c index af91901babb8..916cda4cd5b4 100644 --- a/arch/x86/um/vdso/vma.c +++ b/arch/x86/um/vdso/vma.c @@ -12,7 +12,7 @@ #include #include -unsigned int __read_mostly vdso_enabled = 1; +static unsigned int __read_mostly vdso_enabled = 1; unsigned long um_vdso_addr; extern unsigned long task_size; diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c index 00348980a3a6..5a657d93c6e0 100644 --- a/arch/x86/vdso/vdso32-setup.c +++ b/arch/x86/vdso/vdso32-setup.c @@ -37,7 +37,6 @@ #endif #ifdef CONFIG_X86_64 -#define vdso_enabled sysctl_vsyscall32 #define arch_setup_additional_pages syscall32_setup_pages #endif @@ -45,13 +44,13 @@ * Should the kernel map a VDSO page into processes and pass its * address down to glibc upon exec()? */ -unsigned int __read_mostly vdso_enabled = VDSO_DEFAULT; +unsigned int __read_mostly vdso32_enabled = VDSO_DEFAULT; -static int __init vdso_setup(char *s) +static int __init vdso32_setup(char *s) { - vdso_enabled = simple_strtoul(s, NULL, 0); + vdso32_enabled = simple_strtoul(s, NULL, 0); - if (vdso_enabled > 1) + if (vdso32_enabled > 1) pr_warn("vdso32 values other than 0 and 1 are no longer allowed; vdso disabled\n"); return 1; @@ -62,12 +61,10 @@ static int __init vdso_setup(char *s) * behavior on both 64-bit and 32-bit kernels. * On 32-bit kernels, vdso=[012] means the same thing. */ -__setup("vdso32=", vdso_setup); +__setup("vdso32=", vdso32_setup); #ifdef CONFIG_X86_32 -__setup_param("vdso=", vdso32_setup, vdso_setup, 0); - -EXPORT_SYMBOL_GPL(vdso_enabled); +__setup_param("vdso=", vdso_setup, vdso32_setup, 0); #endif static struct page **vdso32_pages; @@ -160,7 +157,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) return x32_setup_additional_pages(bprm, uses_interp); #endif - if (vdso_enabled != 1) /* Other values all mean "disabled" */ + if (vdso32_enabled != 1) /* Other values all mean "disabled" */ return 0; down_write(&mm->mmap_sem); @@ -244,7 +241,7 @@ subsys_initcall(sysenter_setup); static struct ctl_table abi_table2[] = { { .procname = "vsyscall32", - .data = &sysctl_vsyscall32, + .data = &vdso32_enabled, .maxlen = sizeof(int), .mode = 0644, .proc_handler = proc_dointvec diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c index 1ad102613127..8b790398ed1d 100644 --- a/arch/x86/vdso/vma.c +++ b/arch/x86/vdso/vma.c @@ -17,7 +17,7 @@ #include #if defined(CONFIG_X86_64) -unsigned int __read_mostly vdso_enabled = 1; +unsigned int __read_mostly vdso64_enabled = 1; DECLARE_VDSO_IMAGE(vdso); extern unsigned short vdso_sync_cpuid; @@ -160,7 +160,7 @@ static int setup_additional_pages(struct linux_binprm *bprm, unsigned long addr; int ret; - if (!vdso_enabled) + if (!vdso64_enabled) return 0; down_write(&mm->mmap_sem); @@ -203,7 +203,7 @@ int x32_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) static __init int vdso_setup(char *s) { - vdso_enabled = simple_strtoul(s, NULL, 0); + vdso64_enabled = simple_strtoul(s, NULL, 0); return 0; } __setup("vdso=", vdso_setup); diff --git a/kernel/sysctl.c b/kernel/sysctl.c index 74f5b580fe34..420d77afa8fd 100644 --- a/kernel/sysctl.c +++ b/kernel/sysctl.c @@ -1418,8 +1418,13 @@ static struct ctl_table vm_table[] = { (defined(CONFIG_SUPERH) && defined(CONFIG_VSYSCALL)) { .procname = "vdso_enabled", +#ifdef CONFIG_X86_32 + .data = &vdso32_enabled, + .maxlen = sizeof(vdso32_enabled), +#else .data = &vdso_enabled, .maxlen = sizeof(vdso_enabled), +#endif .mode = 0644, .proc_handler = proc_dointvec, .extra1 = &zero, -- cgit v1.2.3 From cfda7bb9ecbf9d96264bb5bade33a842966d1062 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:33 -0700 Subject: x86, vdso: Move syscall and sysenter setup into kernel/cpu/common.c This code is used during CPU setup, and it isn't strictly speaking related to the 32-bit vdso. It's easier to understand how this works when the code is closer to its callers. This also lets syscall32_cpu_init be static, which might save some trivial amount of kernel text. Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/4e466987204e232d7b55a53ff6b9739f12237461.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/proto.h | 2 -- arch/x86/kernel/cpu/common.c | 32 ++++++++++++++++++++++++++++++++ arch/x86/vdso/vdso32-setup.c | 30 ------------------------------ 3 files changed, 32 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/proto.h b/arch/x86/include/asm/proto.h index 6fd3fd769796..a90f8972dad5 100644 --- a/arch/x86/include/asm/proto.h +++ b/arch/x86/include/asm/proto.h @@ -12,8 +12,6 @@ void ia32_syscall(void); void ia32_cstar_target(void); void ia32_sysenter_target(void); -void syscall32_cpu_init(void); - void x86_configure_nx(void); void x86_report_nx(void); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a135239badb7..7c65b4666c24 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -953,6 +953,38 @@ static void vgetcpu_set_mode(void) else vgetcpu_mode = VGETCPU_LSL; } + +/* May not be __init: called during resume */ +static void syscall32_cpu_init(void) +{ + /* Load these always in case some future AMD CPU supports + SYSENTER from compat mode too. */ + wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); + wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); + wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); + + wrmsrl(MSR_CSTAR, ia32_cstar_target); +} +#endif + +#ifdef CONFIG_X86_32 +void enable_sep_cpu(void) +{ + int cpu = get_cpu(); + struct tss_struct *tss = &per_cpu(init_tss, cpu); + + if (!boot_cpu_has(X86_FEATURE_SEP)) { + put_cpu(); + return; + } + + tss->x86_tss.ss1 = __KERNEL_CS; + tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss; + wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); + wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0); + wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0); + put_cpu(); +} #endif void __init identify_boot_cpu(void) diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c index 5a657d93c6e0..9c78d5b24874 100644 --- a/arch/x86/vdso/vdso32-setup.c +++ b/arch/x86/vdso/vdso32-setup.c @@ -75,41 +75,11 @@ static unsigned vdso32_size; #define vdso32_sysenter() (boot_cpu_has(X86_FEATURE_SYSENTER32)) #define vdso32_syscall() (boot_cpu_has(X86_FEATURE_SYSCALL32)) -/* May not be __init: called during resume */ -void syscall32_cpu_init(void) -{ - /* Load these always in case some future AMD CPU supports - SYSENTER from compat mode too. */ - wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); - wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); - wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); - - wrmsrl(MSR_CSTAR, ia32_cstar_target); -} - #else /* CONFIG_X86_32 */ #define vdso32_sysenter() (boot_cpu_has(X86_FEATURE_SEP)) #define vdso32_syscall() (0) -void enable_sep_cpu(void) -{ - int cpu = get_cpu(); - struct tss_struct *tss = &per_cpu(init_tss, cpu); - - if (!boot_cpu_has(X86_FEATURE_SEP)) { - put_cpu(); - return; - } - - tss->x86_tss.ss1 = __KERNEL_CS; - tss->x86_tss.sp1 = sizeof(struct tss_struct) + (unsigned long) tss; - wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); - wrmsr(MSR_IA32_SYSENTER_ESP, tss->x86_tss.sp1, 0); - wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long) ia32_sysenter_target, 0); - put_cpu(); -} - #endif /* CONFIG_X86_64 */ int __init sysenter_setup(void) -- cgit v1.2.3 From 6f121e548f83674ab4920a4e60afb58d4f61b829 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:34 -0700 Subject: x86, vdso: Reimplement vdso.so preparation in build-time C Currently, vdso.so files are prepared and analyzed by a combination of objcopy, nm, some linker script tricks, and some simple ELF parsers in the kernel. Replace all of that with plain C code that runs at build time. All five vdso images now generate .c files that are compiled and linked in to the kernel image. This should cause only one userspace-visible change: the loaded vDSO images are stripped more heavily than they used to be. Everything outside the loadable segment is dropped. In particular, this causes the section table and section name strings to be missing. This should be fine: real dynamic loaders don't load or inspect these tables anyway. The result is roughly equivalent to eu-strip's --strip-sections option. The purpose of this change is to enable the vvar and hpet mappings to be moved to the page following the vDSO load segment. Currently, it is possible for the section table to extend into the page after the load segment, so, if we map it, it risks overlapping the vvar or hpet page. This happens whenever the load segment is just under a multiple of PAGE_SIZE. The only real subtlety here is that the old code had a C file with inline assembler that did 'call VDSO32_vsyscall' and a linker script that defined 'VDSO32_vsyscall = __kernel_vsyscall'. This most likely worked by accident: the linker script entry defines a symbol associated with an address as opposed to an alias for the real dynamic symbol __kernel_vsyscall. That caused ld to relocate the reference at link time instead of leaving an interposable dynamic relocation. Since the VDSO32_vsyscall hack is no longer needed, I now use 'call __kernel_vsyscall', and I added -Bsymbolic to make it work. vdso2c will generate an error and abort the build if the resulting image contains any dynamic relocations, so we won't silently generate bad vdso images. (Dynamic relocations are a problem because nothing will even attempt to relocate the vdso.) Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/2c4fcf45524162a34d87fdda1eb046b2a5cecee7.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/ia32/ia32_signal.c | 8 +-- arch/x86/include/asm/elf.h | 7 +- arch/x86/include/asm/mmu.h | 2 +- arch/x86/include/asm/vdso.h | 70 +++++++------------ arch/x86/kernel/signal.c | 6 +- arch/x86/mm/init_64.c | 3 +- arch/x86/vdso/.gitignore | 5 +- arch/x86/vdso/Makefile | 90 +++++++++--------------- arch/x86/vdso/vclock_gettime.c | 4 +- arch/x86/vdso/vdso.S | 3 - arch/x86/vdso/vdso2c.c | 142 ++++++++++++++++++++++++++++++++++++++ arch/x86/vdso/vdso2c.h | 137 ++++++++++++++++++++++++++++++++++++ arch/x86/vdso/vdso32-setup.c | 50 ++++++-------- arch/x86/vdso/vdso32.S | 9 --- arch/x86/vdso/vdso32/vdso32.lds.S | 10 --- arch/x86/vdso/vdsox32.S | 3 - arch/x86/vdso/vma.c | 100 +++++---------------------- arch/x86/xen/setup.c | 11 ++- 18 files changed, 400 insertions(+), 260 deletions(-) delete mode 100644 arch/x86/vdso/vdso.S create mode 100644 arch/x86/vdso/vdso2c.c create mode 100644 arch/x86/vdso/vdso2c.h delete mode 100644 arch/x86/vdso/vdso32.S delete mode 100644 arch/x86/vdso/vdsox32.S (limited to 'arch') diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index 220675795e08..f9e181aaba97 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -383,8 +383,8 @@ int ia32_setup_frame(int sig, struct ksignal *ksig, } else { /* Return stub is in 32bit vsyscall page */ if (current->mm->context.vdso) - restorer = VDSO32_SYMBOL(current->mm->context.vdso, - sigreturn); + restorer = current->mm->context.vdso + + selected_vdso32->sym___kernel_sigreturn; else restorer = &frame->retcode; } @@ -462,8 +462,8 @@ int ia32_setup_rt_frame(int sig, struct ksignal *ksig, if (ksig->ka.sa.sa_flags & SA_RESTORER) restorer = ksig->ka.sa.sa_restorer; else - restorer = VDSO32_SYMBOL(current->mm->context.vdso, - rt_sigreturn); + restorer = current->mm->context.vdso + + selected_vdso32->sym___kernel_rt_sigreturn; put_user_ex(ptr_to_compat(restorer), &frame->pretcode); /* diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h index e96df2c0dd69..65b21bcbe9f7 100644 --- a/arch/x86/include/asm/elf.h +++ b/arch/x86/include/asm/elf.h @@ -299,7 +299,7 @@ do { \ do { \ if (vdso64_enabled) \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (unsigned long)current->mm->context.vdso); \ + (unsigned long __force)current->mm->context.vdso); \ } while (0) /* As a historical oddity, the x32 and x86_64 vDSOs are controlled together. */ @@ -307,7 +307,7 @@ do { \ do { \ if (vdso64_enabled) \ NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (unsigned long)current->mm->context.vdso); \ + (unsigned long __force)current->mm->context.vdso); \ } while (0) #define AT_SYSINFO 32 @@ -325,7 +325,8 @@ else \ #define VDSO_CURRENT_BASE ((unsigned long)current->mm->context.vdso) #define VDSO_ENTRY \ - ((unsigned long)VDSO32_SYMBOL(VDSO_CURRENT_BASE, vsyscall)) + ((unsigned long)current->mm->context.vdso + \ + selected_vdso32->sym___kernel_vsyscall) struct linux_binprm; diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 5f55e6962769..876e74e8eec7 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -18,7 +18,7 @@ typedef struct { #endif struct mutex lock; - void *vdso; + void __user *vdso; } mm_context_t; #ifdef CONFIG_SMP diff --git a/arch/x86/include/asm/vdso.h b/arch/x86/include/asm/vdso.h index d1dc55404ff1..389fe2ca27c2 100644 --- a/arch/x86/include/asm/vdso.h +++ b/arch/x86/include/asm/vdso.h @@ -3,63 +3,43 @@ #include #include +#include -#ifdef __ASSEMBLER__ +#ifndef __ASSEMBLER__ -#define DEFINE_VDSO_IMAGE(symname, filename) \ -__PAGE_ALIGNED_DATA ; \ - .globl symname##_start, symname##_end ; \ - .align PAGE_SIZE ; \ - symname##_start: ; \ - .incbin filename ; \ - symname##_end: ; \ - .align PAGE_SIZE /* extra data here leaks to userspace. */ ; \ - \ -.previous ; \ - \ - .globl symname##_pages ; \ - .bss ; \ - .align 8 ; \ - .type symname##_pages, @object ; \ - symname##_pages: ; \ - .zero (symname##_end - symname##_start + PAGE_SIZE - 1) / PAGE_SIZE * (BITS_PER_LONG / 8) ; \ - .size symname##_pages, .-symname##_pages +struct vdso_image { + void *data; + unsigned long size; /* Always a multiple of PAGE_SIZE */ + struct page **pages; /* Big enough for data/size page pointers */ -#else + unsigned long alt, alt_len; -#define DECLARE_VDSO_IMAGE(symname) \ - extern char symname##_start[], symname##_end[]; \ - extern struct page *symname##_pages[] + unsigned long sym_VDSO32_NOTE_MASK; + unsigned long sym___kernel_sigreturn; + unsigned long sym___kernel_rt_sigreturn; + unsigned long sym___kernel_vsyscall; + unsigned long sym_VDSO32_SYSENTER_RETURN; +}; -#if defined CONFIG_X86_32 || defined CONFIG_COMPAT +#ifdef CONFIG_X86_64 +extern const struct vdso_image vdso_image_64; +#endif -#include +#ifdef CONFIG_X86_X32 +extern const struct vdso_image vdso_image_x32; +#endif -DECLARE_VDSO_IMAGE(vdso32_int80); +#if defined CONFIG_X86_32 || defined CONFIG_COMPAT +extern const struct vdso_image vdso_image_32_int80; #ifdef CONFIG_COMPAT -DECLARE_VDSO_IMAGE(vdso32_syscall); +extern const struct vdso_image vdso_image_32_syscall; #endif -DECLARE_VDSO_IMAGE(vdso32_sysenter); +extern const struct vdso_image vdso_image_32_sysenter; -/* - * Given a pointer to the vDSO image, find the pointer to VDSO32_name - * as that symbol is defined in the vDSO sources or linker script. - */ -#define VDSO32_SYMBOL(base, name) \ -({ \ - extern const char VDSO32_##name[]; \ - (void __user *)(VDSO32_##name + (unsigned long)(base)); \ -}) +extern const struct vdso_image *selected_vdso32; #endif -/* - * These symbols are defined with the addresses in the vsyscall page. - * See vsyscall-sigreturn.S. - */ -extern void __user __kernel_sigreturn; -extern void __user __kernel_rt_sigreturn; - -void __init patch_vdso32(void *vdso, size_t len); +extern void __init init_vdso_image(const struct vdso_image *image); #endif /* __ASSEMBLER__ */ diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c index 9e5de6813e1f..a0da58db43a8 100644 --- a/arch/x86/kernel/signal.c +++ b/arch/x86/kernel/signal.c @@ -298,7 +298,8 @@ __setup_frame(int sig, struct ksignal *ksig, sigset_t *set, } if (current->mm->context.vdso) - restorer = VDSO32_SYMBOL(current->mm->context.vdso, sigreturn); + restorer = current->mm->context.vdso + + selected_vdso32->sym___kernel_sigreturn; else restorer = &frame->retcode; if (ksig->ka.sa.sa_flags & SA_RESTORER) @@ -361,7 +362,8 @@ static int __setup_rt_frame(int sig, struct ksignal *ksig, save_altstack_ex(&frame->uc.uc_stack, regs->sp); /* Set up to return from userspace. */ - restorer = VDSO32_SYMBOL(current->mm->context.vdso, rt_sigreturn); + restorer = current->mm->context.vdso + + selected_vdso32->sym___kernel_sigreturn; if (ksig->ka.sa.sa_flags & SA_RESTORER) restorer = ksig->ka.sa.sa_restorer; put_user_ex(restorer, &frame->pretcode); diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index f35c66c5959a..563849600d3e 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -1223,7 +1223,8 @@ int in_gate_area_no_mm(unsigned long addr) const char *arch_vma_name(struct vm_area_struct *vma) { - if (vma->vm_mm && vma->vm_start == (long)vma->vm_mm->context.vdso) + if (vma->vm_mm && vma->vm_start == + (long __force)vma->vm_mm->context.vdso) return "[vdso]"; if (vma == &gate_vma) return "[vsyscall]"; diff --git a/arch/x86/vdso/.gitignore b/arch/x86/vdso/.gitignore index 3282874bc61d..aae8ffdd5880 100644 --- a/arch/x86/vdso/.gitignore +++ b/arch/x86/vdso/.gitignore @@ -1,8 +1,7 @@ vdso.lds -vdso-syms.lds vdsox32.lds -vdsox32-syms.lds -vdso32-syms.lds vdso32-syscall-syms.lds vdso32-sysenter-syms.lds vdso32-int80-syms.lds +vdso-image-*.c +vdso2c diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile index c580d1210ffe..895d4b16b7e3 100644 --- a/arch/x86/vdso/Makefile +++ b/arch/x86/vdso/Makefile @@ -24,15 +24,30 @@ vobj64s := $(filter-out $(vobjx32s-compat),$(vobjs-y)) # files to link into kernel obj-y += vma.o -obj-$(VDSO64-y) += vdso.o -obj-$(VDSOX32-y) += vdsox32.o -obj-$(VDSO32-y) += vdso32.o vdso32-setup.o + +# vDSO images to build +vdso_img-$(VDSO64-y) += 64 +vdso_img-$(VDSOX32-y) += x32 +vdso_img-$(VDSO32-y) += 32-int80 +vdso_img-$(CONFIG_COMPAT) += 32-syscall +vdso_img-$(VDSO32-y) += 32-sysenter + +obj-$(VDSO32-y) += vdso32-setup.o vobjs := $(foreach F,$(vobj64s),$(obj)/$F) $(obj)/vdso.o: $(obj)/vdso.so -targets += vdso.so vdso.so.dbg vdso.lds $(vobjs-y) +targets += vdso.lds $(vobjs-y) + +# Build the vDSO image C files and link them in. +vdso_img_objs := $(vdso_img-y:%=vdso-image-%.o) +vdso_img_cfiles := $(vdso_img-y:%=vdso-image-%.c) +vdso_img_sodbg := $(vdso_img-y:%=vdso%.so.dbg) +obj-y += $(vdso_img_objs) +targets += $(vdso_img_cfiles) +targets += $(vdso_img_sodbg) +.SECONDARY: $(vdso_img-y:%=$(obj)/vdso-image-%.c) export CPPFLAGS_vdso.lds += -P -C @@ -41,14 +56,18 @@ VDSO_LDFLAGS_vdso.lds = -m64 -Wl,-soname=linux-vdso.so.1 \ -Wl,-z,max-page-size=4096 -Wl,-z,common-page-size=4096 \ $(DISABLE_LTO) -$(obj)/vdso.o: $(src)/vdso.S $(obj)/vdso.so - -$(obj)/vdso.so.dbg: $(src)/vdso.lds $(vobjs) FORCE +$(obj)/vdso64.so.dbg: $(src)/vdso.lds $(vobjs) FORCE $(call if_changed,vdso) -$(obj)/%.so: OBJCOPYFLAGS := -S -$(obj)/%.so: $(obj)/%.so.dbg FORCE - $(call if_changed,objcopy) +hostprogs-y += vdso2c + +quiet_cmd_vdso2c = VDSO2C $@ +define cmd_vdso2c + $(obj)/vdso2c $< $@ +endef + +$(obj)/vdso-image-%.c: $(obj)/vdso%.so.dbg $(obj)/vdso2c FORCE + $(call if_changed,vdso2c) # # Don't omit frame pointers for ease of userspace debugging, but do @@ -68,22 +87,6 @@ CFLAGS_REMOVE_vclock_gettime.o = -pg CFLAGS_REMOVE_vgetcpu.o = -pg CFLAGS_REMOVE_vvar.o = -pg -targets += vdso-syms.lds -obj-$(VDSO64-y) += vdso-syms.lds - -# -# Match symbols in the DSO that look like VDSO*; produce a file of constants. -# -sed-vdsosym := -e 's/^00*/0/' \ - -e 's/^\([0-9a-fA-F]*\) . \(VDSO[a-zA-Z0-9_]*\)$$/\2 = 0x\1;/p' -quiet_cmd_vdsosym = VDSOSYM $@ -define cmd_vdsosym - $(NM) $< | LC_ALL=C sed -n $(sed-vdsosym) | LC_ALL=C sort > $@ -endef - -$(obj)/%-syms.lds: $(obj)/%.so.dbg FORCE - $(call if_changed,vdsosym) - # # X32 processes use x32 vDSO to access 64bit kernel data. # @@ -94,9 +97,6 @@ $(obj)/%-syms.lds: $(obj)/%.so.dbg FORCE # so that it can reach 64bit address space with 64bit pointers. # -targets += vdsox32-syms.lds -obj-$(VDSOX32-y) += vdsox32-syms.lds - CPPFLAGS_vdsox32.lds = $(CPPFLAGS_vdso.lds) VDSO_LDFLAGS_vdsox32.lds = -Wl,-m,elf32_x86_64 \ -Wl,-soname=linux-vdso.so.1 \ @@ -113,9 +113,7 @@ quiet_cmd_x32 = X32 $@ $(obj)/%-x32.o: $(obj)/%.o FORCE $(call if_changed,x32) -targets += vdsox32.so vdsox32.so.dbg vdsox32.lds $(vobjx32s-y) - -$(obj)/vdsox32.o: $(src)/vdsox32.S $(obj)/vdsox32.so +targets += vdsox32.lds $(vobjx32s-y) $(obj)/vdsox32.so.dbg: $(src)/vdsox32.lds $(vobjx32s) FORCE $(call if_changed,vdso) @@ -123,7 +121,6 @@ $(obj)/vdsox32.so.dbg: $(src)/vdsox32.lds $(vobjx32s) FORCE # # Build multiple 32-bit vDSO images to choose from at boot time. # -obj-$(VDSO32-y) += vdso32-syms.lds vdso32.so-$(VDSO32-y) += int80 vdso32.so-$(CONFIG_COMPAT) += syscall vdso32.so-$(VDSO32-y) += sysenter @@ -138,10 +135,8 @@ VDSO_LDFLAGS_vdso32.lds = -m32 -Wl,-m,elf_i386 -Wl,-soname=linux-gate.so.1 override obj-dirs = $(dir $(obj)) $(obj)/vdso32/ targets += vdso32/vdso32.lds -targets += $(vdso32-images) $(vdso32-images:=.dbg) targets += vdso32/note.o vdso32/vclock_gettime.o $(vdso32.so-y:%=vdso32/%.o) - -extra-y += $(vdso32-images) +targets += vdso32/vclock_gettime.o $(obj)/vdso32.o: $(vdso32-images:%=$(obj)/%) @@ -166,27 +161,6 @@ $(vdso32-images:%=$(obj)/%.dbg): $(obj)/vdso32-%.so.dbg: FORCE \ $(obj)/vdso32/%.o $(call if_changed,vdso) -# Make vdso32-*-syms.lds from each image, and then make sure they match. -# The only difference should be that some do not define VDSO32_SYSENTER_RETURN. - -targets += vdso32-syms.lds $(vdso32.so-y:%=vdso32-%-syms.lds) - -quiet_cmd_vdso32sym = VDSOSYM $@ -define cmd_vdso32sym - if LC_ALL=C sort -u $(filter-out FORCE,$^) > $(@D)/.tmp_$(@F) && \ - $(foreach H,$(filter-out FORCE,$^),\ - if grep -q VDSO32_SYSENTER_RETURN $H; \ - then diff -u $(@D)/.tmp_$(@F) $H; \ - else sed /VDSO32_SYSENTER_RETURN/d $(@D)/.tmp_$(@F) | \ - diff -u - $H; fi &&) : ;\ - then mv -f $(@D)/.tmp_$(@F) $@; \ - else rm -f $(@D)/.tmp_$(@F); exit 1; \ - fi -endef - -$(obj)/vdso32-syms.lds: $(vdso32.so-y:%=$(obj)/vdso32-%-syms.lds) FORCE - $(call if_changed,vdso32sym) - # # The DSO images are built using a special linker script. # @@ -197,7 +171,7 @@ quiet_cmd_vdso = VDSO $@ sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@' VDSO_LDFLAGS = -fPIC -shared $(call cc-ldoption, -Wl$(comma)--hash-style=sysv) \ - $(LTO_CFLAGS) + -Wl,-Bsymbolic $(LTO_CFLAGS) GCOV_PROFILE := n # diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c index 16d686171e9a..091554c20bc9 100644 --- a/arch/x86/vdso/vclock_gettime.c +++ b/arch/x86/vdso/vclock_gettime.c @@ -154,7 +154,7 @@ notrace static long vdso_fallback_gettime(long clock, struct timespec *ts) asm( "mov %%ebx, %%edx \n" "mov %2, %%ebx \n" - "call VDSO32_vsyscall \n" + "call __kernel_vsyscall \n" "mov %%edx, %%ebx \n" : "=a" (ret) : "0" (__NR_clock_gettime), "g" (clock), "c" (ts) @@ -169,7 +169,7 @@ notrace static long vdso_fallback_gtod(struct timeval *tv, struct timezone *tz) asm( "mov %%ebx, %%edx \n" "mov %2, %%ebx \n" - "call VDSO32_vsyscall \n" + "call __kernel_vsyscall \n" "mov %%edx, %%ebx \n" : "=a" (ret) : "0" (__NR_gettimeofday), "g" (tv), "c" (tz) diff --git a/arch/x86/vdso/vdso.S b/arch/x86/vdso/vdso.S deleted file mode 100644 index be3f23b09af5..000000000000 --- a/arch/x86/vdso/vdso.S +++ /dev/null @@ -1,3 +0,0 @@ -#include - -DEFINE_VDSO_IMAGE(vdso, "arch/x86/vdso/vdso.so") diff --git a/arch/x86/vdso/vdso2c.c b/arch/x86/vdso/vdso2c.c new file mode 100644 index 000000000000..976e8e4ced92 --- /dev/null +++ b/arch/x86/vdso/vdso2c.c @@ -0,0 +1,142 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +/* Symbols that we need in vdso2c. */ +char const * const required_syms[] = { + "VDSO32_NOTE_MASK", + "VDSO32_SYSENTER_RETURN", + "__kernel_vsyscall", + "__kernel_sigreturn", + "__kernel_rt_sigreturn", +}; + +__attribute__((format(printf, 1, 2))) __attribute__((noreturn)) +static void fail(const char *format, ...) +{ + va_list ap; + va_start(ap, format); + fprintf(stderr, "Error: "); + vfprintf(stderr, format, ap); + exit(1); + va_end(ap); +} + +#define NSYMS (sizeof(required_syms) / sizeof(required_syms[0])) + +#define BITS 64 +#define GOFUNC go64 +#define Elf_Ehdr Elf64_Ehdr +#define Elf_Shdr Elf64_Shdr +#define Elf_Phdr Elf64_Phdr +#define Elf_Sym Elf64_Sym +#define Elf_Dyn Elf64_Dyn +#include "vdso2c.h" +#undef BITS +#undef GOFUNC +#undef Elf_Ehdr +#undef Elf_Shdr +#undef Elf_Phdr +#undef Elf_Sym +#undef Elf_Dyn + +#define BITS 32 +#define GOFUNC go32 +#define Elf_Ehdr Elf32_Ehdr +#define Elf_Shdr Elf32_Shdr +#define Elf_Phdr Elf32_Phdr +#define Elf_Sym Elf32_Sym +#define Elf_Dyn Elf32_Dyn +#include "vdso2c.h" +#undef BITS +#undef GOFUNC +#undef Elf_Ehdr +#undef Elf_Shdr +#undef Elf_Phdr +#undef Elf_Sym +#undef Elf_Dyn + +static int go(void *addr, size_t len, FILE *outfile, const char *name) +{ + Elf64_Ehdr *hdr = (Elf64_Ehdr *)addr; + + if (hdr->e_ident[EI_CLASS] == ELFCLASS64) { + return go64(addr, len, outfile, name); + } else if (hdr->e_ident[EI_CLASS] == ELFCLASS32) { + return go32(addr, len, outfile, name); + } else { + fprintf(stderr, "Error: unknown ELF class\n"); + return 1; + } +} + +int main(int argc, char **argv) +{ + int fd; + off_t len; + void *addr; + FILE *outfile; + int ret; + char *name, *tmp; + int namelen; + + if (argc != 3) { + printf("Usage: vdso2c INPUT OUTPUT\n"); + return 1; + } + + /* + * Figure out the struct name. If we're writing to a .so file, + * generate raw output insted. + */ + name = strdup(argv[2]); + namelen = strlen(name); + if (namelen >= 3 && !strcmp(name + namelen - 3, ".so")) { + name = NULL; + } else { + tmp = strrchr(name, '/'); + if (tmp) + name = tmp + 1; + tmp = strchr(name, '.'); + if (tmp) + *tmp = '\0'; + for (tmp = name; *tmp; tmp++) + if (*tmp == '-') + *tmp = '_'; + } + + fd = open(argv[1], O_RDONLY); + if (fd == -1) + err(1, "%s", argv[1]); + + len = lseek(fd, 0, SEEK_END); + if (len == (off_t)-1) + err(1, "lseek"); + + addr = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0); + if (addr == MAP_FAILED) + err(1, "mmap"); + + outfile = fopen(argv[2], "w"); + if (!outfile) + err(1, "%s", argv[2]); + + ret = go(addr, (size_t)len, outfile, name); + + munmap(addr, len); + fclose(outfile); + + return ret; +} diff --git a/arch/x86/vdso/vdso2c.h b/arch/x86/vdso/vdso2c.h new file mode 100644 index 000000000000..9276e5207620 --- /dev/null +++ b/arch/x86/vdso/vdso2c.h @@ -0,0 +1,137 @@ +/* + * This file is included twice from vdso2c.c. It generates code for 32-bit + * and 64-bit vDSOs. We need both for 64-bit builds, since 32-bit vDSOs + * are built for 32-bit userspace. + */ + +static int GOFUNC(void *addr, size_t len, FILE *outfile, const char *name) +{ + int found_load = 0; + unsigned long load_size = -1; /* Work around bogus warning */ + unsigned long data_size; + Elf_Ehdr *hdr = (Elf_Ehdr *)addr; + int i; + unsigned long j; + Elf_Shdr *symtab_hdr = NULL, *strtab_hdr, *secstrings_hdr, + *alt_sec = NULL; + Elf_Dyn *dyn = 0, *dyn_end = 0; + const char *secstrings; + uint64_t syms[NSYMS] = {}; + + Elf_Phdr *pt = (Elf_Phdr *)(addr + hdr->e_phoff); + + /* Walk the segment table. */ + for (i = 0; i < hdr->e_phnum; i++) { + if (pt[i].p_type == PT_LOAD) { + if (found_load) + fail("multiple PT_LOAD segs\n"); + + if (pt[i].p_offset != 0 || pt[i].p_vaddr != 0) + fail("PT_LOAD in wrong place\n"); + + if (pt[i].p_memsz != pt[i].p_filesz) + fail("cannot handle memsz != filesz\n"); + + load_size = pt[i].p_memsz; + found_load = 1; + } else if (pt[i].p_type == PT_DYNAMIC) { + dyn = addr + pt[i].p_offset; + dyn_end = addr + pt[i].p_offset + pt[i].p_memsz; + } + } + if (!found_load) + fail("no PT_LOAD seg\n"); + data_size = (load_size + 4095) / 4096 * 4096; + + /* Walk the dynamic table */ + for (i = 0; dyn + i < dyn_end && dyn[i].d_tag != DT_NULL; i++) { + if (dyn[i].d_tag == DT_REL || dyn[i].d_tag == DT_RELSZ || + dyn[i].d_tag == DT_RELENT || dyn[i].d_tag == DT_TEXTREL) + fail("vdso image contains dynamic relocations\n"); + } + + /* Walk the section table */ + secstrings_hdr = addr + hdr->e_shoff + hdr->e_shentsize*hdr->e_shstrndx; + secstrings = addr + secstrings_hdr->sh_offset; + for (i = 0; i < hdr->e_shnum; i++) { + Elf_Shdr *sh = addr + hdr->e_shoff + hdr->e_shentsize * i; + if (sh->sh_type == SHT_SYMTAB) + symtab_hdr = sh; + + if (!strcmp(secstrings + sh->sh_name, ".altinstructions")) + alt_sec = sh; + } + + if (!symtab_hdr) { + fail("no symbol table\n"); + return 1; + } + + strtab_hdr = addr + hdr->e_shoff + + hdr->e_shentsize * symtab_hdr->sh_link; + + /* Walk the symbol table */ + for (i = 0; i < symtab_hdr->sh_size / symtab_hdr->sh_entsize; i++) { + int k; + Elf_Sym *sym = addr + symtab_hdr->sh_offset + + symtab_hdr->sh_entsize * i; + const char *name = addr + strtab_hdr->sh_offset + sym->st_name; + for (k = 0; k < NSYMS; k++) { + if (!strcmp(name, required_syms[k])) { + if (syms[k]) { + fail("duplicate symbol %s\n", + required_syms[k]); + } + syms[k] = sym->st_value; + } + } + } + + /* Remove sections. */ + hdr->e_shoff = 0; + hdr->e_shentsize = 0; + hdr->e_shnum = 0; + hdr->e_shstrndx = SHN_UNDEF; + + if (!name) { + fwrite(addr, load_size, 1, outfile); + return 0; + } + + fprintf(outfile, "/* AUTOMATICALLY GENERATED -- DO NOT EDIT */\n\n"); + fprintf(outfile, "#include \n"); + fprintf(outfile, "#include \n"); + fprintf(outfile, "#include \n"); + fprintf(outfile, "\n"); + fprintf(outfile, + "static unsigned char raw_data[%lu] __page_aligned_data = {", + data_size); + for (j = 0; j < load_size; j++) { + if (j % 10 == 0) + fprintf(outfile, "\n\t"); + fprintf(outfile, "0x%02X, ", (int)((unsigned char *)addr)[j]); + } + fprintf(outfile, "\n};\n\n"); + + fprintf(outfile, "static struct page *pages[%lu];\n\n", + data_size / 4096); + + fprintf(outfile, "const struct vdso_image %s = {\n", name); + fprintf(outfile, "\t.data = raw_data,\n"); + fprintf(outfile, "\t.size = %lu,\n", data_size); + fprintf(outfile, "\t.pages = pages,\n"); + if (alt_sec) { + fprintf(outfile, "\t.alt = %lu,\n", + (unsigned long)alt_sec->sh_offset); + fprintf(outfile, "\t.alt_len = %lu,\n", + (unsigned long)alt_sec->sh_size); + } + for (i = 0; i < NSYMS; i++) { + if (syms[i]) + fprintf(outfile, "\t.sym_%s = 0x%" PRIx64 ",\n", + required_syms[i], syms[i]); + } + fprintf(outfile, "};\n"); + + return 0; +} diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c index 9c78d5b24874..d41460118a28 100644 --- a/arch/x86/vdso/vdso32-setup.c +++ b/arch/x86/vdso/vdso32-setup.c @@ -29,6 +29,7 @@ #include #include #include +#include #ifdef CONFIG_COMPAT_VDSO #define VDSO_DEFAULT 0 @@ -67,9 +68,6 @@ __setup("vdso32=", vdso32_setup); __setup_param("vdso=", vdso_setup, vdso32_setup, 0); #endif -static struct page **vdso32_pages; -static unsigned vdso32_size; - #ifdef CONFIG_X86_64 #define vdso32_sysenter() (boot_cpu_has(X86_FEATURE_SYSENTER32)) @@ -82,34 +80,23 @@ static unsigned vdso32_size; #endif /* CONFIG_X86_64 */ +#if defined(CONFIG_X86_32) || defined(CONFIG_COMPAT) +const struct vdso_image *selected_vdso32; +#endif + int __init sysenter_setup(void) { - char *vdso32_start, *vdso32_end; - int npages, i; - #ifdef CONFIG_COMPAT - if (vdso32_syscall()) { - vdso32_start = vdso32_syscall_start; - vdso32_end = vdso32_syscall_end; - vdso32_pages = vdso32_syscall_pages; - } else + if (vdso32_syscall()) + selected_vdso32 = &vdso_image_32_syscall; + else #endif - if (vdso32_sysenter()) { - vdso32_start = vdso32_sysenter_start; - vdso32_end = vdso32_sysenter_end; - vdso32_pages = vdso32_sysenter_pages; - } else { - vdso32_start = vdso32_int80_start; - vdso32_end = vdso32_int80_end; - vdso32_pages = vdso32_int80_pages; - } - - npages = ((vdso32_end - vdso32_start) + PAGE_SIZE - 1) / PAGE_SIZE; - vdso32_size = npages << PAGE_SHIFT; - for (i = 0; i < npages; i++) - vdso32_pages[i] = virt_to_page(vdso32_start + i*PAGE_SIZE); + if (vdso32_sysenter()) + selected_vdso32 = &vdso_image_32_sysenter; + else + selected_vdso32 = &vdso_image_32_int80; - patch_vdso32(vdso32_start, vdso32_size); + init_vdso_image(selected_vdso32); return 0; } @@ -121,6 +108,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) unsigned long addr; int ret = 0; struct vm_area_struct *vma; + unsigned long vdso32_size = selected_vdso32->size; #ifdef CONFIG_X86_X32_ABI if (test_thread_flag(TIF_X32)) @@ -140,7 +128,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) addr += VDSO_OFFSET(VDSO_PREV_PAGES); - current->mm->context.vdso = (void *)addr; + current->mm->context.vdso = (void __user *)addr; /* * MAYWRITE to allow gdb to COW and set breakpoints @@ -150,7 +138,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) vdso32_size, VM_READ|VM_EXEC| VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, - vdso32_pages); + selected_vdso32->pages); if (ret) goto up_fail; @@ -188,8 +176,10 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) } #endif - current_thread_info()->sysenter_return = - VDSO32_SYMBOL(addr, SYSENTER_RETURN); + if (selected_vdso32->sym_VDSO32_SYSENTER_RETURN) + current_thread_info()->sysenter_return = + current->mm->context.vdso + + selected_vdso32->sym_VDSO32_SYSENTER_RETURN; up_fail: if (ret) diff --git a/arch/x86/vdso/vdso32.S b/arch/x86/vdso/vdso32.S deleted file mode 100644 index 018bcd9f97b4..000000000000 --- a/arch/x86/vdso/vdso32.S +++ /dev/null @@ -1,9 +0,0 @@ -#include - -DEFINE_VDSO_IMAGE(vdso32_int80, "arch/x86/vdso/vdso32-int80.so") - -#ifdef CONFIG_COMPAT -DEFINE_VDSO_IMAGE(vdso32_syscall, "arch/x86/vdso/vdso32-syscall.so") -#endif - -DEFINE_VDSO_IMAGE(vdso32_sysenter, "arch/x86/vdso/vdso32-sysenter.so") diff --git a/arch/x86/vdso/vdso32/vdso32.lds.S b/arch/x86/vdso/vdso32/vdso32.lds.S index aadb8b9994cd..f072095d6427 100644 --- a/arch/x86/vdso/vdso32/vdso32.lds.S +++ b/arch/x86/vdso/vdso32/vdso32.lds.S @@ -38,13 +38,3 @@ VERSION local: *; }; } - -/* - * Symbols we define here called VDSO* get their values into vdso32-syms.h. - */ -VDSO32_vsyscall = __kernel_vsyscall; -VDSO32_sigreturn = __kernel_sigreturn; -VDSO32_rt_sigreturn = __kernel_rt_sigreturn; -VDSO32_clock_gettime = clock_gettime; -VDSO32_gettimeofday = gettimeofday; -VDSO32_time = time; diff --git a/arch/x86/vdso/vdsox32.S b/arch/x86/vdso/vdsox32.S deleted file mode 100644 index f4aa34e7f370..000000000000 --- a/arch/x86/vdso/vdsox32.S +++ /dev/null @@ -1,3 +0,0 @@ -#include - -DEFINE_VDSO_IMAGE(vdsox32, "arch/x86/vdso/vdsox32.so") diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c index 8b790398ed1d..cf217626fb47 100644 --- a/arch/x86/vdso/vma.c +++ b/arch/x86/vdso/vma.c @@ -19,99 +19,31 @@ #if defined(CONFIG_X86_64) unsigned int __read_mostly vdso64_enabled = 1; -DECLARE_VDSO_IMAGE(vdso); extern unsigned short vdso_sync_cpuid; -static unsigned vdso_size; - -#ifdef CONFIG_X86_X32_ABI -DECLARE_VDSO_IMAGE(vdsox32); -static unsigned vdsox32_size; -#endif #endif -#if defined(CONFIG_X86_32) || defined(CONFIG_X86_X32_ABI) || \ - defined(CONFIG_COMPAT) -void __init patch_vdso32(void *vdso, size_t len) +void __init init_vdso_image(const struct vdso_image *image) { - Elf32_Ehdr *hdr = vdso; - Elf32_Shdr *sechdrs, *alt_sec = 0; - char *secstrings; - void *alt_data; int i; + int npages = (image->size) / PAGE_SIZE; - BUG_ON(len < sizeof(Elf32_Ehdr)); - BUG_ON(memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0); - - sechdrs = (void *)hdr + hdr->e_shoff; - secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; - - for (i = 1; i < hdr->e_shnum; i++) { - Elf32_Shdr *shdr = &sechdrs[i]; - if (!strcmp(secstrings + shdr->sh_name, ".altinstructions")) { - alt_sec = shdr; - goto found; - } - } - - /* If we get here, it's probably a bug. */ - pr_warning("patch_vdso32: .altinstructions not found\n"); - return; /* nothing to patch */ + BUG_ON(image->size % PAGE_SIZE != 0); + for (i = 0; i < npages; i++) + image->pages[i] = virt_to_page(image->data + i*PAGE_SIZE); -found: - alt_data = (void *)hdr + alt_sec->sh_offset; - apply_alternatives(alt_data, alt_data + alt_sec->sh_size); + apply_alternatives((struct alt_instr *)(image->data + image->alt), + (struct alt_instr *)(image->data + image->alt + + image->alt_len)); } -#endif - -#if defined(CONFIG_X86_64) -static void __init patch_vdso64(void *vdso, size_t len) -{ - Elf64_Ehdr *hdr = vdso; - Elf64_Shdr *sechdrs, *alt_sec = 0; - char *secstrings; - void *alt_data; - int i; - BUG_ON(len < sizeof(Elf64_Ehdr)); - BUG_ON(memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0); - - sechdrs = (void *)hdr + hdr->e_shoff; - secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; - - for (i = 1; i < hdr->e_shnum; i++) { - Elf64_Shdr *shdr = &sechdrs[i]; - if (!strcmp(secstrings + shdr->sh_name, ".altinstructions")) { - alt_sec = shdr; - goto found; - } - } - - /* If we get here, it's probably a bug. */ - pr_warning("patch_vdso64: .altinstructions not found\n"); - return; /* nothing to patch */ - -found: - alt_data = (void *)hdr + alt_sec->sh_offset; - apply_alternatives(alt_data, alt_data + alt_sec->sh_size); -} +#if defined(CONFIG_X86_64) static int __init init_vdso(void) { - int npages = (vdso_end - vdso_start + PAGE_SIZE - 1) / PAGE_SIZE; - int i; - - patch_vdso64(vdso_start, vdso_end - vdso_start); - - vdso_size = npages << PAGE_SHIFT; - for (i = 0; i < npages; i++) - vdso_pages[i] = virt_to_page(vdso_start + i*PAGE_SIZE); + init_vdso_image(&vdso_image_64); #ifdef CONFIG_X86_X32_ABI - patch_vdso32(vdsox32_start, vdsox32_end - vdsox32_start); - npages = (vdsox32_end - vdsox32_start + PAGE_SIZE - 1) / PAGE_SIZE; - vdsox32_size = npages << PAGE_SHIFT; - for (i = 0; i < npages; i++) - vdsox32_pages[i] = virt_to_page(vdsox32_start + i*PAGE_SIZE); + init_vdso_image(&vdso_image_x32); #endif return 0; @@ -171,7 +103,7 @@ static int setup_additional_pages(struct linux_binprm *bprm, goto up_fail; } - current->mm->context.vdso = (void *)addr; + current->mm->context.vdso = (void __user *)addr; ret = install_special_mapping(mm, addr, size, VM_READ|VM_EXEC| @@ -189,15 +121,15 @@ up_fail: int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) { - return setup_additional_pages(bprm, uses_interp, vdso_pages, - vdso_size); + return setup_additional_pages(bprm, uses_interp, vdso_image_64.pages, + vdso_image_64.size); } #ifdef CONFIG_X86_X32_ABI int x32_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) { - return setup_additional_pages(bprm, uses_interp, vdsox32_pages, - vdsox32_size); + return setup_additional_pages(bprm, uses_interp, vdso_image_x32.pages, + vdso_image_x32.size); } #endif diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c index 0982233b9b84..7225a9557ee2 100644 --- a/arch/x86/xen/setup.c +++ b/arch/x86/xen/setup.c @@ -516,10 +516,17 @@ char * __init xen_memory_setup(void) static void __init fiddle_vdso(void) { #ifdef CONFIG_X86_32 + /* + * This could be called before selected_vdso32 is initialized, so + * just fiddle with both possible images. vdso_image_32_syscall + * can't be selected, since it only exists on 64-bit systems. + */ u32 *mask; - mask = VDSO32_SYMBOL(&vdso32_int80_start, NOTE_MASK); + mask = vdso_image_32_int80.data + + vdso_image_32_int80.sym_VDSO32_NOTE_MASK; *mask |= 1 << VDSO_NOTE_NONEGSEG_BIT; - mask = VDSO32_SYMBOL(&vdso32_sysenter_start, NOTE_MASK); + mask = vdso_image_32_sysenter.data + + vdso_image_32_sysenter.sym_VDSO32_NOTE_MASK; *mask |= 1 << VDSO_NOTE_NONEGSEG_BIT; #endif } -- cgit v1.2.3 From 18d0a6fd227177fd243993179c90e454d0638b06 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:35 -0700 Subject: x86, vdso: Move the 32-bit vdso special pages after the text This unifies the vdso mapping code and teaches it how to map special pages at addresses corresponding to symbols in the vdso image. The new code is used for all vdso variants, but so far only the 32-bit variants use the new vvar page position. Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/b6d7858ad7b5ac3fd3c29cab6d6d769bc45d195e.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/elf.h | 8 +-- arch/x86/include/asm/vdso.h | 4 ++ arch/x86/include/asm/vdso32.h | 11 ---- arch/x86/vdso/vdso-layout.lds.S | 42 ++++++++----- arch/x86/vdso/vdso2c.c | 14 +++++ arch/x86/vdso/vdso2c.h | 17 ++++++ arch/x86/vdso/vdso32-setup.c | 115 +----------------------------------- arch/x86/vdso/vma.c | 128 +++++++++++++++++++++++++++++++++------- 8 files changed, 173 insertions(+), 166 deletions(-) delete mode 100644 arch/x86/include/asm/vdso32.h (limited to 'arch') diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h index 65b21bcbe9f7..1a055c81d864 100644 --- a/arch/x86/include/asm/elf.h +++ b/arch/x86/include/asm/elf.h @@ -333,11 +333,9 @@ struct linux_binprm; #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 extern int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp); -extern int x32_setup_additional_pages(struct linux_binprm *bprm, - int uses_interp); - -extern int syscall32_setup_pages(struct linux_binprm *, int exstack); -#define compat_arch_setup_additional_pages syscall32_setup_pages +extern int compat_arch_setup_additional_pages(struct linux_binprm *bprm, + int uses_interp); +#define compat_arch_setup_additional_pages compat_arch_setup_additional_pages extern unsigned long arch_randomize_brk(struct mm_struct *mm); #define arch_randomize_brk arch_randomize_brk diff --git a/arch/x86/include/asm/vdso.h b/arch/x86/include/asm/vdso.h index 389fe2ca27c2..d0a2c909c72d 100644 --- a/arch/x86/include/asm/vdso.h +++ b/arch/x86/include/asm/vdso.h @@ -14,6 +14,10 @@ struct vdso_image { unsigned long alt, alt_len; + unsigned long sym_end_mapping; /* Total size of the mapping */ + + unsigned long sym_vvar_page; + unsigned long sym_hpet_page; unsigned long sym_VDSO32_NOTE_MASK; unsigned long sym___kernel_sigreturn; unsigned long sym___kernel_rt_sigreturn; diff --git a/arch/x86/include/asm/vdso32.h b/arch/x86/include/asm/vdso32.h deleted file mode 100644 index 7efb7018406e..000000000000 --- a/arch/x86/include/asm/vdso32.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _ASM_X86_VDSO32_H -#define _ASM_X86_VDSO32_H - -#define VDSO_BASE_PAGE 0 -#define VDSO_VVAR_PAGE 1 -#define VDSO_HPET_PAGE 2 -#define VDSO_PAGES 3 -#define VDSO_PREV_PAGES 2 -#define VDSO_OFFSET(x) ((x) * PAGE_SIZE) - -#endif diff --git a/arch/x86/vdso/vdso-layout.lds.S b/arch/x86/vdso/vdso-layout.lds.S index 9df017ab2285..e177c08bb4bc 100644 --- a/arch/x86/vdso/vdso-layout.lds.S +++ b/arch/x86/vdso/vdso-layout.lds.S @@ -1,3 +1,5 @@ +#include + /* * Linker script for vDSO. This is an ELF shared object prelinked to * its virtual address, and with only one read-only segment. @@ -6,20 +8,6 @@ SECTIONS { -#ifdef BUILD_VDSO32 -#include - - hpet_page = . - VDSO_OFFSET(VDSO_HPET_PAGE); - - vvar = . - VDSO_OFFSET(VDSO_VVAR_PAGE); - - /* Place all vvars at the offsets in asm/vvar.h. */ -#define EMIT_VVAR(name, offset) vvar_ ## name = vvar + offset; -#define __VVAR_KERNEL_LDS -#include -#undef __VVAR_KERNEL_LDS -#undef EMIT_VVAR -#endif . = SIZEOF_HEADERS; .hash : { *(.hash) } :text @@ -59,11 +47,33 @@ SECTIONS .text : { *(.text*) } :text =0x90909090, +#ifdef BUILD_VDSO32 /* - * The comma above works around a bug in gold: - * https://sourceware.org/bugzilla/show_bug.cgi?id=16804 + * The remainder of the vDSO consists of special pages that are + * shared between the kernel and userspace. It needs to be at the + * end so that it doesn't overlap the mapping of the actual + * vDSO image. */ + . = ALIGN(PAGE_SIZE); + vvar_page = .; + + /* Place all vvars at the offsets in asm/vvar.h. */ +#define EMIT_VVAR(name, offset) vvar_ ## name = vvar_page + offset; +#define __VVAR_KERNEL_LDS +#include +#undef __VVAR_KERNEL_LDS +#undef EMIT_VVAR + + . = vvar_page + PAGE_SIZE; + + hpet_page = .; + . = . + PAGE_SIZE; +#endif + + . = ALIGN(PAGE_SIZE); + end_mapping = .; + /DISCARD/ : { *(.discard) *(.discard.*) diff --git a/arch/x86/vdso/vdso2c.c b/arch/x86/vdso/vdso2c.c index 976e8e4ced92..81edd1ec9df8 100644 --- a/arch/x86/vdso/vdso2c.c +++ b/arch/x86/vdso/vdso2c.c @@ -15,7 +15,21 @@ #include /* Symbols that we need in vdso2c. */ +enum { + sym_vvar_page, + sym_hpet_page, + sym_end_mapping, +}; + +const int special_pages[] = { + sym_vvar_page, + sym_hpet_page, +}; + char const * const required_syms[] = { + [sym_vvar_page] = "vvar_page", + [sym_hpet_page] = "hpet_page", + [sym_end_mapping] = "end_mapping", "VDSO32_NOTE_MASK", "VDSO32_SYSENTER_RETURN", "__kernel_vsyscall", diff --git a/arch/x86/vdso/vdso2c.h b/arch/x86/vdso/vdso2c.h index 9276e5207620..ed2e894e89ab 100644 --- a/arch/x86/vdso/vdso2c.h +++ b/arch/x86/vdso/vdso2c.h @@ -87,6 +87,23 @@ static int GOFUNC(void *addr, size_t len, FILE *outfile, const char *name) } } + /* Validate mapping addresses. */ + for (i = 0; i < sizeof(special_pages) / sizeof(special_pages[0]); i++) { + if (!syms[i]) + continue; /* The mapping isn't used; ignore it. */ + + if (syms[i] % 4096) + fail("%s must be a multiple of 4096\n", + required_syms[i]); + if (syms[i] < data_size) + fail("%s must be after the text mapping\n", + required_syms[i]); + if (syms[sym_end_mapping] < syms[i] + 4096) + fail("%s overruns end_mapping\n", required_syms[i]); + } + if (syms[sym_end_mapping] % 4096) + fail("end_mapping must be a multiple of 4096\n"); + /* Remove sections. */ hdr->e_shoff = 0; hdr->e_shentsize = 0; diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c index d41460118a28..c3ed708e50f4 100644 --- a/arch/x86/vdso/vdso32-setup.c +++ b/arch/x86/vdso/vdso32-setup.c @@ -8,28 +8,12 @@ #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include -#include -#include -#include -#include -#include +#include #include -#include -#include -#include -#include -#include #ifdef CONFIG_COMPAT_VDSO #define VDSO_DEFAULT 0 @@ -37,10 +21,6 @@ #define VDSO_DEFAULT 1 #endif -#ifdef CONFIG_X86_64 -#define arch_setup_additional_pages syscall32_setup_pages -#endif - /* * Should the kernel map a VDSO page into processes and pass its * address down to glibc upon exec()? @@ -101,95 +81,6 @@ int __init sysenter_setup(void) return 0; } -/* Setup a VMA at program startup for the vsyscall page */ -int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) -{ - struct mm_struct *mm = current->mm; - unsigned long addr; - int ret = 0; - struct vm_area_struct *vma; - unsigned long vdso32_size = selected_vdso32->size; - -#ifdef CONFIG_X86_X32_ABI - if (test_thread_flag(TIF_X32)) - return x32_setup_additional_pages(bprm, uses_interp); -#endif - - if (vdso32_enabled != 1) /* Other values all mean "disabled" */ - return 0; - - down_write(&mm->mmap_sem); - - addr = get_unmapped_area(NULL, 0, vdso32_size + VDSO_OFFSET(VDSO_PREV_PAGES), 0, 0); - if (IS_ERR_VALUE(addr)) { - ret = addr; - goto up_fail; - } - - addr += VDSO_OFFSET(VDSO_PREV_PAGES); - - current->mm->context.vdso = (void __user *)addr; - - /* - * MAYWRITE to allow gdb to COW and set breakpoints - */ - ret = install_special_mapping(mm, - addr, - vdso32_size, - VM_READ|VM_EXEC| - VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, - selected_vdso32->pages); - - if (ret) - goto up_fail; - - vma = _install_special_mapping(mm, - addr - VDSO_OFFSET(VDSO_PREV_PAGES), - VDSO_OFFSET(VDSO_PREV_PAGES), - VM_READ, - NULL); - - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto up_fail; - } - - ret = remap_pfn_range(vma, - addr - VDSO_OFFSET(VDSO_VVAR_PAGE), - __pa_symbol(&__vvar_page) >> PAGE_SHIFT, - PAGE_SIZE, - PAGE_READONLY); - - if (ret) - goto up_fail; - -#ifdef CONFIG_HPET_TIMER - if (hpet_address) { - ret = io_remap_pfn_range(vma, - addr - VDSO_OFFSET(VDSO_HPET_PAGE), - hpet_address >> PAGE_SHIFT, - PAGE_SIZE, - pgprot_noncached(PAGE_READONLY)); - - if (ret) - goto up_fail; - } -#endif - - if (selected_vdso32->sym_VDSO32_SYSENTER_RETURN) - current_thread_info()->sysenter_return = - current->mm->context.vdso + - selected_vdso32->sym_VDSO32_SYSENTER_RETURN; - - up_fail: - if (ret) - current->mm->context.vdso = NULL; - - up_write(&mm->mmap_sem); - - return ret; -} - #ifdef CONFIG_X86_64 subsys_initcall(sysenter_setup); diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c index cf217626fb47..e915eaec4f96 100644 --- a/arch/x86/vdso/vma.c +++ b/arch/x86/vdso/vma.c @@ -15,6 +15,7 @@ #include #include #include +#include #if defined(CONFIG_X86_64) unsigned int __read_mostly vdso64_enabled = 1; @@ -36,7 +37,6 @@ void __init init_vdso_image(const struct vdso_image *image) image->alt_len)); } - #if defined(CONFIG_X86_64) static int __init init_vdso(void) { @@ -49,13 +49,16 @@ static int __init init_vdso(void) return 0; } subsys_initcall(init_vdso); +#endif struct linux_binprm; /* Put the vdso above the (randomized) stack with another randomized offset. This way there is no hole in the middle of address space. To save memory make sure it is still in the same PTE as the stack top. - This doesn't give that many random bits */ + This doesn't give that many random bits. + + Only used for the 64-bit and x32 vdsos. */ static unsigned long vdso_addr(unsigned long start, unsigned len) { unsigned long addr, end; @@ -81,23 +84,23 @@ static unsigned long vdso_addr(unsigned long start, unsigned len) return addr; } -/* Setup a VMA at program startup for the vsyscall page. - Not called for compat tasks */ -static int setup_additional_pages(struct linux_binprm *bprm, - int uses_interp, - struct page **pages, - unsigned size) +static int map_vdso(const struct vdso_image *image, bool calculate_addr) { struct mm_struct *mm = current->mm; + struct vm_area_struct *vma; unsigned long addr; - int ret; + int ret = 0; - if (!vdso64_enabled) - return 0; + if (calculate_addr) { + addr = vdso_addr(current->mm->start_stack, + image->sym_end_mapping); + } else { + addr = 0; + } down_write(&mm->mmap_sem); - addr = vdso_addr(mm->start_stack, size); - addr = get_unmapped_area(NULL, addr, size, 0, 0); + + addr = get_unmapped_area(NULL, addr, image->sym_end_mapping, 0, 0); if (IS_ERR_VALUE(addr)) { ret = addr; goto up_fail; @@ -105,34 +108,115 @@ static int setup_additional_pages(struct linux_binprm *bprm, current->mm->context.vdso = (void __user *)addr; - ret = install_special_mapping(mm, addr, size, + /* + * MAYWRITE to allow gdb to COW and set breakpoints + */ + ret = install_special_mapping(mm, + addr, + image->size, VM_READ|VM_EXEC| VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC, - pages); - if (ret) { - current->mm->context.vdso = NULL; + image->pages); + + if (ret) + goto up_fail; + + vma = _install_special_mapping(mm, + addr + image->size, + image->sym_end_mapping - image->size, + VM_READ, + NULL); + + if (IS_ERR(vma)) { + ret = PTR_ERR(vma); goto up_fail; } + if (image->sym_vvar_page) + ret = remap_pfn_range(vma, + addr + image->sym_vvar_page, + __pa_symbol(&__vvar_page) >> PAGE_SHIFT, + PAGE_SIZE, + PAGE_READONLY); + + if (ret) + goto up_fail; + +#ifdef CONFIG_HPET_TIMER + if (hpet_address && image->sym_hpet_page) { + ret = io_remap_pfn_range(vma, + addr + image->sym_hpet_page, + hpet_address >> PAGE_SHIFT, + PAGE_SIZE, + pgprot_noncached(PAGE_READONLY)); + + if (ret) + goto up_fail; + } +#endif + up_fail: + if (ret) + current->mm->context.vdso = NULL; + up_write(&mm->mmap_sem); return ret; } +#if defined(CONFIG_X86_32) || defined(CONFIG_COMPAT) +static int load_vdso32(void) +{ + int ret; + + if (vdso32_enabled != 1) /* Other values all mean "disabled" */ + return 0; + + ret = map_vdso(selected_vdso32, false); + if (ret) + return ret; + + if (selected_vdso32->sym_VDSO32_SYSENTER_RETURN) + current_thread_info()->sysenter_return = + current->mm->context.vdso + + selected_vdso32->sym_VDSO32_SYSENTER_RETURN; + + return 0; +} +#endif + +#ifdef CONFIG_X86_64 int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) { - return setup_additional_pages(bprm, uses_interp, vdso_image_64.pages, - vdso_image_64.size); + if (!vdso64_enabled) + return 0; + + return map_vdso(&vdso_image_64, true); } +#ifdef CONFIG_COMPAT +int compat_arch_setup_additional_pages(struct linux_binprm *bprm, + int uses_interp) +{ #ifdef CONFIG_X86_X32_ABI -int x32_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) + if (test_thread_flag(TIF_X32)) { + if (!vdso64_enabled) + return 0; + + return map_vdso(&vdso_image_x32, true); + } +#endif + + return load_vdso32(); +} +#endif +#else +int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) { - return setup_additional_pages(bprm, uses_interp, vdso_image_x32.pages, - vdso_image_x32.size); + return load_vdso32(); } #endif +#ifdef CONFIG_X86_64 static __init int vdso_setup(char *s) { vdso64_enabled = simple_strtoul(s, NULL, 0); -- cgit v1.2.3 From f40c330091c7aa9956ab66f97a3abc8a68b67240 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:36 -0700 Subject: x86, vdso: Move the vvar and hpet mappings next to the 64-bit vDSO This makes the 64-bit and x32 vdsos use the same mechanism as the 32-bit vdso. Most of the churn is deleting all the old fixmap code. Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/8af87023f57f6bb96ec8d17fce3f88018195b49b.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/include/asm/fixmap.h | 11 ++++------- arch/x86/include/asm/vvar.h | 20 +------------------- arch/x86/include/uapi/asm/vsyscall.h | 7 +------ arch/x86/kernel/cpu/common.c | 1 + arch/x86/kernel/hpet.c | 3 --- arch/x86/kernel/vsyscall_64.c | 15 ++++----------- arch/x86/mm/fault.c | 5 +++-- arch/x86/mm/init_64.c | 10 +++++----- arch/x86/vdso/vclock_gettime.c | 22 +++++----------------- arch/x86/vdso/vdso-layout.lds.S | 2 -- arch/x86/xen/mmu.c | 8 +++----- 11 files changed, 27 insertions(+), 77 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index 43f482a0db37..b0910f97a3ea 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h @@ -24,7 +24,7 @@ #include #include #else -#include +#include #endif /* @@ -41,7 +41,8 @@ extern unsigned long __FIXADDR_TOP; #define FIXADDR_TOP ((unsigned long)__FIXADDR_TOP) #else -#define FIXADDR_TOP (VSYSCALL_END-PAGE_SIZE) +#define FIXADDR_TOP (round_up(VSYSCALL_ADDR + PAGE_SIZE, 1<> PAGE_SHIFT) - 1, - VVAR_PAGE, - VSYSCALL_HPET, + VSYSCALL_PAGE = (FIXADDR_TOP - VSYSCALL_ADDR) >> PAGE_SHIFT, #ifdef CONFIG_PARAVIRT_CLOCK PVCLOCK_FIXMAP_BEGIN, PVCLOCK_FIXMAP_END = PVCLOCK_FIXMAP_BEGIN+PVCLOCK_VSYSCALL_NR_PAGES-1, diff --git a/arch/x86/include/asm/vvar.h b/arch/x86/include/asm/vvar.h index 081d909bc495..5d2b9ad2c6d2 100644 --- a/arch/x86/include/asm/vvar.h +++ b/arch/x86/include/asm/vvar.h @@ -29,31 +29,13 @@ #else -#ifdef BUILD_VDSO32 +extern char __vvar_page; #define DECLARE_VVAR(offset, type, name) \ extern type vvar_ ## name __attribute__((visibility("hidden"))); #define VVAR(name) (vvar_ ## name) -#else - -extern char __vvar_page; - -/* Base address of vvars. This is not ABI. */ -#ifdef CONFIG_X86_64 -#define VVAR_ADDRESS (-10*1024*1024 - 4096) -#else -#define VVAR_ADDRESS (&__vvar_page) -#endif - -#define DECLARE_VVAR(offset, type, name) \ - static type const * const vvaraddr_ ## name = \ - (void *)(VVAR_ADDRESS + (offset)); - -#define VVAR(name) (*vvaraddr_ ## name) -#endif - #define DEFINE_VVAR(type, name) \ type name \ __attribute__((section(".vvar_" #name), aligned(16))) __visible diff --git a/arch/x86/include/uapi/asm/vsyscall.h b/arch/x86/include/uapi/asm/vsyscall.h index 85dc1b3825ab..b97dd6e263d2 100644 --- a/arch/x86/include/uapi/asm/vsyscall.h +++ b/arch/x86/include/uapi/asm/vsyscall.h @@ -7,11 +7,6 @@ enum vsyscall_num { __NR_vgetcpu, }; -#define VSYSCALL_START (-10UL << 20) -#define VSYSCALL_SIZE 1024 -#define VSYSCALL_END (-2UL << 20) -#define VSYSCALL_MAPPED_PAGES 1 -#define VSYSCALL_ADDR(vsyscall_nr) (VSYSCALL_START+VSYSCALL_SIZE*(vsyscall_nr)) - +#define VSYSCALL_ADDR (-10UL << 20) #endif /* _UAPI_ASM_X86_VSYSCALL_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 7c65b4666c24..2cbbf88d8f2c 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 8d80ae011603..bbc15a0362d2 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -74,9 +74,6 @@ static inline void hpet_writel(unsigned int d, unsigned int a) static inline void hpet_set_mapping(void) { hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); -#ifdef CONFIG_X86_64 - __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE); -#endif } static inline void hpet_clear_mapping(void) diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c index 8b3b3eb3cead..ea5b5709aa76 100644 --- a/arch/x86/kernel/vsyscall_64.c +++ b/arch/x86/kernel/vsyscall_64.c @@ -91,7 +91,7 @@ static int addr_to_vsyscall_nr(unsigned long addr) { int nr; - if ((addr & ~0xC00UL) != VSYSCALL_START) + if ((addr & ~0xC00UL) != VSYSCALL_ADDR) return -EINVAL; nr = (addr & 0xC00UL) >> 10; @@ -330,24 +330,17 @@ void __init map_vsyscall(void) { extern char __vsyscall_page; unsigned long physaddr_vsyscall = __pa_symbol(&__vsyscall_page); - unsigned long physaddr_vvar_page = __pa_symbol(&__vvar_page); - __set_fixmap(VSYSCALL_FIRST_PAGE, physaddr_vsyscall, + __set_fixmap(VSYSCALL_PAGE, physaddr_vsyscall, vsyscall_mode == NATIVE ? PAGE_KERNEL_VSYSCALL : PAGE_KERNEL_VVAR); - BUILD_BUG_ON((unsigned long)__fix_to_virt(VSYSCALL_FIRST_PAGE) != - (unsigned long)VSYSCALL_START); - - __set_fixmap(VVAR_PAGE, physaddr_vvar_page, PAGE_KERNEL_VVAR); - BUILD_BUG_ON((unsigned long)__fix_to_virt(VVAR_PAGE) != - (unsigned long)VVAR_ADDRESS); + BUILD_BUG_ON((unsigned long)__fix_to_virt(VSYSCALL_PAGE) != + (unsigned long)VSYSCALL_ADDR); } static int __init vsyscall_init(void) { - BUG_ON(VSYSCALL_ADDR(0) != __fix_to_virt(VSYSCALL_FIRST_PAGE)); - cpu_notifier_register_begin(); on_each_cpu(cpu_vsyscall_init, NULL, 1); diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 8e5722992677..858b47b5221b 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -18,7 +18,8 @@ #include /* dotraplinkage, ... */ #include /* pgd_*(), ... */ #include /* kmemcheck_*(), ... */ -#include /* VSYSCALL_START */ +#include /* VSYSCALL_ADDR */ +#include /* emulate_vsyscall */ #define CREATE_TRACE_POINTS #include @@ -771,7 +772,7 @@ __bad_area_nosemaphore(struct pt_regs *regs, unsigned long error_code, * emulation. */ if (unlikely((error_code & PF_INSTR) && - ((address & ~0xfff) == VSYSCALL_START))) { + ((address & ~0xfff) == VSYSCALL_ADDR))) { if (emulate_vsyscall(regs, address)) return; } diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 563849600d3e..6f881842116c 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c @@ -1055,8 +1055,8 @@ void __init mem_init(void) after_bootmem = 1; /* Register memory areas for /proc/kcore */ - kclist_add(&kcore_vsyscall, (void *)VSYSCALL_START, - VSYSCALL_END - VSYSCALL_START, KCORE_OTHER); + kclist_add(&kcore_vsyscall, (void *)VSYSCALL_ADDR, + PAGE_SIZE, KCORE_OTHER); mem_init_print_info(NULL); } @@ -1186,8 +1186,8 @@ int kern_addr_valid(unsigned long addr) * not need special handling anymore: */ static struct vm_area_struct gate_vma = { - .vm_start = VSYSCALL_START, - .vm_end = VSYSCALL_START + (VSYSCALL_MAPPED_PAGES * PAGE_SIZE), + .vm_start = VSYSCALL_ADDR, + .vm_end = VSYSCALL_ADDR + PAGE_SIZE, .vm_page_prot = PAGE_READONLY_EXEC, .vm_flags = VM_READ | VM_EXEC }; @@ -1218,7 +1218,7 @@ int in_gate_area(struct mm_struct *mm, unsigned long addr) */ int in_gate_area_no_mm(unsigned long addr) { - return (addr >= VSYSCALL_START) && (addr < VSYSCALL_END); + return (addr & PAGE_MASK) == VSYSCALL_ADDR; } const char *arch_vma_name(struct vm_area_struct *vma) diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c index 091554c20bc9..b2e4f493e5b0 100644 --- a/arch/x86/vdso/vclock_gettime.c +++ b/arch/x86/vdso/vclock_gettime.c @@ -30,9 +30,12 @@ extern int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz); extern time_t __vdso_time(time_t *t); #ifdef CONFIG_HPET_TIMER -static inline u32 read_hpet_counter(const volatile void *addr) +extern u8 hpet_page + __attribute__((visibility("hidden"))); + +static notrace cycle_t vread_hpet(void) { - return *(const volatile u32 *) (addr + HPET_COUNTER); + return *(const volatile u32 *)(&hpet_page + HPET_COUNTER); } #endif @@ -43,11 +46,6 @@ static inline u32 read_hpet_counter(const volatile void *addr) #include #include -static notrace cycle_t vread_hpet(void) -{ - return read_hpet_counter((const void *)fix_to_virt(VSYSCALL_HPET)); -} - notrace static long vdso_fallback_gettime(long clock, struct timespec *ts) { long ret; @@ -137,16 +135,6 @@ static notrace cycle_t vread_pvclock(int *mode) #else -extern u8 hpet_page - __attribute__((visibility("hidden"))); - -#ifdef CONFIG_HPET_TIMER -static notrace cycle_t vread_hpet(void) -{ - return read_hpet_counter((const void *)(&hpet_page)); -} -#endif - notrace static long vdso_fallback_gettime(long clock, struct timespec *ts) { long ret; diff --git a/arch/x86/vdso/vdso-layout.lds.S b/arch/x86/vdso/vdso-layout.lds.S index e177c08bb4bc..2ec72f651ebf 100644 --- a/arch/x86/vdso/vdso-layout.lds.S +++ b/arch/x86/vdso/vdso-layout.lds.S @@ -47,7 +47,6 @@ SECTIONS .text : { *(.text*) } :text =0x90909090, -#ifdef BUILD_VDSO32 /* * The remainder of the vDSO consists of special pages that are * shared between the kernel and userspace. It needs to be at the @@ -69,7 +68,6 @@ SECTIONS hpet_page = .; . = . + PAGE_SIZE; -#endif . = ALIGN(PAGE_SIZE); end_mapping = .; diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c index 86e02eabb640..3060568248d3 100644 --- a/arch/x86/xen/mmu.c +++ b/arch/x86/xen/mmu.c @@ -1494,7 +1494,7 @@ static int xen_pgd_alloc(struct mm_struct *mm) page->private = (unsigned long)user_pgd; if (user_pgd != NULL) { - user_pgd[pgd_index(VSYSCALL_START)] = + user_pgd[pgd_index(VSYSCALL_ADDR)] = __pgd(__pa(level3_user_vsyscall) | _PAGE_TABLE); ret = 0; } @@ -2062,8 +2062,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot) case FIX_KMAP_BEGIN ... FIX_KMAP_END: # endif #else - case VSYSCALL_LAST_PAGE ... VSYSCALL_FIRST_PAGE: - case VVAR_PAGE: + case VSYSCALL_PAGE: #endif case FIX_TEXT_POKE0: case FIX_TEXT_POKE1: @@ -2104,8 +2103,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot) #ifdef CONFIG_X86_64 /* Replicate changes to map the vsyscall page into the user pagetable vsyscall mapping. */ - if ((idx >= VSYSCALL_LAST_PAGE && idx <= VSYSCALL_FIRST_PAGE) || - idx == VVAR_PAGE) { + if (idx == VSYSCALL_PAGE) { unsigned long vaddr = __fix_to_virt(idx); set_pte_vaddr_pud(level3_user_vsyscall, vaddr, pte); } -- cgit v1.2.3 From 2b6f2e649f7376d9871df63a9aa0b41efd464d74 Mon Sep 17 00:00:00 2001 From: Andy Lutomirski Date: Mon, 5 May 2014 12:19:37 -0700 Subject: x86, vdso: Remove vestiges of VDSO_PRELINK and some outdated comments These definitions had no effect. Signed-off-by: Andy Lutomirski Link: http://lkml.kernel.org/r/946c104e40c47319f8ab406e54118799cb55bd99.1399317206.git.luto@amacapital.net Signed-off-by: H. Peter Anvin --- arch/x86/vdso/vdso.lds.S | 7 +------ arch/x86/vdso/vdso32/vdso32.lds.S | 5 +---- arch/x86/vdso/vdsox32.lds.S | 7 +------ 3 files changed, 3 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/x86/vdso/vdso.lds.S b/arch/x86/vdso/vdso.lds.S index b96b2677cad8..75e3404c83b1 100644 --- a/arch/x86/vdso/vdso.lds.S +++ b/arch/x86/vdso/vdso.lds.S @@ -1,14 +1,11 @@ /* * Linker script for 64-bit vDSO. * We #include the file to define the layout details. - * Here we only choose the prelinked virtual address. * * This file defines the version script giving the user-exported symbols in - * the DSO. We can define local symbols here called VDSO* to make their - * values visible using the asm-x86/vdso.h macros from the kernel proper. + * the DSO. */ -#define VDSO_PRELINK 0xffffffffff700000 #include "vdso-layout.lds.S" /* @@ -28,5 +25,3 @@ VERSION { local: *; }; } - -VDSO64_PRELINK = VDSO_PRELINK; diff --git a/arch/x86/vdso/vdso32/vdso32.lds.S b/arch/x86/vdso/vdso32/vdso32.lds.S index f072095d6427..31056cf294bf 100644 --- a/arch/x86/vdso/vdso32/vdso32.lds.S +++ b/arch/x86/vdso/vdso32/vdso32.lds.S @@ -1,17 +1,14 @@ /* * Linker script for 32-bit vDSO. * We #include the file to define the layout details. - * Here we only choose the prelinked virtual address. * * This file defines the version script giving the user-exported symbols in - * the DSO. We can define local symbols here called VDSO* to make their - * values visible using the asm-x86/vdso.h macros from the kernel proper. + * the DSO. */ #include #define BUILD_VDSO32 -#define VDSO_PRELINK 0 #include "../vdso-layout.lds.S" diff --git a/arch/x86/vdso/vdsox32.lds.S b/arch/x86/vdso/vdsox32.lds.S index 62272aa2ae0a..46b991b578a8 100644 --- a/arch/x86/vdso/vdsox32.lds.S +++ b/arch/x86/vdso/vdsox32.lds.S @@ -1,14 +1,11 @@ /* * Linker script for x32 vDSO. * We #include the file to define the layout details. - * Here we only choose the prelinked virtual address. * * This file defines the version script giving the user-exported symbols in - * the DSO. We can define local symbols here called VDSO* to make their - * values visible using the asm-x86/vdso.h macros from the kernel proper. + * the DSO. */ -#define VDSO_PRELINK 0 #include "vdso-layout.lds.S" /* @@ -24,5 +21,3 @@ VERSION { local: *; }; } - -VDSOX32_PRELINK = VDSO_PRELINK; -- cgit v1.2.3 From 1171903d899b1930f502b4c10a2a3565d6603c71 Mon Sep 17 00:00:00 2001 From: Ulrich Obergfell Date: Fri, 2 May 2014 17:57:47 +0200 Subject: KVM: x86: improve the usability of the 'kvm_pio' tracepoint This patch moves the 'kvm_pio' tracepoint to emulator_pio_in_emulated() and emulator_pio_out_emulated(), and it adds an argument (a pointer to the 'pio_data'). A single 8-bit or 16-bit or 32-bit data item is fetched from 'pio_data' (depending on 'size'), and the value is included in the trace record ('val'). If 'count' is greater than one, this is indicated by the string "(...)" in the trace output. Signed-off-by: Ulrich Obergfell Reviewed-by: Xiao Guangrong Signed-off-by: Paolo Bonzini --- arch/x86/kvm/trace.h | 20 ++++++++++++++++---- arch/x86/kvm/x86.c | 4 ++-- 2 files changed, 18 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index 545245d7cc63..33574c95220d 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -91,16 +91,21 @@ TRACE_EVENT(kvm_hv_hypercall, /* * Tracepoint for PIO. */ + +#define KVM_PIO_IN 0 +#define KVM_PIO_OUT 1 + TRACE_EVENT(kvm_pio, TP_PROTO(unsigned int rw, unsigned int port, unsigned int size, - unsigned int count), - TP_ARGS(rw, port, size, count), + unsigned int count, void *data), + TP_ARGS(rw, port, size, count, data), TP_STRUCT__entry( __field( unsigned int, rw ) __field( unsigned int, port ) __field( unsigned int, size ) __field( unsigned int, count ) + __field( unsigned int, val ) ), TP_fast_assign( @@ -108,11 +113,18 @@ TRACE_EVENT(kvm_pio, __entry->port = port; __entry->size = size; __entry->count = count; + if (size == 1) + __entry->val = *(unsigned char *)data; + else if (size == 2) + __entry->val = *(unsigned short *)data; + else + __entry->val = *(unsigned int *)data; ), - TP_printk("pio_%s at 0x%x size %d count %d", + TP_printk("pio_%s at 0x%x size %d count %d val 0x%x %s", __entry->rw ? "write" : "read", - __entry->port, __entry->size, __entry->count) + __entry->port, __entry->size, __entry->count, __entry->val, + __entry->count > 1 ? "(...)" : "") ); /* diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c5582c385bc0..de0931cb3f58 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4480,8 +4480,6 @@ static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, unsigned short port, void *val, unsigned int count, bool in) { - trace_kvm_pio(!in, port, size, count); - vcpu->arch.pio.port = port; vcpu->arch.pio.in = in; vcpu->arch.pio.count = count; @@ -4516,6 +4514,7 @@ static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, if (ret) { data_avail: memcpy(val, vcpu->arch.pio_data, size * count); + trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data); vcpu->arch.pio.count = 0; return 1; } @@ -4530,6 +4529,7 @@ static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); memcpy(vcpu->arch.pio_data, val, size * count); + trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data); return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); } -- cgit v1.2.3 From 189c20832903abfec38242255b84e2c4f6a8552f Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 15 Apr 2014 15:10:27 -0600 Subject: ARM: multi_v7: enable AT24C EEPROM driver This is used for the board ID EEPROM on Jetson TK1, as well as likely a whole slew of other NVIDIA reference boards; we simply haven't added enabled the EEPROM in the DT files until now. Signed-off-by: Stephen Warren Signed-off-by: Olof Johansson --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index d4e8a47a2f7c..a692b7ae3bd1 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -112,6 +112,7 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_ICS932S401=y CONFIG_APDS9802ALS=y CONFIG_ISL29003=y +CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_SCSI_MULTI_LUN=y -- cgit v1.2.3 From 9630cc932489ec671a6d0ecd9b062a23bec74a36 Mon Sep 17 00:00:00 2001 From: Antoine Ténart Date: Thu, 17 Apr 2014 10:42:30 +0200 Subject: ARM: multi_v7_defconfig: select CONFIG_GPIO_DWAPB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The newly integrated dwapb gpio driver handles the Berlin SoCs GPIOs. Add this driver to the multi_v7_defconfig. Signed-off-by: Antoine Ténart Signed-off-by: Olof Johansson --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index a692b7ae3bd1..1014e9d52ae1 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -192,6 +192,7 @@ CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_PALMAS=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_TWL4030=y CONFIG_GPIO_PALMAS=y -- cgit v1.2.3 From f1e9637f4b49690a6c5793f1745f743506b1bfd1 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 21 Mar 2014 20:39:17 +0100 Subject: ARM: multi_v7_defconfig: Select CONFIG_MACH_BERLIN_BG2Q Now that we support Berlin BG2Q, select CONFIG_MACH_BERLIN_BG2Q so that we can boot BG2Q based boards like the BG2Q DMP. Signed-off-by: Alexandre Belloni Acked-by: Sebastian Hesselbarth Signed-off-by: Olof Johansson --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 1014e9d52ae1..8b3c10ae22c9 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BCM_MOBILE=y CONFIG_ARCH_BERLIN=y CONFIG_MACH_BERLIN_BG2=y CONFIG_MACH_BERLIN_BG2CD=y +CONFIG_MACH_BERLIN_BG2Q=y CONFIG_GPIO_PCA953X=y CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_HI3xxx=y -- cgit v1.2.3 From 55fc5ecd6c2746b93e1363d86692fea68ca906d0 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 16:41:18 +0200 Subject: ARM: configs: add CONFIG_MMC_SDHCI_PXAV3 to the multi_v7_defconfig The Marvell Armada 38x platform has a SDHCI interface managed by the sdhci-pxav3 MMC host driver. It therefore makes sense to enable this driver in multi_v7_defconfig, which supports the Armada 38x platform. Signed-off-by: Thomas Petazzoni Acked-by: Jason Cooper Signed-off-by: Olof Johansson --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 8b3c10ae22c9..5039cc6cedc0 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -276,6 +276,7 @@ CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MMC_SDHCI_PXAV3=y CONFIG_MMC_SDHCI_TEGRA=y CONFIG_MMC_SDHCI_DOVE=y CONFIG_MMC_SDHCI_SPEAR=y -- cgit v1.2.3 From 3906c0a688587408fa37a411d5e79778039e9dc3 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 2 May 2014 17:57:29 +0200 Subject: ARM: dts: sun7i: Add basic support for the Cubietruck WiFi module The CubieTruck has an AMPAK AP6210 WiFi+Bluetooth module. The WiFi part is a BCM43362 IC connected to MMC3 in the A20 SoC via SDIO. The IC also takes a power enable signal via GPIO. The WiFi module supports out-of-band interrupt signaling via GPIO, but this is not supported in this patch. Signed-off-by: Chen-Yu Tsai Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index a39f08970b64..9dbb763c8e27 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -29,6 +29,14 @@ status = "okay"; }; + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_vmmc3>; + non-removable; + status = "okay"; + }; + usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -57,6 +65,18 @@ }; pinctrl@01c20800 { + mmc3_pins_a: mmc3@0 { + /* AP6210 requires pull-up */ + allwinner,pull = <1>; + }; + + vmmc3_pin_cubietruck: vmmc3_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 { allwinner,pins = "PH12"; allwinner,function = "gpio_out"; @@ -154,4 +174,15 @@ reg_usb2_vbus: usb2-vbus { status = "okay"; }; + + reg_vmmc3: vmmc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc3_pin_cubietruck>; + regulator-name = "vmmc3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 7 9 0>; + }; }; -- cgit v1.2.3 From 55fde31cae6a815a184271317abf15f468abcb44 Mon Sep 17 00:00:00 2001 From: Joel Fernandes Date: Tue, 29 Apr 2014 21:53:47 -0500 Subject: ARM: OMAP5: Redo THUMB mode switch on secondary CPU Here's a redo of the patch [1] that effectively does the same thing but is the right way to do things by using ENDPROC instead. The firmware correctly switches to THUMB before entry. The patch applies ontop of the earlier patch [1]. [1] https://lkml.org/lkml/2014/4/22/1044 Suggested-by: Dave Martin Cc: Dave Martin Cc: Santosh Shilimkar Cc: Russell King Cc: Nishanth Menon Cc: Tony Lindgren Signed-off-by: Joel Fernandes Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-headsmp.S | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 40c5d5f1451c..4993d4bfe9b2 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -31,10 +31,6 @@ * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) -.arm -THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. -THUMB( bx r9 ) @ If this is a Thumb-2 kernel, -THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5 @@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 cmp r0, r4 bne wait b secondary_startup -END(omap5_secondary_startup) +ENDPROC(omap5_secondary_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which -- cgit v1.2.3 From 332f19317e50bf9bb7eff16b98403ef11ee25751 Mon Sep 17 00:00:00 2001 From: Oussama Ghorbel Date: Mon, 14 Apr 2014 17:49:30 +0100 Subject: ARM: OMAP2+: free use_gptimer_clksrc variable after boot The variable use_gptimer_clksrc is only used by two __init functions, So we can freely free it after boot. Signed-off-by: Oussama Ghorbel Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b62de9f9d05c..842b81f31957 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -361,7 +361,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, /* Clocksource code */ static struct omap_dm_timer clksrc; -static bool use_gptimer_clksrc; +static bool use_gptimer_clksrc __initdata; /* * clocksource -- cgit v1.2.3 From 6ecb6ca410db42ba0982381a071874ab53950799 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 25 Apr 2014 15:36:26 +0200 Subject: ARM: dts: am335x-boneblack: remove use of ti,vcc-aux-disable-is-sleep Remove use of property ti,vcc-aux-disable-is-sleep, which does not exist. Signed-off-by: Johan Hovold Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 6b71ad95a5cf..305975d3f531 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -26,7 +26,6 @@ pinctrl-0 = <&emmc_pins>; bus-width = <8>; status = "okay"; - ti,vcc-aux-disable-is-sleep; }; &am33xx_pinmux { -- cgit v1.2.3 From 083cdaf3ed035a156d8361d419c6708b84846bf6 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 10:39:35 -0500 Subject: ARM: socfpga: dts: fix pdma interrupt The first interrupt is not at 180 but 104. Fix it. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 56fc214e6d2c..97a9346a7bc5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -75,7 +75,7 @@ pdma: pdma@ffe01000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffe01000 0x1000>; - interrupts = <0 180 4>; + interrupts = <0 104 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; -- cgit v1.2.3 From 18d561990a8c5b78f5274064bb450aef931408ab Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 10:40:30 -0500 Subject: ARM: socfpga: dts: add remaining interrupts for pdma Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 97a9346a7bc5..d13652ca5eee 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -75,7 +75,14 @@ pdma: pdma@ffe01000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffe01000 0x1000>; - interrupts = <0 104 4>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; -- cgit v1.2.3 From fdeda1566af8b25c726d4ce177a5a306772fe6b8 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 11:05:31 -0500 Subject: ARM: socfpga: dts: add i2c busses Add all 4 i2c busses. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index d13652ca5eee..f3df5da1406f 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -482,6 +482,46 @@ status = "disabled"; }; + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + L2: l2-cache@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; -- cgit v1.2.3 From 36fe3f5455faa709f15b7a0b492c0b62142213b3 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 11:11:26 -0500 Subject: ARM: socfpga: dts: add can0+1 Add both can controllers to the dtsi. Reviewed-by: Pavel Machek Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f3df5da1406f..84d12b1af037 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -91,6 +91,22 @@ }; }; + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; -- cgit v1.2.3 From ca94287c40ca8bce8a727663288ca7027fd32c88 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 11:13:11 -0500 Subject: ARM: socfpga: dts: add support for EBV SOCrates The SOCrates is a SOCFpga-Cyclone5 based board from EBV. Add support for it. Reviewed-by: Pavel Machek Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 41 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_socrates.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 35c146f31e46..e7ec14a2126f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -327,6 +327,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ + socfpga_cyclone5_socrates.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ spear1340-evb.dtb diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 000000000000..1e31f3281f1c --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/include/ "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&mmc { + status = "okay"; +}; -- cgit v1.2.3 From 1a721677194c98536c75e776e0f83795089ff1aa Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 11:14:50 -0500 Subject: ARM: socfpga: dts: add rtc on i2c0 to socrates The SOCrates has an M41T82M RTC on i2c0. Add it. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index 1e31f3281f1c..f8d17dcc8761 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -36,6 +36,15 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + &mmc { status = "okay"; }; -- cgit v1.2.3 From 7da9b436d837941533ec0a0ccc78d3b294f997e8 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 2 Apr 2014 21:31:31 -0500 Subject: ARM: socfpga: dts: convert to preprocessor includes Convert all socfpga DT files to the dtc preprocessor include syntax. This allows to include header files in the devicetrees like other SoC-types already do. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 2 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 2 +- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts | 2 +- arch/arm/boot/dts/socfpga_vt.dts | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 84d12b1af037..4393c4565fe5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -15,7 +15,7 @@ * along with this program. If not, see . */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { #address-cells = <1>; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 6c87b7070ca7..373b340e4931 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -15,7 +15,7 @@ */ /dts-v1/; -/include/ "socfpga.dtsi" +#include "socfpga.dtsi" / { soc { diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index a87ee1c07661..88e4a8e02033 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -15,7 +15,7 @@ * along with this program. If not, see . */ -/include/ "socfpga_arria5.dtsi" +#include "socfpga_arria5.dtsi" / { model = "Altera SOCFPGA Arria V SoC Development Kit"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index ca41b0ebf461..63a951366a98 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -16,7 +16,7 @@ */ /dts-v1/; -/include/ "socfpga.dtsi" +#include "socfpga.dtsi" / { soc { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index ae16d975196d..5e9445a1caf7 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -15,7 +15,7 @@ * along with this program. If not, see . */ -/include/ "socfpga_cyclone5.dtsi" +#include "socfpga_cyclone5.dtsi" / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index b79e2a2bf175..d5ce22cf784a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -15,7 +15,7 @@ * along with this program. If not, see . */ -/include/ "socfpga_cyclone5.dtsi" +#include "socfpga_cyclone5.dtsi" / { model = "Terasic SoCkit"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index f8d17dcc8761..a1814b457450 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -15,7 +15,7 @@ * along with this program. If not, see . */ -/include/ "socfpga_cyclone5.dtsi" +#include "socfpga_cyclone5.dtsi" / { model = "EBV SOCrates"; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 87d6f759a9c1..09792b411110 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -16,7 +16,7 @@ */ /dts-v1/; -/include/ "socfpga.dtsi" +#include "socfpga.dtsi" / { model = "Altera SOCFPGA VT"; -- cgit v1.2.3 From 58303f1f961d6a1abc0496790c9c557d67e9ae64 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 2 Apr 2014 14:02:42 -0500 Subject: ARM: socfpga: dts: add eeprom and rtc on i2c0 The Altera Cyclone5 and Arria5 devkit has an EEPROM and a RTC on the board. This patch adds support for them. Signed-off-by: Dinh Nguyen --- v2: Remove LCD as the driver has not been upstreamed. --- arch/arm/boot/dts/socfpga_arria5_socdk.dts | 15 +++++++++++++++ arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 15 +++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 88e4a8e02033..a04061f6bb0a 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -59,3 +59,18 @@ rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 5e9445a1caf7..55d54f7ad212 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -52,3 +52,18 @@ rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; -- cgit v1.2.3 From bd785efda77c073e8ed5c7f29c7bdab6a3f3f6ad Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 2 Apr 2014 21:14:57 -0500 Subject: ARM: socfpga: dts: Remove hard coded clock-frequency property The timers and uart can get their clock frequencies using the common clock driver. Reviewed-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 10 ++++++++++ arch/arm/boot/dts/socfpga_arria5.dtsi | 24 ------------------------ arch/arm/boot/dts/socfpga_cyclone5.dtsi | 24 ------------------------ 3 files changed, 10 insertions(+), 48 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4393c4565fe5..2c3922f700f3 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -571,24 +571,32 @@ compatible = "snps,dw-apb-timer"; interrupts = <0 167 4>; reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; }; timer1: timer1@ffc09000 { compatible = "snps,dw-apb-timer"; interrupts = <0 168 4>; reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; }; timer2: timer2@ffd00000 { compatible = "snps,dw-apb-timer"; interrupts = <0 169 4>; reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; }; timer3: timer3@ffd01000 { compatible = "snps,dw-apb-timer"; interrupts = <0 170 4>; reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; }; uart0: serial0@ffc02000 { @@ -597,6 +605,7 @@ interrupts = <0 162 4>; reg-shift = <2>; reg-io-width = <4>; + clocks = <&l4_sp_clk>; }; uart1: serial1@ffc03000 { @@ -605,6 +614,7 @@ interrupts = <0 163 4>; reg-shift = <2>; reg-io-width = <4>; + clocks = <&l4_sp_clk>; }; rstmgr@ffd05000 { diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 373b340e4931..12d1c2ccaf5b 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -38,32 +38,8 @@ }; }; - serial0@ffc02000 { - clock-frequency = <100000000>; - }; - - serial1@ffc03000 { - clock-frequency = <100000000>; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; - - timer0@ffc08000 { - clock-frequency = <100000000>; - }; - - timer1@ffc09000 { - clock-frequency = <100000000>; - }; - - timer2@ffd00000 { - clock-frequency = <25000000>; - }; - - timer3@ffd01000 { - clock-frequency = <25000000>; - }; }; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 63a951366a98..bf511828729f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -45,30 +45,6 @@ status = "okay"; }; - timer0@ffc08000 { - clock-frequency = <100000000>; - }; - - timer1@ffc09000 { - clock-frequency = <100000000>; - }; - - timer2@ffd00000 { - clock-frequency = <25000000>; - }; - - timer3@ffd01000 { - clock-frequency = <25000000>; - }; - - serial0@ffc02000 { - clock-frequency = <100000000>; - }; - - serial1@ffc03000 { - clock-frequency = <100000000>; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; -- cgit v1.2.3 From 1403250b6bac281ebf741b7c07263cc6fb2c6466 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 28 Oct 2013 09:48:32 -0500 Subject: ARM: socfpga: dts: Add DTS entries for USB Update all the SOCFPGA DTS files with USB entries. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 28 +++++++++++++++++++++++++++ arch/arm/boot/dts/socfpga_arria5_socdk.dts | 4 ++++ arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 4 ++++ arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 4 ++++ 4 files changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2c3922f700f3..f31c5fa5525b 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -622,6 +622,34 @@ reg = <0xffd05000 0x1000>; }; + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + sysmgr: sysmgr@ffd08000 { compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x4000>; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index a04061f6bb0a..d532d171e391 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -74,3 +74,7 @@ reg = <0x68>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 55d54f7ad212..45de1514af0a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -67,3 +67,7 @@ reg = <0x68>; }; }; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index d5ce22cf784a..d26f155f5fd9 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -52,3 +52,7 @@ rxdv-skew-ps = <0>; rxc-skew-ps = <2000>; }; + +&usb1 { + status = "okay"; +}; -- cgit v1.2.3 From 16fb4f8bd59e0e954991f624bcc53dad2052ef0d Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Tue, 15 Apr 2014 17:27:07 -0500 Subject: ARM: socfpga: dts: add reset-controller Add the necessary #reset-cells property to the rst-mgr node and provide a header-file with all possible resets specified. Signed-off-by: Steffen Trumtrar Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 7 ++- include/dt-bindings/reset/altr,rst-mgr.h | 90 ++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h (limited to 'arch') diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index f31c5fa5525b..917464ac01ef 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -16,6 +16,7 @@ */ #include "skeleton.dtsi" +#include / { #address-cells = <1>; @@ -483,6 +484,8 @@ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ clocks = <&emac0_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -495,6 +498,8 @@ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ clocks = <&emac1_clk>; clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; status = "disabled"; }; @@ -617,7 +622,7 @@ clocks = <&l4_sp_clk>; }; - rstmgr@ffd05000 { + rst: rstmgr@ffd05000 { compatible = "altr,rst-mgr"; reg = <0xffd05000 0x1000>; }; diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 000000000000..3f04908fb87c --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif -- cgit v1.2.3 From 8cb289ed60668d3350dda5aa19b4fa1dce1c07f1 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 16 Apr 2014 15:05:15 -0500 Subject: ARM: socfpga: dts: Add div-reg to the main_pll clocks The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/clock/altr_socfpga.txt | 4 ++-- arch/arm/boot/dts/socfpga.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 5dfd145d3ccf..f72e80e0dade 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -21,8 +21,8 @@ Optional properties: - fixed-divider : If clocks have a fixed divider value, use this property. - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register and the bit index. -- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, - and width. +- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains + the divider register, bit shift, and width. - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 917464ac01ef..280966b92e5e 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -148,7 +148,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <2>; + div-reg = <0xe0 0 9>; reg = <0x48>; }; @@ -156,7 +156,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <4>; + div-reg = <0xe4 0 9>; reg = <0x4C>; }; @@ -164,7 +164,7 @@ #clock-cells = <0>; compatible = "altr,socfpga-perip-clk"; clocks = <&main_pll>; - fixed-divider = <4>; + div-reg = <0xe8 0 9>; reg = <0x50>; }; -- cgit v1.2.3 From f7b1e9b5bc87a379c9746091aae4de4ece4e7931 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Mon, 5 May 2014 10:16:08 -0700 Subject: ARM: zynq: dt: Clean up device tree - Use generic node names - Fix up some weird formatting and white spaces - Update copyright info Signed-off-by: Soren Brinkmann --- arch/arm/boot/dts/zynq-7000.dtsi | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 34dff3856e99..c494f9651499 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -55,7 +55,7 @@ interrupt-parent = <&intc>; ranges; - i2c0: zynq-i2c@e0004000 { + i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; @@ -66,7 +66,7 @@ #size-cells = <0>; }; - i2c1: zynq-i2c@e0005000 { + i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; @@ -94,7 +94,7 @@ cache-level = <2>; }; - uart0: uart@e0000000 { + uart0: serial@e0000000 { compatible = "xlnx,xuartps"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; @@ -103,7 +103,7 @@ interrupts = <0 27 4>; }; - uart1: uart@e0001000 { + uart1: serial@e0001000 { compatible = "xlnx,xuartps"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; @@ -130,7 +130,7 @@ clock-names = "pclk", "hclk", "tx_clk"; }; - sdhci0: ps7-sdhci@e0100000 { + sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -140,7 +140,7 @@ reg = <0xe0100000 0x1000>; } ; - sdhci1: ps7-sdhci@e0101000 { + sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; @@ -184,26 +184,27 @@ clocks = <&clkc 4>; }; - ttc0: ttc0@f8001000 { + ttc0: timer@f8001000 { interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; - ttc1: ttc1@f8002000 { + ttc1: timer@f8002000 { interrupt-parent = <&intc>; - interrupts = < 0 37 4 0 38 4 0 39 4 >; + interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; - scutimer: scutimer@f8f00600 { + + scutimer: timer@f8f00600 { interrupt-parent = <&intc>; - interrupts = < 1 13 0x301 >; + interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; - reg = < 0xf8f00600 0x20 >; + reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; } ; }; -- cgit v1.2.3 From fcc9aec3de0a1d00cbce47f7274ec0c62122266b Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 3 May 2014 23:18:11 +0300 Subject: KVM: s390: return -EFAULT if copy_from_user() fails When copy_from_user() fails, this code returns the number of bytes remaining instead of a negative error code. The positive number is returned to the user but otherwise it is harmless. Signed-off-by: Dan Carpenter Signed-off-by: Christian Borntraeger --- arch/s390/kvm/guestdbg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/s390/kvm/guestdbg.c b/arch/s390/kvm/guestdbg.c index 757ccef62fd5..3e8d4092ce30 100644 --- a/arch/s390/kvm/guestdbg.c +++ b/arch/s390/kvm/guestdbg.c @@ -223,9 +223,10 @@ int kvm_s390_import_bp_data(struct kvm_vcpu *vcpu, goto error; } - ret = copy_from_user(bp_data, dbg->arch.hw_bp, size); - if (ret) + if (copy_from_user(bp_data, dbg->arch.hw_bp, size)) { + ret = -EFAULT; goto error; + } for (i = 0; i < dbg->arch.nr_hw_bp; i++) { switch (bp_data[i].type) { -- cgit v1.2.3 From e029ae5b787e08e976a683c6a45fac20fc227447 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Wed, 26 Mar 2014 16:11:54 +0100 Subject: KVM: s390: Add clock comparator and CPU timer IRQ injection Add an interface to inject clock comparator and CPU timer interrupts into the guest. This is needed for handling the external interrupt interception. Signed-off-by: Thomas Huth Reviewed-by: David Hildenbrand Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- Documentation/virtual/kvm/api.txt | 2 ++ arch/s390/kvm/interrupt.c | 32 ++++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 2 ++ 3 files changed, 36 insertions(+) (limited to 'arch') diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 2014ff12b492..0581f6c40f2b 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2211,6 +2211,8 @@ KVM_S390_SIGP_STOP (vcpu) - sigp restart KVM_S390_PROGRAM_INT (vcpu) - program check; code in parm KVM_S390_SIGP_SET_PREFIX (vcpu) - sigp set prefix; prefix address in parm KVM_S390_RESTART (vcpu) - restart +KVM_S390_INT_CLOCK_COMP (vcpu) - clock comparator interrupt +KVM_S390_INT_CPU_TIMER (vcpu) - CPU timer interrupt KVM_S390_INT_VIRTIO (vm) - virtio external interrupt; external interrupt parameters in parm and parm64 KVM_S390_INT_SERVICE (vm) - sclp external interrupt; sclp parameter in parm diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c index d9526bb29194..75cd3217cd5a 100644 --- a/arch/s390/kvm/interrupt.c +++ b/arch/s390/kvm/interrupt.c @@ -27,6 +27,8 @@ #define IOINT_CSSID_MASK 0x03fc0000 #define IOINT_AI_MASK 0x04000000 +static void deliver_ckc_interrupt(struct kvm_vcpu *vcpu); + static int is_ioint(u64 type) { return ((type & 0xfffe0000u) != 0xfffe0000u); @@ -89,6 +91,14 @@ static int __interrupt_is_deliverable(struct kvm_vcpu *vcpu, if (vcpu->arch.sie_block->gcr[0] & 0x4000ul) return 1; return 0; + case KVM_S390_INT_CLOCK_COMP: + return ckc_interrupts_enabled(vcpu); + case KVM_S390_INT_CPU_TIMER: + if (psw_extint_disabled(vcpu)) + return 0; + if (vcpu->arch.sie_block->gcr[0] & 0x400ul) + return 1; + return 0; case KVM_S390_INT_SERVICE: case KVM_S390_INT_PFAULT_INIT: case KVM_S390_INT_PFAULT_DONE: @@ -166,6 +176,8 @@ static void __set_intercept_indicator(struct kvm_vcpu *vcpu, case KVM_S390_INT_PFAULT_INIT: case KVM_S390_INT_PFAULT_DONE: case KVM_S390_INT_VIRTIO: + case KVM_S390_INT_CLOCK_COMP: + case KVM_S390_INT_CPU_TIMER: if (psw_extint_disabled(vcpu)) __set_cpuflag(vcpu, CPUSTAT_EXT_INT); else @@ -326,6 +338,24 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu, &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); break; + case KVM_S390_INT_CLOCK_COMP: + trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, + inti->ext.ext_params, 0); + deliver_ckc_interrupt(vcpu); + break; + case KVM_S390_INT_CPU_TIMER: + trace_kvm_s390_deliver_interrupt(vcpu->vcpu_id, inti->type, + inti->ext.ext_params, 0); + rc = put_guest_lc(vcpu, EXT_IRQ_CPU_TIMER, + (u16 *)__LC_EXT_INT_CODE); + rc |= write_guest_lc(vcpu, __LC_EXT_OLD_PSW, + &vcpu->arch.sie_block->gpsw, + sizeof(psw_t)); + rc |= read_guest_lc(vcpu, __LC_EXT_NEW_PSW, + &vcpu->arch.sie_block->gpsw, sizeof(psw_t)); + rc |= put_guest_lc(vcpu, inti->ext.ext_params, + (u32 *)__LC_EXT_PARAMS); + break; case KVM_S390_INT_SERVICE: VCPU_EVENT(vcpu, 4, "interrupt: sclp parm:%x", inti->ext.ext_params); @@ -984,6 +1014,8 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu, break; case KVM_S390_SIGP_STOP: case KVM_S390_RESTART: + case KVM_S390_INT_CLOCK_COMP: + case KVM_S390_INT_CPU_TIMER: VCPU_EVENT(vcpu, 3, "inject: type %x", s390int->type); inti->type = s390int->type; break; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 836e15b7abc8..2b83cf35437a 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -416,6 +416,8 @@ struct kvm_s390_psw { #define KVM_S390_INT_PFAULT_INIT 0xfffe0004u #define KVM_S390_INT_PFAULT_DONE 0xfffe0005u #define KVM_S390_MCHK 0xfffe1000u +#define KVM_S390_INT_CLOCK_COMP 0xffff1004u +#define KVM_S390_INT_CPU_TIMER 0xffff1005u #define KVM_S390_INT_VIRTIO 0xffff2603u #define KVM_S390_INT_SERVICE 0xffff2401u #define KVM_S390_INT_EMERGENCY 0xffff1201u -- cgit v1.2.3 From f14d82e06a008b8977b64866a4907d2e152af939 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Wed, 15 Jan 2014 16:46:07 +0100 Subject: KVM: s390: Fix external interrupt interception The external interrupt interception can only occur in rare cases, e.g. when the PSW of the interrupt handler has a bad value. The old handler for this interception simply ignored these events (except for increasing the exit_external_interrupt counter), but for proper operation we either have to inject the interrupts manually or we should drop to userspace in case of errors. Signed-off-by: Thomas Huth Reviewed-by: David Hildenbrand Reviewed-by: Cornelia Huck Signed-off-by: Christian Borntraeger --- arch/s390/include/asm/kvm_host.h | 5 +++- arch/s390/kvm/intercept.c | 49 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 49 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index f0a1dc5e5d1f..96b8a67ddaf8 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -132,7 +132,10 @@ struct kvm_s390_sie_block { psw_t gpsw; /* 0x0090 */ __u64 gg14; /* 0x00a0 */ __u64 gg15; /* 0x00a8 */ - __u8 reservedb0[28]; /* 0x00b0 */ + __u8 reservedb0[20]; /* 0x00b0 */ + __u16 extcpuaddr; /* 0x00c4 */ + __u16 eic; /* 0x00c6 */ + __u32 reservedc8; /* 0x00c8 */ __u16 pgmilc; /* 0x00cc */ __u16 iprcc; /* 0x00ce */ __u32 dxc; /* 0x00d0 */ diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index 99e4b76e3487..bd607cf01a5d 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -17,6 +17,7 @@ #include #include +#include #include "kvm-s390.h" #include "gaccess.h" @@ -46,9 +47,6 @@ static int handle_noop(struct kvm_vcpu *vcpu) case 0x10: vcpu->stat.exit_external_request++; break; - case 0x14: - vcpu->stat.exit_external_interrupt++; - break; default: break; /* nothing */ } @@ -233,6 +231,49 @@ static int handle_instruction_and_prog(struct kvm_vcpu *vcpu) return rc2; } +/** + * handle_external_interrupt - used for external interruption interceptions + * + * This interception only occurs if the CPUSTAT_EXT_INT bit was set, or if + * the new PSW does not have external interrupts disabled. In the first case, + * we've got to deliver the interrupt manually, and in the second case, we + * drop to userspace to handle the situation there. + */ +static int handle_external_interrupt(struct kvm_vcpu *vcpu) +{ + u16 eic = vcpu->arch.sie_block->eic; + struct kvm_s390_interrupt irq; + psw_t newpsw; + int rc; + + vcpu->stat.exit_external_interrupt++; + + rc = read_guest_lc(vcpu, __LC_EXT_NEW_PSW, &newpsw, sizeof(psw_t)); + if (rc) + return rc; + /* We can not handle clock comparator or timer interrupt with bad PSW */ + if ((eic == EXT_IRQ_CLK_COMP || eic == EXT_IRQ_CPU_TIMER) && + (newpsw.mask & PSW_MASK_EXT)) + return -EOPNOTSUPP; + + switch (eic) { + case EXT_IRQ_CLK_COMP: + irq.type = KVM_S390_INT_CLOCK_COMP; + break; + case EXT_IRQ_CPU_TIMER: + irq.type = KVM_S390_INT_CPU_TIMER; + break; + case EXT_IRQ_EXTERNAL_CALL: + irq.type = KVM_S390_INT_EXTERNAL_CALL; + irq.parm = vcpu->arch.sie_block->extcpuaddr; + break; + default: + return -EOPNOTSUPP; + } + + return kvm_s390_inject_vcpu(vcpu, &irq); +} + /** * Handle MOVE PAGE partial execution interception. * @@ -291,7 +332,7 @@ static const intercept_handler_t intercept_funcs[] = { [0x08 >> 2] = handle_prog, [0x0C >> 2] = handle_instruction_and_prog, [0x10 >> 2] = handle_noop, - [0x14 >> 2] = handle_noop, + [0x14 >> 2] = handle_external_interrupt, [0x18 >> 2] = handle_noop, [0x1C >> 2] = kvm_s390_handle_wait, [0x20 >> 2] = handle_validity, -- cgit v1.2.3 From 2347152bb7684a1f7d66b62f9fd91b30939675ad Mon Sep 17 00:00:00 2001 From: Pekon Gupta Date: Tue, 22 Apr 2014 14:32:42 +0530 Subject: ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition MTD NAND partition for file-system should start at offset=0xA00000 Signed-off-by: Pekon Gupta [tony@atomide.com: changed to lower case hex like we tend to use] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 167dbc8494de..2836328b90c8 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -341,7 +341,7 @@ }; partition@9 { label = "NAND.file-system"; - reg = <0x00800000 0x1F600000>; + reg = <0x00a00000 0x1f600000>; }; }; }; -- cgit v1.2.3 From ae774090b8e65e5274314718a3865da84f72f85b Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sun, 4 May 2014 01:11:37 +0100 Subject: ARM: dts: Only build OMAP dtb if associated SoC is built With ARCH_OMAP2PLUS being separated out into OMAP2/3/4/5 etc all the TI device tree blobs are built no matter the combination of SoCs that are enabled. This often causes a bunch of irrelevant .dts to be built on a multi platform kernel, this enables the building of just the ones relevant to the SoCs that are actually enabled. It also orders the dts file alphabetically. This also helps to avoid trivial merge conflicts when adding support for new boards. [tony@atomide.com: updated the order for am335x and am43x, moved am3517 to omap3] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 64 +++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 377b7c364033..6efdd3eea301 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -230,65 +230,65 @@ dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ nspire-tp.dtb \ nspire-clp.dtb -dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ - omap2430-sdp.dtb \ +dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \ omap2420-n800.dtb \ omap2420-n810.dtb \ omap2420-n810-wimax.dtb \ + omap2430-sdp.dtb +dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ + am3517-evm.dtb \ + am3517_mt_ventoux.dtb \ omap3430-sdp.dtb \ omap3-beagle.dtb \ + omap3-beagle-xm.dtb \ + omap3-beagle-xm-ab.dtb \ omap3-cm-t3517.dtb \ - omap3-sbc-t3517.dtb \ omap3-cm-t3530.dtb \ - omap3-sbc-t3530.dtb \ omap3-cm-t3730.dtb \ - omap3-sbc-t3730.dtb \ omap3-devkit8000.dtb \ - omap3-beagle-xm.dtb \ - omap3-beagle-xm-ab.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ + omap3-gta04.dtb \ + omap3-igep0020.dtb \ + omap3-igep0030.dtb \ omap3-ldp.dtb \ + omap3-lilly-dbb056.dtb \ omap3-n900.dtb \ omap3-n9.dtb \ omap3-n950.dtb \ omap3-overo-alto35.dtb \ - omap3-overo-storm-alto35.dtb \ omap3-overo-chestnut43.dtb \ - omap3-overo-storm-chestnut43.dtb \ omap3-overo-gallop43.dtb \ - omap3-overo-storm-gallop43.dtb \ omap3-overo-palo43.dtb \ + omap3-overo-storm-alto35.dtb \ + omap3-overo-storm-chestnut43.dtb \ + omap3-overo-storm-gallop43.dtb \ omap3-overo-storm-palo43.dtb \ - omap3-overo-summit.dtb \ omap3-overo-storm-summit.dtb \ - omap3-overo-tobi.dtb \ omap3-overo-storm-tobi.dtb \ - omap3-gta04.dtb \ - omap3-igep0020.dtb \ - omap3-igep0030.dtb \ - omap3-lilly-dbb056.dtb \ - omap3-zoom3.dtb \ - omap4-duovero-parlor.dtb \ + omap3-overo-summit.dtb \ + omap3-overo-tobi.dtb \ + omap3-sbc-t3517.dtb \ + omap3-sbc-t3530.dtb \ + omap3-sbc-t3730.dtb \ + omap3-zoom3.dtb +dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ + am335x-bone.dtb \ + am335x-boneblack.dtb \ + am335x-evm.dtb \ + am335x-evmsk.dtb \ + am335x-nano.dtb +dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ - omap4-var-som.dtb \ omap4-sdp.dtb \ omap4-sdp-es23plus.dtb \ - omap5-uevm.dtb \ - am335x-evm.dtb \ - am335x-evmsk.dtb \ - am335x-bone.dtb \ - am335x-boneblack.dtb \ - am335x-nano.dtb \ - am335x-base0033.dtb \ - am3517-craneboard.dtb \ - am3517-evm.dtb \ - am3517_mt_ventoux.dtb \ - am43x-epos-evm.dtb \ - am437x-gp-evm.dtb \ - dra7-evm.dtb + omap4-var-som.dtb +dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ + am437x-gp-evm.dtb +dtb-$(CONFIG_SOC_OMAP5) += omap5-uevm.dtb +dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ -- cgit v1.2.3 From 19677e32fe7d6913e07ce80f6f3dc7663ac7fe67 Mon Sep 17 00:00:00 2001 From: Bandan Das Date: Tue, 6 May 2014 02:19:15 -0400 Subject: KVM: nVMX: rearrange get_vmx_mem_address Our common function for vmptr checks (in 2/4) needs to fetch the memory address Signed-off-by: Bandan Das Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 106 ++++++++++++++++++++++++++--------------------------- 1 file changed, 53 insertions(+), 53 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 72b8012991b9..917a15efc45b 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -5791,6 +5791,59 @@ static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer) return HRTIMER_NORESTART; } +/* + * Decode the memory-address operand of a vmx instruction, as recorded on an + * exit caused by such an instruction (run by a guest hypervisor). + * On success, returns 0. When the operand is invalid, returns 1 and throws + * #UD or #GP. + */ +static int get_vmx_mem_address(struct kvm_vcpu *vcpu, + unsigned long exit_qualification, + u32 vmx_instruction_info, gva_t *ret) +{ + /* + * According to Vol. 3B, "Information for VM Exits Due to Instruction + * Execution", on an exit, vmx_instruction_info holds most of the + * addressing components of the operand. Only the displacement part + * is put in exit_qualification (see 3B, "Basic VM-Exit Information"). + * For how an actual address is calculated from all these components, + * refer to Vol. 1, "Operand Addressing". + */ + int scaling = vmx_instruction_info & 3; + int addr_size = (vmx_instruction_info >> 7) & 7; + bool is_reg = vmx_instruction_info & (1u << 10); + int seg_reg = (vmx_instruction_info >> 15) & 7; + int index_reg = (vmx_instruction_info >> 18) & 0xf; + bool index_is_valid = !(vmx_instruction_info & (1u << 22)); + int base_reg = (vmx_instruction_info >> 23) & 0xf; + bool base_is_valid = !(vmx_instruction_info & (1u << 27)); + + if (is_reg) { + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; + } + + /* Addr = segment_base + offset */ + /* offset = base + [index * scale] + displacement */ + *ret = vmx_get_segment_base(vcpu, seg_reg); + if (base_is_valid) + *ret += kvm_register_read(vcpu, base_reg); + if (index_is_valid) + *ret += kvm_register_read(vcpu, index_reg)<> 7) & 7; - bool is_reg = vmx_instruction_info & (1u << 10); - int seg_reg = (vmx_instruction_info >> 15) & 7; - int index_reg = (vmx_instruction_info >> 18) & 0xf; - bool index_is_valid = !(vmx_instruction_info & (1u << 22)); - int base_reg = (vmx_instruction_info >> 23) & 0xf; - bool base_is_valid = !(vmx_instruction_info & (1u << 27)); - - if (is_reg) { - kvm_queue_exception(vcpu, UD_VECTOR); - return 1; - } - - /* Addr = segment_base + offset */ - /* offset = base + [index * scale] + displacement */ - *ret = vmx_get_segment_base(vcpu, seg_reg); - if (base_is_valid) - *ret += kvm_register_read(vcpu, base_reg); - if (index_is_valid) - *ret += kvm_register_read(vcpu, index_reg)< Date: Tue, 6 May 2014 02:19:16 -0400 Subject: KVM: nVMX: additional checks on vmxon region Currently, the vmxon region isn't used in the nested case. However, according to the spec, the vmxon instruction performs additional sanity checks on this region and the associated pointer. Modify emulated vmxon to better adhere to the spec requirements Signed-off-by: Bandan Das Signed-off-by: Paolo Bonzini --- arch/x86/kvm/cpuid.c | 1 + arch/x86/kvm/vmx.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 333b88db22fe..17b42fabc842 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -732,6 +732,7 @@ int cpuid_maxphyaddr(struct kvm_vcpu *vcpu) not_found: return 36; } +EXPORT_SYMBOL_GPL(cpuid_maxphyaddr); /* * If no match is found, check whether we exceed the vCPU's limit diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 917a15efc45b..0f7934767a2f 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -354,6 +354,7 @@ struct vmcs02_list { struct nested_vmx { /* Has the level1 guest done vmxon? */ bool vmxon; + gpa_t vmxon_ptr; /* The guest-physical address of the current VMCS L1 keeps for L2 */ gpa_t current_vmptr; @@ -5844,6 +5845,68 @@ static int get_vmx_mem_address(struct kvm_vcpu *vcpu, return 0; } +/* + * This function performs the various checks including + * - if it's 4KB aligned + * - No bits beyond the physical address width are set + * - Returns 0 on success or else 1 + */ +static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason) +{ + gva_t gva; + gpa_t vmptr; + struct x86_exception e; + struct page *page; + struct vcpu_vmx *vmx = to_vmx(vcpu); + int maxphyaddr = cpuid_maxphyaddr(vcpu); + + if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), + vmcs_read32(VMX_INSTRUCTION_INFO), &gva)) + return 1; + + if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, + sizeof(vmptr), &e)) { + kvm_inject_page_fault(vcpu, &e); + return 1; + } + + switch (exit_reason) { + case EXIT_REASON_VMON: + /* + * SDM 3: 24.11.5 + * The first 4 bytes of VMXON region contain the supported + * VMCS revision identifier + * + * Note - IA32_VMX_BASIC[48] will never be 1 + * for the nested case; + * which replaces physical address width with 32 + * + */ + if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) { + nested_vmx_failInvalid(vcpu); + skip_emulated_instruction(vcpu); + return 1; + } + + page = nested_get_page(vcpu, vmptr); + if (page == NULL || + *(u32 *)kmap(page) != VMCS12_REVISION) { + nested_vmx_failInvalid(vcpu); + kunmap(page); + skip_emulated_instruction(vcpu); + return 1; + } + kunmap(page); + vmx->nested.vmxon_ptr = vmptr; + break; + + default: + return 1; /* shouldn't happen */ + } + + return 0; +} + /* * Emulate the VMXON instruction. * Currently, we just remember that VMX is active, and do not save or even @@ -5882,6 +5945,10 @@ static int handle_vmon(struct kvm_vcpu *vcpu) kvm_inject_gp(vcpu, 0); return 1; } + + if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON)) + return 1; + if (vmx->nested.vmxon) { nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION); skip_emulated_instruction(vcpu); -- cgit v1.2.3 From 96ec146330d18a938b4773be8d6dd1f93399507c Mon Sep 17 00:00:00 2001 From: Bandan Das Date: Tue, 6 May 2014 02:19:17 -0400 Subject: KVM: nVMX: fail on invalid vmclear/vmptrld pointer The spec mandates that if the vmptrld or vmclear address is equal to the vmxon region pointer, the instruction should fail with error "VMPTRLD with VMXON pointer" or "VMCLEAR with VMXON pointer" Signed-off-by: Bandan Das Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 0f7934767a2f..1d7e7279f1b4 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -6100,6 +6100,12 @@ static int handle_vmclear(struct kvm_vcpu *vcpu) return 1; } + if (vmptr == vmx->nested.vmxon_ptr) { + nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); + skip_emulated_instruction(vcpu); + return 1; + } + if (vmptr == vmx->nested.current_vmptr) { nested_release_vmcs12(vmx); vmx->nested.current_vmptr = -1ull; @@ -6443,6 +6449,12 @@ static int handle_vmptrld(struct kvm_vcpu *vcpu) return 1; } + if (vmptr == vmx->nested.vmxon_ptr) { + nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); + skip_emulated_instruction(vcpu); + return 1; + } + if (vmx->nested.current_vmptr != vmptr) { struct vmcs12 *new_vmcs12; struct page *page; -- cgit v1.2.3 From 4291b58885f5af560488a5b9667ca6930b9fdc3d Mon Sep 17 00:00:00 2001 From: Bandan Das Date: Tue, 6 May 2014 02:19:18 -0400 Subject: KVM: nVMX: move vmclear and vmptrld pre-checks to nested_vmx_check_vmptr Some checks are common to all, and moreover, according to the spec, the check for whether any bits beyond the physical address width are set are also applicable to all of them Signed-off-by: Bandan Das Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 83 ++++++++++++++++++++++++------------------------------ 1 file changed, 37 insertions(+), 46 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 1d7e7279f1b4..a5fd47e4abfc 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -5850,8 +5850,10 @@ static int get_vmx_mem_address(struct kvm_vcpu *vcpu, * - if it's 4KB aligned * - No bits beyond the physical address width are set * - Returns 0 on success or else 1 + * (Intel SDM Section 30.3) */ -static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason) +static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason, + gpa_t *vmpointer) { gva_t gva; gpa_t vmptr; @@ -5899,11 +5901,42 @@ static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason) kunmap(page); vmx->nested.vmxon_ptr = vmptr; break; + case EXIT_REASON_VMCLEAR: + if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) { + nested_vmx_failValid(vcpu, + VMXERR_VMCLEAR_INVALID_ADDRESS); + skip_emulated_instruction(vcpu); + return 1; + } + if (vmptr == vmx->nested.vmxon_ptr) { + nested_vmx_failValid(vcpu, + VMXERR_VMCLEAR_VMXON_POINTER); + skip_emulated_instruction(vcpu); + return 1; + } + break; + case EXIT_REASON_VMPTRLD: + if (!IS_ALIGNED(vmptr, PAGE_SIZE) || (vmptr >> maxphyaddr)) { + nested_vmx_failValid(vcpu, + VMXERR_VMPTRLD_INVALID_ADDRESS); + skip_emulated_instruction(vcpu); + return 1; + } + + if (vmptr == vmx->nested.vmxon_ptr) { + nested_vmx_failValid(vcpu, + VMXERR_VMCLEAR_VMXON_POINTER); + skip_emulated_instruction(vcpu); + return 1; + } + break; default: return 1; /* shouldn't happen */ } + if (vmpointer) + *vmpointer = vmptr; return 0; } @@ -5946,7 +5979,7 @@ static int handle_vmon(struct kvm_vcpu *vcpu) return 1; } - if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON)) + if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL)) return 1; if (vmx->nested.vmxon) { @@ -6075,37 +6108,16 @@ static int handle_vmoff(struct kvm_vcpu *vcpu) static int handle_vmclear(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); - gva_t gva; gpa_t vmptr; struct vmcs12 *vmcs12; struct page *page; - struct x86_exception e; if (!nested_vmx_check_permission(vcpu)) return 1; - if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), - vmcs_read32(VMX_INSTRUCTION_INFO), &gva)) + if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr)) return 1; - if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, - sizeof(vmptr), &e)) { - kvm_inject_page_fault(vcpu, &e); - return 1; - } - - if (!IS_ALIGNED(vmptr, PAGE_SIZE)) { - nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS); - skip_emulated_instruction(vcpu); - return 1; - } - - if (vmptr == vmx->nested.vmxon_ptr) { - nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); - skip_emulated_instruction(vcpu); - return 1; - } - if (vmptr == vmx->nested.current_vmptr) { nested_release_vmcs12(vmx); vmx->nested.current_vmptr = -1ull; @@ -6425,35 +6437,14 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu) static int handle_vmptrld(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx = to_vmx(vcpu); - gva_t gva; gpa_t vmptr; - struct x86_exception e; u32 exec_control; if (!nested_vmx_check_permission(vcpu)) return 1; - if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), - vmcs_read32(VMX_INSTRUCTION_INFO), &gva)) - return 1; - - if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr, - sizeof(vmptr), &e)) { - kvm_inject_page_fault(vcpu, &e); - return 1; - } - - if (!IS_ALIGNED(vmptr, PAGE_SIZE)) { - nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS); - skip_emulated_instruction(vcpu); + if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr)) return 1; - } - - if (vmptr == vmx->nested.vmxon_ptr) { - nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER); - skip_emulated_instruction(vcpu); - return 1; - } if (vmx->nested.current_vmptr != vmptr) { struct vmcs12 *new_vmcs12; -- cgit v1.2.3 From 2be8f4a66d2d85338ab01048f28f2ab3c08991de Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 28 Apr 2014 12:10:26 -0600 Subject: ARM: tegra: add SD wp-gpios to Venice2 DT Venice2 can detect write-protect on the SD card. Add the required DT entries to allow this. Signed-off-by: Stephen Warren [swarren: fixed GPIO polarity per Thierry's testing] Tested-by: Thierry Reding --- arch/arm/boot/dts/tegra124-venice2.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 84a6ec039e1d..f0bb84244025 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -943,6 +943,7 @@ sdhci@0,700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; status = "okay"; bus-width = <4>; vqmmc-supply = <&vddio_sdmmc3>; -- cgit v1.2.3 From eac1cd3bd6a619e842e7a58bc0845d222627e9ed Mon Sep 17 00:00:00 2001 From: George Cherian Date: Wed, 19 Mar 2014 15:40:00 +0530 Subject: ARM: dts: am43xx clock data Add USB and USB PHY reference clock data Signed-off-by: George Cherian Acked-by: Roger Quadros Acked-by: Felipe Balbi [tony@atomide.com: tabified] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43xx-clocks.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 142009cc9332..775d5b103992 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -653,4 +653,36 @@ clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; + + usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a40>; + }; + + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&usbphy_32khz_clkmux>; + ti,bit-shift = <8>; + reg = <0x2a48>; + }; + + usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x8a60>; + }; + + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_clkdcoldo>; + ti,bit-shift = <8>; + reg = <0x8a68>; + }; }; -- cgit v1.2.3 From a0ae47ea3e1b6fac920762b8949cb7fd7b982e32 Mon Sep 17 00:00:00 2001 From: George Cherian Date: Wed, 19 Mar 2014 15:40:01 +0530 Subject: ARM: dts: AM4372: Add USB nodes Add nodes for 2 instances each of - ocp2scp - USB PHY control module - USB PHY - dwc3_omap - USB for AM43xx. Signed-off-by: George Cherian Acked-by: Roger Quadros Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 94 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d1f8707ff1df..957ecfd84ef7 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -735,6 +735,100 @@ #size-cells = <1>; status = "disabled"; }; + + am43xx_control_usb2phy1: control-phy@44e10620 { + compatible = "ti,control-phy-usb2-am437"; + reg = <0x44e10620 0x4>; + reg-names = "power"; + }; + + am43xx_control_usb2phy2: control-phy@0x44e10628 { + compatible = "ti,control-phy-usb2-am437"; + reg = <0x44e10628 0x4>; + reg-names = "power"; + }; + + ocp2scp0: ocp2scp@483a8000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp0"; + + usb2_phy1: phy@483a8000 { + compatible = "ti,am437x-usb2"; + reg = <0x483a8000 0x8000>; + ctrl-module = <&am43xx_control_usb2phy1>; + clocks = <&usb_phy0_always_on_clk32k>, + <&usb_otg_ss0_refclk960m>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + ocp2scp1: ocp2scp@483e8000 { + compatible = "ti,omap-ocp2scp"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "ocp2scp1"; + + usb2_phy2: phy@483e8000 { + compatible = "ti,am437x-usb2"; + reg = <0x483e8000 0x8000>; + ctrl-module = <&am43xx_control_usb2phy2>; + clocks = <&usb_phy1_always_on_clk32k>, + <&usb_otg_ss1_refclk960m>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + dwc3_1: omap_dwc3@48380000 { + compatible = "ti,am437x-dwc3"; + ti,hwmods = "usb_otg_ss0"; + reg = <0x48380000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges; + + usb1: usb@48390000 { + compatible = "synopsys,dwc3"; + reg = <0x48390000 0x17000>; + interrupts = ; + phys = <&usb2_phy1>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + }; + }; + + dwc3_2: omap_dwc3@483c0000 { + compatible = "ti,am437x-dwc3"; + ti,hwmods = "usb_otg_ss1"; + reg = <0x483c0000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <1>; + ranges; + + usb2: usb@483d0000 { + compatible = "synopsys,dwc3"; + reg = <0x483d0000 0x17000>; + interrupts = ; + phys = <&usb2_phy2>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + status = "disabled"; + }; + }; }; }; -- cgit v1.2.3 From b5820d3a2c2aa10870da81c08294956ae2276309 Mon Sep 17 00:00:00 2001 From: George Cherian Date: Wed, 19 Mar 2014 15:40:02 +0530 Subject: ARM: dts: am437x-gp-evm: Enable USB Enable - USB PHY - USB for am437x-gp-evm Signed-off-by: George Cherian Acked-by: Roger Quadros Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index df8798e8bd25..9e57538bd661 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -125,3 +125,21 @@ pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; }; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; -- cgit v1.2.3 From 61d5924fa73e08c122a016a66322890938f46559 Mon Sep 17 00:00:00 2001 From: George Cherian Date: Wed, 19 Mar 2014 15:40:03 +0530 Subject: ARM: dts: am43x-epos-evm: Enable USB Enable - USB PHY - USB for am43x-epos-evm Signed-off-by: George Cherian Acked-by: Roger Quadros Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 167dbc8494de..1a4946a76ea2 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -367,3 +367,21 @@ pinctrl-0 = <&spi1_pins>; status = "okay"; }; + +&usb2_phy1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + status = "okay"; +}; -- cgit v1.2.3 From c1ad22069c20ade981235d727c151094ca78f30c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 13 Mar 2014 22:59:55 +0100 Subject: ARM: dts: omap3-n900: Add WL1251 support Add device tree support for the wireless chip built into the Nokia N900. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 1a57b61f5e24..0a14a6baaddd 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -130,6 +130,15 @@ >; }; + mcspi4_pins: pinmux_mcspi4_pins { + pinctrl-single,pins = < + 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ + 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ + 0x160 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ + 0x166 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ @@ -173,6 +182,13 @@ 0x0da (PIN_OUTPUT | MUX_MODE1) /* dss_data23.sdi_clkn */ >; }; + + wl1251_pins: pinmux_wl1251 { + pinctrl-single,pins = < + 0x0ce (PIN_OUTPUT | MUX_MODE4) /* gpio 87 => wl1251 enable */ + 0x05a (PIN_INPUT | MUX_MODE4) /* gpio 42 => wl1251 irq */ + >; + }; }; &i2c1 { @@ -604,6 +620,30 @@ }; }; +&mcspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi4_pins>; + + wl1251@0 { + pinctrl-names = "default"; + pinctrl-0 = <&wl1251_pins>; + + vio-supply = <&vio>; + + compatible = "ti,wl1251"; + reg = <0>; + spi-max-frequency = <48000000>; + + spi-cpol; + spi-cpha; + + ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */ + + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */ + }; +}; + &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; -- cgit v1.2.3 From b36c8ac9a9016dcf047a48c3072e12247a75e36a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 19 Mar 2014 00:13:46 +0100 Subject: ARM: dts: twl4030: Add madc Add madc node to twl4030, so that board DTS files can simply reference the A/D converter. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/twl4030.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi index 86cfc7d15ca7..36ae9160b558 100644 --- a/arch/arm/boot/dts/twl4030.dtsi +++ b/arch/arm/boot/dts/twl4030.dtsi @@ -152,4 +152,10 @@ keypad,num-rows = <8>; keypad,num-columns = <8>; }; + + twl_madc: madc { + compatible = "ti,twl4030-madc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; }; -- cgit v1.2.3 From f7d0f2a08567222205a8b5449b5eac90b94f8b27 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 28 Apr 2014 16:07:27 +0200 Subject: ARM: dts: omap3-n900: Add sound support This patch adds support for the Nokia N900's sound system. Signed-off-by: Sebastian Reichel Reviewed-by: Mark Brown Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 0a14a6baaddd..a8292de8f22b 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -90,6 +90,19 @@ }; }; }; + + sound: n900-audio { + compatible = "nokia,n900-audio"; + + nokia,cpu-dai = <&mcbsp2>; + nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>; + nokia,headphone-amplifier = <&tpa6130a2>; + + tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */ + jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */ + eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ + speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; + }; }; &omap3_pmx_core { @@ -702,3 +715,7 @@ }; }; }; + +&mcbsp2 { + status = "ok"; +}; -- cgit v1.2.3 From 79f7f37a569e80dce060fa54f638b7e66384cf42 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Sun, 4 May 2014 03:23:08 +0300 Subject: ARM: dts: n950: Add missing regulator definitions The N950/N9 uses two additional regulators from the twl 4030 for CSI-2 receiver (vaux2) and cameras (vaux3). Signed-off-by: Sakari Ailus Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n950-n9.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 5c26c184f2c1..70addcba37c5 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -67,6 +67,20 @@ ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ }; +/* CSI-2 receiver */ +&vaux2 { + regulator-name = "vaux2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +/* Cameras */ +&vaux3 { + regulator-name = "vaux3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + &i2c2 { clock-frequency = <400000>; }; -- cgit v1.2.3 From 69a126cbed4b932bcdf363f62b6646a5e8d17435 Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Wed, 19 Mar 2014 10:45:53 -0500 Subject: ARM: dts: OMAP5: add pmu node Expose the PMU on OMAP5. Tested with perf on OMAP5 uEVM. Signed-off-by: Nathan Lynch Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index f8c9855ce587..ae144db8908b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -82,6 +82,12 @@ ; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + ; + }; + gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; -- cgit v1.2.3 From 9f642b5c349a235d2f551267ddaaab2485a5e5c3 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Mon, 28 Apr 2014 14:41:44 +0300 Subject: ARM: dts: sbc-t54: add support for sbc-t54 with cm-t54 Add support for CM-T54 CoM and SBC-T54 board: http://compulab.co.il/products/computer-on-modules/cm-t54/ http://compulab.co.il/products/sbcs/sbc-t54/ SBC-T54 is a single board computer based on OMAP5432 CPU. It is implemented with a CM-T54 CoM providing most of the functions, and SB-T54 carrier board providing connectors and several additional functions. Added basic support for: * PMIC * LED * MMC/SD * eMMC * USB * I2C1/4 * SB-T54 and CM-T54 EEPROMs * RTC Signed-off-by: Dmitry Lifshitz [tony@atomide.com: updated for Makefile sorting] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 4 +- arch/arm/boot/dts/omap5-cm-t54.dts | 362 ++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/omap5-sbc-t54.dts | 51 +++++ 3 files changed, 416 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/omap5-cm-t54.dts create mode 100644 arch/arm/boot/dts/omap5-sbc-t54.dts (limited to 'arch') diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6efdd3eea301..500cf25f8c84 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -287,7 +287,9 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-var-som.dtb dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ am437x-gp-evm.dtb -dtb-$(CONFIG_SOC_OMAP5) += omap5-uevm.dtb +dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ + omap5-sbc-t54.dtb \ + omap5-uevm.dtb dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts new file mode 100644 index 000000000000..e3018656ffd2 --- /dev/null +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -0,0 +1,362 @@ +/* + * Support for CompuLab CM-T54 + */ +/dts-v1/; + +#include "omap5.dtsi" +#include +#include + +/ { + model = "CompuLab CM-T54"; + compatible = "compulab,omap5-cm-t54", "ti,omap5"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x7F000000>; /* 2048 MB */ + }; + + vmmcsd_fixed: fixed-regulator-mmcsd { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */ + }; + + /* HS USB Host PHY on PORT 3 */ + hsusb3_phy: hsusb3_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */ + }; + + leds { + compatible = "gpio-leds"; + led@1 { + label = "Heartbeat"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; +}; + +&omap5_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &led_gpio_pins + &usbhost_pins + >; + + led_gpio_pins: pinmux_led_gpio_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x28b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x29f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */ + OMAP5_CORE_IOPAD(0x29f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x29e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ + OMAP5_CORE_IOPAD(0x29e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */ + OMAP5_CORE_IOPAD(0x29e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */ + OMAP5_CORE_IOPAD(0x29e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */ + OMAP5_CORE_IOPAD(0x29ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */ + OMAP5_CORE_IOPAD(0x29ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x2840, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */ + OMAP5_CORE_IOPAD(0x2842, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */ + OMAP5_CORE_IOPAD(0x2844, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */ + OMAP5_CORE_IOPAD(0x2846, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */ + OMAP5_CORE_IOPAD(0x2848, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */ + OMAP5_CORE_IOPAD(0x284a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */ + OMAP5_CORE_IOPAD(0x284c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */ + OMAP5_CORE_IOPAD(0x284e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */ + OMAP5_CORE_IOPAD(0x2850, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */ + OMAP5_CORE_IOPAD(0x2852, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */ + >; + }; + + usbhost_pins: pinmux_usbhost_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x28c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ + OMAP5_CORE_IOPAD(0x28c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ + + OMAP5_CORE_IOPAD(0x29dc, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ + OMAP5_CORE_IOPAD(0x29de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ + + OMAP5_CORE_IOPAD(0x28a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */ + OMAP5_CORE_IOPAD(0x28b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&ldo9_reg>; + bus-width = <4>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + palmas: palmas@48 { + compatible = "ti,palmas"; + interrupts = ; /* IRQ_SYS_1N */ + interrupt-parent = <&gic>; + reg = <0x48>; + interrupt-controller; + #interrupt-cells = <2>; + ti,system-power-controller; + + extcon_usb3: palmas_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + ti,enable-id-detection; + ti,wakeup; + }; + + rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&palmas>; + interrupts = <8 IRQ_TYPE_NONE>; + }; + + palmas_pmic { + compatible = "ti,palmas-pmic"; + interrupt-parent = <&palmas>; + interrupts = <14 IRQ_TYPE_NONE>; + interrupt-name = "short-irq"; + + ti,ldo6-vibrator; + + regulators { + smps123_reg: smps123 { + /* VDD_OPP_MPU */ + regulator-name = "smps123"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_OPP_MM */ + regulator-name = "smps45"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_DDR3 - over VDD_SMPS6 */ + regulator-name = "smps6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ + regulator-name = "smps7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* VDD_OPP_CORE */ + regulator-name = "smps8"; + regulator-min-microvolt = < 600000>; + regulator-max-microvolt = <1310000>; + regulator-always-on; + regulator-boot-on; + }; + + smps9_reg: smps9 { + /* VDDA_2v1_AUD over VDD_2v1 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + ti,smps-range = <0x80>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out2_reg: smps10_out2 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + smps10_out1_reg: smps10_out1 { + /* VBUS_5V_OTG */ + regulator-name = "smps10_out1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ldo1_reg: ldo1 { + /* VDDAPHY_CAM: vdda_csiport */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2_reg: ldo2 { + /* VDD_3V3_WLAN */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VCC_1V5_AUD */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDAPHY_DISP: vdda_dsiport/hdmi */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PHY: usb/sata/hdmi.. */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo6_reg: ldo6 { + /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo7_reg: ldo7 { + /* VDD_VPP: vpp1 */ + regulator-name = "ldo7"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + /* Only for efuse reprograming! */ + status = "disabled"; + }; + + ldo8_reg: ldo8 { + /* VDD_3v0: Does not go anywhere */ + regulator-name = "ldo8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + /* Unused */ + status = "disabled"; + }; + + ldo9_reg: ldo9 { + /* VCC_DV_SDIO: vdds_sdcard */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3250000>; + regulator-always-on; + regulator-boot-on; + }; + + regen3_reg: regen3 { + /* REGEN3 controls LDO9 supply to card */ + regulator-name = "regen3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; +}; + +&usbhshost { + port2-mode = "ehci-hsic"; + port3-mode = "ehci-hsic"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy &hsusb3_phy>; +}; + +&cpu0 { + cpu0-supply = <&smps123_reg>; +}; diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts new file mode 100644 index 000000000000..9fd0b3c3abac --- /dev/null +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -0,0 +1,51 @@ +/* + * Suppport for CompuLab SBC-T54 with CM-T54 + */ + +#include "omap5-cm-t54.dts" + +/ { + model = "CompuLab SBC-T54 with CM-T54"; + compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; +}; + +&omap5_pmx_core { + i2c4_pins: pinmux_i2c4_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x28f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP5_CORE_IOPAD(0x28fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc1_aux_pins: pinmux_mmc1_aux_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x2974, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ + OMAP5_CORE_IOPAD(0x2976, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc1_pins + &mmc1_aux_pins + >; + cd-inverted; + wp-inverted; + cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */ + wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */ +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; -- cgit v1.2.3 From 4a996d187ed970a0d2116501edb6e744bce78f29 Mon Sep 17 00:00:00 2001 From: Dmitry Lifshitz Date: Mon, 28 Apr 2014 14:41:45 +0300 Subject: ARM: dts: cm-t54: add WiFi/BT support Add support of AW-NH387 (mwifiex) WiFi/BT chip connected to MMC3. Signed-off-by: Dmitry Lifshitz Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-cm-t54.dts | 53 +++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index e3018656ffd2..8fec6a49b688 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -23,6 +23,28 @@ regulator-max-microvolt = <3300000>; }; + vwlan_pdn_fixed: fixed-regulator-vwlan-pdn { + compatible = "regulator-fixed"; + regulator-name = "vwlan_pdn_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ldo2_reg>; + gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* gpio4_109 */ + startup-delay-us = <1000>; + enable-active-high; + }; + + vwlan_fixed: fixed-regulator-vwlan { + compatible = "regulator-fixed"; + regulator-name = "vwlan_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vwlan_pdn_fixed>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio4_110 */ + startup-delay-us = <1000>; + enable-active-high; + }; + /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; @@ -92,6 +114,24 @@ >; }; + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x29a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */ + OMAP5_CORE_IOPAD(0x29a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */ + OMAP5_CORE_IOPAD(0x29a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */ + OMAP5_CORE_IOPAD(0x29aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */ + OMAP5_CORE_IOPAD(0x29ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */ + OMAP5_CORE_IOPAD(0x29ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */ + >; + }; + + wlan_gpios_pins: pinmux_wlan_gpios_pins { + pinctrl-single,pins = < + OMAP5_CORE_IOPAD(0x299c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ + OMAP5_CORE_IOPAD(0x299e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ + >; + }; + usbhost_pins: pinmux_usbhost_pins { pinctrl-single,pins = < OMAP5_CORE_IOPAD(0x28c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ @@ -121,6 +161,17 @@ ti,non-removable; }; +&mmc3 { + pinctrl-names = "default"; + pinctrl-0 = < + &mmc3_pins + &wlan_gpios_pins + >; + vmmc-supply = <&vwlan_fixed>; + bus-width = <4>; + ti,non-removable; +}; + &mmc4 { status = "disabled"; }; @@ -255,7 +306,7 @@ regulator-name = "ldo2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; + startup-delay-us = <1000>; }; ldo3_reg: ldo3 { -- cgit v1.2.3 From 2a1a5043fd3711b8aad6f485a0a6ae17c76e1693 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Mon, 28 Apr 2014 19:12:30 +0530 Subject: ARM: dts: am43x-epos: Add qspi device This patch adds qspi nodes for am43xx SOC devices. Signed-off-by: Sourav Poddar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 11 +++++++ arch/arm/boot/dts/am43x-epos-evm.dts | 63 ++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 957ecfd84ef7..ac37ac9cab31 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -829,6 +829,17 @@ status = "disabled"; }; }; + + qspi: qspi@47900000 { + compatible = "ti,am4372-qspi"; + reg = <0x47900000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "qspi"; + interrupts = <0 138 0x4>; + num-cs = <4>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 1a4946a76ea2..ce5fc3909771 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -138,6 +138,17 @@ 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ >; }; + + qspi1_default: qspi1_default { + pinctrl-single,pins = < + 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) + 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) + 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) + 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) + 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) + 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; }; matrix_keypad: matrix_keypad@0 { @@ -385,3 +396,55 @@ dr_mode = "host"; status = "okay"; }; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_default>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "mx66l51235l"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpol; + spi-cpha; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first 512KiB + * for a valid file to boot(XIP). + */ + partition@0 { + label = "QSPI.U_BOOT"; + reg = <0x00000000 0x000080000>; + }; + partition@1 { + label = "QSPI.U_BOOT.backup"; + reg = <0x00080000 0x00080000>; + }; + partition@2 { + label = "QSPI.U-BOOT-SPL_OS"; + reg = <0x00100000 0x00010000>; + }; + partition@3 { + label = "QSPI.U_BOOT_ENV"; + reg = <0x00110000 0x00010000>; + }; + partition@4 { + label = "QSPI.U-BOOT-ENV.backup"; + reg = <0x00120000 0x00010000>; + }; + partition@5 { + label = "QSPI.KERNEL"; + reg = <0x00130000 0x0800000>; + }; + partition@6 { + label = "QSPI.FILESYSTEM"; + reg = <0x00930000 0x36D0000>; + }; + }; +}; -- cgit v1.2.3 From a31451ce6a9aa3329ab40d9fa209806f9aadb847 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 29 Apr 2014 16:35:09 +0530 Subject: ARM: dts: dra7-evm: Remove the wrong and undocumented compatible "ti,dra752" is neither documented nor correct, since the device is actually a dra742 device as rightly documented in dt bindings. Signed-off-by: Rajendra Nayak Cc: devicetree@vger.kernel.org Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 5babba0a3a75..78074291fdca 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -11,7 +11,7 @@ / { model = "TI DRA7"; - compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7"; + compatible = "ti,dra7-evm", "ti,dra7"; memory { device_type = "memory"; -- cgit v1.2.3 From 38b248db60e32734417534b57f9ab687c445113a Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 29 Apr 2014 16:35:10 +0530 Subject: ARM: dts: Add support for DRA72x family of devices DRA722 is part of DRA72x family which are single core cortex A15 devices with most infrastructure IPs otherwise same as whats on the DRA74x family. So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively. Also add a minimal dra72-evm dts file. Signed-off-by: Rajendra Nayak Cc: linux-doc@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Arnd Bergmann [tony@atomide.com: updated for Makefile sorting] Signed-off-by: Tony Lindgren --- .../devicetree/bindings/arm/omap/omap.txt | 12 +++++-- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/dra7-evm.dts | 6 ++-- arch/arm/boot/dts/dra7.dtsi | 27 -------------- arch/arm/boot/dts/dra72-evm.dts | 24 +++++++++++++ arch/arm/boot/dts/dra72x.dtsi | 25 +++++++++++++ arch/arm/boot/dts/dra74x.dtsi | 41 ++++++++++++++++++++++ 7 files changed, 104 insertions(+), 34 deletions(-) create mode 100644 arch/arm/boot/dts/dra72-evm.dts create mode 100644 arch/arm/boot/dts/dra72x.dtsi create mode 100644 arch/arm/boot/dts/dra74x.dtsi (limited to 'arch') diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 36ede19a1630..3bad25965133 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -80,7 +80,10 @@ SoCs: compatible = "ti,omap5432", "ti,omap5" - DRA742 - compatible = "ti,dra7xx", "ti,dra7" + compatible = "ti,dra742", "ti,dra74", "ti,dra7" + +- DRA722 + compatible = "ti,dra722", "ti,dra72", "ti,dra7" - AM4372 compatible = "ti,am4372", "ti,am43" @@ -120,5 +123,8 @@ Boards: - AM437x GP EVM compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" -- DRA7 EVM: Software Developement Board for DRA7XX - compatible = "ti,dra7-evm", "ti,dra7" +- DRA742 EVM: Software Developement Board for DRA742 + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" + +- DRA722 EVM: Software Development Board for DRA722 + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 500cf25f8c84..53d995f4ce12 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -290,7 +290,8 @@ dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ omap5-sbc-t54.dtb \ omap5-uevm.dtb -dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb +dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ + dra72-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 78074291fdca..39b718adfbec 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -7,11 +7,11 @@ */ /dts-v1/; -#include "dra7.dtsi" +#include "dra74x.dtsi" / { - model = "TI DRA7"; - compatible = "ti,dra7-evm", "ti,dra7"; + model = "TI DRA742"; + compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; memory { device_type = "memory"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 149b55099935..a4f9f3927497 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -33,33 +33,6 @@ serial5 = &uart6; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - timer { compatible = "arm,armv7-timer"; interrupts = , diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts new file mode 100644 index 000000000000..514702348818 --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" + +/ { + model = "TI DRA722"; + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1024 MB */ + }; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi new file mode 100644 index 000000000000..f1ec22f6ebf4 --- /dev/null +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra722", "ti,dra72", "ti,dra7"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi new file mode 100644 index 000000000000..a4e8bb9f95c0 --- /dev/null +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * Based on "omap4.dtsi" + */ + +#include "dra7.dtsi" + +/ { + compatible = "ti,dra742", "ti,dra74", "ti,dra7"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + }; +}; -- cgit v1.2.3 From 1509e24be246e7722e59df4308aee48a50321d75 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 29 Apr 2014 16:35:11 +0530 Subject: ARM: OMAP2+: Replace all __initdata with __initconst for const init Use of const init definition must use __initconst so replace all such instances where __initdata is used. Signed-off-by: Rajendra Nayak Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-generic.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index b8920b6bc104..90dbfdf4c880 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -43,7 +43,7 @@ static void __init omap_generic_init(void) } #ifdef CONFIG_SOC_OMAP2420 -static const char *omap242x_boards_compat[] __initdata = { +static const char *omap242x_boards_compat[] __initconst = { "ti,omap2420", NULL, }; @@ -62,7 +62,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP2430 -static const char *omap243x_boards_compat[] __initdata = { +static const char *omap243x_boards_compat[] __initconst = { "ti,omap2430", NULL, }; @@ -81,7 +81,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP3 -static const char *omap3_boards_compat[] __initdata = { +static const char *omap3_boards_compat[] __initconst = { "ti,omap3430", "ti,omap3", NULL, @@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap36xx_boards_compat[] __initdata = { +static const char *omap36xx_boards_compat[] __initconst = { "ti,omap36xx", NULL, }; @@ -118,7 +118,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *omap3_gp_boards_compat[] __initdata = { +static const char *omap3_gp_boards_compat[] __initconst = { "ti,omap3-beagle", "timll,omap3-devkit8000", NULL, @@ -137,7 +137,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)") .restart = omap3xxx_restart, MACHINE_END -static const char *am3517_boards_compat[] __initdata = { +static const char *am3517_boards_compat[] __initconst = { "ti,am3517", NULL, }; @@ -157,7 +157,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM33XX -static const char *am33xx_boards_compat[] __initdata = { +static const char *am33xx_boards_compat[] __initconst = { "ti,am33xx", NULL, }; @@ -177,7 +177,7 @@ MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP4 -static const char *omap4_boards_compat[] __initdata = { +static const char *omap4_boards_compat[] __initconst = { "ti,omap4460", "ti,omap4430", "ti,omap4", @@ -199,7 +199,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_OMAP5 -static const char *omap5_boards_compat[] __initdata = { +static const char *omap5_boards_compat[] __initconst = { "ti,omap5432", "ti,omap5430", "ti,omap5", @@ -221,7 +221,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_AM43XX -static const char *am43_boards_compat[] __initdata = { +static const char *am43_boards_compat[] __initconst = { "ti,am4372", "ti,am43", NULL, @@ -240,7 +240,7 @@ MACHINE_END #endif #ifdef CONFIG_SOC_DRA7XX -static const char *dra7xx_boards_compat[] __initdata = { +static const char *dra7xx_boards_compat[] __initconst = { "ti,dra7xx", "ti,dra7", NULL, -- cgit v1.2.3 From 44e97ff6dc455a74bd76029a02ce6559e846f1c9 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 29 Apr 2014 16:35:12 +0530 Subject: ARM: OMAP2+: Add machine entry for dra72x devices The only difference from the dra74x devices is the missing .smp entry. Signed-off-by: Rajendra Nayak Acked-by: Arnd Bergmann Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-generic.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 90dbfdf4c880..9480997ba616 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -240,13 +240,13 @@ MACHINE_END #endif #ifdef CONFIG_SOC_DRA7XX -static const char *dra7xx_boards_compat[] __initconst = { - "ti,dra7xx", +static const char *dra74x_boards_compat[] __initconst = { + "ti,dra742", "ti,dra7", NULL, }; -DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") +DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") .reserve = omap_reserve, .smp = smp_ops(omap4_smp_ops), .map_io = omap5_map_io, @@ -255,7 +255,24 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, .init_time = omap5_realtime_timer_init, - .dt_compat = dra7xx_boards_compat, + .dt_compat = dra74x_boards_compat, + .restart = omap44xx_restart, +MACHINE_END + +static const char *dra72x_boards_compat[] __initconst = { + "ti,dra722", + NULL, +}; + +DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)") + .reserve = omap_reserve, + .map_io = omap5_map_io, + .init_early = dra7xx_init_early, + .init_late = dra7xx_init_late, + .init_irq = omap_gic_of_init, + .init_machine = omap_generic_init, + .init_time = omap5_realtime_timer_init, + .dt_compat = dra72x_boards_compat, .restart = omap44xx_restart, MACHINE_END #endif -- cgit v1.2.3 From 081df89d8778ddc9f9fe2b727f4bd8379b463a3f Mon Sep 17 00:00:00 2001 From: Guido Martínez Date: Mon, 28 Apr 2014 17:54:32 -0300 Subject: ARM: dts: am335x-bone-common: use phandles for USB and DMA refs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use phandles instead of unit adresses to reference usb and dma nodes. This makes the DT more robust and readable. Signed-off-by: Guido Martínez Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 38 +++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 2e7d932887b5..ded128340913 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -182,31 +182,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &i2c0 { -- cgit v1.2.3 From bd6fdaf765930b3b0db8753961aac95aac1c83bb Mon Sep 17 00:00:00 2001 From: Guido Martínez Date: Mon, 28 Apr 2014 17:54:33 -0300 Subject: ARM: dts: am335x-evm: use phandles for USB and DMA refs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use phandles instead of unit adresses to reference usb and dma nodes. This makes the DT more robust and readable. Signed-off-by: Guido Martínez Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 6028217ace0f..33f7c57439d9 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -330,31 +330,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &i2c1 { -- cgit v1.2.3 From 0f686d206541d15ce320f708d5ff4804b6886189 Mon Sep 17 00:00:00 2001 From: Guido Martínez Date: Mon, 28 Apr 2014 17:54:34 -0300 Subject: ARM: dts: am335x-evmsk: use phandles for USB and DMA refs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use phandles instead of unit adresses to reference usb and dma nodes. This makes the DT more robust and readable. Signed-off-by: Guido Martínez Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index ab238850a7b2..a460c2e6bfce 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -363,31 +363,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; &epwmss2 { -- cgit v1.2.3 From 2cd1de1c2496b2ebc7e6484fd742bcdaaf57f4bb Mon Sep 17 00:00:00 2001 From: Guido Martínez Date: Mon, 28 Apr 2014 17:54:35 -0300 Subject: ARM: dts: am335x-igep0033: use phandles for USB and DMA refs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use phandles instead of unit adresses to reference usb and dma nodes. This makes the DT more robust and readable. Signed-off-by: Guido Martínez Cc: Enric Balletbo i Serra Acked-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-igep0033.dtsi | 38 +++++++++++++++++----------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 9f22c189f636..9c53b506c327 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -200,31 +200,31 @@ &usb { status = "okay"; +}; - control@44e10620 { - status = "okay"; - }; +&usb_ctrl_mod { + status = "okay"; +}; - usb-phy@47401300 { - status = "okay"; - }; +&usb0_phy { + status = "okay"; +}; - usb-phy@47401b00 { - status = "okay"; - }; +&usb1_phy { + status = "okay"; +}; - usb@47401000 { - status = "okay"; - }; +&usb0 { + status = "okay"; +}; - usb@47401800 { - status = "okay"; - dr_mode = "host"; - }; +&usb1 { + status = "okay"; + dr_mode = "host"; +}; - dma-controller@47402000 { - status = "okay"; - }; +&cppi41dma { + status = "okay"; }; #include "tps65910.dtsi" -- cgit v1.2.3 From 6cfcb5be9540074d40c34de78cc624adeea649f8 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Wed, 30 Apr 2014 15:43:24 +0300 Subject: ARM: dts: am43x-epos-evm: Correct Touch controller info Fixup Y resolution and add default pin state. Also update the compatible id. CC: Benoit Cousson CC: Tony Lindgren CC: Mugunthan V N Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index ce5fc3909771..cf8bdf103a48 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -149,6 +149,12 @@ 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) >; }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ + >; + }; }; matrix_keypad: matrix_keypad@0 { @@ -237,7 +243,9 @@ }; pixcir_ts@5c { - compatible = "pixcir,pixcir_ts"; + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; reg = <0x5c>; interrupt-parent = <&gpio1>; interrupts = <17 0>; @@ -245,7 +253,7 @@ attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; x-size = <1024>; - y-size = <768>; + y-size = <600>; }; }; -- cgit v1.2.3 From 0ebc1e2519b752ebac52b26793859ebc570ebc8f Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Wed, 30 Apr 2014 15:43:25 +0300 Subject: ARM: dts: am437x: Add touchscreen support for GP EVM Add touchscreen support for AM437x GP EVM using pixcir touchscreen controller. CC: Benoit Cousson CC: Tony Lindgren Signed-off-by: Sekhar Nori Acked-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 9e57538bd661..c0cc5251fd47 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -81,6 +81,12 @@ 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ >; }; + + pixcir_ts_pins: pixcir_ts_pins { + pinctrl-single,pins = < + 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ + >; + }; }; &i2c0 { @@ -93,6 +99,20 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + pinctrl-names = "default"; + pinctrl-0 = <&pixcir_ts_pins>; + reg = <0x5c>; + interrupt-parent = <&gpio3>; + interrupts = <22 0>; + + attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + + x-size = <1024>; + y-size = <600>; + }; }; &epwmss0 { -- cgit v1.2.3 From b2873bfa7b5d5c3e6ab3e318d910c7dd707706cb Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Mon, 5 May 2014 14:58:28 -0500 Subject: ARM: dts: am437x-gp-evm: Add vtt_fixed regulator The VTT regulator for DDR3 termination on the am437x-gp-evm is controlled by a gpio. It is configured by the bootloader so here we define an always-on, fixed voltage regulator to hold the gpio. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index c0cc5251fd47..2e0c636a7e72 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -27,6 +27,17 @@ enable-active-high; }; + vtt_fixed: fixedregulator-vtt { + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; -- cgit v1.2.3 From 12f0323685f4f1357169432d1ca8a75282f2233f Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Mon, 5 May 2014 14:58:29 -0500 Subject: ARM: dts: am335x-evmsk: Add vtt_fixed regulator The VTT regulator for DDR3 termination on the am335x-evmsk is controlled by a gpio. It is configured by the bootloader so here we define an always-on, fixed voltage regulator to hold the gpio. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index a460c2e6bfce..6f2e529bca25 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -57,6 +57,17 @@ enable-active-high; }; + vtt_fixed: fixedregulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + leds { pinctrl-names = "default"; pinctrl-0 = <&user_leds_s0>; -- cgit v1.2.3 From dc2dd5b8cb03ee3c4754af2442c9426e9948654a Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Tue, 6 May 2014 16:37:24 +0530 Subject: ARM: dts: dra7: Add qspi device These add device tree entry for qspi controller driver on dra7-evm. Signed-off-by: Sourav Poddar Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 80 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/dra7.dtsi | 14 ++++++++ 2 files changed, 94 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 39b718adfbec..5f1f6da17dad 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -93,6 +93,21 @@ 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ >; }; + + qspi1_pins: pinmux_qspi1_pins { + pinctrl-single,pins = < + 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ + 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ + 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ + 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ + 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ + 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ + 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ + 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ + 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ + 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ + >; + }; }; &i2c1 { @@ -273,3 +288,68 @@ &cpu0 { cpu0-supply = <&smps123_reg>; }; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi1_pins>; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00010000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x00150000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x00160000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x00170000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x00970000 0x01690000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a4f9f3927497..37a0595f47ed 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -762,6 +762,20 @@ dma-names = "tx0", "rx0"; status = "disabled"; }; + + qspi: qspi@4b300000 { + compatible = "ti,dra7xxx-qspi"; + reg = <0x4b300000 0x100>; + reg-names = "qspi_base"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "qspi"; + clocks = <&qspi_gfclk_div>; + clock-names = "fck"; + num-cs = <4>; + interrupts = <0 343 0x4>; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 3fdb77174a2c173e0e69f2499b836a0e412f6c4d Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 6 May 2014 15:14:28 +0200 Subject: ARM: dts: omap3-n900: use MATRIX_KEY for keymap Use MATRIX_KEY macro from dt-bindings/input/input.h to make the keyboard matrix human readable. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 103 ++++++++++++++++++++------------------- 1 file changed, 52 insertions(+), 51 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index a8292de8f22b..f9fbb0315808 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "omap34xx-hs.dtsi" +#include / { model = "Nokia N900"; @@ -312,57 +313,57 @@ }; &twl_keypad { - linux,keymap = < 0x00000010 /* KEY_Q */ - 0x00010018 /* KEY_O */ - 0x00020019 /* KEY_P */ - 0x00030033 /* KEY_COMMA */ - 0x0004000e /* KEY_BACKSPACE */ - 0x0006001e /* KEY_A */ - 0x0007001f /* KEY_S */ - - 0x01000011 /* KEY_W */ - 0x01010020 /* KEY_D */ - 0x01020021 /* KEY_F */ - 0x01030022 /* KEY_G */ - 0x01040023 /* KEY_H */ - 0x01050024 /* KEY_J */ - 0x01060025 /* KEY_K */ - 0x01070026 /* KEY_L */ - - 0x02000012 /* KEY_E */ - 0x02010034 /* KEY_DOT */ - 0x02020067 /* KEY_UP */ - 0x0203001c /* KEY_ENTER */ - 0x0205002c /* KEY_Z */ - 0x0206002d /* KEY_X */ - 0x0207002e /* KEY_C */ - 0x02080043 /* KEY_F9 */ - - 0x03000013 /* KEY_R */ - 0x0301002f /* KEY_V */ - 0x03020030 /* KEY_B */ - 0x03030031 /* KEY_N */ - 0x03040032 /* KEY_M */ - 0x03050039 /* KEY_SPACE */ - 0x03060039 /* KEY_SPACE */ - 0x03070069 /* KEY_LEFT */ - - 0x04000014 /* KEY_T */ - 0x0401006c /* KEY_DOWN */ - 0x0402006a /* KEY_RIGHT */ - 0x0404001d /* KEY_LEFTCTRL */ - 0x04050064 /* KEY_RIGHTALT */ - 0x0406002a /* KEY_LEFTSHIFT */ - 0x04080044 /* KEY_F10 */ - - 0x05000015 /* KEY_Y */ - 0x05080057 /* KEY_F11 */ - - 0x06000016 /* KEY_U */ - - 0x07000017 /* KEY_I */ - 0x07010041 /* KEY_F7 */ - 0x07020042 /* KEY_F8 */ + linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q) + MATRIX_KEY(0x00, 0x01, KEY_O) + MATRIX_KEY(0x00, 0x02, KEY_P) + MATRIX_KEY(0x00, 0x03, KEY_COMMA) + MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE) + MATRIX_KEY(0x00, 0x06, KEY_A) + MATRIX_KEY(0x00, 0x07, KEY_S) + + MATRIX_KEY(0x01, 0x00, KEY_W) + MATRIX_KEY(0x01, 0x01, KEY_D) + MATRIX_KEY(0x01, 0x02, KEY_F) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_H) + MATRIX_KEY(0x01, 0x05, KEY_J) + MATRIX_KEY(0x01, 0x06, KEY_K) + MATRIX_KEY(0x01, 0x07, KEY_L) + + MATRIX_KEY(0x02, 0x00, KEY_E) + MATRIX_KEY(0x02, 0x01, KEY_DOT) + MATRIX_KEY(0x02, 0x02, KEY_UP) + MATRIX_KEY(0x02, 0x03, KEY_ENTER) + MATRIX_KEY(0x02, 0x05, KEY_Z) + MATRIX_KEY(0x02, 0x06, KEY_X) + MATRIX_KEY(0x02, 0x07, KEY_C) + MATRIX_KEY(0x02, 0x08, KEY_F9) + + MATRIX_KEY(0x03, 0x00, KEY_R) + MATRIX_KEY(0x03, 0x01, KEY_V) + MATRIX_KEY(0x03, 0x02, KEY_B) + MATRIX_KEY(0x03, 0x03, KEY_N) + MATRIX_KEY(0x03, 0x04, KEY_M) + MATRIX_KEY(0x03, 0x05, KEY_SPACE) + MATRIX_KEY(0x03, 0x06, KEY_SPACE) + MATRIX_KEY(0x03, 0x07, KEY_LEFT) + + MATRIX_KEY(0x04, 0x00, KEY_T) + MATRIX_KEY(0x04, 0x01, KEY_DOWN) + MATRIX_KEY(0x04, 0x02, KEY_RIGHT) + MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL) + MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT) + MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT) + MATRIX_KEY(0x04, 0x08, KEY_F10) + + MATRIX_KEY(0x05, 0x00, KEY_Y) + MATRIX_KEY(0x05, 0x08, KEY_F11) + + MATRIX_KEY(0x06, 0x00, KEY_U) + + MATRIX_KEY(0x07, 0x00, KEY_I) + MATRIX_KEY(0x07, 0x01, KEY_F7) + MATRIX_KEY(0x07, 0x02, KEY_F8) >; }; -- cgit v1.2.3 From 31f0820a6709fd9f4e4208081f949f9036972e06 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:39 -0700 Subject: ARM: dts: Fix omap serial wake-up when booted with device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We've had deeper idle states working on omaps for few years now, but only in the legacy mode. When booted with device tree, the wake-up events did not have a chance to work until commit 3e6cee1786a1 (pinctrl: single: Add support for wake-up interrupts) that recently got merged. In addition to that we also needed commit 79d9701559a9 (of/irq: create interrupts-extended property) and 9ec36cafe43b (of/irq: do irq resolution in platform_get_irq) that are now also merged. So let's fix the wake-up events for some selected omaps so devices booted in device tree mode won't just hang if deeper power states are enabled, and so systems can wake up from suspend to the serial port event. Note that there's no longer need to specify the wake-up bit in the pinctrl settings, the request_irq on the wake-up pin takes care of that. Cc: devicetree@vger.kernel.org Cc: "Benoît Cousson" Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo [tony@atomide.com: updated comments, added board LDP] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-evm-37xx.dts | 9 +++++++++ arch/arm/boot/dts/omap3-ldp.dts | 4 ++++ arch/arm/boot/dts/omap3-n900.dts | 2 ++ arch/arm/boot/dts/omap3.dtsi | 6 +++--- arch/arm/boot/dts/omap4-panda-common.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/omap4-sdp.dts | 6 ++++++ arch/arm/boot/dts/omap4.dtsi | 6 +++--- include/dt-bindings/pinctrl/omap.h | 12 ++++++++++++ 8 files changed, 54 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index 4df68ad3736a..9cba94bed7ad 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -89,7 +89,16 @@ status = "disabled"; }; +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; +}; + &uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 0abe986a4ecc..476ff158ddb3 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -234,6 +234,10 @@ }; }; +&uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; +}; + &usb_otg_hs { pinctrl-names = "default"; pinctrl-0 = <&musb_pins>; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 1a57b61f5e24..656ae403018f 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -618,11 +618,13 @@ }; &uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index acb9019dc437..8a0ce605fdd8 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -267,7 +267,7 @@ uart1: serial@4806a000 { compatible = "ti,omap3-uart"; reg = <0x4806a000 0x2000>; - interrupts = <72>; + interrupts-extended = <&intc 72>; dmas = <&sdma 49 &sdma 50>; dma-names = "tx", "rx"; ti,hwmods = "uart1"; @@ -277,7 +277,7 @@ uart2: serial@4806c000 { compatible = "ti,omap3-uart"; reg = <0x4806c000 0x400>; - interrupts = <73>; + interrupts-extended = <&intc 73>; dmas = <&sdma 51 &sdma 52>; dma-names = "tx", "rx"; ti,hwmods = "uart2"; @@ -287,7 +287,7 @@ uart3: serial@49020000 { compatible = "ti,omap3-uart"; reg = <0x49020000 0x400>; - interrupts = <74>; + interrupts-extended = <&intc 74>; dmas = <&sdma 53 &sdma 54>; dma-names = "tx", "rx"; ti,hwmods = "uart3"; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index d2c45bfaaa2c..8cfa3c8a72b0 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -481,6 +481,21 @@ usb-supply = <&vusb>; }; +&uart2 { + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; +}; + +&uart3 { + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&uart4 { + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART4_RX>; +}; + &usb_otg_hs { interface-type = <1>; mode = <3>; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 48983c8d56c2..3e1da43068f6 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -570,16 +570,22 @@ }; &uart2 { + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; &uart3 { + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; &uart4 { + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART4_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; }; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 649b5cd38b40..b22664544a09 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -311,7 +311,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; @@ -319,7 +319,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; @@ -327,7 +327,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index b04528cd033c..404ba7ef7813 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h @@ -69,5 +69,17 @@ #define OMAP5_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xc840) (val) #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) +/* + * Define some commonly used pins configured by the boards. + * Note that some boards use alternative pins, so check + * the schematics before using these. + */ +#define OMAP3_UART1_RX 0x152 +#define OMAP3_UART2_RX 0x14a +#define OMAP3_UART3_RX 0x16e +#define OMAP4_UART2_RX 0xdc +#define OMAP4_UART3_RX 0x104 +#define OMAP4_UART4_RX 0x11c + #endif -- cgit v1.2.3 From 3b8c4ebb76302af86873158d192d76ba3b260ca8 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:35 -0700 Subject: ARM: OMAP3: Fix idle mode signaling for sys_clkreq and sys_off_mode While debugging legacy mode vs device tree booted PM regressions, I noticed that omap3 is not toggling sys_clkreq and sys_off_mode pins like it should. The sys_clkreq and sys_off_mode pins are not toggling because of the following issues: 1. The default polarity for the sys_off_mode pin is wrong. OFFMODE_POL needs to be cleared for sys_off_mode to go down when hitting off-idle, while CLKREQ_POL needs to be set so sys_clkreq goes down when hitting retention. 2. The values for voltctrl register need to be updated dynamically. We need to set either the retention idle bits, or off idle bits in the voltctrl register depending the idle mode we're targeting to hit. Let's fix these two issues as otherwise the system will just hang if any twl4030 PMIC idle scripts are loaded. The only case where the system does not hang is if only retention idle over I2C4 is configured by the bootloader. Note that even without the twl4030 PMIC scripts, these fixes will do the proper signaling of sys_clkreq and sys_off_mode pins, so the fixes are needed to fix monitoring of PM states with LEDs or an oscilloscope. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm34xx.c | 4 ++ arch/arm/mach-omap2/prm-regbits-34xx.h | 11 ++++- arch/arm/mach-omap2/vc.c | 84 +++++++++++++++++++++++++++++++++- arch/arm/mach-omap2/vc.h | 3 ++ 4 files changed, 99 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 87099bb6de69..3c8bb8f0304d 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -50,6 +50,7 @@ #include "sdrc.h" #include "sram.h" #include "control.h" +#include "vc.h" /* pm34xx errata defined in pm.h */ u16 pm34xx_errata; @@ -288,6 +289,9 @@ void omap_sram_idle(void) } } + /* Configure PMIC signaling for I2C4 or sys_off_mode */ + omap3_vc_set_pmic_signaling(core_next_state); + omap3_intc_prepare_idle(); /* diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index cebad565ed37..106132db532b 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -123,8 +123,15 @@ #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) -#define OMAP3430_SEL_OFF_MASK (1 << 3) -#define OMAP3430_AUTO_OFF_MASK (1 << 2) +#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE (1 << 4) +#define OMAP3430_PRM_VOLTCTRL_SEL_OFF (1 << 3) +#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF (1 << 2) +#define OMAP3430_PRM_VOLTCTRL_AUTO_RET (1 << 1) +#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP (1 << 0) #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) +#define OMAP3430_PRM_POLCTRL_OFFMODE_POL (1 << 3) +#define OMAP3430_PRM_POLCTRL_CLKOUT_POL (1 << 2) +#define OMAP3430_PRM_POLCTRL_CLKREQ_POL (1 << 1) +#define OMAP3430_PRM_POLCTRL_EXTVOL_POL (1 << 0) #endif diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 49ac7977e03e..705eb35d7b35 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -220,6 +220,87 @@ static inline u32 omap_usec_to_32k(u32 usec) return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); } +struct omap3_vc { + struct voltagedomain *vd; + u32 voltctrl; +}; +static struct omap3_vc vc; + +void omap3_vc_set_pmic_signaling(int core_next_state) +{ + struct voltagedomain *vd = vc.vd; + u32 voltctrl; + + voltctrl = vc.voltctrl; + switch (core_next_state) { + case PWRDM_POWER_OFF: + voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | + OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); + voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; + break; + case PWRDM_POWER_RET: + default: + voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | + OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); + voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; + break; + } + if (voltctrl != vc.voltctrl) { + vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); + vc.voltctrl = voltctrl; + } +} + +#define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \ + OMAP3430_PRM_POLCTRL_CLKREQ_POL) +#define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL + +/* + * Configure signal polarity for sys_clkreq and sys_off_mode pins + * as the default values are wrong and can cause the system to hang + * if any twl4030 scripts are loaded. + */ +static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) +{ + u32 val; + + if (vc.vd) + return; + + vc.vd = voltdm; + + val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); + if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || + (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) { + val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; + val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; + pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n", + val); + voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); + } + + /* + * By default let's use I2C4 signaling for retention idle + * and sys_off_mode pin signaling for off idle. This way we + * have sys_clk_req pin go down for retention and both + * sys_clk_req and sys_off_mode pins will go down for off + * idle. And we can also scale voltages to zero for off-idle. + * Note that no actual voltage scaling during off-idle will + * happen unless the board specific twl4030 PMIC scripts are + * loaded. + */ + val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); + if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { + val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; + pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n", + val); + voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); + } + vc.voltctrl = val; + + omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); +} + /* Set oscillator setup time for omap3 */ static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm) { @@ -292,7 +373,7 @@ static void omap3_set_off_timings(struct voltagedomain *voltdm) /* check if sys_off_mode is used to control off-mode voltages */ val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); - if (!(val & OMAP3430_SEL_OFF_MASK)) { + if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { /* No, omap is controlling them over I2C */ omap3_set_i2c_timings(voltdm, true); return; @@ -337,6 +418,7 @@ static void omap3_set_off_timings(struct voltagedomain *voltdm) static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) { + omap3_vc_init_pmic_signaling(voltdm); omap3_set_off_timings(voltdm); } diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h index 91c8d75bf2ea..cdbdd78e755e 100644 --- a/arch/arm/mach-omap2/vc.h +++ b/arch/arm/mach-omap2/vc.h @@ -117,6 +117,9 @@ extern struct omap_vc_param omap4_mpu_vc_data; extern struct omap_vc_param omap4_iva_vc_data; extern struct omap_vc_param omap4_core_vc_data; +void omap3_vc_set_pmic_signaling(int core_next_state); + + void omap_vc_init_channel(struct voltagedomain *voltdm); int omap_vc_pre_scale(struct voltagedomain *voltdm, unsigned long target_volt, -- cgit v1.2.3 From 9eca2837dd69eeae0dd36ed0853d04b4de6c23bd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:35 -0700 Subject: ARM: OMAP3: Disable broken omap3_set_off_timings function Commit c589eb3869a8 (ARM: OMAP3: VC: calculate ramp times) started using regulator slew rates for calculating the idle mode start-up times. This works fine for I2C4 controlled regulator scaling as the regulators are never completely turned off. For sys_off_mode pin controlled PMIC scripts, the slew rate based calculations won't work at all as the regulators are completely turned off and the start-up time is much longer. This means currently omap3_set_off_timings currently has zero chance of working on any real hardare. The current code is broken in at least the following ways: 1. It attempts to use the default ULONG_MAX value for the oscillator start-up value as we're currently never initializing the start-up value. 2. It relies on a magic number potentially set by the bootloader for volsetup2 register. 3. If no magic value is passed, it attempts to calculate voltsetup2 register based on the regulator slew rate. This won't work as there is roughly at least five times the delay needed for turning on vdd1 and vdd2 regulators. 4. It does duplicate register write to OMAP3_PRM_VOLTOFFSET 5. It duplicates the code for omap_usec_to_32k unnecessarily 6. It initialized global registers twice, once for each channel Let's just remove the broken code and call omap3_set_i2c_timings directly, we're better off with this function doing nothing until it's fixed. And otherwise further fixes to omap3_set_off_timings will be unreadable. And let's get rid of omap3_set_clksetup as that's not needed for off-idle controlled by I2C4 as in that case the oscillator is never shut down. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/vc.c | 62 +----------------------------------------------- 1 file changed, 1 insertion(+), 61 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 705eb35d7b35..728d64daab25 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -301,12 +301,6 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); } -/* Set oscillator setup time for omap3 */ -static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm) -{ - voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET); -} - /** * omap3_set_i2c_timings - sets i2c sleep timings for a channel * @voltdm: channel to configure @@ -323,12 +317,6 @@ static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) unsigned long voltsetup1; u32 tgt_volt; - /* - * Oscillator is shut down only if we are using sys_off_mode pad, - * thus we set a minimal setup time here - */ - omap3_set_clksetup(1, voltdm); - if (off_mode) tgt_volt = voltdm->vc_param->off; else @@ -365,61 +353,13 @@ static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) */ static void omap3_set_off_timings(struct voltagedomain *voltdm) { - unsigned long clksetup; - unsigned long voltsetup2; - unsigned long voltsetup2_old; - u32 val; - u32 tstart, tshut; - - /* check if sys_off_mode is used to control off-mode voltages */ - val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); - if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { - /* No, omap is controlling them over I2C */ - omap3_set_i2c_timings(voltdm, true); - return; - } - - omap_pm_get_oscillator(&tstart, &tshut); - omap3_set_clksetup(tstart, voltdm); - - clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET); - - /* voltsetup 2 in us */ - voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate; - - /* convert to 32k clk cycles */ - voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000); - - voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET); - - /* - * Update voltsetup2 if higher than current value (needed because - * we have multiple channels with different ramp times), also - * update voltoffset always to value recommended by TRM - */ - if (voltsetup2 > voltsetup2_old) { - voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET); - voltdm->write(clksetup - voltsetup2, - OMAP3_PRM_VOLTOFFSET_OFFSET); - } else - voltdm->write(clksetup - voltsetup2_old, - OMAP3_PRM_VOLTOFFSET_OFFSET); - - /* - * omap is not controlling voltage scaling during off-mode, - * thus set voltsetup1 to 0 - */ - voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0, - voltdm->vfsm->voltsetup_reg); - - /* voltoffset must be clksetup minus voltsetup2 according to TRM */ - voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET); } static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) { omap3_vc_init_pmic_signaling(voltdm); omap3_set_off_timings(voltdm); + omap3_set_i2c_timings(voltdm, true); } /** -- cgit v1.2.3 From c46f601cc2a0e8edc97953c0b5d2acb709be71ba Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:36 -0700 Subject: ARM: OMAP3: Fix voltage control for deeper idle states Currently we're attempting to use a static value for the voltctrl register that only works for controlling the PMIC over I2C4. For using sys_off_mode signaling, we need to update update clksetup, voltsetup1, voltsetup2 and voltctrl registers dynamically depending on the idle state. So let's fix this by configuring things for I2C4 controlled idle and sys_off_mode pin controlled idle, and then write the configured register values depending on the idle state. This is similar what N900 kernel is doing too. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/vc.c | 112 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 85 insertions(+), 27 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 728d64daab25..0d1629c5f84e 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -220,35 +220,64 @@ static inline u32 omap_usec_to_32k(u32 usec) return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); } +struct omap3_vc_timings { + u32 voltsetup1; + u32 voltsetup2; +}; + struct omap3_vc { struct voltagedomain *vd; u32 voltctrl; + u32 voltsetup1; + u32 voltsetup2; + struct omap3_vc_timings timings[2]; }; static struct omap3_vc vc; void omap3_vc_set_pmic_signaling(int core_next_state) { struct voltagedomain *vd = vc.vd; - u32 voltctrl; + struct omap3_vc_timings *c = vc.timings; + u32 voltctrl, voltsetup1, voltsetup2; voltctrl = vc.voltctrl; + voltsetup1 = vc.voltsetup1; + voltsetup2 = vc.voltsetup2; + switch (core_next_state) { case PWRDM_POWER_OFF: voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; + if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF) + voltsetup2 = c->voltsetup2; + else + voltsetup1 = c->voltsetup1; break; case PWRDM_POWER_RET: default: + c++; voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; + voltsetup1 = c->voltsetup1; break; } + if (voltctrl != vc.voltctrl) { vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); vc.voltctrl = voltctrl; } + if (voltsetup1 != vc.voltsetup1) { + vd->write(c->voltsetup1, + OMAP3_PRM_VOLTSETUP1_OFFSET); + vc.voltsetup1 = voltsetup1; + } + if (voltsetup2 != vc.voltsetup2) { + vd->write(c->voltsetup2, + OMAP3_PRM_VOLTSETUP2_OFFSET); + vc.voltsetup2 = voltsetup2; + } } #define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \ @@ -301,6 +330,18 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); } +static void omap3_init_voltsetup1(struct voltagedomain *voltdm, + struct omap3_vc_timings *c, u32 idle) +{ + unsigned long val; + + val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; + val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; + val <<= __ffs(voltdm->vfsm->voltsetup_mask); + c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; + c->voltsetup1 |= val; +} + /** * omap3_set_i2c_timings - sets i2c sleep timings for a channel * @voltdm: channel to configure @@ -311,31 +352,21 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) * or retention. Off mode has additionally an option to use sys_off_mode * pad, which uses a global signal to program the whole power IC to * off-mode. + * + * Note that pmic is not controlling the voltage scaling during + * retention signaled over I2C4, so we can keep voltsetup2 as 0. + * And the oscillator is not shut off over I2C4, so no need to + * set clksetup. */ -static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) +static void omap3_set_i2c_timings(struct voltagedomain *voltdm) { - unsigned long voltsetup1; - u32 tgt_volt; - - if (off_mode) - tgt_volt = voltdm->vc_param->off; - else - tgt_volt = voltdm->vc_param->ret; - - voltsetup1 = (voltdm->vc_param->on - tgt_volt) / - voltdm->pmic->slew_rate; + struct omap3_vc_timings *c = vc.timings; - voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1; - - voltdm->rmw(voltdm->vfsm->voltsetup_mask, - voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask), - voltdm->vfsm->voltsetup_reg); - - /* - * pmic is not controlling the voltage scaling during retention, - * thus set voltsetup2 to 0 - */ - voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET); + /* Configure PRWDM_POWER_OFF over I2C4 */ + omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off); + c++; + /* Configure PRWDM_POWER_RET over I2C4 */ + omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret); } /** @@ -344,22 +375,49 @@ static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode) * * Calculates and sets up off-mode timings for a channel. Off-mode * can use either I2C based voltage scaling, or alternatively - * sys_off_mode pad can be used to send a global command to power IC. - * This function first checks which mode is being used, and calls - * omap3_set_i2c_timings() if the system is using I2C control mode. + * sys_off_mode pad can be used to send a global command to power IC.n, * sys_off_mode has the additional benefit that voltages can be * scaled to zero volt level with TWL4030 / TWL5030, I2C can only * scale to 600mV. + * + * Note that omap is not controlling the voltage scaling during + * off idle signaled by sys_off_mode, so we can keep voltsetup1 + * as 0. */ static void omap3_set_off_timings(struct voltagedomain *voltdm) { + struct omap3_vc_timings *c = vc.timings; + u32 tstart, tshut, clksetup, voltoffset; + + if (c->voltsetup2) + return; + + omap_pm_get_oscillator(&tstart, &tshut); + if (tstart == ULONG_MAX) { + pr_debug("PM: oscillator start-up time not initialized, using 10ms\n"); + clksetup = omap_usec_to_32k(10000); + } else { + clksetup = omap_usec_to_32k(tstart); + } + + /* + * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to + * switch from HFCLKIN to internal oscillator. That means timings + * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And + * that means we can calculate the value based on the oscillator + * start-up time since voltoffset2 = clksetup - voltoffset. + */ + voltoffset = omap_usec_to_32k(488); + c->voltsetup2 = clksetup - voltoffset; + voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET); + voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET); } static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) { omap3_vc_init_pmic_signaling(voltdm); omap3_set_off_timings(voltdm); - omap3_set_i2c_timings(voltdm, true); + omap3_set_i2c_timings(voltdm); } /** -- cgit v1.2.3 From 327456a79f53056e9db6afa80bfe2ca9448bc91f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:37 -0700 Subject: ARM: dts: Configure omap3 twl4030 I2C4 pins by default Almost certainly any sane board has the twl4030 has the I2C4 pins connected as those are needed for voltage control during idle. If the I2C4 lines are not properly muxed, any voltage scaling over I2C4 will fail. Let's mux those pins by default, the boards that are not using them can still configure things separately. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/twl4030_omap3.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi index c353ef0a6ac7..3537ae5b2146 100644 --- a/arch/arm/boot/dts/twl4030_omap3.dtsi +++ b/arch/arm/boot/dts/twl4030_omap3.dtsi @@ -8,7 +8,7 @@ &twl { pinctrl-names = "default"; - pinctrl-0 = <&twl4030_pins>; + pinctrl-0 = <&twl4030_pins &twl4030_vpins>; }; &omap3_pmx_core { @@ -23,3 +23,20 @@ >; }; }; + +/* + * If your board is not using the I2C4 pins with twl4030, then don't include + * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode + * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and + * sys_nvmode2 signaling. + */ +&omap3_pmx_wkup { + twl4030_vpins: pinmux_twl4030_vpins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */ + OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */ + OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */ + OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */ + >; + }; +}; -- cgit v1.2.3 From 2ee5f528a8102269ba1c0562799d30dd0075d57a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:37 -0700 Subject: ARM: OMAP2+: Fix voltage scaling init for device tree We are currently disabling the init of voltage scaling for device tree. With the voltage scaling problems fixed for omap3 in general, there's no need to disable the voltage scaling init for device tree based booting. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index e1b41416fbf1..ccefd11f8fe8 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -287,25 +287,21 @@ omap_postcore_initcall(omap2_common_pm_init); int __init omap2_common_pm_late_init(void) { - /* - * In the case of DT, the PMIC and SR initialization will be done using - * a completely different mechanism. - * Disable this part if a DT blob is available. - */ - if (!of_have_populated_dt()) { - - /* Init the voltage layer */ - omap_pmic_late_init(); - omap_voltage_late_init(); + if (of_have_populated_dt()) { + omap3_twl_init(); + omap4_twl_init(); + } - /* Initialize the voltages */ - omap3_init_voltages(); - omap4_init_voltages(); + /* Init the voltage layer */ + omap_pmic_late_init(); + omap_voltage_late_init(); - /* Smartreflex device init */ - omap_devinit_smartreflex(); + /* Initialize the voltages */ + omap3_init_voltages(); + omap4_init_voltages(); - } + /* Smartreflex device init */ + omap_devinit_smartreflex(); /* cpufreq dummy device instantiation */ omap_init_cpufreq(); -- cgit v1.2.3 From c1be2032f66df9e1238bd5bc4ca666de88a62abc Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:38 -0700 Subject: ARM: dts: Enable N900 keyboard sleep leds by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On N900 there are nice LEDs that show the state of the sys_clkreq and sys_off_mode pins. These LEDs go low when the system enters deeper idle states. The left LED shows the state of the sys_clkreq pin, and goes off during retention idle. The right LED shows the state of sys_off_mode pin and both go off during off idle. As N900 is a battery operated device, these LEDs should be off most of the time. So let's enable them by default so we can make sure the system is mostly idle. This allows the maintainers to also immediately test patches for PM regressions by looking at the LEDs, which certainly makes my life easier. The LED can naturally be disabled during runtime with: # echo none > /sys/class/leds/debug::sleep/trigger Note that we don't currently have support for omap3 errata 1.158 that remuxes GPIO pins to INPUT_PULLUP | MUX_MODE7 for the duration of idle. This means that the GPIO pins set high will go down during off idle. In this case it does not matter as the sys_off_mode goes down too, but there's still a slim chance of false off idle LED signals. If in doubt, false LED signals can be verified by the sys_off_mode or vdd_core values. Also note that to allow the UARTs to autoidle, the following needs to be run on N900 to enable off idle: #!/bin/sh uarts=$(find /sys/class/tty/ttyO*/device/power/ -type d) for uart in $uarts; do echo 3000 > $uart/autosuspend_delay_ms done uarts=$(find /sys/class/tty/ttyO*/power/ -type d) for uart in $uarts; do echo enabled > $uart/wakeup echo auto > $uart/control done echo 1 > /sys/kernel/debug/pm_debug/enable_off_mode For retention idle, change the above to set 0 to enable_off_mode. Also note that without the twl4030 PM scripts the actual voltage scaling won't happen for off idle so we only get voltage scaling over I2C4 for retention idle. I'll do some device tree patches for those also a bit later on. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Pali Rohár Cc: Paul Walmsley Cc: Pavel Machek Cc: Sebastian Reichel Cc: Tero Kristo Acked-by: Aaro Koskinen [tony@atomide.com: also make sure the LEDs get built to see PM regressions] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 17 +++++++++++++++++ arch/arm/configs/omap2plus_defconfig | 1 + 2 files changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 656ae403018f..150ca097c02d 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -21,6 +21,17 @@ }; }; + leds { + compatible = "gpio-leds"; + heartbeat { + label = "debug::sleep"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* gpio162 */ + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&debug_leds>; + }; + }; + memory { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ @@ -130,6 +141,12 @@ >; }; + debug_leds: pinmux_debug_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 */ + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk */ diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index a4e8d017f25b..0a7017012719 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -239,6 +239,7 @@ CONFIG_SDIO_UART=y CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP_HS=y CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y -- cgit v1.2.3 From 57b05572267581c2320462e9b606709fa6da4c5a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 5 May 2014 17:27:39 -0700 Subject: ARM: OMAP2+: Enable CPUidle in omap2plus_defconfig Enable CPUidle so it's easier for maintainers to notice if some future code changes cause regressions. Cc: Kevin Hilman Cc: Nishanth Menon Cc: Paul Walmsley Cc: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 0a7017012719..28f3b6e3b589 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -21,6 +21,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_MULTI_V6=y +CONFIG_POWER_AVS_OMAP=y +CONFIG_POWER_AVS_OMAP_CLASS3=y CONFIG_OMAP_RESET_CLOCKS=y CONFIG_OMAP_MUX_DEBUG=y CONFIG_ARCH_OMAP2=y @@ -42,6 +44,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200" CONFIG_KEXEC=y CONFIG_FPE_NWFPE=y +CONFIG_CPU_IDLE=y CONFIG_BINFMT_MISC=y CONFIG_PM_DEBUG=y CONFIG_NET=y @@ -159,11 +162,14 @@ CONFIG_GPIO_SYSFS=y CONFIG_GPIO_TWL4030=y CONFIG_W1=y CONFIG_POWER_SUPPLY=y +CONFIG_POWER_AVS=y CONFIG_SENSORS_LM75=m CONFIG_THERMAL=y CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_CPU_THERMAL=y CONFIG_TI_SOC_THERMAL=y +CONFIG_TI_THERMAL=y CONFIG_OMAP4_THERMAL=y CONFIG_OMAP5_THERMAL=y CONFIG_DRA752_THERMAL=y @@ -177,6 +183,7 @@ CONFIG_MFD_TPS65910=y CONFIG_TWL6040_CORE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_TI_ABB=y CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS65217=y -- cgit v1.2.3 From 6b90f55f63c75c2c65454aea6703c2ea91b9e372 Mon Sep 17 00:00:00 2001 From: Hanjun Guo Date: Tue, 6 May 2014 11:24:30 +0800 Subject: ACPI / PCI: Stub out pci_acpi_crs_quirks() and make it x86 specific For pci_acpi_crs_quirks(), ia64 already doesn't use it, and we can not foresee it should be used in ARM64, so stub out pci_acpi_crs_quirks() to avoid introducing platform specific dummy stub function. Signed-off-by: Hanjun Guo Reviewed-by: Bjorn Helgaas Signed-off-by: Rafael J. Wysocki --- arch/ia64/include/asm/acpi.h | 1 - include/acpi/acpi_drivers.h | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index d651102a4d45..97cb16086314 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -92,7 +92,6 @@ ia64_acpi_release_global_lock (unsigned int *lock) #endif #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ static inline void disable_acpi(void) { } -static inline void pci_acpi_crs_quirks(void) { } #ifdef CONFIG_IA64_GENERIC const char *acpi_get_sysname (void); diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index d504613bbf80..ea6428b7dacb 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -96,7 +96,12 @@ struct pci_dev *acpi_get_pci_dev(acpi_handle); /* Arch-defined function to add a bus to the system */ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root); + +#ifdef CONFIG_X86 void pci_acpi_crs_quirks(void); +#else +static inline void pci_acpi_crs_quirks(void) { } +#endif /* -------------------------------------------------------------------------- Processor -- cgit v1.2.3 From 00954c1bdb7dc284b461008dddaf0231c9412467 Mon Sep 17 00:00:00 2001 From: Rongjun Ying Date: Thu, 30 Jan 2014 13:54:53 +0800 Subject: ARM: dts: sirf: add pin group for USP0 with only RX or TX frame sync for atlas6 add pin groups for USP0 only holding one of TX and RX frame sync. this patch matches with the change in drivers/pinctrl/sirf. commit 73f68c01f46 did this for prima2, but missed prima2. this patch fixes the problem. Signed-off-by: Rongjun Ying Signed-off-by: Barry Song Acked-by: Linus Walleij --- arch/arm/boot/dts/atlas6.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index 9d72674049d6..c84c45c2bd41 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -554,6 +554,18 @@ sirf,function = "usp0_uart_nostreamctrl"; }; }; + usp0_only_utfs_pins_a: usp0@2 { + usp0 { + sirf,pins = "usp0_only_utfs_grp"; + sirf,function = "usp0_only_utfs"; + }; + }; + usp0_only_urfs_pins_a: usp0@3 { + usp0 { + sirf,pins = "usp0_only_urfs_grp"; + sirf,function = "usp0_only_urfs"; + }; + }; usp1_pins_a: usp1@0 { usp1 { sirf,pins = "usp1grp"; -- cgit v1.2.3 From 143e1e28cb40bed836b0a06567208bd7347c9672 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 11 Apr 2014 11:44:37 +0200 Subject: sched: Rework sched_domain topology definition We replace the old way to configure the scheduler topology with a new method which enables a platform to declare additionnal level (if needed). We still have a default topology table definition that can be used by platform that don't want more level than the SMT, MC, CPU and NUMA ones. This table can be overwritten by an arch which either wants to add new level where a load balance make sense like BOOK or powergating level or wants to change the flags configuration of some levels. For each level, we need a function pointer that returns cpumask for each cpu, a function pointer that returns the flags for the level and a name. Only flags that describe topology, can be set by an architecture. The current topology flags are: SD_SHARE_CPUPOWER SD_SHARE_PKG_RESOURCES SD_NUMA SD_ASYM_PACKING Then, each level must be a subset on the next one. The build sequence of the sched_domain will take care of removing useless levels like those with 1 CPU and those with the same CPU span and no more relevant information for load balancing than its children. Signed-off-by: Vincent Guittot Tested-by: Dietmar Eggemann Reviewed-by: Preeti U Murthy Reviewed-by: Dietmar Eggemann Signed-off-by: Peter Zijlstra Cc: Andrew Morton Cc: Benjamin Herrenschmidt Cc: Bjorn Helgaas Cc: Chris Metcalf Cc: Christoph Lameter Cc: David S. Miller Cc: Fenghua Yu Cc: Greg Kroah-Hartman Cc: Hanjun Guo Cc: Heiko Carstens Cc: Jason Low Cc: Linus Torvalds Cc: Martin Schwidefsky Cc: Tony Luck Cc: linux390@de.ibm.com Cc: linux-ia64@vger.kernel.org Cc: linux-s390@vger.kernel.org Link: http://lkml.kernel.org/r/1397209481-28542-2-git-send-email-vincent.guittot@linaro.org Signed-off-by: Ingo Molnar --- arch/ia64/include/asm/topology.h | 24 ---- arch/s390/include/asm/topology.h | 2 - arch/tile/include/asm/topology.h | 33 ------ include/linux/sched.h | 53 +++++++++ include/linux/topology.h | 128 +++------------------ kernel/sched/core.c | 233 ++++++++++++++++++++------------------- 6 files changed, 186 insertions(+), 287 deletions(-) (limited to 'arch') diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h index 5cb55a1e606b..3202aa74e0d6 100644 --- a/arch/ia64/include/asm/topology.h +++ b/arch/ia64/include/asm/topology.h @@ -46,30 +46,6 @@ void build_cpu_to_node_map(void); -#define SD_CPU_INIT (struct sched_domain) { \ - .parent = NULL, \ - .child = NULL, \ - .groups = NULL, \ - .min_interval = 1, \ - .max_interval = 4, \ - .busy_factor = 64, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 2, \ - .busy_idx = 2, \ - .idle_idx = 1, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_NEWIDLE \ - | SD_BALANCE_EXEC \ - | SD_BALANCE_FORK \ - | SD_WAKE_AFFINE, \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .nr_balance_failed = 0, \ -} - #endif /* CONFIG_NUMA */ #ifdef CONFIG_SMP diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h index 05425b18c0aa..07763bdb408d 100644 --- a/arch/s390/include/asm/topology.h +++ b/arch/s390/include/asm/topology.h @@ -64,8 +64,6 @@ static inline void s390_init_cpu_topology(void) }; #endif -#define SD_BOOK_INIT SD_CPU_INIT - #include #endif /* _ASM_S390_TOPOLOGY_H */ diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h index d15c0d8d550f..938311844233 100644 --- a/arch/tile/include/asm/topology.h +++ b/arch/tile/include/asm/topology.h @@ -44,39 +44,6 @@ static inline const struct cpumask *cpumask_of_node(int node) /* For now, use numa node -1 for global allocation. */ #define pcibus_to_node(bus) ((void)(bus), -1) -/* - * TILE architecture has many cores integrated in one processor, so we need - * setup bigger balance_interval for both CPU/NODE scheduling domains to - * reduce process scheduling costs. - */ - -/* sched_domains SD_CPU_INIT for TILE architecture */ -#define SD_CPU_INIT (struct sched_domain) { \ - .min_interval = 4, \ - .max_interval = 128, \ - .busy_factor = 64, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .busy_idx = 2, \ - .idle_idx = 1, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 0*SD_WAKE_AFFINE \ - | 0*SD_SHARE_CPUPOWER \ - | 0*SD_SHARE_PKG_RESOURCES \ - | 0*SD_SERIALIZE \ - , \ - .last_balance = jiffies, \ - .balance_interval = 32, \ -} - /* By definition, we create nodes based on online memory. */ #define node_has_online_mem(nid) 1 diff --git a/include/linux/sched.h b/include/linux/sched.h index 2a4298fb0d85..656b035c30e5 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -879,6 +879,27 @@ enum cpu_idle_type { extern int __weak arch_sd_sibiling_asym_packing(void); +#ifdef CONFIG_SCHED_SMT +static inline const int cpu_smt_flags(void) +{ + return SD_SHARE_CPUPOWER | SD_SHARE_PKG_RESOURCES; +} +#endif + +#ifdef CONFIG_SCHED_MC +static inline const int cpu_core_flags(void) +{ + return SD_SHARE_PKG_RESOURCES; +} +#endif + +#ifdef CONFIG_NUMA +static inline const int cpu_numa_flags(void) +{ + return SD_NUMA; +} +#endif + struct sched_domain_attr { int relax_domain_level; }; @@ -985,6 +1006,38 @@ void free_sched_domains(cpumask_var_t doms[], unsigned int ndoms); bool cpus_share_cache(int this_cpu, int that_cpu); +typedef const struct cpumask *(*sched_domain_mask_f)(int cpu); +typedef const int (*sched_domain_flags_f)(void); + +#define SDTL_OVERLAP 0x01 + +struct sd_data { + struct sched_domain **__percpu sd; + struct sched_group **__percpu sg; + struct sched_group_power **__percpu sgp; +}; + +struct sched_domain_topology_level { + sched_domain_mask_f mask; + sched_domain_flags_f sd_flags; + int flags; + int numa_level; + struct sd_data data; +#ifdef CONFIG_SCHED_DEBUG + char *name; +#endif +}; + +extern struct sched_domain_topology_level *sched_domain_topology; + +extern void set_sched_topology(struct sched_domain_topology_level *tl); + +#ifdef CONFIG_SCHED_DEBUG +# define SD_INIT_NAME(type) .name = #type +#else +# define SD_INIT_NAME(type) +#endif + #else /* CONFIG_SMP */ struct sched_domain_attr; diff --git a/include/linux/topology.h b/include/linux/topology.h index 7062330a1329..973671ff9e7d 100644 --- a/include/linux/topology.h +++ b/include/linux/topology.h @@ -66,121 +66,6 @@ int arch_update_cpu_topology(void); #define PENALTY_FOR_NODE_WITH_CPUS (1) #endif -/* - * Below are the 3 major initializers used in building sched_domains: - * SD_SIBLING_INIT, for SMT domains - * SD_CPU_INIT, for SMP domains - * - * Any architecture that cares to do any tuning to these values should do so - * by defining their own arch-specific initializer in include/asm/topology.h. - * A definition there will automagically override these default initializers - * and allow arch-specific performance tuning of sched_domains. - * (Only non-zero and non-null fields need be specified.) - */ - -#ifdef CONFIG_SCHED_SMT -/* MCD - Do we really need this? It is always on if CONFIG_SCHED_SMT is, - * so can't we drop this in favor of CONFIG_SCHED_SMT? - */ -#define ARCH_HAS_SCHED_WAKE_IDLE -/* Common values for SMT siblings */ -#ifndef SD_SIBLING_INIT -#define SD_SIBLING_INIT (struct sched_domain) { \ - .min_interval = 1, \ - .max_interval = 2, \ - .busy_factor = 64, \ - .imbalance_pct = 110, \ - \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 1*SD_WAKE_AFFINE \ - | 1*SD_SHARE_CPUPOWER \ - | 1*SD_SHARE_PKG_RESOURCES \ - | 0*SD_SERIALIZE \ - | 0*SD_PREFER_SIBLING \ - | arch_sd_sibling_asym_packing() \ - , \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .smt_gain = 1178, /* 15% */ \ - .max_newidle_lb_cost = 0, \ - .next_decay_max_lb_cost = jiffies, \ -} -#endif -#endif /* CONFIG_SCHED_SMT */ - -#ifdef CONFIG_SCHED_MC -/* Common values for MC siblings. for now mostly derived from SD_CPU_INIT */ -#ifndef SD_MC_INIT -#define SD_MC_INIT (struct sched_domain) { \ - .min_interval = 1, \ - .max_interval = 4, \ - .busy_factor = 64, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .busy_idx = 2, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 1*SD_WAKE_AFFINE \ - | 0*SD_SHARE_CPUPOWER \ - | 1*SD_SHARE_PKG_RESOURCES \ - | 0*SD_SERIALIZE \ - , \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .max_newidle_lb_cost = 0, \ - .next_decay_max_lb_cost = jiffies, \ -} -#endif -#endif /* CONFIG_SCHED_MC */ - -/* Common values for CPUs */ -#ifndef SD_CPU_INIT -#define SD_CPU_INIT (struct sched_domain) { \ - .min_interval = 1, \ - .max_interval = 4, \ - .busy_factor = 64, \ - .imbalance_pct = 125, \ - .cache_nice_tries = 1, \ - .busy_idx = 2, \ - .idle_idx = 1, \ - .newidle_idx = 0, \ - .wake_idx = 0, \ - .forkexec_idx = 0, \ - \ - .flags = 1*SD_LOAD_BALANCE \ - | 1*SD_BALANCE_NEWIDLE \ - | 1*SD_BALANCE_EXEC \ - | 1*SD_BALANCE_FORK \ - | 0*SD_BALANCE_WAKE \ - | 1*SD_WAKE_AFFINE \ - | 0*SD_SHARE_CPUPOWER \ - | 0*SD_SHARE_PKG_RESOURCES \ - | 0*SD_SERIALIZE \ - | 1*SD_PREFER_SIBLING \ - , \ - .last_balance = jiffies, \ - .balance_interval = 1, \ - .max_newidle_lb_cost = 0, \ - .next_decay_max_lb_cost = jiffies, \ -} -#endif - -#ifdef CONFIG_SCHED_BOOK -#ifndef SD_BOOK_INIT -#error Please define an appropriate SD_BOOK_INIT in include/asm/topology.h!!! -#endif -#endif /* CONFIG_SCHED_BOOK */ - #ifdef CONFIG_USE_PERCPU_NUMA_NODE_ID DECLARE_PER_CPU(int, numa_node); @@ -295,4 +180,17 @@ static inline int cpu_to_mem(int cpu) #define topology_core_cpumask(cpu) cpumask_of(cpu) #endif +#ifdef CONFIG_SCHED_SMT +static inline const struct cpumask *cpu_smt_mask(int cpu) +{ + return topology_thread_cpumask(cpu); +} +#endif + +static inline const struct cpumask *cpu_cpu_mask(int cpu) +{ + return cpumask_of_node(cpu_to_node(cpu)); +} + + #endif /* _LINUX_TOPOLOGY_H */ diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 13584f1cccfc..7d332b7899cc 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5566,17 +5566,6 @@ static int __init isolated_cpu_setup(char *str) __setup("isolcpus=", isolated_cpu_setup); -static const struct cpumask *cpu_cpu_mask(int cpu) -{ - return cpumask_of_node(cpu_to_node(cpu)); -} - -struct sd_data { - struct sched_domain **__percpu sd; - struct sched_group **__percpu sg; - struct sched_group_power **__percpu sgp; -}; - struct s_data { struct sched_domain ** __percpu sd; struct root_domain *rd; @@ -5589,21 +5578,6 @@ enum s_alloc { sa_none, }; -struct sched_domain_topology_level; - -typedef struct sched_domain *(*sched_domain_init_f)(struct sched_domain_topology_level *tl, int cpu); -typedef const struct cpumask *(*sched_domain_mask_f)(int cpu); - -#define SDTL_OVERLAP 0x01 - -struct sched_domain_topology_level { - sched_domain_init_f init; - sched_domain_mask_f mask; - int flags; - int numa_level; - struct sd_data data; -}; - /* * Build an iteration mask that can exclude certain CPUs from the upwards * domain traversal. @@ -5832,34 +5806,6 @@ int __weak arch_sd_sibling_asym_packing(void) * Non-inlined to reduce accumulated stack pressure in build_sched_domains() */ -#ifdef CONFIG_SCHED_DEBUG -# define SD_INIT_NAME(sd, type) sd->name = #type -#else -# define SD_INIT_NAME(sd, type) do { } while (0) -#endif - -#define SD_INIT_FUNC(type) \ -static noinline struct sched_domain * \ -sd_init_##type(struct sched_domain_topology_level *tl, int cpu) \ -{ \ - struct sched_domain *sd = *per_cpu_ptr(tl->data.sd, cpu); \ - *sd = SD_##type##_INIT; \ - SD_INIT_NAME(sd, type); \ - sd->private = &tl->data; \ - return sd; \ -} - -SD_INIT_FUNC(CPU) -#ifdef CONFIG_SCHED_SMT - SD_INIT_FUNC(SIBLING) -#endif -#ifdef CONFIG_SCHED_MC - SD_INIT_FUNC(MC) -#endif -#ifdef CONFIG_SCHED_BOOK - SD_INIT_FUNC(BOOK) -#endif - static int default_relax_domain_level = -1; int sched_domain_level_max; @@ -5947,99 +5893,156 @@ static void claim_allocations(int cpu, struct sched_domain *sd) *per_cpu_ptr(sdd->sgp, cpu) = NULL; } -#ifdef CONFIG_SCHED_SMT -static const struct cpumask *cpu_smt_mask(int cpu) -{ - return topology_thread_cpumask(cpu); -} -#endif - -/* - * Topology list, bottom-up. - */ -static struct sched_domain_topology_level default_topology[] = { -#ifdef CONFIG_SCHED_SMT - { sd_init_SIBLING, cpu_smt_mask, }, -#endif -#ifdef CONFIG_SCHED_MC - { sd_init_MC, cpu_coregroup_mask, }, -#endif -#ifdef CONFIG_SCHED_BOOK - { sd_init_BOOK, cpu_book_mask, }, -#endif - { sd_init_CPU, cpu_cpu_mask, }, - { NULL, }, -}; - -static struct sched_domain_topology_level *sched_domain_topology = default_topology; - -#define for_each_sd_topology(tl) \ - for (tl = sched_domain_topology; tl->init; tl++) - #ifdef CONFIG_NUMA - static int sched_domains_numa_levels; static int *sched_domains_numa_distance; static struct cpumask ***sched_domains_numa_masks; static int sched_domains_curr_level; +#endif -static inline int sd_local_flags(int level) -{ - if (sched_domains_numa_distance[level] > RECLAIM_DISTANCE) - return 0; - - return SD_BALANCE_EXEC | SD_BALANCE_FORK | SD_WAKE_AFFINE; -} +/* + * SD_flags allowed in topology descriptions. + * + * SD_SHARE_CPUPOWER - describes SMT topologies + * SD_SHARE_PKG_RESOURCES - describes shared caches + * SD_NUMA - describes NUMA topologies + * + * Odd one out: + * SD_ASYM_PACKING - describes SMT quirks + */ +#define TOPOLOGY_SD_FLAGS \ + (SD_SHARE_CPUPOWER | \ + SD_SHARE_PKG_RESOURCES | \ + SD_NUMA | \ + SD_ASYM_PACKING) static struct sched_domain * -sd_numa_init(struct sched_domain_topology_level *tl, int cpu) +sd_init(struct sched_domain_topology_level *tl, int cpu) { struct sched_domain *sd = *per_cpu_ptr(tl->data.sd, cpu); - int level = tl->numa_level; - int sd_weight = cpumask_weight( - sched_domains_numa_masks[level][cpu_to_node(cpu)]); + int sd_weight, sd_flags = 0; + +#ifdef CONFIG_NUMA + /* + * Ugly hack to pass state to sd_numa_mask()... + */ + sched_domains_curr_level = tl->numa_level; +#endif + + sd_weight = cpumask_weight(tl->mask(cpu)); + + if (tl->sd_flags) + sd_flags = (*tl->sd_flags)(); + if (WARN_ONCE(sd_flags & ~TOPOLOGY_SD_FLAGS, + "wrong sd_flags in topology description\n")) + sd_flags &= ~TOPOLOGY_SD_FLAGS; *sd = (struct sched_domain){ .min_interval = sd_weight, .max_interval = 2*sd_weight, .busy_factor = 32, .imbalance_pct = 125, - .cache_nice_tries = 2, - .busy_idx = 3, - .idle_idx = 2, + + .cache_nice_tries = 0, + .busy_idx = 0, + .idle_idx = 0, .newidle_idx = 0, .wake_idx = 0, .forkexec_idx = 0, .flags = 1*SD_LOAD_BALANCE | 1*SD_BALANCE_NEWIDLE - | 0*SD_BALANCE_EXEC - | 0*SD_BALANCE_FORK + | 1*SD_BALANCE_EXEC + | 1*SD_BALANCE_FORK | 0*SD_BALANCE_WAKE - | 0*SD_WAKE_AFFINE + | 1*SD_WAKE_AFFINE | 0*SD_SHARE_CPUPOWER | 0*SD_SHARE_PKG_RESOURCES - | 1*SD_SERIALIZE + | 0*SD_SERIALIZE | 0*SD_PREFER_SIBLING - | 1*SD_NUMA - | sd_local_flags(level) + | 0*SD_NUMA + | sd_flags , + .last_balance = jiffies, .balance_interval = sd_weight, + .smt_gain = 0, .max_newidle_lb_cost = 0, .next_decay_max_lb_cost = jiffies, +#ifdef CONFIG_SCHED_DEBUG + .name = tl->name, +#endif }; - SD_INIT_NAME(sd, NUMA); - sd->private = &tl->data; /* - * Ugly hack to pass state to sd_numa_mask()... + * Convert topological properties into behaviour. */ - sched_domains_curr_level = tl->numa_level; + + if (sd->flags & SD_SHARE_CPUPOWER) { + sd->imbalance_pct = 110; + sd->smt_gain = 1178; /* ~15% */ + sd->flags |= arch_sd_sibling_asym_packing(); + + } else if (sd->flags & SD_SHARE_PKG_RESOURCES) { + sd->imbalance_pct = 117; + sd->cache_nice_tries = 1; + sd->busy_idx = 2; + +#ifdef CONFIG_NUMA + } else if (sd->flags & SD_NUMA) { + sd->cache_nice_tries = 2; + sd->busy_idx = 3; + sd->idle_idx = 2; + + sd->flags |= SD_SERIALIZE; + if (sched_domains_numa_distance[tl->numa_level] > RECLAIM_DISTANCE) { + sd->flags &= ~(SD_BALANCE_EXEC | + SD_BALANCE_FORK | + SD_WAKE_AFFINE); + } + +#endif + } else { + sd->flags |= SD_PREFER_SIBLING; + sd->cache_nice_tries = 1; + sd->busy_idx = 2; + sd->idle_idx = 1; + } + + sd->private = &tl->data; return sd; } +/* + * Topology list, bottom-up. + */ +static struct sched_domain_topology_level default_topology[] = { +#ifdef CONFIG_SCHED_SMT + { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, +#endif +#ifdef CONFIG_SCHED_MC + { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, +#endif +#ifdef CONFIG_SCHED_BOOK + { cpu_book_mask, SD_INIT_NAME(BOOK) }, +#endif + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + +struct sched_domain_topology_level *sched_domain_topology = default_topology; + +#define for_each_sd_topology(tl) \ + for (tl = sched_domain_topology; tl->mask; tl++) + +void set_sched_topology(struct sched_domain_topology_level *tl) +{ + sched_domain_topology = tl; +} + +#ifdef CONFIG_NUMA + static const struct cpumask *sd_numa_mask(int cpu) { return sched_domains_numa_masks[sched_domains_curr_level][cpu_to_node(cpu)]; @@ -6183,7 +6186,10 @@ static void sched_init_numa(void) } } - tl = kzalloc((ARRAY_SIZE(default_topology) + level) * + /* Compute default topology size */ + for (i = 0; sched_domain_topology[i].mask; i++); + + tl = kzalloc((i + level) * sizeof(struct sched_domain_topology_level), GFP_KERNEL); if (!tl) return; @@ -6191,18 +6197,19 @@ static void sched_init_numa(void) /* * Copy the default topology bits.. */ - for (i = 0; default_topology[i].init; i++) - tl[i] = default_topology[i]; + for (i = 0; sched_domain_topology[i].mask; i++) + tl[i] = sched_domain_topology[i]; /* * .. and append 'j' levels of NUMA goodness. */ for (j = 0; j < level; i++, j++) { tl[i] = (struct sched_domain_topology_level){ - .init = sd_numa_init, .mask = sd_numa_mask, + .sd_flags = cpu_numa_flags, .flags = SDTL_OVERLAP, .numa_level = j, + SD_INIT_NAME(NUMA) }; } @@ -6360,7 +6367,7 @@ struct sched_domain *build_sched_domain(struct sched_domain_topology_level *tl, const struct cpumask *cpu_map, struct sched_domain_attr *attr, struct sched_domain *child, int cpu) { - struct sched_domain *sd = tl->init(tl, cpu); + struct sched_domain *sd = sd_init(tl, cpu); if (!sd) return child; -- cgit v1.2.3 From 2dfd747629e65f89d2dbceb92fffc763f66228b2 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 11 Apr 2014 11:44:38 +0200 Subject: sched, s390: Create a dedicated topology table BOOK level is only relevant for s390 so we create a dedicated topology table with BOOK level and remove it from default table. Signed-off-by: Vincent Guittot Signed-off-by: Peter Zijlstra Cc: Heiko Carstens Cc: Linus Torvalds Cc: Martin Schwidefsky Cc: Philipp Hachtmann Cc: cmetcalf@tilera.com Cc: benh@kernel.crashing.org Cc: dietmar.eggemann@arm.com Cc: preeti@linux.vnet.ibm.com Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: linux390@de.ibm.com Cc: linux-s390@vger.kernel.org Link: http://lkml.kernel.org/r/1397209481-28542-3-git-send-email-vincent.guittot@linaro.org Signed-off-by: Ingo Molnar --- arch/s390/include/asm/topology.h | 11 +---------- arch/s390/kernel/topology.c | 20 ++++++++++++++++++++ kernel/sched/core.c | 3 --- 3 files changed, 21 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h index 07763bdb408d..56af53093d24 100644 --- a/arch/s390/include/asm/topology.h +++ b/arch/s390/include/asm/topology.h @@ -26,21 +26,12 @@ extern struct cpu_topology_s390 cpu_topology[NR_CPUS]; #define mc_capable() 1 -static inline const struct cpumask *cpu_coregroup_mask(int cpu) -{ - return &cpu_topology[cpu].core_mask; -} - -static inline const struct cpumask *cpu_book_mask(int cpu) -{ - return &cpu_topology[cpu].book_mask; -} - int topology_cpu_init(struct cpu *); int topology_set_cpu_management(int fc); void topology_schedule_update(void); void store_topology(struct sysinfo_15_1_x *info); void topology_expect_change(void); +const struct cpumask *cpu_coregroup_mask(int cpu); #else /* CONFIG_SCHED_BOOK */ diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index 6298fed11ced..1860ad3cbc04 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -443,6 +443,23 @@ int topology_cpu_init(struct cpu *cpu) return sysfs_create_group(&cpu->dev.kobj, &topology_cpu_attr_group); } +const struct cpumask *cpu_coregroup_mask(int cpu) +{ + return &cpu_topology[cpu].core_mask; +} + +static const struct cpumask *cpu_book_mask(int cpu) +{ + return &cpu_topology[cpu].book_mask; +} + +static struct sched_domain_topology_level s390_topology[] = { + { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, + { cpu_book_mask, SD_INIT_NAME(BOOK) }, + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + static int __init topology_init(void) { if (!MACHINE_HAS_TOPOLOGY) { @@ -451,6 +468,9 @@ static int __init topology_init(void) } set_topology_timer(); out: + + set_sched_topology(s390_topology); + return device_create_file(cpu_subsys.dev_root, &dev_attr_dispatching); } device_initcall(topology_init); diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 7d332b7899cc..e59e5aec745a 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -6023,9 +6023,6 @@ static struct sched_domain_topology_level default_topology[] = { #endif #ifdef CONFIG_SCHED_MC { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, -#endif -#ifdef CONFIG_SCHED_BOOK - { cpu_book_mask, SD_INIT_NAME(BOOK) }, #endif { cpu_cpu_mask, SD_INIT_NAME(DIE) }, { NULL, }, -- cgit v1.2.3 From 607b45e9a216e89a63351556e488eea06be0ff48 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 11 Apr 2014 11:44:39 +0200 Subject: sched, powerpc: Create a dedicated topology table Create a dedicated topology table for handling asymetric feature of powerpc. Signed-off-by: Vincent Guittot Reviewed-by: Preeti U Murthy Signed-off-by: Peter Zijlstra Cc: Andy Fleming Cc: Anton Blanchard Cc: Benjamin Herrenschmidt Cc: Grant Likely Cc: Linus Torvalds Cc: Michael Ellerman Cc: Paul Gortmaker Cc: Paul Mackerras Cc: Preeti U. Murthy Cc: Rob Herring Cc: Srivatsa S. Bhat Cc: Toshi Kani Cc: Vasant Hegde Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: schwidefsky@de.ibm.com Cc: cmetcalf@tilera.com Cc: dietmar.eggemann@arm.com Cc: devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Link: http://lkml.kernel.org/r/1397209481-28542-4-git-send-email-vincent.guittot@linaro.org Signed-off-by: Ingo Molnar --- arch/powerpc/kernel/smp.c | 31 +++++++++++++++++++++++-------- include/linux/sched.h | 2 -- kernel/sched/core.c | 6 ------ 3 files changed, 23 insertions(+), 16 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index e2a4232c5871..10ffffef0414 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -766,6 +766,28 @@ int setup_profiling_timer(unsigned int multiplier) return 0; } +#ifdef CONFIG_SCHED_SMT +/* cpumask of CPUs with asymetric SMT dependancy */ +static const int powerpc_smt_flags(void) +{ + int flags = SD_SHARE_CPUPOWER | SD_SHARE_PKG_RESOURCES; + + if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { + printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); + flags |= SD_ASYM_PACKING; + } + return flags; +} +#endif + +static struct sched_domain_topology_level powerpc_topology[] = { +#ifdef CONFIG_SCHED_SMT + { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, +#endif + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + void __init smp_cpus_done(unsigned int max_cpus) { cpumask_var_t old_mask; @@ -790,15 +812,8 @@ void __init smp_cpus_done(unsigned int max_cpus) dump_numa_cpu_topology(); -} + set_sched_topology(powerpc_topology); -int arch_sd_sibling_asym_packing(void) -{ - if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { - printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); - return SD_ASYM_PACKING; - } - return 0; } #ifdef CONFIG_HOTPLUG_CPU diff --git a/include/linux/sched.h b/include/linux/sched.h index 656b035c30e5..439a153b8403 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -877,8 +877,6 @@ enum cpu_idle_type { #define SD_OVERLAP 0x2000 /* sched_domains of this level overlap */ #define SD_NUMA 0x4000 /* cross-node balancing */ -extern int __weak arch_sd_sibiling_asym_packing(void); - #ifdef CONFIG_SCHED_SMT static inline const int cpu_smt_flags(void) { diff --git a/kernel/sched/core.c b/kernel/sched/core.c index e59e5aec745a..7e348e238bf1 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5796,11 +5796,6 @@ static void init_sched_groups_power(int cpu, struct sched_domain *sd) atomic_set(&sg->sgp->nr_busy_cpus, sg->group_weight); } -int __weak arch_sd_sibling_asym_packing(void) -{ - return 0*SD_ASYM_PACKING; -} - /* * Initializers for schedule domains * Non-inlined to reduce accumulated stack pressure in build_sched_domains() @@ -5981,7 +5976,6 @@ sd_init(struct sched_domain_topology_level *tl, int cpu) if (sd->flags & SD_SHARE_CPUPOWER) { sd->imbalance_pct = 110; sd->smt_gain = 1178; /* ~15% */ - sd->flags |= arch_sd_sibling_asym_packing(); } else if (sd->flags & SD_SHARE_PKG_RESOURCES) { sd->imbalance_pct = 117; -- cgit v1.2.3 From fb2aa85564f4de35d25db022ab93640f8bb51821 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 11 Apr 2014 11:44:41 +0200 Subject: sched, ARM: Create a dedicated scheduler topology table Create a dedicated topology table for ARM which will create new level to differentiate CPUs that can or not powergate independantly from others. The patch gives an example of how to add domain that will take advantage of SD_SHARE_POWERDOMAIN. Signed-off-by: Vincent Guittot Reviewed-by: Dietmar Eggemann Tested-by: Dietmar Eggemann Signed-off-by: Peter Zijlstra Cc: Arnd Bergmann Cc: Grant Likely Cc: Linus Torvalds Cc: Mark Brown Cc: Nicolas Pitre Cc: Rob Herring Cc: Russell King Cc: Sudeep KarkadaNagesha Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: tony.luck@intel.com Cc: fenghua.yu@intel.com Cc: schwidefsky@de.ibm.com Cc: cmetcalf@tilera.com Cc: benh@kernel.crashing.org Cc: preeti@linux.vnet.ibm.com Link: http://lkml.kernel.org/r/1397209481-28542-6-git-send-email-vincent.guittot@linaro.org Signed-off-by: Ingo Molnar --- arch/arm/kernel/topology.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 0bc94b1fd1ae..71e1fec6d31a 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -185,6 +185,15 @@ const struct cpumask *cpu_coregroup_mask(int cpu) return &cpu_topology[cpu].core_sibling; } +/* + * The current assumption is that we can power gate each core independently. + * This will be superseded by DT binding once available. + */ +const struct cpumask *cpu_corepower_mask(int cpu) +{ + return &cpu_topology[cpu].thread_sibling; +} + static void update_siblings_masks(unsigned int cpuid) { struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid]; @@ -266,6 +275,20 @@ void store_cpu_topology(unsigned int cpuid) cpu_topology[cpuid].socket_id, mpidr); } +static inline const int cpu_corepower_flags(void) +{ + return SD_SHARE_PKG_RESOURCES | SD_SHARE_POWERDOMAIN; +} + +static struct sched_domain_topology_level arm_topology[] = { +#ifdef CONFIG_SCHED_MC + { cpu_corepower_mask, cpu_corepower_flags, SD_INIT_NAME(GMC) }, + { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, +#endif + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + /* * init_cpu_topology is called at boot when only one cpu is running * which prevent simultaneous write access to cpu_topology array @@ -289,4 +312,7 @@ void __init init_cpu_topology(void) smp_wmb(); parse_dt_topology(); + + /* Set scheduler topology descriptor */ + set_sched_topology(arm_topology); } -- cgit v1.2.3 From 6ce0d20016925d031f1e24d64302e4c976d7cec6 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Thu, 24 Apr 2014 11:30:05 -0400 Subject: ARM: dma: Use dma_pfn_offset for dma address translation In most of cases DMA addresses can be performed using offset value of Bus address space relatively to physical address space as following: PFN->DMA: __pfn_to_phys(pfn + [-]dma_pfn_offset) DMA->PFN: __phys_to_pfn(dma_addr) + [-]dma_pfn_offset Thanks to Russell King for suggesting the optimised macro's for conversion. Cc: Greg Kroah-Hartman Cc: Russell King Cc: Arnd Bergmann Cc: Olof Johansson Cc: Grant Likely Cc: Catalin Marinas Cc: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/include/asm/dma-mapping.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index e701a4d9aa59..b0c79fdd9375 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -58,21 +58,37 @@ static inline int dma_set_mask(struct device *dev, u64 mask) #ifndef __arch_pfn_to_dma static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn) { + if (dev) + pfn -= dev->dma_pfn_offset; return (dma_addr_t)__pfn_to_bus(pfn); } static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr) { - return __bus_to_pfn(addr); + unsigned long pfn = __bus_to_pfn(addr); + + if (dev) + pfn += dev->dma_pfn_offset; + + return pfn; } static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) { + if (dev) { + unsigned long pfn = dma_to_pfn(dev, addr); + + return phys_to_virt(__pfn_to_phys(pfn)); + } + return (void *)__bus_to_virt((unsigned long)addr); } static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) { + if (dev) + return pfn_to_dma(dev, virt_to_pfn(addr)); + return (dma_addr_t)__virt_to_bus((unsigned long)(addr)); } -- cgit v1.2.3 From 812b99e4b024d6f83e9281ec1a0bd4bf63dad90f Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 24 Apr 2014 11:30:06 -0400 Subject: ARM: dma: implement set_arch_dma_coherent_ops() Implement the set_arch_dma_coherent_ops() for ARM architecture. Cc: Greg Kroah-Hartman Cc: Russell King Cc: Arnd Bergmann Cc: Olof Johansson Cc: Grant Likely Cc: Catalin Marinas Cc: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/include/asm/dma-mapping.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index b0c79fdd9375..c45b61a4b4a5 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -121,6 +121,13 @@ static inline unsigned long dma_max_pfn(struct device *dev) } #define dma_max_pfn(dev) dma_max_pfn(dev) +static inline int set_arch_dma_coherent_ops(struct device *dev) +{ + set_dma_ops(dev, &arm_coherent_dma_ops); + return 0; +} +#define set_arch_dma_coherent_ops(dev) set_arch_dma_coherent_ops(dev) + static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) { unsigned int offset = paddr & ~PAGE_MASK; -- cgit v1.2.3 From 2161c2485d03520060f6094359b22f33913eefa2 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 24 Apr 2014 11:30:07 -0400 Subject: ARM: dma: use phys_addr_t in __dma_page_[cpu_to_dev/dev_to_cpu] On a 32 bit ARM architecture with LPAE extension physical addresses cannot fit into unsigned long variable. So fix it by using phys_addr_t instead of unsigned long. Cc: Nicolas Pitre Cc: Russell King - ARM Linux Cc: Catalin Marinas Acked-by: Will Deacon Signed-off-by: Santosh Shilimkar --- arch/arm/mm/dma-mapping.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index f62aa0677e5c..5260f43c3d03 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -885,7 +885,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset, static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, size_t size, enum dma_data_direction dir) { - unsigned long paddr; + phys_addr_t paddr; dma_cache_maint_page(page, off, size, dir, dmac_map_area); @@ -901,7 +901,7 @@ static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, size_t size, enum dma_data_direction dir) { - unsigned long paddr = page_to_phys(page) + off; + phys_addr_t paddr = page_to_phys(page) + off; /* FIXME: non-speculating: not required */ /* don't bother invalidating if DMA to device */ -- cgit v1.2.3 From a4ab9d0cf1ef0bf521bb69099aa464f38c71393c Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Wed, 7 May 2014 15:32:49 +0300 Subject: KVM: vmx: handle_dr does not handle RSP correctly The RSP register is not automatically cached, causing mov DR instruction with RSP to fail. Instead the regular register accessing interface should be used. Signed-off-by: Nadav Amit Signed-off-by: Paolo Bonzini --- arch/x86/kvm/vmx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index a5fd47e4abfc..61e818d80732 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -5143,7 +5143,7 @@ static int handle_dr(struct kvm_vcpu *vcpu) return 1; kvm_register_write(vcpu, reg, val); } else - if (kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg])) + if (kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg))) return 1; skip_emulated_instruction(vcpu); -- cgit v1.2.3 From 5f7dde7bbb3c628766676cbd63c0a1834035d6fa Mon Sep 17 00:00:00 2001 From: Nadav Amit Date: Wed, 7 May 2014 15:32:50 +0300 Subject: KVM: x86: Mark bit 7 in long-mode PDPTE according to 1GB pages support In long-mode, bit 7 in the PDPTE is not reserved only if 1GB pages are supported by the CPU. Currently the bit is considered by KVM as always reserved. Signed-off-by: Nadav Amit Signed-off-by: Paolo Bonzini --- arch/x86/kvm/cpuid.h | 7 +++++++ arch/x86/kvm/mmu.c | 8 ++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h index eeecbed26ac7..f9087315e0cd 100644 --- a/arch/x86/kvm/cpuid.h +++ b/arch/x86/kvm/cpuid.h @@ -88,4 +88,11 @@ static inline bool guest_cpuid_has_x2apic(struct kvm_vcpu *vcpu) return best && (best->ecx & bit(X86_FEATURE_X2APIC)); } +static inline bool guest_cpuid_has_gbpages(struct kvm_vcpu *vcpu) +{ + struct kvm_cpuid_entry2 *best; + + best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0); + return best && (best->edx & bit(X86_FEATURE_GBPAGES)); +} #endif diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index 65f2400b8268..931467881da7 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -22,6 +22,7 @@ #include "mmu.h" #include "x86.h" #include "kvm_cache_regs.h" +#include "cpuid.h" #include #include @@ -3516,11 +3517,14 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, { int maxphyaddr = cpuid_maxphyaddr(vcpu); u64 exb_bit_rsvd = 0; + u64 gbpages_bit_rsvd = 0; context->bad_mt_xwr = 0; if (!context->nx) exb_bit_rsvd = rsvd_bits(63, 63); + if (!guest_cpuid_has_gbpages(vcpu)) + gbpages_bit_rsvd = rsvd_bits(7, 7); switch (context->root_level) { case PT32_ROOT_LEVEL: /* no rsvd bits for 2 level 4K page table entries */ @@ -3557,14 +3561,14 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, context->rsvd_bits_mask[0][3] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7); context->rsvd_bits_mask[0][2] = exb_bit_rsvd | - rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 7); + gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51); context->rsvd_bits_mask[0][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51); context->rsvd_bits_mask[0][0] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51); context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3]; context->rsvd_bits_mask[1][2] = exb_bit_rsvd | - rsvd_bits(maxphyaddr, 51) | + gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | rsvd_bits(13, 29); context->rsvd_bits_mask[1][1] = exb_bit_rsvd | rsvd_bits(maxphyaddr, 51) | -- cgit v1.2.3 From 498bb3da7e04ed82d9b66106c4baeb3000a7100e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 6 May 2014 17:04:11 +0200 Subject: ARM: tegra: Support reboot modes The boot ROM on Tegra SoCs supports booting into forced recovery mode (RCM) by setting a bit in the PMC scratch register 0. Similarily, the Android bootloader examines some of the bits in this register to disable autoboot or enter recovery mode. Support these modes by setting the corresponding bits depending on the specified reboot command (forced-recovery, bootloader, recovery). Recent systemd-based distributions allow this to be specified using an optional argument to the reboot command. Signed-off-by: Thierry Reding Tested-by: Alexandre Courbot Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/pmc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c index fb7920201ab4..7c7123e7557b 100644 --- a/arch/arm/mach-tegra/pmc.c +++ b/arch/arm/mach-tegra/pmc.c @@ -41,6 +41,14 @@ #define PMC_REMOVE_CLAMPING 0x34 #define PMC_PWRGATE_STATUS 0x38 +#define PMC_SCRATCH0 0x50 +#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) +#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) +#define PMC_SCRATCH0_MODE_RCM (1 << 1) +#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ + PMC_SCRATCH0_MODE_BOOTLOADER | \ + PMC_SCRATCH0_MODE_RCM) + #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc @@ -165,6 +173,22 @@ void tegra_pmc_restart(enum reboot_mode mode, const char *cmd) { u32 val; + val = tegra_pmc_readl(PMC_SCRATCH0); + val &= ~PMC_SCRATCH0_MODE_MASK; + + if (cmd) { + if (strcmp(cmd, "recovery") == 0) + val |= PMC_SCRATCH0_MODE_RECOVERY; + + if (strcmp(cmd, "bootloader") == 0) + val |= PMC_SCRATCH0_MODE_BOOTLOADER; + + if (strcmp(cmd, "forced-recovery") == 0) + val |= PMC_SCRATCH0_MODE_RCM; + } + + tegra_pmc_writel(val, PMC_SCRATCH0); + val = tegra_pmc_readl(0); val |= 0x10; tegra_pmc_writel(val, 0); -- cgit v1.2.3 From b63cf42fd1d8c18fab71222321aaf356f63089c9 Mon Sep 17 00:00:00 2001 From: "Michael S. Tsirkin" Date: Wed, 7 May 2014 16:29:48 +0300 Subject: kvm/x86: implement hv EOI assist It seems that it's easy to implement the EOI assist on top of the PV EOI feature: simply convert the page address to the format expected by PV EOI. Notes: -"No EOI required" is set only if interrupt injected is edge triggered; this is true because level interrupts are going through IOAPIC which disables PV EOI. In any case, if guest triggers EOI the bit will get cleared on exit. -For migration, set of HV_X64_MSR_APIC_ASSIST_PAGE sets KVM_PV_EOI_EN internally, so restoring HV_X64_MSR_APIC_ASSIST_PAGE seems sufficient In any case, bit is cleared on exit so worst case it's never re-enabled -no handling of PV EOI data is performed at HV_X64_MSR_EOI write; HV_X64_MSR_EOI is a separate optimization - it's an X2APIC replacement that lets you do EOI with an MSR and not IO. Signed-off-by: Michael S. Tsirkin Signed-off-by: Paolo Bonzini --- arch/x86/kvm/x86.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index de0931cb3f58..41f673facf2f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1917,6 +1917,8 @@ static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) { vcpu->arch.hv_vapic = data; + if (kvm_lapic_enable_pv_eoi(vcpu, 0)) + return 1; break; } gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT; @@ -1927,6 +1929,8 @@ static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data) return 1; vcpu->arch.hv_vapic = data; mark_page_dirty(vcpu->kvm, gfn); + if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED)) + return 1; break; } case HV_X64_MSR_EOI: -- cgit v1.2.3 From cf2e933ce6da2a8bacd52e49c4dd4c0974af1d09 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 27 Mar 2014 14:18:51 +0100 Subject: ARM: at91: localize GPIO header This moves the header in the AT91 platform down into the machine directory and removes the reliance on MACH_NEED_GPIO_H from the AT91. This does not move the platform to GENERIC_GPIO but localize the remaining work to be done for this to the mach-at91 folder. Signed-off-by: Linus Walleij [nicolas.ferre@atmel.com: adapt to newer kernel, add rsi-ews board] Signed-off-by: Nicolas Ferre --- arch/arm/Kconfig | 1 - arch/arm/mach-at91/at91rm9200_devices.c | 1 + arch/arm/mach-at91/at91sam9260_devices.c | 2 +- arch/arm/mach-at91/at91sam9261_devices.c | 2 +- arch/arm/mach-at91/at91sam9263_devices.c | 1 + arch/arm/mach-at91/at91sam9g45_devices.c | 1 + arch/arm/mach-at91/at91sam9rl_devices.c | 1 + arch/arm/mach-at91/board-1arm.c | 2 +- arch/arm/mach-at91/board-afeb-9260v1.c | 1 + arch/arm/mach-at91/board-cam60.c | 1 + arch/arm/mach-at91/board-carmeva.c | 1 + arch/arm/mach-at91/board-cpu9krea.c | 1 + arch/arm/mach-at91/board-cpuat91.c | 2 + arch/arm/mach-at91/board-csb337.c | 2 +- arch/arm/mach-at91/board-csb637.c | 1 + arch/arm/mach-at91/board-eb9200.c | 1 + arch/arm/mach-at91/board-ecbat91.c | 1 + arch/arm/mach-at91/board-eco920.c | 2 + arch/arm/mach-at91/board-flexibity.c | 1 + arch/arm/mach-at91/board-foxg20.c | 1 + arch/arm/mach-at91/board-gsia18s.c | 1 + arch/arm/mach-at91/board-kafa.c | 1 + arch/arm/mach-at91/board-kb9202.c | 1 + arch/arm/mach-at91/board-pcontrol-g20.c | 1 + arch/arm/mach-at91/board-picotux200.c | 1 + arch/arm/mach-at91/board-rm9200ek.c | 1 + arch/arm/mach-at91/board-rsi-ews.c | 1 + arch/arm/mach-at91/board-sam9-l9260.c | 1 + arch/arm/mach-at91/board-sam9260ek.c | 1 + arch/arm/mach-at91/board-sam9261ek.c | 1 + arch/arm/mach-at91/board-sam9263ek.c | 1 + arch/arm/mach-at91/board-sam9g20ek.c | 1 + arch/arm/mach-at91/board-sam9m10g45ek.c | 1 + arch/arm/mach-at91/board-sam9rlek.c | 1 + arch/arm/mach-at91/board-snapper9260.c | 1 + arch/arm/mach-at91/board-stamp9g20.c | 1 + arch/arm/mach-at91/board-yl-9200.c | 1 + arch/arm/mach-at91/gpio.c | 1 + arch/arm/mach-at91/gpio.h | 214 +++++++++++++++++++++++++++ arch/arm/mach-at91/include/mach/gpio.h | 222 ----------------------------- arch/arm/mach-at91/include/mach/hardware.h | 15 ++ arch/arm/mach-at91/leds.c | 1 + arch/arm/mach-at91/pm.c | 1 + 43 files changed, 270 insertions(+), 227 deletions(-) create mode 100644 arch/arm/mach-at91/gpio.h delete mode 100644 arch/arm/mach-at91/include/mach/gpio.h (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index db3c5414223e..1c1fbbf6e4ae 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -376,7 +376,6 @@ config ARCH_AT91 select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP select IRQ_DOMAIN - select NEED_MACH_GPIO_H select NEED_MACH_IO_H if PCCARD select PINCTRL select PINCTRL_AT91 if USE_OF diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index f3f19f21352a..4860918b411e 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -25,6 +25,7 @@ #include "board.h" #include "generic.h" +#include "gpio.h" /* -------------------------------------------------------------------- diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index a0282928e9c1..df5a7d83d37d 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -29,7 +29,7 @@ #include "board.h" #include "generic.h" - +#include "gpio.h" /* -------------------------------------------------------------------- * USB Host diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 80e35895d28f..43b21f456f6e 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -29,7 +29,7 @@ #include "board.h" #include "generic.h" - +#include "gpio.h" /* -------------------------------------------------------------------- * USB Host diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 43d53d6156dd..953616e5dbcb 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -28,6 +28,7 @@ #include "board.h" #include "generic.h" +#include "gpio.h" /* -------------------------------------------------------------------- diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index dab362c06487..7f02a5366a31 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -39,6 +39,7 @@ #include "board.h" #include "generic.h" #include "clock.h" +#include "gpio.h" /* -------------------------------------------------------------------- diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 428fc412aaf1..ba7ebd9dd4bb 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -26,6 +26,7 @@ #include "board.h" #include "generic.h" +#include "gpio.h" /* -------------------------------------------------------------------- diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index 35ab632bbf68..3f6dbcc34022 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c @@ -39,7 +39,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" - +#include "gpio.h" static void __init onearm_init_early(void) { diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index f95e31cda4b3..597c649170aa 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c @@ -46,6 +46,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init afeb9260_init_early(void) diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 112e867c4abe..a30502c8d379 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c @@ -44,6 +44,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init cam60_init_early(void) diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 92983050a9bd..47313d3ee037 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c @@ -39,6 +39,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init carmeva_init_early(void) diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 008527efdbcf..2037f78c84e7 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c @@ -48,6 +48,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init cpu9krea_init_early(void) { diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index 42f1353a4baf..c094350c9314 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c @@ -43,6 +43,8 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" + static struct gpio_led cpuat91_leds[] = { { diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index e5fde215225b..0e35a45cf8d4 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c @@ -42,7 +42,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" - +#include "gpio.h" static void __init csb337_init_early(void) { diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index fdf11061c577..18d027f529a8 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c @@ -39,6 +39,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init csb637_init_early(void) diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index f9be8161bbfa..aa457a8b22f5 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c @@ -38,6 +38,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init eb9200_init_early(void) diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index b2fcd71262ba..ede1373ccaba 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c @@ -42,6 +42,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init ecb_at91init_early(void) diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index 77de410efc90..4e75321a8f2a 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c @@ -31,6 +31,8 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" + static void __init eco920_init_early(void) { diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 737c08563628..68f1ab6bd08f 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c @@ -37,6 +37,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init flexibity_init_early(void) { diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index c20a870ea9c9..8b22c60bb238 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c @@ -47,6 +47,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" /* * The FOX Board G20 hardware comes as the "Netus G20" board with diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 416bae8435ee..b729dd1271bf 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c @@ -39,6 +39,7 @@ #include "generic.h" #include "gsia18s.h" #include "stamp9g20.h" +#include "gpio.h" static void __init gsia18s_init_early(void) { diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index 88e2f5d2d16d..93b1df42f639 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c @@ -39,6 +39,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init kafa_init_early(void) diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index 0c519d9ebffc..d58d36225e08 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c @@ -42,6 +42,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init kb9202_init_early(void) diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 5f25fa54eb93..b48d95ec5152 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c @@ -37,6 +37,7 @@ #include "sam9_smc.h" #include "generic.h" #include "stamp9g20.h" +#include "gpio.h" static void __init pcontrol_g20_init_early(void) diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index ab2b2ec36c14..2c0f2d554d84 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c @@ -43,6 +43,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init picotux200_init_early(void) diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 8b17dadc1aba..953cea416754 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c @@ -45,6 +45,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index f6d7f1958c7e..f28e8b74df4b 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c @@ -31,6 +31,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init rsi_ews_init_early(void) { diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index 43ee4dc43b50..d24dda67e2d3 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c @@ -43,6 +43,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index f4f8735315da..65dea12d685e 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c @@ -49,6 +49,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 473546b9408b..4637432de08f 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c @@ -53,6 +53,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 2f931915c80c..cd2726ee5add 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c @@ -52,6 +52,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index f9cd1f2c7146..e1be6e25b380 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -50,6 +50,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" /* * board revision encoding diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index ef39078c8ce2..5cd95ede623e 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -50,6 +50,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index 604eecf6cd70..6b81e4671646 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c @@ -38,6 +38,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" static void __init ek_init_early(void) diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index f1d49e929ccb..1b870e6def0c 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c @@ -38,6 +38,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" #define SNAPPER9260_IO_EXP_GPIO(x) (NR_BUILTIN_GPIO + (x)) diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index e4a5ac17cdbc..3b575036ff96 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c @@ -32,6 +32,7 @@ #include "board.h" #include "sam9_smc.h" #include "generic.h" +#include "gpio.h" void __init stamp9g20_init_early(void) diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index be083771df2e..46fdb0c68a68 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c @@ -50,6 +50,7 @@ #include "at91_aic.h" #include "board.h" #include "generic.h" +#include "gpio.h" static void __init yl9200_init_early(void) diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index a5afcf76550e..12ed05bbdc5c 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -29,6 +29,7 @@ #include #include "generic.h" +#include "gpio.h" #define MAX_NB_GPIO_PER_BANK 32 diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h new file mode 100644 index 000000000000..eed465ab0dd7 --- /dev/null +++ b/arch/arm/mach-at91/gpio.h @@ -0,0 +1,214 @@ +/* + * arch/arm/mach-at91/include/mach/gpio.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91RM9200_GPIO_H +#define __ASM_ARCH_AT91RM9200_GPIO_H + +#include +#include + +#define MAX_GPIO_BANKS 5 +#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32) + +/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ + +#define AT91_PIN_PA0 (0x00 + 0) +#define AT91_PIN_PA1 (0x00 + 1) +#define AT91_PIN_PA2 (0x00 + 2) +#define AT91_PIN_PA3 (0x00 + 3) +#define AT91_PIN_PA4 (0x00 + 4) +#define AT91_PIN_PA5 (0x00 + 5) +#define AT91_PIN_PA6 (0x00 + 6) +#define AT91_PIN_PA7 (0x00 + 7) +#define AT91_PIN_PA8 (0x00 + 8) +#define AT91_PIN_PA9 (0x00 + 9) +#define AT91_PIN_PA10 (0x00 + 10) +#define AT91_PIN_PA11 (0x00 + 11) +#define AT91_PIN_PA12 (0x00 + 12) +#define AT91_PIN_PA13 (0x00 + 13) +#define AT91_PIN_PA14 (0x00 + 14) +#define AT91_PIN_PA15 (0x00 + 15) +#define AT91_PIN_PA16 (0x00 + 16) +#define AT91_PIN_PA17 (0x00 + 17) +#define AT91_PIN_PA18 (0x00 + 18) +#define AT91_PIN_PA19 (0x00 + 19) +#define AT91_PIN_PA20 (0x00 + 20) +#define AT91_PIN_PA21 (0x00 + 21) +#define AT91_PIN_PA22 (0x00 + 22) +#define AT91_PIN_PA23 (0x00 + 23) +#define AT91_PIN_PA24 (0x00 + 24) +#define AT91_PIN_PA25 (0x00 + 25) +#define AT91_PIN_PA26 (0x00 + 26) +#define AT91_PIN_PA27 (0x00 + 27) +#define AT91_PIN_PA28 (0x00 + 28) +#define AT91_PIN_PA29 (0x00 + 29) +#define AT91_PIN_PA30 (0x00 + 30) +#define AT91_PIN_PA31 (0x00 + 31) + +#define AT91_PIN_PB0 (0x20 + 0) +#define AT91_PIN_PB1 (0x20 + 1) +#define AT91_PIN_PB2 (0x20 + 2) +#define AT91_PIN_PB3 (0x20 + 3) +#define AT91_PIN_PB4 (0x20 + 4) +#define AT91_PIN_PB5 (0x20 + 5) +#define AT91_PIN_PB6 (0x20 + 6) +#define AT91_PIN_PB7 (0x20 + 7) +#define AT91_PIN_PB8 (0x20 + 8) +#define AT91_PIN_PB9 (0x20 + 9) +#define AT91_PIN_PB10 (0x20 + 10) +#define AT91_PIN_PB11 (0x20 + 11) +#define AT91_PIN_PB12 (0x20 + 12) +#define AT91_PIN_PB13 (0x20 + 13) +#define AT91_PIN_PB14 (0x20 + 14) +#define AT91_PIN_PB15 (0x20 + 15) +#define AT91_PIN_PB16 (0x20 + 16) +#define AT91_PIN_PB17 (0x20 + 17) +#define AT91_PIN_PB18 (0x20 + 18) +#define AT91_PIN_PB19 (0x20 + 19) +#define AT91_PIN_PB20 (0x20 + 20) +#define AT91_PIN_PB21 (0x20 + 21) +#define AT91_PIN_PB22 (0x20 + 22) +#define AT91_PIN_PB23 (0x20 + 23) +#define AT91_PIN_PB24 (0x20 + 24) +#define AT91_PIN_PB25 (0x20 + 25) +#define AT91_PIN_PB26 (0x20 + 26) +#define AT91_PIN_PB27 (0x20 + 27) +#define AT91_PIN_PB28 (0x20 + 28) +#define AT91_PIN_PB29 (0x20 + 29) +#define AT91_PIN_PB30 (0x20 + 30) +#define AT91_PIN_PB31 (0x20 + 31) + +#define AT91_PIN_PC0 (0x40 + 0) +#define AT91_PIN_PC1 (0x40 + 1) +#define AT91_PIN_PC2 (0x40 + 2) +#define AT91_PIN_PC3 (0x40 + 3) +#define AT91_PIN_PC4 (0x40 + 4) +#define AT91_PIN_PC5 (0x40 + 5) +#define AT91_PIN_PC6 (0x40 + 6) +#define AT91_PIN_PC7 (0x40 + 7) +#define AT91_PIN_PC8 (0x40 + 8) +#define AT91_PIN_PC9 (0x40 + 9) +#define AT91_PIN_PC10 (0x40 + 10) +#define AT91_PIN_PC11 (0x40 + 11) +#define AT91_PIN_PC12 (0x40 + 12) +#define AT91_PIN_PC13 (0x40 + 13) +#define AT91_PIN_PC14 (0x40 + 14) +#define AT91_PIN_PC15 (0x40 + 15) +#define AT91_PIN_PC16 (0x40 + 16) +#define AT91_PIN_PC17 (0x40 + 17) +#define AT91_PIN_PC18 (0x40 + 18) +#define AT91_PIN_PC19 (0x40 + 19) +#define AT91_PIN_PC20 (0x40 + 20) +#define AT91_PIN_PC21 (0x40 + 21) +#define AT91_PIN_PC22 (0x40 + 22) +#define AT91_PIN_PC23 (0x40 + 23) +#define AT91_PIN_PC24 (0x40 + 24) +#define AT91_PIN_PC25 (0x40 + 25) +#define AT91_PIN_PC26 (0x40 + 26) +#define AT91_PIN_PC27 (0x40 + 27) +#define AT91_PIN_PC28 (0x40 + 28) +#define AT91_PIN_PC29 (0x40 + 29) +#define AT91_PIN_PC30 (0x40 + 30) +#define AT91_PIN_PC31 (0x40 + 31) + +#define AT91_PIN_PD0 (0x60 + 0) +#define AT91_PIN_PD1 (0x60 + 1) +#define AT91_PIN_PD2 (0x60 + 2) +#define AT91_PIN_PD3 (0x60 + 3) +#define AT91_PIN_PD4 (0x60 + 4) +#define AT91_PIN_PD5 (0x60 + 5) +#define AT91_PIN_PD6 (0x60 + 6) +#define AT91_PIN_PD7 (0x60 + 7) +#define AT91_PIN_PD8 (0x60 + 8) +#define AT91_PIN_PD9 (0x60 + 9) +#define AT91_PIN_PD10 (0x60 + 10) +#define AT91_PIN_PD11 (0x60 + 11) +#define AT91_PIN_PD12 (0x60 + 12) +#define AT91_PIN_PD13 (0x60 + 13) +#define AT91_PIN_PD14 (0x60 + 14) +#define AT91_PIN_PD15 (0x60 + 15) +#define AT91_PIN_PD16 (0x60 + 16) +#define AT91_PIN_PD17 (0x60 + 17) +#define AT91_PIN_PD18 (0x60 + 18) +#define AT91_PIN_PD19 (0x60 + 19) +#define AT91_PIN_PD20 (0x60 + 20) +#define AT91_PIN_PD21 (0x60 + 21) +#define AT91_PIN_PD22 (0x60 + 22) +#define AT91_PIN_PD23 (0x60 + 23) +#define AT91_PIN_PD24 (0x60 + 24) +#define AT91_PIN_PD25 (0x60 + 25) +#define AT91_PIN_PD26 (0x60 + 26) +#define AT91_PIN_PD27 (0x60 + 27) +#define AT91_PIN_PD28 (0x60 + 28) +#define AT91_PIN_PD29 (0x60 + 29) +#define AT91_PIN_PD30 (0x60 + 30) +#define AT91_PIN_PD31 (0x60 + 31) + +#define AT91_PIN_PE0 (0x80 + 0) +#define AT91_PIN_PE1 (0x80 + 1) +#define AT91_PIN_PE2 (0x80 + 2) +#define AT91_PIN_PE3 (0x80 + 3) +#define AT91_PIN_PE4 (0x80 + 4) +#define AT91_PIN_PE5 (0x80 + 5) +#define AT91_PIN_PE6 (0x80 + 6) +#define AT91_PIN_PE7 (0x80 + 7) +#define AT91_PIN_PE8 (0x80 + 8) +#define AT91_PIN_PE9 (0x80 + 9) +#define AT91_PIN_PE10 (0x80 + 10) +#define AT91_PIN_PE11 (0x80 + 11) +#define AT91_PIN_PE12 (0x80 + 12) +#define AT91_PIN_PE13 (0x80 + 13) +#define AT91_PIN_PE14 (0x80 + 14) +#define AT91_PIN_PE15 (0x80 + 15) +#define AT91_PIN_PE16 (0x80 + 16) +#define AT91_PIN_PE17 (0x80 + 17) +#define AT91_PIN_PE18 (0x80 + 18) +#define AT91_PIN_PE19 (0x80 + 19) +#define AT91_PIN_PE20 (0x80 + 20) +#define AT91_PIN_PE21 (0x80 + 21) +#define AT91_PIN_PE22 (0x80 + 22) +#define AT91_PIN_PE23 (0x80 + 23) +#define AT91_PIN_PE24 (0x80 + 24) +#define AT91_PIN_PE25 (0x80 + 25) +#define AT91_PIN_PE26 (0x80 + 26) +#define AT91_PIN_PE27 (0x80 + 27) +#define AT91_PIN_PE28 (0x80 + 28) +#define AT91_PIN_PE29 (0x80 + 29) +#define AT91_PIN_PE30 (0x80 + 30) +#define AT91_PIN_PE31 (0x80 + 31) + +#ifndef __ASSEMBLY__ +/* setup setup routines, called from board init or driver probe() */ +extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); +extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); +extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); +extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div); +extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); +extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on); +extern int __init_or_module at91_disable_schmitt_trig(unsigned pin); + +/* callable at any time */ +extern int at91_set_gpio_value(unsigned pin, int value); +extern int at91_get_gpio_value(unsigned pin); + +/* callable only from core power-management code */ +extern void at91_gpio_suspend(void); +extern void at91_gpio_resume(void); + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h deleted file mode 100644 index 5fc23771c154..000000000000 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/gpio.h - * - * Copyright (C) 2005 HP Labs - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#ifndef __ASM_ARCH_AT91RM9200_GPIO_H -#define __ASM_ARCH_AT91RM9200_GPIO_H - -#include -#include - -#define MAX_GPIO_BANKS 5 -#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32) - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ - -#define AT91_PIN_PA0 (0x00 + 0) -#define AT91_PIN_PA1 (0x00 + 1) -#define AT91_PIN_PA2 (0x00 + 2) -#define AT91_PIN_PA3 (0x00 + 3) -#define AT91_PIN_PA4 (0x00 + 4) -#define AT91_PIN_PA5 (0x00 + 5) -#define AT91_PIN_PA6 (0x00 + 6) -#define AT91_PIN_PA7 (0x00 + 7) -#define AT91_PIN_PA8 (0x00 + 8) -#define AT91_PIN_PA9 (0x00 + 9) -#define AT91_PIN_PA10 (0x00 + 10) -#define AT91_PIN_PA11 (0x00 + 11) -#define AT91_PIN_PA12 (0x00 + 12) -#define AT91_PIN_PA13 (0x00 + 13) -#define AT91_PIN_PA14 (0x00 + 14) -#define AT91_PIN_PA15 (0x00 + 15) -#define AT91_PIN_PA16 (0x00 + 16) -#define AT91_PIN_PA17 (0x00 + 17) -#define AT91_PIN_PA18 (0x00 + 18) -#define AT91_PIN_PA19 (0x00 + 19) -#define AT91_PIN_PA20 (0x00 + 20) -#define AT91_PIN_PA21 (0x00 + 21) -#define AT91_PIN_PA22 (0x00 + 22) -#define AT91_PIN_PA23 (0x00 + 23) -#define AT91_PIN_PA24 (0x00 + 24) -#define AT91_PIN_PA25 (0x00 + 25) -#define AT91_PIN_PA26 (0x00 + 26) -#define AT91_PIN_PA27 (0x00 + 27) -#define AT91_PIN_PA28 (0x00 + 28) -#define AT91_PIN_PA29 (0x00 + 29) -#define AT91_PIN_PA30 (0x00 + 30) -#define AT91_PIN_PA31 (0x00 + 31) - -#define AT91_PIN_PB0 (0x20 + 0) -#define AT91_PIN_PB1 (0x20 + 1) -#define AT91_PIN_PB2 (0x20 + 2) -#define AT91_PIN_PB3 (0x20 + 3) -#define AT91_PIN_PB4 (0x20 + 4) -#define AT91_PIN_PB5 (0x20 + 5) -#define AT91_PIN_PB6 (0x20 + 6) -#define AT91_PIN_PB7 (0x20 + 7) -#define AT91_PIN_PB8 (0x20 + 8) -#define AT91_PIN_PB9 (0x20 + 9) -#define AT91_PIN_PB10 (0x20 + 10) -#define AT91_PIN_PB11 (0x20 + 11) -#define AT91_PIN_PB12 (0x20 + 12) -#define AT91_PIN_PB13 (0x20 + 13) -#define AT91_PIN_PB14 (0x20 + 14) -#define AT91_PIN_PB15 (0x20 + 15) -#define AT91_PIN_PB16 (0x20 + 16) -#define AT91_PIN_PB17 (0x20 + 17) -#define AT91_PIN_PB18 (0x20 + 18) -#define AT91_PIN_PB19 (0x20 + 19) -#define AT91_PIN_PB20 (0x20 + 20) -#define AT91_PIN_PB21 (0x20 + 21) -#define AT91_PIN_PB22 (0x20 + 22) -#define AT91_PIN_PB23 (0x20 + 23) -#define AT91_PIN_PB24 (0x20 + 24) -#define AT91_PIN_PB25 (0x20 + 25) -#define AT91_PIN_PB26 (0x20 + 26) -#define AT91_PIN_PB27 (0x20 + 27) -#define AT91_PIN_PB28 (0x20 + 28) -#define AT91_PIN_PB29 (0x20 + 29) -#define AT91_PIN_PB30 (0x20 + 30) -#define AT91_PIN_PB31 (0x20 + 31) - -#define AT91_PIN_PC0 (0x40 + 0) -#define AT91_PIN_PC1 (0x40 + 1) -#define AT91_PIN_PC2 (0x40 + 2) -#define AT91_PIN_PC3 (0x40 + 3) -#define AT91_PIN_PC4 (0x40 + 4) -#define AT91_PIN_PC5 (0x40 + 5) -#define AT91_PIN_PC6 (0x40 + 6) -#define AT91_PIN_PC7 (0x40 + 7) -#define AT91_PIN_PC8 (0x40 + 8) -#define AT91_PIN_PC9 (0x40 + 9) -#define AT91_PIN_PC10 (0x40 + 10) -#define AT91_PIN_PC11 (0x40 + 11) -#define AT91_PIN_PC12 (0x40 + 12) -#define AT91_PIN_PC13 (0x40 + 13) -#define AT91_PIN_PC14 (0x40 + 14) -#define AT91_PIN_PC15 (0x40 + 15) -#define AT91_PIN_PC16 (0x40 + 16) -#define AT91_PIN_PC17 (0x40 + 17) -#define AT91_PIN_PC18 (0x40 + 18) -#define AT91_PIN_PC19 (0x40 + 19) -#define AT91_PIN_PC20 (0x40 + 20) -#define AT91_PIN_PC21 (0x40 + 21) -#define AT91_PIN_PC22 (0x40 + 22) -#define AT91_PIN_PC23 (0x40 + 23) -#define AT91_PIN_PC24 (0x40 + 24) -#define AT91_PIN_PC25 (0x40 + 25) -#define AT91_PIN_PC26 (0x40 + 26) -#define AT91_PIN_PC27 (0x40 + 27) -#define AT91_PIN_PC28 (0x40 + 28) -#define AT91_PIN_PC29 (0x40 + 29) -#define AT91_PIN_PC30 (0x40 + 30) -#define AT91_PIN_PC31 (0x40 + 31) - -#define AT91_PIN_PD0 (0x60 + 0) -#define AT91_PIN_PD1 (0x60 + 1) -#define AT91_PIN_PD2 (0x60 + 2) -#define AT91_PIN_PD3 (0x60 + 3) -#define AT91_PIN_PD4 (0x60 + 4) -#define AT91_PIN_PD5 (0x60 + 5) -#define AT91_PIN_PD6 (0x60 + 6) -#define AT91_PIN_PD7 (0x60 + 7) -#define AT91_PIN_PD8 (0x60 + 8) -#define AT91_PIN_PD9 (0x60 + 9) -#define AT91_PIN_PD10 (0x60 + 10) -#define AT91_PIN_PD11 (0x60 + 11) -#define AT91_PIN_PD12 (0x60 + 12) -#define AT91_PIN_PD13 (0x60 + 13) -#define AT91_PIN_PD14 (0x60 + 14) -#define AT91_PIN_PD15 (0x60 + 15) -#define AT91_PIN_PD16 (0x60 + 16) -#define AT91_PIN_PD17 (0x60 + 17) -#define AT91_PIN_PD18 (0x60 + 18) -#define AT91_PIN_PD19 (0x60 + 19) -#define AT91_PIN_PD20 (0x60 + 20) -#define AT91_PIN_PD21 (0x60 + 21) -#define AT91_PIN_PD22 (0x60 + 22) -#define AT91_PIN_PD23 (0x60 + 23) -#define AT91_PIN_PD24 (0x60 + 24) -#define AT91_PIN_PD25 (0x60 + 25) -#define AT91_PIN_PD26 (0x60 + 26) -#define AT91_PIN_PD27 (0x60 + 27) -#define AT91_PIN_PD28 (0x60 + 28) -#define AT91_PIN_PD29 (0x60 + 29) -#define AT91_PIN_PD30 (0x60 + 30) -#define AT91_PIN_PD31 (0x60 + 31) - -#define AT91_PIN_PE0 (0x80 + 0) -#define AT91_PIN_PE1 (0x80 + 1) -#define AT91_PIN_PE2 (0x80 + 2) -#define AT91_PIN_PE3 (0x80 + 3) -#define AT91_PIN_PE4 (0x80 + 4) -#define AT91_PIN_PE5 (0x80 + 5) -#define AT91_PIN_PE6 (0x80 + 6) -#define AT91_PIN_PE7 (0x80 + 7) -#define AT91_PIN_PE8 (0x80 + 8) -#define AT91_PIN_PE9 (0x80 + 9) -#define AT91_PIN_PE10 (0x80 + 10) -#define AT91_PIN_PE11 (0x80 + 11) -#define AT91_PIN_PE12 (0x80 + 12) -#define AT91_PIN_PE13 (0x80 + 13) -#define AT91_PIN_PE14 (0x80 + 14) -#define AT91_PIN_PE15 (0x80 + 15) -#define AT91_PIN_PE16 (0x80 + 16) -#define AT91_PIN_PE17 (0x80 + 17) -#define AT91_PIN_PE18 (0x80 + 18) -#define AT91_PIN_PE19 (0x80 + 19) -#define AT91_PIN_PE20 (0x80 + 20) -#define AT91_PIN_PE21 (0x80 + 21) -#define AT91_PIN_PE22 (0x80 + 22) -#define AT91_PIN_PE23 (0x80 + 23) -#define AT91_PIN_PE24 (0x80 + 24) -#define AT91_PIN_PE25 (0x80 + 25) -#define AT91_PIN_PE26 (0x80 + 26) -#define AT91_PIN_PE27 (0x80 + 27) -#define AT91_PIN_PE28 (0x80 + 28) -#define AT91_PIN_PE29 (0x80 + 29) -#define AT91_PIN_PE30 (0x80 + 30) -#define AT91_PIN_PE31 (0x80 + 31) - -#ifndef __ASSEMBLY__ -/* setup setup routines, called from board init or driver probe() */ -extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); -extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); -extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); -extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div); -extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); -extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on); -extern int __init_or_module at91_disable_schmitt_trig(unsigned pin); - -/* callable at any time */ -extern int at91_set_gpio_value(unsigned pin, int value); -extern int at91_get_gpio_value(unsigned pin); - -/* callable only from core power-management code */ -extern void at91_gpio_suspend(void); -extern void at91_gpio_resume(void); - -#ifdef CONFIG_PINCTRL_AT91 -extern void at91_pinctrl_gpio_suspend(void); -extern void at91_pinctrl_gpio_resume(void); -#else -static inline void at91_pinctrl_gpio_suspend(void) {} -static inline void at91_pinctrl_gpio_resume(void) {} -#endif - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index f17aa3150019..56338245653a 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -104,5 +104,20 @@ /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ +/* + * FIXME: this is needed to communicate between the pinctrl driver and + * the PM implementation in the machine. Possibly part of the PM + * implementation should be moved down into the pinctrl driver and get + * called as part of the generic suspend/resume path. + */ +#ifndef __ASSEMBLY__ +#ifdef CONFIG_PINCTRL_AT91 +extern void at91_pinctrl_gpio_suspend(void); +extern void at91_pinctrl_gpio_resume(void); +#else +static inline void at91_pinctrl_gpio_suspend(void) {} +static inline void at91_pinctrl_gpio_resume(void) {} +#endif +#endif #endif diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c index 3e22978b5547..77c4d8fd03fd 100644 --- a/arch/arm/mach-at91/leds.c +++ b/arch/arm/mach-at91/leds.c @@ -16,6 +16,7 @@ #include #include "board.h" +#include "gpio.h" /* ------------------------------------------------------------------------- */ diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 8bda1cefdf96..e95554532987 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -32,6 +32,7 @@ #include "at91_aic.h" #include "generic.h" #include "pm.h" +#include "gpio.h" /* * Show the reason for the previous system reset. -- cgit v1.2.3 From 4753219dd3df5cc069336ff419c06c2a1e84ca5d Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:34 +0200 Subject: ARM: at91/dt: move sama5d3 SoC to the new main/slow clk model Replace the old main and clk definitions (fixed rate clk) by the new main and slow clk subtree definition (ck = mux(rc_osc, osc)). Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3.dtsi | 61 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 55 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index eabcfdbb403a..ceb274f24dbf 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -58,6 +58,18 @@ reg = <0x20000000 0x8000000>; }; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + clocks { adc_op_clk: adc_op_clk{ compatible = "fixed-clock"; @@ -749,18 +761,29 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { - compatible = "fixed-clock"; + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; #clock-cells = <0>; - clock-frequency = <32768>; + interrupt-parent = <&pmc>; + interrupts = ; + clock-frequency = <12000000>; + clock-accuracy = <50000000>; }; - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; #clock-cells = <0>; interrupt-parent = <&pmc>; interrupts = ; - clocks = <&clk32k>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = ; + clocks = <&main_rc_osc &main_osc>; }; plla: pllack { @@ -1089,6 +1112,32 @@ status = "disabled"; }; + sckc@fffffe50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffe50 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + rtc@fffffeb0 { compatible = "atmel,at91rm9200-rtc"; reg = <0xfffffeb0 0x30>; -- cgit v1.2.3 From 221bfd054c944307f227c586c95e082495c06b2f Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:35 +0200 Subject: ARM: at91/dt: add xtal frequencies to sama5d3xcm boards Define crystal frequencies of sama5d3xcm boards. Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/sama5d3xcm.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index f55ed072c8e6..b0b1331c1974 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -18,6 +18,14 @@ reg = <0x20000000 0x20000000>; }; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + ahb { apb { spi0: spi@f0004000 { -- cgit v1.2.3 From 58a5c3d896811183efac043dd56c0eeb46d92b49 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:36 +0200 Subject: ARM: at91/dt: add xtal frequencies to sama5d3 xplained board Define crystal properties of sama5d3 xplained board. Signed-off-by: Boris BREZILLON Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sama5d3_xplained.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index ce1375595e5f..f1a11193fba2 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -21,6 +21,14 @@ reg = <0x20000000 0x10000000>; }; + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + ahb { apb { mmc0: mmc@f0000000 { -- cgit v1.2.3 From 884fb7d07be2927293f7fd6a241a4b9723a0a839 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:37 +0200 Subject: ARM: at91/dt: move at91sam9261 SoC to the new main clock model Signed-off-by: Boris BREZILLON Acked-by: Jean-Jacques HIBLOT Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9261.dtsi | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index e21dda0e8986..561addceb81e 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -45,6 +45,18 @@ reg = <0x20000000 0x08000000>; }; + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -524,17 +536,24 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { + slow_rc_osc: slow_rc_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9260-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_xtal>; }; main: mainck { compatible = "atmel,at91rm9200-clk-main"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&clk32k>; + clocks = <&main_xtal>; }; plla: pllack { -- cgit v1.2.3 From b6170645bde58c82ae0965ea4052f105f3395e05 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:38 +0200 Subject: ARM: at91/dt: define main xtal frequency of the at91sam9261ek board Define at91sam9261ek main crystal frequency. Signed-off-by: Boris BREZILLON Acked-by: Jean-Jacques HIBLOT Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9261ek.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index 2ce527e70c7a..c6683ea8b743 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -20,6 +20,10 @@ reg = <0x20000000 0x4000000>; }; + main_xtal { + clock-frequency = <18432000>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 2078da966ff16961a631681164267903bd32a9b3 Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:39 +0200 Subject: ARM: at91/dt: move at91sam9rl SoC to the new slow/main clock models Move at91sam9rl SoC to the new main/slow clock model. Signed-off-by: Boris BREZILLON Acked-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9rl.dtsi | 46 +++++++++++++++++++++++++++++++++------ 1 file changed, 39 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 63e1784d272c..a19a7c26a7fc 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -48,6 +48,18 @@ reg = <0x20000000 0x04000000>; }; + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -548,17 +560,11 @@ #size-cells = <0>; #interrupt-cells = <1>; - clk32k: slck { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - main: mainck { compatible = "atmel,at91rm9200-clk-main"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&clk32k>; + clocks = <&main_xtal>; }; plla: pllack { @@ -769,6 +775,32 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + sckc@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <1200000>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <75>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; }; }; -- cgit v1.2.3 From 6730fefd8ec75be7f9ac6100767792ab75b6e0de Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Tue, 22 Apr 2014 15:12:40 +0200 Subject: ARM: at91/dt: define sam9rlek crystal frequencies Define at91sam9rlek crystal frequencies. Signed-off-by: Boris BREZILLON Acked-by: Alexandre Belloni Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91sam9rlek.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index cddb37825fad..b3b89baf972e 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -20,6 +20,15 @@ reg = <0x20000000 0x4000000>; }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 616a28eda7fe5e41ff71f2aad115fb9d36f62457 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Tue, 15 Apr 2014 12:27:56 +0200 Subject: ARM: at91: sam9g45: remove unused platform_data num_channels and registers are not used anymore since they are defined inside the at91_adc driver and assigned by matching the id_table. Also, remove the mach/at91_adc.h include that is not necessary anymore. Signed-off-by: Alexandre Belloni Acked-by: Jonathan Cameron Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/at91sam9g45_devices.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 7f02a5366a31..eb06348de330 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -25,7 +25,6 @@ #include #include