From 2d11251168d1f4104b4824893288f1220ead22b3 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 17 Apr 2012 15:31:48 +1000 Subject: m68knommu: move the 5249 platform code into the common ColdFire code directory All these separate directories for each ColdFire CPU SoC varient seems like overkill. The majority of them only contain a single small config file. Move these into the common ColdFire code directory. Signed-off-by: Greg Ungerer --- arch/m68k/Makefile | 1 - arch/m68k/platform/5249/Makefile | 18 ----- arch/m68k/platform/5249/config.c | 118 -------------------------------- arch/m68k/platform/5249/intc2.c | 61 ----------------- arch/m68k/platform/coldfire/Makefile | 2 +- arch/m68k/platform/coldfire/intc-5249.c | 61 +++++++++++++++++ arch/m68k/platform/coldfire/m5249.c | 118 ++++++++++++++++++++++++++++++++ 7 files changed, 180 insertions(+), 199 deletions(-) delete mode 100644 arch/m68k/platform/5249/Makefile delete mode 100644 arch/m68k/platform/5249/config.c delete mode 100644 arch/m68k/platform/5249/intc2.c create mode 100644 arch/m68k/platform/coldfire/intc-5249.c create mode 100644 arch/m68k/platform/coldfire/m5249.c (limited to 'arch') diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 922a7ddcd8f5..314c10c7bfd1 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -115,7 +115,6 @@ core-$(CONFIG_M68000) += arch/m68k/platform/68328/ core-$(CONFIG_M68EZ328) += arch/m68k/platform/68EZ328/ core-$(CONFIG_M68VZ328) += arch/m68k/platform/68VZ328/ core-$(CONFIG_COLDFIRE) += arch/m68k/platform/coldfire/ -core-$(CONFIG_M5249) += arch/m68k/platform/5249/ core-$(CONFIG_M527x) += arch/m68k/platform/527x/ core-$(CONFIG_M5272) += arch/m68k/platform/5272/ core-$(CONFIG_M528x) += arch/m68k/platform/528x/ diff --git a/arch/m68k/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile deleted file mode 100644 index 8a0186bce829..000000000000 --- a/arch/m68k/platform/5249/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# Makefile for the m68knommu linux kernel. -# - -# -# If you want to play with the HW breakpoints then you will -# need to add define this, which will give you a stack backtrace -# on the console port whenever a DBG interrupt occurs. You have to -# set up you HW breakpoints to trigger a DBG interrupt: -# -# ccflags-y := -DTRAP_DBG_INTERRUPT -# asflags-y := -DTRAP_DBG_INTERRUPT -# - -asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 - -obj-y := config.o intc2.o - diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/5249/config.c deleted file mode 100644 index fdfa1edfd1ac..000000000000 --- a/arch/m68k/platform/5249/config.c +++ /dev/null @@ -1,118 +0,0 @@ -/***************************************************************************/ - -/* - * linux/arch/m68knommu/platform/5249/config.c - * - * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com) - */ - -/***************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/***************************************************************************/ - -struct mcf_gpio_chip mcf_gpio_chips[] = { - MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), - MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), -}; - -unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); - -/***************************************************************************/ - -#ifdef CONFIG_M5249C3 - -static struct resource m5249_smc91x_resources[] = { - { - .start = 0xe0000300, - .end = 0xe0000300 + 0x100, - .flags = IORESOURCE_MEM, - }, - { - .start = MCFINTC2_GPIOIRQ6, - .end = MCFINTC2_GPIOIRQ6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device m5249_smc91x = { - .name = "smc91x", - .id = 0, - .num_resources = ARRAY_SIZE(m5249_smc91x_resources), - .resource = m5249_smc91x_resources, -}; - -#endif /* CONFIG_M5249C3 */ - -static struct platform_device *m5249_devices[] __initdata = { -#ifdef CONFIG_M5249C3 - &m5249_smc91x, -#endif -}; - -/***************************************************************************/ - -#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) - -static void __init m5249_qspi_init(void) -{ - /* QSPI irq setup */ - writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, - MCF_MBAR + MCFSIM_QSPIICR); - mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); -} - -#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ - -/***************************************************************************/ - -#ifdef CONFIG_M5249C3 - -static void __init m5249_smc91x_init(void) -{ - u32 gpio; - - /* Set the GPIO line as interrupt source for smc91x device */ - gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - - gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5); - writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5); -} - -#endif /* CONFIG_M5249C3 */ - -/***************************************************************************/ - -void __init config_BSP(char *commandp, int size) -{ - mach_sched_init = hw_timer_init; - -#ifdef CONFIG_M5249C3 - m5249_smc91x_init(); -#endif -#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) - m5249_qspi_init(); -#endif -} - -/***************************************************************************/ - -static int __init init_BSP(void) -{ - platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); - return 0; -} - -arch_initcall(init_BSP); - -/***************************************************************************/ diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/5249/intc2.c deleted file mode 100644 index f343bf7bf5b0..000000000000 --- a/arch/m68k/platform/5249/intc2.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * intc2.c -- support for the 2nd INTC controller of the 5249 - * - * (C) Copyright 2009, Greg Ungerer - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static void intc2_irq_gpio_mask(struct irq_data *d) -{ - u32 imr; - imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); - writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); -} - -static void intc2_irq_gpio_unmask(struct irq_data *d) -{ - u32 imr; - imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); - imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); - writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); -} - -static void intc2_irq_gpio_ack(struct irq_data *d) -{ - writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); -} - -static struct irq_chip intc2_irq_gpio_chip = { - .name = "CF-INTC2", - .irq_mask = intc2_irq_gpio_mask, - .irq_unmask = intc2_irq_gpio_unmask, - .irq_ack = intc2_irq_gpio_ack, -}; - -static int __init mcf_intc2_init(void) -{ - int irq; - - /* GPIO interrupt sources */ - for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { - irq_set_chip(irq, &intc2_irq_gpio_chip); - irq_set_handler(irq, handle_edge_irq); - } - - return 0; -} - -arch_initcall(mcf_intc2_init); diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile index 50a3aefde30b..87ffd2ce374c 100644 --- a/arch/m68k/platform/coldfire/Makefile +++ b/arch/m68k/platform/coldfire/Makefile @@ -19,7 +19,7 @@ obj-$(CONFIG_M5206) += m5206.o timers.o intc.o reset.o obj-$(CONFIG_M5206e) += m5206.o timers.o intc.o reset.o obj-$(CONFIG_M520x) += m520x.o pit.o intc-simr.o reset.o obj-$(CONFIG_M523x) += m523x.o pit.o dma_timer.o intc-2.o reset.o -obj-$(CONFIG_M5249) += timers.o intc.o reset.o +obj-$(CONFIG_M5249) += m5249.o timers.o intc.o intc-5249.o reset.o obj-$(CONFIG_M527x) += pit.o intc-2.o reset.o obj-$(CONFIG_M5272) += timers.o obj-$(CONFIG_M528x) += pit.o intc-2.o reset.o diff --git a/arch/m68k/platform/coldfire/intc-5249.c b/arch/m68k/platform/coldfire/intc-5249.c new file mode 100644 index 000000000000..f343bf7bf5b0 --- /dev/null +++ b/arch/m68k/platform/coldfire/intc-5249.c @@ -0,0 +1,61 @@ +/* + * intc2.c -- support for the 2nd INTC controller of the 5249 + * + * (C) Copyright 2009, Greg Ungerer + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void intc2_irq_gpio_mask(struct irq_data *d) +{ + u32 imr; + imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); + imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); + writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_unmask(struct irq_data *d) +{ + u32 imr; + imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); + imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0)); + writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); +} + +static void intc2_irq_gpio_ack(struct irq_data *d) +{ + writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR); +} + +static struct irq_chip intc2_irq_gpio_chip = { + .name = "CF-INTC2", + .irq_mask = intc2_irq_gpio_mask, + .irq_unmask = intc2_irq_gpio_unmask, + .irq_ack = intc2_irq_gpio_ack, +}; + +static int __init mcf_intc2_init(void) +{ + int irq; + + /* GPIO interrupt sources */ + for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { + irq_set_chip(irq, &intc2_irq_gpio_chip); + irq_set_handler(irq, handle_edge_irq); + } + + return 0; +} + +arch_initcall(mcf_intc2_init); diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c new file mode 100644 index 000000000000..fdfa1edfd1ac --- /dev/null +++ b/arch/m68k/platform/coldfire/m5249.c @@ -0,0 +1,118 @@ +/***************************************************************************/ + +/* + * linux/arch/m68knommu/platform/5249/config.c + * + * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com) + */ + +/***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/***************************************************************************/ + +struct mcf_gpio_chip mcf_gpio_chips[] = { + MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD), + MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ), +}; + +unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips); + +/***************************************************************************/ + +#ifdef CONFIG_M5249C3 + +static struct resource m5249_smc91x_resources[] = { + { + .start = 0xe0000300, + .end = 0xe0000300 + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MCFINTC2_GPIOIRQ6, + .end = MCFINTC2_GPIOIRQ6, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device m5249_smc91x = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(m5249_smc91x_resources), + .resource = m5249_smc91x_resources, +}; + +#endif /* CONFIG_M5249C3 */ + +static struct platform_device *m5249_devices[] __initdata = { +#ifdef CONFIG_M5249C3 + &m5249_smc91x, +#endif +}; + +/***************************************************************************/ + +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + +static void __init m5249_qspi_init(void) +{ + /* QSPI irq setup */ + writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, + MCF_MBAR + MCFSIM_QSPIICR); + mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI); +} + +#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ + +/***************************************************************************/ + +#ifdef CONFIG_M5249C3 + +static void __init m5249_smc91x_init(void) +{ + u32 gpio; + + /* Set the GPIO line as interrupt source for smc91x device */ + gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); + writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE); + + gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5); + writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5); +} + +#endif /* CONFIG_M5249C3 */ + +/***************************************************************************/ + +void __init config_BSP(char *commandp, int size) +{ + mach_sched_init = hw_timer_init; + +#ifdef CONFIG_M5249C3 + m5249_smc91x_init(); +#endif +#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) + m5249_qspi_init(); +#endif +} + +/***************************************************************************/ + +static int __init init_BSP(void) +{ + platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); + return 0; +} + +arch_initcall(init_BSP); + +/***************************************************************************/ -- cgit v1.2.3