From 6d4ee83b423fe663a8574d2f16b48b98cbfc9b26 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Tue, 1 Nov 2022 13:09:33 -0500 Subject: arm64: dts: ti: k3-am625: Introduce operating-points table Introduce an operating-points table for the A53 cores, containing only frequency values as this platform operates on a fixed voltage for the CPUs. Also provide opp-supported-hw values to ensure appropriate OPPs are enabled based on which type of silicon is in use. The latency between pre and post frequency transition was measured in CPUFreq driver for all combinations of OPP changes. The average value was selected as overall clock-latency-ns. Signed-off-by: Dave Gerlach Signed-off-by: Vibhore Vardhan Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index 887f31c23fef..cea2cc7de5dd 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -48,6 +48,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 135 0>; }; cpu1: cpu@1 { @@ -62,6 +64,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 136 0>; }; cpu2: cpu@2 { @@ -76,6 +80,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 137 0>; }; cpu3: cpu@3 { @@ -90,6 +96,51 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&L2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&k3_clks 138 0>; + }; + }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&wkup_conf>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0007>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0006>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + opp-suspend; }; }; -- cgit v1.2.3 From 1313edfdcd79ac8f7aa92162db646eb0eb7a32c2 Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Tue, 1 Nov 2022 13:09:35 -0500 Subject: arm64: dts: ti: k3-am625-sk: Add 1.4GHz OPP The 1.4 GHz OPP requires supported silicon variant (T speed grade) and also VDD_CORE to be at 0.85V. All production revisions of the AM625-SK have both so we can enable the 1.4 GHz OPP for it. Any other boards based on this design should verify that they have the right silicon variant and the right power tree before adding 1.4 GHz support in their board dts file. Signed-off-by: Vibhore Vardhan Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 93a5f0817efc..4620ef5e19bb 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -31,6 +31,15 @@ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + opp-table { + /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + memory@80000000 { device_type = "memory"; /* 2G RAM */ -- cgit v1.2.3