From abfbd89595e91d5108f807e10bbd2152bc55f36b Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 24 Aug 2015 19:44:46 +0300 Subject: xtensa: xtfpga: fix serial port register width and endianness Serial port is attached to XTFPGA boards as native endian device, mark it as such in DTS and pass correct endianness in platform data. Set register width in DTS to 4, this way it matches the platform data and works correctly on big-endian CPUs. Signed-off-by: Max Filippov --- arch/xtensa/boot/dts/xtfpga.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/xtensa/boot') diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi index cd0b9e34adc8..be3fd769677a 100644 --- a/arch/xtensa/boot/dts/xtfpga.dtsi +++ b/arch/xtensa/boot/dts/xtfpga.dtsi @@ -60,6 +60,8 @@ no-loopback-test; reg = <0x0d050020 0x20>; reg-shift = <2>; + reg-io-width = <4>; + native-endian; interrupts = <0 1>; /* external irq 0 */ clocks = <&osc>; }; -- cgit v1.2.3