From 5026dafa177133f9b6bf0000dfc98596fa4ad2fd Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Mon, 5 Aug 2013 14:27:05 -0400 Subject: tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 system On Tilera Gx72 systems, the logic for figuring out whether a given port is root complex is slightly different. Signed-off-by: Chris Metcalf --- arch/tile/include/hv/drv_trio_intf.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/tile/include') diff --git a/arch/tile/include/hv/drv_trio_intf.h b/arch/tile/include/hv/drv_trio_intf.h index ec643a02b4c5..237e04dee66c 100644 --- a/arch/tile/include/hv/drv_trio_intf.h +++ b/arch/tile/include/hv/drv_trio_intf.h @@ -168,6 +168,9 @@ pcie_stream_intr_config_sel_t; struct pcie_trio_ports_property { struct pcie_port_property ports[TILEGX_TRIO_PCIES]; + + /** Set if this TRIO belongs to a Gx72 device. */ + uint8_t is_gx72; }; /* Flags indicating traffic class. */ -- cgit v1.2.3