From 9318c51acd9689505850152cc98277a6d6f2d752 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Tue, 20 Jun 2006 17:15:20 +0100 Subject: [MIPS] MIPS32/MIPS64 secondary cache management Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/mm/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/mm/Makefile') diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4a6220116c96..19e41fd186c4 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o +obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o # # Choose one DMA coherency model -- cgit v1.2.3