From 98873f53becea9a8a46972ff252e96fe575b120d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 9 Dec 2008 17:58:46 +0000 Subject: MIPS: Better than nothing implementation of PCI mmap to fix X. Certain X11 servers such as the SIS server will only work if PCI mmap is implemented. This patch implements PCI mmap but to be on the same side so close to a release it only supports uncached mappings so performance will not be optimal for some uses such as framebuffers. Thanks to Zhang Le for the original report and testing. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pci.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 5510c53b7feb..053e4634acee 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -79,6 +79,11 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) /* We don't do dynamic PCI IRQ allocation */ } +#define HAVE_PCI_MMAP + +extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, int write_combine); + /* * Dynamic DMA mapping stuff. * MIPS has everything mapped statically. -- cgit v1.2.3 From b6354db5bbbc538bf009cae6c019810b4a3ef21d Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Dec 2008 08:37:25 -0800 Subject: MIPS: Use EI/DI for MIPS R2. For MIPS R2, use the EI and DI instructions to enable and disable interrupts. Signed-off-by: Tomaso Paoletti Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/include/asm/asmmacro.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 7a881755800f..6c8342ae74db 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -35,6 +35,16 @@ mtc0 \reg, CP0_TCSTATUS _ehb .endm +#elif defined(CONFIG_CPU_MIPSR2) + .macro local_irq_enable reg=t0 + ei + irq_enable_hazard + .endm + + .macro local_irq_disable reg=t0 + di + irq_disable_hazard + .endm #else .macro local_irq_enable reg=t0 mfc0 \reg, CP0_STATUS -- cgit v1.2.3 From 08d9d1c4d44ce43856da048cb0737ef769b61e9a Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 17 Dec 2008 18:19:18 -0800 Subject: MIPS: Fix preprocessor warnings flaged by GCC 4.4 Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/include/asm/elf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index a8eac1697b3d..d58f128aa747 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -232,7 +232,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; */ #ifdef __MIPSEB__ #define ELF_DATA ELFDATA2MSB -#elif __MIPSEL__ +#elif defined(__MIPSEL__) #define ELF_DATA ELFDATA2LSB #endif #define ELF_ARCH EM_MIPS -- cgit v1.2.3 From ed2b03ed3cec2a4719d04ef208319f9de6a4258a Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 17 Dec 2008 13:28:39 -0800 Subject: MIPS: MIPS64R2: Fix buggy __arch_swab64 The way the code is written it was assuming dshd has the function of a hypothetical dshw instruction ... Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/include/asm/byteorder.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h index 2988d29a0867..33790b9e0cc0 100644 --- a/arch/mips/include/asm/byteorder.h +++ b/arch/mips/include/asm/byteorder.h @@ -50,9 +50,8 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x) static inline __attribute_const__ __u64 __arch_swab64(__u64 x) { __asm__( - " dsbh %0, %1 \n" - " dshd %0, %0 \n" - " drotr %0, %0, 32 \n" + " dsbh %0, %1\n" + " dshd %0, %0" : "=r" (x) : "r" (x)); -- cgit v1.2.3