From 43df4eb2fc9511e09c66252c3fec4f8933a77c73 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 24 Aug 2020 18:32:51 +0200 Subject: MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-cavium-octeon/war.h | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/include/asm/mach-cavium-octeon/war.h') diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h index 9aa4ea5522a9..0a2bf6b7af94 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/war.h +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h @@ -10,7 +10,6 @@ #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H #define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 #define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \ OCTEON_IS_MODEL(OCTEON_CN6XXX) -- cgit v1.2.3