From d631fc60706ccd86c5c2b0084bcea0739952ce90 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Mon, 16 Mar 2015 14:43:07 -0700 Subject: MIPS: Create a common 11 platforms require at least one of these workarounds to be enabled; 22 platforms do not. In the latter case we can fall back to a generic version. Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR. Suggested-by: Arnd Bergmann Signed-off-by: Kevin Cernekee Signed-off-by: Andrew Bresticker Reviewed-by: James Hogan Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Ezequiel Garcia Cc: James Hartley Cc: James Hogan Patchwork: https://patchwork.linux-mips.org/patch/9567/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-bcm63xx/war.h | 24 ------------------------ 1 file changed, 24 deletions(-) delete mode 100644 arch/mips/include/asm/mach-bcm63xx/war.h (limited to 'arch/mips/include/asm/mach-bcm63xx') diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h deleted file mode 100644 index 05ee8671bef1..000000000000 --- a/arch/mips/include/asm/mach-bcm63xx/war.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H -#define __ASM_MIPS_MACH_BCM63XX_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */ -- cgit v1.2.3 From 3cf29543413207d3ab1c3f62a88c09bb46f2264e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 7 Apr 2015 13:34:02 -0700 Subject: MIPS: BCM63xx: Provide a plat_post_dma_flush hook Broadcom BCM63xx DSL SoCs utilize BMIPS CPUs, and as such are required to perform a read-ahead cache flush after a DMA transfer. Utilize asm/bmips.h to provide a plat_post_dma_flush_hook, and mach-generic/dma-coherence.h for everything else. Signed-off-by: Florian Fainelli Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/9726/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-bcm63xx/dma-coherence.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/mips/include/asm/mach-bcm63xx/dma-coherence.h (limited to 'arch/mips/include/asm/mach-bcm63xx') diff --git a/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h b/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h new file mode 100644 index 000000000000..11d3b572b1b3 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/dma-coherence.h @@ -0,0 +1,10 @@ +#ifndef __ASM_MACH_BCM63XX_DMA_COHERENCE_H +#define __ASM_MACH_BCM63XX_DMA_COHERENCE_H + +#include + +#define plat_post_dma_flush bmips_post_dma_flush + +#include + +#endif /* __ASM_MACH_BCM63XX_DMA_COHERENCE_H */ -- cgit v1.2.3