From 2d3cbc780437ae4e81f09d0efdd6769852bce5f5 Mon Sep 17 00:00:00 2001 From: Richard Kuo Date: Mon, 31 Oct 2011 18:50:51 -0500 Subject: Hexagon: Implement basic cache-flush support Signed-off-by: Richard Kuo Acked-by: Arnd Bergmann Signed-off-by: Linus Torvalds --- arch/hexagon/include/asm/cache.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/hexagon/include/asm/cache.h (limited to 'arch/hexagon/include/asm/cache.h') diff --git a/arch/hexagon/include/asm/cache.h b/arch/hexagon/include/asm/cache.h new file mode 100644 index 000000000000..0f01de2eb4ab --- /dev/null +++ b/arch/hexagon/include/asm/cache.h @@ -0,0 +1,34 @@ +/* + * Cache definitions for the Hexagon architecture + * + * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef __ASM_CACHE_H +#define __ASM_CACHE_H + +/* Bytes per L1 cache line */ +#define L1_CACHE_SHIFT (5) +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define __cacheline_aligned __aligned(L1_CACHE_BYTES) +#define ____cacheline_aligned __aligned(L1_CACHE_BYTES) + +/* See http://kerneltrap.org/node/15100 */ +#define __read_mostly + +#endif -- cgit v1.2.3