From 6ad69e07def67c95e677a747d5320f2f734fd583 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 3 May 2022 00:41:23 +0200 Subject: ARM: dts: lan966x: add MIIM nodes Add the MDIO controller nodes. The integrated PHYs are connected to the second controller. This controller also takes care of the resets of the integrated PHYs, thus it has two memory regions. The first controller is routed to the external MDIO/MDC pins. By default, they are disabled. Signed-off-by: Michael Walle Reviewed-by: Claudiu Beznea Tested-by: Horatiu Vultur Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220502224127.2604333-10-michael@walle.cc Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/lan966x.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 140bdeb9d4fd..786655b65dc5 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -418,6 +418,37 @@ #interrupt-cells = <2>; }; + mdio0: mdio@e2004118 { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe2004118 0x24>; + clocks = <&sys_clk>; + status = "disabled"; + }; + + mdio1: mdio@e200413c { + compatible = "microchip,lan966x-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe200413c 0x24>, + <0xe2010020 0x4>; + clocks = <&sys_clk>; + status = "disabled"; + + phy0: ethernet-phy@1 { + reg = <1>; + interrupts = ; + status = "disabled"; + }; + + phy1: ethernet-phy@2 { + reg = <2>; + interrupts = ; + status = "disabled"; + }; + }; + sgpio: gpio@e2004190 { compatible = "microchip,sparx5-sgpio"; reg = <0xe2004190 0x118>; -- cgit v1.2.3