From e3239ff92a17976ac5d26fa0fe40ef3a9daf2523 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 4 Aug 2010 14:06:41 +1000 Subject: memblock: Rename memblock_region to memblock_type and memblock_property to memblock_region Signed-off-by: Benjamin Herrenschmidt --- arch/arm/mm/init.c | 2 +- arch/arm/plat-omap/fb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 7185b00650fe..d1496e65dc2d 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -237,7 +237,7 @@ static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min, #ifndef CONFIG_SPARSEMEM int pfn_valid(unsigned long pfn) { - struct memblock_region *mem = &memblock.memory; + struct memblock_type *mem = &memblock.memory; unsigned int left = 0, right = mem->cnt; do { diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 0054b9501a53..05bf22827404 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -173,7 +173,7 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg, static int valid_sdram(unsigned long addr, unsigned long size) { - struct memblock_property res; + struct memblock_region res; res.base = addr; res.size = size; -- cgit v1.2.3 From 5e6f6aa1c243fafeb2648cf4ebd5abd99ab2531b Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 4 Aug 2010 13:23:02 +1000 Subject: memblock/arm: pfn_valid uses memblock_is_memory() The implementation is pretty much similar. There is a -small- added overhead by having another function call and the address shift. If that becomes a concern, I suppose we could actually have memblock itself expose a memblock_pfn_valid() which then ARM can use directly with an appropriate #define... Signed-off-by: Benjamin Herrenschmidt --- arch/arm/mm/init.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index d1496e65dc2d..e739223e2a54 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -237,20 +237,7 @@ static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min, #ifndef CONFIG_SPARSEMEM int pfn_valid(unsigned long pfn) { - struct memblock_type *mem = &memblock.memory; - unsigned int left = 0, right = mem->cnt; - - do { - unsigned int mid = (right + left) / 2; - - if (pfn < memblock_start_pfn(mem, mid)) - right = mid; - else if (pfn >= memblock_end_pfn(mem, mid)) - left = mid + 1; - else - return 1; - } while (left < right); - return 0; + return memblock_is_memory(pfn << PAGE_SHIFT); } EXPORT_SYMBOL(pfn_valid); -- cgit v1.2.3 From dbe3039e64b1dd4cf26f782d45b524f85b444ad4 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 4 Aug 2010 14:09:23 +1000 Subject: memblock/arm: Use memblock_region_is_memory() for omap fb Instead of the deprecated memblock_find() Signed-off-by: Benjamin Herrenschmidt --- arch/arm/plat-omap/fb.c | 6 +----- drivers/video/omap2/vram.c | 8 ++------ 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 05bf22827404..441af2bdfd15 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -173,11 +173,7 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg, static int valid_sdram(unsigned long addr, unsigned long size) { - struct memblock_region res; - - res.base = addr; - res.size = size; - return !memblock_find(&res) && res.base == addr && res.size == size; + return memblock_region_is_memory(addr, size); } static int reserve_sdram(unsigned long addr, unsigned long size) diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c index 0f2532bf0f04..34514a899d13 100644 --- a/drivers/video/omap2/vram.c +++ b/drivers/video/omap2/vram.c @@ -554,12 +554,8 @@ void __init omap_vram_reserve_sdram_memblock(void) size = PAGE_ALIGN(size); if (paddr) { - struct memblock_region res; - - res.base = paddr; - res.size = size; - if ((paddr & ~PAGE_MASK) || memblock_find(&res) || - res.base != paddr || res.size != size) { + if ((paddr & ~PAGE_MASK) || + !memblock_region_is_memory(paddr, size)) { pr_err("Illegal SDRAM region for VRAM\n"); return; } -- cgit v1.2.3 From 719c1514f2fef5f01fcfa2bba81b7bb079c7c6a1 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 5 Aug 2010 12:55:55 +1000 Subject: memblock/arm: Use new accessors CC: Russell King Signed-off-by: Benjamin Herrenschmidt --- arch/arm/mm/init.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index e739223e2a54..8504906b147f 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -150,6 +150,7 @@ static void __init find_limits(struct meminfo *mi, static void __init arm_bootmem_init(struct meminfo *mi, unsigned long start_pfn, unsigned long end_pfn) { + struct memblock_region *reg; unsigned int boot_pages; phys_addr_t bitmap; pg_data_t *pgdat; @@ -180,13 +181,13 @@ static void __init arm_bootmem_init(struct meminfo *mi, /* * Reserve the memblock reserved regions in bootmem. */ - for (i = 0; i < memblock.reserved.cnt; i++) { - phys_addr_t start = memblock_start_pfn(&memblock.reserved, i); - if (start >= start_pfn && - memblock_end_pfn(&memblock.reserved, i) <= end_pfn) + for_each_memblock(reserved, reg) { + phys_addr_t start = memblock_region_base_pfn(reg); + phys_addr_t end = memblock_region_end_pfn(reg); + if (start >= start_pfn && end <= end_pfn) reserve_bootmem_node(pgdat, __pfn_to_phys(start), - memblock_size_bytes(&memblock.reserved, i), - BOOTMEM_DEFAULT); + (end - start) << PAGE_SHIFT, + BOOTMEM_DEFAULT); } } @@ -247,10 +248,12 @@ static void arm_memory_present(void) #else static void arm_memory_present(void) { + struct memblock_region *reg; int i; - for (i = 0; i < memblock.memory.cnt; i++) - memory_present(0, memblock_start_pfn(&memblock.memory, i), - memblock_end_pfn(&memblock.memory, i)); + + for_each_memblock(memory, reg) { + memory_present(0, memblock_region_base_pfn(reg), + memblock_region_end_pfn(reg)); } #endif -- cgit v1.2.3 From 426d31071ac476ea62c62656b242930c17b58c00 Mon Sep 17 00:00:00 2001 From: Paul Bolle Date: Sat, 7 Aug 2010 12:30:03 +0200 Subject: fix printk typo 'faild' Signed-off-by: Paul Bolle Signed-off-by: Jiri Kosina --- arch/arm/mach-omap1/board-nokia770.c | 2 +- drivers/ata/pata_bf54x.c | 2 +- drivers/gpu/drm/radeon/radeon_cs.c | 2 +- drivers/net/ps3_gelic_net.c | 4 ++-- drivers/net/tulip/pnic2.c | 2 +- drivers/rtc/rtc-nuc900.c | 2 +- drivers/video/bf54x-lq043fb.c | 6 +++--- drivers/video/bfin-t350mcqb-fb.c | 2 +- fs/exofs/inode.c | 14 +++++++------- fs/exofs/ios.c | 10 +++++----- fs/jfs/jfs_mount.c | 4 ++-- kernel/trace/trace_kprobe.c | 2 +- net/wanrouter/wanmain.c | 4 ++-- 13 files changed, 28 insertions(+), 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 8c28b10f3dae..bc93afbb0a68 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -362,7 +362,7 @@ static __init int omap_dsp_init(void) ret = dsp_kfunc_device_register(&nokia770_audio_device); if (ret) { printk(KERN_ERR - "KFUNC device registration faild: %s\n", + "KFUNC device registration failed: %s\n", nokia770_audio_device.name); goto out; } diff --git a/drivers/ata/pata_bf54x.c b/drivers/ata/pata_bf54x.c index 9cae65de750e..be7b1b21e777 100644 --- a/drivers/ata/pata_bf54x.c +++ b/drivers/ata/pata_bf54x.c @@ -1588,7 +1588,7 @@ static int __devinit bfin_atapi_probe(struct platform_device *pdev) host->ports[0]->ioaddr.ctl_addr = (void *)res->start; if (peripheral_request_list(atapi_io_port, "atapi-io-port")) { - dev_err(&pdev->dev, "Requesting Peripherals faild\n"); + dev_err(&pdev->dev, "Requesting Peripherals failed\n"); return -EFAULT; } diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index ae0fb7356e62..8de578ee4987 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -268,7 +268,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) } r = radeon_ib_schedule(rdev, parser.ib); if (r) { - DRM_ERROR("Faild to schedule IB !\n"); + DRM_ERROR("Failed to schedule IB !\n"); } radeon_cs_parser_fini(&parser, r); mutex_unlock(&rdev->cs_mutex); diff --git a/drivers/net/ps3_gelic_net.c b/drivers/net/ps3_gelic_net.c index 87d6b8f36304..49f6700e2ec2 100644 --- a/drivers/net/ps3_gelic_net.c +++ b/drivers/net/ps3_gelic_net.c @@ -642,7 +642,7 @@ static inline void gelic_card_disable_rxdmac(struct gelic_card *card) status = lv1_net_stop_rx_dma(bus_id(card), dev_id(card), 0); if (status) dev_err(ctodev(card), - "lv1_net_stop_rx_dma faild, %d\n", status); + "lv1_net_stop_rx_dma failed, %d\n", status); } /** @@ -660,7 +660,7 @@ static inline void gelic_card_disable_txdmac(struct gelic_card *card) status = lv1_net_stop_tx_dma(bus_id(card), dev_id(card), 0); if (status) dev_err(ctodev(card), - "lv1_net_stop_tx_dma faild, status=%d\n", status); + "lv1_net_stop_tx_dma failed, status=%d\n", status); } /** diff --git a/drivers/net/tulip/pnic2.c b/drivers/net/tulip/pnic2.c index b8197666021e..4690c8e69207 100644 --- a/drivers/net/tulip/pnic2.c +++ b/drivers/net/tulip/pnic2.c @@ -59,7 +59,7 @@ * Bit 14:12 - autonegotiation state (write 001 to start autonegotiate) * Bit 3 - Autopolarity state * Bit 2 - LS10B - link state of 10baseT 0 - good, 1 - failed - * Bit 1 - LS100B - link state of 100baseT 0 - good, 1- faild + * Bit 1 - LS100B - link state of 100baseT 0 - good, 1 - failed * * * Data Port Selection Info diff --git a/drivers/rtc/rtc-nuc900.c b/drivers/rtc/rtc-nuc900.c index a351bd5d8176..08f95bd3adb3 100644 --- a/drivers/rtc/rtc-nuc900.c +++ b/drivers/rtc/rtc-nuc900.c @@ -279,7 +279,7 @@ static int __devinit nuc900_rtc_probe(struct platform_device *pdev) nuc900_rtc->rtcdev = rtc_device_register(pdev->name, &pdev->dev, &nuc900_rtc_ops, THIS_MODULE); if (IS_ERR(nuc900_rtc->rtcdev)) { - dev_err(&pdev->dev, "rtc device register faild\n"); + dev_err(&pdev->dev, "rtc device register failed\n"); err = PTR_ERR(nuc900_rtc->rtcdev); goto fail4; } diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c index b020ba7f1cf2..e7d0f525041e 100644 --- a/drivers/video/bf54x-lq043fb.c +++ b/drivers/video/bf54x-lq043fb.c @@ -241,12 +241,12 @@ static int request_ports(struct bfin_bf54xfb_info *fbi) u16 disp = fbi->mach_info->disp; if (gpio_request(disp, DRIVER_NAME)) { - printk(KERN_ERR "Requesting GPIO %d faild\n", disp); + printk(KERN_ERR "Requesting GPIO %d failed\n", disp); return -EFAULT; } if (peripheral_request_list(eppi_req_18, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals faild\n"); + printk(KERN_ERR "Requesting Peripherals failed\n"); gpio_free(disp); return -EFAULT; } @@ -256,7 +256,7 @@ static int request_ports(struct bfin_bf54xfb_info *fbi) u16 eppi_req_24[] = EPPI0_24; if (peripheral_request_list(eppi_req_24, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals faild\n"); + printk(KERN_ERR "Requesting Peripherals failed\n"); peripheral_free_list(eppi_req_18); gpio_free(disp); return -EFAULT; diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c index 7a50272eaab9..3cf77676947c 100644 --- a/drivers/video/bfin-t350mcqb-fb.c +++ b/drivers/video/bfin-t350mcqb-fb.c @@ -192,7 +192,7 @@ static int bfin_t350mcqb_request_ports(int action) { if (action) { if (peripheral_request_list(ppi0_req_8, DRIVER_NAME)) { - printk(KERN_ERR "Requesting Peripherals faild\n"); + printk(KERN_ERR "Requesting Peripherals failed\n"); return -EFAULT; } } else diff --git a/fs/exofs/inode.c b/fs/exofs/inode.c index 4bb6ef822e46..5862ae87ed29 100644 --- a/fs/exofs/inode.c +++ b/fs/exofs/inode.c @@ -508,7 +508,7 @@ static int write_exec(struct page_collect *pcol) pcol_copy = kmalloc(sizeof(*pcol_copy), GFP_KERNEL); if (!pcol_copy) { - EXOFS_ERR("write_exec: Faild to kmalloc(pcol)\n"); + EXOFS_ERR("write_exec: Failed to kmalloc(pcol)\n"); ret = -ENOMEM; goto err; } @@ -524,7 +524,7 @@ static int write_exec(struct page_collect *pcol) ret = exofs_oi_write(oi, ios); if (unlikely(ret)) { - EXOFS_ERR("write_exec: exofs_oi_write() Faild\n"); + EXOFS_ERR("write_exec: exofs_oi_write() Failed\n"); goto err; } @@ -625,7 +625,7 @@ try_again: /* split the request, next loop will start again */ ret = write_exec(pcol); if (unlikely(ret)) { - EXOFS_DBGMSG("write_exec faild => %d", ret); + EXOFS_DBGMSG("write_exec failed => %d", ret); goto fail; } @@ -709,7 +709,7 @@ int exofs_write_begin(struct file *file, struct address_space *mapping, ret = simple_write_begin(file, mapping, pos, len, flags, pagep, fsdata); if (ret) { - EXOFS_DBGMSG("simple_write_begin faild\n"); + EXOFS_DBGMSG("simple_write_begin failed\n"); return ret; } @@ -722,7 +722,7 @@ int exofs_write_begin(struct file *file, struct address_space *mapping, if (ret) { /*SetPageError was done by _readpage. Is it ok?*/ unlock_page(page); - EXOFS_DBGMSG("__readpage_filler faild\n"); + EXOFS_DBGMSG("__readpage_filler failed\n"); } } @@ -1112,7 +1112,7 @@ static void create_done(struct exofs_io_state *ios, void *p) atomic_dec(&sbi->s_curr_pending); if (unlikely(ret)) { - EXOFS_ERR("object=0x%llx creation faild in pid=0x%llx", + EXOFS_ERR("object=0x%llx creation failed in pid=0x%llx", _LLU(exofs_oi_objno(oi)), _LLU(sbi->layout.s_pid)); /*TODO: When FS is corrupted creation can fail, object already * exist. Get rid of this asynchronous creation, if exist @@ -1232,7 +1232,7 @@ static int exofs_update_inode(struct inode *inode, int do_sync) args = kzalloc(sizeof(*args), GFP_KERNEL); if (!args) { - EXOFS_DBGMSG("Faild kzalloc of args\n"); + EXOFS_DBGMSG("Failed kzalloc of args\n"); return -ENOMEM; } diff --git a/fs/exofs/ios.c b/fs/exofs/ios.c index 4337cad7777b..95921f501f2f 100644 --- a/fs/exofs/ios.c +++ b/fs/exofs/ios.c @@ -55,7 +55,7 @@ int exofs_read_kern(struct osd_dev *od, u8 *cred, struct osd_obj_id *obj, ret = osd_finalize_request(or, 0, cred, NULL); if (unlikely(ret)) { - EXOFS_DBGMSG("Faild to osd_finalize_request() => %d\n", ret); + EXOFS_DBGMSG("Failed to osd_finalize_request() => %d\n", ret); goto out; } @@ -79,7 +79,7 @@ int exofs_get_io_state(struct exofs_layout *layout, */ ios = kzalloc(exofs_io_state_size(layout->s_numdevs), GFP_KERNEL); if (unlikely(!ios)) { - EXOFS_DBGMSG("Faild kzalloc bytes=%d\n", + EXOFS_DBGMSG("Failed kzalloc bytes=%d\n", exofs_io_state_size(layout->s_numdevs)); *pios = NULL; return -ENOMEM; @@ -172,7 +172,7 @@ static int exofs_io_execute(struct exofs_io_state *ios) ret = osd_finalize_request(or, 0, ios->cred, NULL); if (unlikely(ret)) { - EXOFS_DBGMSG("Faild to osd_finalize_request() => %d\n", + EXOFS_DBGMSG("Failed to osd_finalize_request() => %d\n", ret); return ret; } @@ -365,7 +365,7 @@ static int _add_stripe_unit(struct exofs_io_state *ios, unsigned *cur_pg, per_dev->bio = bio_kmalloc(GFP_KERNEL, bio_size); if (unlikely(!per_dev->bio)) { - EXOFS_DBGMSG("Faild to allocate BIO size=%u\n", + EXOFS_DBGMSG("Failed to allocate BIO size=%u\n", bio_size); return -ENOMEM; } @@ -584,7 +584,7 @@ static int _sbi_write_mirror(struct exofs_io_state *ios, int cur_comp) master_dev->bio->bi_max_vecs); if (unlikely(!bio)) { EXOFS_DBGMSG( - "Faild to allocate BIO size=%u\n", + "Failed to allocate BIO size=%u\n", master_dev->bio->bi_max_vecs); ret = -ENOMEM; goto out; diff --git a/fs/jfs/jfs_mount.c b/fs/jfs/jfs_mount.c index 7b698f2ec45a..9895595fd2f2 100644 --- a/fs/jfs/jfs_mount.c +++ b/fs/jfs/jfs_mount.c @@ -97,7 +97,7 @@ int jfs_mount(struct super_block *sb) ipaimap = diReadSpecial(sb, AGGREGATE_I, 0); if (ipaimap == NULL) { - jfs_err("jfs_mount: Faild to read AGGREGATE_I"); + jfs_err("jfs_mount: Failed to read AGGREGATE_I"); rc = -EIO; goto errout20; } @@ -148,7 +148,7 @@ int jfs_mount(struct super_block *sb) if ((sbi->mntflag & JFS_BAD_SAIT) == 0) { ipaimap2 = diReadSpecial(sb, AGGREGATE_I, 1); if (!ipaimap2) { - jfs_err("jfs_mount: Faild to read AGGREGATE_I"); + jfs_err("jfs_mount: Failed to read AGGREGATE_I"); rc = -EIO; goto errout35; } diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c index f52b5f50299d..58716e73e2a2 100644 --- a/kernel/trace/trace_kprobe.c +++ b/kernel/trace/trace_kprobe.c @@ -490,7 +490,7 @@ static int register_trace_probe(struct trace_probe *tp) } ret = register_probe_event(tp); if (ret) { - pr_warning("Faild to register probe event(%d)\n", ret); + pr_warning("Failed to register probe event(%d)\n", ret); goto end; } diff --git a/net/wanrouter/wanmain.c b/net/wanrouter/wanmain.c index 2bf23406637a..74944a2dd436 100644 --- a/net/wanrouter/wanmain.c +++ b/net/wanrouter/wanmain.c @@ -471,7 +471,7 @@ static int wanrouter_device_setup(struct wan_device *wandev, data = vmalloc(conf->data_size); if (!data) { printk(KERN_INFO - "%s: ERROR, Faild allocate kernel memory !\n", + "%s: ERROR, Failed allocate kernel memory !\n", wandev->name); kfree(conf); return -ENOBUFS; @@ -481,7 +481,7 @@ static int wanrouter_device_setup(struct wan_device *wandev, err = wandev->setup(wandev, conf); } else { printk(KERN_INFO - "%s: ERROR, Faild to copy from user data !\n", + "%s: ERROR, Failed to copy from user data !\n", wandev->name); err = -EFAULT; } -- cgit v1.2.3 From c1a65932fd7216fdc9a0db8bbffe1d47842f862c Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Tue, 29 Jun 2010 18:08:13 +0200 Subject: perf: Drop unappropriate tests on arch callchains Drop the TASK_RUNNING test on user tasks for callchains as this check doesn't seem to make any sense. Also remove the tests for !current that is not supposed to happen and current->pid as this should be handled at the generic level, with exclude_idle attribute. Signed-off-by: Frederic Weisbecker Tested-by: Will Deacon Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Arnaldo Carvalho de Melo Cc: Paul Mackerras Cc: Stephane Eranian Cc: David Miller Cc: Paul Mundt Cc: Borislav Petkov --- arch/arm/kernel/perf_event.c | 6 ------ arch/sh/kernel/perf_callchain.c | 3 --- arch/x86/kernel/cpu/perf_event.c | 3 --- 3 files changed, 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 417c392ddf1c..fdcb0be47df1 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -3107,12 +3107,6 @@ perf_do_callchain(struct pt_regs *regs, is_user = user_mode(regs); - if (!current || !current->pid) - return; - - if (is_user && current->state != TASK_RUNNING) - return; - if (!is_user) perf_callchain_kernel(regs, entry); diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c index a9dd3abde28e..1d6dbce7a3bc 100644 --- a/arch/sh/kernel/perf_callchain.c +++ b/arch/sh/kernel/perf_callchain.c @@ -68,9 +68,6 @@ perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) is_user = user_mode(regs); - if (is_user && current->state != TASK_RUNNING) - return; - /* * Only the kernel side is implemented for now. */ diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index f2da20fda02d..4a4d191f9492 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -1703,9 +1703,6 @@ perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) is_user = user_mode(regs); - if (is_user && current->state != TASK_RUNNING) - return; - if (!is_user) perf_callchain_kernel(regs, entry); -- cgit v1.2.3 From 70791ce9ba68a5921c9905ef05d23f62a90bc10c Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Tue, 29 Jun 2010 19:34:05 +0200 Subject: perf: Generalize callchain_store() callchain_store() is the same on every archs, inline it in perf_event.h and rename it to perf_callchain_store() to avoid any collision. This removes repetitive code. Signed-off-by: Frederic Weisbecker Acked-by: Paul Mackerras Tested-by: Will Deacon Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Arnaldo Carvalho de Melo Cc: Stephane Eranian Cc: David Miller Cc: Paul Mundt Cc: Borislav Petkov --- arch/arm/kernel/perf_event.c | 15 ++++---------- arch/powerpc/kernel/perf_callchain.c | 40 +++++++++++++----------------------- arch/sh/kernel/perf_callchain.c | 11 +++------- arch/sparc/kernel/perf_event.c | 26 +++++++++-------------- arch/x86/kernel/cpu/perf_event.c | 20 +++++++----------- include/linux/perf_event.h | 7 +++++++ 6 files changed, 45 insertions(+), 74 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index fdcb0be47df1..a07c3b1955f0 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -3001,13 +3001,6 @@ arch_initcall(init_hw_perf_events); /* * Callchain handling code. */ -static inline void -callchain_store(struct perf_callchain_entry *entry, - u64 ip) -{ - if (entry->nr < PERF_MAX_STACK_DEPTH) - entry->ip[entry->nr++] = ip; -} /* * The registers we're interested in are at the end of the variable @@ -3039,7 +3032,7 @@ user_backtrace(struct frame_tail *tail, if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) return NULL; - callchain_store(entry, buftail.lr); + perf_callchain_store(entry, buftail.lr); /* * Frame pointers should strictly progress back up the stack @@ -3057,7 +3050,7 @@ perf_callchain_user(struct pt_regs *regs, { struct frame_tail *tail; - callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, PERF_CONTEXT_USER); if (!user_mode(regs)) regs = task_pt_regs(current); @@ -3078,7 +3071,7 @@ callchain_trace(struct stackframe *fr, void *data) { struct perf_callchain_entry *entry = data; - callchain_store(entry, fr->pc); + perf_callchain_store(entry, fr->pc); return 0; } @@ -3088,7 +3081,7 @@ perf_callchain_kernel(struct pt_regs *regs, { struct stackframe fr; - callchain_store(entry, PERF_CONTEXT_KERNEL); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); fr.fp = regs->ARM_fp; fr.sp = regs->ARM_sp; fr.lr = regs->ARM_lr; diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c index 95ad9dad298e..a286c2e5a3ea 100644 --- a/arch/powerpc/kernel/perf_callchain.c +++ b/arch/powerpc/kernel/perf_callchain.c @@ -23,18 +23,6 @@ #include "ppc32.h" #endif -/* - * Store another value in a callchain_entry. - */ -static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip) -{ - unsigned int nr = entry->nr; - - if (nr < PERF_MAX_STACK_DEPTH) { - entry->ip[nr] = ip; - entry->nr = nr + 1; - } -} /* * Is sp valid as the address of the next kernel stack frame after prev_sp? @@ -69,8 +57,8 @@ static void perf_callchain_kernel(struct pt_regs *regs, lr = regs->link; sp = regs->gpr[1]; - callchain_store(entry, PERF_CONTEXT_KERNEL); - callchain_store(entry, regs->nip); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); + perf_callchain_store(entry, regs->nip); if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD)) return; @@ -89,7 +77,7 @@ static void perf_callchain_kernel(struct pt_regs *regs, next_ip = regs->nip; lr = regs->link; level = 0; - callchain_store(entry, PERF_CONTEXT_KERNEL); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); } else { if (level == 0) @@ -111,7 +99,7 @@ static void perf_callchain_kernel(struct pt_regs *regs, ++level; } - callchain_store(entry, next_ip); + perf_callchain_store(entry, next_ip); if (!valid_next_sp(next_sp, sp)) return; sp = next_sp; @@ -246,8 +234,8 @@ static void perf_callchain_user_64(struct pt_regs *regs, next_ip = regs->nip; lr = regs->link; sp = regs->gpr[1]; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, next_ip); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, next_ip); for (;;) { fp = (unsigned long __user *) sp; @@ -276,14 +264,14 @@ static void perf_callchain_user_64(struct pt_regs *regs, read_user_stack_64(&uregs[PT_R1], &sp)) return; level = 0; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, next_ip); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, next_ip); continue; } if (level == 0) next_ip = lr; - callchain_store(entry, next_ip); + perf_callchain_store(entry, next_ip); ++level; sp = next_sp; } @@ -447,8 +435,8 @@ static void perf_callchain_user_32(struct pt_regs *regs, next_ip = regs->nip; lr = regs->link; sp = regs->gpr[1]; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, next_ip); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, next_ip); while (entry->nr < PERF_MAX_STACK_DEPTH) { fp = (unsigned int __user *) (unsigned long) sp; @@ -470,14 +458,14 @@ static void perf_callchain_user_32(struct pt_regs *regs, read_user_stack_32(&uregs[PT_R1], &sp)) return; level = 0; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, next_ip); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, next_ip); continue; } if (level == 0) next_ip = lr; - callchain_store(entry, next_ip); + perf_callchain_store(entry, next_ip); ++level; sp = next_sp; } diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c index 1d6dbce7a3bc..00143f3dd196 100644 --- a/arch/sh/kernel/perf_callchain.c +++ b/arch/sh/kernel/perf_callchain.c @@ -14,11 +14,6 @@ #include #include -static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip) -{ - if (entry->nr < PERF_MAX_STACK_DEPTH) - entry->ip[entry->nr++] = ip; -} static void callchain_warning(void *data, char *msg) { @@ -39,7 +34,7 @@ static void callchain_address(void *data, unsigned long addr, int reliable) struct perf_callchain_entry *entry = data; if (reliable) - callchain_store(entry, addr); + perf_callchain_store(entry, addr); } static const struct stacktrace_ops callchain_ops = { @@ -52,8 +47,8 @@ static const struct stacktrace_ops callchain_ops = { static void perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) { - callchain_store(entry, PERF_CONTEXT_KERNEL); - callchain_store(entry, regs->pc); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); + perf_callchain_store(entry, regs->pc); unwind_stack(NULL, regs, NULL, &callchain_ops, entry); } diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 357ced3c33ff..2a95a9079862 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1283,12 +1283,6 @@ void __init init_hw_perf_events(void) register_die_notifier(&perf_event_nmi_notifier); } -static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip) -{ - if (entry->nr < PERF_MAX_STACK_DEPTH) - entry->ip[entry->nr++] = ip; -} - static void perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) { @@ -1297,8 +1291,8 @@ static void perf_callchain_kernel(struct pt_regs *regs, int graph = 0; #endif - callchain_store(entry, PERF_CONTEXT_KERNEL); - callchain_store(entry, regs->tpc); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); + perf_callchain_store(entry, regs->tpc); ksp = regs->u_regs[UREG_I6]; fp = ksp + STACK_BIAS; @@ -1322,13 +1316,13 @@ static void perf_callchain_kernel(struct pt_regs *regs, pc = sf->callers_pc; fp = (unsigned long)sf->fp + STACK_BIAS; } - callchain_store(entry, pc); + perf_callchain_store(entry, pc); #ifdef CONFIG_FUNCTION_GRAPH_TRACER if ((pc + 8UL) == (unsigned long) &return_to_handler) { int index = current->curr_ret_stack; if (current->ret_stack && index >= graph) { pc = current->ret_stack[index - graph].ret; - callchain_store(entry, pc); + perf_callchain_store(entry, pc); graph++; } } @@ -1341,8 +1335,8 @@ static void perf_callchain_user_64(struct pt_regs *regs, { unsigned long ufp; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, regs->tpc); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, regs->tpc); ufp = regs->u_regs[UREG_I6] + STACK_BIAS; do { @@ -1355,7 +1349,7 @@ static void perf_callchain_user_64(struct pt_regs *regs, pc = sf.callers_pc; ufp = (unsigned long)sf.fp + STACK_BIAS; - callchain_store(entry, pc); + perf_callchain_store(entry, pc); } while (entry->nr < PERF_MAX_STACK_DEPTH); } @@ -1364,8 +1358,8 @@ static void perf_callchain_user_32(struct pt_regs *regs, { unsigned long ufp; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, regs->tpc); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, regs->tpc); ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; do { @@ -1378,7 +1372,7 @@ static void perf_callchain_user_32(struct pt_regs *regs, pc = sf.callers_pc; ufp = (unsigned long)sf.fp; - callchain_store(entry, pc); + perf_callchain_store(entry, pc); } while (entry->nr < PERF_MAX_STACK_DEPTH); } diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 4a4d191f9492..8af28caeafc1 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -1571,12 +1571,6 @@ const struct pmu *hw_perf_event_init(struct perf_event *event) * callchain support */ -static inline -void callchain_store(struct perf_callchain_entry *entry, u64 ip) -{ - if (entry->nr < PERF_MAX_STACK_DEPTH) - entry->ip[entry->nr++] = ip; -} static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); @@ -1602,7 +1596,7 @@ static void backtrace_address(void *data, unsigned long addr, int reliable) { struct perf_callchain_entry *entry = data; - callchain_store(entry, addr); + perf_callchain_store(entry, addr); } static const struct stacktrace_ops backtrace_ops = { @@ -1616,8 +1610,8 @@ static const struct stacktrace_ops backtrace_ops = { static void perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) { - callchain_store(entry, PERF_CONTEXT_KERNEL); - callchain_store(entry, regs->ip); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); + perf_callchain_store(entry, regs->ip); dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); } @@ -1646,7 +1640,7 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) if (fp < compat_ptr(regs->sp)) break; - callchain_store(entry, frame.return_address); + perf_callchain_store(entry, frame.return_address); fp = compat_ptr(frame.next_frame); } return 1; @@ -1670,8 +1664,8 @@ perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) fp = (void __user *)regs->bp; - callchain_store(entry, PERF_CONTEXT_USER); - callchain_store(entry, regs->ip); + perf_callchain_store(entry, PERF_CONTEXT_USER); + perf_callchain_store(entry, regs->ip); if (perf_callchain_user32(regs, entry)) return; @@ -1688,7 +1682,7 @@ perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) if ((unsigned long)fp < regs->sp) break; - callchain_store(entry, frame.return_address); + perf_callchain_store(entry, frame.return_address); fp = frame.next_frame; } } diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 937495c25073..358880404b42 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -978,6 +978,13 @@ extern void perf_event_fork(struct task_struct *tsk); extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); +static inline void +perf_callchain_store(struct perf_callchain_entry *entry, u64 ip) +{ + if (entry->nr < PERF_MAX_STACK_DEPTH) + entry->ip[entry->nr++] = ip; +} + extern int sysctl_perf_event_paranoid; extern int sysctl_perf_event_mlock; extern int sysctl_perf_event_sample_rate; -- cgit v1.2.3 From 56962b4449af34070bb1994621ef4f0265eed4d8 Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 30 Jun 2010 23:03:51 +0200 Subject: perf: Generalize some arch callchain code - Most archs use one callchain buffer per cpu, except x86 that needs to deal with NMIs. Provide a default perf_callchain_buffer() implementation that x86 overrides. - Centralize all the kernel/user regs handling and invoke new arch handlers from there: perf_callchain_user() / perf_callchain_kernel() That avoid all the user_mode(), current->mm checks and so... - Invert some parameters in perf_callchain_*() helpers: entry to the left, regs to the right, following the traditional (dst, src). Signed-off-by: Frederic Weisbecker Acked-by: Paul Mackerras Tested-by: Will Deacon Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Arnaldo Carvalho de Melo Cc: Stephane Eranian Cc: David Miller Cc: Paul Mundt Cc: Borislav Petkov --- arch/arm/kernel/perf_event.c | 43 +++---------------------------- arch/powerpc/kernel/perf_callchain.c | 49 +++++++++++------------------------- arch/sh/kernel/perf_callchain.c | 37 ++------------------------- arch/sparc/kernel/perf_event.c | 46 +++++++++++---------------------- arch/x86/kernel/cpu/perf_event.c | 45 ++++++--------------------------- include/linux/perf_event.h | 10 +++++++- kernel/perf_event.c | 40 +++++++++++++++++++++++++++-- 7 files changed, 90 insertions(+), 180 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index a07c3b1955f0..0e3bbdb15927 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -3044,17 +3044,13 @@ user_backtrace(struct frame_tail *tail, return buftail.fp - 1; } -static void -perf_callchain_user(struct pt_regs *regs, - struct perf_callchain_entry *entry) +void +perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { struct frame_tail *tail; perf_callchain_store(entry, PERF_CONTEXT_USER); - if (!user_mode(regs)) - regs = task_pt_regs(current); - tail = (struct frame_tail *)regs->ARM_fp - 1; while (tail && !((unsigned long)tail & 0x3)) @@ -3075,9 +3071,8 @@ callchain_trace(struct stackframe *fr, return 0; } -static void -perf_callchain_kernel(struct pt_regs *regs, - struct perf_callchain_entry *entry) +void +perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { struct stackframe fr; @@ -3088,33 +3083,3 @@ perf_callchain_kernel(struct pt_regs *regs, fr.pc = regs->ARM_pc; walk_stackframe(&fr, callchain_trace, entry); } - -static void -perf_do_callchain(struct pt_regs *regs, - struct perf_callchain_entry *entry) -{ - int is_user; - - if (!regs) - return; - - is_user = user_mode(regs); - - if (!is_user) - perf_callchain_kernel(regs, entry); - - if (current->mm) - perf_callchain_user(regs, entry); -} - -static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); - -struct perf_callchain_entry * -perf_callchain(struct pt_regs *regs) -{ - struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry); - - entry->nr = 0; - perf_do_callchain(regs, entry); - return entry; -} diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c index a286c2e5a3ea..f7a85ede8407 100644 --- a/arch/powerpc/kernel/perf_callchain.c +++ b/arch/powerpc/kernel/perf_callchain.c @@ -46,8 +46,8 @@ static int valid_next_sp(unsigned long sp, unsigned long prev_sp) return 0; } -static void perf_callchain_kernel(struct pt_regs *regs, - struct perf_callchain_entry *entry) +void +perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { unsigned long sp, next_sp; unsigned long next_ip; @@ -221,8 +221,8 @@ static int sane_signal_64_frame(unsigned long sp) puc == (unsigned long) &sf->uc; } -static void perf_callchain_user_64(struct pt_regs *regs, - struct perf_callchain_entry *entry) +static void perf_callchain_user_64(struct perf_callchain_entry *entry, + struct pt_regs *regs) { unsigned long sp, next_sp; unsigned long next_ip; @@ -303,8 +303,8 @@ static int read_user_stack_32(unsigned int __user *ptr, unsigned int *ret) return __get_user_inatomic(*ret, ptr); } -static inline void perf_callchain_user_64(struct pt_regs *regs, - struct perf_callchain_entry *entry) +static inline void perf_callchain_user_64(struct perf_callchain_entry *entry, + struct pt_regs *regs) { } @@ -423,8 +423,8 @@ static unsigned int __user *signal_frame_32_regs(unsigned int sp, return mctx->mc_gregs; } -static void perf_callchain_user_32(struct pt_regs *regs, - struct perf_callchain_entry *entry) +static void perf_callchain_user_32(struct perf_callchain_entry *entry, + struct pt_regs *regs) { unsigned int sp, next_sp; unsigned int next_ip; @@ -471,32 +471,11 @@ static void perf_callchain_user_32(struct pt_regs *regs, } } -/* - * Since we can't get PMU interrupts inside a PMU interrupt handler, - * we don't need separate irq and nmi entries here. - */ -static DEFINE_PER_CPU(struct perf_callchain_entry, cpu_perf_callchain); - -struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) +void +perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { - struct perf_callchain_entry *entry = &__get_cpu_var(cpu_perf_callchain); - - entry->nr = 0; - - if (!user_mode(regs)) { - perf_callchain_kernel(regs, entry); - if (current->mm) - regs = task_pt_regs(current); - else - regs = NULL; - } - - if (regs) { - if (current_is_64bit()) - perf_callchain_user_64(regs, entry); - else - perf_callchain_user_32(regs, entry); - } - - return entry; + if (current_is_64bit()) + perf_callchain_user_64(entry, regs); + else + perf_callchain_user_32(entry, regs); } diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c index 00143f3dd196..ef076a91292a 100644 --- a/arch/sh/kernel/perf_callchain.c +++ b/arch/sh/kernel/perf_callchain.c @@ -44,44 +44,11 @@ static const struct stacktrace_ops callchain_ops = { .address = callchain_address, }; -static void -perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) +void +perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->pc); unwind_stack(NULL, regs, NULL, &callchain_ops, entry); } - -static void -perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) -{ - int is_user; - - if (!regs) - return; - - is_user = user_mode(regs); - - /* - * Only the kernel side is implemented for now. - */ - if (!is_user) - perf_callchain_kernel(regs, entry); -} - -/* - * No need for separate IRQ and NMI entries. - */ -static DEFINE_PER_CPU(struct perf_callchain_entry, callchain); - -struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) -{ - struct perf_callchain_entry *entry = &__get_cpu_var(callchain); - - entry->nr = 0; - - perf_do_callchain(regs, entry); - - return entry; -} diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 2a95a9079862..460162d74aba 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1283,14 +1283,16 @@ void __init init_hw_perf_events(void) register_die_notifier(&perf_event_nmi_notifier); } -static void perf_callchain_kernel(struct pt_regs *regs, - struct perf_callchain_entry *entry) +void perf_callchain_kernel(struct perf_callchain_entry *entry, + struct pt_regs *regs) { unsigned long ksp, fp; #ifdef CONFIG_FUNCTION_GRAPH_TRACER int graph = 0; #endif + stack_trace_flush(); + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->tpc); @@ -1330,8 +1332,8 @@ static void perf_callchain_kernel(struct pt_regs *regs, } while (entry->nr < PERF_MAX_STACK_DEPTH); } -static void perf_callchain_user_64(struct pt_regs *regs, - struct perf_callchain_entry *entry) +static void perf_callchain_user_64(struct perf_callchain_entry *entry, + struct pt_regs *regs) { unsigned long ufp; @@ -1353,8 +1355,8 @@ static void perf_callchain_user_64(struct pt_regs *regs, } while (entry->nr < PERF_MAX_STACK_DEPTH); } -static void perf_callchain_user_32(struct pt_regs *regs, - struct perf_callchain_entry *entry) +static void perf_callchain_user_32(struct perf_callchain_entry *entry, + struct pt_regs *regs) { unsigned long ufp; @@ -1376,30 +1378,12 @@ static void perf_callchain_user_32(struct pt_regs *regs, } while (entry->nr < PERF_MAX_STACK_DEPTH); } -/* Like powerpc we can't get PMU interrupts within the PMU handler, - * so no need for separate NMI and IRQ chains as on x86. - */ -static DEFINE_PER_CPU(struct perf_callchain_entry, callchain); - -struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) +void +perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { - struct perf_callchain_entry *entry = &__get_cpu_var(callchain); - - entry->nr = 0; - if (!user_mode(regs)) { - stack_trace_flush(); - perf_callchain_kernel(regs, entry); - if (current->mm) - regs = task_pt_regs(current); - else - regs = NULL; - } - if (regs) { - flushw_user(); - if (test_thread_flag(TIF_32BIT)) - perf_callchain_user_32(regs, entry); - else - perf_callchain_user_64(regs, entry); - } - return entry; + flushw_user(); + if (test_thread_flag(TIF_32BIT)) + perf_callchain_user_32(entry, regs); + else + perf_callchain_user_64(entry, regs); } diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 8af28caeafc1..39f8421b86e6 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -1571,9 +1571,7 @@ const struct pmu *hw_perf_event_init(struct perf_event *event) * callchain support */ - -static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); -static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); +static DEFINE_PER_CPU(struct perf_callchain_entry, perf_callchain_entry_nmi); static void @@ -1607,8 +1605,8 @@ static const struct stacktrace_ops backtrace_ops = { .walk_stack = print_context_stack_bp, }; -static void -perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) +void +perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->ip); @@ -1653,14 +1651,12 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) } #endif -static void -perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) +void +perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { struct stack_frame frame; const void __user *fp; - if (!user_mode(regs)) - regs = task_pt_regs(current); fp = (void __user *)regs->bp; @@ -1687,42 +1683,17 @@ perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) } } -static void -perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) -{ - int is_user; - - if (!regs) - return; - - is_user = user_mode(regs); - - if (!is_user) - perf_callchain_kernel(regs, entry); - - if (current->mm) - perf_callchain_user(regs, entry); -} - -struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) +struct perf_callchain_entry *perf_callchain_buffer(void) { - struct perf_callchain_entry *entry; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { /* TODO: We don't support guest os callchain now */ return NULL; } if (in_nmi()) - entry = &__get_cpu_var(pmc_nmi_entry); - else - entry = &__get_cpu_var(pmc_irq_entry); - - entry->nr = 0; - - perf_do_callchain(regs, entry); + return &__get_cpu_var(perf_callchain_entry_nmi); - return entry; + return &__get_cpu_var(perf_callchain_entry); } unsigned long perf_instruction_pointer(struct pt_regs *regs) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 358880404b42..4db61dded388 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -976,7 +976,15 @@ extern int perf_unregister_guest_info_callbacks(struct perf_guest_info_callbacks extern void perf_event_comm(struct task_struct *tsk); extern void perf_event_fork(struct task_struct *tsk); -extern struct perf_callchain_entry *perf_callchain(struct pt_regs *regs); +/* Callchains */ +DECLARE_PER_CPU(struct perf_callchain_entry, perf_callchain_entry); + +extern void perf_callchain_user(struct perf_callchain_entry *entry, + struct pt_regs *regs); +extern void perf_callchain_kernel(struct perf_callchain_entry *entry, + struct pt_regs *regs); +extern struct perf_callchain_entry *perf_callchain_buffer(void); + static inline void perf_callchain_store(struct perf_callchain_entry *entry, u64 ip) diff --git a/kernel/perf_event.c b/kernel/perf_event.c index c772a3d4000d..02efde6c8798 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -2937,13 +2937,49 @@ void perf_event_do_pending(void) __perf_pending_run(); } +DEFINE_PER_CPU(struct perf_callchain_entry, perf_callchain_entry); + /* * Callchain support -- arch specific */ -__weak struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) +__weak struct perf_callchain_entry *perf_callchain_buffer(void) { - return NULL; + return &__get_cpu_var(perf_callchain_entry); +} + +__weak void perf_callchain_kernel(struct perf_callchain_entry *entry, + struct pt_regs *regs) +{ +} + +__weak void perf_callchain_user(struct perf_callchain_entry *entry, + struct pt_regs *regs) +{ +} + +static struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) +{ + struct perf_callchain_entry *entry; + + entry = perf_callchain_buffer(); + if (!entry) + return NULL; + + entry->nr = 0; + + if (!user_mode(regs)) { + perf_callchain_kernel(entry, regs); + if (current->mm) + regs = task_pt_regs(current); + else + regs = NULL; + } + + if (regs) + perf_callchain_user(entry, regs); + + return entry; } -- cgit v1.2.3 From f72c1a931e311bb7780fee19e41a89ac42cab50e Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Thu, 1 Jul 2010 02:31:21 +0200 Subject: perf: Factorize callchain context handling Store the kernel and user contexts from the generic layer instead of archs, this gathers some repetitive code. Signed-off-by: Frederic Weisbecker Acked-by: Paul Mackerras Tested-by: Will Deacon Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Arnaldo Carvalho de Melo Cc: Stephane Eranian Cc: David Miller Cc: Paul Mundt Cc: Borislav Petkov --- arch/arm/kernel/perf_event.c | 2 -- arch/powerpc/kernel/perf_callchain.c | 3 --- arch/sh/kernel/perf_callchain.c | 1 - arch/sparc/kernel/perf_event.c | 3 --- arch/x86/kernel/cpu/perf_event.c | 2 -- kernel/perf_event.c | 5 ++++- 6 files changed, 4 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 0e3bbdb15927..64ca8c3ab94b 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -3049,7 +3049,6 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) { struct frame_tail *tail; - perf_callchain_store(entry, PERF_CONTEXT_USER); tail = (struct frame_tail *)regs->ARM_fp - 1; @@ -3076,7 +3075,6 @@ perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { struct stackframe fr; - perf_callchain_store(entry, PERF_CONTEXT_KERNEL); fr.fp = regs->ARM_fp; fr.sp = regs->ARM_sp; fr.lr = regs->ARM_lr; diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c index f7a85ede8407..d05ae4204bbf 100644 --- a/arch/powerpc/kernel/perf_callchain.c +++ b/arch/powerpc/kernel/perf_callchain.c @@ -57,7 +57,6 @@ perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) lr = regs->link; sp = regs->gpr[1]; - perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->nip); if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD)) @@ -234,7 +233,6 @@ static void perf_callchain_user_64(struct perf_callchain_entry *entry, next_ip = regs->nip; lr = regs->link; sp = regs->gpr[1]; - perf_callchain_store(entry, PERF_CONTEXT_USER); perf_callchain_store(entry, next_ip); for (;;) { @@ -435,7 +433,6 @@ static void perf_callchain_user_32(struct perf_callchain_entry *entry, next_ip = regs->nip; lr = regs->link; sp = regs->gpr[1]; - perf_callchain_store(entry, PERF_CONTEXT_USER); perf_callchain_store(entry, next_ip); while (entry->nr < PERF_MAX_STACK_DEPTH) { diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c index ef076a91292a..d5ca1ef50fa9 100644 --- a/arch/sh/kernel/perf_callchain.c +++ b/arch/sh/kernel/perf_callchain.c @@ -47,7 +47,6 @@ static const struct stacktrace_ops callchain_ops = { void perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { - perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->pc); unwind_stack(NULL, regs, NULL, &callchain_ops, entry); diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 460162d74aba..4bc402938575 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1293,7 +1293,6 @@ void perf_callchain_kernel(struct perf_callchain_entry *entry, stack_trace_flush(); - perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->tpc); ksp = regs->u_regs[UREG_I6]; @@ -1337,7 +1336,6 @@ static void perf_callchain_user_64(struct perf_callchain_entry *entry, { unsigned long ufp; - perf_callchain_store(entry, PERF_CONTEXT_USER); perf_callchain_store(entry, regs->tpc); ufp = regs->u_regs[UREG_I6] + STACK_BIAS; @@ -1360,7 +1358,6 @@ static void perf_callchain_user_32(struct perf_callchain_entry *entry, { unsigned long ufp; - perf_callchain_store(entry, PERF_CONTEXT_USER); perf_callchain_store(entry, regs->tpc); ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 39f8421b86e6..a3c922288cc0 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -1608,7 +1608,6 @@ static const struct stacktrace_ops backtrace_ops = { void perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) { - perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_store(entry, regs->ip); dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); @@ -1660,7 +1659,6 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) fp = (void __user *)regs->bp; - perf_callchain_store(entry, PERF_CONTEXT_USER); perf_callchain_store(entry, regs->ip); if (perf_callchain_user32(regs, entry)) diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 02efde6c8798..615d024894cf 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -2969,6 +2969,7 @@ static struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) entry->nr = 0; if (!user_mode(regs)) { + perf_callchain_store(entry, PERF_CONTEXT_KERNEL); perf_callchain_kernel(entry, regs); if (current->mm) regs = task_pt_regs(current); @@ -2976,8 +2977,10 @@ static struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) regs = NULL; } - if (regs) + if (regs) { + perf_callchain_store(entry, PERF_CONTEXT_USER); perf_callchain_user(entry, regs); + } return entry; } -- cgit v1.2.3 From 2971944582ff43b7dedbb460777052243ac9915a Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Mon, 9 Aug 2010 12:54:43 +0100 Subject: ARM: 6307/1: mmci: allow the card detect GPIO value not to be inverted On some platforms, the GPIO value from the gpio_cd pin doesn't need to be inverted to get it active high. Add a cd_invert platform data parameter and change existing platforms using GPIO for CD (only Realview) to enable it. Acked-by: Linus Walleij Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/mach-realview/core.c | 2 ++ drivers/mmc/host/mmci.c | 5 +++-- include/linux/amba/mmci.h | 2 ++ 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 2fa38df28414..07c08151dfe6 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -259,6 +259,7 @@ struct mmci_platform_data realview_mmc0_plat_data = { .status = realview_mmc_status, .gpio_wp = 17, .gpio_cd = 16, + .cd_invert = true, }; struct mmci_platform_data realview_mmc1_plat_data = { @@ -266,6 +267,7 @@ struct mmci_platform_data realview_mmc1_plat_data = { .status = realview_mmc_status, .gpio_wp = 19, .gpio_cd = 18, + .cd_invert = true, }; /* diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 840b301b5671..9a9aeac50a6c 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -570,12 +570,13 @@ static int mmci_get_ro(struct mmc_host *mmc) static int mmci_get_cd(struct mmc_host *mmc) { struct mmci_host *host = mmc_priv(mmc); + struct mmci_platform_data *plat = host->plat; unsigned int status; if (host->gpio_cd == -ENOSYS) - status = host->plat->status(mmc_dev(host->mmc)); + status = plat->status(mmc_dev(host->mmc)); else - status = !gpio_get_value(host->gpio_cd); + status = !!gpio_get_value(host->gpio_cd) ^ plat->cd_invert; /* * Use positive logic throughout - status is zero for no card, diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h index ca84ce70d5d5..f4ee9acc9721 100644 --- a/include/linux/amba/mmci.h +++ b/include/linux/amba/mmci.h @@ -24,6 +24,7 @@ * whether a card is present in the MMC slot or not * @gpio_wp: read this GPIO pin to see if the card is write protected * @gpio_cd: read this GPIO pin to detect card insertion + * @cd_invert: true if the gpio_cd pin value is active low * @capabilities: the capabilities of the block as implemented in * this platform, signify anything MMC_CAP_* from mmc/host.h */ @@ -35,6 +36,7 @@ struct mmci_platform_data { unsigned int (*status)(struct device *); int gpio_wp; int gpio_cd; + bool cd_invert; unsigned long capabilities; }; -- cgit v1.2.3 From c7fd239a647ead1c336a051012d6bb96465ea8c6 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Sun, 29 Aug 2010 14:52:00 -0400 Subject: ARM: oprofile: fix and simplify init/exit functions Now that oprofile_arch_exit is only called when the OProfile module is unloaded, it can assume that init completed successfully and not have to worry about double frees or releasing NULL perf events. This patch ensures that oprofile_arch_init fails gracefully on ARM and simplifies the exit code based on the above. Cc: Robert Richter Cc: Matt Fleming Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon Signed-off-by: Robert Richter --- arch/arm/oprofile/common.c | 47 ++++++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 0691176899ff..c3652f73fed4 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -275,7 +275,7 @@ out: return ret; } -static void exit_driverfs(void) +static void __exit exit_driverfs(void) { platform_device_unregister(oprofile_pdev); platform_driver_unregister(&oprofile_driver); @@ -359,14 +359,13 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) if (!counter_config) { pr_info("oprofile: failed to allocate %d " "counters\n", perf_num_counters); - return -ENOMEM; + ret = -ENOMEM; + goto out; } ret = init_driverfs(); - if (ret) { - kfree(counter_config); - return ret; - } + if (ret) + goto out; for_each_possible_cpu(cpu) { perf_events[cpu] = kcalloc(perf_num_counters, @@ -374,9 +373,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) if (!perf_events[cpu]) { pr_info("oprofile: failed to allocate %d perf events " "for cpu %d\n", perf_num_counters, cpu); - while (--cpu >= 0) - kfree(perf_events[cpu]); - return -ENOMEM; + ret = -ENOMEM; + goto out; } } @@ -393,28 +391,33 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) else pr_info("oprofile: using %s\n", ops->cpu_type); +out: + if (ret) { + for_each_possible_cpu(cpu) + kfree(perf_events[cpu]); + kfree(counter_config); + } + return ret; } -void oprofile_arch_exit(void) +void __exit oprofile_arch_exit(void) { int cpu, id; struct perf_event *event; - if (*perf_events) { - exit_driverfs(); - for_each_possible_cpu(cpu) { - for (id = 0; id < perf_num_counters; ++id) { - event = perf_events[cpu][id]; - if (event != NULL) - perf_event_release_kernel(event); - } - kfree(perf_events[cpu]); + for_each_possible_cpu(cpu) { + for (id = 0; id < perf_num_counters; ++id) { + event = perf_events[cpu][id]; + if (event) + perf_event_release_kernel(event); } + + kfree(perf_events[cpu]); } - if (counter_config) - kfree(counter_config); + kfree(counter_config); + exit_driverfs(); } #else int __init oprofile_arch_init(struct oprofile_operations *ops) @@ -422,5 +425,5 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) pr_info("oprofile: hardware counters not available\n"); return -ENODEV; } -void oprofile_arch_exit(void) {} +void __exit oprofile_arch_exit(void) {} #endif /* CONFIG_HW_PERF_EVENTS */ -- cgit v1.2.3 From 4cbe75be5c6ae86bdc7daec864eeb2dfd66f48bb Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Mon, 30 Aug 2010 18:21:55 +0200 Subject: oprofile, arm: initialize perf_event pointers with NULL The pointers must be NULL'ed to avoid double-freeing the pointers in rare cases during reinitialization. Signed-off-by: Robert Richter --- arch/arm/oprofile/common.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index c3652f73fed4..d660cb8dab36 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -351,6 +351,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) { int cpu, ret = 0; + memset(&perf_events, 0, sizeof(perf_events)); + perf_num_counters = armpmu_get_max_events(); counter_config = kcalloc(perf_num_counters, -- cgit v1.2.3 From a17f79553f052f04d47689a842118f775f81b7e3 Mon Sep 17 00:00:00 2001 From: Abraham Arce Date: Tue, 31 Aug 2010 17:05:27 -0700 Subject: Input: add support for OMAP4 keyboard controller OMAP4 keyboard controller includes: - built-in scanning algorithm - debouncing feature Driver implementation is based on matrix_keypad.c Signed-off-by: Syed Rafiuddin Signed-off-by: Abraham Arce Signed-off-by: Dmitry Torokhov --- arch/arm/plat-omap/include/plat/omap4-keypad.h | 16 ++ drivers/input/keyboard/Kconfig | 9 + drivers/input/keyboard/Makefile | 1 + drivers/input/keyboard/omap4-keypad.c | 287 +++++++++++++++++++++++++ 4 files changed, 313 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/omap4-keypad.h create mode 100644 drivers/input/keyboard/omap4-keypad.c (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h new file mode 100644 index 000000000000..522a8ab5c5ff --- /dev/null +++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h @@ -0,0 +1,16 @@ +#ifndef ARCH_ARM_PLAT_OMAP4_KEYPAD_H +#define ARCH_ARM_PLAT_OMAP4_KEYPAD_H + +#include + +struct omap4_keypad_platform_data { + const struct matrix_keymap_data *keymap_data; + + u8 rows; + u8 cols; + + u16 irq; + void __iomem *base; +}; + +#endif diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index 9cc488d21490..4f300488e1f3 100644 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -424,6 +424,15 @@ config KEYBOARD_OMAP To compile this driver as a module, choose M here: the module will be called omap-keypad. +config KEYBOARD_OMAP4 + tristate "TI OMAP4 keypad support" + depends on ARCH_OMAP4 + help + Say Y here if you want to use the OMAP4 keypad. + + To compile this driver as a module, choose M here: the + module will be called omap4-keypad. + config KEYBOARD_TWL4030 tristate "TI TWL4030/TWL5030/TPS659x0 keypad support" depends on TWL4030_CORE diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index 504b591be0cd..8ac01fb642c1 100644 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_KEYBOARD_MAX7359) += max7359_keypad.o obj-$(CONFIG_KEYBOARD_MCS) += mcs_touchkey.o obj-$(CONFIG_KEYBOARD_NEWTON) += newtonkbd.o obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o +obj-$(CONFIG_KEYBOARD_OMAP4) += omap4-keypad.o obj-$(CONFIG_KEYBOARD_OPENCORES) += opencores-kbd.o obj-$(CONFIG_KEYBOARD_PXA27x) += pxa27x_keypad.o obj-$(CONFIG_KEYBOARD_PXA930_ROTARY) += pxa930_rotary.o diff --git a/drivers/input/keyboard/omap4-keypad.c b/drivers/input/keyboard/omap4-keypad.c new file mode 100644 index 000000000000..975f8bbcc69b --- /dev/null +++ b/drivers/input/keyboard/omap4-keypad.c @@ -0,0 +1,287 @@ +/* + * OMAP4 Keypad Driver + * + * Copyright (C) 2010 Texas Instruments + * + * Author: Abraham Arce + * Initial Code: Syed Rafiuddin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* OMAP4 registers */ +#define OMAP4_KBD_REVISION 0x00 +#define OMAP4_KBD_SYSCONFIG 0x10 +#define OMAP4_KBD_SYSSTATUS 0x14 +#define OMAP4_KBD_IRQSTATUS 0x18 +#define OMAP4_KBD_IRQENABLE 0x1C +#define OMAP4_KBD_WAKEUPENABLE 0x20 +#define OMAP4_KBD_PENDING 0x24 +#define OMAP4_KBD_CTRL 0x28 +#define OMAP4_KBD_DEBOUNCINGTIME 0x2C +#define OMAP4_KBD_LONGKEYTIME 0x30 +#define OMAP4_KBD_TIMEOUT 0x34 +#define OMAP4_KBD_STATEMACHINE 0x38 +#define OMAP4_KBD_ROWINPUTS 0x3C +#define OMAP4_KBD_COLUMNOUTPUTS 0x40 +#define OMAP4_KBD_FULLCODE31_0 0x44 +#define OMAP4_KBD_FULLCODE63_32 0x48 + +/* OMAP4 bit definitions */ +#define OMAP4_DEF_SYSCONFIG_SOFTRST (1 << 1) +#define OMAP4_DEF_SYSCONFIG_ENAWKUP (1 << 2) +#define OMAP4_DEF_IRQENABLE_EVENTEN (1 << 0) +#define OMAP4_DEF_IRQENABLE_LONGKEY (1 << 1) +#define OMAP4_DEF_IRQENABLE_TIMEOUTEN (1 << 2) +#define OMAP4_DEF_CTRL_NOSOFTMODE (1 << 1) +#define OMAP4_DEF_CTRLPTVVALUE (1 << 2) +#define OMAP4_DEF_CTRLPTV (1 << 1) +#define OMAP4_DEF_IRQDISABLE 0x00 + +/* OMAP4 values */ +#define OMAP4_VAL_DEBOUNCINGTIME 0x07 +#define OMAP4_VAL_FUNCTIONALCFG 0x1E + +#define OMAP4_MASK_IRQSTATUSDISABLE 0xFFFF + +struct omap4_keypad { + struct input_dev *input; + + void __iomem *base; + int irq; + + unsigned int rows; + unsigned int cols; + unsigned int row_shift; + unsigned char key_state[8]; + unsigned short keymap[]; +}; + +static void __devinit omap4_keypad_config(struct omap4_keypad *keypad_data) +{ + __raw_writel(OMAP4_DEF_SYSCONFIG_SOFTRST | OMAP4_DEF_SYSCONFIG_ENAWKUP, + keypad_data->base + OMAP4_KBD_SYSCONFIG); + __raw_writel(OMAP4_VAL_FUNCTIONALCFG, + keypad_data->base + OMAP4_KBD_CTRL); + __raw_writel(OMAP4_VAL_DEBOUNCINGTIME, + keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME); + __raw_writel(OMAP4_DEF_IRQDISABLE, + keypad_data->base + OMAP4_KBD_IRQSTATUS); + __raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY, + keypad_data->base + OMAP4_KBD_IRQENABLE); +} + +/* Interrupt handler */ +static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id) +{ + struct omap4_keypad *keypad_data = dev_id; + struct input_dev *input_dev = keypad_data->input; + unsigned char key_state[ARRAY_SIZE(keypad_data->key_state)]; + unsigned int col, row, code, changed; + u32 *new_state = (u32 *) key_state; + + /* Disable interrupts */ + __raw_writel(OMAP4_DEF_IRQDISABLE, + keypad_data->base + OMAP4_KBD_IRQENABLE); + + *new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0); + *(new_state + 1) = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE63_32); + + for (row = 0; row < keypad_data->rows; row++) { + changed = key_state[row] ^ keypad_data->key_state[row]; + if (!changed) + continue; + + for (col = 0; col < keypad_data->cols; col++) { + if (changed & (1 << col)) { + code = MATRIX_SCAN_CODE(row, col, + keypad_data->row_shift); + input_event(input_dev, EV_MSC, MSC_SCAN, code); + input_report_key(input_dev, + keypad_data->keymap[code], + key_state[row] & (1 << col)); + } + } + } + + input_sync(input_dev); + + memcpy(keypad_data->key_state, key_state, + sizeof(keypad_data->key_state)); + + /* clear pending interrupts */ + __raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS), + keypad_data->base + OMAP4_KBD_IRQSTATUS); + + /* enable interrupts */ + __raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN | OMAP4_DEF_IRQENABLE_LONGKEY, + keypad_data->base + OMAP4_KBD_IRQENABLE); + + return IRQ_HANDLED; +} + +static int __devinit omap4_keypad_probe(struct platform_device *pdev) +{ + const struct omap4_keypad_platform_data *pdata; + struct omap4_keypad *keypad_data; + struct input_dev *input_dev; + unsigned int row_shift, max_keys; + int error; + + /* platform data */ + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "no platform data defined\n"); + return -EINVAL; + } + + if (!pdata->base) { + dev_err(&pdev->dev, "no base address specified\n"); + return -EINVAL; + } + + if (!pdata->irq) { + dev_err(&pdev->dev, "no keyboard irq assigned\n"); + return -EINVAL; + } + + if (!pdata->keymap_data) { + dev_err(&pdev->dev, "no keymap data defined\n"); + return -EINVAL; + } + + row_shift = get_count_order(pdata->cols); + max_keys = pdata->rows << row_shift; + + keypad_data = kzalloc(sizeof(struct omap4_keypad) + + max_keys * sizeof(keypad_data->keymap[0]), + GFP_KERNEL); + if (!keypad_data) { + dev_err(&pdev->dev, "keypad_data memory allocation failed\n"); + return -ENOMEM; + } + + keypad_data->base = pdata->base; + keypad_data->irq = pdata->irq; + + keypad_data->row_shift = row_shift; + keypad_data->rows = pdata->rows; + keypad_data->cols = pdata->cols; + + /* input device allocation */ + keypad_data->input = input_dev = input_allocate_device(); + if (!input_dev) { + error = -ENOMEM; + goto err_free_keypad; + } + + input_dev->name = pdev->name; + input_dev->dev.parent = &pdev->dev; + input_dev->id.bustype = BUS_HOST; + input_dev->id.vendor = 0x0001; + input_dev->id.product = 0x0001; + input_dev->id.version = 0x0001; + + input_dev->keycode = keypad_data->keymap; + input_dev->keycodesize = sizeof(keypad_data->keymap[0]); + input_dev->keycodemax = max_keys; + + __set_bit(EV_KEY, input_dev->evbit); + __set_bit(EV_REP, input_dev->evbit); + + input_set_capability(input_dev, EV_MSC, MSC_SCAN); + + input_set_drvdata(input_dev, keypad_data); + + matrix_keypad_build_keymap(pdata->keymap_data, row_shift, + input_dev->keycode, input_dev->keybit); + + omap4_keypad_config(keypad_data); + + error = request_irq(keypad_data->irq, omap4_keypad_interrupt, + IRQF_TRIGGER_FALLING, + "omap4-keypad", keypad_data); + if (error) { + dev_err(&pdev->dev, "failed to register interrupt\n"); + goto err_free_input; + } + + error = input_register_device(keypad_data->input); + if (error < 0) { + dev_err(&pdev->dev, "failed to register input device\n"); + goto err_free_irq; + } + + + platform_set_drvdata(pdev, keypad_data); + return 0; + +err_free_irq: + free_irq(keypad_data->irq, keypad_data); +err_free_input: + input_free_device(input_dev); +err_free_keypad: + kfree(keypad_data); + return error; +} + +static int __devexit omap4_keypad_remove(struct platform_device *pdev) +{ + struct omap4_keypad *keypad_data = platform_get_drvdata(pdev); + + free_irq(keypad_data->irq, keypad_data); + input_unregister_device(keypad_data->input); + kfree(keypad_data); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver omap4_keypad_driver = { + .probe = omap4_keypad_probe, + .remove = __devexit_p(omap4_keypad_remove), + .driver = { + .name = "omap4-keypad", + .owner = THIS_MODULE, + }, +}; + +static int __init omap4_keypad_init(void) +{ + return platform_driver_register(&omap4_keypad_driver); +} +module_init(omap4_keypad_init); + +static void __exit omap4_keypad_exit(void) +{ + platform_driver_unregister(&omap4_keypad_driver); +} +module_exit(omap4_keypad_exit); + +MODULE_AUTHOR("Texas Instruments"); +MODULE_DESCRIPTION("OMAP4 Keypad Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:omap4-keypad"); -- cgit v1.2.3 From 09bfafac3e237415cc4b6adde49f9f28b3a42659 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Tue, 10 Aug 2010 19:32:37 +0100 Subject: ARM: 6314/1: ftrace: allow build without frame pointers on ARM With a new enough GCC, ARM function tracing can be supported without the need for frame pointers. This is essential for Thumb-2 support, since frame pointers aren't available then. Acked-by: Catalin Marinas Acked-by: Steven Rostedt Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/Kconfig.debug | 5 +++++ arch/arm/kernel/armksyms.c | 2 ++ arch/arm/kernel/entry-common.S | 14 ++++++++++++++ kernel/trace/Kconfig | 2 +- 4 files changed, 22 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 91344af75f39..4dbce538fec4 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -27,6 +27,11 @@ config ARM_UNWIND the performance is not affected. Currently, this feature only works with EABI compilers. If unsure say Y. +config OLD_MCOUNT + bool + depends on FUNCTION_TRACER && FRAME_POINTER + default y + config DEBUG_USER bool "Verbose user fault messages" help diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 8214bfebfaca..e5e1e5387678 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -165,6 +165,8 @@ EXPORT_SYMBOL(_find_next_bit_be); #endif #ifdef CONFIG_FUNCTION_TRACER +#ifdef CONFIG_OLD_MCOUNT EXPORT_SYMBOL(mcount); +#endif EXPORT_SYMBOL(__gnu_mcount_nc); #endif diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index f05a35a59694..6805a7216bf8 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -128,6 +128,13 @@ ENDPROC(ret_from_fork) * allows it to be clobbered in subroutines and doesn't use it to hold * parameters.) */ + +#ifndef CONFIG_OLD_MCOUNT +#if (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 4)) +#error Ftrace requires CONFIG_FRAME_POINTER=y with GCC older than 4.4.0. +#endif +#endif + #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(mcount) stmdb sp!, {r0-r3, lr} @@ -173,6 +180,12 @@ gnu_trace: ldmia sp!, {r0-r3, ip, lr} mov pc, ip +#ifdef CONFIG_OLD_MCOUNT +/* + * This is under an ifdef in order to force link-time errors for people trying + * to build with !FRAME_POINTER with a GCC which doesn't use the new-style + * mcount. + */ ENTRY(mcount) stmdb sp!, {r0-r3, lr} ldr r0, =ftrace_trace_function @@ -191,6 +204,7 @@ trace: mov pc, r2 ldr lr, [fp, #-4] @ restore lr ldmia sp!, {r0-r3, pc} +#endif #endif /* CONFIG_DYNAMIC_FTRACE */ diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index 538501c6ea50..6329d063b5e4 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -121,7 +121,7 @@ if FTRACE config FUNCTION_TRACER bool "Kernel Function Tracer" depends on HAVE_FUNCTION_TRACER - select FRAME_POINTER + select FRAME_POINTER if (!ARM_UNWIND) select KALLSYMS select GENERIC_TRACER select CONTEXT_SWITCH_TRACER -- cgit v1.2.3 From 72fa62fa5dff0e2e06491dd99c429adb137f299b Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Tue, 10 Aug 2010 19:33:52 +0100 Subject: ARM: 6315/1: ftrace: add ENDPROC annotations When building as Thumb-2, the ".type foo, %function" annotation in ENDPROC seems to be required in order for the assembly routines to be recognized as Thumb-2 code. If the ENDPROC annotations are not present, calls to these routines are generated as BLX instead of BL. Acked-by: Catalin Marinas Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/kernel/entry-common.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 6805a7216bf8..c7a8c208a45c 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -146,6 +146,7 @@ mcount_call: bl ftrace_stub ldr lr, [fp, #-4] @ restore lr ldmia sp!, {r0-r3, pc} +ENDPROC(mcount) ENTRY(ftrace_caller) stmdb sp!, {r0-r3, lr} @@ -158,6 +159,7 @@ ftrace_call: bl ftrace_stub ldr lr, [fp, #-4] @ restore lr ldmia sp!, {r0-r3, pc} +ENDPROC(ftrace_caller) #else @@ -179,6 +181,7 @@ gnu_trace: mov pc, r2 ldmia sp!, {r0-r3, ip, lr} mov pc, ip +ENDPROC(__gnu_mcount_nc) #ifdef CONFIG_OLD_MCOUNT /* @@ -204,13 +207,14 @@ trace: mov pc, r2 ldr lr, [fp, #-4] @ restore lr ldmia sp!, {r0-r3, pc} +ENDPROC(mcount) #endif #endif /* CONFIG_DYNAMIC_FTRACE */ - .globl ftrace_stub -ftrace_stub: +ENTRY(ftrace_stub) mov pc, lr +ENDPROC(ftrace_stub) #endif /* CONFIG_FUNCTION_TRACER */ -- cgit v1.2.3 From a3ba87a614992500cf2c47e6f788e74a971ce91f Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Tue, 10 Aug 2010 19:37:21 +0100 Subject: ARM: 6316/1: ftrace: add Thumb-2 support Fix the mcount routines to build and run on a kernel built with the Thumb-2 instruction set by correcting the following errors using the fixes suggested by Catalin Marinas: - Problem: The following assembler errors appear at the "adr r0, ftrace_stub" instruction: entry-common.S: Assembler messages: entry-common.S:179: Error: invalid immediate for address calculation (value = 0x00000004) Fix: The errors don't occur with a non-global symbol, so use one. - Problem: The "mov lr, pc" does not set the lsb when storing the pc in lr. The called function returns with "bx lr", and the mode changes to ARM. Fix: Add a label on the return address and use "adr lr, BSYM(label)". We don't modify the old mcount because it won't be built when using Thumb-2. Acked-by: Catalin Marinas Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/kernel/entry-common.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index c7a8c208a45c..f5e75de0203e 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -167,7 +167,7 @@ ENTRY(__gnu_mcount_nc) stmdb sp!, {r0-r3, lr} ldr r0, =ftrace_trace_function ldr r2, [r0] - adr r0, ftrace_stub + adr r0, .Lftrace_stub cmp r0, r2 bne gnu_trace ldmia sp!, {r0-r3, ip, lr} @@ -177,8 +177,9 @@ gnu_trace: ldr r1, [sp, #20] @ lr of instrumented routine mov r0, lr sub r0, r0, #MCOUNT_INSN_SIZE - mov lr, pc + adr lr, BSYM(1f) mov pc, r2 +1: ldmia sp!, {r0-r3, ip, lr} mov pc, ip ENDPROC(__gnu_mcount_nc) @@ -213,6 +214,7 @@ ENDPROC(mcount) #endif /* CONFIG_DYNAMIC_FTRACE */ ENTRY(ftrace_stub) +.Lftrace_stub: mov pc, lr ENDPROC(ftrace_stub) -- cgit v1.2.3 From 3b6c223b1b97ad60bbb0f4efda57d649414ac2a2 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Tue, 10 Aug 2010 19:43:28 +0100 Subject: ARM: 6318/1: ftrace: fix and update dynamic ftrace This adds mcount recording and updates dynamic ftrace for ARM to work with the new ftrace dyamic tracing implementation. It also adds support for the mcount format used by newer ARM compilers. With dynamic tracing, mcount() is implemented as a nop. Callsites are patched on startup with nops, and dynamically patched to call to the ftrace_caller() routine as needed. Acked-by: Steven Rostedt [recordmcount.pl change] Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/include/asm/ftrace.h | 19 ++++- arch/arm/kernel/entry-common.S | 37 +++++++--- arch/arm/kernel/ftrace.c | 155 ++++++++++++++++++++++++++++------------- scripts/recordmcount.pl | 2 + 4 files changed, 155 insertions(+), 58 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index 103f7ee97313..4a56a2ee067c 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h @@ -2,12 +2,29 @@ #define _ASM_ARM_FTRACE #ifdef CONFIG_FUNCTION_TRACER -#define MCOUNT_ADDR ((long)(mcount)) +#define MCOUNT_ADDR ((unsigned long)(__gnu_mcount_nc)) #define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ #ifndef __ASSEMBLY__ extern void mcount(void); extern void __gnu_mcount_nc(void); + +#ifdef CONFIG_DYNAMIC_FTRACE +struct dyn_arch_ftrace { +#ifdef CONFIG_OLD_MCOUNT + bool old_mcount; +#endif +}; + +static inline unsigned long ftrace_call_adjust(unsigned long addr) +{ + return addr; +} + +extern void ftrace_caller_old(void); +extern void ftrace_call_old(void); +#endif + #endif #endif diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index f5e75de0203e..e02790f28879 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -127,6 +127,10 @@ ENDPROC(ret_from_fork) * clobber the ip register. This is OK because the ARM calling convention * allows it to be clobbered in subroutines and doesn't use it to hold * parameters.) + * + * When using dynamic ftrace, we patch out the mcount call by a "mov r0, r0" + * for the mcount case, and a "pop {lr}" for the __gnu_mcount_nc case (see + * arch/arm/kernel/ftrace.c). */ #ifndef CONFIG_OLD_MCOUNT @@ -136,30 +140,45 @@ ENDPROC(ret_from_fork) #endif #ifdef CONFIG_DYNAMIC_FTRACE -ENTRY(mcount) +ENTRY(__gnu_mcount_nc) + mov ip, lr + ldmia sp!, {lr} + mov pc, ip +ENDPROC(__gnu_mcount_nc) + +ENTRY(ftrace_caller) stmdb sp!, {r0-r3, lr} mov r0, lr sub r0, r0, #MCOUNT_INSN_SIZE + ldr r1, [sp, #20] - .globl mcount_call -mcount_call: + .global ftrace_call +ftrace_call: bl ftrace_stub - ldr lr, [fp, #-4] @ restore lr - ldmia sp!, {r0-r3, pc} + ldmia sp!, {r0-r3, ip, lr} + mov pc, ip +ENDPROC(ftrace_caller) + +#ifdef CONFIG_OLD_MCOUNT +ENTRY(mcount) + stmdb sp!, {lr} + ldr lr, [fp, #-4] + ldmia sp!, {pc} ENDPROC(mcount) -ENTRY(ftrace_caller) +ENTRY(ftrace_caller_old) stmdb sp!, {r0-r3, lr} ldr r1, [fp, #-4] mov r0, lr sub r0, r0, #MCOUNT_INSN_SIZE - .globl ftrace_call -ftrace_call: + .globl ftrace_call_old +ftrace_call_old: bl ftrace_stub ldr lr, [fp, #-4] @ restore lr ldmia sp!, {r0-r3, pc} -ENDPROC(ftrace_caller) +ENDPROC(ftrace_caller_old) +#endif #else diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index 0298286ad4ad..f09014cfbf2c 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -2,102 +2,161 @@ * Dynamic function tracing support. * * Copyright (C) 2008 Abhishek Sagar + * Copyright (C) 2010 Rabin Vincent * * For licencing details, see COPYING. * * Defines low-level handling of mcount calls when the kernel * is compiled with the -pg flag. When using dynamic ftrace, the - * mcount call-sites get patched lazily with NOP till they are - * enabled. All code mutation routines here take effect atomically. + * mcount call-sites get patched with NOP till they are enabled. + * All code mutation routines here are called under stop_machine(). */ #include +#include #include #include -#define PC_OFFSET 8 -#define BL_OPCODE 0xeb000000 -#define BL_OFFSET_MASK 0x00ffffff +#define NOP 0xe8bd4000 /* pop {lr} */ -static unsigned long bl_insn; -static const unsigned long NOP = 0xe1a00000; /* mov r0, r0 */ +#ifdef CONFIG_OLD_MCOUNT +#define OLD_MCOUNT_ADDR ((unsigned long) mcount) +#define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old) -unsigned char *ftrace_nop_replace(void) +#define OLD_NOP 0xe1a00000 /* mov r0, r0 */ + +static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec) +{ + return rec->arch.old_mcount ? OLD_NOP : NOP; +} + +static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr) +{ + if (!rec->arch.old_mcount) + return addr; + + if (addr == MCOUNT_ADDR) + addr = OLD_MCOUNT_ADDR; + else if (addr == FTRACE_ADDR) + addr = OLD_FTRACE_ADDR; + + return addr; +} +#else +static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec) +{ + return NOP; +} + +static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr) { - return (char *)&NOP; + return addr; } +#endif /* construct a branch (BL) instruction to addr */ -unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr) +static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) { long offset; - offset = (long)addr - (long)(pc + PC_OFFSET); + offset = (long)addr - (long)(pc + 8); if (unlikely(offset < -33554432 || offset > 33554428)) { /* Can't generate branches that far (from ARM ARM). Ftrace * doesn't generate branches outside of kernel text. */ WARN_ON_ONCE(1); - return NULL; + return 0; } - offset = (offset >> 2) & BL_OFFSET_MASK; - bl_insn = BL_OPCODE | offset; - return (unsigned char *)&bl_insn; -} -int ftrace_modify_code(unsigned long pc, unsigned char *old_code, - unsigned char *new_code) -{ - unsigned long err = 0, replaced = 0, old, new; + offset = (offset >> 2) & 0x00ffffff; - old = *(unsigned long *)old_code; - new = *(unsigned long *)new_code; + return 0xeb000000 | offset; +} - __asm__ __volatile__ ( - "1: ldr %1, [%2] \n" - " cmp %1, %4 \n" - "2: streq %3, [%2] \n" - " cmpne %1, %3 \n" - " movne %0, #2 \n" - "3:\n" +static int ftrace_modify_code(unsigned long pc, unsigned long old, + unsigned long new) +{ + unsigned long replaced; - ".pushsection .fixup, \"ax\"\n" - "4: mov %0, #1 \n" - " b 3b \n" - ".popsection\n" + if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE)) + return -EFAULT; - ".pushsection __ex_table, \"a\"\n" - " .long 1b, 4b \n" - " .long 2b, 4b \n" - ".popsection\n" + if (replaced != old) + return -EINVAL; - : "=r"(err), "=r"(replaced) - : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced) - : "memory"); + if (probe_kernel_write((void *)pc, &new, MCOUNT_INSN_SIZE)) + return -EPERM; - if (!err && (replaced == old)) - flush_icache_range(pc, pc + MCOUNT_INSN_SIZE); + flush_icache_range(pc, pc + MCOUNT_INSN_SIZE); - return err; + return 0; } int ftrace_update_ftrace_func(ftrace_func_t func) { - int ret; unsigned long pc, old; - unsigned char *new; + unsigned long new; + int ret; pc = (unsigned long)&ftrace_call; memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE); new = ftrace_call_replace(pc, (unsigned long)func); - ret = ftrace_modify_code(pc, (unsigned char *)&old, new); + + ret = ftrace_modify_code(pc, old, new); + +#ifdef CONFIG_OLD_MCOUNT + if (!ret) { + pc = (unsigned long)&ftrace_call_old; + memcpy(&old, &ftrace_call_old, MCOUNT_INSN_SIZE); + new = ftrace_call_replace(pc, (unsigned long)func); + + ret = ftrace_modify_code(pc, old, new); + } +#endif + + return ret; +} + +int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) +{ + unsigned long new, old; + unsigned long ip = rec->ip; + + old = ftrace_nop_replace(rec); + new = ftrace_call_replace(ip, adjust_address(rec, addr)); + + return ftrace_modify_code(rec->ip, old, new); +} + +int ftrace_make_nop(struct module *mod, + struct dyn_ftrace *rec, unsigned long addr) +{ + unsigned long ip = rec->ip; + unsigned long old; + unsigned long new; + int ret; + + old = ftrace_call_replace(ip, adjust_address(rec, addr)); + new = ftrace_nop_replace(rec); + ret = ftrace_modify_code(ip, old, new); + +#ifdef CONFIG_OLD_MCOUNT + if (ret == -EINVAL && addr == MCOUNT_ADDR) { + rec->arch.old_mcount = true; + + old = ftrace_call_replace(ip, adjust_address(rec, addr)); + new = ftrace_nop_replace(rec); + ret = ftrace_modify_code(ip, old, new); + } +#endif + return ret; } -/* run from ftrace_init with irqs disabled */ int __init ftrace_dyn_arch_init(void *data) { - ftrace_mcount_set(data); + *(unsigned long *)data = 0; + return 0; } diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl index e67f05486087..022d4679b1b3 100755 --- a/scripts/recordmcount.pl +++ b/scripts/recordmcount.pl @@ -270,6 +270,8 @@ if ($arch eq "x86_64") { } elsif ($arch eq "arm") { $alignment = 2; $section_type = '%progbits'; + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_ARM_(CALL|PC24)" . + "\\s+(__gnu_mcount_nc|mcount)\$"; } elsif ($arch eq "ia64") { $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s_mcount\$"; -- cgit v1.2.3 From 72dc43a9eb123d2742bd413c80dbeab0c588f622 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Tue, 10 Aug 2010 19:52:35 +0100 Subject: ARM: 6319/1: ftrace: add Thumb-2 support to dynamic ftrace Handle the different nop and call instructions for Thumb-2. Also, we need to adjust the recorded mcount_loc addresses because they have the lsb set. Cc: Catalin Marinas Acked-by: Steven Rostedt [recordmcount.pl change] Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/include/asm/ftrace.h | 3 ++- arch/arm/kernel/ftrace.c | 33 +++++++++++++++++++++++++++++++++ scripts/recordmcount.pl | 2 +- 3 files changed, 36 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index 4a56a2ee067c..f89515adac60 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h @@ -18,7 +18,8 @@ struct dyn_arch_ftrace { static inline unsigned long ftrace_call_adjust(unsigned long addr) { - return addr; + /* With Thumb-2, the recorded addresses have the lsb set */ + return addr & ~1; } extern void ftrace_caller_old(void); diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index f09014cfbf2c..971ac8c36ea7 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -18,7 +18,11 @@ #include #include +#ifdef CONFIG_THUMB2_KERNEL +#define NOP 0xeb04f85d /* pop.w {lr} */ +#else #define NOP 0xe8bd4000 /* pop {lr} */ +#endif #ifdef CONFIG_OLD_MCOUNT #define OLD_MCOUNT_ADDR ((unsigned long) mcount) @@ -56,6 +60,34 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr) #endif /* construct a branch (BL) instruction to addr */ +#ifdef CONFIG_THUMB2_KERNEL +static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) +{ + unsigned long s, j1, j2, i1, i2, imm10, imm11; + unsigned long first, second; + long offset; + + offset = (long)addr - (long)(pc + 4); + if (offset < -16777216 || offset > 16777214) { + WARN_ON_ONCE(1); + return 0; + } + + s = (offset >> 24) & 0x1; + i1 = (offset >> 23) & 0x1; + i2 = (offset >> 22) & 0x1; + imm10 = (offset >> 12) & 0x3ff; + imm11 = (offset >> 1) & 0x7ff; + + j1 = (!i1) ^ s; + j2 = (!i2) ^ s; + + first = 0xf000 | (s << 10) | imm10; + second = 0xd000 | (j1 << 13) | (j2 << 11) | imm11; + + return (second << 16) | first; +} +#else static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) { long offset; @@ -73,6 +105,7 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr) return 0xeb000000 | offset; } +#endif static int ftrace_modify_code(unsigned long pc, unsigned long old, unsigned long new) diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl index 022d4679b1b3..1d7963f4ee79 100755 --- a/scripts/recordmcount.pl +++ b/scripts/recordmcount.pl @@ -270,7 +270,7 @@ if ($arch eq "x86_64") { } elsif ($arch eq "arm") { $alignment = 2; $section_type = '%progbits'; - $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_ARM_(CALL|PC24)" . + $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_ARM_(CALL|PC24|THM_CALL)" . "\\s+(__gnu_mcount_nc|mcount)\$"; } elsif ($arch eq "ia64") { -- cgit v1.2.3 From 80be7a7f642719bf99fc49692fc77d6333f51a73 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Tue, 10 Aug 2010 19:58:17 +0100 Subject: ARM: 6320/1: ftrace: enable dynamic ftrace Dynamic ftrace for ARM has been disabled since 07c4cc1cdaa08f ("ftrace: disable dynamic ftrace for all archs that use daemon"). Now that the code has been updated, re-enable it. Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 92951103255a..8d09765ce564 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -19,6 +19,8 @@ config ARM select HAVE_KPROBES if (!XIP_KERNEL) select HAVE_KRETPROBES if (HAVE_KPROBES) select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) + select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) + select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) select HAVE_GENERIC_DMA_COHERENT select HAVE_KERNEL_GZIP select HAVE_KERNEL_LZO -- cgit v1.2.3 From 5793432628ad76f93ae4d31c23fb1c26e3d8b525 Mon Sep 17 00:00:00 2001 From: Phil Carmody Date: Thu, 19 Aug 2010 15:10:24 +0100 Subject: ARM: 6338/1: module - simplify code with temporaries Less to read. Signed-off-by: Phil Carmody Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/module.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 6b4605893f1e..1dae0468677a 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -71,17 +71,19 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; for (s = sechdrs; s < sechdrs_end; s++) { - if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0) + char const *secname = secstrings + s->sh_name; + + if (strcmp(".ARM.exidx.init.text", secname) == 0) mod->arch.unw_sec_init = s; - else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0) + else if (strcmp(".ARM.exidx.devinit.text", secname) == 0) mod->arch.unw_sec_devinit = s; - else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0) + else if (strcmp(".ARM.exidx", secname) == 0) mod->arch.unw_sec_core = s; - else if (strcmp(".init.text", secstrings + s->sh_name) == 0) + else if (strcmp(".init.text", secname) == 0) mod->arch.sec_init_text = s; - else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0) + else if (strcmp(".devinit.text", secname) == 0) mod->arch.sec_devinit_text = s; - else if (strcmp(".text", secstrings + s->sh_name) == 0) + else if (strcmp(".text", secname) == 0) mod->arch.sec_core_text = s; } #endif -- cgit v1.2.3 From e5f7772eec3ec342ecfe686ab8330ef538af134b Mon Sep 17 00:00:00 2001 From: Phil Carmody Date: Thu, 19 Aug 2010 15:16:37 +0100 Subject: ARM: 6339/1: module - simplify unwind table handling The various sections are all dealt with similarly, so factor out that common behaviour. (Incorporating Peter Huewe's fix.) Cc: Peter Huewe Signed-off-by: Phil Carmody Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/module.h | 29 ++++++++++++++++----------- arch/arm/kernel/module.c | 46 ++++++++++++++++++------------------------- 2 files changed, 36 insertions(+), 39 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index e4dfa69abb68..6dcff0f7f8d7 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -7,20 +7,25 @@ struct unwind_table; -struct mod_arch_specific -{ #ifdef CONFIG_ARM_UNWIND - Elf_Shdr *unw_sec_init; - Elf_Shdr *unw_sec_devinit; - Elf_Shdr *unw_sec_core; - Elf_Shdr *sec_init_text; - Elf_Shdr *sec_devinit_text; - Elf_Shdr *sec_core_text; - struct unwind_table *unwind_init; - struct unwind_table *unwind_devinit; - struct unwind_table *unwind_core; -#endif +struct arm_unwind_mapping { + Elf_Shdr *unw_sec; + Elf_Shdr *sec_text; + struct unwind_table *unwind; +}; +enum { + ARM_SEC_INIT, + ARM_SEC_DEVINIT, + ARM_SEC_CORE, + ARM_SEC_MAX, +}; +struct mod_arch_specific { + struct arm_unwind_mapping map[ARM_SEC_MAX]; }; +#else +struct mod_arch_specific { +}; +#endif /* * Include the ARM architecture version. diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 1dae0468677a..0aa622e84b24 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -69,22 +69,23 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, { #ifdef CONFIG_ARM_UNWIND Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; + struct arm_unwind_mapping *maps = mod->arch.map; for (s = sechdrs; s < sechdrs_end; s++) { char const *secname = secstrings + s->sh_name; if (strcmp(".ARM.exidx.init.text", secname) == 0) - mod->arch.unw_sec_init = s; + maps[ARM_SEC_INIT].unw_sec = s; else if (strcmp(".ARM.exidx.devinit.text", secname) == 0) - mod->arch.unw_sec_devinit = s; + maps[ARM_SEC_DEVINIT].unw_sec = s; else if (strcmp(".ARM.exidx", secname) == 0) - mod->arch.unw_sec_core = s; + maps[ARM_SEC_CORE].unw_sec = s; else if (strcmp(".init.text", secname) == 0) - mod->arch.sec_init_text = s; + maps[ARM_SEC_INIT].sec_text = s; else if (strcmp(".devinit.text", secname) == 0) - mod->arch.sec_devinit_text = s; + maps[ARM_SEC_DEVINIT].sec_text = s; else if (strcmp(".text", secname) == 0) - mod->arch.sec_core_text = s; + maps[ARM_SEC_CORE].sec_text = s; } #endif return 0; @@ -294,31 +295,22 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab, #ifdef CONFIG_ARM_UNWIND static void register_unwind_tables(struct module *mod) { - if (mod->arch.unw_sec_init && mod->arch.sec_init_text) - mod->arch.unwind_init = - unwind_table_add(mod->arch.unw_sec_init->sh_addr, - mod->arch.unw_sec_init->sh_size, - mod->arch.sec_init_text->sh_addr, - mod->arch.sec_init_text->sh_size); - if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text) - mod->arch.unwind_devinit = - unwind_table_add(mod->arch.unw_sec_devinit->sh_addr, - mod->arch.unw_sec_devinit->sh_size, - mod->arch.sec_devinit_text->sh_addr, - mod->arch.sec_devinit_text->sh_size); - if (mod->arch.unw_sec_core && mod->arch.sec_core_text) - mod->arch.unwind_core = - unwind_table_add(mod->arch.unw_sec_core->sh_addr, - mod->arch.unw_sec_core->sh_size, - mod->arch.sec_core_text->sh_addr, - mod->arch.sec_core_text->sh_size); + int i; + for (i = 0; i < ARM_SEC_MAX; ++i) { + struct arm_unwind_mapping *map = &mod->arch.map[i]; + if (map->unw_sec && map->sec_text) + map->unwind = unwind_table_add(map->unw_sec->sh_addr, + map->unw_sec->sh_size, + map->sec_text->sh_addr, + map->sec_text->sh_size); + } } static void unregister_unwind_tables(struct module *mod) { - unwind_table_del(mod->arch.unwind_init); - unwind_table_del(mod->arch.unwind_devinit); - unwind_table_del(mod->arch.unwind_core); + int i = ARM_SEC_MAX; + while (--i >= 0) + unwind_table_del(mod->arch.map[i].unwind); } #else static inline void register_unwind_tables(struct module *mod) { } -- cgit v1.2.3 From 09e56a2d076c2afb2a1932ae4283e10ef2d26ef3 Mon Sep 17 00:00:00 2001 From: Phil Carmody Date: Thu, 19 Aug 2010 15:19:04 +0100 Subject: ARM: 6340/1: module - additional unwind tables for exit/devexit sections Without these, exit functions cannot be stack-traced, so to speak. This implies that module unloads that perform allocations (don't laugh) will cause noisy warnings on the console when kmemleak is enabled, as it presumes that all code's call chains are traceable. Similarly, BUGs and WARN_ONs will give additional console spam. Signed-off-by: Phil Carmody Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/module.h | 2 ++ arch/arm/kernel/module.c | 8 ++++++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 6dcff0f7f8d7..cbb0bc295d2b 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h @@ -17,6 +17,8 @@ enum { ARM_SEC_INIT, ARM_SEC_DEVINIT, ARM_SEC_CORE, + ARM_SEC_EXIT, + ARM_SEC_DEVEXIT, ARM_SEC_MAX, }; struct mod_arch_specific { diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 0aa622e84b24..d9bd786ce23d 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -80,12 +80,20 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, maps[ARM_SEC_DEVINIT].unw_sec = s; else if (strcmp(".ARM.exidx", secname) == 0) maps[ARM_SEC_CORE].unw_sec = s; + else if (strcmp(".ARM.exidx.exit.text", secname) == 0) + maps[ARM_SEC_EXIT].unw_sec = s; + else if (strcmp(".ARM.exidx.devexit.text", secname) == 0) + maps[ARM_SEC_DEVEXIT].unw_sec = s; else if (strcmp(".init.text", secname) == 0) maps[ARM_SEC_INIT].sec_text = s; else if (strcmp(".devinit.text", secname) == 0) maps[ARM_SEC_DEVINIT].sec_text = s; else if (strcmp(".text", secname) == 0) maps[ARM_SEC_CORE].sec_text = s; + else if (strcmp(".exit.text", secname) == 0) + maps[ARM_SEC_EXIT].sec_text = s; + else if (strcmp(".devexit.text", secname) == 0) + maps[ARM_SEC_DEVEXIT].sec_text = s; } #endif return 0; -- cgit v1.2.3 From 5333a3de3cdd739ec4f6d501f5f6d09bab7ff919 Mon Sep 17 00:00:00 2001 From: Phil Carmody Date: Thu, 19 Aug 2010 15:20:37 +0100 Subject: ARM: 6341/1: unwind - optimise linked-list searches for modules With several sections per module, and dozens of modules, the searches down the linked list of sections would dominate the lookup time, dwarfing any savings from the binary search within the section. A simple move-to-front optimisation exploits the commonality of the code paths taken, and in simple real-world tests reduces the number of steps in the search to barely more than 1. Signed-off-by: Phil Carmody Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/kernel/unwind.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index dd81a918c106..2a161765f6d5 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -146,6 +146,8 @@ static struct unwind_idx *unwind_find_idx(unsigned long addr) addr < table->end_addr) { idx = search_index(addr, table->start, table->stop - 1); + /* Move-to-front to exploit common traces */ + list_move(&table->list, &unwind_tables); break; } } -- cgit v1.2.3 From f946738ca882c365a963043de471f45e91ab0a95 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 19 Aug 2010 10:27:49 +0100 Subject: ARM: 6331/1: ux500 cpu/SoC version macros v2 This patch adds support for checking if the digital baseband (DB) System-on-Chip (aka "cpu) ASIC hardware version is 1.0, 1.1 or 2.0. We print the result in the bootlog, the functions are then used for runtime decisions based on hardware version. Signed-off-by: Mattias Wallin Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/cpu-db8500.c | 82 ++++++++++++++++++++++++++ arch/arm/mach-ux500/include/mach/db8500-regs.h | 2 - arch/arm/mach-ux500/include/mach/hardware.h | 23 +++++++- arch/arm/mach-ux500/include/mach/setup.h | 7 +++ 4 files changed, 110 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index f21c444edd99..4acab7544b3c 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -38,10 +38,12 @@ static struct platform_device *platform_devs[] __initdata = { /* minimum static i/o mapping required to boot U8500 platforms */ static struct map_desc u8500_io_desc[] __initdata = { __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), + __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), + __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M), }; static struct map_desc u8500ed_io_desc[] __initdata = { @@ -53,6 +55,69 @@ static struct map_desc u8500v1_io_desc[] __initdata = { __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), }; +/* + * Functions to differentiate between later ASICs + * We look into the end of the ROM to locate the hardcoded ASIC ID. + * This is only needed to differentiate between minor revisions and + * process variants of an ASIC, the major revisions are encoded in + * the cpuid. + */ +#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4) +#define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4) +#define U8500_ASIC_REV_ED 0x01 +#define U8500_ASIC_REV_V10 0xA0 +#define U8500_ASIC_REV_V11 0xA1 +#define U8500_ASIC_REV_V20 0xB0 + +/** + * struct db8500_asic_id - fields of the ASIC ID + * @process: the manufacturing process, 0x40 is 40 nm + * 0x00 is "standard" + * @partnumber: hithereto 0x8500 for DB8500 + * @revision: version code in the series + * This field definion is not formally defined but makes + * sense. + */ +struct db8500_asic_id { + u8 process; + u16 partnumber; + u8 revision; +}; + +/* This isn't going to change at runtime */ +static struct db8500_asic_id db8500_id; + +static void __init get_db8500_asic_id(void) +{ + u32 asicid; + + if (cpu_is_u8500v1() || cpu_is_u8500ed()) + asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1)); + else if (cpu_is_u8500v2()) + asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2)); + else + BUG(); + + db8500_id.process = (asicid >> 24); + db8500_id.partnumber = (asicid >> 16) & 0xFFFFU; + db8500_id.revision = asicid & 0xFFU; +} + +bool cpu_is_u8500v10(void) +{ + return (db8500_id.revision == U8500_ASIC_REV_V10); +} + +bool cpu_is_u8500v11(void) +{ + return (db8500_id.revision == U8500_ASIC_REV_V11); +} + +bool cpu_is_u8500v20(void) +{ + return (db8500_id.revision == U8500_ASIC_REV_V20); +} + void __init u8500_map_io(void) { ux500_map_io(); @@ -63,6 +128,9 @@ void __init u8500_map_io(void) iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc)); else iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc)); + + /* Read out the ASIC ID as early as we can */ + get_db8500_asic_id(); } /* @@ -70,6 +138,20 @@ void __init u8500_map_io(void) */ void __init u8500_init_devices(void) { + /* Display some ASIC boilerplate */ + pr_info("DB8500: process: %02x, revision ID: 0x%02x\n", + db8500_id.process, db8500_id.revision); + if (cpu_is_u8500ed()) + pr_info("DB8500: Early Drop (ED)\n"); + else if (cpu_is_u8500v10()) + pr_info("DB8500: version 1.0\n"); + else if (cpu_is_u8500v11()) + pr_info("DB8500: version 1.1\n"); + else if (cpu_is_u8500v20()) + pr_info("DB8500: version 2.0\n"); + else + pr_warning("ASIC: UNKNOWN SILICON VERSION!\n"); + ux500_init_devices(); if (cpu_is_u8500ed()) diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h index f000218210c9..f07d0986409d 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h @@ -30,8 +30,6 @@ #define U8500_ICN_BASE 0x81000000 #define U8500_BOOT_ROM_BASE 0x90000000 -/* ASIC ID is at 0xff4 offset within this region */ -#define U8500_ASIC_ID_BASE 0x9001F000 #define U8500_PER6_BASE 0xa03c0000 #define U8500_PER5_BASE 0xa03e0000 diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index 8656379a8309..32e883a8f2a2 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -104,16 +104,35 @@ static inline bool cpu_is_u8500(void) #endif } +#define CPUID_DB8500ED 0x410fc090 +#define CPUID_DB8500V1 0x411fc091 +#define CPUID_DB8500V2 0x412fc091 + static inline bool cpu_is_u8500ed(void) { - return cpu_is_u8500() && (read_cpuid_id() & 15) == 0; + return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED); } static inline bool cpu_is_u8500v1(void) { - return cpu_is_u8500() && (read_cpuid_id() & 15) == 1; + return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1); +} + +static inline bool cpu_is_u8500v2(void) +{ + return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2); } +#ifdef CONFIG_UX500_SOC_DB8500 +bool cpu_is_u8500v10(void); +bool cpu_is_u8500v11(void); +bool cpu_is_u8500v20(void); +#else +static inline bool cpu_is_u8500v10(void) { return false; } +static inline bool cpu_is_u8500v11(void) { return false; } +static inline bool cpu_is_u8500v20(void) { return false; } +#endif + static inline bool cpu_is_u5500(void) { #ifdef CONFIG_UX500_SOC_DB5500 diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h index e978dbd9e210..54bbe648bf58 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/include/mach/setup.h @@ -38,4 +38,11 @@ extern struct sys_timer ux500_timer; .type = MT_DEVICE, \ } +#define __MEM_DEV_DESC(x, sz) { \ + .virtual = IO_ADDRESS(x), \ + .pfn = __phys_to_pfn(x), \ + .length = sz, \ + .type = MT_MEMORY, \ +} + #endif /* __ASM_ARCH_SETUP_H */ -- cgit v1.2.3 From 1c833abc1f8c056f562ccf4d57a69514d338cc35 Mon Sep 17 00:00:00 2001 From: Hanumath Prasad Date: Thu, 19 Aug 2010 12:06:10 +0100 Subject: ARM: 6334/1: ux500: add DB8500 SD/MMC platform devices Acked-by: Linus Walleij Signed-off-by: Hanumath Prasad Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/mach-ux500/devices-db8500.c | 76 ++++++++++++++++++++++++++++++ arch/arm/mach-ux500/include/mach/devices.h | 7 +++ 2 files changed, 83 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 9280d2561111..f2e01a6dafe7 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -110,6 +110,82 @@ struct platform_device u8500_i2c4_device = { .num_resources = ARRAY_SIZE(u8500_i2c4_resources), }; +/* + * SD/MMC + */ + +struct amba_device u8500_sdi0_device = { + .dev = { + .init_name = "sdi0", + }, + .res = { + .start = U8500_SDI0_BASE, + .end = U8500_SDI0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_DB8500_SDMMC0, NO_IRQ}, +}; + +struct amba_device u8500_sdi1_device = { + .dev = { + .init_name = "sdi1", + }, + .res = { + .start = U8500_SDI1_BASE, + .end = U8500_SDI1_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_DB8500_SDMMC1, NO_IRQ}, +}; + +struct amba_device u8500_sdi2_device = { + .dev = { + .init_name = "sdi2", + }, + .res = { + .start = U8500_SDI2_BASE, + .end = U8500_SDI2_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_DB8500_SDMMC2, NO_IRQ}, +}; + +struct amba_device u8500_sdi3_device = { + .dev = { + .init_name = "sdi3", + }, + .res = { + .start = U8500_SDI3_BASE, + .end = U8500_SDI3_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_DB8500_SDMMC3, NO_IRQ}, +}; + +struct amba_device u8500_sdi4_device = { + .dev = { + .init_name = "sdi4", + }, + .res = { + .start = U8500_SDI4_BASE, + .end = U8500_SDI4_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_DB8500_SDMMC4, NO_IRQ}, +}; + +struct amba_device u8500_sdi5_device = { + .dev = { + .init_name = "sdi5", + }, + .res = { + .start = U8500_SDI5_BASE, + .end = U8500_SDI5_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_DB8500_SDMMC5, NO_IRQ}, +}; + static struct resource dma40_resources[] = { [0] = { .start = U8500_DMA_BASE, diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index c2b2f2574947..33a120c2e82e 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -27,6 +27,13 @@ extern struct platform_device u8500_i2c0_device; extern struct platform_device u8500_i2c4_device; extern struct platform_device u8500_dma40_device; +extern struct amba_device u8500_sdi0_device; +extern struct amba_device u8500_sdi1_device; +extern struct amba_device u8500_sdi2_device; +extern struct amba_device u8500_sdi3_device; +extern struct amba_device u8500_sdi4_device; +extern struct amba_device u8500_sdi5_device; + void dma40_u8500ed_fixup(void); #endif -- cgit v1.2.3 From 008f8a2f7ff4d63559b7ba7a6f7073efef9b1e08 Mon Sep 17 00:00:00 2001 From: Hanumath Prasad Date: Thu, 19 Aug 2010 12:06:32 +0100 Subject: ARM: 6335/1: ux500: mop500: register eMMC devices Acked-by: Linus Walleij Signed-off-by: Hanumath Prasad Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/mach-ux500/Makefile | 2 +- arch/arm/mach-ux500/board-mop500-sdi.c | 91 ++++++++++++++++++++++++++++++++++ arch/arm/mach-ux500/board-mop500.c | 3 ++ arch/arm/mach-ux500/board-mop500.h | 12 +++++ arch/arm/mach-ux500/pins-db8500.h | 66 ++++++++++++------------ 5 files changed, 140 insertions(+), 34 deletions(-) create mode 100644 arch/arm/mach-ux500/board-mop500-sdi.c create mode 100644 arch/arm/mach-ux500/board-mop500.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 4556aea9c3c5..33903af98b24 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -5,7 +5,7 @@ obj-y := clock.o cpu.o devices.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o -obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o +obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o obj-$(CONFIG_MACH_U5500) += board-u5500.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c new file mode 100644 index 000000000000..bac995665b58 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Hanumath Prasad + * License terms: GNU General Public License (GPL) version 2 + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "pins-db8500.h" +#include "board-mop500.h" + +static pin_cfg_t mop500_sdi_pins[] = { + /* SDI4 (on-board eMMC) */ + GPIO197_MC4_DAT3, + GPIO198_MC4_DAT2, + GPIO199_MC4_DAT1, + GPIO200_MC4_DAT0, + GPIO201_MC4_CMD, + GPIO202_MC4_FBCLK, + GPIO203_MC4_CLK, + GPIO204_MC4_DAT7, + GPIO205_MC4_DAT6, + GPIO206_MC4_DAT5, + GPIO207_MC4_DAT4, +}; + +static pin_cfg_t mop500_sdi2_pins[] = { + /* SDI2 (POP eMMC) */ + GPIO128_MC2_CLK, + GPIO129_MC2_CMD, + GPIO130_MC2_FBCLK, + GPIO131_MC2_DAT0, + GPIO132_MC2_DAT1, + GPIO133_MC2_DAT2, + GPIO134_MC2_DAT3, + GPIO135_MC2_DAT4, + GPIO136_MC2_DAT5, + GPIO137_MC2_DAT6, + GPIO138_MC2_DAT7, +}; + +/* + * SDI 2 (POP eMMC, not on DB8500ed) + */ + +static struct mmci_platform_data mop500_sdi2_data = { + .ocr_mask = MMC_VDD_165_195, + .f_max = 100000000, + .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .gpio_cd = -1, + .gpio_wp = -1, +}; + +/* + * SDI 4 (on-board eMMC) + */ + +static struct mmci_platform_data mop500_sdi4_data = { + .ocr_mask = MMC_VDD_29_30, + .f_max = 100000000, + .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED, + .gpio_cd = -1, + .gpio_wp = -1, +}; + +void mop500_sdi_init(void) +{ + nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins)); + + u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data; + u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data; + + if (!cpu_is_u8500ed()) { + nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins)); + amba_device_register(&u8500_sdi2_device, &iomem_resource); + } + + /* On-board eMMC */ + amba_device_register(&u8500_sdi4_device, &iomem_resource); +} diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 0e8fd135a57d..de310326df1c 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -30,6 +30,7 @@ #include #include "pins-db8500.h" +#include "board-mop500.h" static pin_cfg_t mop500_pins[] = { /* SSP0 */ @@ -163,6 +164,8 @@ static void __init u8500_init_machine(void) platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); + mop500_sdi_init(); + spi_register_board_info(u8500_spi_devices, ARRAY_SIZE(u8500_spi_devices)); } diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h new file mode 100644 index 000000000000..2d240322fa6f --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __BOARD_MOP500_H +#define __BOARD_MOP500_H + +extern void mop500_sdi_init(void); + +#endif diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h index 9055d5d3233c..66f8761cc823 100644 --- a/arch/arm/mach-ux500/pins-db8500.h +++ b/arch/arm/mach-ux500/pins-db8500.h @@ -96,57 +96,57 @@ #define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) #define GPIO18_GPIO PIN_CFG(18, GPIO) -#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_MC0_CMDDIR PIN_CFG_PULL(18, ALT_A, UP) #define GPIO18_U2_RXD PIN_CFG(18, ALT_B) #define GPIO18_MS_IEP PIN_CFG(18, ALT_C) #define GPIO19_GPIO PIN_CFG(19, GPIO) -#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_MC0_DAT0DIR PIN_CFG_PULL(19, ALT_A, UP) #define GPIO19_U2_TXD PIN_CFG(19, ALT_B) #define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) #define GPIO20_GPIO PIN_CFG(20, GPIO) -#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_MC0_DAT2DIR PIN_CFG_PULL(20, ALT_A, UP) #define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) #define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) #define GPIO21_GPIO PIN_CFG(21, GPIO) -#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MC0_DAT31DIR PIN_CFG_PULL(21, ALT_A, UP) #define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) #define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) #define GPIO22_GPIO PIN_CFG(22, GPIO) -#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_MC0_FBCLK PIN_CFG_PULL(22, ALT_A, UP) #define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) #define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) #define GPIO23_GPIO PIN_CFG(23, GPIO) -#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_MC0_CLK PIN_CFG_PULL(23, ALT_A, UP) #define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) #define GPIO23_MS_CLK PIN_CFG(23, ALT_C) #define GPIO24_GPIO PIN_CFG(24, GPIO) -#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_MC0_CMD PIN_CFG_PULL(24, ALT_A, UP) #define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) #define GPIO24_MS_BS PIN_CFG(24, ALT_C) #define GPIO25_GPIO PIN_CFG(25, GPIO) -#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_MC0_DAT0 PIN_CFG_PULL(25, ALT_A, UP) #define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) #define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) #define GPIO26_GPIO PIN_CFG(26, GPIO) -#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_MC0_DAT1 PIN_CFG_PULL(26, ALT_A, UP) #define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) #define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) #define GPIO27_GPIO PIN_CFG(27, GPIO) -#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_MC0_DAT2 PIN_CFG_PULL(27, ALT_A, UP) #define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) #define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) #define GPIO28_GPIO PIN_CFG(28, GPIO) -#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_MC0_DAT3 PIN_CFG_PULL(28, ALT_A, UP) #define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) #define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) @@ -357,48 +357,48 @@ #define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) #define GPIO128_GPIO PIN_CFG(128, GPIO) -#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_MC2_CLK PIN_CFG_PULL(128, ALT_A, UP) #define GPIO128_SM_CKO PIN_CFG(128, ALT_B) #define GPIO129_GPIO PIN_CFG(129, GPIO) -#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_MC2_CMD PIN_CFG_PULL(129, ALT_A, UP) #define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) #define GPIO130_GPIO PIN_CFG(130, GPIO) -#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_MC2_FBCLK PIN_CFG_PULL(130, ALT_A, UP) #define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) #define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) #define GPIO131_GPIO PIN_CFG(131, GPIO) -#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_MC2_DAT0 PIN_CFG_PULL(131, ALT_A, UP) #define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) #define GPIO132_GPIO PIN_CFG(132, GPIO) -#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_MC2_DAT1 PIN_CFG_PULL(132, ALT_A, UP) #define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) #define GPIO133_GPIO PIN_CFG(133, GPIO) -#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_MC2_DAT2 PIN_CFG_PULL(133, ALT_A, UP) #define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) #define GPIO134_GPIO PIN_CFG(134, GPIO) -#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_MC2_DAT3 PIN_CFG_PULL(134, ALT_A, UP) #define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) #define GPIO135_GPIO PIN_CFG(135, GPIO) -#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_MC2_DAT4 PIN_CFG_PULL(135, ALT_A, UP) #define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) #define GPIO136_GPIO PIN_CFG(136, GPIO) -#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_MC2_DAT5 PIN_CFG_PULL(136, ALT_A, UP) #define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) #define GPIO137_GPIO PIN_CFG(137, GPIO) -#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_MC2_DAT6 PIN_CFG_PULL(137, ALT_A, UP) #define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) #define GPIO138_GPIO PIN_CFG(138, GPIO) -#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_MC2_DAT7 PIN_CFG_PULL(138, ALT_A, UP) #define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) #define GPIO139_GPIO PIN_CFG(139, GPIO) @@ -569,39 +569,39 @@ #define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) #define GPIO197_GPIO PIN_CFG(197, GPIO) -#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) +#define GPIO197_MC4_DAT3 PIN_CFG_PULL(197, ALT_A, UP) #define GPIO198_GPIO PIN_CFG(198, GPIO) -#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) +#define GPIO198_MC4_DAT2 PIN_CFG_PULL(198, ALT_A, UP) #define GPIO199_GPIO PIN_CFG(199, GPIO) -#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) +#define GPIO199_MC4_DAT1 PIN_CFG_PULL(199, ALT_A, UP) #define GPIO200_GPIO PIN_CFG(200, GPIO) -#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) +#define GPIO200_MC4_DAT0 PIN_CFG_PULL(200, ALT_A, UP) #define GPIO201_GPIO PIN_CFG(201, GPIO) -#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) +#define GPIO201_MC4_CMD PIN_CFG_PULL(201, ALT_A, UP) #define GPIO202_GPIO PIN_CFG(202, GPIO) -#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_MC4_FBCLK PIN_CFG_PULL(202, ALT_A, UP) #define GPIO202_PWL PIN_CFG(202, ALT_B) #define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) #define GPIO203_GPIO PIN_CFG(203, GPIO) -#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) +#define GPIO203_MC4_CLK PIN_CFG_PULL(203, ALT_A, UP) #define GPIO204_GPIO PIN_CFG(204, GPIO) -#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) +#define GPIO204_MC4_DAT7 PIN_CFG_PULL(204, ALT_A, UP) #define GPIO205_GPIO PIN_CFG(205, GPIO) -#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) +#define GPIO205_MC4_DAT6 PIN_CFG_PULL(205, ALT_A, UP) #define GPIO206_GPIO PIN_CFG(206, GPIO) -#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) +#define GPIO206_MC4_DAT5 PIN_CFG_PULL(206, ALT_A, UP) #define GPIO207_GPIO PIN_CFG(207, GPIO) -#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) +#define GPIO207_MC4_DAT4 PIN_CFG_PULL(207, ALT_A, UP) #define GPIO208_GPIO PIN_CFG(208, GPIO) #define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) -- cgit v1.2.3 From e3726fcf263adf764a4f1b9428082837662a41c4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 19 Aug 2010 12:36:01 +0100 Subject: ARM: 6336/1: U8500 PRCMU driver Add an initial driver for communicating with the Power, Reset and Clock Management Unit (PRCMU) firmware in U8500. This initial version supports AB8500 communication only. Signed-off-by: Mattias Nilsson Signed-off-by: Mattias Wallin Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/Makefile | 2 +- arch/arm/mach-ux500/include/mach/irqs.h | 1 + arch/arm/mach-ux500/include/mach/prcmu-regs.h | 91 ++++++++++ arch/arm/mach-ux500/include/mach/prcmu.h | 15 ++ arch/arm/mach-ux500/prcmu.c | 231 ++++++++++++++++++++++++++ 5 files changed, 339 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-ux500/include/mach/prcmu-regs.h create mode 100644 arch/arm/mach-ux500/include/mach/prcmu.h create mode 100644 arch/arm/mach-ux500/prcmu.c (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 33903af98b24..009731864399 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -4,7 +4,7 @@ obj-y := clock.o cpu.o devices.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o -obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o +obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o obj-$(CONFIG_MACH_U5500) += board-u5500.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 10385bdc2b77..0e7a2cec1994 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -41,6 +41,7 @@ #define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) #define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) #define IRQ_AB4500 (IRQ_SHPI_START + 40) +#define IRQ_PRCMU (IRQ_SHPI_START + 47) #define IRQ_DISP (IRQ_SHPI_START + 48) #define IRQ_SiPI3 (IRQ_SHPI_START + 49) #define IRQ_I2C4 (IRQ_SHPI_START + 51) diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h new file mode 100644 index 000000000000..8885f39a6421 --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2009 ST-Ericsson SA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ +#ifndef __MACH_PRCMU_REGS_H +#define __MACH_PRCMU_REGS_H + +#include + +#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE) + +#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) +#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) +#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) +#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0) +#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4) +#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0) +#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c) +#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308) + +/* ARM WFI Standby signal register */ +#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) +#define PRCMU_IOCR (_PRCMU_BASE + 0x310) + +/* CPU mailbox registers */ +#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc) +#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100) +#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104) + +/* Dual A9 core interrupt management unit registers */ +#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328) +#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c) +#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c) +#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120) +#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124) +#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128) +#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C) +#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260) +#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264) +#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268) +#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C) + +#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334) +#define ARM_WAKEUP_MODEM 0x1 + +#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C) +#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494) +#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174) + +#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148) +#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150) +#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158) +#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160) +#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168) +#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484) +#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488) +#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018) + +/* System reset register */ +#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) + +/* Level shifter and clamp control registers */ +#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) +#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) + +/* PRCMU clock/PLL/reset registers */ +#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) +#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) +#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044) +#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064) +#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058) +#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c) +#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) +#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) +#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) +#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) + +/* ePOD and memory power signal control registers */ +#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) +#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304) + +/* Debug power control unit registers */ +#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254) + +/* Miscellaneous unit registers */ +#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) + +#endif /* __MACH_PRCMU__REGS_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h new file mode 100644 index 000000000000..549843ff6dbe --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/prcmu.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * PRCMU f/w APIs + */ +#ifndef __MACH_PRCMU_H +#define __MACH_PRCMU_H + +int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); +int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); + +#endif /* __MACH_PRCMU_H */ diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c new file mode 100644 index 000000000000..293274d1342a --- /dev/null +++ b/arch/arm/mach-ux500/prcmu.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) ST Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * Author: Mattias Nilsson + * + * U8500 PRCMU driver. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE) + +#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44) +#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4) + +#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5) +#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1) +#define REQ_MB5_I2C_REG (REQ_MB5 + 2) +#define REQ_MB5_I2C_VAL (REQ_MB5 + 3) + +#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1) +#define ACK_MB5_I2C_VAL (ACK_MB5 + 3) + +#define I2C_WRITE(slave) ((slave) << 1) +#define I2C_READ(slave) (((slave) << 1) | BIT(0)) +#define I2C_STOP_EN BIT(3) + +enum ack_mb5_status { + I2C_WR_OK = 0x01, + I2C_RD_OK = 0x02, +}; + +#define MBOX_BIT BIT +#define NUM_MBOX 8 + +static struct { + struct mutex lock; + struct completion work; + bool failed; + struct { + u8 status; + u8 value; + } ack; +} mb5_transfer; + +/** + * prcmu_abb_read() - Read register value(s) from the ABB. + * @slave: The I2C slave address. + * @reg: The (start) register address. + * @value: The read out value(s). + * @size: The number of registers to read. + * + * Reads register value(s) from the ABB. + * @size has to be 1 for the current firmware version. + */ +int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) +{ + int r; + + if (size != 1) + return -EINVAL; + + r = mutex_lock_interruptible(&mb5_transfer.lock); + if (r) + return r; + + while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) + cpu_relax(); + + writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP); + writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS); + writeb(reg, REQ_MB5_I2C_REG); + + writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); + if (!wait_for_completion_timeout(&mb5_transfer.work, + msecs_to_jiffies(500))) { + pr_err("prcmu: prcmu_abb_read timed out.\n"); + r = -EIO; + goto unlock_and_return; + } + r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO); + if (!r) + *value = mb5_transfer.ack.value; + +unlock_and_return: + mutex_unlock(&mb5_transfer.lock); + return r; +} +EXPORT_SYMBOL(prcmu_abb_read); + +/** + * prcmu_abb_write() - Write register value(s) to the ABB. + * @slave: The I2C slave address. + * @reg: The (start) register address. + * @value: The value(s) to write. + * @size: The number of registers to write. + * + * Reads register value(s) from the ABB. + * @size has to be 1 for the current firmware version. + */ +int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) +{ + int r; + + if (size != 1) + return -EINVAL; + + r = mutex_lock_interruptible(&mb5_transfer.lock); + if (r) + return r; + + + while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5)) + cpu_relax(); + + writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP); + writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS); + writeb(reg, REQ_MB5_I2C_REG); + writeb(*value, REQ_MB5_I2C_VAL); + + writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET); + if (!wait_for_completion_timeout(&mb5_transfer.work, + msecs_to_jiffies(500))) { + pr_err("prcmu: prcmu_abb_write timed out.\n"); + r = -EIO; + goto unlock_and_return; + } + r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO); + +unlock_and_return: + mutex_unlock(&mb5_transfer.lock); + return r; +} +EXPORT_SYMBOL(prcmu_abb_write); + +static void read_mailbox_0(void) +{ + writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_1(void) +{ + writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_2(void) +{ + writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_3(void) +{ + writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_4(void) +{ + writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_5(void) +{ + mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS); + mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL); + complete(&mb5_transfer.work); + writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_6(void) +{ + writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR); +} + +static void read_mailbox_7(void) +{ + writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR); +} + +static void (* const read_mailbox[NUM_MBOX])(void) = { + read_mailbox_0, + read_mailbox_1, + read_mailbox_2, + read_mailbox_3, + read_mailbox_4, + read_mailbox_5, + read_mailbox_6, + read_mailbox_7 +}; + +static irqreturn_t prcmu_irq_handler(int irq, void *data) +{ + u32 bits; + u8 n; + + bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1)); + if (unlikely(!bits)) + return IRQ_NONE; + + for (n = 0; bits; n++) { + if (bits & MBOX_BIT(n)) { + bits -= MBOX_BIT(n); + read_mailbox[n](); + } + } + return IRQ_HANDLED; +} + +static int __init prcmu_init(void) +{ + mutex_init(&mb5_transfer.lock); + init_completion(&mb5_transfer.work); + + /* Clean up the mailbox interrupts after pre-kernel code. */ + writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR); + + return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL); +} + +arch_initcall(prcmu_init); -- cgit v1.2.3 From 7e3f7e59ccc6ed8b243de9941ffd09d2ad7a5b9c Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Thu, 2 Sep 2010 11:28:05 +0100 Subject: ARM: 6353/1: nomadik-gpio: add SLPM register handing for DB8500v2 The SLPM register enables/disables wakeup detection on DB8500v2. Acked-by: Linus Walleij Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/plat-nomadik/gpio.c | 30 ++++++++++++++++++++++++++--- arch/arm/plat-nomadik/include/plat/gpio.h | 2 ++ arch/arm/plat-nomadik/include/plat/pincfg.h | 5 ++++- 3 files changed, 33 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 977c8f9a07a2..014da39b6a88 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -118,8 +118,8 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, [3] /* illegal */ = "??" }; static const char *slpmnames[] = { - [NMK_GPIO_SLPM_INPUT] = "input", - [NMK_GPIO_SLPM_NOCHANGE] = "no-change", + [NMK_GPIO_SLPM_INPUT] = "input/wakeup", + [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", }; int pin = PIN_NUM(cfg); @@ -200,6 +200,10 @@ EXPORT_SYMBOL(nmk_config_pins); * changed to an input (with pullup/down enabled) in sleep and deep sleep. If * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was * configured even when in sleep and deep sleep. + * + * On DB8500v2 onwards, this setting loses the previous meaning and instead + * indicates if wakeup detection is enabled on the pin. Note that + * enable_irq_wake() will automatically enable wakeup detection. */ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) { @@ -367,7 +371,27 @@ static void nmk_gpio_irq_unmask(unsigned int irq) static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on) { - return nmk_gpio_irq_modify(irq, WAKE, on); + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + int gpio; + + gpio = NOMADIK_IRQ_TO_GPIO(irq); + nmk_chip = get_irq_chip_data(irq); + if (!nmk_chip) + return -EINVAL; + + spin_lock_irqsave(&nmk_chip->lock, flags); +#ifdef CONFIG_ARCH_U8500 + if (cpu_is_u8500v2()) { + __nmk_gpio_set_slpm(nmk_chip, gpio, + on ? NMK_GPIO_SLPM_WAKEUP_ENABLE + : NMK_GPIO_SLPM_WAKEUP_DISABLE); + } +#endif + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); + spin_unlock_irqrestore(&nmk_chip->lock, flags); + + return 0; } static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h index aba355101f49..67b113d639d8 100644 --- a/arch/arm/plat-nomadik/include/plat/gpio.h +++ b/arch/arm/plat-nomadik/include/plat/gpio.h @@ -65,7 +65,9 @@ enum nmk_gpio_pull { /* Sleep mode */ enum nmk_gpio_slpm { NMK_GPIO_SLPM_INPUT, + NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, NMK_GPIO_SLPM_NOCHANGE, + NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, }; extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 7eed11c1038d..432a201b3b41 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -24,7 +24,7 @@ * * PIN_CFG_DEFAULT - default config (0): * pull up/down = disabled - * sleep mode = input + * sleep mode = input/wakeup * * PIN_CFG - default config with alternate function * PIN_CFG_PULL - default config with alternate function and pull up/down @@ -55,6 +55,9 @@ typedef unsigned long pin_cfg_t; #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) #define PIN_SLPM_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) #define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) -- cgit v1.2.3 From 6720db7cc592b2148e0d88a7d76dc0532f3d266c Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Thu, 2 Sep 2010 11:28:48 +0100 Subject: ARM: 6354/1: nomadik-gpio: allow control of sleep mode direction and pull up DB8500v2 allows control of direction and pull up/down configuration in sleep mode, instead of switching the pin to input with pull up/down enabled. Acked-by: Linus Walleij Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/plat-nomadik/gpio.c | 42 +++++++++++++++++++++-------- arch/arm/plat-nomadik/include/plat/pincfg.h | 31 ++++++++++++++++++++- 2 files changed, 61 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 014da39b6a88..7afc7e8850b6 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -102,6 +102,22 @@ static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); } +static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int val) +{ + if (val) + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); + else + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); +} + +static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int val) +{ + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); + __nmk_gpio_set_output(nmk_chip, offset, val); +} + static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, pin_cfg_t cfg) { @@ -126,12 +142,21 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, int pull = PIN_PULL(cfg); int af = PIN_ALT(cfg); int slpm = PIN_SLPM(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); - dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n", - pin, afnames[af], pullnames[pull], slpmnames[slpm]); + dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n", + pin, afnames[af], pullnames[pull], slpmnames[slpm], + output ? "output " : "input", + output ? (val ? "high" : "low") : ""); + + if (output) + __nmk_gpio_make_output(nmk_chip, offset, val); + else { + __nmk_gpio_make_input(nmk_chip, offset); + __nmk_gpio_set_pull(nmk_chip, offset, pull); + } - __nmk_gpio_make_input(nmk_chip, offset); - __nmk_gpio_set_pull(nmk_chip, offset, pull); __nmk_gpio_set_slpm(nmk_chip, offset, slpm); __nmk_gpio_set_mode(nmk_chip, offset, af); } @@ -519,12 +544,8 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, { struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - u32 bit = 1 << offset; - if (val) - writel(bit, nmk_chip->addr + NMK_GPIO_DATS); - else - writel(bit, nmk_chip->addr + NMK_GPIO_DATC); + __nmk_gpio_set_output(nmk_chip, offset, val); } static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, @@ -533,8 +554,7 @@ static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); - writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); - nmk_gpio_set_output(chip, offset, val); + __nmk_gpio_make_output(nmk_chip, offset, val); return 0; } diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h index 432a201b3b41..8c5ae3f2acf8 100644 --- a/arch/arm/plat-nomadik/include/plat/pincfg.h +++ b/arch/arm/plat-nomadik/include/plat/pincfg.h @@ -19,12 +19,16 @@ * bit 9..10 - Alternate Function Selection * bit 11..12 - Pull up/down state * bit 13 - Sleep mode behaviour + * bit 14 - (sleep mode) Direction + * bit 15 - (sleep mode) Value (if output) * * to facilitate the definition, the following macros are provided * * PIN_CFG_DEFAULT - default config (0): * pull up/down = disabled * sleep mode = input/wakeup + * (sleep mode) direction = input + * (sleep mode) value = low * * PIN_CFG - default config with alternate function * PIN_CFG_PULL - default config with alternate function and pull up/down @@ -53,12 +57,37 @@ typedef unsigned long pin_cfg_t; #define PIN_SLPM_SHIFT 13 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) -#define PIN_SLPM_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) /* These two replace the above in DB8500v2+ */ #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +/* Shortcuts. Use these instead of separate DIR and VAL. */ +#define PIN_INPUT PIN_DIR_INPUT +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +/* + * These are the same as the ones above, but should make more sense to the + * reader when seen along with a setting a pin to AF mode. + */ +#define PIN_SLPM_INPUT PIN_INPUT +#define PIN_SLPM_OUTPUT_LOW PIN_OUTPUT_LOW +#define PIN_SLPM_OUTPUT_HIGH PIN_OUTPUT_HIGH + #define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) #define PIN_CFG(num, alt) \ -- cgit v1.2.3 From 495c7b8e64811e8117eca472c6f90dccda039dc4 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 2 Sep 2010 09:14:19 +0100 Subject: ARM: 6348/1: s3c64xx: don't put smartq7_leds in .init.data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a section mismatch found by modpost: WARNING: arch/arm/mach-s3c64xx/built-in.o(.data+0x2c1c): Section mismatch in reference from the variable smartq7_led_data to the (unknown reference) .init.data:(unknown) The variable smartq7_led_data references the (unknown reference) __initdata (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console, Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/mach-s3c64xx/mach-smartq7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c index e50a7d781732..78a58c351f0a 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c @@ -32,7 +32,7 @@ #include "mach-smartq.h" -static struct gpio_led smartq7_leds[] __initdata = { +static struct gpio_led smartq7_leds[] = { { .name = "smartq7:red", .active_low = 1, -- cgit v1.2.3 From d684f640639d7be8efb7b324294830d9bcbf15f9 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 2 Sep 2010 09:14:22 +0100 Subject: ARM: 6350/1: s3c64xx: don't put smartq5_leds in .init.data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a section mismatch found by modpost: WARNING: arch/arm/mach-s3c64xx/built-in.o(.data+0x2814): Section mismatch in reference from the variable smartq5_led_data to the (unknown reference) .init.data:(unknown) The variable smartq5_led_data references the (unknown reference) __initdata (unknown) If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console, Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/mach-s3c64xx/mach-smartq5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c index a4d59b076e3d..235e43928cb8 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c @@ -32,7 +32,7 @@ #include "mach-smartq.h" -static struct gpio_led smartq5_leds[] __initdata = { +static struct gpio_led smartq5_leds[] = { { .name = "smartq5:green", .active_low = 1, -- cgit v1.2.3 From 9e978f096241e303c10cf6e6dc80dce41ef41b92 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 2 Sep 2010 09:14:20 +0100 Subject: ARM: 6351/1: s3c64xx: don't put smartq_bl_init in .init.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a section mismatch found by modpost: WARNING: arch/arm/mach-s3c64xx/built-in.o(.data+0x2498): Section mismatch in reference from the variable smartq_backlight_data to the function .init.text:smartq_bl_init() The variable smartq_backlight_data references the function __init smartq_bl_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console, Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/mach-s3c64xx/mach-smartq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 3a9639bc3d9b..cb1ebeb08763 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -136,7 +136,7 @@ static struct platform_device smartq_usb_otg_vbus_dev = { .dev.platform_data = &smartq_usb_otg_vbus_pdata, }; -static int __init smartq_bl_init(struct device *dev) +static int smartq_bl_init(struct device *dev) { s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2)); -- cgit v1.2.3 From fd0d67d62def64ed5aa57f99d247e2b3d5eff8c5 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 2 Sep 2010 16:13:35 +0100 Subject: ARM: 6347/2: nomadik: move nmk_gpio_probe to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a section mismatch reported by modpost: WARNING: arch/arm/plat-nomadik/built-in.o(.data+0x100): Section mismatch in reference from the variable nmk_gpio_driver to the function .init.text:nmk_gpio_probe() The variable nmk_gpio_driver references the function __init nmk_gpio_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console, According to Rabin VINCENT the alternative to use platform_driver_probe won't work because the "platform devices are not yet registered when nmk_gpio_init() is called." Acked-by: Rabin Vincent Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/plat-nomadik/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 7afc7e8850b6..85e6fd212a41 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c @@ -578,7 +578,7 @@ static struct gpio_chip nmk_gpio_template = { .can_sleep = 0, }; -static int __init nmk_gpio_probe(struct platform_device *dev) +static int __devinit nmk_gpio_probe(struct platform_device *dev) { struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; struct nmk_gpio_chip *nmk_chip; -- cgit v1.2.3 From b744c679f62b368cb94c21c1dcd4618e42d88d63 Mon Sep 17 00:00:00 2001 From: Dmitry Kasatkin Date: Fri, 3 Sep 2010 19:13:55 +0800 Subject: crypto: updates to enable omap aes Signed-off-by: Dmitry Kasatkin Signed-off-by: Herbert Xu --- arch/arm/mach-omap2/clock2420_data.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 2 +- arch/arm/mach-omap2/clock3xxx_data.c | 2 +- arch/arm/mach-omap2/devices.c | 71 ++++++++++++++++++++++++++++++++++++ 4 files changed, 74 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 37d65d62ed8f..5f2066a6ba74 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -1838,7 +1838,7 @@ static struct omap_clk omap2420_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_242X), CLK("omap-sham", "ick", &sha_ick, CK_242X), CLK("omap_rng", "ick", &rng_ick, CK_242X), - CLK(NULL, "aes_ick", &aes_ick, CK_242X), + CLK("omap-aes", "ick", &aes_ick, CK_242X), CLK(NULL, "pka_ick", &pka_ick, CK_242X), CLK(NULL, "usb_fck", &usb_fck, CK_242X), CLK("musb_hdrc", "fck", &osc_ck, CK_242X), diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index b33118fb6a87..701a1716019e 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -1926,7 +1926,7 @@ static struct omap_clk omap2430_clks[] = { CLK(NULL, "des_ick", &des_ick, CK_243X), CLK("omap-sham", "ick", &sha_ick, CK_243X), CLK("omap_rng", "ick", &rng_ick, CK_243X), - CLK(NULL, "aes_ick", &aes_ick, CK_243X), + CLK("omap-aes", "ick", &aes_ick, CK_243X), CLK(NULL, "pka_ick", &pka_ick, CK_243X), CLK(NULL, "usb_fck", &usb_fck, CK_243X), CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index d33744117ce2..e3e65d1c86b2 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -3288,7 +3288,7 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), CLK(NULL, "icr_ick", &icr_ick, CK_343X), - CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), + CLK("omap-aes", "ick", &aes2_ick, CK_343X), CLK("omap-sham", "ick", &sha12_ick, CK_343X), CLK(NULL, "des2_ick", &des2_ick, CK_343X), CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 03e6c9ed82a4..072893a7d136 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -552,6 +552,76 @@ static void omap_init_sham(void) static inline void omap_init_sham(void) { } #endif +#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) + +#ifdef CONFIG_ARCH_OMAP24XX +static struct resource omap2_aes_resources[] = { + { + .start = OMAP24XX_SEC_AES_BASE, + .end = OMAP24XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP24XX_DMA_AES_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP24XX_DMA_AES_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); +#else +#define omap2_aes_resources NULL +#define omap2_aes_resources_sz 0 +#endif + +#ifdef CONFIG_ARCH_OMAP34XX +static struct resource omap3_aes_resources[] = { + { + .start = OMAP34XX_SEC_AES_BASE, + .end = OMAP34XX_SEC_AES_BASE + 0x4C, + .flags = IORESOURCE_MEM, + }, + { + .start = OMAP34XX_DMA_AES2_TX, + .flags = IORESOURCE_DMA, + }, + { + .start = OMAP34XX_DMA_AES2_RX, + .flags = IORESOURCE_DMA, + } +}; +static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); +#else +#define omap3_aes_resources NULL +#define omap3_aes_resources_sz 0 +#endif + +static struct platform_device aes_device = { + .name = "omap-aes", + .id = -1, +}; + +static void omap_init_aes(void) +{ + if (cpu_is_omap24xx()) { + aes_device.resource = omap2_aes_resources; + aes_device.num_resources = omap2_aes_resources_sz; + } else if (cpu_is_omap34xx()) { + aes_device.resource = omap3_aes_resources; + aes_device.num_resources = omap3_aes_resources_sz; + } else { + pr_err("%s: platform not supported\n", __func__); + return; + } + platform_device_register(&aes_device); +} + +#else +static inline void omap_init_aes(void) { } +#endif + /*-------------------------------------------------------------------------*/ #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) @@ -908,6 +978,7 @@ static int __init omap2_init_devices(void) omap_hdq_init(); omap_init_sti(); omap_init_sham(); + omap_init_aes(); omap_init_vout(); return 0; -- cgit v1.2.3 From 3a4b5dca53aecb16db9e007d782b2d1e757e941a Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 3 Sep 2010 10:39:59 +0100 Subject: ARM: 6355/1: hw-breakpoint: add mechanism for hooking into prefetch aborts On ARM processors with hardware breakpoint and watchpoint support, triggering these events results in a debug exception. These manifest as prefetch and data aborts respectively. arch/arm/mm/fault.c already provides hook_fault_code for hooking into data aborts dependent on the DFSR. This patch adds a new function, hook_ifault_code for hooking into prefetch aborts in the same manner. Cc: Frederic Weisbecker Cc: S. Karthikeyan Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/system.h | 4 ++++ arch/arm/mm/fault.c | 13 +++++++++++++ 2 files changed, 17 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 8ba1ccf82a02..b516cdea5ae2 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -85,6 +85,10 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), int sig, int code, const char *name); +void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, + struct pt_regs *), + int sig, int code, const char *name); + #define xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 23b0b03af5ea..1e21e125fe3a 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -581,6 +581,19 @@ static struct fsr_info ifsr_info[] = { { do_bad, SIGBUS, 0, "unknown 31" }, }; +void __init +hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *), + int sig, int code, const char *name) +{ + if (nr < 0 || nr >= ARRAY_SIZE(ifsr_info)) + BUG(); + + ifsr_info[nr].fn = fn; + ifsr_info[nr].sig = sig; + ifsr_info[nr].code = code; + ifsr_info[nr].name = name; +} + asmlinkage void __exception do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs) { -- cgit v1.2.3 From f81ef4a920c8e1af75adf9f15042c2daa49d3cb3 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 3 Sep 2010 10:41:08 +0100 Subject: ARM: 6356/1: hw-breakpoint: add ARM backend for the hw-breakpoint framework The hw-breakpoint framework in the kernel requires architecture-specific support in order to install, remove, validate and manage hardware breakpoints. This patch adds initial support for this framework to the ARM architecture, but restricts the number of watchpoints to a single resource to get around the fact that the Data Fault Address Register is unknown when a watchpoint debug exception is taken. On cores with v7 debug, the Kernel can handle breakpoint and watchpoint exceptions occuring from userspace. Older cores require clients to handle the exception themselves by registering an appropriate overflow handler or, in the case of ptrace, handling the raised SIGTRAP. The memory-mapped extended debug interface is unsupported due to its unreliability in real implementations. Cc: Frederic Weisbecker Cc: S. Karthikeyan Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/hw_breakpoint.h | 123 +++++ arch/arm/kernel/hw_breakpoint.c | 849 +++++++++++++++++++++++++++++++++++ 2 files changed, 972 insertions(+) create mode 100644 arch/arm/include/asm/hw_breakpoint.h create mode 100644 arch/arm/kernel/hw_breakpoint.c (limited to 'arch/arm') diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h new file mode 100644 index 000000000000..33048c700caa --- /dev/null +++ b/arch/arm/include/asm/hw_breakpoint.h @@ -0,0 +1,123 @@ +#ifndef _ARM_HW_BREAKPOINT_H +#define _ARM_HW_BREAKPOINT_H + +#ifdef __KERNEL__ +struct arch_hw_breakpoint_ctrl { + u32 __reserved : 9, + mismatch : 1, + : 9, + len : 8, + type : 2, + privilege : 2, + enabled : 1; +}; + +struct arch_hw_breakpoint { + u32 address; + u32 trigger; + struct perf_event *suspended_wp; + struct arch_hw_breakpoint_ctrl ctrl; +}; + +static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) +{ + return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) | + (ctrl.privilege << 1) | ctrl.enabled; +} + +static inline void decode_ctrl_reg(u32 reg, + struct arch_hw_breakpoint_ctrl *ctrl) +{ + ctrl->enabled = reg & 0x1; + reg >>= 1; + ctrl->privilege = reg & 0x3; + reg >>= 2; + ctrl->type = reg & 0x3; + reg >>= 2; + ctrl->len = reg & 0xff; + reg >>= 17; + ctrl->mismatch = reg & 0x1; +} + +/* Debug architecture numbers. */ +#define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */ +#define ARM_DEBUG_ARCH_V6 1 +#define ARM_DEBUG_ARCH_V6_1 2 +#define ARM_DEBUG_ARCH_V7_ECP14 3 +#define ARM_DEBUG_ARCH_V7_MM 4 + +/* Breakpoint */ +#define ARM_BREAKPOINT_EXECUTE 0 + +/* Watchpoints */ +#define ARM_BREAKPOINT_LOAD 1 +#define ARM_BREAKPOINT_STORE 2 + +/* Privilege Levels */ +#define ARM_BREAKPOINT_PRIV 1 +#define ARM_BREAKPOINT_USER 2 + +/* Lengths */ +#define ARM_BREAKPOINT_LEN_1 0x1 +#define ARM_BREAKPOINT_LEN_2 0x3 +#define ARM_BREAKPOINT_LEN_4 0xf +#define ARM_BREAKPOINT_LEN_8 0xff + +/* Limits */ +#define ARM_MAX_BRP 16 +#define ARM_MAX_WRP 16 +#define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP) + +/* DSCR method of entry bits. */ +#define ARM_DSCR_MOE(x) ((x >> 2) & 0xf) +#define ARM_ENTRY_BREAKPOINT 0x1 +#define ARM_ENTRY_ASYNC_WATCHPOINT 0x2 +#define ARM_ENTRY_SYNC_WATCHPOINT 0xa + +/* DSCR monitor/halting bits. */ +#define ARM_DSCR_HDBGEN (1 << 14) +#define ARM_DSCR_MDBGEN (1 << 15) + +/* opcode2 numbers for the co-processor instructions. */ +#define ARM_OP2_BVR 4 +#define ARM_OP2_BCR 5 +#define ARM_OP2_WVR 6 +#define ARM_OP2_WCR 7 + +/* Base register numbers for the debug registers. */ +#define ARM_BASE_BVR 64 +#define ARM_BASE_BCR 80 +#define ARM_BASE_WVR 96 +#define ARM_BASE_WCR 112 + +/* Accessor macros for the debug registers. */ +#define ARM_DBG_READ(M, OP2, VAL) do {\ + asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\ +} while (0) + +#define ARM_DBG_WRITE(M, OP2, VAL) do {\ + asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\ +} while (0) + +struct notifier_block; +struct perf_event; +struct pmu; +struct task_struct; + +extern struct pmu perf_ops_bp; +extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, + int *gen_len, int *gen_type); +extern int arch_check_bp_in_kernelspace(struct perf_event *bp); +extern int arch_validate_hwbkpt_settings(struct perf_event *bp); +extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data); +extern u8 arch_get_debug_arch(void); +extern u8 arch_get_max_wp_len(void); + +int arch_install_hw_breakpoint(struct perf_event *bp); +void arch_uninstall_hw_breakpoint(struct perf_event *bp); +void hw_breakpoint_pmu_read(struct perf_event *bp); +int hw_breakpoint_slots(int type); + +#endif /* __KERNEL__ */ +#endif /* _ARM_HW_BREAKPOINT_H */ diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c new file mode 100644 index 000000000000..54593b0c241b --- /dev/null +++ b/arch/arm/kernel/hw_breakpoint.c @@ -0,0 +1,849 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2009, 2010 ARM Limited + * + * Author: Will Deacon + */ + +/* + * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, + * using the CPU's debug registers. + */ +#define pr_fmt(fmt) "hw-breakpoint: " fmt + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Breakpoint currently in use for each BRP. */ +static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); + +/* Watchpoint currently in use for each WRP. */ +static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); + +/* Number of BRP/WRP registers on this CPU. */ +static int core_num_brps; +static int core_num_wrps; + +/* Debug architecture version. */ +static u8 debug_arch; + +/* Maximum supported watchpoint length. */ +static u8 max_watchpoint_len; + +/* Determine number of BRP registers available. */ +static int get_num_brps(void) +{ + u32 didr; + ARM_DBG_READ(c0, 0, didr); + return ((didr >> 24) & 0xf) + 1; +} + +/* Determine number of WRP registers available. */ +static int get_num_wrps(void) +{ + /* + * FIXME: When a watchpoint fires, the only way to work out which + * watchpoint it was is by disassembling the faulting instruction + * and working out the address of the memory access. + * + * Furthermore, we can only do this if the watchpoint was precise + * since imprecise watchpoints prevent us from calculating register + * based addresses. + * + * For the time being, we only report 1 watchpoint register so we + * always know which watchpoint fired. In the future we can either + * add a disassembler and address generation emulator, or we can + * insert a check to see if the DFAR is set on watchpoint exception + * entry [the ARM ARM states that the DFAR is UNKNOWN, but + * experience shows that it is set on some implementations]. + */ + +#if 0 + u32 didr, wrps; + ARM_DBG_READ(c0, 0, didr); + return ((didr >> 28) & 0xf) + 1; +#endif + + return 1; +} + +int hw_breakpoint_slots(int type) +{ + /* + * We can be called early, so don't rely on + * our static variables being initialised. + */ + switch (type) { + case TYPE_INST: + return get_num_brps(); + case TYPE_DATA: + return get_num_wrps(); + default: + pr_warning("unknown slot type: %d\n", type); + return 0; + } +} + +/* Determine debug architecture. */ +static u8 get_debug_arch(void) +{ + u32 didr; + + /* Do we implement the extended CPUID interface? */ + if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { + pr_warning("CPUID feature registers not supported. " + "Assuming v6 debug is present.\n"); + return ARM_DEBUG_ARCH_V6; + } + + ARM_DBG_READ(c0, 0, didr); + return (didr >> 16) & 0xf; +} + +/* Does this core support mismatch breakpoints? */ +static int core_has_mismatch_bps(void) +{ + return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1; +} + +u8 arch_get_debug_arch(void) +{ + return debug_arch; +} + +#define READ_WB_REG_CASE(OP2, M, VAL) \ + case ((OP2 << 4) + M): \ + ARM_DBG_READ(c ## M, OP2, VAL); \ + break + +#define WRITE_WB_REG_CASE(OP2, M, VAL) \ + case ((OP2 << 4) + M): \ + ARM_DBG_WRITE(c ## M, OP2, VAL);\ + break + +#define GEN_READ_WB_REG_CASES(OP2, VAL) \ + READ_WB_REG_CASE(OP2, 0, VAL); \ + READ_WB_REG_CASE(OP2, 1, VAL); \ + READ_WB_REG_CASE(OP2, 2, VAL); \ + READ_WB_REG_CASE(OP2, 3, VAL); \ + READ_WB_REG_CASE(OP2, 4, VAL); \ + READ_WB_REG_CASE(OP2, 5, VAL); \ + READ_WB_REG_CASE(OP2, 6, VAL); \ + READ_WB_REG_CASE(OP2, 7, VAL); \ + READ_WB_REG_CASE(OP2, 8, VAL); \ + READ_WB_REG_CASE(OP2, 9, VAL); \ + READ_WB_REG_CASE(OP2, 10, VAL); \ + READ_WB_REG_CASE(OP2, 11, VAL); \ + READ_WB_REG_CASE(OP2, 12, VAL); \ + READ_WB_REG_CASE(OP2, 13, VAL); \ + READ_WB_REG_CASE(OP2, 14, VAL); \ + READ_WB_REG_CASE(OP2, 15, VAL) + +#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ + WRITE_WB_REG_CASE(OP2, 0, VAL); \ + WRITE_WB_REG_CASE(OP2, 1, VAL); \ + WRITE_WB_REG_CASE(OP2, 2, VAL); \ + WRITE_WB_REG_CASE(OP2, 3, VAL); \ + WRITE_WB_REG_CASE(OP2, 4, VAL); \ + WRITE_WB_REG_CASE(OP2, 5, VAL); \ + WRITE_WB_REG_CASE(OP2, 6, VAL); \ + WRITE_WB_REG_CASE(OP2, 7, VAL); \ + WRITE_WB_REG_CASE(OP2, 8, VAL); \ + WRITE_WB_REG_CASE(OP2, 9, VAL); \ + WRITE_WB_REG_CASE(OP2, 10, VAL); \ + WRITE_WB_REG_CASE(OP2, 11, VAL); \ + WRITE_WB_REG_CASE(OP2, 12, VAL); \ + WRITE_WB_REG_CASE(OP2, 13, VAL); \ + WRITE_WB_REG_CASE(OP2, 14, VAL); \ + WRITE_WB_REG_CASE(OP2, 15, VAL) + +static u32 read_wb_reg(int n) +{ + u32 val = 0; + + switch (n) { + GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); + GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); + GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); + GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); + default: + pr_warning("attempt to read from unknown breakpoint " + "register %d\n", n); + } + + return val; +} + +static void write_wb_reg(int n, u32 val) +{ + switch (n) { + GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); + GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); + GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); + GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); + default: + pr_warning("attempt to write to unknown breakpoint " + "register %d\n", n); + } + isb(); +} + +/* + * In order to access the breakpoint/watchpoint control registers, + * we must be running in debug monitor mode. Unfortunately, we can + * be put into halting debug mode at any time by an external debugger + * but there is nothing we can do to prevent that. + */ +static int enable_monitor_mode(void) +{ + u32 dscr; + int ret = 0; + + ARM_DBG_READ(c1, 0, dscr); + + /* Ensure that halting mode is disabled. */ + if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled." + "Unable to access hardware resources.")) { + ret = -EPERM; + goto out; + } + + /* Write to the corresponding DSCR. */ + switch (debug_arch) { + case ARM_DEBUG_ARCH_V6: + case ARM_DEBUG_ARCH_V6_1: + ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); + break; + case ARM_DEBUG_ARCH_V7_ECP14: + ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); + break; + default: + ret = -ENODEV; + goto out; + } + + /* Check that the write made it through. */ + ARM_DBG_READ(c1, 0, dscr); + if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN), + "failed to enable monitor mode.")) { + ret = -EPERM; + } + +out: + return ret; +} + +/* + * Check if 8-bit byte-address select is available. + * This clobbers WRP 0. + */ +static u8 get_max_wp_len(void) +{ + u32 ctrl_reg; + struct arch_hw_breakpoint_ctrl ctrl; + u8 size = 4; + + if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) + goto out; + + if (enable_monitor_mode()) + goto out; + + memset(&ctrl, 0, sizeof(ctrl)); + ctrl.len = ARM_BREAKPOINT_LEN_8; + ctrl_reg = encode_ctrl_reg(ctrl); + + write_wb_reg(ARM_BASE_WVR, 0); + write_wb_reg(ARM_BASE_WCR, ctrl_reg); + if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) + size = 8; + +out: + return size; +} + +u8 arch_get_max_wp_len(void) +{ + return max_watchpoint_len; +} + +/* + * Handler for reactivating a suspended watchpoint when the single + * step `mismatch' breakpoint is triggered. + */ +static void wp_single_step_handler(struct perf_event *bp, int unused, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + perf_event_enable(counter_arch_bp(bp)->suspended_wp); + unregister_hw_breakpoint(bp); +} + +static int bp_is_single_step(struct perf_event *bp) +{ + return bp->overflow_handler == wp_single_step_handler; +} + +/* + * Install a perf counter breakpoint. + */ +int arch_install_hw_breakpoint(struct perf_event *bp) +{ + struct arch_hw_breakpoint *info = counter_arch_bp(bp); + struct perf_event **slot, **slots; + int i, max_slots, ctrl_base, val_base, ret = 0; + + /* Ensure that we are in monitor mode and halting mode is disabled. */ + ret = enable_monitor_mode(); + if (ret) + goto out; + + if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { + /* Breakpoint */ + ctrl_base = ARM_BASE_BCR; + val_base = ARM_BASE_BVR; + slots = __get_cpu_var(bp_on_reg); + max_slots = core_num_brps - 1; + + if (bp_is_single_step(bp)) { + info->ctrl.mismatch = 1; + i = max_slots; + slots[i] = bp; + goto setup; + } + } else { + /* Watchpoint */ + ctrl_base = ARM_BASE_WCR; + val_base = ARM_BASE_WVR; + slots = __get_cpu_var(wp_on_reg); + max_slots = core_num_wrps; + } + + for (i = 0; i < max_slots; ++i) { + slot = &slots[i]; + + if (!*slot) { + *slot = bp; + break; + } + } + + if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) { + ret = -EBUSY; + goto out; + } + +setup: + /* Setup the address register. */ + write_wb_reg(val_base + i, info->address); + + /* Setup the control register. */ + write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1); + +out: + return ret; +} + +void arch_uninstall_hw_breakpoint(struct perf_event *bp) +{ + struct arch_hw_breakpoint *info = counter_arch_bp(bp); + struct perf_event **slot, **slots; + int i, max_slots, base; + + if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { + /* Breakpoint */ + base = ARM_BASE_BCR; + slots = __get_cpu_var(bp_on_reg); + max_slots = core_num_brps - 1; + + if (bp_is_single_step(bp)) { + i = max_slots; + slots[i] = NULL; + goto reset; + } + } else { + /* Watchpoint */ + base = ARM_BASE_WCR; + slots = __get_cpu_var(wp_on_reg); + max_slots = core_num_wrps; + } + + /* Remove the breakpoint. */ + for (i = 0; i < max_slots; ++i) { + slot = &slots[i]; + + if (*slot == bp) { + *slot = NULL; + break; + } + } + + if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) + return; + +reset: + /* Reset the control register. */ + write_wb_reg(base + i, 0); +} + +static int get_hbp_len(u8 hbp_len) +{ + unsigned int len_in_bytes = 0; + + switch (hbp_len) { + case ARM_BREAKPOINT_LEN_1: + len_in_bytes = 1; + break; + case ARM_BREAKPOINT_LEN_2: + len_in_bytes = 2; + break; + case ARM_BREAKPOINT_LEN_4: + len_in_bytes = 4; + break; + case ARM_BREAKPOINT_LEN_8: + len_in_bytes = 8; + break; + } + + return len_in_bytes; +} + +/* + * Check whether bp virtual address is in kernel space. + */ +int arch_check_bp_in_kernelspace(struct perf_event *bp) +{ + unsigned int len; + unsigned long va; + struct arch_hw_breakpoint *info = counter_arch_bp(bp); + + va = info->address; + len = get_hbp_len(info->ctrl.len); + + return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); +} + +/* + * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. + * Hopefully this will disappear when ptrace can bypass the conversion + * to generic breakpoint descriptions. + */ +int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, + int *gen_len, int *gen_type) +{ + /* Type */ + switch (ctrl.type) { + case ARM_BREAKPOINT_EXECUTE: + *gen_type = HW_BREAKPOINT_X; + break; + case ARM_BREAKPOINT_LOAD: + *gen_type = HW_BREAKPOINT_R; + break; + case ARM_BREAKPOINT_STORE: + *gen_type = HW_BREAKPOINT_W; + break; + case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: + *gen_type = HW_BREAKPOINT_RW; + break; + default: + return -EINVAL; + } + + /* Len */ + switch (ctrl.len) { + case ARM_BREAKPOINT_LEN_1: + *gen_len = HW_BREAKPOINT_LEN_1; + break; + case ARM_BREAKPOINT_LEN_2: + *gen_len = HW_BREAKPOINT_LEN_2; + break; + case ARM_BREAKPOINT_LEN_4: + *gen_len = HW_BREAKPOINT_LEN_4; + break; + case ARM_BREAKPOINT_LEN_8: + *gen_len = HW_BREAKPOINT_LEN_8; + break; + default: + return -EINVAL; + } + + return 0; +} + +/* + * Construct an arch_hw_breakpoint from a perf_event. + */ +static int arch_build_bp_info(struct perf_event *bp) +{ + struct arch_hw_breakpoint *info = counter_arch_bp(bp); + + /* Type */ + switch (bp->attr.bp_type) { + case HW_BREAKPOINT_X: + info->ctrl.type = ARM_BREAKPOINT_EXECUTE; + break; + case HW_BREAKPOINT_R: + info->ctrl.type = ARM_BREAKPOINT_LOAD; + break; + case HW_BREAKPOINT_W: + info->ctrl.type = ARM_BREAKPOINT_STORE; + break; + case HW_BREAKPOINT_RW: + info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; + break; + default: + return -EINVAL; + } + + /* Len */ + switch (bp->attr.bp_len) { + case HW_BREAKPOINT_LEN_1: + info->ctrl.len = ARM_BREAKPOINT_LEN_1; + break; + case HW_BREAKPOINT_LEN_2: + info->ctrl.len = ARM_BREAKPOINT_LEN_2; + break; + case HW_BREAKPOINT_LEN_4: + info->ctrl.len = ARM_BREAKPOINT_LEN_4; + break; + case HW_BREAKPOINT_LEN_8: + info->ctrl.len = ARM_BREAKPOINT_LEN_8; + if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) + && max_watchpoint_len >= 8) + break; + default: + return -EINVAL; + } + + /* Address */ + info->address = bp->attr.bp_addr; + + /* Privilege */ + info->ctrl.privilege = ARM_BREAKPOINT_USER; + if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp)) + info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; + + /* Enabled? */ + info->ctrl.enabled = !bp->attr.disabled; + + /* Mismatch */ + info->ctrl.mismatch = 0; + + return 0; +} + +/* + * Validate the arch-specific HW Breakpoint register settings. + */ +int arch_validate_hwbkpt_settings(struct perf_event *bp) +{ + struct arch_hw_breakpoint *info = counter_arch_bp(bp); + int ret = 0; + u32 bytelen, max_len, offset, alignment_mask = 0x3; + + /* Build the arch_hw_breakpoint. */ + ret = arch_build_bp_info(bp); + if (ret) + goto out; + + /* Check address alignment. */ + if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) + alignment_mask = 0x7; + if (info->address & alignment_mask) { + /* + * Try to fix the alignment. This may result in a length + * that is too large, so we must check for that. + */ + bytelen = get_hbp_len(info->ctrl.len); + max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 : + max_watchpoint_len; + + if (max_len >= 8) + offset = info->address & 0x7; + else + offset = info->address & 0x3; + + if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) { + ret = -EFBIG; + goto out; + } + + info->ctrl.len <<= offset; + info->address &= ~offset; + + pr_debug("breakpoint alignment fixup: length = 0x%x, " + "address = 0x%x\n", info->ctrl.len, info->address); + } + + /* + * Currently we rely on an overflow handler to take + * care of single-stepping the breakpoint when it fires. + * In the case of userspace breakpoints on a core with V7 debug, + * we can use the mismatch feature as a poor-man's hardware single-step. + */ + if (WARN_ONCE(!bp->overflow_handler && + (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()), + "overflow handler required but none found")) { + ret = -EINVAL; + goto out; + } +out: + return ret; +} + +static void update_mismatch_flag(int idx, int flag) +{ + struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]); + struct arch_hw_breakpoint *info; + + if (bp == NULL) + return; + + info = counter_arch_bp(bp); + + /* Update the mismatch field to enter/exit `single-step' mode */ + if (!bp->overflow_handler && info->ctrl.mismatch != flag) { + info->ctrl.mismatch = flag; + write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1); + } +} + +static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) +{ + int i; + struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg); + struct arch_hw_breakpoint *info; + struct perf_event_attr attr; + + /* Without a disassembler, we can only handle 1 watchpoint. */ + BUG_ON(core_num_wrps > 1); + + hw_breakpoint_init(&attr); + attr.bp_addr = regs->ARM_pc & ~0x3; + attr.bp_len = HW_BREAKPOINT_LEN_4; + attr.bp_type = HW_BREAKPOINT_X; + + for (i = 0; i < core_num_wrps; ++i) { + rcu_read_lock(); + + if (slots[i] == NULL) { + rcu_read_unlock(); + continue; + } + + /* + * The DFAR is an unknown value. Since we only allow a + * single watchpoint, we can set the trigger to the lowest + * possible faulting address. + */ + info = counter_arch_bp(slots[i]); + info->trigger = slots[i]->attr.bp_addr; + pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); + perf_bp_event(slots[i], regs); + + /* + * If no overflow handler is present, insert a temporary + * mismatch breakpoint so we can single-step over the + * watchpoint trigger. + */ + if (!slots[i]->overflow_handler) { + bp = register_user_hw_breakpoint(&attr, + wp_single_step_handler, + current); + counter_arch_bp(bp)->suspended_wp = slots[i]; + perf_event_disable(slots[i]); + } + + rcu_read_unlock(); + } +} + +static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) +{ + int i; + int mismatch; + u32 ctrl_reg, val, addr; + struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg); + struct arch_hw_breakpoint *info; + struct arch_hw_breakpoint_ctrl ctrl; + + /* The exception entry code places the amended lr in the PC. */ + addr = regs->ARM_pc; + + for (i = 0; i < core_num_brps; ++i) { + rcu_read_lock(); + + bp = slots[i]; + + if (bp == NULL) { + rcu_read_unlock(); + continue; + } + + mismatch = 0; + + /* Check if the breakpoint value matches. */ + val = read_wb_reg(ARM_BASE_BVR + i); + if (val != (addr & ~0x3)) + goto unlock; + + /* Possible match, check the byte address select to confirm. */ + ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); + decode_ctrl_reg(ctrl_reg, &ctrl); + if ((1 << (addr & 0x3)) & ctrl.len) { + mismatch = 1; + info = counter_arch_bp(bp); + info->trigger = addr; + } + +unlock: + if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) { + pr_debug("breakpoint fired: address = 0x%x\n", addr); + perf_bp_event(bp, regs); + } + + update_mismatch_flag(i, mismatch); + rcu_read_unlock(); + } +} + +/* + * Called from either the Data Abort Handler [watchpoint] or the + * Prefetch Abort Handler [breakpoint]. + */ +static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + int ret = 1; /* Unhandled fault. */ + u32 dscr; + + /* We only handle watchpoints and hardware breakpoints. */ + ARM_DBG_READ(c1, 0, dscr); + + /* Perform perf callbacks. */ + switch (ARM_DSCR_MOE(dscr)) { + case ARM_ENTRY_BREAKPOINT: + breakpoint_handler(addr, regs); + break; + case ARM_ENTRY_ASYNC_WATCHPOINT: + WARN_ON("Asynchronous watchpoint exception taken. " + "Debugging results may be unreliable"); + case ARM_ENTRY_SYNC_WATCHPOINT: + watchpoint_handler(addr, regs); + break; + default: + goto out; + } + + ret = 0; +out: + return ret; +} + +/* + * One-time initialisation. + */ +static void __init reset_ctrl_regs(void *unused) +{ + int i; + + if (enable_monitor_mode()) + return; + + for (i = 0; i < core_num_brps; ++i) { + write_wb_reg(ARM_BASE_BCR + i, 0UL); + write_wb_reg(ARM_BASE_BVR + i, 0UL); + } + + for (i = 0; i < core_num_wrps; ++i) { + write_wb_reg(ARM_BASE_WCR + i, 0UL); + write_wb_reg(ARM_BASE_WVR + i, 0UL); + } +} + +static int __init arch_hw_breakpoint_init(void) +{ + int ret = 0; + u32 dscr; + + debug_arch = get_debug_arch(); + + if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { + pr_info("debug architecture 0x%x unsupported.\n", debug_arch); + ret = -ENODEV; + goto out; + } + + /* Determine how many BRPs/WRPs are available. */ + core_num_brps = get_num_brps(); + core_num_wrps = get_num_wrps(); + + pr_info("found %d breakpoint and %d watchpoint registers.\n", + core_num_brps, core_num_wrps); + + if (core_has_mismatch_bps()) + pr_info("1 breakpoint reserved for watchpoint single-step.\n"); + + ARM_DBG_READ(c1, 0, dscr); + if (dscr & ARM_DSCR_HDBGEN) { + pr_warning("halting debug mode enabled. Assuming maximum " + "watchpoint size of 4 bytes."); + } else { + /* Work out the maximum supported watchpoint length. */ + max_watchpoint_len = get_max_wp_len(); + pr_info("maximum watchpoint size is %u bytes.\n", + max_watchpoint_len); + + /* + * Reset the breakpoint resources. We assume that a halting + * debugger will leave the world in a nice state for us. + */ + smp_call_function(reset_ctrl_regs, NULL, 1); + reset_ctrl_regs(NULL); + } + + /* Register debug fault handler. */ + hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, + "watchpoint debug exception"); + hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, + "breakpoint debug exception"); + +out: + return ret; +} +arch_initcall(arch_hw_breakpoint_init); + +void hw_breakpoint_pmu_read(struct perf_event *bp) +{ +} + +/* + * Dummy function to register with die_notifier. + */ +int hw_breakpoint_exceptions_notify(struct notifier_block *unused, + unsigned long val, void *data) +{ + return NOTIFY_DONE; +} -- cgit v1.2.3 From 864232fa1a2f8dfe003438ef0851a56722740f3e Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 3 Sep 2010 10:42:55 +0100 Subject: ARM: 6357/1: hw-breakpoint: add new ptrace requests for hw-breakpoint interaction For debuggers to take advantage of the hw-breakpoint framework in the kernel, it is necessary to expose the API calls via a ptrace interface. This patch exposes the hardware breakpoints framework as a collection of virtual registers, accesible using PTRACE_SETHBPREGS and PTRACE_GETHBPREGS requests. The breakpoints are stored in the debug_info struct of the running thread. Cc: Frederic Weisbecker Cc: S. Karthikeyan Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/hw_breakpoint.h | 12 +- arch/arm/include/asm/processor.h | 4 + arch/arm/include/asm/ptrace.h | 2 + arch/arm/kernel/process.c | 5 + arch/arm/kernel/ptrace.c | 239 +++++++++++++++++++++++++++++++++++ 5 files changed, 261 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h index 33048c700caa..4d8ae9d67abe 100644 --- a/arch/arm/include/asm/hw_breakpoint.h +++ b/arch/arm/include/asm/hw_breakpoint.h @@ -2,6 +2,11 @@ #define _ARM_HW_BREAKPOINT_H #ifdef __KERNEL__ + +struct task_struct; + +#ifdef CONFIG_HAVE_HW_BREAKPOINT + struct arch_hw_breakpoint_ctrl { u32 __reserved : 9, mismatch : 1, @@ -102,7 +107,6 @@ static inline void decode_ctrl_reg(u32 reg, struct notifier_block; struct perf_event; struct pmu; -struct task_struct; extern struct pmu perf_ops_bp; extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, @@ -111,13 +115,19 @@ extern int arch_check_bp_in_kernelspace(struct perf_event *bp); extern int arch_validate_hwbkpt_settings(struct perf_event *bp); extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, unsigned long val, void *data); + extern u8 arch_get_debug_arch(void); extern u8 arch_get_max_wp_len(void); +extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk); int arch_install_hw_breakpoint(struct perf_event *bp); void arch_uninstall_hw_breakpoint(struct perf_event *bp); void hw_breakpoint_pmu_read(struct perf_event *bp); int hw_breakpoint_slots(int type); +#else +static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {} + +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ #endif /* __KERNEL__ */ #endif /* _ARM_HW_BREAKPOINT_H */ diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 7bed3daf83b8..67357baaeeeb 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ +#include #include #include @@ -41,6 +42,9 @@ struct debug_entry { struct debug_info { int nsaved; struct debug_entry bp[2]; +#ifdef CONFIG_HAVE_HW_BREAKPOINT + struct perf_event *hbp[ARM_MAX_HBP_SLOTS]; +#endif }; struct thread_struct { diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 7ce15eb15f72..783d50f32618 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -29,6 +29,8 @@ #define PTRACE_SETCRUNCHREGS 26 #define PTRACE_GETVFPREGS 27 #define PTRACE_SETVFPREGS 28 +#define PTRACE_GETHBPREGS 29 +#define PTRACE_SETHBPREGS 30 /* * PSR bits diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 401e38be1f78..974af1c3eb1d 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -317,6 +318,8 @@ void flush_thread(void) struct thread_info *thread = current_thread_info(); struct task_struct *tsk = current; + flush_ptrace_hw_breakpoint(tsk); + memset(thread->used_cp, 0, sizeof(thread->used_cp)); memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); memset(&thread->fpstate, 0, sizeof(union fp_state)); @@ -345,6 +348,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start, thread->cpu_context.sp = (unsigned long)childregs; thread->cpu_context.pc = (unsigned long)ret_from_fork; + clear_ptrace_hw_breakpoint(p); + if (clone_flags & CLONE_SETTLS) thread->tp_value = regs->ARM_r3; diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index f99d489822d5..e0cb6370ed14 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include @@ -847,6 +849,232 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) } #endif +#ifdef CONFIG_HAVE_HW_BREAKPOINT +/* + * Convert a virtual register number into an index for a thread_info + * breakpoint array. Breakpoints are identified using positive numbers + * whilst watchpoints are negative. The registers are laid out as pairs + * of (address, control), each pair mapping to a unique hw_breakpoint struct. + * Register 0 is reserved for describing resource information. + */ +static int ptrace_hbp_num_to_idx(long num) +{ + if (num < 0) + num = (ARM_MAX_BRP << 1) - num; + return (num - 1) >> 1; +} + +/* + * Returns the virtual register number for the address of the + * breakpoint at index idx. + */ +static long ptrace_hbp_idx_to_num(int idx) +{ + long mid = ARM_MAX_BRP << 1; + long num = (idx << 1) + 1; + return num > mid ? mid - num : num; +} + +/* + * Handle hitting a HW-breakpoint. + */ +static void ptrace_hbptriggered(struct perf_event *bp, int unused, + struct perf_sample_data *data, + struct pt_regs *regs) +{ + struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp); + long num; + int i; + siginfo_t info; + + for (i = 0; i < ARM_MAX_HBP_SLOTS; ++i) + if (current->thread.debug.hbp[i] == bp) + break; + + num = (i == ARM_MAX_HBP_SLOTS) ? 0 : ptrace_hbp_idx_to_num(i); + + info.si_signo = SIGTRAP; + info.si_errno = (int)num; + info.si_code = TRAP_HWBKPT; + info.si_addr = (void __user *)(bkpt->trigger); + + force_sig_info(SIGTRAP, &info, current); +} + +/* + * Set ptrace breakpoint pointers to zero for this task. + * This is required in order to prevent child processes from unregistering + * breakpoints held by their parent. + */ +void clear_ptrace_hw_breakpoint(struct task_struct *tsk) +{ + memset(tsk->thread.debug.hbp, 0, sizeof(tsk->thread.debug.hbp)); +} + +/* + * Unregister breakpoints from this task and reset the pointers in + * the thread_struct. + */ +void flush_ptrace_hw_breakpoint(struct task_struct *tsk) +{ + int i; + struct thread_struct *t = &tsk->thread; + + for (i = 0; i < ARM_MAX_HBP_SLOTS; i++) { + if (t->debug.hbp[i]) { + unregister_hw_breakpoint(t->debug.hbp[i]); + t->debug.hbp[i] = NULL; + } + } +} + +static u32 ptrace_get_hbp_resource_info(void) +{ + u8 num_brps, num_wrps, debug_arch, wp_len; + u32 reg = 0; + + num_brps = hw_breakpoint_slots(TYPE_INST); + num_wrps = hw_breakpoint_slots(TYPE_DATA); + debug_arch = arch_get_debug_arch(); + wp_len = arch_get_max_wp_len(); + + reg |= debug_arch; + reg <<= 8; + reg |= wp_len; + reg <<= 8; + reg |= num_wrps; + reg <<= 8; + reg |= num_brps; + + return reg; +} + +static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type) +{ + struct perf_event_attr attr; + + ptrace_breakpoint_init(&attr); + + /* Initialise fields to sane defaults. */ + attr.bp_addr = 0; + attr.bp_len = HW_BREAKPOINT_LEN_4; + attr.bp_type = type; + attr.disabled = 1; + + return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, tsk); +} + +static int ptrace_gethbpregs(struct task_struct *tsk, long num, + unsigned long __user *data) +{ + u32 reg; + int idx, ret = 0; + struct perf_event *bp; + struct arch_hw_breakpoint_ctrl arch_ctrl; + + if (num == 0) { + reg = ptrace_get_hbp_resource_info(); + } else { + idx = ptrace_hbp_num_to_idx(num); + if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) { + ret = -EINVAL; + goto out; + } + + bp = tsk->thread.debug.hbp[idx]; + if (!bp) { + reg = 0; + goto put; + } + + arch_ctrl = counter_arch_bp(bp)->ctrl; + + /* + * Fix up the len because we may have adjusted it + * to compensate for an unaligned address. + */ + while (!(arch_ctrl.len & 0x1)) + arch_ctrl.len >>= 1; + + if (idx & 0x1) + reg = encode_ctrl_reg(arch_ctrl); + else + reg = bp->attr.bp_addr; + } + +put: + if (put_user(reg, data)) + ret = -EFAULT; + +out: + return ret; +} + +static int ptrace_sethbpregs(struct task_struct *tsk, long num, + unsigned long __user *data) +{ + int idx, gen_len, gen_type, implied_type, ret = 0; + u32 user_val; + struct perf_event *bp; + struct arch_hw_breakpoint_ctrl ctrl; + struct perf_event_attr attr; + + if (num == 0) + goto out; + else if (num < 0) + implied_type = HW_BREAKPOINT_RW; + else + implied_type = HW_BREAKPOINT_X; + + idx = ptrace_hbp_num_to_idx(num); + if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) { + ret = -EINVAL; + goto out; + } + + if (get_user(user_val, data)) { + ret = -EFAULT; + goto out; + } + + bp = tsk->thread.debug.hbp[idx]; + if (!bp) { + bp = ptrace_hbp_create(tsk, implied_type); + if (IS_ERR(bp)) { + ret = PTR_ERR(bp); + goto out; + } + tsk->thread.debug.hbp[idx] = bp; + } + + attr = bp->attr; + + if (num & 0x1) { + /* Address */ + attr.bp_addr = user_val; + } else { + /* Control */ + decode_ctrl_reg(user_val, &ctrl); + ret = arch_bp_generic_fields(ctrl, &gen_len, &gen_type); + if (ret) + goto out; + + if ((gen_type & implied_type) != gen_type) { + ret = -EINVAL; + goto out; + } + + attr.bp_len = gen_len; + attr.bp_type = gen_type; + attr.disabled = !ctrl.enabled; + } + + ret = modify_user_hw_breakpoint(bp, &attr); +out: + return ret; +} +#endif + long arch_ptrace(struct task_struct *child, long request, long addr, long data) { int ret; @@ -916,6 +1144,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) break; #endif +#ifdef CONFIG_HAVE_HW_BREAKPOINT + case PTRACE_GETHBPREGS: + ret = ptrace_gethbpregs(child, addr, + (unsigned long __user *)data); + break; + case PTRACE_SETHBPREGS: + ret = ptrace_sethbpregs(child, addr, + (unsigned long __user *)data); + break; +#endif + default: ret = ptrace_request(child, request, addr, data); break; -- cgit v1.2.3 From 19852e59002fbba1c2c6ba0f154095a37ad2ac03 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 3 Sep 2010 10:44:33 +0100 Subject: ARM: 6358/1: hw-breakpoint: add HAVE_HW_BREAKPOINT to Kconfig If we're targetting a v6 or v7 core and have at least software perf events available, then automatically add support for hardware breakpoints. Cc: Frederic Weisbecker Cc: S. Karthikeyan Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/Kconfig | 1 + arch/arm/kernel/Makefile | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 16bc8eb4901c..0fdd099d4a67 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -26,6 +26,7 @@ config ARM select HAVE_PERF_EVENTS select PERF_USE_VMALLOC select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 980b78e31328..5b9b268f4fbb 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_ARM_UNWIND) += unwind.o obj-$(CONFIG_HAVE_TCM) += tcm.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o +obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 -- cgit v1.2.3 From 51b0fe39549a04858001922919ab355dee9bdfcf Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 11 Jun 2010 13:35:57 +0200 Subject: perf: Deconstify struct pmu sed -ie 's/const struct pmu\>/struct pmu/g' `git grep -l "const struct pmu\>"` Signed-off-by: Peter Zijlstra Cc: paulus Cc: stephane eranian Cc: Robert Richter Cc: Will Deacon Cc: Paul Mundt Cc: Frederic Weisbecker Cc: Cyrill Gorcunov Cc: Lin Ming Cc: Yanmin Cc: Deng-Cheng Zhu Cc: David Miller Cc: Michael Cree LKML-Reference: Signed-off-by: Ingo Molnar --- arch/alpha/kernel/perf_event.c | 4 ++-- arch/arm/kernel/perf_event.c | 2 +- arch/powerpc/kernel/perf_event.c | 8 ++++---- arch/powerpc/kernel/perf_event_fsl_emb.c | 2 +- arch/sh/kernel/perf_event.c | 4 ++-- arch/sparc/kernel/perf_event.c | 10 +++++----- arch/x86/kernel/cpu/perf_event.c | 14 +++++++------- include/linux/perf_event.h | 10 +++++----- kernel/perf_event.c | 26 +++++++++++++------------- 9 files changed, 40 insertions(+), 40 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 51c39fa41693..56fa41590381 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -642,7 +642,7 @@ static int __hw_perf_event_init(struct perf_event *event) return 0; } -static const struct pmu pmu = { +static struct pmu pmu = { .enable = alpha_pmu_enable, .disable = alpha_pmu_disable, .read = alpha_pmu_read, @@ -653,7 +653,7 @@ static const struct pmu pmu = { /* * Main entry point to initialise a HW performance event. */ -const struct pmu *hw_perf_event_init(struct perf_event *event) +struct pmu *hw_perf_event_init(struct perf_event *event) { int err; diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 64ca8c3ab94b..0671e92c5111 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -491,7 +491,7 @@ __hw_perf_event_init(struct perf_event *event) return err; } -const struct pmu * +struct pmu * hw_perf_event_init(struct perf_event *event) { int err = 0; diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index d301a30445e0..5f78681ad902 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -857,7 +857,7 @@ static void power_pmu_unthrottle(struct perf_event *event) * Set the flag to make pmu::enable() not perform the * schedulability test, it will be performed at commit time */ -void power_pmu_start_txn(const struct pmu *pmu) +void power_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); @@ -870,7 +870,7 @@ void power_pmu_start_txn(const struct pmu *pmu) * Clear the flag and pmu::enable() will perform the * schedulability test. */ -void power_pmu_cancel_txn(const struct pmu *pmu) +void power_pmu_cancel_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); @@ -882,7 +882,7 @@ void power_pmu_cancel_txn(const struct pmu *pmu) * Perform the group schedulability test as a whole * Return 0 if success */ -int power_pmu_commit_txn(const struct pmu *pmu) +int power_pmu_commit_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw; long i, n; @@ -1014,7 +1014,7 @@ static int hw_perf_cache_event(u64 config, u64 *eventp) return 0; } -const struct pmu *hw_perf_event_init(struct perf_event *event) +struct pmu *hw_perf_event_init(struct perf_event *event) { u64 ev; unsigned long flags; diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c index 1ba45471ae43..d7619b5e7a6e 100644 --- a/arch/powerpc/kernel/perf_event_fsl_emb.c +++ b/arch/powerpc/kernel/perf_event_fsl_emb.c @@ -428,7 +428,7 @@ static int hw_perf_cache_event(u64 config, u64 *eventp) return 0; } -const struct pmu *hw_perf_event_init(struct perf_event *event) +struct pmu *hw_perf_event_init(struct perf_event *event) { u64 ev; struct perf_event *events[MAX_HWEVENTS]; diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index 7a3dc3567258..395572c94c6a 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -257,13 +257,13 @@ static void sh_pmu_read(struct perf_event *event) sh_perf_event_update(event, &event->hw, event->hw.idx); } -static const struct pmu pmu = { +static struct pmu pmu = { .enable = sh_pmu_enable, .disable = sh_pmu_disable, .read = sh_pmu_read, }; -const struct pmu *hw_perf_event_init(struct perf_event *event) +struct pmu *hw_perf_event_init(struct perf_event *event) { int err = __hw_perf_event_init(event); if (unlikely(err)) { diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 4bc402938575..481b894a5018 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1099,7 +1099,7 @@ static int __hw_perf_event_init(struct perf_event *event) * Set the flag to make pmu::enable() not perform the * schedulability test, it will be performed at commit time */ -static void sparc_pmu_start_txn(const struct pmu *pmu) +static void sparc_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); @@ -1111,7 +1111,7 @@ static void sparc_pmu_start_txn(const struct pmu *pmu) * Clear the flag and pmu::enable() will perform the * schedulability test. */ -static void sparc_pmu_cancel_txn(const struct pmu *pmu) +static void sparc_pmu_cancel_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); @@ -1123,7 +1123,7 @@ static void sparc_pmu_cancel_txn(const struct pmu *pmu) * Perform the group schedulability test as a whole * Return 0 if success */ -static int sparc_pmu_commit_txn(const struct pmu *pmu) +static int sparc_pmu_commit_txn(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int n; @@ -1142,7 +1142,7 @@ static int sparc_pmu_commit_txn(const struct pmu *pmu) return 0; } -static const struct pmu pmu = { +static struct pmu pmu = { .enable = sparc_pmu_enable, .disable = sparc_pmu_disable, .read = sparc_pmu_read, @@ -1152,7 +1152,7 @@ static const struct pmu pmu = { .commit_txn = sparc_pmu_commit_txn, }; -const struct pmu *hw_perf_event_init(struct perf_event *event) +struct pmu *hw_perf_event_init(struct perf_event *event) { int err = __hw_perf_event_init(event); diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index de6569c04cd0..fdd97f2e9961 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -618,7 +618,7 @@ static void x86_pmu_enable_all(int added) } } -static const struct pmu pmu; +static struct pmu pmu; static inline int is_x86_event(struct perf_event *event) { @@ -1427,7 +1427,7 @@ static inline void x86_pmu_read(struct perf_event *event) * Set the flag to make pmu::enable() not perform the * schedulability test, it will be performed at commit time */ -static void x86_pmu_start_txn(const struct pmu *pmu) +static void x86_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -1440,7 +1440,7 @@ static void x86_pmu_start_txn(const struct pmu *pmu) * Clear the flag and pmu::enable() will perform the * schedulability test. */ -static void x86_pmu_cancel_txn(const struct pmu *pmu) +static void x86_pmu_cancel_txn(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -1457,7 +1457,7 @@ static void x86_pmu_cancel_txn(const struct pmu *pmu) * Perform the group schedulability test as a whole * Return 0 if success */ -static int x86_pmu_commit_txn(const struct pmu *pmu) +static int x86_pmu_commit_txn(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int assign[X86_PMC_IDX_MAX]; @@ -1483,7 +1483,7 @@ static int x86_pmu_commit_txn(const struct pmu *pmu) return 0; } -static const struct pmu pmu = { +static struct pmu pmu = { .enable = x86_pmu_enable, .disable = x86_pmu_disable, .start = x86_pmu_start, @@ -1569,9 +1569,9 @@ out: return ret; } -const struct pmu *hw_perf_event_init(struct perf_event *event) +struct pmu *hw_perf_event_init(struct perf_event *event) { - const struct pmu *tmp; + struct pmu *tmp; int err; err = __hw_perf_event_init(event); diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 000610c4de71..09d048b52115 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -578,19 +578,19 @@ struct pmu { * Start the transaction, after this ->enable() doesn't need * to do schedulability tests. */ - void (*start_txn) (const struct pmu *pmu); + void (*start_txn) (struct pmu *pmu); /* * If ->start_txn() disabled the ->enable() schedulability test * then ->commit_txn() is required to perform one. On success * the transaction is closed. On error the transaction is kept * open until ->cancel_txn() is called. */ - int (*commit_txn) (const struct pmu *pmu); + int (*commit_txn) (struct pmu *pmu); /* * Will cancel the transaction, assumes ->disable() is called for * each successfull ->enable() during the transaction. */ - void (*cancel_txn) (const struct pmu *pmu); + void (*cancel_txn) (struct pmu *pmu); }; /** @@ -669,7 +669,7 @@ struct perf_event { int nr_siblings; int group_flags; struct perf_event *group_leader; - const struct pmu *pmu; + struct pmu *pmu; enum perf_event_active_state state; unsigned int attach_state; @@ -849,7 +849,7 @@ struct perf_output_handle { */ extern int perf_max_events; -extern const struct pmu *hw_perf_event_init(struct perf_event *event); +extern struct pmu *hw_perf_event_init(struct perf_event *event); extern void perf_event_task_sched_in(struct task_struct *task); extern void perf_event_task_sched_out(struct task_struct *task, struct task_struct *next); diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 2d74f31220ad..fb46fd13f31f 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -75,7 +75,7 @@ static DEFINE_SPINLOCK(perf_resource_lock); /* * Architecture provided APIs - weak aliases: */ -extern __weak const struct pmu *hw_perf_event_init(struct perf_event *event) +extern __weak struct pmu *hw_perf_event_init(struct perf_event *event) { return NULL; } @@ -691,7 +691,7 @@ group_sched_in(struct perf_event *group_event, struct perf_event_context *ctx) { struct perf_event *event, *partial_group = NULL; - const struct pmu *pmu = group_event->pmu; + struct pmu *pmu = group_event->pmu; bool txn = false; if (group_event->state == PERF_EVENT_STATE_OFF) @@ -4501,7 +4501,7 @@ static int perf_swevent_int(struct perf_event *event) return 0; } -static const struct pmu perf_ops_generic = { +static struct pmu perf_ops_generic = { .enable = perf_swevent_enable, .disable = perf_swevent_disable, .start = perf_swevent_int, @@ -4614,7 +4614,7 @@ static void cpu_clock_perf_event_read(struct perf_event *event) cpu_clock_perf_event_update(event); } -static const struct pmu perf_ops_cpu_clock = { +static struct pmu perf_ops_cpu_clock = { .enable = cpu_clock_perf_event_enable, .disable = cpu_clock_perf_event_disable, .read = cpu_clock_perf_event_read, @@ -4671,7 +4671,7 @@ static void task_clock_perf_event_read(struct perf_event *event) task_clock_perf_event_update(event, time); } -static const struct pmu perf_ops_task_clock = { +static struct pmu perf_ops_task_clock = { .enable = task_clock_perf_event_enable, .disable = task_clock_perf_event_disable, .read = task_clock_perf_event_read, @@ -4785,7 +4785,7 @@ static int swevent_hlist_get(struct perf_event *event) #ifdef CONFIG_EVENT_TRACING -static const struct pmu perf_ops_tracepoint = { +static struct pmu perf_ops_tracepoint = { .enable = perf_trace_enable, .disable = perf_trace_disable, .start = perf_swevent_int, @@ -4849,7 +4849,7 @@ static void tp_perf_event_destroy(struct perf_event *event) perf_trace_destroy(event); } -static const struct pmu *tp_perf_event_init(struct perf_event *event) +static struct pmu *tp_perf_event_init(struct perf_event *event) { int err; @@ -4896,7 +4896,7 @@ static void perf_event_free_filter(struct perf_event *event) #else -static const struct pmu *tp_perf_event_init(struct perf_event *event) +static struct pmu *tp_perf_event_init(struct perf_event *event) { return NULL; } @@ -4918,7 +4918,7 @@ static void bp_perf_event_destroy(struct perf_event *event) release_bp_slot(event); } -static const struct pmu *bp_perf_event_init(struct perf_event *bp) +static struct pmu *bp_perf_event_init(struct perf_event *bp) { int err; @@ -4942,7 +4942,7 @@ void perf_bp_event(struct perf_event *bp, void *data) perf_swevent_add(bp, 1, 1, &sample, regs); } #else -static const struct pmu *bp_perf_event_init(struct perf_event *bp) +static struct pmu *bp_perf_event_init(struct perf_event *bp) { return NULL; } @@ -4964,9 +4964,9 @@ static void sw_perf_event_destroy(struct perf_event *event) swevent_hlist_put(event); } -static const struct pmu *sw_perf_event_init(struct perf_event *event) +static struct pmu *sw_perf_event_init(struct perf_event *event) { - const struct pmu *pmu = NULL; + struct pmu *pmu = NULL; u64 event_id = event->attr.config; /* @@ -5028,7 +5028,7 @@ perf_event_alloc(struct perf_event_attr *attr, perf_overflow_handler_t overflow_handler, gfp_t gfpflags) { - const struct pmu *pmu; + struct pmu *pmu; struct perf_event *event; struct hw_perf_event *hwc; long err; -- cgit v1.2.3 From b0a873ebbf87bf38bf70b5e39a7cadc96099fa13 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 11 Jun 2010 13:35:08 +0200 Subject: perf: Register PMU implementations Simple registration interface for struct pmu, this provides the infrastructure for removing all the weak functions. Signed-off-by: Peter Zijlstra Cc: paulus Cc: stephane eranian Cc: Robert Richter Cc: Will Deacon Cc: Paul Mundt Cc: Frederic Weisbecker Cc: Cyrill Gorcunov Cc: Lin Ming Cc: Yanmin Cc: Deng-Cheng Zhu Cc: David Miller Cc: Michael Cree LKML-Reference: Signed-off-by: Ingo Molnar --- arch/alpha/kernel/perf_event.c | 37 +- arch/arm/kernel/perf_event.c | 38 +- arch/powerpc/kernel/perf_event.c | 46 +-- arch/powerpc/kernel/perf_event_fsl_emb.c | 37 +- arch/sh/kernel/perf_event.c | 35 +- arch/sparc/kernel/perf_event.c | 29 +- arch/x86/kernel/cpu/perf_event.c | 45 ++- include/linux/perf_event.h | 10 +- kernel/hw_breakpoint.c | 35 +- kernel/perf_event.c | 588 +++++++++++++++---------------- 10 files changed, 488 insertions(+), 412 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 56fa41590381..19660b5c298f 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -642,34 +642,39 @@ static int __hw_perf_event_init(struct perf_event *event) return 0; } -static struct pmu pmu = { - .enable = alpha_pmu_enable, - .disable = alpha_pmu_disable, - .read = alpha_pmu_read, - .unthrottle = alpha_pmu_unthrottle, -}; - - /* * Main entry point to initialise a HW performance event. */ -struct pmu *hw_perf_event_init(struct perf_event *event) +static int alpha_pmu_event_init(struct perf_event *event) { int err; + switch (event->attr.type) { + case PERF_TYPE_RAW: + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + break; + + default: + return -ENOENT; + } + if (!alpha_pmu) - return ERR_PTR(-ENODEV); + return -ENODEV; /* Do the real initialisation work. */ err = __hw_perf_event_init(event); - if (err) - return ERR_PTR(err); - - return &pmu; + return err; } - +static struct pmu pmu = { + .event_init = alpha_pmu_event_init, + .enable = alpha_pmu_enable, + .disable = alpha_pmu_disable, + .read = alpha_pmu_read, + .unthrottle = alpha_pmu_unthrottle, +}; /* * Main entry point - enable HW performance counters. @@ -838,5 +843,7 @@ void __init init_hw_perf_events(void) /* And set up PMU specification */ alpha_pmu = &ev67_pmu; perf_max_events = alpha_pmu->num_pmcs; + + perf_pmu_register(&pmu); } diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 0671e92c5111..f62f9db35db3 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -306,12 +306,7 @@ out: return err; } -static struct pmu pmu = { - .enable = armpmu_enable, - .disable = armpmu_disable, - .unthrottle = armpmu_unthrottle, - .read = armpmu_read, -}; +static struct pmu pmu; static int validate_event(struct cpu_hw_events *cpuc, @@ -491,20 +486,29 @@ __hw_perf_event_init(struct perf_event *event) return err; } -struct pmu * -hw_perf_event_init(struct perf_event *event) +static int armpmu_event_init(struct perf_event *event) { int err = 0; + switch (event->attr.type) { + case PERF_TYPE_RAW: + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + break; + + default: + return -ENOENT; + } + if (!armpmu) - return ERR_PTR(-ENODEV); + return -ENODEV; event->destroy = hw_perf_event_destroy; if (!atomic_inc_not_zero(&active_events)) { if (atomic_read(&active_events) > perf_max_events) { atomic_dec(&active_events); - return ERR_PTR(-ENOSPC); + return -ENOSPC; } mutex_lock(&pmu_reserve_mutex); @@ -518,15 +522,23 @@ hw_perf_event_init(struct perf_event *event) } if (err) - return ERR_PTR(err); + return err; err = __hw_perf_event_init(event); if (err) hw_perf_event_destroy(event); - return err ? ERR_PTR(err) : &pmu; + return err; } +static struct pmu pmu = { + .event_init = armpmu_event_init, + .enable = armpmu_enable, + .disable = armpmu_disable, + .unthrottle = armpmu_unthrottle, + .read = armpmu_read, +}; + void hw_perf_enable(void) { @@ -2994,6 +3006,8 @@ init_hw_perf_events(void) perf_max_events = -1; } + perf_pmu_register(&pmu); + return 0; } arch_initcall(init_hw_perf_events); diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index 5f78681ad902..19131b2614b9 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -904,16 +904,6 @@ int power_pmu_commit_txn(struct pmu *pmu) return 0; } -struct pmu power_pmu = { - .enable = power_pmu_enable, - .disable = power_pmu_disable, - .read = power_pmu_read, - .unthrottle = power_pmu_unthrottle, - .start_txn = power_pmu_start_txn, - .cancel_txn = power_pmu_cancel_txn, - .commit_txn = power_pmu_commit_txn, -}; - /* * Return 1 if we might be able to put event on a limited PMC, * or 0 if not. @@ -1014,7 +1004,7 @@ static int hw_perf_cache_event(u64 config, u64 *eventp) return 0; } -struct pmu *hw_perf_event_init(struct perf_event *event) +static int power_pmu_event_init(struct perf_event *event) { u64 ev; unsigned long flags; @@ -1026,25 +1016,27 @@ struct pmu *hw_perf_event_init(struct perf_event *event) struct cpu_hw_events *cpuhw; if (!ppmu) - return ERR_PTR(-ENXIO); + return -ENOENT; + switch (event->attr.type) { case PERF_TYPE_HARDWARE: ev = event->attr.config; if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) - return ERR_PTR(-EOPNOTSUPP); + return -EOPNOTSUPP; ev = ppmu->generic_events[ev]; break; case PERF_TYPE_HW_CACHE: err = hw_perf_cache_event(event->attr.config, &ev); if (err) - return ERR_PTR(err); + return err; break; case PERF_TYPE_RAW: ev = event->attr.config; break; default: - return ERR_PTR(-EINVAL); + return -ENOENT; } + event->hw.config_base = ev; event->hw.idx = 0; @@ -1081,7 +1073,7 @@ struct pmu *hw_perf_event_init(struct perf_event *event) */ ev = normal_pmc_alternative(ev, flags); if (!ev) - return ERR_PTR(-EINVAL); + return -EINVAL; } } @@ -1095,19 +1087,19 @@ struct pmu *hw_perf_event_init(struct perf_event *event) n = collect_events(event->group_leader, ppmu->n_counter - 1, ctrs, events, cflags); if (n < 0) - return ERR_PTR(-EINVAL); + return -EINVAL; } events[n] = ev; ctrs[n] = event; cflags[n] = flags; if (check_excludes(ctrs, cflags, n, 1)) - return ERR_PTR(-EINVAL); + return -EINVAL; cpuhw = &get_cpu_var(cpu_hw_events); err = power_check_constraints(cpuhw, events, cflags, n + 1); put_cpu_var(cpu_hw_events); if (err) - return ERR_PTR(-EINVAL); + return -EINVAL; event->hw.config = events[n]; event->hw.event_base = cflags[n]; @@ -1132,11 +1124,20 @@ struct pmu *hw_perf_event_init(struct perf_event *event) } event->destroy = hw_perf_event_destroy; - if (err) - return ERR_PTR(err); - return &power_pmu; + return err; } +struct pmu power_pmu = { + .event_init = power_pmu_event_init, + .enable = power_pmu_enable, + .disable = power_pmu_disable, + .read = power_pmu_read, + .unthrottle = power_pmu_unthrottle, + .start_txn = power_pmu_start_txn, + .cancel_txn = power_pmu_cancel_txn, + .commit_txn = power_pmu_commit_txn, +}; + /* * A counter has overflowed; update its count and record * things if requested. Note that interrupts are hard-disabled @@ -1342,6 +1343,7 @@ int register_power_pmu(struct power_pmu *pmu) freeze_events_kernel = MMCR0_FCHV; #endif /* CONFIG_PPC64 */ + perf_pmu_register(&power_pmu); perf_cpu_notifier(power_pmu_notifier); return 0; diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c index d7619b5e7a6e..ea6a804e43fd 100644 --- a/arch/powerpc/kernel/perf_event_fsl_emb.c +++ b/arch/powerpc/kernel/perf_event_fsl_emb.c @@ -378,13 +378,6 @@ static void fsl_emb_pmu_unthrottle(struct perf_event *event) local_irq_restore(flags); } -static struct pmu fsl_emb_pmu = { - .enable = fsl_emb_pmu_enable, - .disable = fsl_emb_pmu_disable, - .read = fsl_emb_pmu_read, - .unthrottle = fsl_emb_pmu_unthrottle, -}; - /* * Release the PMU if this is the last perf_event. */ @@ -428,7 +421,7 @@ static int hw_perf_cache_event(u64 config, u64 *eventp) return 0; } -struct pmu *hw_perf_event_init(struct perf_event *event) +static int fsl_emb_pmu_event_init(struct perf_event *event) { u64 ev; struct perf_event *events[MAX_HWEVENTS]; @@ -441,14 +434,14 @@ struct pmu *hw_perf_event_init(struct perf_event *event) case PERF_TYPE_HARDWARE: ev = event->attr.config; if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) - return ERR_PTR(-EOPNOTSUPP); + return -EOPNOTSUPP; ev = ppmu->generic_events[ev]; break; case PERF_TYPE_HW_CACHE: err = hw_perf_cache_event(event->attr.config, &ev); if (err) - return ERR_PTR(err); + return err; break; case PERF_TYPE_RAW: @@ -456,12 +449,12 @@ struct pmu *hw_perf_event_init(struct perf_event *event) break; default: - return ERR_PTR(-EINVAL); + return -ENOENT; } event->hw.config = ppmu->xlate_event(ev); if (!(event->hw.config & FSL_EMB_EVENT_VALID)) - return ERR_PTR(-EINVAL); + return -EINVAL; /* * If this is in a group, check if it can go on with all the @@ -473,7 +466,7 @@ struct pmu *hw_perf_event_init(struct perf_event *event) n = collect_events(event->group_leader, ppmu->n_counter - 1, events); if (n < 0) - return ERR_PTR(-EINVAL); + return -EINVAL; } if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) { @@ -484,7 +477,7 @@ struct pmu *hw_perf_event_init(struct perf_event *event) } if (num_restricted >= ppmu->n_restricted) - return ERR_PTR(-EINVAL); + return -EINVAL; } event->hw.idx = -1; @@ -497,7 +490,7 @@ struct pmu *hw_perf_event_init(struct perf_event *event) if (event->attr.exclude_kernel) event->hw.config_base |= PMLCA_FCS; if (event->attr.exclude_idle) - return ERR_PTR(-ENOTSUPP); + return -ENOTSUPP; event->hw.last_period = event->hw.sample_period; local64_set(&event->hw.period_left, event->hw.last_period); @@ -523,11 +516,17 @@ struct pmu *hw_perf_event_init(struct perf_event *event) } event->destroy = hw_perf_event_destroy; - if (err) - return ERR_PTR(err); - return &fsl_emb_pmu; + return err; } +static struct pmu fsl_emb_pmu = { + .event_init = fsl_emb_pmu_event_init, + .enable = fsl_emb_pmu_enable, + .disable = fsl_emb_pmu_disable, + .read = fsl_emb_pmu_read, + .unthrottle = fsl_emb_pmu_unthrottle, +}; + /* * A counter has overflowed; update its count and record * things if requested. Note that interrupts are hard-disabled @@ -651,5 +650,7 @@ int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu) pr_info("%s performance monitor hardware support registered\n", pmu->name); + perf_pmu_register(&fsl_emb_pmu); + return 0; } diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index 395572c94c6a..8cb206597e0c 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -257,26 +257,38 @@ static void sh_pmu_read(struct perf_event *event) sh_perf_event_update(event, &event->hw, event->hw.idx); } -static struct pmu pmu = { - .enable = sh_pmu_enable, - .disable = sh_pmu_disable, - .read = sh_pmu_read, -}; - -struct pmu *hw_perf_event_init(struct perf_event *event) +static int sh_pmu_event_init(struct perf_event *event) { - int err = __hw_perf_event_init(event); + int err; + + switch (event->attr.type) { + case PERF_TYPE_RAW: + case PERF_TYPE_HW_CACHE: + case PERF_TYPE_HARDWARE: + err = __hw_perf_event_init(event); + break; + + default: + return -ENOENT; + } + if (unlikely(err)) { if (event->destroy) event->destroy(event); - return ERR_PTR(err); } - return &pmu; + return err; } +static struct pmu pmu = { + .event_init = sh_pmu_event_init, + .enable = sh_pmu_enable, + .disable = sh_pmu_disable, + .read = sh_pmu_read, +}; + static void sh_pmu_setup(int cpu) -{ + struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); memset(cpuhw, 0, sizeof(struct cpu_hw_events)); @@ -325,6 +337,7 @@ int __cpuinit register_sh_pmu(struct sh_pmu *pmu) WARN_ON(pmu->num_events > MAX_HWEVENTS); + perf_pmu_register(&pmu); perf_cpu_notifier(sh_pmu_notifier); return 0; } diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 481b894a5018..bed4327f5a7a 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1025,7 +1025,7 @@ out: return ret; } -static int __hw_perf_event_init(struct perf_event *event) +static int sparc_pmu_event_init(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; struct perf_event *evts[MAX_HWEVENTS]; @@ -1038,17 +1038,27 @@ static int __hw_perf_event_init(struct perf_event *event) if (atomic_read(&nmi_active) < 0) return -ENODEV; - if (attr->type == PERF_TYPE_HARDWARE) { + switch (attr->type) { + case PERF_TYPE_HARDWARE: if (attr->config >= sparc_pmu->max_events) return -EINVAL; pmap = sparc_pmu->event_map(attr->config); - } else if (attr->type == PERF_TYPE_HW_CACHE) { + break; + + case PERF_TYPE_HW_CACHE: pmap = sparc_map_cache_event(attr->config); if (IS_ERR(pmap)) return PTR_ERR(pmap); - } else + break; + + case PERF_TYPE_RAW: return -EOPNOTSUPP; + default: + return -ENOENT; + + } + /* We save the enable bits in the config_base. */ hwc->config_base = sparc_pmu->irq_bit; if (!attr->exclude_user) @@ -1143,6 +1153,7 @@ static int sparc_pmu_commit_txn(struct pmu *pmu) } static struct pmu pmu = { + .event_init = sparc_pmu_event_init, .enable = sparc_pmu_enable, .disable = sparc_pmu_disable, .read = sparc_pmu_read, @@ -1152,15 +1163,6 @@ static struct pmu pmu = { .commit_txn = sparc_pmu_commit_txn, }; -struct pmu *hw_perf_event_init(struct perf_event *event) -{ - int err = __hw_perf_event_init(event); - - if (err) - return ERR_PTR(err); - return &pmu; -} - void perf_event_print_debug(void) { unsigned long flags; @@ -1280,6 +1282,7 @@ void __init init_hw_perf_events(void) /* All sparc64 PMUs currently have 2 events. */ perf_max_events = 2; + perf_pmu_register(&pmu); register_die_notifier(&perf_event_nmi_notifier); } diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index fdd97f2e9961..2c89264ee791 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -530,7 +530,7 @@ static int x86_pmu_hw_config(struct perf_event *event) /* * Setup the hardware configuration for a given attr_type */ -static int __hw_perf_event_init(struct perf_event *event) +static int __x86_pmu_event_init(struct perf_event *event) { int err; @@ -1414,6 +1414,7 @@ void __init init_hw_perf_events(void) pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); + perf_pmu_register(&pmu); perf_cpu_notifier(x86_pmu_notifier); } @@ -1483,18 +1484,6 @@ static int x86_pmu_commit_txn(struct pmu *pmu) return 0; } -static struct pmu pmu = { - .enable = x86_pmu_enable, - .disable = x86_pmu_disable, - .start = x86_pmu_start, - .stop = x86_pmu_stop, - .read = x86_pmu_read, - .unthrottle = x86_pmu_unthrottle, - .start_txn = x86_pmu_start_txn, - .cancel_txn = x86_pmu_cancel_txn, - .commit_txn = x86_pmu_commit_txn, -}; - /* * validate that we can schedule this event */ @@ -1569,12 +1558,22 @@ out: return ret; } -struct pmu *hw_perf_event_init(struct perf_event *event) +int x86_pmu_event_init(struct perf_event *event) { struct pmu *tmp; int err; - err = __hw_perf_event_init(event); + switch (event->attr.type) { + case PERF_TYPE_RAW: + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + break; + + default: + return -ENOENT; + } + + err = __x86_pmu_event_init(event); if (!err) { /* * we temporarily connect event to its pmu @@ -1594,12 +1593,24 @@ struct pmu *hw_perf_event_init(struct perf_event *event) if (err) { if (event->destroy) event->destroy(event); - return ERR_PTR(err); } - return &pmu; + return err; } +static struct pmu pmu = { + .event_init = x86_pmu_event_init, + .enable = x86_pmu_enable, + .disable = x86_pmu_disable, + .start = x86_pmu_start, + .stop = x86_pmu_stop, + .read = x86_pmu_read, + .unthrottle = x86_pmu_unthrottle, + .start_txn = x86_pmu_start_txn, + .cancel_txn = x86_pmu_cancel_txn, + .commit_txn = x86_pmu_commit_txn, +}; + /* * callchain support */ diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 09d048b52115..ab72f56eb372 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -561,6 +561,13 @@ struct perf_event; * struct pmu - generic performance monitoring unit */ struct pmu { + struct list_head entry; + + /* + * Should return -ENOENT when the @event doesn't match this pmu + */ + int (*event_init) (struct perf_event *event); + int (*enable) (struct perf_event *event); void (*disable) (struct perf_event *event); int (*start) (struct perf_event *event); @@ -849,7 +856,8 @@ struct perf_output_handle { */ extern int perf_max_events; -extern struct pmu *hw_perf_event_init(struct perf_event *event); +extern int perf_pmu_register(struct pmu *pmu); +extern void perf_pmu_unregister(struct pmu *pmu); extern void perf_event_task_sched_in(struct task_struct *task); extern void perf_event_task_sched_out(struct task_struct *task, struct task_struct *next); diff --git a/kernel/hw_breakpoint.c b/kernel/hw_breakpoint.c index d71a987fd2bf..e9c5cfa1fd20 100644 --- a/kernel/hw_breakpoint.c +++ b/kernel/hw_breakpoint.c @@ -565,6 +565,34 @@ static struct notifier_block hw_breakpoint_exceptions_nb = { .priority = 0x7fffffff }; +static void bp_perf_event_destroy(struct perf_event *event) +{ + release_bp_slot(event); +} + +static int hw_breakpoint_event_init(struct perf_event *bp) +{ + int err; + + if (bp->attr.type != PERF_TYPE_BREAKPOINT) + return -ENOENT; + + err = register_perf_hw_breakpoint(bp); + if (err) + return err; + + bp->destroy = bp_perf_event_destroy; + + return 0; +} + +static struct pmu perf_breakpoint = { + .event_init = hw_breakpoint_event_init, + .enable = arch_install_hw_breakpoint, + .disable = arch_uninstall_hw_breakpoint, + .read = hw_breakpoint_pmu_read, +}; + static int __init init_hw_breakpoint(void) { unsigned int **task_bp_pinned; @@ -586,6 +614,8 @@ static int __init init_hw_breakpoint(void) constraints_initialized = 1; + perf_pmu_register(&perf_breakpoint); + return register_die_notifier(&hw_breakpoint_exceptions_nb); err_alloc: @@ -601,8 +631,3 @@ static int __init init_hw_breakpoint(void) core_initcall(init_hw_breakpoint); -struct pmu perf_ops_bp = { - .enable = arch_install_hw_breakpoint, - .disable = arch_uninstall_hw_breakpoint, - .read = hw_breakpoint_pmu_read, -}; diff --git a/kernel/perf_event.c b/kernel/perf_event.c index fb46fd13f31f..288ce43de57c 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -31,7 +31,6 @@ #include #include #include -#include #include @@ -72,14 +71,6 @@ static atomic64_t perf_event_id; */ static DEFINE_SPINLOCK(perf_resource_lock); -/* - * Architecture provided APIs - weak aliases: - */ -extern __weak struct pmu *hw_perf_event_init(struct perf_event *event) -{ - return NULL; -} - void __weak hw_perf_disable(void) { barrier(); } void __weak hw_perf_enable(void) { barrier(); } @@ -4501,182 +4492,6 @@ static int perf_swevent_int(struct perf_event *event) return 0; } -static struct pmu perf_ops_generic = { - .enable = perf_swevent_enable, - .disable = perf_swevent_disable, - .start = perf_swevent_int, - .stop = perf_swevent_void, - .read = perf_swevent_read, - .unthrottle = perf_swevent_void, /* hwc->interrupts already reset */ -}; - -/* - * hrtimer based swevent callback - */ - -static enum hrtimer_restart perf_swevent_hrtimer(struct hrtimer *hrtimer) -{ - enum hrtimer_restart ret = HRTIMER_RESTART; - struct perf_sample_data data; - struct pt_regs *regs; - struct perf_event *event; - u64 period; - - event = container_of(hrtimer, struct perf_event, hw.hrtimer); - event->pmu->read(event); - - perf_sample_data_init(&data, 0); - data.period = event->hw.last_period; - regs = get_irq_regs(); - - if (regs && !perf_exclude_event(event, regs)) { - if (!(event->attr.exclude_idle && current->pid == 0)) - if (perf_event_overflow(event, 0, &data, regs)) - ret = HRTIMER_NORESTART; - } - - period = max_t(u64, 10000, event->hw.sample_period); - hrtimer_forward_now(hrtimer, ns_to_ktime(period)); - - return ret; -} - -static void perf_swevent_start_hrtimer(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - - hrtimer_init(&hwc->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - hwc->hrtimer.function = perf_swevent_hrtimer; - if (hwc->sample_period) { - u64 period; - - if (hwc->remaining) { - if (hwc->remaining < 0) - period = 10000; - else - period = hwc->remaining; - hwc->remaining = 0; - } else { - period = max_t(u64, 10000, hwc->sample_period); - } - __hrtimer_start_range_ns(&hwc->hrtimer, - ns_to_ktime(period), 0, - HRTIMER_MODE_REL, 0); - } -} - -static void perf_swevent_cancel_hrtimer(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - - if (hwc->sample_period) { - ktime_t remaining = hrtimer_get_remaining(&hwc->hrtimer); - hwc->remaining = ktime_to_ns(remaining); - - hrtimer_cancel(&hwc->hrtimer); - } -} - -/* - * Software event: cpu wall time clock - */ - -static void cpu_clock_perf_event_update(struct perf_event *event) -{ - int cpu = raw_smp_processor_id(); - s64 prev; - u64 now; - - now = cpu_clock(cpu); - prev = local64_xchg(&event->hw.prev_count, now); - local64_add(now - prev, &event->count); -} - -static int cpu_clock_perf_event_enable(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int cpu = raw_smp_processor_id(); - - local64_set(&hwc->prev_count, cpu_clock(cpu)); - perf_swevent_start_hrtimer(event); - - return 0; -} - -static void cpu_clock_perf_event_disable(struct perf_event *event) -{ - perf_swevent_cancel_hrtimer(event); - cpu_clock_perf_event_update(event); -} - -static void cpu_clock_perf_event_read(struct perf_event *event) -{ - cpu_clock_perf_event_update(event); -} - -static struct pmu perf_ops_cpu_clock = { - .enable = cpu_clock_perf_event_enable, - .disable = cpu_clock_perf_event_disable, - .read = cpu_clock_perf_event_read, -}; - -/* - * Software event: task time clock - */ - -static void task_clock_perf_event_update(struct perf_event *event, u64 now) -{ - u64 prev; - s64 delta; - - prev = local64_xchg(&event->hw.prev_count, now); - delta = now - prev; - local64_add(delta, &event->count); -} - -static int task_clock_perf_event_enable(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - u64 now; - - now = event->ctx->time; - - local64_set(&hwc->prev_count, now); - - perf_swevent_start_hrtimer(event); - - return 0; -} - -static void task_clock_perf_event_disable(struct perf_event *event) -{ - perf_swevent_cancel_hrtimer(event); - task_clock_perf_event_update(event, event->ctx->time); - -} - -static void task_clock_perf_event_read(struct perf_event *event) -{ - u64 time; - - if (!in_nmi()) { - update_context_time(event->ctx); - time = event->ctx->time; - } else { - u64 now = perf_clock(); - u64 delta = now - event->ctx->timestamp; - time = event->ctx->time + delta; - } - - task_clock_perf_event_update(event, time); -} - -static struct pmu perf_ops_task_clock = { - .enable = task_clock_perf_event_enable, - .disable = task_clock_perf_event_disable, - .read = task_clock_perf_event_read, -}; - /* Deref the hlist from the update side */ static inline struct swevent_hlist * swevent_hlist_deref(struct perf_cpu_context *cpuctx) @@ -4783,17 +4598,63 @@ static int swevent_hlist_get(struct perf_event *event) return err; } -#ifdef CONFIG_EVENT_TRACING +atomic_t perf_swevent_enabled[PERF_COUNT_SW_MAX]; -static struct pmu perf_ops_tracepoint = { - .enable = perf_trace_enable, - .disable = perf_trace_disable, +static void sw_perf_event_destroy(struct perf_event *event) +{ + u64 event_id = event->attr.config; + + WARN_ON(event->parent); + + atomic_dec(&perf_swevent_enabled[event_id]); + swevent_hlist_put(event); +} + +static int perf_swevent_init(struct perf_event *event) +{ + int event_id = event->attr.config; + + if (event->attr.type != PERF_TYPE_SOFTWARE) + return -ENOENT; + + switch (event_id) { + case PERF_COUNT_SW_CPU_CLOCK: + case PERF_COUNT_SW_TASK_CLOCK: + return -ENOENT; + + default: + break; + } + + if (event_id > PERF_COUNT_SW_MAX) + return -ENOENT; + + if (!event->parent) { + int err; + + err = swevent_hlist_get(event); + if (err) + return err; + + atomic_inc(&perf_swevent_enabled[event_id]); + event->destroy = sw_perf_event_destroy; + } + + return 0; +} + +static struct pmu perf_swevent = { + .event_init = perf_swevent_init, + .enable = perf_swevent_enable, + .disable = perf_swevent_disable, .start = perf_swevent_int, .stop = perf_swevent_void, .read = perf_swevent_read, - .unthrottle = perf_swevent_void, + .unthrottle = perf_swevent_void, /* hwc->interrupts already reset */ }; +#ifdef CONFIG_EVENT_TRACING + static int perf_tp_filter_match(struct perf_event *event, struct perf_sample_data *data) { @@ -4849,10 +4710,13 @@ static void tp_perf_event_destroy(struct perf_event *event) perf_trace_destroy(event); } -static struct pmu *tp_perf_event_init(struct perf_event *event) +static int perf_tp_event_init(struct perf_event *event) { int err; + if (event->attr.type != PERF_TYPE_TRACEPOINT) + return -ENOENT; + /* * Raw tracepoint data is a severe data leak, only allow root to * have these. @@ -4860,15 +4724,30 @@ static struct pmu *tp_perf_event_init(struct perf_event *event) if ((event->attr.sample_type & PERF_SAMPLE_RAW) && perf_paranoid_tracepoint_raw() && !capable(CAP_SYS_ADMIN)) - return ERR_PTR(-EPERM); + return -EPERM; err = perf_trace_init(event); if (err) - return NULL; + return err; event->destroy = tp_perf_event_destroy; - return &perf_ops_tracepoint; + return 0; +} + +static struct pmu perf_tracepoint = { + .event_init = perf_tp_event_init, + .enable = perf_trace_enable, + .disable = perf_trace_disable, + .start = perf_swevent_int, + .stop = perf_swevent_void, + .read = perf_swevent_read, + .unthrottle = perf_swevent_void, +}; + +static inline void perf_tp_register(void) +{ + perf_pmu_register(&perf_tracepoint); } static int perf_event_set_filter(struct perf_event *event, void __user *arg) @@ -4896,9 +4775,8 @@ static void perf_event_free_filter(struct perf_event *event) #else -static struct pmu *tp_perf_event_init(struct perf_event *event) +static inline void perf_tp_register(void) { - return NULL; } static int perf_event_set_filter(struct perf_event *event, void __user *arg) @@ -4913,105 +4791,247 @@ static void perf_event_free_filter(struct perf_event *event) #endif /* CONFIG_EVENT_TRACING */ #ifdef CONFIG_HAVE_HW_BREAKPOINT -static void bp_perf_event_destroy(struct perf_event *event) +void perf_bp_event(struct perf_event *bp, void *data) { - release_bp_slot(event); + struct perf_sample_data sample; + struct pt_regs *regs = data; + + perf_sample_data_init(&sample, bp->attr.bp_addr); + + if (!perf_exclude_event(bp, regs)) + perf_swevent_add(bp, 1, 1, &sample, regs); } +#endif + +/* + * hrtimer based swevent callback + */ -static struct pmu *bp_perf_event_init(struct perf_event *bp) +static enum hrtimer_restart perf_swevent_hrtimer(struct hrtimer *hrtimer) { - int err; + enum hrtimer_restart ret = HRTIMER_RESTART; + struct perf_sample_data data; + struct pt_regs *regs; + struct perf_event *event; + u64 period; - err = register_perf_hw_breakpoint(bp); - if (err) - return ERR_PTR(err); + event = container_of(hrtimer, struct perf_event, hw.hrtimer); + event->pmu->read(event); + + perf_sample_data_init(&data, 0); + data.period = event->hw.last_period; + regs = get_irq_regs(); + + if (regs && !perf_exclude_event(event, regs)) { + if (!(event->attr.exclude_idle && current->pid == 0)) + if (perf_event_overflow(event, 0, &data, regs)) + ret = HRTIMER_NORESTART; + } - bp->destroy = bp_perf_event_destroy; + period = max_t(u64, 10000, event->hw.sample_period); + hrtimer_forward_now(hrtimer, ns_to_ktime(period)); - return &perf_ops_bp; + return ret; } -void perf_bp_event(struct perf_event *bp, void *data) +static void perf_swevent_start_hrtimer(struct perf_event *event) { - struct perf_sample_data sample; - struct pt_regs *regs = data; + struct hw_perf_event *hwc = &event->hw; - perf_sample_data_init(&sample, bp->attr.bp_addr); + hrtimer_init(&hwc->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + hwc->hrtimer.function = perf_swevent_hrtimer; + if (hwc->sample_period) { + u64 period; - if (!perf_exclude_event(bp, regs)) - perf_swevent_add(bp, 1, 1, &sample, regs); + if (hwc->remaining) { + if (hwc->remaining < 0) + period = 10000; + else + period = hwc->remaining; + hwc->remaining = 0; + } else { + period = max_t(u64, 10000, hwc->sample_period); + } + __hrtimer_start_range_ns(&hwc->hrtimer, + ns_to_ktime(period), 0, + HRTIMER_MODE_REL, 0); + } } -#else -static struct pmu *bp_perf_event_init(struct perf_event *bp) + +static void perf_swevent_cancel_hrtimer(struct perf_event *event) { - return NULL; + struct hw_perf_event *hwc = &event->hw; + + if (hwc->sample_period) { + ktime_t remaining = hrtimer_get_remaining(&hwc->hrtimer); + hwc->remaining = ktime_to_ns(remaining); + + hrtimer_cancel(&hwc->hrtimer); + } } -void perf_bp_event(struct perf_event *bp, void *regs) +/* + * Software event: cpu wall time clock + */ + +static void cpu_clock_event_update(struct perf_event *event) { + int cpu = raw_smp_processor_id(); + s64 prev; + u64 now; + + now = cpu_clock(cpu); + prev = local64_xchg(&event->hw.prev_count, now); + local64_add(now - prev, &event->count); } -#endif -atomic_t perf_swevent_enabled[PERF_COUNT_SW_MAX]; +static int cpu_clock_event_enable(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + int cpu = raw_smp_processor_id(); -static void sw_perf_event_destroy(struct perf_event *event) + local64_set(&hwc->prev_count, cpu_clock(cpu)); + perf_swevent_start_hrtimer(event); + + return 0; +} + +static void cpu_clock_event_disable(struct perf_event *event) { - u64 event_id = event->attr.config; + perf_swevent_cancel_hrtimer(event); + cpu_clock_event_update(event); +} - WARN_ON(event->parent); +static void cpu_clock_event_read(struct perf_event *event) +{ + cpu_clock_event_update(event); +} - atomic_dec(&perf_swevent_enabled[event_id]); - swevent_hlist_put(event); +static int cpu_clock_event_init(struct perf_event *event) +{ + if (event->attr.type != PERF_TYPE_SOFTWARE) + return -ENOENT; + + if (event->attr.config != PERF_COUNT_SW_CPU_CLOCK) + return -ENOENT; + + return 0; } -static struct pmu *sw_perf_event_init(struct perf_event *event) +static struct pmu perf_cpu_clock = { + .event_init = cpu_clock_event_init, + .enable = cpu_clock_event_enable, + .disable = cpu_clock_event_disable, + .read = cpu_clock_event_read, +}; + +/* + * Software event: task time clock + */ + +static void task_clock_event_update(struct perf_event *event, u64 now) { - struct pmu *pmu = NULL; - u64 event_id = event->attr.config; + u64 prev; + s64 delta; - /* - * Software events (currently) can't in general distinguish - * between user, kernel and hypervisor events. - * However, context switches and cpu migrations are considered - * to be kernel events, and page faults are never hypervisor - * events. - */ - switch (event_id) { - case PERF_COUNT_SW_CPU_CLOCK: - pmu = &perf_ops_cpu_clock; + prev = local64_xchg(&event->hw.prev_count, now); + delta = now - prev; + local64_add(delta, &event->count); +} - break; - case PERF_COUNT_SW_TASK_CLOCK: - /* - * If the user instantiates this as a per-cpu event, - * use the cpu_clock event instead. - */ - if (event->ctx->task) - pmu = &perf_ops_task_clock; - else - pmu = &perf_ops_cpu_clock; +static int task_clock_event_enable(struct perf_event *event) +{ + struct hw_perf_event *hwc = &event->hw; + u64 now; - break; - case PERF_COUNT_SW_PAGE_FAULTS: - case PERF_COUNT_SW_PAGE_FAULTS_MIN: - case PERF_COUNT_SW_PAGE_FAULTS_MAJ: - case PERF_COUNT_SW_CONTEXT_SWITCHES: - case PERF_COUNT_SW_CPU_MIGRATIONS: - case PERF_COUNT_SW_ALIGNMENT_FAULTS: - case PERF_COUNT_SW_EMULATION_FAULTS: - if (!event->parent) { - int err; - - err = swevent_hlist_get(event); - if (err) - return ERR_PTR(err); + now = event->ctx->time; - atomic_inc(&perf_swevent_enabled[event_id]); - event->destroy = sw_perf_event_destroy; + local64_set(&hwc->prev_count, now); + + perf_swevent_start_hrtimer(event); + + return 0; +} + +static void task_clock_event_disable(struct perf_event *event) +{ + perf_swevent_cancel_hrtimer(event); + task_clock_event_update(event, event->ctx->time); + +} + +static void task_clock_event_read(struct perf_event *event) +{ + u64 time; + + if (!in_nmi()) { + update_context_time(event->ctx); + time = event->ctx->time; + } else { + u64 now = perf_clock(); + u64 delta = now - event->ctx->timestamp; + time = event->ctx->time + delta; + } + + task_clock_event_update(event, time); +} + +static int task_clock_event_init(struct perf_event *event) +{ + if (event->attr.type != PERF_TYPE_SOFTWARE) + return -ENOENT; + + if (event->attr.config != PERF_COUNT_SW_TASK_CLOCK) + return -ENOENT; + + return 0; +} + +static struct pmu perf_task_clock = { + .event_init = task_clock_event_init, + .enable = task_clock_event_enable, + .disable = task_clock_event_disable, + .read = task_clock_event_read, +}; + +static LIST_HEAD(pmus); +static DEFINE_MUTEX(pmus_lock); +static struct srcu_struct pmus_srcu; + +int perf_pmu_register(struct pmu *pmu) +{ + mutex_lock(&pmus_lock); + list_add_rcu(&pmu->entry, &pmus); + mutex_unlock(&pmus_lock); + + return 0; +} + +void perf_pmu_unregister(struct pmu *pmu) +{ + mutex_lock(&pmus_lock); + list_del_rcu(&pmu->entry); + mutex_unlock(&pmus_lock); + + synchronize_srcu(&pmus_srcu); +} + +struct pmu *perf_init_event(struct perf_event *event) +{ + struct pmu *pmu = NULL; + int idx; + + idx = srcu_read_lock(&pmus_srcu); + list_for_each_entry_rcu(pmu, &pmus, entry) { + int ret = pmu->event_init(event); + if (!ret) + break; + if (ret != -ENOENT) { + pmu = ERR_PTR(ret); + break; } - pmu = &perf_ops_generic; - break; } + srcu_read_unlock(&pmus_srcu, idx); return pmu; } @@ -5092,29 +5112,8 @@ perf_event_alloc(struct perf_event_attr *attr, if (attr->inherit && (attr->read_format & PERF_FORMAT_GROUP)) goto done; - switch (attr->type) { - case PERF_TYPE_RAW: - case PERF_TYPE_HARDWARE: - case PERF_TYPE_HW_CACHE: - pmu = hw_perf_event_init(event); - break; - - case PERF_TYPE_SOFTWARE: - pmu = sw_perf_event_init(event); - break; - - case PERF_TYPE_TRACEPOINT: - pmu = tp_perf_event_init(event); - break; + pmu = perf_init_event(event); - case PERF_TYPE_BREAKPOINT: - pmu = bp_perf_event_init(event); - break; - - - default: - break; - } done: err = 0; if (!pmu) @@ -5979,22 +5978,15 @@ perf_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu) return NOTIFY_OK; } -/* - * This has to have a higher priority than migration_notifier in sched.c. - */ -static struct notifier_block __cpuinitdata perf_cpu_nb = { - .notifier_call = perf_cpu_notify, - .priority = 20, -}; - void __init perf_event_init(void) { perf_event_init_all_cpus(); - perf_cpu_notify(&perf_cpu_nb, (unsigned long)CPU_UP_PREPARE, - (void *)(long)smp_processor_id()); - perf_cpu_notify(&perf_cpu_nb, (unsigned long)CPU_ONLINE, - (void *)(long)smp_processor_id()); - register_cpu_notifier(&perf_cpu_nb); + init_srcu_struct(&pmus_srcu); + perf_pmu_register(&perf_swevent); + perf_pmu_register(&perf_cpu_clock); + perf_pmu_register(&perf_task_clock); + perf_tp_register(); + perf_cpu_notifier(perf_cpu_notify); } static ssize_t perf_show_reserve_percpu(struct sysdev_class *class, -- cgit v1.2.3 From 24cd7f54a0d47e1d5b3de29e2456bfbd2d8447b7 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 11 Jun 2010 17:32:03 +0200 Subject: perf: Reduce perf_disable() usage Since the current perf_disable() usage is only an optimization, remove it for now. This eases the removal of the __weak hw_perf_enable() interface. Signed-off-by: Peter Zijlstra Cc: paulus Cc: stephane eranian Cc: Robert Richter Cc: Will Deacon Cc: Paul Mundt Cc: Frederic Weisbecker Cc: Cyrill Gorcunov Cc: Lin Ming Cc: Yanmin Cc: Deng-Cheng Zhu Cc: David Miller Cc: Michael Cree LKML-Reference: Signed-off-by: Ingo Molnar --- arch/arm/kernel/perf_event.c | 3 +++ arch/powerpc/kernel/perf_event.c | 3 +++ arch/powerpc/kernel/perf_event_fsl_emb.c | 8 +++++-- arch/sh/kernel/perf_event.c | 11 +++++++--- arch/sparc/kernel/perf_event.c | 3 +++ arch/x86/kernel/cpu/perf_event.c | 22 ++++++++++++------- include/linux/perf_event.h | 20 ++++++++--------- kernel/perf_event.c | 37 +------------------------------- 8 files changed, 48 insertions(+), 59 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index f62f9db35db3..afc92c580d18 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -277,6 +277,8 @@ armpmu_enable(struct perf_event *event) int idx; int err = 0; + perf_disable(); + /* If we don't have a space for the counter then finish early. */ idx = armpmu->get_event_idx(cpuc, hwc); if (idx < 0) { @@ -303,6 +305,7 @@ armpmu_enable(struct perf_event *event) perf_event_update_userpage(event); out: + perf_enable(); return err; } diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index 19131b2614b9..c1408821dbc2 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -861,6 +861,7 @@ void power_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); + perf_disable(); cpuhw->group_flag |= PERF_EVENT_TXN; cpuhw->n_txn_start = cpuhw->n_events; } @@ -875,6 +876,7 @@ void power_pmu_cancel_txn(struct pmu *pmu) struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); cpuhw->group_flag &= ~PERF_EVENT_TXN; + perf_enable(); } /* @@ -901,6 +903,7 @@ int power_pmu_commit_txn(struct pmu *pmu) cpuhw->event[i]->hw.config = cpuhw->events[i]; cpuhw->group_flag &= ~PERF_EVENT_TXN; + perf_enable(); return 0; } diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c index ea6a804e43fd..9bc84a7fd901 100644 --- a/arch/powerpc/kernel/perf_event_fsl_emb.c +++ b/arch/powerpc/kernel/perf_event_fsl_emb.c @@ -262,7 +262,7 @@ static int collect_events(struct perf_event *group, int max_count, return n; } -/* perf must be disabled, context locked on entry */ +/* context locked on entry */ static int fsl_emb_pmu_enable(struct perf_event *event) { struct cpu_hw_events *cpuhw; @@ -271,6 +271,7 @@ static int fsl_emb_pmu_enable(struct perf_event *event) u64 val; int i; + perf_disable(); cpuhw = &get_cpu_var(cpu_hw_events); if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) @@ -310,15 +311,17 @@ static int fsl_emb_pmu_enable(struct perf_event *event) ret = 0; out: put_cpu_var(cpu_hw_events); + perf_enable(); return ret; } -/* perf must be disabled, context locked on entry */ +/* context locked on entry */ static void fsl_emb_pmu_disable(struct perf_event *event) { struct cpu_hw_events *cpuhw; int i = event->hw.idx; + perf_disable(); if (i < 0) goto out; @@ -346,6 +349,7 @@ static void fsl_emb_pmu_disable(struct perf_event *event) cpuhw->n_events--; out: + perf_enable(); put_cpu_var(cpu_hw_events); } diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index 8cb206597e0c..d042989ceb45 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -230,11 +230,14 @@ static int sh_pmu_enable(struct perf_event *event) struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; + int ret = -EAGAIN; + + perf_disable(); if (test_and_set_bit(idx, cpuc->used_mask)) { idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); if (idx == sh_pmu->num_events) - return -EAGAIN; + goto out; set_bit(idx, cpuc->used_mask); hwc->idx = idx; @@ -248,8 +251,10 @@ static int sh_pmu_enable(struct perf_event *event) sh_pmu->enable(hwc, idx); perf_event_update_userpage(event); - - return 0; + ret = 0; +out: + perf_enable(); + return ret; } static void sh_pmu_read(struct perf_event *event) diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index bed4327f5a7a..d0131deeeaf6 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1113,6 +1113,7 @@ static void sparc_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); + perf_disable(); cpuhw->group_flag |= PERF_EVENT_TXN; } @@ -1126,6 +1127,7 @@ static void sparc_pmu_cancel_txn(struct pmu *pmu) struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); cpuhw->group_flag &= ~PERF_EVENT_TXN; + perf_enable(); } /* @@ -1149,6 +1151,7 @@ static int sparc_pmu_commit_txn(struct pmu *pmu) return -EAGAIN; cpuc->group_flag &= ~PERF_EVENT_TXN; + perf_enable(); return 0; } diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 2c89264ee791..846070ce49c3 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -969,10 +969,11 @@ static int x86_pmu_enable(struct perf_event *event) hwc = &event->hw; + perf_disable(); n0 = cpuc->n_events; - n = collect_events(cpuc, event, false); - if (n < 0) - return n; + ret = n = collect_events(cpuc, event, false); + if (ret < 0) + goto out; /* * If group events scheduling transaction was started, @@ -980,23 +981,26 @@ static int x86_pmu_enable(struct perf_event *event) * at commit time(->commit_txn) as a whole */ if (cpuc->group_flag & PERF_EVENT_TXN) - goto out; + goto done_collect; ret = x86_pmu.schedule_events(cpuc, n, assign); if (ret) - return ret; + goto out; /* * copy new assignment, now we know it is possible * will be used by hw_perf_enable() */ memcpy(cpuc->assign, assign, n*sizeof(int)); -out: +done_collect: cpuc->n_events = n; cpuc->n_added += n - n0; cpuc->n_txn += n - n0; - return 0; + ret = 0; +out: + perf_enable(); + return ret; } static int x86_pmu_start(struct perf_event *event) @@ -1432,6 +1436,7 @@ static void x86_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + perf_disable(); cpuc->group_flag |= PERF_EVENT_TXN; cpuc->n_txn = 0; } @@ -1451,6 +1456,7 @@ static void x86_pmu_cancel_txn(struct pmu *pmu) */ cpuc->n_added -= cpuc->n_txn; cpuc->n_events -= cpuc->n_txn; + perf_enable(); } /* @@ -1480,7 +1486,7 @@ static int x86_pmu_commit_txn(struct pmu *pmu) memcpy(cpuc->assign, assign, n*sizeof(int)); cpuc->group_flag &= ~PERF_EVENT_TXN; - + perf_enable(); return 0; } diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index ab72f56eb372..243286a8ded7 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -564,26 +564,26 @@ struct pmu { struct list_head entry; /* - * Should return -ENOENT when the @event doesn't match this pmu + * Should return -ENOENT when the @event doesn't match this PMU. */ int (*event_init) (struct perf_event *event); - int (*enable) (struct perf_event *event); + int (*enable) (struct perf_event *event); void (*disable) (struct perf_event *event); - int (*start) (struct perf_event *event); + int (*start) (struct perf_event *event); void (*stop) (struct perf_event *event); void (*read) (struct perf_event *event); void (*unthrottle) (struct perf_event *event); /* - * Group events scheduling is treated as a transaction, add group - * events as a whole and perform one schedulability test. If the test - * fails, roll back the whole group + * Group events scheduling is treated as a transaction, add + * group events as a whole and perform one schedulability test. + * If the test fails, roll back the whole group */ /* - * Start the transaction, after this ->enable() doesn't need - * to do schedulability tests. + * Start the transaction, after this ->enable() doesn't need to + * do schedulability tests. */ void (*start_txn) (struct pmu *pmu); /* @@ -594,8 +594,8 @@ struct pmu { */ int (*commit_txn) (struct pmu *pmu); /* - * Will cancel the transaction, assumes ->disable() is called for - * each successfull ->enable() during the transaction. + * Will cancel the transaction, assumes ->disable() is called + * for each successfull ->enable() during the transaction. */ void (*cancel_txn) (struct pmu *pmu); }; diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 149ca18371b7..9a98ce953561 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -478,11 +478,6 @@ static void __perf_event_remove_from_context(void *info) return; raw_spin_lock(&ctx->lock); - /* - * Protect the list operation against NMI by disabling the - * events on a global level. - */ - perf_disable(); event_sched_out(event, cpuctx, ctx); @@ -498,7 +493,6 @@ static void __perf_event_remove_from_context(void *info) perf_max_events - perf_reserved_percpu); } - perf_enable(); raw_spin_unlock(&ctx->lock); } @@ -803,12 +797,6 @@ static void __perf_install_in_context(void *info) ctx->is_active = 1; update_context_time(ctx); - /* - * Protect the list operation against NMI by disabling the - * events on a global level. NOP for non NMI based events. - */ - perf_disable(); - add_event_to_ctx(event, ctx); if (event->cpu != -1 && event->cpu != smp_processor_id()) @@ -850,8 +838,6 @@ static void __perf_install_in_context(void *info) cpuctx->max_pertask--; unlock: - perf_enable(); - raw_spin_unlock(&ctx->lock); } @@ -972,12 +958,10 @@ static void __perf_event_enable(void *info) if (!group_can_go_on(event, cpuctx, 1)) { err = -EEXIST; } else { - perf_disable(); if (event == leader) err = group_sched_in(event, cpuctx, ctx); else err = event_sched_in(event, cpuctx, ctx); - perf_enable(); } if (err) { @@ -1090,9 +1074,8 @@ static void ctx_sched_out(struct perf_event_context *ctx, goto out; update_context_time(ctx); - perf_disable(); if (!ctx->nr_active) - goto out_enable; + goto out; if (event_type & EVENT_PINNED) { list_for_each_entry(event, &ctx->pinned_groups, group_entry) @@ -1103,9 +1086,6 @@ static void ctx_sched_out(struct perf_event_context *ctx, list_for_each_entry(event, &ctx->flexible_groups, group_entry) group_sched_out(event, cpuctx, ctx); } - - out_enable: - perf_enable(); out: raw_spin_unlock(&ctx->lock); } @@ -1364,8 +1344,6 @@ ctx_sched_in(struct perf_event_context *ctx, ctx->timestamp = perf_clock(); - perf_disable(); - /* * First go through the list and put on any pinned groups * in order to give them the best chance of going on. @@ -1377,7 +1355,6 @@ ctx_sched_in(struct perf_event_context *ctx, if (event_type & EVENT_FLEXIBLE) ctx_flexible_sched_in(ctx, cpuctx); - perf_enable(); out: raw_spin_unlock(&ctx->lock); } @@ -1425,8 +1402,6 @@ void perf_event_task_sched_in(struct task_struct *task) if (cpuctx->task_ctx == ctx) return; - perf_disable(); - /* * We want to keep the following priority order: * cpu pinned (that don't need to move), task pinned, @@ -1439,8 +1414,6 @@ void perf_event_task_sched_in(struct task_struct *task) ctx_sched_in(ctx, cpuctx, EVENT_FLEXIBLE); cpuctx->task_ctx = ctx; - - perf_enable(); } #define MAX_INTERRUPTS (~0ULL) @@ -1555,11 +1528,9 @@ static void perf_adjust_period(struct perf_event *event, u64 nsec, u64 count) hwc->sample_period = sample_period; if (local64_read(&hwc->period_left) > 8*sample_period) { - perf_disable(); perf_event_stop(event); local64_set(&hwc->period_left, 0); perf_event_start(event); - perf_enable(); } } @@ -1588,15 +1559,12 @@ static void perf_ctx_adjust_freq(struct perf_event_context *ctx) */ if (interrupts == MAX_INTERRUPTS) { perf_log_throttle(event, 1); - perf_disable(); event->pmu->unthrottle(event); - perf_enable(); } if (!event->attr.freq || !event->attr.sample_freq) continue; - perf_disable(); event->pmu->read(event); now = local64_read(&event->count); delta = now - hwc->freq_count_stamp; @@ -1604,7 +1572,6 @@ static void perf_ctx_adjust_freq(struct perf_event_context *ctx) if (delta > 0) perf_adjust_period(event, TICK_NSEC, delta); - perf_enable(); } raw_spin_unlock(&ctx->lock); } @@ -1647,7 +1614,6 @@ void perf_event_task_tick(struct task_struct *curr) if (!rotate) return; - perf_disable(); cpu_ctx_sched_out(cpuctx, EVENT_FLEXIBLE); if (ctx) task_ctx_sched_out(ctx, EVENT_FLEXIBLE); @@ -1659,7 +1625,6 @@ void perf_event_task_tick(struct task_struct *curr) cpu_ctx_sched_in(cpuctx, EVENT_FLEXIBLE); if (ctx) task_ctx_sched_in(curr, EVENT_FLEXIBLE); - perf_enable(); } static int event_enable_on_exec(struct perf_event *event, -- cgit v1.2.3 From 33696fc0d141bbbcb12f75b69608ea83282e3117 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 14 Jun 2010 08:49:00 +0200 Subject: perf: Per PMU disable Changes perf_disable() into perf_pmu_disable(). Signed-off-by: Peter Zijlstra Cc: paulus Cc: stephane eranian Cc: Robert Richter Cc: Will Deacon Cc: Paul Mundt Cc: Frederic Weisbecker Cc: Cyrill Gorcunov Cc: Lin Ming Cc: Yanmin Cc: Deng-Cheng Zhu Cc: David Miller Cc: Michael Cree LKML-Reference: Signed-off-by: Ingo Molnar --- arch/alpha/kernel/perf_event.c | 30 +++++++++++++------------ arch/arm/kernel/perf_event.c | 28 +++++++++++------------ arch/powerpc/kernel/perf_event.c | 24 +++++++++++--------- arch/powerpc/kernel/perf_event_fsl_emb.c | 18 ++++++++------- arch/sh/kernel/perf_event.c | 38 +++++++++++++++++--------------- arch/sparc/kernel/perf_event.c | 20 +++++++++-------- arch/x86/kernel/cpu/perf_event.c | 16 ++++++++------ include/linux/perf_event.h | 13 ++++++----- kernel/perf_event.c | 31 ++++++++++++++++---------- 9 files changed, 119 insertions(+), 99 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 19660b5c298f..3e260731f8e6 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -435,7 +435,7 @@ static int alpha_pmu_enable(struct perf_event *event) * nevertheless we disable the PMCs first to enable a potential * final PMI to occur before we disable interrupts. */ - perf_disable(); + perf_pmu_disable(event->pmu); local_irq_save(flags); /* Default to error to be returned */ @@ -456,7 +456,7 @@ static int alpha_pmu_enable(struct perf_event *event) } local_irq_restore(flags); - perf_enable(); + perf_pmu_enable(event->pmu); return ret; } @@ -474,7 +474,7 @@ static void alpha_pmu_disable(struct perf_event *event) unsigned long flags; int j; - perf_disable(); + perf_pmu_disable(event->pmu); local_irq_save(flags); for (j = 0; j < cpuc->n_events; j++) { @@ -502,7 +502,7 @@ static void alpha_pmu_disable(struct perf_event *event) } local_irq_restore(flags); - perf_enable(); + perf_pmu_enable(event->pmu); } @@ -668,18 +668,10 @@ static int alpha_pmu_event_init(struct perf_event *event) return err; } -static struct pmu pmu = { - .event_init = alpha_pmu_event_init, - .enable = alpha_pmu_enable, - .disable = alpha_pmu_disable, - .read = alpha_pmu_read, - .unthrottle = alpha_pmu_unthrottle, -}; - /* * Main entry point - enable HW performance counters. */ -void hw_perf_enable(void) +static void alpha_pmu_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -705,7 +697,7 @@ void hw_perf_enable(void) * Main entry point - disable HW performance counters. */ -void hw_perf_disable(void) +static void alpha_pmu_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -718,6 +710,16 @@ void hw_perf_disable(void) wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask); } +static struct pmu pmu = { + .pmu_enable = alpha_pmu_pmu_enable, + .pmu_disable = alpha_pmu_pmu_disable, + .event_init = alpha_pmu_event_init, + .enable = alpha_pmu_enable, + .disable = alpha_pmu_disable, + .read = alpha_pmu_read, + .unthrottle = alpha_pmu_unthrottle, +}; + /* * Main entry point - don't know when this is called but it diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index afc92c580d18..3343f3f4b973 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -277,7 +277,7 @@ armpmu_enable(struct perf_event *event) int idx; int err = 0; - perf_disable(); + perf_pmu_disable(event->pmu); /* If we don't have a space for the counter then finish early. */ idx = armpmu->get_event_idx(cpuc, hwc); @@ -305,7 +305,7 @@ armpmu_enable(struct perf_event *event) perf_event_update_userpage(event); out: - perf_enable(); + perf_pmu_enable(event->pmu); return err; } @@ -534,16 +534,7 @@ static int armpmu_event_init(struct perf_event *event) return err; } -static struct pmu pmu = { - .event_init = armpmu_event_init, - .enable = armpmu_enable, - .disable = armpmu_disable, - .unthrottle = armpmu_unthrottle, - .read = armpmu_read, -}; - -void -hw_perf_enable(void) +static void armpmu_pmu_enable(struct pmu *pmu) { /* Enable all of the perf events on hardware. */ int idx; @@ -564,13 +555,22 @@ hw_perf_enable(void) armpmu->start(); } -void -hw_perf_disable(void) +static void armpmu_pmu_disable(struct pmu *pmu) { if (armpmu) armpmu->stop(); } +static struct pmu pmu = { + .pmu_enable = armpmu_pmu_enable, + .pmu_disable= armpmu_pmu_disable, + .event_init = armpmu_event_init, + .enable = armpmu_enable, + .disable = armpmu_disable, + .unthrottle = armpmu_unthrottle, + .read = armpmu_read, +}; + /* * ARMv6 Performance counter handling code. * diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index c1408821dbc2..deb84bbcb0e6 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -517,7 +517,7 @@ static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) * Disable all events to prevent PMU interrupts and to allow * events to be added or removed. */ -void hw_perf_disable(void) +static void power_pmu_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -565,7 +565,7 @@ void hw_perf_disable(void) * If we were previously disabled and events were added, then * put the new config on the PMU. */ -void hw_perf_enable(void) +static void power_pmu_pmu_enable(struct pmu *pmu) { struct perf_event *event; struct cpu_hw_events *cpuhw; @@ -735,7 +735,7 @@ static int power_pmu_enable(struct perf_event *event) int ret = -EAGAIN; local_irq_save(flags); - perf_disable(); + perf_pmu_disable(event->pmu); /* * Add the event to the list (if there is room) @@ -769,7 +769,7 @@ nocheck: ret = 0; out: - perf_enable(); + perf_pmu_enable(event->pmu); local_irq_restore(flags); return ret; } @@ -784,7 +784,7 @@ static void power_pmu_disable(struct perf_event *event) unsigned long flags; local_irq_save(flags); - perf_disable(); + perf_pmu_disable(event->pmu); power_pmu_read(event); @@ -821,7 +821,7 @@ static void power_pmu_disable(struct perf_event *event) cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); } - perf_enable(); + perf_pmu_enable(event->pmu); local_irq_restore(flags); } @@ -837,7 +837,7 @@ static void power_pmu_unthrottle(struct perf_event *event) if (!event->hw.idx || !event->hw.sample_period) return; local_irq_save(flags); - perf_disable(); + perf_pmu_disable(event->pmu); power_pmu_read(event); left = event->hw.sample_period; event->hw.last_period = left; @@ -848,7 +848,7 @@ static void power_pmu_unthrottle(struct perf_event *event) local64_set(&event->hw.prev_count, val); local64_set(&event->hw.period_left, left); perf_event_update_userpage(event); - perf_enable(); + perf_pmu_enable(event->pmu); local_irq_restore(flags); } @@ -861,7 +861,7 @@ void power_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); - perf_disable(); + perf_pmu_disable(pmu); cpuhw->group_flag |= PERF_EVENT_TXN; cpuhw->n_txn_start = cpuhw->n_events; } @@ -876,7 +876,7 @@ void power_pmu_cancel_txn(struct pmu *pmu) struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); cpuhw->group_flag &= ~PERF_EVENT_TXN; - perf_enable(); + perf_pmu_enable(pmu); } /* @@ -903,7 +903,7 @@ int power_pmu_commit_txn(struct pmu *pmu) cpuhw->event[i]->hw.config = cpuhw->events[i]; cpuhw->group_flag &= ~PERF_EVENT_TXN; - perf_enable(); + perf_pmu_enable(pmu); return 0; } @@ -1131,6 +1131,8 @@ static int power_pmu_event_init(struct perf_event *event) } struct pmu power_pmu = { + .pmu_enable = power_pmu_pmu_enable, + .pmu_disable = power_pmu_pmu_disable, .event_init = power_pmu_event_init, .enable = power_pmu_enable, .disable = power_pmu_disable, diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c index 9bc84a7fd901..84b1974c628f 100644 --- a/arch/powerpc/kernel/perf_event_fsl_emb.c +++ b/arch/powerpc/kernel/perf_event_fsl_emb.c @@ -177,7 +177,7 @@ static void fsl_emb_pmu_read(struct perf_event *event) * Disable all events to prevent PMU interrupts and to allow * events to be added or removed. */ -void hw_perf_disable(void) +static void fsl_emb_pmu_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -216,7 +216,7 @@ void hw_perf_disable(void) * If we were previously disabled and events were added, then * put the new config on the PMU. */ -void hw_perf_enable(void) +static void fsl_emb_pmu_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -271,7 +271,7 @@ static int fsl_emb_pmu_enable(struct perf_event *event) u64 val; int i; - perf_disable(); + perf_pmu_disable(event->pmu); cpuhw = &get_cpu_var(cpu_hw_events); if (event->hw.config & FSL_EMB_EVENT_RESTRICTED) @@ -311,7 +311,7 @@ static int fsl_emb_pmu_enable(struct perf_event *event) ret = 0; out: put_cpu_var(cpu_hw_events); - perf_enable(); + perf_pmu_enable(event->pmu); return ret; } @@ -321,7 +321,7 @@ static void fsl_emb_pmu_disable(struct perf_event *event) struct cpu_hw_events *cpuhw; int i = event->hw.idx; - perf_disable(); + perf_pmu_disable(event->pmu); if (i < 0) goto out; @@ -349,7 +349,7 @@ static void fsl_emb_pmu_disable(struct perf_event *event) cpuhw->n_events--; out: - perf_enable(); + perf_pmu_enable(event->pmu); put_cpu_var(cpu_hw_events); } @@ -367,7 +367,7 @@ static void fsl_emb_pmu_unthrottle(struct perf_event *event) if (event->hw.idx < 0 || !event->hw.sample_period) return; local_irq_save(flags); - perf_disable(); + perf_pmu_disable(event->pmu); fsl_emb_pmu_read(event); left = event->hw.sample_period; event->hw.last_period = left; @@ -378,7 +378,7 @@ static void fsl_emb_pmu_unthrottle(struct perf_event *event) local64_set(&event->hw.prev_count, val); local64_set(&event->hw.period_left, left); perf_event_update_userpage(event); - perf_enable(); + perf_pmu_enable(event->pmu); local_irq_restore(flags); } @@ -524,6 +524,8 @@ static int fsl_emb_pmu_event_init(struct perf_event *event) } static struct pmu fsl_emb_pmu = { + .pmu_enable = fsl_emb_pmu_pmu_enable, + .pmu_disable = fsl_emb_pmu_pmu_disable, .event_init = fsl_emb_pmu_event_init, .enable = fsl_emb_pmu_enable, .disable = fsl_emb_pmu_disable, diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index d042989ceb45..4bbe19058a58 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -232,7 +232,7 @@ static int sh_pmu_enable(struct perf_event *event) int idx = hwc->idx; int ret = -EAGAIN; - perf_disable(); + perf_pmu_disable(event->pmu); if (test_and_set_bit(idx, cpuc->used_mask)) { idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); @@ -253,7 +253,7 @@ static int sh_pmu_enable(struct perf_event *event) perf_event_update_userpage(event); ret = 0; out: - perf_enable(); + perf_pmu_enable(event->pmu); return ret; } @@ -285,7 +285,25 @@ static int sh_pmu_event_init(struct perf_event *event) return err; } +static void sh_pmu_pmu_enable(struct pmu *pmu) +{ + if (!sh_pmu_initialized()) + return; + + sh_pmu->enable_all(); +} + +static void sh_pmu_pmu_disable(struct pmu *pmu) +{ + if (!sh_pmu_initialized()) + return; + + sh_pmu->disable_all(); +} + static struct pmu pmu = { + .pmu_enable = sh_pmu_pmu_enable, + .pmu_disable = sh_pmu_pmu_disable, .event_init = sh_pmu_event_init, .enable = sh_pmu_enable, .disable = sh_pmu_disable, @@ -316,22 +334,6 @@ sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) return NOTIFY_OK; } -void hw_perf_enable(void) -{ - if (!sh_pmu_initialized()) - return; - - sh_pmu->enable_all(); -} - -void hw_perf_disable(void) -{ - if (!sh_pmu_initialized()) - return; - - sh_pmu->disable_all(); -} - int __cpuinit register_sh_pmu(struct sh_pmu *pmu) { if (sh_pmu) diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index d0131deeeaf6..37cae676536c 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -664,7 +664,7 @@ out: return pcr; } -void hw_perf_enable(void) +static void sparc_pmu_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); u64 pcr; @@ -691,7 +691,7 @@ void hw_perf_enable(void) pcr_ops->write(cpuc->pcr); } -void hw_perf_disable(void) +static void sparc_pmu_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); u64 val; @@ -718,7 +718,7 @@ static void sparc_pmu_disable(struct perf_event *event) int i; local_irq_save(flags); - perf_disable(); + perf_pmu_disable(event->pmu); for (i = 0; i < cpuc->n_events; i++) { if (event == cpuc->event[i]) { @@ -748,7 +748,7 @@ static void sparc_pmu_disable(struct perf_event *event) } } - perf_enable(); + perf_pmu_enable(event->pmu); local_irq_restore(flags); } @@ -991,7 +991,7 @@ static int sparc_pmu_enable(struct perf_event *event) unsigned long flags; local_irq_save(flags); - perf_disable(); + perf_pmu_disable(event->pmu); n0 = cpuc->n_events; if (n0 >= perf_max_events) @@ -1020,7 +1020,7 @@ nocheck: ret = 0; out: - perf_enable(); + perf_pmu_enable(event->pmu); local_irq_restore(flags); return ret; } @@ -1113,7 +1113,7 @@ static void sparc_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); - perf_disable(); + perf_pmu_disable(pmu); cpuhw->group_flag |= PERF_EVENT_TXN; } @@ -1127,7 +1127,7 @@ static void sparc_pmu_cancel_txn(struct pmu *pmu) struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); cpuhw->group_flag &= ~PERF_EVENT_TXN; - perf_enable(); + perf_pmu_enable(pmu); } /* @@ -1151,11 +1151,13 @@ static int sparc_pmu_commit_txn(struct pmu *pmu) return -EAGAIN; cpuc->group_flag &= ~PERF_EVENT_TXN; - perf_enable(); + perf_pmu_enable(pmu); return 0; } static struct pmu pmu = { + .pmu_enable = sparc_pmu_pmu_enable, + .pmu_disable = sparc_pmu_pmu_disable, .event_init = sparc_pmu_event_init, .enable = sparc_pmu_enable, .disable = sparc_pmu_disable, diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 846070ce49c3..79705ac45019 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -583,7 +583,7 @@ static void x86_pmu_disable_all(void) } } -void hw_perf_disable(void) +static void x86_pmu_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -803,7 +803,7 @@ static inline int match_prev_assignment(struct hw_perf_event *hwc, static int x86_pmu_start(struct perf_event *event); static void x86_pmu_stop(struct perf_event *event); -void hw_perf_enable(void) +static void x86_pmu_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct perf_event *event; @@ -969,7 +969,7 @@ static int x86_pmu_enable(struct perf_event *event) hwc = &event->hw; - perf_disable(); + perf_pmu_disable(event->pmu); n0 = cpuc->n_events; ret = n = collect_events(cpuc, event, false); if (ret < 0) @@ -999,7 +999,7 @@ done_collect: ret = 0; out: - perf_enable(); + perf_pmu_enable(event->pmu); return ret; } @@ -1436,7 +1436,7 @@ static void x86_pmu_start_txn(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - perf_disable(); + perf_pmu_disable(pmu); cpuc->group_flag |= PERF_EVENT_TXN; cpuc->n_txn = 0; } @@ -1456,7 +1456,7 @@ static void x86_pmu_cancel_txn(struct pmu *pmu) */ cpuc->n_added -= cpuc->n_txn; cpuc->n_events -= cpuc->n_txn; - perf_enable(); + perf_pmu_enable(pmu); } /* @@ -1486,7 +1486,7 @@ static int x86_pmu_commit_txn(struct pmu *pmu) memcpy(cpuc->assign, assign, n*sizeof(int)); cpuc->group_flag &= ~PERF_EVENT_TXN; - perf_enable(); + perf_pmu_enable(pmu); return 0; } @@ -1605,6 +1605,8 @@ int x86_pmu_event_init(struct perf_event *event) } static struct pmu pmu = { + .pmu_enable = x86_pmu_pmu_enable, + .pmu_disable = x86_pmu_pmu_disable, .event_init = x86_pmu_event_init, .enable = x86_pmu_enable, .disable = x86_pmu_disable, diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 243286a8ded7..6abf103fb7f8 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -563,6 +563,11 @@ struct perf_event; struct pmu { struct list_head entry; + int *pmu_disable_count; + + void (*pmu_enable) (struct pmu *pmu); + void (*pmu_disable) (struct pmu *pmu); + /* * Should return -ENOENT when the @event doesn't match this PMU. */ @@ -868,10 +873,8 @@ extern void perf_event_free_task(struct task_struct *task); extern void set_perf_event_pending(void); extern void perf_event_do_pending(void); extern void perf_event_print_debug(void); -extern void __perf_disable(void); -extern bool __perf_enable(void); -extern void perf_disable(void); -extern void perf_enable(void); +extern void perf_pmu_disable(struct pmu *pmu); +extern void perf_pmu_enable(struct pmu *pmu); extern int perf_event_task_disable(void); extern int perf_event_task_enable(void); extern void perf_event_update_userpage(struct perf_event *event); @@ -1056,8 +1059,6 @@ static inline void perf_event_exit_task(struct task_struct *child) { } static inline void perf_event_free_task(struct task_struct *task) { } static inline void perf_event_do_pending(void) { } static inline void perf_event_print_debug(void) { } -static inline void perf_disable(void) { } -static inline void perf_enable(void) { } static inline int perf_event_task_disable(void) { return -EINVAL; } static inline int perf_event_task_enable(void) { return -EINVAL; } diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 9a98ce953561..5ed0c06765bb 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -71,23 +71,20 @@ static atomic64_t perf_event_id; */ static DEFINE_SPINLOCK(perf_resource_lock); -void __weak hw_perf_disable(void) { barrier(); } -void __weak hw_perf_enable(void) { barrier(); } - void __weak perf_event_print_debug(void) { } -static DEFINE_PER_CPU(int, perf_disable_count); - -void perf_disable(void) +void perf_pmu_disable(struct pmu *pmu) { - if (!__get_cpu_var(perf_disable_count)++) - hw_perf_disable(); + int *count = this_cpu_ptr(pmu->pmu_disable_count); + if (!(*count)++) + pmu->pmu_disable(pmu); } -void perf_enable(void) +void perf_pmu_enable(struct pmu *pmu) { - if (!--__get_cpu_var(perf_disable_count)) - hw_perf_enable(); + int *count = this_cpu_ptr(pmu->pmu_disable_count); + if (!--(*count)) + pmu->pmu_enable(pmu); } static void get_ctx(struct perf_event_context *ctx) @@ -4970,11 +4967,19 @@ static struct srcu_struct pmus_srcu; int perf_pmu_register(struct pmu *pmu) { + int ret; + mutex_lock(&pmus_lock); + ret = -ENOMEM; + pmu->pmu_disable_count = alloc_percpu(int); + if (!pmu->pmu_disable_count) + goto unlock; list_add_rcu(&pmu->entry, &pmus); + ret = 0; +unlock: mutex_unlock(&pmus_lock); - return 0; + return ret; } void perf_pmu_unregister(struct pmu *pmu) @@ -4984,6 +4989,8 @@ void perf_pmu_unregister(struct pmu *pmu) mutex_unlock(&pmus_lock); synchronize_srcu(&pmus_srcu); + + free_percpu(pmu->pmu_disable_count); } struct pmu *perf_init_event(struct perf_event *event) -- cgit v1.2.3 From a4eaf7f14675cb512d69f0c928055e73d0c6d252 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 16 Jun 2010 14:37:10 +0200 Subject: perf: Rework the PMU methods Replace pmu::{enable,disable,start,stop,unthrottle} with pmu::{add,del,start,stop}, all of which take a flags argument. The new interface extends the capability to stop a counter while keeping it scheduled on the PMU. We replace the throttled state with the generic stopped state. This also allows us to efficiently stop/start counters over certain code paths (like IRQ handlers). It also allows scheduling a counter without it starting, allowing for a generic frozen state (useful for rotating stopped counters). The stopped state is implemented in two different ways, depending on how the architecture implemented the throttled state: 1) We disable the counter: a) the pmu has per-counter enable bits, we flip that b) we program a NOP event, preserving the counter state 2) We store the counter state and ignore all read/overflow events Signed-off-by: Peter Zijlstra Cc: paulus Cc: stephane eranian Cc: Robert Richter Cc: Will Deacon Cc: Paul Mundt Cc: Frederic Weisbecker Cc: Cyrill Gorcunov Cc: Lin Ming Cc: Yanmin Cc: Deng-Cheng Zhu Cc: David Miller Cc: Michael Cree LKML-Reference: Signed-off-by: Ingo Molnar --- arch/alpha/kernel/perf_event.c | 71 +++++++++++---- arch/arm/kernel/perf_event.c | 96 ++++++++++++-------- arch/powerpc/kernel/perf_event.c | 105 ++++++++++++++-------- arch/powerpc/kernel/perf_event_fsl_emb.c | 107 ++++++++++++++--------- arch/sh/kernel/perf_event.c | 75 +++++++++++----- arch/sparc/kernel/perf_event.c | 109 ++++++++++++++--------- arch/x86/kernel/cpu/perf_event.c | 106 ++++++++++++---------- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- arch/x86/kernel/cpu/perf_event_intel_ds.c | 2 +- include/linux/ftrace_event.h | 4 +- include/linux/perf_event.h | 54 +++++++++--- kernel/hw_breakpoint.c | 29 ++++++- kernel/perf_event.c | 140 +++++++++++++++--------------- kernel/trace/trace_event_perf.c | 7 +- 14 files changed, 576 insertions(+), 331 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 3e260731f8e6..380ef02d557a 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -307,7 +307,7 @@ again: new_raw_count) != prev_raw_count) goto again; - delta = (new_raw_count - (prev_raw_count & alpha_pmu->pmc_count_mask[idx])) + ovf; + delta = (new_raw_count - (prev_raw_count & alpha_pmu->pmc_count_mask[idx])) + ovf; /* It is possible on very rare occasions that the PMC has overflowed * but the interrupt is yet to come. Detect and fix this situation. @@ -402,14 +402,13 @@ static void maybe_change_configuration(struct cpu_hw_events *cpuc) struct hw_perf_event *hwc = &pe->hw; int idx = hwc->idx; - if (cpuc->current_idx[j] != PMC_NO_INDEX) { - cpuc->idx_mask |= (1<current_idx[j]); - continue; + if (cpuc->current_idx[j] == PMC_NO_INDEX) { + alpha_perf_event_set_period(pe, hwc, idx); + cpuc->current_idx[j] = idx; } - alpha_perf_event_set_period(pe, hwc, idx); - cpuc->current_idx[j] = idx; - cpuc->idx_mask |= (1<current_idx[j]); + if (!(hwc->state & PERF_HES_STOPPED)) + cpuc->idx_mask |= (1<current_idx[j]); } cpuc->config = cpuc->event[0]->hw.config_base; } @@ -420,7 +419,7 @@ static void maybe_change_configuration(struct cpu_hw_events *cpuc) * - this function is called from outside this module via the pmu struct * returned from perf event initialisation. */ -static int alpha_pmu_enable(struct perf_event *event) +static int alpha_pmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int n0; @@ -455,6 +454,10 @@ static int alpha_pmu_enable(struct perf_event *event) } } + hwc->state = PERF_HES_UPTODATE; + if (!(flags & PERF_EF_START)) + hwc->state |= PERF_HES_STOPPED; + local_irq_restore(flags); perf_pmu_enable(event->pmu); @@ -467,7 +470,7 @@ static int alpha_pmu_enable(struct perf_event *event) * - this function is called from outside this module via the pmu struct * returned from perf event initialisation. */ -static void alpha_pmu_disable(struct perf_event *event) +static void alpha_pmu_del(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; @@ -514,13 +517,44 @@ static void alpha_pmu_read(struct perf_event *event) } -static void alpha_pmu_unthrottle(struct perf_event *event) +static void alpha_pmu_stop(struct perf_event *event, int flags) { struct hw_perf_event *hwc = &event->hw; struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + if (!(hwc->state & PERF_HES_STOPPED)) { + cpuc->idx_mask &= !(1UL<idx); + hwc->state |= PERF_HES_STOPPED; + } + + if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { + alpha_perf_event_update(event, hwc, hwc->idx, 0); + hwc->state |= PERF_HES_UPTODATE; + } + + if (cpuc->enabled) + wrperfmon(PERFMON_CMD_ENABLE, (1UL<idx)); +} + + +static void alpha_pmu_start(struct perf_event *event, int flags) +{ + struct hw_perf_event *hwc = &event->hw; + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + + if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED))) + return; + + if (flags & PERF_EF_RELOAD) { + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); + alpha_perf_event_set_period(event, hwc, hwc->idx); + } + + hwc->state = 0; + cpuc->idx_mask |= 1UL<idx; - wrperfmon(PERFMON_CMD_ENABLE, (1UL<idx)); + if (cpuc->enabled) + wrperfmon(PERFMON_CMD_ENABLE, (1UL<idx)); } @@ -671,7 +705,7 @@ static int alpha_pmu_event_init(struct perf_event *event) /* * Main entry point - enable HW performance counters. */ -static void alpha_pmu_pmu_enable(struct pmu *pmu) +static void alpha_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -697,7 +731,7 @@ static void alpha_pmu_pmu_enable(struct pmu *pmu) * Main entry point - disable HW performance counters. */ -static void alpha_pmu_pmu_disable(struct pmu *pmu) +static void alpha_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -711,13 +745,14 @@ static void alpha_pmu_pmu_disable(struct pmu *pmu) } static struct pmu pmu = { - .pmu_enable = alpha_pmu_pmu_enable, - .pmu_disable = alpha_pmu_pmu_disable, + .pmu_enable = alpha_pmu_enable, + .pmu_disable = alpha_pmu_disable, .event_init = alpha_pmu_event_init, - .enable = alpha_pmu_enable, - .disable = alpha_pmu_disable, + .add = alpha_pmu_add, + .del = alpha_pmu_del, + .start = alpha_pmu_start, + .stop = alpha_pmu_stop, .read = alpha_pmu_read, - .unthrottle = alpha_pmu_unthrottle, }; diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 3343f3f4b973..448cfa6b3ef0 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -221,46 +221,56 @@ again: } static void -armpmu_disable(struct perf_event *event) +armpmu_read(struct perf_event *event) { - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - WARN_ON(idx < 0); - - clear_bit(idx, cpuc->active_mask); - armpmu->disable(hwc, idx); - - barrier(); - armpmu_event_update(event, hwc, idx); - cpuc->events[idx] = NULL; - clear_bit(idx, cpuc->used_mask); + /* Don't read disabled counters! */ + if (hwc->idx < 0) + return; - perf_event_update_userpage(event); + armpmu_event_update(event, hwc, hwc->idx); } static void -armpmu_read(struct perf_event *event) +armpmu_stop(struct perf_event *event, int flags) { struct hw_perf_event *hwc = &event->hw; - /* Don't read disabled counters! */ - if (hwc->idx < 0) + if (!armpmu) return; - armpmu_event_update(event, hwc, hwc->idx); + /* + * ARM pmu always has to update the counter, so ignore + * PERF_EF_UPDATE, see comments in armpmu_start(). + */ + if (!(hwc->state & PERF_HES_STOPPED)) { + armpmu->disable(hwc, hwc->idx); + barrier(); /* why? */ + armpmu_event_update(event, hwc, hwc->idx); + hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; + } } static void -armpmu_unthrottle(struct perf_event *event) +armpmu_start(struct perf_event *event, int flags) { struct hw_perf_event *hwc = &event->hw; + if (!armpmu) + return; + + /* + * ARM pmu always has to reprogram the period, so ignore + * PERF_EF_RELOAD, see the comment below. + */ + if (flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); + + hwc->state = 0; /* * Set the period again. Some counters can't be stopped, so when we - * were throttled we simply disabled the IRQ source and the counter + * were stopped we simply disabled the IRQ source and the counter * may have been left counting. If we don't do this step then we may * get an interrupt too soon or *way* too late if the overflow has * happened since disabling. @@ -269,8 +279,25 @@ armpmu_unthrottle(struct perf_event *event) armpmu->enable(hwc, hwc->idx); } +static void +armpmu_del(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; + + WARN_ON(idx < 0); + + clear_bit(idx, cpuc->active_mask); + armpmu_stop(event, PERF_EF_UPDATE); + cpuc->events[idx] = NULL; + clear_bit(idx, cpuc->used_mask); + + perf_event_update_userpage(event); +} + static int -armpmu_enable(struct perf_event *event) +armpmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; @@ -295,11 +322,9 @@ armpmu_enable(struct perf_event *event) cpuc->events[idx] = event; set_bit(idx, cpuc->active_mask); - /* Set the period for the event. */ - armpmu_event_set_period(event, hwc, idx); - - /* Enable the event. */ - armpmu->enable(hwc, idx); + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + if (flags & PERF_EF_START) + armpmu_start(event, PERF_EF_RELOAD); /* Propagate our changes to the userspace mapping. */ perf_event_update_userpage(event); @@ -534,7 +559,7 @@ static int armpmu_event_init(struct perf_event *event) return err; } -static void armpmu_pmu_enable(struct pmu *pmu) +static void armpmu_enable(struct pmu *pmu) { /* Enable all of the perf events on hardware. */ int idx; @@ -555,20 +580,21 @@ static void armpmu_pmu_enable(struct pmu *pmu) armpmu->start(); } -static void armpmu_pmu_disable(struct pmu *pmu) +static void armpmu_disable(struct pmu *pmu) { if (armpmu) armpmu->stop(); } static struct pmu pmu = { - .pmu_enable = armpmu_pmu_enable, - .pmu_disable= armpmu_pmu_disable, - .event_init = armpmu_event_init, - .enable = armpmu_enable, - .disable = armpmu_disable, - .unthrottle = armpmu_unthrottle, - .read = armpmu_read, + .pmu_enable = armpmu_enable, + .pmu_disable = armpmu_disable, + .event_init = armpmu_event_init, + .add = armpmu_add, + .del = armpmu_del, + .start = armpmu_start, + .stop = armpmu_stop, + .read = armpmu_read, }; /* diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c index deb84bbcb0e6..9cb4924b6c07 100644 --- a/arch/powerpc/kernel/perf_event.c +++ b/arch/powerpc/kernel/perf_event.c @@ -402,6 +402,9 @@ static void power_pmu_read(struct perf_event *event) { s64 val, delta, prev; + if (event->hw.state & PERF_HES_STOPPED) + return; + if (!event->hw.idx) return; /* @@ -517,7 +520,7 @@ static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) * Disable all events to prevent PMU interrupts and to allow * events to be added or removed. */ -static void power_pmu_pmu_disable(struct pmu *pmu) +static void power_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -565,7 +568,7 @@ static void power_pmu_pmu_disable(struct pmu *pmu) * If we were previously disabled and events were added, then * put the new config on the PMU. */ -static void power_pmu_pmu_enable(struct pmu *pmu) +static void power_pmu_enable(struct pmu *pmu) { struct perf_event *event; struct cpu_hw_events *cpuhw; @@ -672,6 +675,8 @@ static void power_pmu_pmu_enable(struct pmu *pmu) } local64_set(&event->hw.prev_count, val); event->hw.idx = idx; + if (event->hw.state & PERF_HES_STOPPED) + val = 0; write_pmc(idx, val); perf_event_update_userpage(event); } @@ -727,7 +732,7 @@ static int collect_events(struct perf_event *group, int max_count, * re-enable the PMU in order to get hw_perf_enable to do the * actual work of reconfiguring the PMU. */ -static int power_pmu_enable(struct perf_event *event) +static int power_pmu_add(struct perf_event *event, int ef_flags) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -749,6 +754,9 @@ static int power_pmu_enable(struct perf_event *event) cpuhw->events[n0] = event->hw.config; cpuhw->flags[n0] = event->hw.event_base; + if (!(ef_flags & PERF_EF_START)) + event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + /* * If group events scheduling transaction was started, * skip the schedulability test here, it will be peformed @@ -777,7 +785,7 @@ nocheck: /* * Remove a event from the PMU. */ -static void power_pmu_disable(struct perf_event *event) +static void power_pmu_del(struct perf_event *event, int ef_flags) { struct cpu_hw_events *cpuhw; long i; @@ -826,27 +834,53 @@ static void power_pmu_disable(struct perf_event *event) } /* - * Re-enable interrupts on a event after they were throttled - * because they were coming too fast. + * POWER-PMU does not support disabling individual counters, hence + * program their cycle counter to their max value and ignore the interrupts. */ -static void power_pmu_unthrottle(struct perf_event *event) + +static void power_pmu_start(struct perf_event *event, int ef_flags) { - s64 val, left; unsigned long flags; + s64 left; if (!event->hw.idx || !event->hw.sample_period) return; + + if (!(event->hw.state & PERF_HES_STOPPED)) + return; + + if (ef_flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); + + local_irq_save(flags); + perf_pmu_disable(event->pmu); + + event->hw.state = 0; + left = local64_read(&event->hw.period_left); + write_pmc(event->hw.idx, left); + + perf_event_update_userpage(event); + perf_pmu_enable(event->pmu); + local_irq_restore(flags); +} + +static void power_pmu_stop(struct perf_event *event, int ef_flags) +{ + unsigned long flags; + + if (!event->hw.idx || !event->hw.sample_period) + return; + + if (event->hw.state & PERF_HES_STOPPED) + return; + local_irq_save(flags); perf_pmu_disable(event->pmu); + power_pmu_read(event); - left = event->hw.sample_period; - event->hw.last_period = left; - val = 0; - if (left < 0x80000000L) - val = 0x80000000L - left; - write_pmc(event->hw.idx, val); - local64_set(&event->hw.prev_count, val); - local64_set(&event->hw.period_left, left); + event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; + write_pmc(event->hw.idx, 0); + perf_event_update_userpage(event); perf_pmu_enable(event->pmu); local_irq_restore(flags); @@ -1131,13 +1165,14 @@ static int power_pmu_event_init(struct perf_event *event) } struct pmu power_pmu = { - .pmu_enable = power_pmu_pmu_enable, - .pmu_disable = power_pmu_pmu_disable, + .pmu_enable = power_pmu_enable, + .pmu_disable = power_pmu_disable, .event_init = power_pmu_event_init, - .enable = power_pmu_enable, - .disable = power_pmu_disable, + .add = power_pmu_add, + .del = power_pmu_del, + .start = power_pmu_start, + .stop = power_pmu_stop, .read = power_pmu_read, - .unthrottle = power_pmu_unthrottle, .start_txn = power_pmu_start_txn, .cancel_txn = power_pmu_cancel_txn, .commit_txn = power_pmu_commit_txn, @@ -1155,6 +1190,11 @@ static void record_and_restart(struct perf_event *event, unsigned long val, s64 prev, delta, left; int record = 0; + if (event->hw.state & PERF_HES_STOPPED) { + write_pmc(event->hw.idx, 0); + return; + } + /* we don't have to worry about interrupts here */ prev = local64_read(&event->hw.prev_count); delta = (val - prev) & 0xfffffffful; @@ -1177,6 +1217,11 @@ static void record_and_restart(struct perf_event *event, unsigned long val, val = 0x80000000LL - left; } + write_pmc(event->hw.idx, val); + local64_set(&event->hw.prev_count, val); + local64_set(&event->hw.period_left, left); + perf_event_update_userpage(event); + /* * Finally record data if requested. */ @@ -1189,23 +1234,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val, if (event->attr.sample_type & PERF_SAMPLE_ADDR) perf_get_data_addr(regs, &data.addr); - if (perf_event_overflow(event, nmi, &data, regs)) { - /* - * Interrupts are coming too fast - throttle them - * by setting the event to 0, so it will be - * at least 2^30 cycles until the next interrupt - * (assuming each event counts at most 2 counts - * per cycle). - */ - val = 0; - left = ~0ULL >> 1; - } + if (perf_event_overflow(event, nmi, &data, regs)) + power_pmu_stop(event, 0); } - - write_pmc(event->hw.idx, val); - local64_set(&event->hw.prev_count, val); - local64_set(&event->hw.period_left, left); - perf_event_update_userpage(event); } /* diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c index 84b1974c628f..7ecca59ddf77 100644 --- a/arch/powerpc/kernel/perf_event_fsl_emb.c +++ b/arch/powerpc/kernel/perf_event_fsl_emb.c @@ -156,6 +156,9 @@ static void fsl_emb_pmu_read(struct perf_event *event) { s64 val, delta, prev; + if (event->hw.state & PERF_HES_STOPPED) + return; + /* * Performance monitor interrupts come even when interrupts * are soft-disabled, as long as interrupts are hard-enabled. @@ -177,7 +180,7 @@ static void fsl_emb_pmu_read(struct perf_event *event) * Disable all events to prevent PMU interrupts and to allow * events to be added or removed. */ -static void fsl_emb_pmu_pmu_disable(struct pmu *pmu) +static void fsl_emb_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -216,7 +219,7 @@ static void fsl_emb_pmu_pmu_disable(struct pmu *pmu) * If we were previously disabled and events were added, then * put the new config on the PMU. */ -static void fsl_emb_pmu_pmu_enable(struct pmu *pmu) +static void fsl_emb_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuhw; unsigned long flags; @@ -263,7 +266,7 @@ static int collect_events(struct perf_event *group, int max_count, } /* context locked on entry */ -static int fsl_emb_pmu_enable(struct perf_event *event) +static int fsl_emb_pmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuhw; int ret = -EAGAIN; @@ -302,6 +305,12 @@ static int fsl_emb_pmu_enable(struct perf_event *event) val = 0x80000000L - left; } local64_set(&event->hw.prev_count, val); + + if (!(flags & PERF_EF_START)) { + event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; + val = 0; + } + write_pmc(i, val); perf_event_update_userpage(event); @@ -316,7 +325,7 @@ static int fsl_emb_pmu_enable(struct perf_event *event) } /* context locked on entry */ -static void fsl_emb_pmu_disable(struct perf_event *event) +static void fsl_emb_pmu_del(struct perf_event *event, int flags) { struct cpu_hw_events *cpuhw; int i = event->hw.idx; @@ -353,30 +362,49 @@ static void fsl_emb_pmu_disable(struct perf_event *event) put_cpu_var(cpu_hw_events); } -/* - * Re-enable interrupts on a event after they were throttled - * because they were coming too fast. - * - * Context is locked on entry, but perf is not disabled. - */ -static void fsl_emb_pmu_unthrottle(struct perf_event *event) +static void fsl_emb_pmu_start(struct perf_event *event, int ef_flags) +{ + unsigned long flags; + s64 left; + + if (event->hw.idx < 0 || !event->hw.sample_period) + return; + + if (!(event->hw.state & PERF_HES_STOPPED)) + return; + + if (ef_flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); + + local_irq_save(flags); + perf_pmu_disable(event->pmu); + + event->hw.state = 0; + left = local64_read(&event->hw.period_left); + write_pmc(event->hw.idx, left); + + perf_event_update_userpage(event); + perf_pmu_enable(event->pmu); + local_irq_restore(flags); +} + +static void fsl_emb_pmu_stop(struct perf_event *event, int ef_flags) { - s64 val, left; unsigned long flags; if (event->hw.idx < 0 || !event->hw.sample_period) return; + + if (event->hw.state & PERF_HES_STOPPED) + return; + local_irq_save(flags); perf_pmu_disable(event->pmu); + fsl_emb_pmu_read(event); - left = event->hw.sample_period; - event->hw.last_period = left; - val = 0; - if (left < 0x80000000L) - val = 0x80000000L - left; - write_pmc(event->hw.idx, val); - local64_set(&event->hw.prev_count, val); - local64_set(&event->hw.period_left, left); + event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; + write_pmc(event->hw.idx, 0); + perf_event_update_userpage(event); perf_pmu_enable(event->pmu); local_irq_restore(flags); @@ -524,13 +552,14 @@ static int fsl_emb_pmu_event_init(struct perf_event *event) } static struct pmu fsl_emb_pmu = { - .pmu_enable = fsl_emb_pmu_pmu_enable, - .pmu_disable = fsl_emb_pmu_pmu_disable, + .pmu_enable = fsl_emb_pmu_enable, + .pmu_disable = fsl_emb_pmu_disable, .event_init = fsl_emb_pmu_event_init, - .enable = fsl_emb_pmu_enable, - .disable = fsl_emb_pmu_disable, + .add = fsl_emb_pmu_add, + .del = fsl_emb_pmu_del, + .start = fsl_emb_pmu_start, + .stop = fsl_emb_pmu_stop, .read = fsl_emb_pmu_read, - .unthrottle = fsl_emb_pmu_unthrottle, }; /* @@ -545,6 +574,11 @@ static void record_and_restart(struct perf_event *event, unsigned long val, s64 prev, delta, left; int record = 0; + if (event->hw.state & PERF_HES_STOPPED) { + write_pmc(event->hw.idx, 0); + return; + } + /* we don't have to worry about interrupts here */ prev = local64_read(&event->hw.prev_count); delta = (val - prev) & 0xfffffffful; @@ -567,6 +601,11 @@ static void record_and_restart(struct perf_event *event, unsigned long val, val = 0x80000000LL - left; } + write_pmc(event->hw.idx, val); + local64_set(&event->hw.prev_count, val); + local64_set(&event->hw.period_left, left); + perf_event_update_userpage(event); + /* * Finally record data if requested. */ @@ -576,23 +615,9 @@ static void record_and_restart(struct perf_event *event, unsigned long val, perf_sample_data_init(&data, 0); data.period = event->hw.last_period; - if (perf_event_overflow(event, nmi, &data, regs)) { - /* - * Interrupts are coming too fast - throttle them - * by setting the event to 0, so it will be - * at least 2^30 cycles until the next interrupt - * (assuming each event counts at most 2 counts - * per cycle). - */ - val = 0; - left = ~0ULL >> 1; - } + if (perf_event_overflow(event, nmi, &data, regs)) + fsl_emb_pmu_stop(event, 0); } - - write_pmc(event->hw.idx, val); - local64_set(&event->hw.prev_count, val); - local64_set(&event->hw.period_left, left); - perf_event_update_userpage(event); } static void perf_event_interrupt(struct pt_regs *regs) diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index 4bbe19058a58..cf39c4873468 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -206,26 +206,52 @@ again: local64_add(delta, &event->count); } -static void sh_pmu_disable(struct perf_event *event) +static void sh_pmu_stop(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; - clear_bit(idx, cpuc->active_mask); - sh_pmu->disable(hwc, idx); + if (!(event->hw.state & PERF_HES_STOPPED)) { + sh_pmu->disable(hwc, idx); + cpuc->events[idx] = NULL; + event->hw.state |= PERF_HES_STOPPED; + } - barrier(); + if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) { + sh_perf_event_update(event, &event->hw, idx); + event->hw.state |= PERF_HES_UPTODATE; + } +} - sh_perf_event_update(event, &event->hw, idx); +static void sh_pmu_start(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + struct hw_perf_event *hwc = &event->hw; + int idx = hwc->idx; - cpuc->events[idx] = NULL; - clear_bit(idx, cpuc->used_mask); + if (WARN_ON_ONCE(idx == -1)) + return; + + if (flags & PERF_EF_RELOAD) + WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); + + cpuc->events[idx] = event; + event->hw.state = 0; + sh_pmu->enable(hwc, idx); +} + +static void sh_pmu_del(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + + sh_pmu_stop(event, PERF_EF_UPDATE); + __clear_bit(event->hw.idx, cpuc->used_mask); perf_event_update_userpage(event); } -static int sh_pmu_enable(struct perf_event *event) +static int sh_pmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; @@ -234,21 +260,20 @@ static int sh_pmu_enable(struct perf_event *event) perf_pmu_disable(event->pmu); - if (test_and_set_bit(idx, cpuc->used_mask)) { + if (__test_and_set_bit(idx, cpuc->used_mask)) { idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); if (idx == sh_pmu->num_events) goto out; - set_bit(idx, cpuc->used_mask); + __set_bit(idx, cpuc->used_mask); hwc->idx = idx; } sh_pmu->disable(hwc, idx); - cpuc->events[idx] = event; - set_bit(idx, cpuc->active_mask); - - sh_pmu->enable(hwc, idx); + event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED; + if (flags & PERF_EF_START) + sh_pmu_start(event, PERF_EF_RELOAD); perf_event_update_userpage(event); ret = 0; @@ -285,7 +310,7 @@ static int sh_pmu_event_init(struct perf_event *event) return err; } -static void sh_pmu_pmu_enable(struct pmu *pmu) +static void sh_pmu_enable(struct pmu *pmu) { if (!sh_pmu_initialized()) return; @@ -293,7 +318,7 @@ static void sh_pmu_pmu_enable(struct pmu *pmu) sh_pmu->enable_all(); } -static void sh_pmu_pmu_disable(struct pmu *pmu) +static void sh_pmu_disable(struct pmu *pmu) { if (!sh_pmu_initialized()) return; @@ -302,11 +327,13 @@ static void sh_pmu_pmu_disable(struct pmu *pmu) } static struct pmu pmu = { - .pmu_enable = sh_pmu_pmu_enable, - .pmu_disable = sh_pmu_pmu_disable, + .pmu_enable = sh_pmu_enable, + .pmu_disable = sh_pmu_disable, .event_init = sh_pmu_event_init, - .enable = sh_pmu_enable, - .disable = sh_pmu_disable, + .add = sh_pmu_add, + .del = sh_pmu_del, + .start = sh_pmu_start, + .stop = sh_pmu_stop, .read = sh_pmu_read, }; @@ -334,15 +361,15 @@ sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) return NOTIFY_OK; } -int __cpuinit register_sh_pmu(struct sh_pmu *pmu) +int __cpuinit register_sh_pmu(struct sh_pmu *_pmu) { if (sh_pmu) return -EBUSY; - sh_pmu = pmu; + sh_pmu = _pmu; - pr_info("Performance Events: %s support registered\n", pmu->name); + pr_info("Performance Events: %s support registered\n", _pmu->name); - WARN_ON(pmu->num_events > MAX_HWEVENTS); + WARN_ON(_pmu->num_events > MAX_HWEVENTS); perf_pmu_register(&pmu); perf_cpu_notifier(sh_pmu_notifier); diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 37cae676536c..516be2314b54 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -658,13 +658,16 @@ static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr) enc = perf_event_get_enc(cpuc->events[i]); pcr &= ~mask_for_index(idx); - pcr |= event_encoding(enc, idx); + if (hwc->state & PERF_HES_STOPPED) + pcr |= nop_for_index(idx); + else + pcr |= event_encoding(enc, idx); } out: return pcr; } -static void sparc_pmu_pmu_enable(struct pmu *pmu) +static void sparc_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); u64 pcr; @@ -691,7 +694,7 @@ static void sparc_pmu_pmu_enable(struct pmu *pmu) pcr_ops->write(cpuc->pcr); } -static void sparc_pmu_pmu_disable(struct pmu *pmu) +static void sparc_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); u64 val; @@ -710,10 +713,53 @@ static void sparc_pmu_pmu_disable(struct pmu *pmu) pcr_ops->write(cpuc->pcr); } -static void sparc_pmu_disable(struct perf_event *event) +static int active_event_index(struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + int i; + + for (i = 0; i < cpuc->n_events; i++) { + if (cpuc->event[i] == event) + break; + } + BUG_ON(i == cpuc->n_events); + return cpuc->current_idx[i]; +} + +static void sparc_pmu_start(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int idx = active_event_index(cpuc, event); + + if (flags & PERF_EF_RELOAD) { + WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); + sparc_perf_event_set_period(event, &event->hw, idx); + } + + event->hw.state = 0; + + sparc_pmu_enable_event(cpuc, &event->hw, idx); +} + +static void sparc_pmu_stop(struct perf_event *event, int flags) +{ + struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); + int idx = active_event_index(cpuc, event); + + if (!(event->hw.state & PERF_HES_STOPPED)) { + sparc_pmu_disable_event(cpuc, &event->hw, idx); + event->hw.state |= PERF_HES_STOPPED; + } + + if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) { + sparc_perf_event_update(event, &event->hw, idx); + event->hw.state |= PERF_HES_UPTODATE; + } +} + +static void sparc_pmu_del(struct perf_event *event, int _flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - struct hw_perf_event *hwc = &event->hw; unsigned long flags; int i; @@ -722,7 +768,10 @@ static void sparc_pmu_disable(struct perf_event *event) for (i = 0; i < cpuc->n_events; i++) { if (event == cpuc->event[i]) { - int idx = cpuc->current_idx[i]; + /* Absorb the final count and turn off the + * event. + */ + sparc_pmu_stop(event, PERF_EF_UPDATE); /* Shift remaining entries down into * the existing slot. @@ -734,13 +783,6 @@ static void sparc_pmu_disable(struct perf_event *event) cpuc->current_idx[i]; } - /* Absorb the final count and turn off the - * event. - */ - sparc_pmu_disable_event(cpuc, hwc, idx); - barrier(); - sparc_perf_event_update(event, hwc, idx); - perf_event_update_userpage(event); cpuc->n_events--; @@ -752,19 +794,6 @@ static void sparc_pmu_disable(struct perf_event *event) local_irq_restore(flags); } -static int active_event_index(struct cpu_hw_events *cpuc, - struct perf_event *event) -{ - int i; - - for (i = 0; i < cpuc->n_events; i++) { - if (cpuc->event[i] == event) - break; - } - BUG_ON(i == cpuc->n_events); - return cpuc->current_idx[i]; -} - static void sparc_pmu_read(struct perf_event *event) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -774,15 +803,6 @@ static void sparc_pmu_read(struct perf_event *event) sparc_perf_event_update(event, hwc, idx); } -static void sparc_pmu_unthrottle(struct perf_event *event) -{ - struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); - int idx = active_event_index(cpuc, event); - struct hw_perf_event *hwc = &event->hw; - - sparc_pmu_enable_event(cpuc, hwc, idx); -} - static atomic_t active_events = ATOMIC_INIT(0); static DEFINE_MUTEX(pmc_grab_mutex); @@ -984,7 +1004,7 @@ static int collect_events(struct perf_event *group, int max_count, return n; } -static int sparc_pmu_enable(struct perf_event *event) +static int sparc_pmu_add(struct perf_event *event, int ef_flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int n0, ret = -EAGAIN; @@ -1001,6 +1021,10 @@ static int sparc_pmu_enable(struct perf_event *event) cpuc->events[n0] = event->hw.event_base; cpuc->current_idx[n0] = PIC_NO_INDEX; + event->hw.state = PERF_HES_UPTODATE; + if (!(ef_flags & PERF_EF_START)) + event->hw.state |= PERF_HES_STOPPED; + /* * If group events scheduling transaction was started, * skip the schedulability test here, it will be peformed @@ -1156,13 +1180,14 @@ static int sparc_pmu_commit_txn(struct pmu *pmu) } static struct pmu pmu = { - .pmu_enable = sparc_pmu_pmu_enable, - .pmu_disable = sparc_pmu_pmu_disable, + .pmu_enable = sparc_pmu_enable, + .pmu_disable = sparc_pmu_disable, .event_init = sparc_pmu_event_init, - .enable = sparc_pmu_enable, - .disable = sparc_pmu_disable, + .add = sparc_pmu_add, + .del = sparc_pmu_del, + .start = sparc_pmu_start, + .stop = sparc_pmu_stop, .read = sparc_pmu_read, - .unthrottle = sparc_pmu_unthrottle, .start_txn = sparc_pmu_start_txn, .cancel_txn = sparc_pmu_cancel_txn, .commit_txn = sparc_pmu_commit_txn, @@ -1243,7 +1268,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self, continue; if (perf_event_overflow(event, 1, &data, regs)) - sparc_pmu_disable_event(cpuc, hwc, idx); + sparc_pmu_stop(event, 0); } return NOTIFY_STOP; diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 79705ac45019..dd6fec710677 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -583,7 +583,7 @@ static void x86_pmu_disable_all(void) } } -static void x86_pmu_pmu_disable(struct pmu *pmu) +static void x86_pmu_disable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); @@ -800,10 +800,10 @@ static inline int match_prev_assignment(struct hw_perf_event *hwc, hwc->last_tag == cpuc->tags[i]; } -static int x86_pmu_start(struct perf_event *event); -static void x86_pmu_stop(struct perf_event *event); +static void x86_pmu_start(struct perf_event *event, int flags); +static void x86_pmu_stop(struct perf_event *event, int flags); -static void x86_pmu_pmu_enable(struct pmu *pmu) +static void x86_pmu_enable(struct pmu *pmu) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct perf_event *event; @@ -839,7 +839,14 @@ static void x86_pmu_pmu_enable(struct pmu *pmu) match_prev_assignment(hwc, cpuc, i)) continue; - x86_pmu_stop(event); + /* + * Ensure we don't accidentally enable a stopped + * counter simply because we rescheduled. + */ + if (hwc->state & PERF_HES_STOPPED) + hwc->state |= PERF_HES_ARCH; + + x86_pmu_stop(event, PERF_EF_UPDATE); } for (i = 0; i < cpuc->n_events; i++) { @@ -851,7 +858,10 @@ static void x86_pmu_pmu_enable(struct pmu *pmu) else if (i < n_running) continue; - x86_pmu_start(event); + if (hwc->state & PERF_HES_ARCH) + continue; + + x86_pmu_start(event, PERF_EF_RELOAD); } cpuc->n_added = 0; perf_events_lapic_init(); @@ -952,15 +962,12 @@ static void x86_pmu_enable_event(struct perf_event *event) } /* - * activate a single event + * Add a single event to the PMU. * * The event is added to the group of enabled events * but only if it can be scehduled with existing events. - * - * Called with PMU disabled. If successful and return value 1, - * then guaranteed to call perf_enable() and hw_perf_enable() */ -static int x86_pmu_enable(struct perf_event *event) +static int x86_pmu_add(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc; @@ -975,10 +982,14 @@ static int x86_pmu_enable(struct perf_event *event) if (ret < 0) goto out; + hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; + if (!(flags & PERF_EF_START)) + hwc->state |= PERF_HES_ARCH; + /* * If group events scheduling transaction was started, * skip the schedulability test here, it will be peformed - * at commit time(->commit_txn) as a whole + * at commit time (->commit_txn) as a whole */ if (cpuc->group_flag & PERF_EVENT_TXN) goto done_collect; @@ -1003,27 +1014,28 @@ out: return ret; } -static int x86_pmu_start(struct perf_event *event) +static void x86_pmu_start(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int idx = event->hw.idx; - if (idx == -1) - return -EAGAIN; + if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) + return; + + if (WARN_ON_ONCE(idx == -1)) + return; + + if (flags & PERF_EF_RELOAD) { + WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); + x86_perf_event_set_period(event); + } + + event->hw.state = 0; - x86_perf_event_set_period(event); cpuc->events[idx] = event; __set_bit(idx, cpuc->active_mask); x86_pmu.enable(event); perf_event_update_userpage(event); - - return 0; -} - -static void x86_pmu_unthrottle(struct perf_event *event) -{ - int ret = x86_pmu_start(event); - WARN_ON_ONCE(ret); } void perf_event_print_debug(void) @@ -1080,27 +1092,29 @@ void perf_event_print_debug(void) local_irq_restore(flags); } -static void x86_pmu_stop(struct perf_event *event) +static void x86_pmu_stop(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (!__test_and_clear_bit(idx, cpuc->active_mask)) - return; - - x86_pmu.disable(event); - /* - * Drain the remaining delta count out of a event - * that we are disabling: - */ - x86_perf_event_update(event); + if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { + x86_pmu.disable(event); + cpuc->events[hwc->idx] = NULL; + WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); + hwc->state |= PERF_HES_STOPPED; + } - cpuc->events[idx] = NULL; + if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { + /* + * Drain the remaining delta count out of a event + * that we are disabling: + */ + x86_perf_event_update(event); + hwc->state |= PERF_HES_UPTODATE; + } } -static void x86_pmu_disable(struct perf_event *event) +static void x86_pmu_del(struct perf_event *event, int flags) { struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); int i; @@ -1113,7 +1127,7 @@ static void x86_pmu_disable(struct perf_event *event) if (cpuc->group_flag & PERF_EVENT_TXN) return; - x86_pmu_stop(event); + x86_pmu_stop(event, PERF_EF_UPDATE); for (i = 0; i < cpuc->n_events; i++) { if (event == cpuc->event_list[i]) { @@ -1165,7 +1179,7 @@ static int x86_pmu_handle_irq(struct pt_regs *regs) continue; if (perf_event_overflow(event, 1, &data, regs)) - x86_pmu_stop(event); + x86_pmu_stop(event, 0); } if (handled) @@ -1605,15 +1619,17 @@ int x86_pmu_event_init(struct perf_event *event) } static struct pmu pmu = { - .pmu_enable = x86_pmu_pmu_enable, - .pmu_disable = x86_pmu_pmu_disable, + .pmu_enable = x86_pmu_enable, + .pmu_disable = x86_pmu_disable, + .event_init = x86_pmu_event_init, - .enable = x86_pmu_enable, - .disable = x86_pmu_disable, + + .add = x86_pmu_add, + .del = x86_pmu_del, .start = x86_pmu_start, .stop = x86_pmu_stop, .read = x86_pmu_read, - .unthrottle = x86_pmu_unthrottle, + .start_txn = x86_pmu_start_txn, .cancel_txn = x86_pmu_cancel_txn, .commit_txn = x86_pmu_commit_txn, diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index ee05c90012d2..82395f2378ec 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -763,7 +763,7 @@ again: data.period = event->hw.last_period; if (perf_event_overflow(event, 1, &data, regs)) - x86_pmu_stop(event); + x86_pmu_stop(event, 0); } /* diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 18018d1311cd..9893a2f77b7a 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -491,7 +491,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event, regs.flags &= ~PERF_EFLAGS_EXACT; if (perf_event_overflow(event, 1, &data, ®s)) - x86_pmu_stop(event); + x86_pmu_stop(event, 0); } static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) diff --git a/include/linux/ftrace_event.h b/include/linux/ftrace_event.h index 5f8ad7bec636..8beabb958f61 100644 --- a/include/linux/ftrace_event.h +++ b/include/linux/ftrace_event.h @@ -252,8 +252,8 @@ DECLARE_PER_CPU(struct pt_regs, perf_trace_regs); extern int perf_trace_init(struct perf_event *event); extern void perf_trace_destroy(struct perf_event *event); -extern int perf_trace_enable(struct perf_event *event); -extern void perf_trace_disable(struct perf_event *event); +extern int perf_trace_add(struct perf_event *event, int flags); +extern void perf_trace_del(struct perf_event *event, int flags); extern int ftrace_profile_set_filter(struct perf_event *event, int event_id, char *filter_str); extern void ftrace_profile_free_filter(struct perf_event *event); diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 8cafa15af60d..402073c61669 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -538,6 +538,7 @@ struct hw_perf_event { }; #endif }; + int state; local64_t prev_count; u64 sample_period; u64 last_period; @@ -549,6 +550,13 @@ struct hw_perf_event { #endif }; +/* + * hw_perf_event::state flags + */ +#define PERF_HES_STOPPED 0x01 /* the counter is stopped */ +#define PERF_HES_UPTODATE 0x02 /* event->count up-to-date */ +#define PERF_HES_ARCH 0x04 + struct perf_event; /* @@ -564,42 +572,62 @@ struct pmu { int *pmu_disable_count; + /* + * Fully disable/enable this PMU, can be used to protect from the PMI + * as well as for lazy/batch writing of the MSRs. + */ void (*pmu_enable) (struct pmu *pmu); /* optional */ void (*pmu_disable) (struct pmu *pmu); /* optional */ /* + * Try and initialize the event for this PMU. * Should return -ENOENT when the @event doesn't match this PMU. */ int (*event_init) (struct perf_event *event); - int (*enable) (struct perf_event *event); - void (*disable) (struct perf_event *event); - int (*start) (struct perf_event *event); - void (*stop) (struct perf_event *event); +#define PERF_EF_START 0x01 /* start the counter when adding */ +#define PERF_EF_RELOAD 0x02 /* reload the counter when starting */ +#define PERF_EF_UPDATE 0x04 /* update the counter when stopping */ + + /* + * Adds/Removes a counter to/from the PMU, can be done inside + * a transaction, see the ->*_txn() methods. + */ + int (*add) (struct perf_event *event, int flags); + void (*del) (struct perf_event *event, int flags); + + /* + * Starts/Stops a counter present on the PMU. The PMI handler + * should stop the counter when perf_event_overflow() returns + * !0. ->start() will be used to continue. + */ + void (*start) (struct perf_event *event, int flags); + void (*stop) (struct perf_event *event, int flags); + + /* + * Updates the counter value of the event. + */ void (*read) (struct perf_event *event); - void (*unthrottle) (struct perf_event *event); /* * Group events scheduling is treated as a transaction, add * group events as a whole and perform one schedulability test. * If the test fails, roll back the whole group - */ - - /* - * Start the transaction, after this ->enable() doesn't need to + * + * Start the transaction, after this ->add() doesn't need to * do schedulability tests. */ void (*start_txn) (struct pmu *pmu); /* optional */ /* - * If ->start_txn() disabled the ->enable() schedulability test + * If ->start_txn() disabled the ->add() schedulability test * then ->commit_txn() is required to perform one. On success * the transaction is closed. On error the transaction is kept * open until ->cancel_txn() is called. */ int (*commit_txn) (struct pmu *pmu); /* optional */ /* - * Will cancel the transaction, assumes ->disable() is called - * for each successfull ->enable() during the transaction. + * Will cancel the transaction, assumes ->del() is called + * for each successfull ->add() during the transaction. */ void (*cancel_txn) (struct pmu *pmu); /* optional */ }; @@ -680,7 +708,7 @@ struct perf_event { int nr_siblings; int group_flags; struct perf_event *group_leader; - struct pmu *pmu; + struct pmu *pmu; enum perf_event_active_state state; unsigned int attach_state; diff --git a/kernel/hw_breakpoint.c b/kernel/hw_breakpoint.c index e9c5cfa1fd20..6f150095cafe 100644 --- a/kernel/hw_breakpoint.c +++ b/kernel/hw_breakpoint.c @@ -586,10 +586,35 @@ static int hw_breakpoint_event_init(struct perf_event *bp) return 0; } +static int hw_breakpoint_add(struct perf_event *bp, int flags) +{ + if (!(flags & PERF_EF_START)) + bp->hw.state = PERF_HES_STOPPED; + + return arch_install_hw_breakpoint(bp); +} + +static void hw_breakpoint_del(struct perf_event *bp, int flags) +{ + arch_uninstall_hw_breakpoint(bp); +} + +static void hw_breakpoint_start(struct perf_event *bp, int flags) +{ + bp->hw.state = 0; +} + +static void hw_breakpoint_stop(struct perf_event *bp, int flags) +{ + bp->hw.state = PERF_HES_STOPPED; +} + static struct pmu perf_breakpoint = { .event_init = hw_breakpoint_event_init, - .enable = arch_install_hw_breakpoint, - .disable = arch_uninstall_hw_breakpoint, + .add = hw_breakpoint_add, + .del = hw_breakpoint_del, + .start = hw_breakpoint_start, + .stop = hw_breakpoint_stop, .read = hw_breakpoint_pmu_read, }; diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 1a6cdbf0d091..3bace4fd0355 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -424,7 +424,7 @@ event_sched_out(struct perf_event *event, event->state = PERF_EVENT_STATE_OFF; } event->tstamp_stopped = ctx->time; - event->pmu->disable(event); + event->pmu->del(event, 0); event->oncpu = -1; if (!is_software_event(event)) @@ -649,7 +649,7 @@ event_sched_in(struct perf_event *event, */ smp_wmb(); - if (event->pmu->enable(event)) { + if (event->pmu->add(event, PERF_EF_START)) { event->state = PERF_EVENT_STATE_INACTIVE; event->oncpu = -1; return -EAGAIN; @@ -1482,22 +1482,6 @@ do { \ return div64_u64(dividend, divisor); } -static void perf_event_stop(struct perf_event *event) -{ - if (!event->pmu->stop) - return event->pmu->disable(event); - - return event->pmu->stop(event); -} - -static int perf_event_start(struct perf_event *event) -{ - if (!event->pmu->start) - return event->pmu->enable(event); - - return event->pmu->start(event); -} - static void perf_adjust_period(struct perf_event *event, u64 nsec, u64 count) { struct hw_perf_event *hwc = &event->hw; @@ -1517,9 +1501,9 @@ static void perf_adjust_period(struct perf_event *event, u64 nsec, u64 count) hwc->sample_period = sample_period; if (local64_read(&hwc->period_left) > 8*sample_period) { - perf_event_stop(event); + event->pmu->stop(event, PERF_EF_UPDATE); local64_set(&hwc->period_left, 0); - perf_event_start(event); + event->pmu->start(event, PERF_EF_RELOAD); } } @@ -1548,7 +1532,7 @@ static void perf_ctx_adjust_freq(struct perf_event_context *ctx) */ if (interrupts == MAX_INTERRUPTS) { perf_log_throttle(event, 1); - event->pmu->unthrottle(event); + event->pmu->start(event, 0); } if (!event->attr.freq || !event->attr.sample_freq) @@ -2506,6 +2490,9 @@ int perf_event_task_disable(void) static int perf_event_index(struct perf_event *event) { + if (event->hw.state & PERF_HES_STOPPED) + return 0; + if (event->state != PERF_EVENT_STATE_ACTIVE) return 0; @@ -4120,8 +4107,6 @@ static int __perf_event_overflow(struct perf_event *event, int nmi, struct hw_perf_event *hwc = &event->hw; int ret = 0; - throttle = (throttle && event->pmu->unthrottle != NULL); - if (!throttle) { hwc->interrupts++; } else { @@ -4246,7 +4231,7 @@ static void perf_swevent_overflow(struct perf_event *event, u64 overflow, } } -static void perf_swevent_add(struct perf_event *event, u64 nr, +static void perf_swevent_event(struct perf_event *event, u64 nr, int nmi, struct perf_sample_data *data, struct pt_regs *regs) { @@ -4272,6 +4257,9 @@ static void perf_swevent_add(struct perf_event *event, u64 nr, static int perf_exclude_event(struct perf_event *event, struct pt_regs *regs) { + if (event->hw.state & PERF_HES_STOPPED) + return 0; + if (regs) { if (event->attr.exclude_user && user_mode(regs)) return 1; @@ -4371,7 +4359,7 @@ static void do_perf_sw_event(enum perf_type_id type, u32 event_id, hlist_for_each_entry_rcu(event, node, head, hlist_entry) { if (perf_swevent_match(event, type, event_id, data, regs)) - perf_swevent_add(event, nr, nmi, data, regs); + perf_swevent_event(event, nr, nmi, data, regs); } end: rcu_read_unlock(); @@ -4415,7 +4403,7 @@ static void perf_swevent_read(struct perf_event *event) { } -static int perf_swevent_enable(struct perf_event *event) +static int perf_swevent_add(struct perf_event *event, int flags) { struct hw_perf_event *hwc = &event->hw; struct perf_cpu_context *cpuctx; @@ -4428,6 +4416,8 @@ static int perf_swevent_enable(struct perf_event *event) perf_swevent_set_period(event); } + hwc->state = !(flags & PERF_EF_START); + head = find_swevent_head(cpuctx, event); if (WARN_ON_ONCE(!head)) return -EINVAL; @@ -4437,18 +4427,19 @@ static int perf_swevent_enable(struct perf_event *event) return 0; } -static void perf_swevent_disable(struct perf_event *event) +static void perf_swevent_del(struct perf_event *event, int flags) { hlist_del_rcu(&event->hlist_entry); } -static void perf_swevent_void(struct perf_event *event) +static void perf_swevent_start(struct perf_event *event, int flags) { + event->hw.state = 0; } -static int perf_swevent_int(struct perf_event *event) +static void perf_swevent_stop(struct perf_event *event, int flags) { - return 0; + event->hw.state = PERF_HES_STOPPED; } /* Deref the hlist from the update side */ @@ -4604,12 +4595,11 @@ static int perf_swevent_init(struct perf_event *event) static struct pmu perf_swevent = { .event_init = perf_swevent_init, - .enable = perf_swevent_enable, - .disable = perf_swevent_disable, - .start = perf_swevent_int, - .stop = perf_swevent_void, + .add = perf_swevent_add, + .del = perf_swevent_del, + .start = perf_swevent_start, + .stop = perf_swevent_stop, .read = perf_swevent_read, - .unthrottle = perf_swevent_void, /* hwc->interrupts already reset */ }; #ifdef CONFIG_EVENT_TRACING @@ -4657,7 +4647,7 @@ void perf_tp_event(u64 addr, u64 count, void *record, int entry_size, hlist_for_each_entry_rcu(event, node, head, hlist_entry) { if (perf_tp_event_match(event, &data, regs)) - perf_swevent_add(event, count, 1, &data, regs); + perf_swevent_event(event, count, 1, &data, regs); } perf_swevent_put_recursion_context(rctx); @@ -4696,12 +4686,11 @@ static int perf_tp_event_init(struct perf_event *event) static struct pmu perf_tracepoint = { .event_init = perf_tp_event_init, - .enable = perf_trace_enable, - .disable = perf_trace_disable, - .start = perf_swevent_int, - .stop = perf_swevent_void, + .add = perf_trace_add, + .del = perf_trace_del, + .start = perf_swevent_start, + .stop = perf_swevent_stop, .read = perf_swevent_read, - .unthrottle = perf_swevent_void, }; static inline void perf_tp_register(void) @@ -4757,8 +4746,8 @@ void perf_bp_event(struct perf_event *bp, void *data) perf_sample_data_init(&sample, bp->attr.bp_addr); - if (!perf_exclude_event(bp, regs)) - perf_swevent_add(bp, 1, 1, &sample, regs); + if (!bp->hw.state && !perf_exclude_event(bp, regs)) + perf_swevent_event(bp, 1, 1, &sample, regs); } #endif @@ -4834,32 +4823,39 @@ static void perf_swevent_cancel_hrtimer(struct perf_event *event) static void cpu_clock_event_update(struct perf_event *event) { - int cpu = raw_smp_processor_id(); s64 prev; u64 now; - now = cpu_clock(cpu); + now = local_clock(); prev = local64_xchg(&event->hw.prev_count, now); local64_add(now - prev, &event->count); } -static int cpu_clock_event_enable(struct perf_event *event) +static void cpu_clock_event_start(struct perf_event *event, int flags) { - struct hw_perf_event *hwc = &event->hw; - int cpu = raw_smp_processor_id(); - - local64_set(&hwc->prev_count, cpu_clock(cpu)); + local64_set(&event->hw.prev_count, local_clock()); perf_swevent_start_hrtimer(event); - - return 0; } -static void cpu_clock_event_disable(struct perf_event *event) +static void cpu_clock_event_stop(struct perf_event *event, int flags) { perf_swevent_cancel_hrtimer(event); cpu_clock_event_update(event); } +static int cpu_clock_event_add(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_START) + cpu_clock_event_start(event, flags); + + return 0; +} + +static void cpu_clock_event_del(struct perf_event *event, int flags) +{ + cpu_clock_event_stop(event, flags); +} + static void cpu_clock_event_read(struct perf_event *event) { cpu_clock_event_update(event); @@ -4878,8 +4874,10 @@ static int cpu_clock_event_init(struct perf_event *event) static struct pmu perf_cpu_clock = { .event_init = cpu_clock_event_init, - .enable = cpu_clock_event_enable, - .disable = cpu_clock_event_disable, + .add = cpu_clock_event_add, + .del = cpu_clock_event_del, + .start = cpu_clock_event_start, + .stop = cpu_clock_event_stop, .read = cpu_clock_event_read, }; @@ -4897,25 +4895,29 @@ static void task_clock_event_update(struct perf_event *event, u64 now) local64_add(delta, &event->count); } -static int task_clock_event_enable(struct perf_event *event) +static void task_clock_event_start(struct perf_event *event, int flags) { - struct hw_perf_event *hwc = &event->hw; - u64 now; - - now = event->ctx->time; - - local64_set(&hwc->prev_count, now); - + local64_set(&event->hw.prev_count, event->ctx->time); perf_swevent_start_hrtimer(event); - - return 0; } -static void task_clock_event_disable(struct perf_event *event) +static void task_clock_event_stop(struct perf_event *event, int flags) { perf_swevent_cancel_hrtimer(event); task_clock_event_update(event, event->ctx->time); +} + +static int task_clock_event_add(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_START) + task_clock_event_start(event, flags); + return 0; +} + +static void task_clock_event_del(struct perf_event *event, int flags) +{ + task_clock_event_stop(event, PERF_EF_UPDATE); } static void task_clock_event_read(struct perf_event *event) @@ -4947,8 +4949,10 @@ static int task_clock_event_init(struct perf_event *event) static struct pmu perf_task_clock = { .event_init = task_clock_event_init, - .enable = task_clock_event_enable, - .disable = task_clock_event_disable, + .add = task_clock_event_add, + .del = task_clock_event_del, + .start = task_clock_event_start, + .stop = task_clock_event_stop, .read = task_clock_event_read, }; diff --git a/kernel/trace/trace_event_perf.c b/kernel/trace/trace_event_perf.c index f3bbcd1c90c8..39c059ca670e 100644 --- a/kernel/trace/trace_event_perf.c +++ b/kernel/trace/trace_event_perf.c @@ -101,7 +101,7 @@ int perf_trace_init(struct perf_event *p_event) return ret; } -int perf_trace_enable(struct perf_event *p_event) +int perf_trace_add(struct perf_event *p_event, int flags) { struct ftrace_event_call *tp_event = p_event->tp_event; struct hlist_head __percpu *pcpu_list; @@ -111,13 +111,16 @@ int perf_trace_enable(struct perf_event *p_event) if (WARN_ON_ONCE(!pcpu_list)) return -EINVAL; + if (!(flags & PERF_EF_START)) + p_event->hw.state = PERF_HES_STOPPED; + list = this_cpu_ptr(pcpu_list); hlist_add_head_rcu(&p_event->hlist_entry, list); return 0; } -void perf_trace_disable(struct perf_event *p_event) +void perf_trace_del(struct perf_event *p_event, int flags) { hlist_del_rcu(&p_event->hlist_entry); } -- cgit v1.2.3 From 15ac9a395a753cb28c674e7ea80386ffdff21785 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Mon, 6 Sep 2010 15:51:45 +0200 Subject: perf: Remove the sysfs bits Neither the overcommit nor the reservation sysfs parameter were actually working, remove them as they'll only get in the way. Signed-off-by: Peter Zijlstra Cc: paulus LKML-Reference: Signed-off-by: Ingo Molnar --- arch/alpha/kernel/perf_event.c | 3 +- arch/arm/kernel/perf_event.c | 9 +-- arch/sparc/kernel/perf_event.c | 9 +-- arch/x86/kernel/cpu/perf_event.c | 1 - include/linux/perf_event.h | 6 -- kernel/perf_event.c | 124 --------------------------------------- 6 files changed, 5 insertions(+), 147 deletions(-) (limited to 'arch/arm') diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 380ef02d557a..9bb8c024080c 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -808,7 +808,7 @@ static void alpha_perf_event_irq_handler(unsigned long la_ptr, wrperfmon(PERFMON_CMD_DISABLE, cpuc->idx_mask); /* la_ptr is the counter that overflowed. */ - if (unlikely(la_ptr >= perf_max_events)) { + if (unlikely(la_ptr >= alpha_pmu->num_pmcs)) { /* This should never occur! */ irq_err_count++; pr_warning("PMI: silly index %ld\n", la_ptr); @@ -879,7 +879,6 @@ void __init init_hw_perf_events(void) /* And set up PMU specification */ alpha_pmu = &ev67_pmu; - perf_max_events = alpha_pmu->num_pmcs; perf_pmu_register(&pmu); } diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 448cfa6b3ef0..45d6a35217c1 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c @@ -534,7 +534,7 @@ static int armpmu_event_init(struct perf_event *event) event->destroy = hw_perf_event_destroy; if (!atomic_inc_not_zero(&active_events)) { - if (atomic_read(&active_events) > perf_max_events) { + if (atomic_read(&active_events) > armpmu.num_events) { atomic_dec(&active_events); return -ENOSPC; } @@ -2974,14 +2974,12 @@ init_hw_perf_events(void) armpmu = &armv6pmu; memcpy(armpmu_perf_cache_map, armv6_perf_cache_map, sizeof(armv6_perf_cache_map)); - perf_max_events = armv6pmu.num_events; break; case 0xB020: /* ARM11mpcore */ armpmu = &armv6mpcore_pmu; memcpy(armpmu_perf_cache_map, armv6mpcore_perf_cache_map, sizeof(armv6mpcore_perf_cache_map)); - perf_max_events = armv6mpcore_pmu.num_events; break; case 0xC080: /* Cortex-A8 */ armv7pmu.id = ARM_PERF_PMU_ID_CA8; @@ -2993,7 +2991,6 @@ init_hw_perf_events(void) /* Reset PMNC and read the nb of CNTx counters supported */ armv7pmu.num_events = armv7_reset_read_pmnc(); - perf_max_events = armv7pmu.num_events; break; case 0xC090: /* Cortex-A9 */ armv7pmu.id = ARM_PERF_PMU_ID_CA9; @@ -3005,7 +3002,6 @@ init_hw_perf_events(void) /* Reset PMNC and read the nb of CNTx counters supported */ armv7pmu.num_events = armv7_reset_read_pmnc(); - perf_max_events = armv7pmu.num_events; break; } /* Intel CPUs [xscale]. */ @@ -3016,13 +3012,11 @@ init_hw_perf_events(void) armpmu = &xscale1pmu; memcpy(armpmu_perf_cache_map, xscale_perf_cache_map, sizeof(xscale_perf_cache_map)); - perf_max_events = xscale1pmu.num_events; break; case 2: armpmu = &xscale2pmu; memcpy(armpmu_perf_cache_map, xscale_perf_cache_map, sizeof(xscale_perf_cache_map)); - perf_max_events = xscale2pmu.num_events; break; } } @@ -3032,7 +3026,6 @@ init_hw_perf_events(void) arm_pmu_names[armpmu->id], armpmu->num_events); } else { pr_info("no hardware support available\n"); - perf_max_events = -1; } perf_pmu_register(&pmu); diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 516be2314b54..f9a706759364 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -897,7 +897,7 @@ static int sparc_check_constraints(struct perf_event **evts, if (!n_ev) return 0; - if (n_ev > perf_max_events) + if (n_ev > MAX_HWEVENTS) return -1; msk0 = perf_event_get_msk(events[0]); @@ -1014,7 +1014,7 @@ static int sparc_pmu_add(struct perf_event *event, int ef_flags) perf_pmu_disable(event->pmu); n0 = cpuc->n_events; - if (n0 >= perf_max_events) + if (n0 >= MAX_HWEVENTS) goto out; cpuc->event[n0] = event; @@ -1097,7 +1097,7 @@ static int sparc_pmu_event_init(struct perf_event *event) n = 0; if (event->group_leader != event) { n = collect_events(event->group_leader, - perf_max_events - 1, + MAX_HWEVENTS - 1, evts, events, current_idx_dmy); if (n < 0) return -EINVAL; @@ -1309,9 +1309,6 @@ void __init init_hw_perf_events(void) pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); - /* All sparc64 PMUs currently have 2 events. */ - perf_max_events = 2; - perf_pmu_register(&pmu); register_die_notifier(&perf_event_nmi_notifier); } diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index dd6fec710677..0fb17050360f 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -1396,7 +1396,6 @@ void __init init_hw_perf_events(void) x86_pmu.num_counters = X86_PMC_MAX_GENERIC; } x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; - perf_max_events = x86_pmu.num_counters; if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 402073c61669..b22176d3ebdf 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -860,7 +860,6 @@ struct perf_cpu_context { struct perf_event_context ctx; struct perf_event_context *task_ctx; int active_oncpu; - int max_pertask; int exclusive; struct swevent_hlist *swevent_hlist; struct mutex hlist_mutex; @@ -883,11 +882,6 @@ struct perf_output_handle { #ifdef CONFIG_PERF_EVENTS -/* - * Set by architecture code: - */ -extern int perf_max_events; - extern int perf_pmu_register(struct pmu *pmu); extern void perf_pmu_unregister(struct pmu *pmu); diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 3bace4fd0355..8462e69409ae 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -39,10 +39,6 @@ */ static DEFINE_PER_CPU(struct perf_cpu_context, perf_cpu_context); -int perf_max_events __read_mostly = 1; -static int perf_reserved_percpu __read_mostly; -static int perf_overcommit __read_mostly = 1; - static atomic_t nr_events __read_mostly; static atomic_t nr_mmap_events __read_mostly; static atomic_t nr_comm_events __read_mostly; @@ -66,11 +62,6 @@ int sysctl_perf_event_sample_rate __read_mostly = 100000; static atomic64_t perf_event_id; -/* - * Lock for (sysadmin-configurable) event reservations: - */ -static DEFINE_SPINLOCK(perf_resource_lock); - void __weak perf_event_print_debug(void) { } void perf_pmu_disable(struct pmu *pmu) @@ -480,16 +471,6 @@ static void __perf_event_remove_from_context(void *info) list_del_event(event, ctx); - if (!ctx->task) { - /* - * Allow more per task events with respect to the - * reservation: - */ - cpuctx->max_pertask = - min(perf_max_events - ctx->nr_events, - perf_max_events - perf_reserved_percpu); - } - raw_spin_unlock(&ctx->lock); } @@ -823,9 +804,6 @@ static void __perf_install_in_context(void *info) } } - if (!err && !ctx->task && cpuctx->max_pertask) - cpuctx->max_pertask--; - unlock: raw_spin_unlock(&ctx->lock); } @@ -5930,10 +5908,6 @@ static void __cpuinit perf_event_init_cpu(int cpu) cpuctx = &per_cpu(perf_cpu_context, cpu); - spin_lock(&perf_resource_lock); - cpuctx->max_pertask = perf_max_events - perf_reserved_percpu; - spin_unlock(&perf_resource_lock); - mutex_lock(&cpuctx->hlist_mutex); if (cpuctx->hlist_refcount > 0) { struct swevent_hlist *hlist; @@ -6008,101 +5982,3 @@ void __init perf_event_init(void) perf_tp_register(); perf_cpu_notifier(perf_cpu_notify); } - -static ssize_t perf_show_reserve_percpu(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - char *buf) -{ - return sprintf(buf, "%d\n", perf_reserved_percpu); -} - -static ssize_t -perf_set_reserve_percpu(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - const char *buf, - size_t count) -{ - struct perf_cpu_context *cpuctx; - unsigned long val; - int err, cpu, mpt; - - err = strict_strtoul(buf, 10, &val); - if (err) - return err; - if (val > perf_max_events) - return -EINVAL; - - spin_lock(&perf_resource_lock); - perf_reserved_percpu = val; - for_each_online_cpu(cpu) { - cpuctx = &per_cpu(perf_cpu_context, cpu); - raw_spin_lock_irq(&cpuctx->ctx.lock); - mpt = min(perf_max_events - cpuctx->ctx.nr_events, - perf_max_events - perf_reserved_percpu); - cpuctx->max_pertask = mpt; - raw_spin_unlock_irq(&cpuctx->ctx.lock); - } - spin_unlock(&perf_resource_lock); - - return count; -} - -static ssize_t perf_show_overcommit(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - char *buf) -{ - return sprintf(buf, "%d\n", perf_overcommit); -} - -static ssize_t -perf_set_overcommit(struct sysdev_class *class, - struct sysdev_class_attribute *attr, - const char *buf, size_t count) -{ - unsigned long val; - int err; - - err = strict_strtoul(buf, 10, &val); - if (err) - return err; - if (val > 1) - return -EINVAL; - - spin_lock(&perf_resource_lock); - perf_overcommit = val; - spin_unlock(&perf_resource_lock); - - return count; -} - -static SYSDEV_CLASS_ATTR( - reserve_percpu, - 0644, - perf_show_reserve_percpu, - perf_set_reserve_percpu - ); - -static SYSDEV_CLASS_ATTR( - overcommit, - 0644, - perf_show_overcommit, - perf_set_overcommit - ); - -static struct attribute *perfclass_attrs[] = { - &attr_reserve_percpu.attr, - &attr_overcommit.attr, - NULL -}; - -static struct attribute_group perfclass_attr_group = { - .attrs = perfclass_attrs, - .name = "perf_events", -}; - -static int __init perf_event_sysfs_init(void) -{ - return sysfs_create_group(&cpu_sysdev_class.kset.kobj, - &perfclass_attr_group); -} -device_initcall(perf_event_sysfs_init); -- cgit v1.2.3 From 38a81da2205f94e8a2a834b51a6b99c91fc7c2e8 Mon Sep 17 00:00:00 2001 From: Matt Helsley Date: Mon, 13 Sep 2010 13:01:20 -0700 Subject: perf events: Clean up pid passing The kernel perf event creation path shouldn't use find_task_by_vpid() because a vpid exists in a specific namespace. find_task_by_vpid() uses current's pid namespace which isn't always the correct namespace to use for the vpid in all the places perf_event_create_kernel_counter() (and thus find_get_context()) is called. The goal is to clean up pid namespace handling and prevent bugs like: https://bugzilla.kernel.org/show_bug.cgi?id=17281 Instead of using pids switch find_get_context() to use task struct pointers directly. The syscall is responsible for resolving the pid to a task struct. This moves the pid namespace resolution into the syscall much like every other syscall that takes pid parameters. Signed-off-by: Matt Helsley Signed-off-by: Peter Zijlstra Cc: Robin Green Cc: Prasad Cc: Arnaldo Carvalho de Melo Cc: Steven Rostedt Cc: Will Deacon Cc: Mahesh Salgaonkar LKML-Reference: Signed-off-by: Ingo Molnar --- arch/arm/oprofile/common.c | 2 +- include/linux/perf_event.h | 2 +- kernel/hw_breakpoint.c | 5 ++--- kernel/perf_event.c | 21 ++++++++++----------- kernel/watchdog.c | 2 +- 5 files changed, 15 insertions(+), 17 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 0691176899ff..aad63e611b36 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -96,7 +96,7 @@ static int op_create_counter(int cpu, int event) return ret; pevent = perf_event_create_kernel_counter(&counter_config[event].attr, - cpu, -1, + cpu, NULL, op_overflow_handler); if (IS_ERR(pevent)) { diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 93bf53aa50e5..39d8860b2684 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -902,7 +902,7 @@ extern int perf_event_release_kernel(struct perf_event *event); extern struct perf_event * perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu, - pid_t pid, + struct task_struct *task, perf_overflow_handler_t callback); extern u64 perf_event_read_value(struct perf_event *event, u64 *enabled, u64 *running); diff --git a/kernel/hw_breakpoint.c b/kernel/hw_breakpoint.c index 6122f02cfedf..3b714e839c10 100644 --- a/kernel/hw_breakpoint.c +++ b/kernel/hw_breakpoint.c @@ -433,8 +433,7 @@ register_user_hw_breakpoint(struct perf_event_attr *attr, perf_overflow_handler_t triggered, struct task_struct *tsk) { - return perf_event_create_kernel_counter(attr, -1, task_pid_vnr(tsk), - triggered); + return perf_event_create_kernel_counter(attr, -1, tsk, triggered); } EXPORT_SYMBOL_GPL(register_user_hw_breakpoint); @@ -516,7 +515,7 @@ register_wide_hw_breakpoint(struct perf_event_attr *attr, get_online_cpus(); for_each_online_cpu(cpu) { pevent = per_cpu_ptr(cpu_events, cpu); - bp = perf_event_create_kernel_counter(attr, cpu, -1, triggered); + bp = perf_event_create_kernel_counter(attr, cpu, NULL, triggered); *pevent = bp; diff --git a/kernel/perf_event.c b/kernel/perf_event.c index 3f5309db72f1..86f394e15d53 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -2053,15 +2053,14 @@ errout: } static struct perf_event_context * -find_get_context(struct pmu *pmu, pid_t pid, int cpu) +find_get_context(struct pmu *pmu, struct task_struct *task, int cpu) { struct perf_event_context *ctx; struct perf_cpu_context *cpuctx; - struct task_struct *task; unsigned long flags; int ctxn, err; - if (pid == -1 && cpu != -1) { + if (!task && cpu != -1) { /* Must be root to operate on a CPU event: */ if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) return ERR_PTR(-EACCES); @@ -2084,10 +2083,6 @@ find_get_context(struct pmu *pmu, pid_t pid, int cpu) return ctx; } - task = find_lively_task_by_vpid(pid); - if (IS_ERR(task)) - return (void*)task; - err = -EINVAL; ctxn = pmu->task_ctx_nr; if (ctxn < 0) @@ -5527,6 +5522,7 @@ SYSCALL_DEFINE5(perf_event_open, struct perf_event_context *ctx; struct file *event_file = NULL; struct file *group_file = NULL; + struct task_struct *task = NULL; struct pmu *pmu; int event_fd; int fput_needed = 0; @@ -5581,10 +5577,13 @@ SYSCALL_DEFINE5(perf_event_open, if ((pmu->task_ctx_nr == perf_sw_context) && group_leader) pmu = group_leader->pmu; + if (pid != -1) + task = find_lively_task_by_vpid(pid); + /* * Get the target context (task or percpu): */ - ctx = find_get_context(pmu, pid, cpu); + ctx = find_get_context(pmu, task, cpu); if (IS_ERR(ctx)) { err = PTR_ERR(ctx); goto err_group_fd; @@ -5666,11 +5665,11 @@ err_fd: * * @attr: attributes of the counter to create * @cpu: cpu in which the counter is bound - * @pid: task to profile + * @task: task to profile (NULL for percpu) */ struct perf_event * perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu, - pid_t pid, + struct task_struct *task, perf_overflow_handler_t overflow_handler) { struct perf_event_context *ctx; @@ -5687,7 +5686,7 @@ perf_event_create_kernel_counter(struct perf_event_attr *attr, int cpu, goto err; } - ctx = find_get_context(event->pmu, pid, cpu); + ctx = find_get_context(event->pmu, task, cpu); if (IS_ERR(ctx)) { err = PTR_ERR(ctx); goto err_free; diff --git a/kernel/watchdog.c b/kernel/watchdog.c index 89eadbb9cefe..dc8e16824b51 100644 --- a/kernel/watchdog.c +++ b/kernel/watchdog.c @@ -358,7 +358,7 @@ static int watchdog_nmi_enable(int cpu) /* Try to register using hardware perf events */ wd_attr = &wd_hw_attr; wd_attr->sample_period = hw_nmi_get_sample_period(); - event = perf_event_create_kernel_counter(wd_attr, cpu, -1, watchdog_overflow_callback); + event = perf_event_create_kernel_counter(wd_attr, cpu, NULL, watchdog_overflow_callback); if (!IS_ERR(event)) { printk(KERN_INFO "NMI watchdog enabled, takes one hw-pmu counter.\n"); goto out_save; -- cgit v1.2.3 From 359f64f7b3997e94ee71039b5fcdc1278b9b77c4 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 15 Sep 2010 10:18:51 -0700 Subject: omap: Fix compile dependency to LEDS_CLASS If we LEDS_CLASS is not selected, we will get undefined reference to `led_classdev_register'. Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index e39a417a368d..a92cb499313f 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -33,7 +33,7 @@ config OMAP_DEBUG_DEVICES config OMAP_DEBUG_LEDS bool depends on OMAP_DEBUG_DEVICES - default y if LEDS + default y if LEDS_CLASS config OMAP_RESET_CLOCKS bool "Reset unused clocks during boot" -- cgit v1.2.3 From 7c996361ef0d02ef8c1435902c909d14195adcdc Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Thu, 16 Sep 2010 00:20:36 -0700 Subject: arm, memblock: Fix the sparsemem build Stephen Rothwell reported this build failure: arch/arm/mm/init.c: In function 'arm_memory_present': arch/arm/mm/init.c:260: warning: ISO C90 forbids mixed declarations and code Caused by commit 719c1514f2 ("memblock/arm: Use new accessors") which forgot a closing brace on a new for_each_memblock() in arm_memory_present(). Reported-by: Stephen Rothwell Signed-off-by: Yinghai Lu Cc: Peter Zijlstra Cc: Benjamin Herrenschmidt Cc: Russell King LKML-Reference: <4C91C544.5050907@kernel.org> Signed-off-by: Ingo Molnar --- arch/arm/mm/init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 8504906b147f..d6022d1f51d1 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -249,9 +249,8 @@ static void arm_memory_present(void) static void arm_memory_present(void) { struct memblock_region *reg; - int i; - for_each_memblock(memory, reg) { + for_each_memblock(memory, reg) memory_present(0, memblock_region_base_pfn(reg), memblock_region_end_pfn(reg)); } -- cgit v1.2.3 From c0b0aca0e0e8c479c43c1e126cddc5fc82b2803a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 6 Jul 2010 19:16:33 +0200 Subject: arm/omap: use generic_file_llseek in iommu_debug In future kernels, debugfs files need to specify the llseek operation explicitly to allow seeking. This sets the llseek operation in the omap iommu debugfs files to generic_file_llseek, which is appropriate for files using simple_read_from_buffer. Signed-off-by: Arnd Bergmann Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org --- arch/arm/plat-omap/iommu-debug.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/iommu-debug.c b/arch/arm/plat-omap/iommu-debug.c index e6c0d536899c..f07cf2f08e09 100644 --- a/arch/arm/plat-omap/iommu-debug.c +++ b/arch/arm/plat-omap/iommu-debug.c @@ -328,12 +328,14 @@ static int debug_open_generic(struct inode *inode, struct file *file) .open = debug_open_generic, \ .read = debug_read_##name, \ .write = debug_write_##name, \ + .llseek = generic_file_llseek, \ }; #define DEBUG_FOPS_RO(name) \ static const struct file_operations debug_##name##_fops = { \ .open = debug_open_generic, \ .read = debug_read_##name, \ + .llseek = generic_file_llseek, \ }; DEBUG_FOPS_RO(ver); -- cgit v1.2.3 From 83ef3338a2ae5d5bd9f5f6803b900b8067660054 Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:13:56 +0200 Subject: ARM: Introduce plat-tcc This patch introduces support for the tcc platform by creating an arch/arm/plat-tcc and arch/arm/mach-tcc8k directories and adding basic include files plus Kconfig and Makefile. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/Kconfig | 11 + arch/arm/Makefile | 2 + arch/arm/mach-tcc8k/Kconfig | 5 + arch/arm/plat-tcc/Kconfig | 20 + arch/arm/plat-tcc/Makefile | 3 + arch/arm/plat-tcc/include/mach/debug-macro.S | 33 ++ arch/arm/plat-tcc/include/mach/entry-macro.S | 68 +++ arch/arm/plat-tcc/include/mach/hardware.h | 43 ++ arch/arm/plat-tcc/include/mach/memory.h | 18 + arch/arm/plat-tcc/include/mach/system.h | 31 ++ arch/arm/plat-tcc/include/mach/tcc8k-regs.h | 796 +++++++++++++++++++++++++++ arch/arm/plat-tcc/include/mach/uncompress.h | 34 ++ arch/arm/plat-tcc/include/mach/vmalloc.h | 10 + arch/arm/plat-tcc/system.c | 25 + 14 files changed, 1099 insertions(+) create mode 100644 arch/arm/mach-tcc8k/Kconfig create mode 100644 arch/arm/plat-tcc/Kconfig create mode 100644 arch/arm/plat-tcc/Makefile create mode 100644 arch/arm/plat-tcc/include/mach/debug-macro.S create mode 100644 arch/arm/plat-tcc/include/mach/entry-macro.S create mode 100644 arch/arm/plat-tcc/include/mach/hardware.h create mode 100644 arch/arm/plat-tcc/include/mach/memory.h create mode 100644 arch/arm/plat-tcc/include/mach/system.h create mode 100644 arch/arm/plat-tcc/include/mach/tcc8k-regs.h create mode 100644 arch/arm/plat-tcc/include/mach/uncompress.h create mode 100644 arch/arm/plat-tcc/include/mach/vmalloc.h create mode 100644 arch/arm/plat-tcc/system.c (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 553b7cf17bfb..8d395352f1c9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -748,6 +748,15 @@ config ARCH_SHARK Support for the StrongARM based Digital DNARD machine, also known as "Shark" (). +config ARCH_TCC_926 + bool "Telechips TCC ARM926-based systems" + select CPU_ARM926T + select HAVE_CLK + select COMMON_CLKDEV + select GENERIC_CLOCKEVENTS + help + Support for Telechips TCC ARM926-based systems. + config ARCH_LH7A40X bool "Sharp LH7A40X" select CPU_ARM922T @@ -916,6 +925,8 @@ source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-spear/Kconfig" +source "arch/arm/plat-tcc/Kconfig" + if ARCH_S3C2410 source "arch/arm/mach-s3c2400/Kconfig" source "arch/arm/mach-s3c2410/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59c1ce858fc8..4e0b6c8d7ed3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_STMP378X) := stmp378x machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx +machine-$(CONFIG_ARCH_TCC8K) := tcc8k machine-$(CONFIG_ARCH_TEGRA) := tegra machine-$(CONFIG_ARCH_U300) := u300 machine-$(CONFIG_ARCH_U8500) := ux500 @@ -202,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_ARCH_S3C64XX) := samsung plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx +plat-$(CONFIG_ARCH_TCC_926) := tcc plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_NOMADIK) := nomadik plat-$(CONFIG_PLAT_ORION) := orion diff --git a/arch/arm/mach-tcc8k/Kconfig b/arch/arm/mach-tcc8k/Kconfig new file mode 100644 index 000000000000..ec7f71b17c06 --- /dev/null +++ b/arch/arm/mach-tcc8k/Kconfig @@ -0,0 +1,5 @@ +if ARCH_TCC8K + +comment "TCC8000 systems:" + +endif diff --git a/arch/arm/plat-tcc/Kconfig b/arch/arm/plat-tcc/Kconfig new file mode 100644 index 000000000000..1bf499570f42 --- /dev/null +++ b/arch/arm/plat-tcc/Kconfig @@ -0,0 +1,20 @@ +if ARCH_TCC_926 + +menu "Telechips ARM926-based CPUs" + +choice + prompt "Telechips CPU type:" + default ARCH_TCC8K + +config ARCH_TCC8K + bool TCC8000 + select USB_ARCH_HAS_OHCI + help + Support for Telechips TCC8000 systems + +endchoice + +source "arch/arm/mach-tcc8k/Kconfig" + +endmenu +endif diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile new file mode 100644 index 000000000000..3f2e4fe70d5a --- /dev/null +++ b/arch/arm/plat-tcc/Makefile @@ -0,0 +1,3 @@ +# "Telechips Platform Common Modules" + +obj-y := system.o diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S new file mode 100644 index 000000000000..97537845df64 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/debug-macro.S @@ -0,0 +1,33 @@ +/* + * Copyright (C) 1994-1999 Russell King + * Copyright (C) 2008-2009 Telechips + * Copyright (C) 2009 Hans J. Koch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + .macro addruart,rx,tmp + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x90000000 @ physical base address + movne \rx, #0xF1000000 @ virtual base + orr \rx, \rx, #0x00007000 @ UART0 + .endm + + .macro senduart,rd,rx + strb \rd, [\rx, #0x44] + .endm + + .macro waituart,rd,rx + .endm + + .macro busyuart,rd,rx +1001: + ldr \rd, [\rx, #0x14] + tst \rd, #0x20 + + beq 1001b + .endm diff --git a/arch/arm/plat-tcc/include/mach/entry-macro.S b/arch/arm/plat-tcc/include/mach/entry-macro.S new file mode 100644 index 000000000000..748f401e4b6d --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/entry-macro.S @@ -0,0 +1,68 @@ +/* + * include/asm-arm/arch-tcc83x/entry-macro.S + * + * Author : + * Created: June 10, 2008 + * Description: Low-level IRQ helper macros for Telechips-based platforms + * + * Copyright (C) 2008-2009 Telechips + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + ldr \base, =0xF2003000 @ base address of PIC registers + + @@ read MREQ register of PIC0 + + mov \irqnr, #0 + ldr \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts + cmp \irqstat, #0 + bne 1001f + + @@ read MREQ register of PIC1 + + ldr \irqstat, [\base, #0x00000094] @ upper 32 interrupts + cmp \irqstat, #0 + beq 1002f + mov \irqnr, #0x20 + +1001: + movs \tmp, \irqstat, lsl #16 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #16 + + movs \tmp, \irqstat, lsl #8 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #8 + + movs \tmp, \irqstat, lsl #4 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #4 + + movs \tmp, \irqstat, lsl #2 + movne \irqstat, \tmp + addeq \irqnr, \irqnr, #2 + + movs \tmp, \irqstat, lsl #1 + addeq \irqnr, \irqnr, #1 + orrs \base, \base, #1 +1002: + @@ exit here, Z flag unset if IRQ + + .endm diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h new file mode 100644 index 000000000000..e70d126ccaf3 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/hardware.h @@ -0,0 +1,43 @@ +/* + * Author: RidgeRun, Inc. Greg Lonnon + * Reorganized for Linux-2.6 by Tony Lindgren + * and Dirk Behme + * Rewritten by: + * Description: Hardware definitions for TCC8300 processors and boards + * + * Copyright (C) 2001 RidgeRun, Inc. + * Copyright (C) 2008-2009 Telechips + * + * Modifications for mainline (C) 2009 Hans J. Koch + * + * Licensed under the terms of the GNU Pulic License version 2. + */ + +#ifndef __ASM_ARCH_TCC_HARDWARE_H +#define __ASM_ARCH_TCC_HARDWARE_H + +#include +#ifndef __ASSEMBLER__ +#include +#endif +#include + +/* + * ---------------------------------------------------------------------------- + * Clocks + * ---------------------------------------------------------------------------- + */ +#define CLKGEN_REG_BASE 0xfffece00 +#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) +#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) +#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) +#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) +#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) +#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) +#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) +#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) + +/* DPLL control registers */ +#define DPLL_CTL 0xfffecf00 + +#endif /* __ASM_ARCH_TCC_HARDWARE_H */ diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h new file mode 100644 index 000000000000..cd91ba8a670b --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/memory.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 1999 ARM Limited + * Copyright (C) 2000 RidgeRun, Inc. + * Copyright (C) 2008-2009 Telechips + * Copyright (C) 2010 Hans J. Koch + * + * Licensed under the terms of the GPL v2. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/* + * Physical DRAM offset. + */ +#define PHYS_OFFSET UL(0x20000000) + +#endif diff --git a/arch/arm/plat-tcc/include/mach/system.h b/arch/arm/plat-tcc/include/mach/system.h new file mode 100644 index 000000000000..909e6035d843 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/system.h @@ -0,0 +1,31 @@ +/* + * Author: + * Created: June 10, 2008 + * Description: LINUX SYSTEM FUNCTIONS for TCC83x + * + * Copyright (C) 2008-2009 Telechips + * + * Licensed under the terms of the GPL v2. + * + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H +#include + +#include +#include + +extern void plat_tcc_reboot(void); + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + plat_tcc_reboot(); +} + +#endif diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h new file mode 100644 index 000000000000..f3243ebea463 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h @@ -0,0 +1,796 @@ +/* + * Telechips TCC8000 register definitions + * + * (C) 2009 Hans J. Koch + * + * Licensed under the terms of the GPLv2. + */ + +#ifndef TCC8K_REGS_H +#define TCC8K_REGS_H + +#include + +#define EXT_SDRAM_BASE 0x20000000 +#define INT_SRAM_BASE 0x30000000 +#define INT_SRAM_SIZE SZ_32K +#define CS0_BASE 0x40000000 +#define CS1_BASE 0x50000000 +#define CS1_SIZE SZ_64K +#define CS2_BASE 0x60000000 +#define CS3_BASE 0x70000000 +#define AHB_PERI_BASE 0x80000000 +#define AHB_PERI_SIZE SZ_64K +#define APB0_PERI_BASE 0x90000000 +#define APB0_PERI_SIZE SZ_128K +#define APB1_PERI_BASE 0x98000000 +#define APB1_PERI_SIZE SZ_128K +#define DATA_TCM_BASE 0xa0000000 +#define DATA_TCM_SIZE SZ_8K +#define EXT_MEM_CTRL_BASE 0xf0000000 +#define EXT_MEM_CTRL_SIZE SZ_4K + +#define CS1_BASE_VIRT 0xf7000000 +#define AHB_PERI_BASE_VIRT 0xf4000000 +#define APB0_PERI_BASE_VIRT 0xf1000000 +#define APB1_PERI_BASE_VIRT 0xf2000000 +#define EXT_MEM_CTRL_BASE_VIRT 0xf3000000 +#define INT_SRAM_BASE_VIRT 0xf5000000 +#define DATA_TCM_BASE_VIRT 0xf6000000 + +#define __REG(x) (*((volatile u32 *)(x))) + +/* USB Device Controller Registers */ +#define UDC_BASE (AHB_PERI_BASE_VIRT + 0x8000) +#define UDC_BASE_PHYS (AHB_PERI_BASE + 0x8000) + +#define UDC_IR_OFFS 0x00 +#define UDC_EIR_OFFS 0x04 +#define UDC_EIER_OFFS 0x08 +#define UDC_FAR_OFFS 0x0c +#define UDC_FNR_OFFS 0x10 +#define UDC_EDR_OFFS 0x14 +#define UDC_RT_OFFS 0x18 +#define UDC_SSR_OFFS 0x1c +#define UDC_SCR_OFFS 0x20 +#define UDC_EP0SR_OFFS 0x24 +#define UDC_EP0CR_OFFS 0x28 + +#define UDC_ESR_OFFS 0x2c +#define UDC_ECR_OFFS 0x30 +#define UDC_BRCR_OFFS 0x34 +#define UDC_BWCR_OFFS 0x38 +#define UDC_MPR_OFFS 0x3c +#define UDC_DCR_OFFS 0x40 +#define UDC_DTCR_OFFS 0x44 +#define UDC_DFCR_OFFS 0x48 +#define UDC_DTTCR1_OFFS 0x4c +#define UDC_DTTCR2_OFFS 0x50 +#define UDC_ESR2_OFFS 0x54 + +#define UDC_SCR2_OFFS 0x58 +#define UDC_EP0BUF_OFFS 0x60 +#define UDC_EP1BUF_OFFS 0x64 +#define UDC_EP2BUF_OFFS 0x68 +#define UDC_EP3BUF_OFFS 0x6c +#define UDC_PLICR_OFFS 0xa0 +#define UDC_PCR_OFFS 0xa4 + +#define UDC_UPCR0_OFFS 0xc8 +#define UDC_UPCR1_OFFS 0xcc +#define UDC_UPCR2_OFFS 0xd0 +#define UDC_UPCR3_OFFS 0xd4 + +/* Bits in UDC_EIR */ +#define UDC_EIR_EP0I (1 << 0) +#define UDC_EIR_EP1I (1 << 1) +#define UDC_EIR_EP2I (1 << 2) +#define UDC_EIR_EP3I (1 << 3) +#define UDC_EIR_EPI_MASK 0x0f + +/* Bits in UDC_EIER */ +#define UDC_EIER_EP0IE (1 << 0) +#define UDC_EIER_EP1IE (1 << 1) +#define UDC_EIER_EP2IE (1 << 2) +#define UDC_EIER_EP3IE (1 << 3) + +/* Bits in UDC_FNR */ +#define UDC_FNR_FN_MASK 0x7ff +#define UDC_FNR_SM (1 << 13) +#define UDC_FNR_FTL (1 << 14) + +/* Bits in UDC_SSR */ +#define UDC_SSR_HFRES (1 << 0) +#define UDC_SSR_HFSUSP (1 << 1) +#define UDC_SSR_HFRM (1 << 2) +#define UDC_SSR_SDE (1 << 3) +#define UDC_SSR_HSP (1 << 4) +#define UDC_SSR_DM (1 << 5) +#define UDC_SSR_DP (1 << 6) +#define UDC_SSR_TBM (1 << 7) +#define UDC_SSR_VBON (1 << 8) +#define UDC_SSR_VBOFF (1 << 9) +#define UDC_SSR_EOERR (1 << 10) +#define UDC_SSR_DCERR (1 << 11) +#define UDC_SSR_TCERR (1 << 12) +#define UDC_SSR_BSERR (1 << 13) +#define UDC_SSR_TMERR (1 << 14) +#define UDC_SSR_BAERR (1 << 15) + +/* Bits in UDC_SCR */ +#define UDC_SCR_HRESE (1 << 0) +#define UDC_SCR_HSSPE (1 << 1) +#define UDC_SCR_RRDE (1 << 5) +#define UDC_SCR_SPDEN (1 << 6) +#define UDC_SCR_DIEN (1 << 12) + +/* Bits in UDC_EP0SR */ +#define UDC_EP0SR_RSR (1 << 0) +#define UDC_EP0SR_TST (1 << 1) +#define UDC_EP0SR_SHT (1 << 4) +#define UDC_EP0SR_LWO (1 << 6) + +/* Bits in UDC_EP0CR */ +#define UDC_EP0CR_ESS (1 << 1) + +/* Bits in UDC_ESR */ +#define UDC_ESR_RPS (1 << 0) +#define UDC_ESR_TPS (1 << 1) +#define UDC_ESR_LWO (1 << 4) +#define UDC_ESR_FFS (1 << 6) + +/* Bits in UDC_ECR */ +#define UDC_ECR_ESS (1 << 1) +#define UDC_ECR_CDP (1 << 2) + +#define UDC_ECR_FLUSH (1 << 6) +#define UDC_ECR_DUEN (1 << 7) + +/* Bits in UDC_UPCR0 */ +#define UDC_UPCR0_VBD (1 << 1) +#define UDC_UPCR0_VBDS (1 << 6) +#define UDC_UPCR0_RCD_12 (0x0 << 9) +#define UDC_UPCR0_RCD_24 (0x1 << 9) +#define UDC_UPCR0_RCD_48 (0x2 << 9) +#define UDC_UPCR0_RCS_EXT (0x1 << 11) +#define UDC_UPCR0_RCS_XTAL (0x0 << 11) + +/* Bits in UDC_UPCR1 */ +#define UDC_UPCR1_CDT(x) ((x) << 0) +#define UDC_UPCR1_OTGT(x) ((x) << 3) +#define UDC_UPCR1_SQRXT(x) ((x) << 8) +#define UDC_UPCR1_TXFSLST(x) ((x) << 12) + +/* Bits in UDC_UPCR2 */ +#define UDC_UPCR2_TP (1 << 0) +#define UDC_UPCR2_TXRT(x) ((x) << 2) +#define UDC_UPCR2_TXVRT(x) ((x) << 5) +#define UDC_UPCR2_OPMODE(x) ((x) << 9) +#define UDC_UPCR2_XCVRSEL(x) ((x) << 12) +#define UDC_UPCR2_TM (1 << 14) + +/* USB Host Controller registers */ +#define USBH0_BASE (AHB_PERI_BASE_VIRT + 0xb000) +#define USBH1_BASE (AHB_PERI_BASE_VIRT + 0xb800) + +#define OHCI_INT_ENABLE_OFFS 0x10 + +#define RH_DESCRIPTOR_A_OFFS 0x48 +#define RH_DESCRIPTOR_B_OFFS 0x4c + +#define USBHTCFG0_OFFS 0x100 +#define USBHHCFG0_OFFS 0x104 +#define USBHHCFG1_OFFS 0x104 + +/* DMA controller registers */ +#define DMAC0_BASE (AHB_PERI_BASE + 0x4000) +#define DMAC1_BASE (AHB_PERI_BASE + 0xa000) +#define DMAC2_BASE (AHB_PERI_BASE + 0x4800) +#define DMAC3_BASE (AHB_PERI_BASE + 0xa800) + +#define DMAC_CH_OFFSET(ch) (ch * 0x30) + +#define ST_SADR_OFFS 0x00 +#define SPARAM_OFFS 0x04 +#define C_SADR_OFFS 0x0c +#define ST_DADR_OFFS 0x10 +#define DPARAM_OFFS 0x14 +#define C_DADR_OFFS 0x1c +#define HCOUNT_OFFS 0x20 +#define CHCTRL_OFFS 0x24 +#define RPTCTRL_OFFS 0x28 +#define EXTREQ_A_OFFS 0x2c + +/* Bits in CHCTRL register */ +#define CHCTRL_EN (1 << 0) + +#define CHCTRL_IEN (1 << 2) +#define CHCTRL_FLAG (1 << 3) +#define CHCTRL_WSIZE8 (0 << 4) +#define CHCTRL_WSIZE16 (1 << 4) +#define CHCTRL_WSIZE32 (2 << 4) + +#define CHCTRL_BSIZE1 (0 << 6) +#define CHCTRL_BSIZE2 (1 << 6) +#define CHCTRL_BSIZE4 (2 << 6) +#define CHCTRL_BSIZE8 (3 << 6) + +#define CHCTRL_TYPE_SINGLE_E (0 << 8) +#define CHCTRL_TYPE_HW (1 << 8) +#define CHCTRL_TYPE_SW (2 << 8) +#define CHCTRL_TYPE_SINGLE_L (3 << 8) + +#define CHCTRL_BST (1 << 10) + +/* Use DMA controller 0, channel 2 for USB */ +#define USB_DMA_BASE (DMAC0_BASE + DMAC_CH_OFFSET(2)) + +/* NAND flash controller registers */ +#define NFC_BASE (AHB_PERI_BASE_VIRT + 0xd000) +#define NFC_BASE_PHYS (AHB_PERI_BASE + 0xd000) + +#define NFC_CMD_OFFS 0x00 +#define NFC_LADDR_OFFS 0x04 +#define NFC_BADDR_OFFS 0x08 +#define NFC_SADDR_OFFS 0x0c +#define NFC_WDATA_OFFS 0x10 +#define NFC_LDATA_OFFS 0x20 +#define NFC_SDATA_OFFS 0x40 +#define NFC_CTRL_OFFS 0x50 +#define NFC_PSTART_OFFS 0x54 +#define NFC_RSTART_OFFS 0x58 +#define NFC_DSIZE_OFFS 0x5c +#define NFC_IREQ_OFFS 0x60 +#define NFC_RST_OFFS 0x64 +#define NFC_CTRL1_OFFS 0x68 +#define NFC_MDATA_OFFS 0x70 + +#define NFC_WDATA_PHYS_ADDR (NFC_BASE_PHYS + NFC_WDATA_OFFS) + +/* Bits in NFC_CTRL */ +#define NFC_CTRL_BHLD_MASK (0xf << 0) +#define NFC_CTRL_BPW_MASK (0xf << 4) +#define NFC_CTRL_BSTP_MASK (0xf << 8) +#define NFC_CTRL_CADDR_MASK (0x7 << 12) +#define NFC_CTRL_CADDR_1 (0x0 << 12) +#define NFC_CTRL_CADDR_2 (0x1 << 12) +#define NFC_CTRL_CADDR_3 (0x2 << 12) +#define NFC_CTRL_CADDR_4 (0x3 << 12) +#define NFC_CTRL_CADDR_5 (0x4 << 12) +#define NFC_CTRL_MSK (1 << 15) +#define NFC_CTRL_PSIZE256 (0 << 16) +#define NFC_CTRL_PSIZE512 (1 << 16) +#define NFC_CTRL_PSIZE1024 (2 << 16) +#define NFC_CTRL_PSIZE2048 (3 << 16) +#define NFC_CTRL_PSIZE4096 (4 << 16) +#define NFC_CTRL_PSIZE_MASK (7 << 16) +#define NFC_CTRL_BSIZE1 (0 << 19) +#define NFC_CTRL_BSIZE2 (1 << 19) +#define NFC_CTRL_BSIZE4 (2 << 19) +#define NFC_CTRL_BSIZE8 (3 << 19) +#define NFC_CTRL_BSIZE_MASK (3 << 19) +#define NFC_CTRL_RDY (1 << 21) +#define NFC_CTRL_CS0SEL (1 << 22) +#define NFC_CTRL_CS1SEL (1 << 23) +#define NFC_CTRL_CS2SEL (1 << 24) +#define NFC_CTRL_CS3SEL (1 << 25) +#define NFC_CTRL_CSMASK (0xf << 22) +#define NFC_CTRL_BW (1 << 26) +#define NFC_CTRL_FS (1 << 27) +#define NFC_CTRL_DEN (1 << 28) +#define NFC_CTRL_READ_IEN (1 << 29) +#define NFC_CTRL_PROG_IEN (1 << 30) +#define NFC_CTRL_RDY_IEN (1 << 31) + +/* Bits in NFC_IREQ */ +#define NFC_IREQ_IRQ0 (1 << 0) +#define NFC_IREQ_IRQ1 (1 << 1) +#define NFC_IREQ_IRQ2 (1 << 2) + +#define NFC_IREQ_FLAG0 (1 << 4) +#define NFC_IREQ_FLAG1 (1 << 5) +#define NFC_IREQ_FLAG2 (1 << 6) + +/* MMC controller registers */ +#define MMC0_BASE (AHB_PERI_BASE_VIRT + 0xe000) +#define MMC1_BASE (AHB_PERI_BASE_VIRT + 0xe800) + +/* UART base addresses */ + +#define UART0_BASE (APB0_PERI_BASE_VIRT + 0x07000) +#define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000) +#define UART1_BASE (APB0_PERI_BASE_VIRT + 0x08000) +#define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000) +#define UART2_BASE (APB0_PERI_BASE_VIRT + 0x09000) +#define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000) +#define UART3_BASE (APB0_PERI_BASE_VIRT + 0x0a000) +#define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000) +#define UART4_BASE (APB0_PERI_BASE_VIRT + 0x15000) +#define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000) + +#define UART_BASE UART0_BASE +#define UART_BASE_PHYS UART0_BASE_PHYS + +/* ECC controller */ +#define ECC_CTR_BASE (APB0_PERI_BASE_VIRT + 0xd000) + +#define ECC_CTRL_OFFS 0x00 +#define ECC_BASE_OFFS 0x04 +#define ECC_MASK_OFFS 0x08 +#define ECC_CLEAR_OFFS 0x0c +#define ECC4_0_OFFS 0x10 +#define ECC4_1_OFFS 0x14 + +#define ECC_EADDR0_OFFS 0x50 + +#define ECC_ERRNUM_OFFS 0x90 +#define ECC_IREQ_OFFS 0x94 + +/* Bits in ECC_CTRL */ +#define ECC_CTRL_ECC4_DIEN (1 << 28) +#define ECC_CTRL_ECC8_DIEN (1 << 29) +#define ECC_CTRL_ECC12_DIEN (1 << 30) +#define ECC_CTRL_ECC_DISABLE 0x0 +#define ECC_CTRL_ECC_SLC_ENC 0x8 +#define ECC_CTRL_ECC_SLC_DEC 0x9 +#define ECC_CTRL_ECC4_ENC 0xa +#define ECC_CTRL_ECC4_DEC 0xb +#define ECC_CTRL_ECC8_ENC 0xc +#define ECC_CTRL_ECC8_DEC 0xd +#define ECC_CTRL_ECC12_ENC 0xe +#define ECC_CTRL_ECC12_DEC 0xf + +/* Bits in ECC_IREQ */ +#define ECC_IREQ_E4DI (1 << 4) + +#define ECC_IREQ_E4DF (1 << 20) +#define ECC_IREQ_E4EF (1 << 21) + +/* Interrupt controller */ + +#define PIC0_BASE (APB1_PERI_BASE_VIRT + 0x3000) +#define PIC0_BASE_PHYS (APB1_PERI_BASE + 0x3000) + +#define PIC0_IEN_OFFS 0x00 +#define PIC0_CREQ_OFFS 0x04 +#define PIC0_IREQ_OFFS 0x08 +#define PIC0_IRQSEL_OFFS 0x0c +#define PIC0_SRC_OFFS 0x10 +#define PIC0_MREQ_OFFS 0x14 +#define PIC0_TSTREQ_OFFS 0x18 +#define PIC0_POL_OFFS 0x1c +#define PIC0_IRQ_OFFS 0x20 +#define PIC0_FIQ_OFFS 0x24 +#define PIC0_MIRQ_OFFS 0x28 +#define PIC0_MFIQ_OFFS 0x2c +#define PIC0_TMODE_OFFS 0x30 +#define PIC0_SYNC_OFFS 0x34 +#define PIC0_WKUP_OFFS 0x38 +#define PIC0_TMODEA_OFFS 0x3c +#define PIC0_INTOEN_OFFS 0x40 +#define PIC0_MEN0_OFFS 0x44 +#define PIC0_MEN_OFFS 0x48 + +#define PIC0_IEN __REG(PIC0_BASE + PIC0_IEN_OFFS) +#define PIC0_IEN_PHYS __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS) +#define PIC0_CREQ __REG(PIC0_BASE + PIC0_CREQ_OFFS) +#define PIC0_CREQ_PHYS __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS) +#define PIC0_IREQ __REG(PIC0_BASE + PIC0_IREQ_OFFS) +#define PIC0_IRQSEL __REG(PIC0_BASE + PIC0_IRQSEL_OFFS) +#define PIC0_IRQSEL_PHYS __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS) +#define PIC0_SRC __REG(PIC0_BASE + PIC0_SRC_OFFS) +#define PIC0_MREQ __REG(PIC0_BASE + PIC0_MREQ_OFFS) +#define PIC0_TSTREQ __REG(PIC0_BASE + PIC0_TSTREQ_OFFS) +#define PIC0_POL __REG(PIC0_BASE + PIC0_POL_OFFS) +#define PIC0_IRQ __REG(PIC0_BASE + PIC0_IRQ_OFFS) +#define PIC0_FIQ __REG(PIC0_BASE + PIC0_FIQ_OFFS) +#define PIC0_MIRQ __REG(PIC0_BASE + PIC0_MIRQ_OFFS) +#define PIC0_MFIQ __REG(PIC0_BASE + PIC0_MFIQ_OFFS) +#define PIC0_TMODE __REG(PIC0_BASE + PIC0_TMODE_OFFS) +#define PIC0_TMODE_PHYS __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS) +#define PIC0_SYNC __REG(PIC0_BASE + PIC0_SYNC_OFFS) +#define PIC0_WKUP __REG(PIC0_BASE + PIC0_WKUP_OFFS) +#define PIC0_TMODEA __REG(PIC0_BASE + PIC0_TMODEA_OFFS) +#define PIC0_INTOEN __REG(PIC0_BASE + PIC0_INTOEN_OFFS) +#define PIC0_MEN0 __REG(PIC0_BASE + PIC0_MEN0_OFFS) +#define PIC0_MEN __REG(PIC0_BASE + PIC0_MEN_OFFS) + +#define PIC1_BASE (APB1_PERI_BASE_VIRT + 0x3080) + +#define PIC1_IEN_OFFS 0x00 +#define PIC1_CREQ_OFFS 0x04 +#define PIC1_IREQ_OFFS 0x08 +#define PIC1_IRQSEL_OFFS 0x0c +#define PIC1_SRC_OFFS 0x10 +#define PIC1_MREQ_OFFS 0x14 +#define PIC1_TSTREQ_OFFS 0x18 +#define PIC1_POL_OFFS 0x1c +#define PIC1_IRQ_OFFS 0x20 +#define PIC1_FIQ_OFFS 0x24 +#define PIC1_MIRQ_OFFS 0x28 +#define PIC1_MFIQ_OFFS 0x2c +#define PIC1_TMODE_OFFS 0x30 +#define PIC1_SYNC_OFFS 0x34 +#define PIC1_WKUP_OFFS 0x38 +#define PIC1_TMODEA_OFFS 0x3c +#define PIC1_INTOEN_OFFS 0x40 +#define PIC1_MEN1_OFFS 0x44 +#define PIC1_MEN_OFFS 0x48 + +#define PIC1_IEN __REG(PIC1_BASE + PIC1_IEN_OFFS) +#define PIC1_CREQ __REG(PIC1_BASE + PIC1_CREQ_OFFS) +#define PIC1_IREQ __REG(PIC1_BASE + PIC1_IREQ_OFFS) +#define PIC1_IRQSEL __REG(PIC1_BASE + PIC1_IRQSEL_OFFS) +#define PIC1_SRC __REG(PIC1_BASE + PIC1_SRC_OFFS) +#define PIC1_MREQ __REG(PIC1_BASE + PIC1_MREQ_OFFS) +#define PIC1_TSTREQ __REG(PIC1_BASE + PIC1_TSTREQ_OFFS) +#define PIC1_POL __REG(PIC1_BASE + PIC1_POL_OFFS) +#define PIC1_IRQ __REG(PIC1_BASE + PIC1_IRQ_OFFS) +#define PIC1_FIQ __REG(PIC1_BASE + PIC1_FIQ_OFFS) +#define PIC1_MIRQ __REG(PIC1_BASE + PIC1_MIRQ_OFFS) +#define PIC1_MFIQ __REG(PIC1_BASE + PIC1_MFIQ_OFFS) +#define PIC1_TMODE __REG(PIC1_BASE + PIC1_TMODE_OFFS) +#define PIC1_SYNC __REG(PIC1_BASE + PIC1_SYNC_OFFS) +#define PIC1_WKUP __REG(PIC1_BASE + PIC1_WKUP_OFFS) +#define PIC1_TMODEA __REG(PIC1_BASE + PIC1_TMODEA_OFFS) +#define PIC1_INTOEN __REG(PIC1_BASE + PIC1_INTOEN_OFFS) +#define PIC1_MEN1 __REG(PIC1_BASE + PIC1_MEN1_OFFS) +#define PIC1_MEN __REG(PIC1_BASE + PIC1_MEN_OFFS) + +/* Timer registers */ +#define TIMER_BASE (APB1_PERI_BASE_VIRT + 0x4000) +#define TIMER_BASE_PHYS (APB1_PERI_BASE + 0x4000) + +#define TWDCFG_OFFS 0x70 + +#define TC32EN_OFFS 0x80 +#define TC32LDV_OFFS 0x84 +#define TC32CMP0_OFFS 0x88 +#define TC32CMP1_OFFS 0x8c +#define TC32PCNT_OFFS 0x90 +#define TC32MCNT_OFFS 0x94 +#define TC32IRQ_OFFS 0x98 + +/* Bits in TC32EN */ +#define TC32EN_PRESCALE_MASK 0x00ffffff +#define TC32EN_ENABLE (1 << 24) +#define TC32EN_LOADZERO (1 << 25) +#define TC32EN_STOPMODE (1 << 26) +#define TC32EN_LDM0 (1 << 28) +#define TC32EN_LDM1 (1 << 29) + +/* Bits in TC32IRQ */ +#define TC32IRQ_MSTAT_MASK 0x0000001f +#define TC32IRQ_RSTAT_MASK (0x1f << 8) +#define TC32IRQ_IRQEN0 (1 << 16) +#define TC32IRQ_IRQEN1 (1 << 17) +#define TC32IRQ_IRQEN2 (1 << 18) +#define TC32IRQ_IRQEN3 (1 << 19) +#define TC32IRQ_IRQEN4 (1 << 20) +#define TC32IRQ_RSYNC (1 << 30) +#define TC32IRQ_IRQCLR (1 << 31) + +/* GPIO registers */ +#define GPIOPD_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOPD_DAT_OFFS 0x00 +#define GPIOPD_DOE_OFFS 0x04 +#define GPIOPD_FS0_OFFS 0x08 +#define GPIOPD_FS1_OFFS 0x0c +#define GPIOPD_FS2_OFFS 0x10 +#define GPIOPD_RPU_OFFS 0x30 +#define GPIOPD_RPD_OFFS 0x34 +#define GPIOPD_DV0_OFFS 0x38 +#define GPIOPD_DV1_OFFS 0x3c + +#define GPIOPS_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOPS_DAT_OFFS 0x40 +#define GPIOPS_DOE_OFFS 0x44 +#define GPIOPS_FS0_OFFS 0x48 +#define GPIOPS_FS1_OFFS 0x4c +#define GPIOPS_FS2_OFFS 0x50 +#define GPIOPS_FS3_OFFS 0x54 +#define GPIOPS_RPU_OFFS 0x70 +#define GPIOPS_RPD_OFFS 0x74 +#define GPIOPS_DV0_OFFS 0x78 +#define GPIOPS_DV1_OFFS 0x7c + +#define GPIOPS_FS1_SDH0_BITS 0x000000ff +#define GPIOPS_FS1_SDH1_BITS 0x0000ff00 + +#define GPIOPU_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOPU_DAT_OFFS 0x80 +#define GPIOPU_DOE_OFFS 0x84 +#define GPIOPU_FS0_OFFS 0x88 +#define GPIOPU_FS1_OFFS 0x8c +#define GPIOPU_FS2_OFFS 0x90 +#define GPIOPU_RPU_OFFS 0xb0 +#define GPIOPU_RPD_OFFS 0xb4 +#define GPIOPU_DV0_OFFS 0xb8 +#define GPIOPU_DV1_OFFS 0xbc + +#define GPIOPU_FS0_TXD0 (1 << 0) +#define GPIOPU_FS0_RXD0 (1 << 1) +#define GPIOPU_FS0_CTS0 (1 << 2) +#define GPIOPU_FS0_RTS0 (1 << 3) +#define GPIOPU_FS0_TXD1 (1 << 4) +#define GPIOPU_FS0_RXD1 (1 << 5) +#define GPIOPU_FS0_CTS1 (1 << 6) +#define GPIOPU_FS0_RTS1 (1 << 7) +#define GPIOPU_FS0_TXD2 (1 << 8) +#define GPIOPU_FS0_RXD2 (1 << 9) +#define GPIOPU_FS0_CTS2 (1 << 10) +#define GPIOPU_FS0_RTS2 (1 << 11) +#define GPIOPU_FS0_TXD3 (1 << 12) +#define GPIOPU_FS0_RXD3 (1 << 13) +#define GPIOPU_FS0_CTS3 (1 << 14) +#define GPIOPU_FS0_RTS3 (1 << 15) +#define GPIOPU_FS0_TXD4 (1 << 16) +#define GPIOPU_FS0_RXD4 (1 << 17) +#define GPIOPU_FS0_CTS4 (1 << 18) +#define GPIOPU_FS0_RTS4 (1 << 19) + +#define GPIOFC_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOFC_DAT_OFFS 0xc0 +#define GPIOFC_DOE_OFFS 0xc4 +#define GPIOFC_FS0_OFFS 0xc8 +#define GPIOFC_FS1_OFFS 0xcc +#define GPIOFC_FS2_OFFS 0xd0 +#define GPIOFC_FS3_OFFS 0xd4 +#define GPIOFC_RPU_OFFS 0xf0 +#define GPIOFC_RPD_OFFS 0xf4 +#define GPIOFC_DV0_OFFS 0xf8 +#define GPIOFC_DV1_OFFS 0xfc + +#define GPIOFD_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOFD_DAT_OFFS 0x100 +#define GPIOFD_DOE_OFFS 0x104 +#define GPIOFD_FS0_OFFS 0x108 +#define GPIOFD_FS1_OFFS 0x10c +#define GPIOFD_FS2_OFFS 0x110 +#define GPIOFD_RPU_OFFS 0x130 +#define GPIOFD_RPD_OFFS 0x134 +#define GPIOFD_DV0_OFFS 0x138 +#define GPIOFD_DV1_OFFS 0x13c + +#define GPIOLC_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOLC_DAT_OFFS 0x140 +#define GPIOLC_DOE_OFFS 0x144 +#define GPIOLC_FS0_OFFS 0x148 +#define GPIOLC_FS1_OFFS 0x14c +#define GPIOLC_RPU_OFFS 0x170 +#define GPIOLC_RPD_OFFS 0x174 +#define GPIOLC_DV0_OFFS 0x178 +#define GPIOLC_DV1_OFFS 0x17c + +#define GPIOLD_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOLD_DAT_OFFS 0x180 +#define GPIOLD_DOE_OFFS 0x184 +#define GPIOLD_FS0_OFFS 0x188 +#define GPIOLD_FS1_OFFS 0x18c +#define GPIOLD_FS2_OFFS 0x190 +#define GPIOLD_RPU_OFFS 0x1b0 +#define GPIOLD_RPD_OFFS 0x1b4 +#define GPIOLD_DV0_OFFS 0x1b8 +#define GPIOLD_DV1_OFFS 0x1bc + +#define GPIOAD_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOAD_DAT_OFFS 0x1c0 +#define GPIOAD_DOE_OFFS 0x1c4 +#define GPIOAD_FS0_OFFS 0x1c8 +#define GPIOAD_RPU_OFFS 0x1f0 +#define GPIOAD_RPD_OFFS 0x1f4 +#define GPIOAD_DV0_OFFS 0x1f8 +#define GPIOAD_DV1_OFFS 0x1fc + +#define GPIOXC_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOXC_DAT_OFFS 0x200 +#define GPIOXC_DOE_OFFS 0x204 +#define GPIOXC_FS0_OFFS 0x208 +#define GPIOXC_RPU_OFFS 0x230 +#define GPIOXC_RPD_OFFS 0x234 +#define GPIOXC_DV0_OFFS 0x238 +#define GPIOXC_DV1_OFFS 0x23c + +#define GPIOXC_FS0 __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS) + +#define GPIOXC_FS0_CS0 (1 << 26) +#define GPIOXC_FS0_CS1 (1 << 27) + +#define GPIOXD_BASE (APB1_PERI_BASE_VIRT + 0x5000) + +#define GPIOXD_DAT_OFFS 0x240 +#define GPIOXD_FS0_OFFS 0x248 +#define GPIOXD_RPU_OFFS 0x270 +#define GPIOXD_RPD_OFFS 0x274 +#define GPIOXD_DV0_OFFS 0x278 +#define GPIOXD_DV1_OFFS 0x27c + +#define GPIOPK_BASE (APB1_PERI_BASE_VIRT + 0x1c000) + +#define GPIOPK_RST_OFFS 0x008 +#define GPIOPK_DAT_OFFS 0x100 +#define GPIOPK_DOE_OFFS 0x104 +#define GPIOPK_FS0_OFFS 0x108 +#define GPIOPK_FS1_OFFS 0x10c +#define GPIOPK_FS2_OFFS 0x110 +#define GPIOPK_IRQST_OFFS 0x210 +#define GPIOPK_IRQEN_OFFS 0x214 +#define GPIOPK_IRQPOL_OFFS 0x218 +#define GPIOPK_IRQTM0_OFFS 0x21c +#define GPIOPK_IRQTM1_OFFS 0x220 +#define GPIOPK_CTL_OFFS 0x22c + +#define PMGPIO_BASE (APB1_PERI_BASE_VIRT + 0x10000) +#define BACKUP_RAM_BASE PMGPIO_BASE + +#define PMGPIO_DAT_OFFS 0x800 +#define PMGPIO_DOE_OFFS 0x804 +#define PMGPIO_FS0_OFFS 0x808 +#define PMGPIO_RPU_OFFS 0x810 +#define PMGPIO_RPD_OFFS 0x814 +#define PMGPIO_DV0_OFFS 0x818 +#define PMGPIO_DV1_OFFS 0x81c +#define PMGPIO_EE0_OFFS 0x820 +#define PMGPIO_EE1_OFFS 0x824 +#define PMGPIO_CTL_OFFS 0x828 +#define PMGPIO_DI_OFFS 0x82c +#define PMGPIO_STR_OFFS 0x830 +#define PMGPIO_STF_OFFS 0x834 +#define PMGPIO_POL_OFFS 0x838 +#define PMGPIO_APB_OFFS 0x800 + +/* Clock controller registers */ +#define CKC_BASE (APB1_PERI_BASE_VIRT + 0x6000) +#define CKC_BASE_PHYS (APB1_PERI_BASE + 0x6000) + +#define CLKCTRL_OFFS 0x00 +#define PLL0CFG_OFFS 0x04 +#define PLL1CFG_OFFS 0x08 +#define CLKDIVC0_OFFS 0x0c + +#define BCLKCTR0_OFFS 0x14 +#define SWRESET0_OFFS 0x18 + +#define BCLKCTR1_OFFS 0x60 +#define SWRESET1_OFFS 0x64 +#define PWDCTL_OFFS 0x68 +#define PLL2CFG_OFFS 0x6c +#define CLKDIVC1_OFFS 0x70 + +#define ACLKREF_OFFS 0x80 +#define ACLKI2C_OFFS 0x84 +#define ACLKSPI0_OFFS 0x88 +#define ACLKSPI1_OFFS 0x8c +#define ACLKUART0_OFFS 0x90 +#define ACLKUART1_OFFS 0x94 +#define ACLKUART2_OFFS 0x98 +#define ACLKUART3_OFFS 0x9c +#define ACLKUART4_OFFS 0xa0 +#define ACLKTCT_OFFS 0xa4 +#define ACLKTCX_OFFS 0xa8 +#define ACLKTCZ_OFFS 0xac +#define ACLKADC_OFFS 0xb0 +#define ACLKDAI0_OFFS 0xb4 +#define ACLKDAI1_OFFS 0xb8 +#define ACLKLCD_OFFS 0xbc +#define ACLKSPDIF_OFFS 0xc0 +#define ACLKUSBH_OFFS 0xc4 +#define ACLKSDH0_OFFS 0xc8 +#define ACLKSDH1_OFFS 0xcc +#define ACLKC3DEC_OFFS 0xd0 +#define ACLKEXT_OFFS 0xd4 +#define ACLKCAN0_OFFS 0xd8 +#define ACLKCAN1_OFFS 0xdc +#define ACLKGSB0_OFFS 0xe0 +#define ACLKGSB1_OFFS 0xe4 +#define ACLKGSB2_OFFS 0xe8 +#define ACLKGSB3_OFFS 0xec + +#define PLLxCFG_PD (1 << 31) + +/* CLKCTRL bits */ +#define CLKCTRL_XE (1 << 31) + +/* CLKDIVCx bits */ +#define CLKDIVC0_XTE (1 << 7) +#define CLKDIVC0_XE (1 << 15) +#define CLKDIVC0_P1E (1 << 23) +#define CLKDIVC0_P0E (1 << 31) + +#define CLKDIVC1_P2E (1 << 7) + +/* BCLKCTR0 clock bits */ +#define BCLKCTR0_USBD (1 << 4) +#define BCLKCTR0_ECC (1 << 9) +#define BCLKCTR0_USBH0 (1 << 11) +#define BCLKCTR0_NFC (1 << 16) + +/* BCLKCTR1 clock bits */ +#define BCLKCTR1_USBH1 (1 << 20) + +/* SWRESET0 bits */ +#define SWRESET0_USBD (1 << 4) +#define SWRESET0_USBH0 (1 << 11) + +/* SWRESET1 bits */ +#define SWRESET1_USBH1 (1 << 20) + +/* System clock sources */ +enum root_clks { + CLK_SRC_PLL0 = 0, + CLK_SRC_PLL1, + CLK_SRC_PLL0DIV, + CLK_SRC_PLL1DIV, + CLK_SRC_XI, + CLK_SRC_XIDIV, + CLK_SRC_XTI, + CLK_SRC_XTIDIV, + CLK_SRC_PLL2, + CLK_SRC_PLL2DIV, + CLK_SRC_PK0, + CLK_SRC_PK1, + CLK_SRC_PK2, + CLK_SRC_PK3, + CLK_SRC_PK4, + CLK_SRC_48MHZ +}; + +#define CLK_SRC_MASK 0xf + +/* Bits in ACLK* registers */ +#define ACLK_EN (1 << 28) +#define ACLK_SEL_SHIFT 24 +#define ACLK_SEL_MASK 0x0f000000 +#define ACLK_DIV_MASK 0x00000fff + +/* System configuration registers */ + +#define SCFG_BASE (APB1_PERI_BASE_VIRT + 0x13000) + +#define BMI_OFFS 0x00 +#define AHBCON0_OFFS 0x04 +#define APBPWE_OFFS 0x08 +#define DTCMWAIT_OFFS 0x0c +#define ECCSEL_OFFS 0x10 +#define AHBCON1_OFFS 0x14 +#define SDHCFG_OFFS 0x18 +#define REMAP_OFFS 0x20 +#define LCDSIAE_OFFS 0x24 +#define XMCCFG_OFFS 0xe0 +#define IMCCFG_OFFS 0xe4 + +/* Values for ECCSEL */ +#define ECCSEL_EXTMEM 0x0 +#define ECCSEL_DTCM 0x1 +#define ECCSEL_INT_SRAM 0x2 +#define ECCSEL_AHB 0x3 + +/* Bits in XMCCFG */ +#define XMCCFG_NFCE (1 << 1) +#define XMCCFG_FDXD (1 << 2) + +/* External memory controller registers */ + +#define EMC_BASE EXT_MEM_CTRL_BASE + +#define SDCFG_OFFS 0x00 +#define SDFSM_OFFS 0x04 +#define MCFG_OFFS 0x08 + +#define CSCFG0_OFFS 0x10 +#define CSCFG1_OFFS 0x14 +#define CSCFG2_OFFS 0x18 +#define CSCFG3_OFFS 0x1c + +#define MCFG_SDEN (1 << 4) + +#endif /* TCC8K_REGS_H */ diff --git a/arch/arm/plat-tcc/include/mach/uncompress.h b/arch/arm/plat-tcc/include/mach/uncompress.h new file mode 100644 index 000000000000..7a3e33a27a30 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/uncompress.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009 Hans J. Koch + * + * This file is licensed under the terms of the GPL version 2. + */ + +#include +#include + +#include + +unsigned int system_rev; + +#define ID_MASK 0x7fff + +static void putc(int c) +{ + u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2)); + u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2)); + + while (!(*uart_lsr & UART_LSR_THRE)) + barrier(); + *uart_tx = c; +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h new file mode 100644 index 000000000000..99414d9c2b94 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/vmalloc.h @@ -0,0 +1,10 @@ +/* + * Author: + * Created: June 10, 2008 + * + * Copyright (C) 2000 Russell King. + * Copyright (C) 2008-2009 Telechips + * + * Licensed under the terms of the GPL v2. + */ +#define VMALLOC_END 0xf0000000UL diff --git a/arch/arm/plat-tcc/system.c b/arch/arm/plat-tcc/system.c new file mode 100644 index 000000000000..cc208fae3e7a --- /dev/null +++ b/arch/arm/plat-tcc/system.c @@ -0,0 +1,25 @@ +/* + * System functions for Telechips TCCxxxx SoCs + * + * Copyright (C) Hans J. Koch + * + * Licensed under the terms of the GPL v2. + * + */ + +#include + +#include + +/* System reboot */ +void plat_tcc_reboot(void) +{ + /* Make sure clocks are on */ + __raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS); + + /* Enable watchdog reset */ + __raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS); + /* Wait for reset */ + while(1) + ; +} -- cgit v1.2.3 From da15797eaec795bc2a1a9adb441214a6f5ea07fc Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:15:11 +0200 Subject: ARM: Add the clock framework for Telechips TCC8xxx processors. This adds definitions and low-level functions to handle clocks in TCC8xxx processors. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/Makefile | 6 + arch/arm/mach-tcc8k/clock.c | 566 ++++++++++++++++++++++++++++ arch/arm/mach-tcc8k/common.h | 6 + arch/arm/plat-tcc/Makefile | 2 +- arch/arm/plat-tcc/clock.c | 179 +++++++++ arch/arm/plat-tcc/include/mach/clkdev.h | 7 + arch/arm/plat-tcc/include/mach/clock.h | 48 +++ arch/arm/plat-tcc/include/mach/tcc8k-regs.h | 31 +- 8 files changed, 834 insertions(+), 11 deletions(-) create mode 100644 arch/arm/mach-tcc8k/Makefile create mode 100644 arch/arm/mach-tcc8k/clock.c create mode 100644 arch/arm/mach-tcc8k/common.h create mode 100644 arch/arm/plat-tcc/clock.c create mode 100644 arch/arm/plat-tcc/include/mach/clkdev.h create mode 100644 arch/arm/plat-tcc/include/mach/clock.h (limited to 'arch/arm') diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile new file mode 100644 index 000000000000..805d850919eb --- /dev/null +++ b/arch/arm/mach-tcc8k/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for TCC8K boards and common files. +# + +# Common support +obj-y += clock.o diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c new file mode 100644 index 000000000000..a8982af15326 --- /dev/null +++ b/arch/arm/mach-tcc8k/clock.c @@ -0,0 +1,566 @@ +/* + * Lowlevel clock handling for Telechips TCC8xxx SoCs + * + * Copyright (C) 2010 by Hans J. Koch + * + * Licensed under the terms of the GPL v2 + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "common.h" + +#define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS) +#define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS) + +#define ACLKREF (CKC_BASE + ACLKREF_OFFS) +#define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS) +#define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS) +#define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS) +#define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS) +#define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS) +#define ACLKI2C (CKC_BASE + ACLKI2C_OFFS) +#define ACLKADC (CKC_BASE + ACLKADC_OFFS) +#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) +#define ACLKLCD (CKC_BASE + ACLKLCD_OFFS) +#define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS) +#define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS) +#define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS) +#define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS) +#define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS) +#define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS) +#define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS) +#define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS) +#define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS) +#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS) +#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS) +#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS) +#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS) +#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS) +#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS) +#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS) + +/* Crystal frequencies */ +static unsigned long xi_rate, xti_rate; + +static void __iomem *pll_cfg_addr(int pll) +{ + switch (pll) { + case 0: return (CKC_BASE + PLL0CFG_OFFS); + case 1: return (CKC_BASE + PLL1CFG_OFFS); + case 2: return (CKC_BASE + PLL2CFG_OFFS); + default: + BUG(); + } +} + +static int pll_enable(int pll, int enable) +{ + u32 reg; + void __iomem *addr = pll_cfg_addr(pll); + + reg = __raw_readl(addr); + if (enable) + reg &= ~PLLxCFG_PD; + else + reg |= PLLxCFG_PD; + + __raw_writel(reg, addr); + return 0; +} + +static int xi_enable(int enable) +{ + u32 reg; + + reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); + if (enable) + reg |= CLKCTRL_XE; + else + reg &= ~CLKCTRL_XE; + + __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS); + return 0; +} + +static int root_clk_enable(enum root_clks src) +{ + switch (src) { + case CLK_SRC_PLL0: return pll_enable(0, 1); + case CLK_SRC_PLL1: return pll_enable(1, 1); + case CLK_SRC_PLL2: return pll_enable(2, 1); + case CLK_SRC_XI: return xi_enable(1); + default: + BUG(); + } + return 0; +} + +static int root_clk_disable(enum root_clks root_src) +{ + switch (root_src) { + case CLK_SRC_PLL0: return pll_enable(0, 0); + case CLK_SRC_PLL1: return pll_enable(1, 0); + case CLK_SRC_PLL2: return pll_enable(2, 0); + case CLK_SRC_XI: return xi_enable(0); + default: + BUG(); + } + return 0; +} + +static int enable_clk(struct clk *clk) +{ + u32 reg; + + if (clk->root_id != CLK_SRC_NOROOT) + return root_clk_enable(clk->root_id); + + if (clk->aclkreg) { + reg = __raw_readl(clk->aclkreg); + reg |= ACLK_EN; + __raw_writel(reg, clk->aclkreg); + } + if (clk->bclkctr) { + reg = __raw_readl(clk->bclkctr); + reg |= 1 << clk->bclk_shift; + __raw_writel(reg, clk->bclkctr); + } + return 0; +} + +static void disable_clk(struct clk *clk) +{ + u32 reg; + + if (clk->root_id != CLK_SRC_NOROOT) { + root_clk_disable(clk->root_id); + return; + } + + if (clk->bclkctr) { + reg = __raw_readl(clk->bclkctr); + reg &= ~(1 << clk->bclk_shift); + __raw_writel(reg, clk->bclkctr); + } + if (clk->aclkreg) { + reg = __raw_readl(clk->aclkreg); + reg &= ~ACLK_EN; + __raw_writel(reg, clk->aclkreg); + } +} + +static unsigned long get_rate_pll(int pll) +{ + u32 reg; + unsigned long s, m, p; + void __iomem *addr = pll_cfg_addr(pll); + + reg = __raw_readl(addr); + s = (reg >> 16) & 0x07; + m = (reg >> 8) & 0xff; + p = reg & 0x3f; + + return (m * xi_rate) / (p * (1 << s)); +} + +static unsigned long get_rate_pll_div(int pll) +{ + u32 reg; + unsigned long div = 0; + void __iomem *addr; + + switch (pll) { + case 0: + addr = CKC_BASE + CLKDIVC0_OFFS; + reg = __raw_readl(addr); + if (reg & CLKDIVC0_P0E) + div = (reg >> 24) & 0x3f; + break; + case 1: + addr = CKC_BASE + CLKDIVC0_OFFS; + reg = __raw_readl(addr); + if (reg & CLKDIVC0_P1E) + div = (reg >> 16) & 0x3f; + break; + case 2: + addr = CKC_BASE + CLKDIVC1_OFFS; + reg = __raw_readl(addr); + if (reg & CLKDIVC1_P2E) + div = __raw_readl(addr) & 0x3f; + break; + } + return get_rate_pll(pll) / (div + 1); +} + +static unsigned long get_rate_xi_div(void) +{ + unsigned long div = 0; + u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS); + + if (reg & CLKDIVC0_XE) + div = (reg >> 8) & 0x3f; + + return xi_rate / (div + 1); +} + +static unsigned long get_rate_xti_div(void) +{ + unsigned long div = 0; + u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS); + + if (reg & CLKDIVC0_XTE) + div = reg & 0x3f; + + return xti_rate / (div + 1); +} + +static unsigned long root_clk_get_rate(enum root_clks src) +{ + switch (src) { + case CLK_SRC_PLL0: return get_rate_pll(0); + case CLK_SRC_PLL1: return get_rate_pll(1); + case CLK_SRC_PLL2: return get_rate_pll(2); + case CLK_SRC_PLL0DIV: return get_rate_pll_div(0); + case CLK_SRC_PLL1DIV: return get_rate_pll_div(1); + case CLK_SRC_PLL2DIV: return get_rate_pll_div(2); + case CLK_SRC_XI: return xi_rate; + case CLK_SRC_XTI: return xti_rate; + case CLK_SRC_XIDIV: return get_rate_xi_div(); + case CLK_SRC_XTIDIV: return get_rate_xti_div(); + default: return 0; + } +} + +static unsigned long aclk_get_rate(struct clk *clk) +{ + u32 reg; + unsigned long div; + unsigned int src; + + reg = __raw_readl(clk->aclkreg); + div = reg & 0x0fff; + src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK; + return root_clk_get_rate(src) / (div + 1); +} + +static unsigned long aclk_best_div(struct clk *clk, unsigned long rate) +{ + unsigned long div, src, freq, r1, r2; + + src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; + src &= CLK_SRC_MASK; + freq = root_clk_get_rate(src); + div = freq / rate + 1; + r1 = freq / div; + r2 = freq / (div + 1); + if (r2 >= rate) + return div + 1; + if ((rate - r2) < (r1 - rate)) + return div + 1; + + return div; +} + +static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int src; + + src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; + src &= CLK_SRC_MASK; + + return root_clk_get_rate(src) / aclk_best_div(clk, rate); +} + +static int aclk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + + reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK; + reg |= aclk_best_div(clk, rate); + return 0; +} + +static unsigned long get_rate_sys(struct clk *clk) +{ + unsigned int src; + + src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK; + return root_clk_get_rate(src); +} + +static unsigned long get_rate_bus(struct clk *clk) +{ + unsigned int div; + + div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff; + return get_rate_sys(clk) / (div + 1); +} + +static unsigned long get_rate_cpu(struct clk *clk) +{ + unsigned int reg, div, fsys, fbus; + + fbus = get_rate_bus(clk); + reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS); + if (reg & (1 << 29)) + return fbus; + fsys = get_rate_sys(clk); + div = (reg >> 16) & 0x0f; + return fbus + ((fsys - fbus) * (div + 1)) / 16; +} + +static unsigned long get_rate_root(struct clk *clk) +{ + return root_clk_get_rate(clk->root_id); +} + +static int aclk_set_parent(struct clk *clock, struct clk *parent) +{ + u32 reg; + + if (clock->parent == parent) + return 0; + + clock->parent = parent; + + if (!parent) + return 0; + + if (parent->root_id == CLK_SRC_NOROOT) + return 0; + reg = __raw_readl(clock->aclkreg); + reg &= ~ACLK_SEL_MASK; + reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK; + __raw_writel(reg, clock->aclkreg); + + return 0; +} + +#define DEFINE_ROOT_CLOCK(name, ri, p) \ + static struct clk name = { \ + .root_id = ri, \ + .get_rate = get_rate_root, \ + .enable = enable_clk, \ + .disable = disable_clk, \ + .parent = p, \ + }; + +#define DEFINE_SPECIAL_CLOCK(name, gr, p) \ + static struct clk name = { \ + .root_id = CLK_SRC_NOROOT, \ + .get_rate = gr, \ + .parent = p, \ + }; + +#define DEFINE_ACLOCK(name, bc, bs, ar) \ + static struct clk name = { \ + .root_id = CLK_SRC_NOROOT, \ + .bclkctr = bc, \ + .bclk_shift = bs, \ + .aclkreg = ar, \ + .get_rate = aclk_get_rate, \ + .set_rate = aclk_set_rate, \ + .round_rate = aclk_round_rate, \ + .enable = enable_clk, \ + .disable = disable_clk, \ + .set_parent = aclk_set_parent, \ + }; + +#define DEFINE_BCLOCK(name, bc, bs, gr, p) \ + static struct clk name = { \ + .root_id = CLK_SRC_NOROOT, \ + .bclkctr = bc, \ + .bclk_shift = bs, \ + .get_rate = gr, \ + .enable = enable_clk, \ + .disable = disable_clk, \ + .parent = p, \ + }; + +DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL) +DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL) +DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi) +DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti) +DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi) +DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi) +DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi) +DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0) +DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1) +DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2) + +/* The following 3 clocks are special and are initialized explicitly later */ +DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL) +DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys) +DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys) + +DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT) +DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX) +DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ) +DEFINE_ACLOCK(ref, NULL, 0, ACLKREF) +DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0) +DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1) +DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2) +DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3) +DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4) +DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C) +DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC) +DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH) +DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD) +DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0) +DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1) +DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0) +DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1) +DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF) +DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC) +DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0) +DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1) +DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0) +DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1) +DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2) +DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3) +DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH) + +DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL) +DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL) +DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL) +DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL) +DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL) +DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL) +DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL) +DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL) +DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL) +DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL) +DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL) +DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL) +DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL) +DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL) +DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL) +DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL) +DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL) +DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL) +DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL) +DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL) +DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL) +DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL) + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "bus", bus) + _REGISTER_CLOCK(NULL, "cpu", cpu) + _REGISTER_CLOCK(NULL, "tct", tct) + _REGISTER_CLOCK(NULL, "tcx", tcx) + _REGISTER_CLOCK(NULL, "tcz", tcz) + _REGISTER_CLOCK(NULL, "ref", ref) + _REGISTER_CLOCK(NULL, "dai0", dai0) + _REGISTER_CLOCK(NULL, "pic", pic) + _REGISTER_CLOCK(NULL, "tc", tc) + _REGISTER_CLOCK(NULL, "gpio", gpio) + _REGISTER_CLOCK(NULL, "usbd", usbd) + _REGISTER_CLOCK("tcc-uart.0", NULL, uart0) + _REGISTER_CLOCK("tcc-uart.2", NULL, uart2) + _REGISTER_CLOCK("tcc-i2c", NULL, i2c) + _REGISTER_CLOCK("tcc-uart.3", NULL, uart3) + _REGISTER_CLOCK(NULL, "ecc", ecc) + _REGISTER_CLOCK(NULL, "adc", adc) + _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0) + _REGISTER_CLOCK(NULL, "gdma0", gdma0) + _REGISTER_CLOCK(NULL, "lcd", lcd) + _REGISTER_CLOCK(NULL, "rtc", rtc) + _REGISTER_CLOCK(NULL, "nfc", nfc) + _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0) + _REGISTER_CLOCK(NULL, "g2d", g2d) + _REGISTER_CLOCK(NULL, "gdma1", gdma1) + _REGISTER_CLOCK("tcc-uart.1", NULL, uart1) + _REGISTER_CLOCK("tcc-spi.0", NULL, spi0) + _REGISTER_CLOCK(NULL, "mscl", mscl) + _REGISTER_CLOCK("tcc-spi.1", NULL, spi1) + _REGISTER_CLOCK(NULL, "bdma", bdma) + _REGISTER_CLOCK(NULL, "adma0", adma0) + _REGISTER_CLOCK(NULL, "spdif", spdif) + _REGISTER_CLOCK(NULL, "scfg", scfg) + _REGISTER_CLOCK(NULL, "cid", cid) + _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1) + _REGISTER_CLOCK("tcc-uart.4", NULL, uart4) + _REGISTER_CLOCK(NULL, "dai1", dai1) + _REGISTER_CLOCK(NULL, "adma1", adma1) + _REGISTER_CLOCK(NULL, "c3dec", c3dec) + _REGISTER_CLOCK("tcc-can.0", NULL, can0) + _REGISTER_CLOCK("tcc-can.1", NULL, can1) + _REGISTER_CLOCK(NULL, "gps", gps) + _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0) + _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1) + _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2) + _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3) + _REGISTER_CLOCK(NULL, "gdma2", gdma2) + _REGISTER_CLOCK(NULL, "gdma3", gdma3) + _REGISTER_CLOCK(NULL, "ddrc", ddrc) + _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1) +}; + +static struct clk *root_clk_by_index(enum root_clks src) +{ + switch (src) { + case CLK_SRC_PLL0: return &pll0; + case CLK_SRC_PLL1: return &pll1; + case CLK_SRC_PLL2: return &pll2; + case CLK_SRC_PLL0DIV: return &pll0div; + case CLK_SRC_PLL1DIV: return &pll1div; + case CLK_SRC_PLL2DIV: return &pll2div; + case CLK_SRC_XI: return ξ + case CLK_SRC_XTI: return &xti; + case CLK_SRC_XIDIV: return &xidiv; + case CLK_SRC_XTIDIV: return &xtidiv; + default: return NULL; + } +} + +static void find_aclk_parent(struct clk *clk) +{ + unsigned int src; + struct clk *clock; + + if (!clk->aclkreg) + return; + + src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT; + src &= CLK_SRC_MASK; + + clock = root_clk_by_index(src); + if (!clock) + return; + + clk->parent = clock; + clk->set_parent = aclk_set_parent; +} + +void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq) +{ + int i; + + xi_rate = xi_freq; + xti_rate = xti_freq; + + /* fixup parents and add the clock */ + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + find_aclk_parent(lookups[i].clk); + clkdev_add(&lookups[i]); + } +} diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h new file mode 100644 index 000000000000..e2c902c1639c --- /dev/null +++ b/arch/arm/mach-tcc8k/common.h @@ -0,0 +1,6 @@ +#ifndef MACH_TCC8K_COMMON_H +#define MACH_TCC8K_COMMON_H + +extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); + +#endif diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile index 3f2e4fe70d5a..eceabc869b8f 100644 --- a/arch/arm/plat-tcc/Makefile +++ b/arch/arm/plat-tcc/Makefile @@ -1,3 +1,3 @@ # "Telechips Platform Common Modules" -obj-y := system.o +obj-y := clock.o system.o diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c new file mode 100644 index 000000000000..f3ced10d5271 --- /dev/null +++ b/arch/arm/plat-tcc/clock.c @@ -0,0 +1,179 @@ +/* + * Clock framework for Telechips SoCs + * Based on arch/arm/plat-mxc/clock.c + * + * Copyright (C) 2004 - 2005 Nokia corporation + * Written by Tuukka Tikkanen + * Modified for omap shared clock framework by Tony Lindgren + * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * Copyright 2010 Hans J. Koch, hjk@linutronix.de + * + * Licensed under the terms of the GPL v2. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +static DEFINE_MUTEX(clocks_mutex); + +/*------------------------------------------------------------------------- + * Standard clock functions defined in include/linux/clk.h + *-------------------------------------------------------------------------*/ + +static void __clk_disable(struct clk *clk) +{ + BUG_ON(clk->refcount == 0); + + if (!(--clk->refcount) && clk->disable) { + /* Unconditionally disable the clock in hardware */ + clk->disable(clk); + /* recursively disable parents */ + if (clk->parent) + __clk_disable(clk->parent); + } +} + +static int __clk_enable(struct clk *clk) +{ + int ret = 0; + + if (clk->refcount++ == 0 && clk->enable) { + if (clk->parent) + ret = __clk_enable(clk->parent); + if (ret) + return ret; + else + return clk->enable(clk); + } + + return 0; +} + +/* This function increments the reference count on the clock and enables the + * clock if not already enabled. The parent clock tree is recursively enabled + */ +int clk_enable(struct clk *clk) +{ + int ret = 0; + + if (!clk) + return -EINVAL; + + mutex_lock(&clocks_mutex); + ret = __clk_enable(clk); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_enable); + +/* This function decrements the reference count on the clock and disables + * the clock when reference count is 0. The parent clock tree is + * recursively disabled + */ +void clk_disable(struct clk *clk) +{ + if (!clk) + return; + + mutex_lock(&clocks_mutex); + __clk_disable(clk); + mutex_unlock(&clocks_mutex); +} +EXPORT_SYMBOL_GPL(clk_disable); + +/* Retrieve the *current* clock rate. If the clock itself + * does not provide a special calculation routine, ask + * its parent and so on, until one is able to return + * a valid clock rate + */ +unsigned long clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0UL; + + if (clk->get_rate) + return clk->get_rate(clk); + + return clk_get_rate(clk->parent); +} +EXPORT_SYMBOL_GPL(clk_get_rate); + +/* Round the requested clock rate to the nearest supported + * rate that is less than or equal to the requested rate. + * This is dependent on the clock's current parent. + */ +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (!clk) + return 0; + if (!clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} +EXPORT_SYMBOL_GPL(clk_round_rate); + +/* Set the clock to the requested clock rate. The rate must + * match a supported rate exactly based on what clk_round_rate returns + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + + if (!clk) + return ret; + if (!clk->set_rate || !rate) + return ret; + + mutex_lock(&clocks_mutex); + ret = clk->set_rate(clk, rate); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_set_rate); + +/* Set the clock's parent to another clock source */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *old; + int ret = -EINVAL; + + if (!clk) + return ret; + if (!clk->set_parent || !parent) + return ret; + + mutex_lock(&clocks_mutex); + old = clk->parent; + if (clk->refcount) + __clk_enable(parent); + ret = clk->set_parent(clk, parent); + if (ret) + old = parent; + if (clk->refcount) + __clk_disable(old); + mutex_unlock(&clocks_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(clk_set_parent); + +/* Retrieve the clock's parent clock source */ +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return NULL; + + return clk->parent; +} +EXPORT_SYMBOL_GPL(clk_get_parent); diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h new file mode 100644 index 000000000000..a12f58ad71a8 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/clock.h @@ -0,0 +1,48 @@ +/* + * Low level clock header file for Telechips TCC architecture + * (C) 2010 Hans J. Koch + * + * Licensed under the GPL v2. + */ + +#ifndef __ASM_ARCH_TCC_CLOCK_H__ +#define __ASM_ARCH_TCC_CLOCK_H__ + +#ifndef __ASSEMBLY__ + +struct clk { + struct clk *parent; + /* id number of a root clock, 0 for normal clocks */ + int root_id; + /* Reference count of clock enable/disable */ + int refcount; + /* Address of associated BCLKCTRx register. Must be set. */ + void __iomem *bclkctr; + /* Bit position for BCLKCTRx. Must be set. */ + int bclk_shift; + /* Address of ACLKxxx register, if any. */ + void __iomem *aclkreg; + /* get the current clock rate (always a fresh value) */ + unsigned long (*get_rate) (struct clk *); + /* Function ptr to set the clock to a new rate. The rate must match a + supported rate returned from round_rate. Leave blank if clock is not + programmable */ + int (*set_rate) (struct clk *, unsigned long); + /* Function ptr to round the requested clock rate to the nearest + supported rate that is less than or equal to the requested rate. */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* Function ptr to enable the clock. Leave blank if clock can not + be gated. */ + int (*enable) (struct clk *); + /* Function ptr to disable the clock. Leave blank if clock can not + be gated. */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + +int clk_register(struct clk *clk); +void clk_unregister(struct clk *clk); + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_CLOCK_H__ */ diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h index f3243ebea463..1d9428295332 100644 --- a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h +++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h @@ -30,13 +30,13 @@ #define EXT_MEM_CTRL_BASE 0xf0000000 #define EXT_MEM_CTRL_SIZE SZ_4K -#define CS1_BASE_VIRT 0xf7000000 -#define AHB_PERI_BASE_VIRT 0xf4000000 -#define APB0_PERI_BASE_VIRT 0xf1000000 -#define APB1_PERI_BASE_VIRT 0xf2000000 -#define EXT_MEM_CTRL_BASE_VIRT 0xf3000000 -#define INT_SRAM_BASE_VIRT 0xf5000000 -#define DATA_TCM_BASE_VIRT 0xf6000000 +#define CS1_BASE_VIRT (void __iomem *)0xf7000000 +#define AHB_PERI_BASE_VIRT (void __iomem *)0xf4000000 +#define APB0_PERI_BASE_VIRT (void __iomem *)0xf1000000 +#define APB1_PERI_BASE_VIRT (void __iomem *)0xf2000000 +#define EXT_MEM_CTRL_BASE_VIRT (void __iomem *)0xf3000000 +#define INT_SRAM_BASE_VIRT (void __iomem *)0xf5000000 +#define DATA_TCM_BASE_VIRT (void __iomem *)0xf6000000 #define __REG(x) (*((volatile u32 *)(x))) @@ -649,8 +649,7 @@ #define PMGPIO_APB_OFFS 0x800 /* Clock controller registers */ -#define CKC_BASE (APB1_PERI_BASE_VIRT + 0x6000) -#define CKC_BASE_PHYS (APB1_PERI_BASE + 0x6000) +#define CKC_BASE ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000)) #define CLKCTRL_OFFS 0x00 #define PLL0CFG_OFFS 0x04 @@ -724,8 +723,20 @@ /* SWRESET1 bits */ #define SWRESET1_USBH1 (1 << 20) -/* System clock sources */ +/* System clock sources. + * Note: These are the clock sources that serve as parents for + * all other clocks. They have no parents themselves. + * + * These values are used for struct clk->root_id. All clocks + * that are not system clock sources have this value set to + * CLK_SRC_NOROOT. + * The values for system clocks start with CLK_SRC_PLL0 == 0 + * because this gives us exactly the values needed for the lower + * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is + * defined as -1 to not disturb the order. + */ enum root_clks { + CLK_SRC_NOROOT = -1, CLK_SRC_PLL0 = 0, CLK_SRC_PLL1, CLK_SRC_PLL0DIV, -- cgit v1.2.3 From e9268ef2252c2dfc7e2d0c435826768bb0e549ea Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:16:29 +0200 Subject: ARM: Introduce plat-tcc irq framework Introduce lowlevel interrupt routines. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/Makefile | 2 +- arch/arm/mach-tcc8k/common.h | 1 + arch/arm/mach-tcc8k/irq.c | 111 ++++++++++++++++++++++++++++++++++ arch/arm/plat-tcc/include/mach/irqs.h | 83 +++++++++++++++++++++++++ 4 files changed, 196 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-tcc8k/irq.c create mode 100644 arch/arm/plat-tcc/include/mach/irqs.h (limited to 'arch/arm') diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile index 805d850919eb..53bc2f58549b 100644 --- a/arch/arm/mach-tcc8k/Makefile +++ b/arch/arm/mach-tcc8k/Makefile @@ -3,4 +3,4 @@ # # Common support -obj-y += clock.o +obj-y += clock.o irq.o diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h index e2c902c1639c..e539548e58d2 100644 --- a/arch/arm/mach-tcc8k/common.h +++ b/arch/arm/mach-tcc8k/common.h @@ -2,5 +2,6 @@ #define MACH_TCC8K_COMMON_H extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); +extern void tcc8k_init_irq(void); #endif diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c new file mode 100644 index 000000000000..34575c4963f0 --- /dev/null +++ b/arch/arm/mach-tcc8k/irq.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) Telechips, Inc. + * Copyright (C) 2009-2010 Hans J. Koch + * + * Licensed under the terms of the GNU GPL version 2. + */ + +#include +#include +#include + +#include +#include + +#include +#include + +#include "common.h" + +/* Disable IRQ */ +static void tcc8000_mask_ack_irq0(unsigned int irq) +{ + PIC0_IEN &= ~(1 << irq); + PIC0_CREQ |= (1 << irq); +} + +static void tcc8000_mask_ack_irq1(unsigned int irq) +{ + PIC1_IEN &= ~(1 << (irq - 32)); + PIC1_CREQ |= (1 << (irq - 32)); +} + +static void tcc8000_mask_irq0(unsigned int irq) +{ + PIC0_IEN &= ~(1 << irq); +} + +static void tcc8000_mask_irq1(unsigned int irq) +{ + PIC1_IEN &= ~(1 << (irq - 32)); +} + +static void tcc8000_ack_irq0(unsigned int irq) +{ + PIC0_CREQ |= (1 << irq); +} + +static void tcc8000_ack_irq1(unsigned int irq) +{ + PIC1_CREQ |= (1 << (irq - 32)); +} + +/* Enable IRQ */ +static void tcc8000_unmask_irq0(unsigned int irq) +{ + PIC0_IEN |= (1 << irq); + PIC0_INTOEN |= (1 << irq); +} + +static void tcc8000_unmask_irq1(unsigned int irq) +{ + PIC1_IEN |= (1 << (irq - 32)); + PIC1_INTOEN |= (1 << (irq - 32)); +} + +static struct irq_chip tcc8000_irq_chip0 = { + .name = "tcc_irq0", + .mask = tcc8000_mask_irq0, + .ack = tcc8000_ack_irq0, + .mask_ack = tcc8000_mask_ack_irq0, + .unmask = tcc8000_unmask_irq0, +}; + +static struct irq_chip tcc8000_irq_chip1 = { + .name = "tcc_irq1", + .mask = tcc8000_mask_irq1, + .ack = tcc8000_ack_irq1, + .mask_ack = tcc8000_mask_ack_irq1, + .unmask = tcc8000_unmask_irq1, +}; + +void __init tcc8k_init_irq(void) +{ + int irqno; + + /* Mask and clear all interrupts */ + PIC0_IEN = 0x00000000; + PIC0_CREQ = 0xffffffff; + PIC1_IEN = 0x00000000; + PIC1_CREQ = 0xffffffff; + + PIC0_MEN0 = 0x00000003; + PIC1_MEN1 = 0x00000003; + PIC1_MEN = 0x00000003; + + /* let all IRQs be level triggered */ + PIC0_TMODE = 0xffffffff; + PIC1_TMODE = 0xffffffff; + /* all IRQs are IRQs (not FIQs) */ + PIC0_IRQSEL = 0xffffffff; + PIC1_IRQSEL = 0xffffffff; + + for (irqno = 0; irqno < NR_IRQS; irqno++) { + if (irqno < 32) + set_irq_chip(irqno, &tcc8000_irq_chip0); + else + set_irq_chip(irqno, &tcc8000_irq_chip1); + set_irq_handler(irqno, handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } +} diff --git a/arch/arm/plat-tcc/include/mach/irqs.h b/arch/arm/plat-tcc/include/mach/irqs.h new file mode 100644 index 000000000000..da863894d498 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/irqs.h @@ -0,0 +1,83 @@ +/* + * IRQ definitions for TCC8xxx + * + * Copyright (C) 2008-2009 Telechips + * Copyright (C) 2009 Hans J. Koch + * + * Licensed under the terms of the GPL v2. + * + */ + +#ifndef __ASM_ARCH_TCC_IRQS_H +#define __ASM_ARCH_TCC_IRQS_H + +#define NR_IRQS 64 + +/* PIC0 interrupts */ +#define INT_ADMA1 0 +#define INT_BDMA 1 +#define INT_ADMA0 2 +#define INT_GDMA1 3 +#define INT_I2S0RX 4 +#define INT_I2S0TX 5 +#define INT_TC 6 +#define INT_UART0 7 +#define INT_USBD 8 +#define INT_SPI0TX 9 +#define INT_UDMA 10 +#define INT_LIRQ 11 +#define INT_GDMA2 12 +#define INT_GDMA0 13 +#define INT_TC32 14 +#define INT_LCD 15 +#define INT_ADC 16 +#define INT_I2C 17 +#define INT_RTCP 18 +#define INT_RTCA 19 +#define INT_NFC 20 +#define INT_SD0 21 +#define INT_GSB0 22 +#define INT_PK 23 +#define INT_USBH0 24 +#define INT_USBH1 25 +#define INT_G2D 26 +#define INT_ECC 27 +#define INT_SPI0RX 28 +#define INT_UART1 29 +#define INT_MSCL 30 +#define INT_GSB1 31 +/* PIC1 interrupts */ +#define INT_E0 32 +#define INT_E1 33 +#define INT_E2 34 +#define INT_E3 35 +#define INT_E4 36 +#define INT_E5 37 +#define INT_E6 38 +#define INT_E7 39 +#define INT_UART2 40 +#define INT_UART3 41 +#define INT_SPI1TX 42 +#define INT_SPI1RX 43 +#define INT_GSB2 44 +#define INT_SPDIF 45 +#define INT_CDIF 46 +#define INT_VBON 47 +#define INT_VBOFF 48 +#define INT_SD1 49 +#define INT_UART4 50 +#define INT_GDMA3 51 +#define INT_I2S1RX 52 +#define INT_I2S1TX 53 +#define INT_CAN0 54 +#define INT_CAN1 55 +#define INT_GSB3 56 +#define INT_KRST 57 +#define INT_UNUSED 58 +#define INT_SD0D3 59 +#define INT_SD1D3 60 +#define INT_GPS0 61 +#define INT_GPS1 62 +#define INT_GPS2 63 + +#endif /* ASM_ARCH_TCC_IRQS_H */ -- cgit v1.2.3 From 3de7b517dfacf1deb0690dbac28f917643e49975 Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:17:42 +0200 Subject: ARM: Add TCC8xxx system timer Add the system timer using clockevents with the internal TC32 timer. This also adds a clocksource using the same timer. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/Makefile | 2 +- arch/arm/mach-tcc8k/clock.c | 1 + arch/arm/mach-tcc8k/common.h | 3 + arch/arm/mach-tcc8k/time.c | 149 +++++++++++++++++++++++++++++++++ arch/arm/plat-tcc/include/mach/timex.h | 5 ++ 5 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-tcc8k/time.c create mode 100644 arch/arm/plat-tcc/include/mach/timex.h (limited to 'arch/arm') diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile index 53bc2f58549b..b4a12f294c57 100644 --- a/arch/arm/mach-tcc8k/Makefile +++ b/arch/arm/mach-tcc8k/Makefile @@ -3,4 +3,4 @@ # # Common support -obj-y += clock.o irq.o +obj-y += clock.o irq.o time.o diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c index a8982af15326..ba32a15127ab 100644 --- a/arch/arm/mach-tcc8k/clock.c +++ b/arch/arm/mach-tcc8k/clock.c @@ -563,4 +563,5 @@ void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq) find_aclk_parent(lookups[i].clk); clkdev_add(&lookups[i]); } + tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32); } diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h index e539548e58d2..858210ecd67a 100644 --- a/arch/arm/mach-tcc8k/common.h +++ b/arch/arm/mach-tcc8k/common.h @@ -1,7 +1,10 @@ #ifndef MACH_TCC8K_COMMON_H #define MACH_TCC8K_COMMON_H +struct clk; + extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); +extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq); extern void tcc8k_init_irq(void); #endif diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c new file mode 100644 index 000000000000..78d06008841d --- /dev/null +++ b/arch/arm/mach-tcc8k/time.c @@ -0,0 +1,149 @@ +/* + * TCC8000 system timer setup + * + * (C) 2009 Hans J. Koch + * + * Licensed under the terms of the GPL version 2. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "common.h" + +static void __iomem *timer_base; + +static cycle_t tcc_get_cycles(struct clocksource *cs) +{ + return __raw_readl(timer_base + TC32MCNT_OFFS); +} + +static struct clocksource clocksource_tcc = { + .name = "tcc_tc32", + .rating = 200, + .read = tcc_get_cycles, + .mask = CLOCKSOURCE_MASK(32), + .shift = 28, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int tcc_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS); + + __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS); + return 0; +} + +static void tcc_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long tc32irq; + + switch (mode) { + case CLOCK_EVT_MODE_ONESHOT: + tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS); + tc32irq |= TC32IRQ_IRQEN0; + __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS); + tc32irq &= ~TC32IRQ_IRQEN0; + __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS); + break; + case CLOCK_EVT_MODE_PERIODIC: + case CLOCK_EVT_MODE_RESUME: + break; + } +} + +static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + + /* Acknowledge TC32 interrupt by reading TC32IRQ */ + __raw_readl(timer_base + TC32IRQ_OFFS); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct clock_event_device clockevent_tcc = { + .name = "tcc_timer1", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = tcc_set_mode, + .set_next_event = tcc_set_next_event, + .rating = 200, +}; + +static struct irqaction tcc8k_timer_irq = { + .name = "TC32_timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = tcc8k_timer_interrupt, + .dev_id = &clockevent_tcc, +}; + +static int __init tcc_clockevent_init(struct clk *clock) +{ + unsigned int c = clk_get_rate(clock); + + clocksource_tcc.mult = clocksource_hz2mult(c, + clocksource_tcc.shift); + clocksource_register(&clocksource_tcc); + + clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC, + clockevent_tcc.shift); + clockevent_tcc.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_tcc); + clockevent_tcc.min_delta_ns = + clockevent_delta2ns(0xff, &clockevent_tcc); + + clockevent_tcc.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_tcc); + + return 0; +} + +void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq) +{ + u32 reg; + + timer_base = base; + tcc8k_timer_irq.irq = irq; + + /* Enable clocks */ + clk_enable(clock); + + /* Initialize 32-bit timer */ + reg = __raw_readl(timer_base + TC32EN_OFFS); + reg &= ~TC32EN_ENABLE; /* Disable timer */ + __raw_writel(reg, timer_base + TC32EN_OFFS); + /* Free running timer, counting from 0 to 0xffffffff */ + __raw_writel(0, timer_base + TC32EN_OFFS); + __raw_writel(0, timer_base + TC32LDV_OFFS); + reg = __raw_readl(timer_base + TC32IRQ_OFFS); + reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */ + __raw_writel(reg, timer_base + TC32IRQ_OFFS); + + __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS); + + tcc_clockevent_init(clock); + setup_irq(irq, &tcc8k_timer_irq); +} diff --git a/arch/arm/plat-tcc/include/mach/timex.h b/arch/arm/plat-tcc/include/mach/timex.h new file mode 100644 index 000000000000..057acbe651d9 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/timex.h @@ -0,0 +1,5 @@ +/* + * A definition needed by arch core code. + * + */ +#define CLOCK_TICK_RATE (HZ * 100000UL) -- cgit v1.2.3 From 8a41fa3b3c89e5bd3c69219ddeee268bdcce886c Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:18:57 +0200 Subject: ARM: Basic IO mappings for mach-tcc8k Map the IO ranges of TCC8xxx peripherals. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/Makefile | 2 +- arch/arm/mach-tcc8k/common.h | 1 + arch/arm/mach-tcc8k/io.c | 62 +++++++++++++++++++++++++++++++++++++ arch/arm/plat-tcc/include/mach/io.h | 23 ++++++++++++++ 4 files changed, 87 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-tcc8k/io.c create mode 100644 arch/arm/plat-tcc/include/mach/io.h (limited to 'arch/arm') diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile index b4a12f294c57..446c4c9f0708 100644 --- a/arch/arm/mach-tcc8k/Makefile +++ b/arch/arm/mach-tcc8k/Makefile @@ -3,4 +3,4 @@ # # Common support -obj-y += clock.o irq.o time.o +obj-y += clock.o irq.o time.o io.o diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h index 858210ecd67a..365f18adf30c 100644 --- a/arch/arm/mach-tcc8k/common.h +++ b/arch/arm/mach-tcc8k/common.h @@ -6,5 +6,6 @@ struct clk; extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq); extern void tcc8k_init_irq(void); +extern void tcc8k_map_common_io(void); #endif diff --git a/arch/arm/mach-tcc8k/io.c b/arch/arm/mach-tcc8k/io.c new file mode 100644 index 000000000000..9b39d7fa658f --- /dev/null +++ b/arch/arm/mach-tcc8k/io.c @@ -0,0 +1,62 @@ +/* + * linux/arch/arm/mach-tcc8k/io.c + * + * (C) 2009 Hans J. Koch + * + * derived from TCC83xx io.c + * Copyright (C) Telechips, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include + +/* + * The machine specific code may provide the extra mapping besides the + * default mapping provided here. + */ +static struct map_desc tcc8k_io_desc[] __initdata = { + { + .virtual = (unsigned long)CS1_BASE_VIRT, + .pfn = __phys_to_pfn(CS1_BASE), + .length = CS1_SIZE, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)AHB_PERI_BASE_VIRT, + .pfn = __phys_to_pfn(AHB_PERI_BASE), + .length = AHB_PERI_SIZE, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)APB0_PERI_BASE_VIRT, + .pfn = __phys_to_pfn(APB0_PERI_BASE), + .length = APB0_PERI_SIZE, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)APB1_PERI_BASE_VIRT, + .pfn = __phys_to_pfn(APB1_PERI_BASE), + .length = APB1_PERI_SIZE, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)EXT_MEM_CTRL_BASE_VIRT, + .pfn = __phys_to_pfn(EXT_MEM_CTRL_BASE), + .length = EXT_MEM_CTRL_SIZE, + .type = MT_DEVICE, + }, +}; + +/* + * Maps common IO regions for tcc8k. + * + */ +void __init tcc8k_map_common_io(void) +{ + iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc)); +} diff --git a/arch/arm/plat-tcc/include/mach/io.h b/arch/arm/plat-tcc/include/mach/io.h new file mode 100644 index 000000000000..3e911d3ea0f1 --- /dev/null +++ b/arch/arm/plat-tcc/include/mach/io.h @@ -0,0 +1,23 @@ +/* + * IO definitions for TCC8000 processors and boards + * + * Copyright (C) 1997-1999 Russell King + * Copyright (C) 2008-2009 Telechips + * Copyright (C) 2010 Hans J. Koch + * + * Licensed under the terms of the GNU Public License version 2. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif -- cgit v1.2.3 From 026cec6164901372c3a16b430cd405f0bb6a7c1f Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:20:11 +0200 Subject: ARM: Add common platform devices for TCC8xxx SoCs This patch introduces a first set of platform devices for integrated peripherals of TCC8xxx processors. Drivers for these devices are available and will be posted in a second step. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/Makefile | 2 +- arch/arm/mach-tcc8k/common.h | 4 + arch/arm/mach-tcc8k/devices.c | 239 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 244 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-tcc8k/devices.c (limited to 'arch/arm') diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile index 446c4c9f0708..e92c0d255ae7 100644 --- a/arch/arm/mach-tcc8k/Makefile +++ b/arch/arm/mach-tcc8k/Makefile @@ -3,4 +3,4 @@ # # Common support -obj-y += clock.o irq.o time.o io.o +obj-y += clock.o irq.o time.o io.o devices.o diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h index 365f18adf30c..705690add395 100644 --- a/arch/arm/mach-tcc8k/common.h +++ b/arch/arm/mach-tcc8k/common.h @@ -1,6 +1,10 @@ #ifndef MACH_TCC8K_COMMON_H #define MACH_TCC8K_COMMON_H +#include + +extern struct platform_device tcc_nand_device; + struct clk; extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); diff --git a/arch/arm/mach-tcc8k/devices.c b/arch/arm/mach-tcc8k/devices.c new file mode 100644 index 000000000000..6722ad7c2836 --- /dev/null +++ b/arch/arm/mach-tcc8k/devices.c @@ -0,0 +1,239 @@ +/* + * linux/arch/arm/mach-tcc8k/devices.c + * + * Copyright (C) Telechips, Inc. + * Copyright (C) 2009 Hans J. Koch + * + * Licensed under the terms of GPL v2. + * + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "common.h" + +static u64 tcc8k_dmamask = DMA_BIT_MASK(32); + +#ifdef CONFIG_MTD_NAND_TCC +/* NAND controller */ +static struct resource tcc_nand_resources[] = { + { + .start = (resource_size_t)NFC_BASE, + .end = (resource_size_t)NFC_BASE + 0x7f, + .flags = IORESOURCE_MEM, + }, { + .start = INT_NFC, + .end = INT_NFC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device tcc_nand_device = { + .name = "tcc_nand", + .id = 0, + .num_resources = ARRAY_SIZE(tcc_nand_resources), + .resource = tcc_nand_resources, +}; +#endif + +#ifdef CONFIG_MMC_TCC8K +/* MMC controller */ +static struct resource tcc8k_mmc0_resource[] = { + { + .start = INT_SD0, + .end = INT_SD0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource tcc8k_mmc1_resource[] = { + { + .start = INT_SD1, + .end = INT_SD1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device tcc8k_mmc0_device = { + .name = "tcc-mmc", + .id = 0, + .num_resources = ARRAY_SIZE(tcc8k_mmc0_resource), + .resource = tcc8k_mmc0_resource, + .dev = { + .dma_mask = &tcc8k_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +struct platform_device tcc8k_mmc1_device = { + .name = "tcc-mmc", + .id = 1, + .num_resources = ARRAY_SIZE(tcc8k_mmc1_resource), + .resource = tcc8k_mmc1_resource, + .dev = { + .dma_mask = &tcc8k_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +static inline void tcc8k_init_mmc(void) +{ + u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS); + + reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS; + __raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS); + + platform_device_register(&tcc8k_mmc0_device); + platform_device_register(&tcc8k_mmc1_device); +} +#else +static inline void tcc8k_init_mmc(void) { } +#endif + +#ifdef CONFIG_USB_OHCI_HCD +static int tcc8k_ohci_init(struct device *dev) +{ + u32 reg; + + /* Use GPIO PK19 as VBUS control output */ + reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS); + reg &= ~(1 << 19); + __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS); + reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS); + reg &= ~(1 << 19); + __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS); + + reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS); + reg |= (1 << 19); + __raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS); + /* Turn on VBUS */ + reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS); + reg |= (1 << 19); + __raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS); + + return 0; +} + +static struct resource tcc8k_ohci0_resources[] = { + [0] = { + .start = (resource_size_t)USBH0_BASE, + .end = (resource_size_t)USBH0_BASE + 0x5c, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USBH0, + .end = INT_USBH0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource tcc8k_ohci1_resources[] = { + [0] = { + .start = (resource_size_t)USBH1_BASE, + .end = (resource_size_t)USBH1_BASE + 0x5c, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_USBH1, + .end = INT_USBH1, + .flags = IORESOURCE_IRQ, + } +}; + +static struct tccohci_platform_data tcc8k_ohci0_platform_data = { + .controller = 0, + .port_mode = PMM_PERPORT_MODE, + .init = tcc8k_ohci_init, +}; + +static struct tccohci_platform_data tcc8k_ohci1_platform_data = { + .controller = 1, + .port_mode = PMM_PERPORT_MODE, + .init = tcc8k_ohci_init, +}; + +static struct platform_device ohci0_device = { + .name = "tcc-ohci", + .id = 0, + .dev = { + .dma_mask = &tcc8k_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &tcc8k_ohci0_platform_data, + }, + .num_resources = ARRAY_SIZE(tcc8k_ohci0_resources), + .resource = tcc8k_ohci0_resources, +}; + +static struct platform_device ohci1_device = { + .name = "tcc-ohci", + .id = 1, + .dev = { + .dma_mask = &tcc8k_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &tcc8k_ohci1_platform_data, + }, + .num_resources = ARRAY_SIZE(tcc8k_ohci1_resources), + .resource = tcc8k_ohci1_resources, +}; + +static void __init tcc8k_init_usbhost(void) +{ + platform_device_register(&ohci0_device); + platform_device_register(&ohci1_device); +} +#else +static void __init tcc8k_init_usbhost(void) { } +#endif + +/* USB device controller*/ +#ifdef CONFIG_USB_GADGET_TCC8K +static struct resource udc_resources[] = { + [0] = { + .start = INT_USBD, + .end = INT_USBD, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = INT_UDMA, + .end = INT_UDMA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tcc8k_udc_device = { + .name = "tcc-udc", + .id = 0, + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), + .dev = { + .dma_mask = &tcc8k_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static void __init tcc8k_init_usb_gadget(void) +{ + platform_device_register(&tcc8k_udc_device); +} +#else +static void __init tcc8k_init_usb_gadget(void) { } +#endif /* CONFIG_USB_GADGET_TCC83X */ + +static int __init tcc8k_init_devices(void) +{ + tcc8k_init_mmc(); + tcc8k_init_usbhost(); + tcc8k_init_usb_gadget(); + return 0; +} + +arch_initcall(tcc8k_init_devices); -- cgit v1.2.3 From 2aea73ce22b786039906be89b0ae191d4c016c1e Mon Sep 17 00:00:00 2001 From: "Hans J. Koch" Date: Fri, 17 Sep 2010 18:21:36 +0200 Subject: ARM: Add board support for Telechips TCC8000-SDK board Add support for the Telechips TCC8000-SDK development board. Signed-off-by: "Hans J. Koch" Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/Kconfig | 6 ++++ arch/arm/mach-tcc8k/Makefile | 3 ++ arch/arm/mach-tcc8k/Makefile.boot | 3 ++ arch/arm/mach-tcc8k/board-tcc8000-sdk.c | 64 +++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+) create mode 100644 arch/arm/mach-tcc8k/Makefile.boot create mode 100644 arch/arm/mach-tcc8k/board-tcc8000-sdk.c (limited to 'arch/arm') diff --git a/arch/arm/mach-tcc8k/Kconfig b/arch/arm/mach-tcc8k/Kconfig index ec7f71b17c06..ad86415d1577 100644 --- a/arch/arm/mach-tcc8k/Kconfig +++ b/arch/arm/mach-tcc8k/Kconfig @@ -2,4 +2,10 @@ if ARCH_TCC8K comment "TCC8000 systems:" +config MACH_TCC8000_SDK + bool "Telechips TCC8000-SDK development kit" + default y + help + Support for the Telechips TCC8000-SDK board. + endif diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile index e92c0d255ae7..9bacf31e49ba 100644 --- a/arch/arm/mach-tcc8k/Makefile +++ b/arch/arm/mach-tcc8k/Makefile @@ -4,3 +4,6 @@ # Common support obj-y += clock.o irq.o time.o io.o devices.o + +# Board specific support +obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o diff --git a/arch/arm/mach-tcc8k/Makefile.boot b/arch/arm/mach-tcc8k/Makefile.boot new file mode 100644 index 000000000000..f135c9deae10 --- /dev/null +++ b/arch/arm/mach-tcc8k/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x20008000 +params_phys-y := 0x20000100 +initrd_phys-y := 0x20800000 diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c new file mode 100644 index 000000000000..4e42555b2009 --- /dev/null +++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2009 Hans J. Koch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +#include + +#include +#include +#include + +#include + +#include "common.h" + +#define XI_FREQUENCY 12000000 +#define XTI_FREQUENCY 32768 + +#ifdef CONFIG_MTD_NAND_TCC +/* NAND */ +static struct tcc_nand_platform_data tcc8k_sdk_nand_data = { + .width = 1, + .hw_ecc = 0, +}; +#endif + +static void __init tcc8k_init(void) +{ +#ifdef CONFIG_MTD_NAND_TCC + tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data; + platform_device_register(&tcc_nand_device); +#endif +} + +static void __init tcc8k_init_timer(void) +{ + tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY); +} + +static struct sys_timer tcc8k_timer = { + .init = tcc8k_init_timer, +}; + +static void __init tcc8k_map_io(void) +{ + tcc8k_map_common_io(); +} + +MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") + .phys_io = 0x90000000, + .io_pg_offst = ((0xf1000000) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x00000100, + .map_io = tcc8k_map_io, + .init_irq = tcc8k_init_irq, + .init_machine = tcc8k_init, + .timer = &tcc8k_timer, +MACHINE_END -- cgit v1.2.3 From 29aeb3cfeb88ecdb2febb5da247d0cf6a82f8831 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 6 Sep 2010 22:15:08 +0100 Subject: ARM: 6337/2: AB8500 I2C platform configuration and irq This patch adds the platform part of the AB8500 PRCMU I2C access driver. The old irq name AB4500 is changed to AB8500. Signed-off-by: Mattias Wallin Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/board-mop500.c | 31 +++++++++++++++++++++++++++---- arch/arm/mach-ux500/include/mach/irqs.h | 2 +- 2 files changed, 28 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index de310326df1c..642b8e60d119 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "pins-db8500.h" #include "board-mop500.h" @@ -76,9 +77,27 @@ static struct ab8500_platform_data ab8500_platdata = { .irq_base = MOP500_AB8500_IRQ_BASE, }; -static struct spi_board_info u8500_spi_devices[] = { +static struct resource ab8500_resources[] = { + [0] = { + .start = IRQ_AB8500, + .end = IRQ_AB8500, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device ab8500_device = { + .name = "ab8500-i2c", + .id = 0, + .dev = { + .platform_data = &ab8500_platdata, + }, + .num_resources = 1, + .resource = ab8500_resources, +}; + +static struct spi_board_info ab8500_spi_devices[] = { { - .modalias = "ab8500", + .modalias = "ab8500-spi", .controller_data = &ab4500_chip_info, .platform_data = &ab8500_platdata, .max_speed_hz = 12000000, @@ -166,8 +185,12 @@ static void __init u8500_init_machine(void) mop500_sdi_init(); - spi_register_board_info(u8500_spi_devices, - ARRAY_SIZE(u8500_spi_devices)); + /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */ + if (cpu_is_u8500ed() || cpu_is_u8500v10()) + spi_register_board_info(ab8500_spi_devices, + ARRAY_SIZE(ab8500_spi_devices)); + else /* If HW is v.1.1 or later use I2C to access AB8500 */ + platform_device_register(&ab8500_device); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 0e7a2cec1994..0d552d9c9c00 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -40,7 +40,7 @@ #define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) #define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) #define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) -#define IRQ_AB4500 (IRQ_SHPI_START + 40) +#define IRQ_AB8500 (IRQ_SHPI_START + 40) #define IRQ_PRCMU (IRQ_SHPI_START + 47) #define IRQ_DISP (IRQ_SHPI_START + 48) #define IRQ_SiPI3 (IRQ_SHPI_START + 49) -- cgit v1.2.3 From eaa7f2d50de08efcebb3909ad81fbd76220c9b95 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Mon, 13 Sep 2010 12:37:52 +0100 Subject: ARM: 6371/1: ux500: add DB5500 pins Acked-by: Linus Walleij Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/mach-ux500/pins-db5500.h | 620 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 620 insertions(+) create mode 100644 arch/arm/mach-ux500/pins-db5500.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h new file mode 100644 index 000000000000..bf50c21fe69d --- /dev/null +++ b/arch/arm/mach-ux500/pins-db5500.h @@ -0,0 +1,620 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent + */ + +#ifndef __MACH_DB5500_PINS_H +#define __MACH_DB5500_PINS_H + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_SM_A3 PIN_CFG(1, ALT_A) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_SM_A4 PIN_CFG(2, ALT_A) +#define GPIO2_SM_AVD PIN_CFG(2, ALT_B) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A) +#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A) +#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A) +#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A) +#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A) +#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A) +#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A) +#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A) +#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A) +#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B) +#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A) +#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B) +#define GPIO14_SM_CKO PIN_CFG(14, ALT_C) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_SM_A5 PIN_CFG(15, ALT_A) +#define GPIO15_SM_CLE PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A) +#define GPIO16_SM_OEn PIN_CFG(16, ALT_B) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A) +#define GPIO17_SM_WEn PIN_CFG(17, ALT_B) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_SM_A6 PIN_CFG(18, ALT_A) +#define GPIO18_SM_ALE PIN_CFG(18, ALT_B) +#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A) +#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A) +#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A) +#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A) +#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A) +#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B) +#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A) +#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B) +#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A) +#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B) +#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A) +#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A) +#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_U0_TXD PIN_CFG(28, ALT_A) +#define GPIO28_SM_A0 PIN_CFG(28, ALT_B) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_U0_RXD PIN_CFG(29, ALT_A) +#define GPIO29_SM_A1 PIN_CFG(29, ALT_B) +#define GPIO29_PWM_0 PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SM_A2 PIN_CFG(30, ALT_B) +#define GPIO30_PWM_1 PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A) +#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B) +#define GPIO31_PWM_2 PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A) +#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A) +#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A) +#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A) +#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A) +#define GPIO64_U0_TXD PIN_CFG(64, ALT_B) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A) +#define GPIO65_U0_RXD PIN_CFG(65, ALT_B) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_USB_STP PIN_CFG(72, ALT_A) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_USB_DIR PIN_CFG(73, ALT_A) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_USB_NXT PIN_CFG(74, ALT_A) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_IRQn PIN_CFG(78, ALT_A) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A) +#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B) +#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A) +#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B) +#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C) + +#define GPIO98_GPIO PIN_CFG(98, GPIO) +#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A) +#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B) +#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C) + +#define GPIO99_GPIO PIN_CFG(99, GPIO) +#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A) +#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B) +#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C) + +#define GPIO100_GPIO PIN_CFG(100, GPIO) +#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A) + +#define GPIO101_GPIO PIN_CFG(101, GPIO) +#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_KP_I0 PIN_CFG(128, ALT_A) +#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_KP_O0 PIN_CFG(129, ALT_A) +#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_KP_I1 PIN_CFG(130, ALT_A) +#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_KP_O1 PIN_CFG(131, ALT_A) +#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_KP_I2 PIN_CFG(132, ALT_A) +#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B) +#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_KP_O2 PIN_CFG(133, ALT_A) +#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B) +#define GPIO133_U0_RXD PIN_CFG(133, ALT_C) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_KP_I3 PIN_CFG(134, ALT_A) +#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B) +#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_KP_O3 PIN_CFG(135, ALT_A) +#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B) +#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_KP_I4 PIN_CFG(136, ALT_A) +#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B) +#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_KP_O4 PIN_CFG(137, ALT_A) +#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B) +#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_KP_I5 PIN_CFG(138, ALT_A) +#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B) +#define GPIO138_U0_TXD PIN_CFG(138, ALT_C) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_KP_O5 PIN_CFG(139, ALT_A) +#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B) +#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_KP_I6 PIN_CFG(140, ALT_A) +#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B) +#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_KP_O6 PIN_CFG(141, ALT_A) +#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B) +#define GPIO141_U0_RXD PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_KP_I7 PIN_CFG(142, ALT_A) +#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B) +#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_KP_O7 PIN_CFG(143, ALT_A) +#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B) +#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A) +#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B) +#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A) +#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B) +#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_PWM_0 PIN_CFG(146, ALT_A) +#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_PWM_1 PIN_CFG(147, ALT_A) +#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_PWM_2 PIN_CFG(148, ALT_A) +#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_GPS_START PIN_CFG(164, ALT_A) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A) +#define GPIO165_U3_RXD PIN_CFG(165, ALT_B) +#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A) +#define GPIO166_U3_TXD PIN_CFG(166, ALT_B) +#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A) +#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B) +#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A) +#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B) +#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A) +#define GPIO169_DDR_RC PIN_CFG(169, ALT_B) +#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A) +#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B) +#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C) + +#define GPIO172_GPIO PIN_CFG(172, GPIO) +#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A) +#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B) +#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C) + +#define GPIO173_GPIO PIN_CFG(173, GPIO) +#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A) +#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B) +#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C) + +#define GPIO174_GPIO PIN_CFG(174, GPIO) +#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A) +#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B) +#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C) + +#define GPIO175_GPIO PIN_CFG(175, GPIO) +#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A) +#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B) +#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C) + +#define GPIO176_GPIO PIN_CFG(176, GPIO) +#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A) +#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B) + +#define GPIO177_GPIO PIN_CFG(177, GPIO) +#define GPIO177_U2_RXD PIN_CFG(177, ALT_A) +#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B) +#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C) + +#define GPIO178_GPIO PIN_CFG(178, GPIO) +#define GPIO178_U2_TXD PIN_CFG(178, ALT_A) +#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B) +#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C) + +#define GPIO179_GPIO PIN_CFG(179, GPIO) +#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A) +#define GPIO179_U3_RXD PIN_CFG(179, ALT_B) +#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C) + +#define GPIO180_GPIO PIN_CFG(180, GPIO) +#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A) +#define GPIO180_U3_TXD PIN_CFG(180, ALT_B) +#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C) + +#define GPIO185_GPIO PIN_CFG(185, GPIO) +#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A) +#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B) + +#define GPIO186_GPIO PIN_CFG(186, GPIO) +#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A) +#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B) + +#define GPIO187_GPIO PIN_CFG(187, GPIO) +#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A) +#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B) + +#define GPIO188_GPIO PIN_CFG(188, GPIO) +#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A) +#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B) + +#define GPIO189_GPIO PIN_CFG(189, GPIO) +#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A) +#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B) + +#define GPIO190_GPIO PIN_CFG(190, GPIO) +#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A) +#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B) + +#define GPIO191_GPIO PIN_CFG(191, GPIO) +#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A) +#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B) +#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A) +#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B) +#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A) +#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B) +#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A) +#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B) +#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A) +#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B) +#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A) +#define GPIO196_U0_RXD PIN_CFG(196, ALT_B) +#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A) +#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A) +#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_U1_TXD PIN_CFG(200, ALT_A) +#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_U1_RXD PIN_CFG(201, ALT_A) +#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A) +#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A) +#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A) +#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B) +#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A) +#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B) +#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A) +#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B) +#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A) +#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B) +#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A) +#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B) +#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A) +#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B) +#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A) +#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A) +#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A) +#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A) +#define GPIO213_LCD_DE PIN_CFG(213, ALT_B) +#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A) +#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B) +#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A) +#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B) +#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A) +#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A) +#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B) +#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A) +#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A) +#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A) +#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A) +#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A) +#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A) +#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A) +#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A) +#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A) +#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A) +#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B) + +#endif -- cgit v1.2.3 From f066439cfc37d498a06de76fcab8c21d4094ca64 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Mon, 13 Sep 2010 12:39:38 +0100 Subject: ARM: 6372/1: ux500: add DB5500 DMA event lines Acked-by: Linus Walleij Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/mach-ux500/ste-dma40-db5500.h | 135 +++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 arch/arm/mach-ux500/ste-dma40-db5500.h (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h new file mode 100644 index 000000000000..cb2110c32858 --- /dev/null +++ b/arch/arm/mach-ux500/ste-dma40-db5500.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Rabin Vincent for ST-Ericsson + * License terms: GNU General Public License (GPL) version 2 + * + * DB5500-SoC-specific configuration for DMA40 + */ + +#ifndef STE_DMA40_DB5500_H +#define STE_DMA40_DB5500_H + +#define DB5500_DMA_NR_DEV 64 + +enum dma_src_dev_type { + DB5500_DMA_DEV0_SPI0_RX = 0, + DB5500_DMA_DEV1_SPI1_RX = 1, + DB5500_DMA_DEV2_SPI2_RX = 2, + DB5500_DMA_DEV3_SPI3_RX = 3, + DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4, + DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5, + DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6, + DB5500_DMA_DEV7_IRDA_RFS = 7, + DB5500_DMA_DEV8_IRDA_FIFO_RX = 8, + DB5500_DMA_DEV9_MSP0_RX = 9, + DB5500_DMA_DEV10_MSP1_RX = 10, + DB5500_DMA_DEV11_MSP2_RX = 11, + DB5500_DMA_DEV12_UART0_RX = 12, + DB5500_DMA_DEV13_UART1_RX = 13, + DB5500_DMA_DEV14_UART2_RX = 14, + DB5500_DMA_DEV15_UART3_RX = 15, + DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16, + DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17, + DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18, + DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19, + DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20, + DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21, + DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22, + DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23, + DB5500_DMA_DEV24_SDMMC0_RX = 24, + DB5500_DMA_DEV25_SDMMC1_RX = 25, + DB5500_DMA_DEV26_SDMMC2_RX = 26, + DB5500_DMA_DEV27_SDMMC3_RX = 27, + DB5500_DMA_DEV28_SDMMC4_RX = 28, + /* 29 - 32 not used */ + DB5500_DMA_DEV33_SDMMC0_RX = 33, + DB5500_DMA_DEV34_SDMMC1_RX = 34, + DB5500_DMA_DEV35_SDMMC2_RX = 35, + DB5500_DMA_DEV36_SDMMC3_RX = 36, + DB5500_DMA_DEV37_SDMMC4_RX = 37, + DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38, + DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39, + DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40, + DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41, + DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42, + DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43, + DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44, + DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45, + /* 46 not used */ + DB5500_DMA_DEV47_MCDE_RX = 47, + DB5500_DMA_DEV48_CRYPTO1_RX = 48, + /* 49, 50 not used */ + DB5500_DMA_DEV49_I2C1_RX = 51, + DB5500_DMA_DEV50_I2C3_RX = 52, + DB5500_DMA_DEV51_I2C2_RX = 53, + /* 54 - 60 not used */ + DB5500_DMA_DEV61_CRYPTO0_RX = 61, + /* 62, 63 not used */ +}; + +enum dma_dest_dev_type { + DB5500_DMA_DEV0_SPI0_TX = 0, + DB5500_DMA_DEV1_SPI1_TX = 1, + DB5500_DMA_DEV2_SPI2_TX = 2, + DB5500_DMA_DEV3_SPI3_TX = 3, + DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4, + DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5, + DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6, + DB5500_DMA_DEV7_IRRC_TX = 7, + DB5500_DMA_DEV8_IRDA_FIFO_TX = 8, + DB5500_DMA_DEV9_MSP0_TX = 9, + DB5500_DMA_DEV10_MSP1_TX = 10, + DB5500_DMA_DEV11_MSP2_TX = 11, + DB5500_DMA_DEV12_UART0_TX = 12, + DB5500_DMA_DEV13_UART1_TX = 13, + DB5500_DMA_DEV14_UART2_TX = 14, + DB5500_DMA_DEV15_UART3_TX = 15, + DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16, + DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17, + DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18, + DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19, + DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20, + DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21, + DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22, + DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23, + DB5500_DMA_DEV24_SDMMC0_TX = 24, + DB5500_DMA_DEV25_SDMMC1_TX = 25, + DB5500_DMA_DEV26_SDMMC2_TX = 26, + DB5500_DMA_DEV27_SDMMC3_TX = 27, + DB5500_DMA_DEV28_SDMMC4_TX = 28, + /* 29 - 31 not used */ + DB5500_DMA_DEV32_FSMC_TX = 32, + DB5500_DMA_DEV33_SDMMC0_TX = 33, + DB5500_DMA_DEV34_SDMMC1_TX = 34, + DB5500_DMA_DEV35_SDMMC2_TX = 35, + DB5500_DMA_DEV36_SDMMC3_TX = 36, + DB5500_DMA_DEV37_SDMMC4_TX = 37, + DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38, + DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39, + DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40, + DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41, + DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42, + DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43, + DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44, + DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45, + /* 46 not used */ + DB5500_DMA_DEV47_STM_TX = 47, + DB5500_DMA_DEV48_CRYPTO1_TX = 48, + DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49, + DB5500_DMA_DEV50_HASH1_TX = 50, + DB5500_DMA_DEV51_I2C1_TX = 51, + DB5500_DMA_DEV52_I2C3_TX = 52, + DB5500_DMA_DEV53_I2C2_TX = 53, + /* 54, 55 not used */ + DB5500_DMA_MEMCPY_TX_1 = 56, + DB5500_DMA_MEMCPY_TX_2 = 57, + DB5500_DMA_MEMCPY_TX_3 = 58, + DB5500_DMA_MEMCPY_TX_4 = 59, + DB5500_DMA_MEMCPY_TX_5 = 60, + DB5500_DMA_DEV61_CRYPTO0_TX = 61, + DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62, + DB5500_DMA_DEV63_HASH0_TX = 63, +}; + +#endif -- cgit v1.2.3 From 9d704c04ff8ae61b60935d67ce334b18fc70f1b2 Mon Sep 17 00:00:00 2001 From: Sundar Iyer Date: Wed, 15 Sep 2010 10:45:51 +0100 Subject: ARM: 6391/1: ux500: add CPU hotplug support Acked-by: Linus Walleij Signed-off-by: Sundar Iyer Signed-off-by: Russell King --- arch/arm/mach-ux500/Makefile | 1 + arch/arm/mach-ux500/hotplug.c | 75 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-ux500/platsmp.c | 2 ++ 3 files changed, 78 insertions(+) create mode 100644 arch/arm/mach-ux500/hotplug.c (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 009731864399..bb3e74e6ab36 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o obj-$(CONFIG_MACH_U5500) += board-u5500.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o +obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c new file mode 100644 index 000000000000..b782a03024be --- /dev/null +++ b/arch/arm/mach-ux500/hotplug.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * Based on ARM realview platform + * + * Author: Sundar Iyer + * + */ +#include +#include +#include +#include + +#include + +extern volatile int pen_release; + +static DECLARE_COMPLETION(cpu_killed); + +static inline void platform_do_lowpower(unsigned int cpu) +{ + flush_cache_all(); + + /* we put the platform to just WFI */ + for (;;) { + __asm__ __volatile__("dsb\n\t" "wfi\n\t" + : : : "memory"); + if (pen_release == cpu) { + /* + * OK, proper wakeup, we're done + */ + break; + } + } +} + +int platform_cpu_kill(unsigned int cpu) +{ + return wait_for_completion_timeout(&cpu_killed, 5000); +} + +/* + * platform-specific code to shutdown a CPU + * + * Called with IRQs disabled + */ +void platform_cpu_die(unsigned int cpu) +{ +#ifdef DEBUG + unsigned int this_cpu = hard_smp_processor_id(); + + if (cpu != this_cpu) { + printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n", + this_cpu, cpu); + BUG(); + } +#endif + + printk(KERN_NOTICE "CPU%u: shutdown\n", cpu); + complete(&cpu_killed); + + /* directly enter low power state, skipping secure registers */ + platform_do_lowpower(cpu); +} + +int platform_cpu_disable(unsigned int cpu) +{ + /* + * we don't allow CPU 0 to be shutdown (it is still too special + * e.g. clock tick interrupts) + */ + return cpu == 0 ? -EPERM : 0; +} diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 438ef16aec90..9e4c678de785 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -78,6 +78,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); + smp_cross_call(cpumask_of(cpu)); + timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { if (pen_release == -1) -- cgit v1.2.3 From 4f724beace1be4ba3dbd1a75cff3940354e3ff4f Mon Sep 17 00:00:00 2001 From: Sundar Iyer Date: Wed, 15 Sep 2010 10:50:59 +0100 Subject: ARM: 6392/1: ux500: add ab8500-regulators machine specific data From: Sundar R Iyer Reviewed-by: Mark Brown Acked-by: Linus Walleij Acked-by: Bengt JONSSON Signed-off-by: Sundar R Iyer Signed-off-by: Russell King --- arch/arm/mach-ux500/Makefile | 1 + arch/arm/mach-ux500/board-mop500-regulators.c | 101 ++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 arch/arm/mach-ux500/board-mop500-regulators.c (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index bb3e74e6ab36..46dbaf640422 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_MACH_U5500) += board-u5500.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o +obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c new file mode 100644 index 000000000000..1187f1fc2e53 --- /dev/null +++ b/arch/arm/mach-ux500/board-mop500-regulators.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + * + * Author: Sundar Iyer + * + * MOP500 board specific initialization for regulators + */ +#include +#include + +/* supplies to the display/camera */ +static struct regulator_init_data ab8500_vaux1_regulator = { + .constraints = { + .name = "V-DISPLAY", + .min_uV = 2500000, + .max_uV = 2900000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_STATUS, + }, +}; + +/* supplies to the on-board eMMC */ +static struct regulator_init_data ab8500_vaux2_regulator = { + .constraints = { + .name = "V-eMMC1", + .min_uV = 1100000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for VAUX3, supplies to SDcard slots */ +static struct regulator_init_data ab8500_vaux3_regulator = { + .constraints = { + .name = "V-MMC-SD", + .min_uV = 1100000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE| + REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for tvout, gpadc, TVOUT LDO */ +static struct regulator_init_data ab8500_vtvout_init = { + .constraints = { + .name = "V-TVOUT", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for ab8500-vaudio, VAUDIO LDO */ +static struct regulator_init_data ab8500_vaudio_init = { + .constraints = { + .name = "V-AUD", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for v-anamic1 VAMic1-LDO */ +static struct regulator_init_data ab8500_vamic1_init = { + .constraints = { + .name = "V-AMIC1", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */ +static struct regulator_init_data ab8500_vamic2_init = { + .constraints = { + .name = "V-AMIC2", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for v-dmic, VDMIC LDO */ +static struct regulator_init_data ab8500_vdmic_init = { + .constraints = { + .name = "V-DMIC", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for v-intcore12, VINTCORE12 LDO */ +static struct regulator_init_data ab8500_vintcore_init = { + .constraints = { + .name = "V-INTCORE", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +/* supply for U8500 CSI/DSI, VANA LDO */ +static struct regulator_init_data ab8500_vana_init = { + .constraints = { + .name = "V-CSI/DSI", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + -- cgit v1.2.3 From 0fc73099dd25df2c5181b7bad57d1faa5cd12d3c Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 13 Sep 2010 15:57:05 +0100 Subject: ARM: 6378/1: Allow lazy cache flushing via PG_arch_1 for highmem pages Commit d73cd42 forced non-lazy cache flushing of highmem pages in flush_dcache_page(). This isn't needed since __flush_dcache_page() (called lazily from update_mmu_cache) can handle highmem pages (fixed by commit 7e5a69e). Signed-off-by: Catalin Marinas Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/mm/flush.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index c6844cb9b508..87dd5ffdfa2d 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -247,7 +247,7 @@ void flush_dcache_page(struct page *page) mapping = page_mapping(page); #ifndef CONFIG_SMP - if (!PageHighMem(page) && mapping && !mapping_mapped(mapping)) + if (mapping && !mapping_mapped(mapping)) set_bit(PG_dcache_dirty, &page->flags); else #endif -- cgit v1.2.3 From c01778001a4f5ad9c62d882776235f3f31922fdd Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 13 Sep 2010 15:57:36 +0100 Subject: ARM: 6379/1: Assume new page cache pages have dirty D-cache There are places in Linux where writes to newly allocated page cache pages happen without a subsequent call to flush_dcache_page() (several PIO drivers including USB HCD). This patch changes the meaning of PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly mapped page in update_mmu_cache(). The patch also sets the PG_arch_1 bit in the DMA cache maintenance function to avoid additional cache flushing in update_mmu_cache(). Tested-by: Rabin Vincent Cc: Nicolas Pitre Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 6 +++--- arch/arm/include/asm/tlbflush.h | 2 +- arch/arm/mm/copypage-v4mc.c | 2 +- arch/arm/mm/copypage-v6.c | 2 +- arch/arm/mm/copypage-xscale.c | 2 +- arch/arm/mm/dma-mapping.c | 6 ++++++ arch/arm/mm/fault-armv.c | 4 ++-- arch/arm/mm/flush.c | 3 ++- 8 files changed, 17 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 4656a24058d2..d3730f0f4b50 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -137,10 +137,10 @@ #endif /* - * This flag is used to indicate that the page pointed to by a pte - * is dirty and requires cleaning before returning it to the user. + * This flag is used to indicate that the page pointed to by a pte is clean + * and does not require cleaning before returning it to the user. */ -#define PG_dcache_dirty PG_arch_1 +#define PG_dcache_clean PG_arch_1 /* * MM Cache Management diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 33b546ae72d4..9ad329ad7458 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -560,7 +560,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); #endif /* - * if PG_dcache_dirty is set for the page, we need to ensure that any + * If PG_dcache_clean is not set for the page, we need to ensure that any * cache entries for the kernels virtual memory range are written * back to the page. */ diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c index 598c51ad5071..b8061519ce77 100644 --- a/arch/arm/mm/copypage-v4mc.c +++ b/arch/arm/mm/copypage-v4mc.c @@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from, { void *kto = kmap_atomic(to, KM_USER1); - if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) + if (!test_and_set_bit(PG_dcache_clean, &from->flags)) __flush_dcache_page(page_mapping(from), from); spin_lock(&minicache_lock); diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c index f55fa1044f72..bdba6c65c901 100644 --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c @@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to, unsigned int offset = CACHE_COLOUR(vaddr); unsigned long kfrom, kto; - if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) + if (!test_and_set_bit(PG_dcache_clean, &from->flags)) __flush_dcache_page(page_mapping(from), from); /* FIXME: not highmem safe */ diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index 9920c0ae2096..649bbcd325bf 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c @@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from, { void *kto = kmap_atomic(to, KM_USER1); - if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) + if (!test_and_set_bit(PG_dcache_clean, &from->flags)) __flush_dcache_page(page_mapping(from), from); spin_lock(&minicache_lock); diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 4bc43e535d3b..e4dd0646e859 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -523,6 +523,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off, outer_inv_range(paddr, paddr + size); dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); + + /* + * Mark the D-cache clean for this page to avoid extra flushing. + */ + if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) + set_bit(PG_dcache_clean, &page->flags); } EXPORT_SYMBOL(___dma_page_dev_to_cpu); diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 9b906dec1ca1..58846cbd0e0b 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, * a page table, or changing an existing PTE. Basically, there are two * things that we need to take care of: * - * 1. If PG_dcache_dirty is set for the page, we need to ensure + * 1. If PG_dcache_clean is not set for the page, we need to ensure * that any cache entries for the kernels virtual memory * range are written back to the page. * 2. If we have multiple shared mappings of the same space in @@ -169,7 +169,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, mapping = page_mapping(page); #ifndef CONFIG_SMP - if (test_and_clear_bit(PG_dcache_dirty, &page->flags)) + if (!test_and_set_bit(PG_dcache_clean, &page->flags)) __flush_dcache_page(mapping, page); #endif if (mapping) { diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 87dd5ffdfa2d..b4efce9b7985 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -248,7 +248,7 @@ void flush_dcache_page(struct page *page) #ifndef CONFIG_SMP if (mapping && !mapping_mapped(mapping)) - set_bit(PG_dcache_dirty, &page->flags); + clear_bit(PG_dcache_clean, &page->flags); else #endif { @@ -257,6 +257,7 @@ void flush_dcache_page(struct page *page) __flush_dcache_aliases(mapping, page); else if (mapping) __flush_icache_all(); + set_bit(PG_dcache_clean, &page->flags); } } EXPORT_SYMBOL(flush_dcache_page); -- cgit v1.2.3 From 6012191aa9c6ffff3a23b81162298318b56d7cb3 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 13 Sep 2010 15:58:06 +0100 Subject: ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT caches On SMP systems, there is a small chance of a PTE becoming visible to a different CPU before the current cache maintenance operations in update_mmu_cache(). To avoid this, cache maintenance must be handled in set_pte_at() (similar to IA-64 and PowerPC). This patch provides a unified VIPT cache handling mechanism and implements the __sync_icache_dcache() function for ARMv6 onwards architectures. It is called from set_pte_at() and replaces the update_mmu_cache(). The latter is still used on VIVT hardware where a vm_area_struct is required. Tested-by: Rabin Vincent Cc: Nicolas Pitre Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/pgtable.h | 26 +++++++++++++++++++++++--- arch/arm/include/asm/tlbflush.h | 10 +++++++++- arch/arm/mm/fault-armv.c | 4 ++-- arch/arm/mm/flush.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 64 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index ab68cf1ef80f..42e694f1d58e 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -278,9 +278,24 @@ extern struct page *empty_zero_page; #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) -#define set_pte_at(mm,addr,ptep,pteval) do { \ - set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \ - } while (0) +#if __LINUX_ARM_ARCH__ < 6 +static inline void __sync_icache_dcache(pte_t pteval) +{ +} +#else +extern void __sync_icache_dcache(pte_t pteval); +#endif + +static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pteval) +{ + if (addr >= TASK_SIZE) + set_pte_ext(ptep, pteval, 0); + else { + __sync_icache_dcache(pteval); + set_pte_ext(ptep, pteval, PTE_EXT_NG); + } +} /* * The following only work if pte_present() is true. @@ -290,8 +305,13 @@ extern struct page *empty_zero_page; #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) +#define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC) #define pte_special(pte) (0) +#define pte_present_user(pte) \ + ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \ + (L_PTE_PRESENT | L_PTE_USER)) + #define PTE_BIT_FUNC(fn,op) \ static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 9ad329ad7458..989c9e57d92b 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -562,10 +562,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); /* * If PG_dcache_clean is not set for the page, we need to ensure that any * cache entries for the kernels virtual memory range are written - * back to the page. + * back to the page. On ARMv6 and later, the cache coherency is handled via + * the set_pte_at() function. */ +#if __LINUX_ARM_ARCH__ < 6 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep); +#else +static inline void update_mmu_cache(struct vm_area_struct *vma, + unsigned long addr, pte_t *ptep) +{ +} +#endif #endif diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 58846cbd0e0b..8440d952ba6d 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -28,6 +28,7 @@ static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE; +#if __LINUX_ARM_ARCH__ < 6 /* * We take the easy way out of this problem - we make the * PTE uncacheable. However, we leave the write buffer on. @@ -168,10 +169,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, return; mapping = page_mapping(page); -#ifndef CONFIG_SMP if (!test_and_set_bit(PG_dcache_clean, &page->flags)) __flush_dcache_page(mapping, page); -#endif if (mapping) { if (cache_is_vivt()) make_coherent(mapping, vma, addr, ptep, pfn); @@ -179,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, __flush_icache_all(); } } +#endif /* __LINUX_ARM_ARCH__ < 6 */ /* * Check whether the write buffer has physical address aliasing diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index b4efce9b7985..dd5b0120b92e 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -215,6 +215,36 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p flush_dcache_mmap_unlock(mapping); } +#if __LINUX_ARM_ARCH__ >= 6 +void __sync_icache_dcache(pte_t pteval) +{ + unsigned long pfn; + struct page *page; + struct address_space *mapping; + + if (!pte_present_user(pteval)) + return; + if (cache_is_vipt_nonaliasing() && !pte_exec(pteval)) + /* only flush non-aliasing VIPT caches for exec mappings */ + return; + pfn = pte_pfn(pteval); + if (!pfn_valid(pfn)) + return; + + page = pfn_to_page(pfn); + if (cache_is_vipt_aliasing()) + mapping = page_mapping(page); + else + mapping = NULL; + + if (!test_and_set_bit(PG_dcache_clean, &page->flags)) + __flush_dcache_page(mapping, page); + /* pte_exec() already checked above for non-aliasing VIPT cache */ + if (cache_is_vipt_nonaliasing() || pte_exec(pteval)) + __flush_icache_all(); +} +#endif + /* * Ensure cache coherency between kernel mapping and userspace mapping * of this page. -- cgit v1.2.3 From 85848dd7ab75fce1134856228582a8df522c91d9 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 13 Sep 2010 15:58:37 +0100 Subject: ARM: 6381/1: Use lazy cache flushing on ARMv7 SMP systems ARMv7 processors like Cortex-A9 broadcast the cache maintenance operations in hardware. This patch allows the flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode similar to the UP case. Note that cache flushing on SMP systems now takes place via the set_pte_at() call (__sync_icache_dcache) and there is no race with other CPUs executing code from the new PTE before the cache flushing took place. Tested-by: Rabin Vincent Cc: Nicolas Pitre Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/smp_plat.h | 4 ++++ arch/arm/mm/flush.c | 13 ++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index e6215305544a..963a338d567b 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h @@ -13,9 +13,13 @@ static inline int tlb_ops_need_broadcast(void) return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2; } +#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7 +#define cache_ops_need_broadcast() 0 +#else static inline int cache_ops_need_broadcast(void) { return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1; } +#endif #endif diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index dd5b0120b92e..2332b774c6b9 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "mm.h" @@ -93,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig #define flush_pfn_alias(pfn,vaddr) do { } while (0) #endif -#ifdef CONFIG_SMP static void flush_ptrace_access_other(void *args) { __flush_icache_all(); } -#endif static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, @@ -122,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, if (vma->vm_flags & VM_EXEC) { unsigned long addr = (unsigned long)kaddr; __cpuc_coherent_kern_range(addr, addr + len); -#ifdef CONFIG_SMP if (cache_ops_need_broadcast()) smp_call_function(flush_ptrace_access_other, NULL, 1); -#endif } } @@ -276,12 +273,10 @@ void flush_dcache_page(struct page *page) mapping = page_mapping(page); -#ifndef CONFIG_SMP - if (mapping && !mapping_mapped(mapping)) + if (!cache_ops_need_broadcast() && + mapping && !mapping_mapped(mapping)) clear_bit(PG_dcache_clean, &page->flags); - else -#endif - { + else { __flush_dcache_page(mapping, page); if (mapping && cache_is_vivt()) __flush_dcache_aliases(mapping, page); -- cgit v1.2.3 From f8b63c184ad13cc8adc3dadb557d4fbc29f76e4d Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Mon, 13 Sep 2010 15:59:07 +0100 Subject: ARM: 6382/1: Remove superfluous flush_kernel_dcache_page() Since page cache pages are now considered 'dirty' by default, the cache flushing is handled via __flush_dcache_page() when a page gets mapped to user space. Highmem pages on VIVT systems are flushed during kunmap() and flush_kernel_dcache_page() was already a no-op in this case. ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE is still defined since ARM needs specific implementations for flush_kernel_vmap_range() and invalidate_kernel_vmap_range(). Cc: Nicolas Pitre Signed-off-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index d3730f0f4b50..042e13994d38 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -405,9 +405,6 @@ static inline void flush_anon_page(struct vm_area_struct *vma, #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE static inline void flush_kernel_dcache_page(struct page *page) { - /* highmem pages are always flushed upon kunmap already */ - if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page)) - __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); } #define flush_dcache_mmap_lock(mapping) \ -- cgit v1.2.3 From fd2ce9c59a63d1daec8d76d272eca5149fb8706a Mon Sep 17 00:00:00 2001 From: Tanmay Upadhyay Date: Thu, 26 Aug 2010 11:11:58 +0530 Subject: [ARM] OpenRD: Enable SD/UART selection for serial port 1 This patch enables users to choose either the SDIO interface or UART1 (RS232/RS485). The selection can be done through kernel parameter. By default the port would be used for SDIO interface. Passing the string "kw_openrd_init_uart1=232" or "kw_openrd_init_uart1=485" enables either the RS-232 or RS-485 port respectively; disabling the SDIO interface. Anything else selects the default SDIO interface. "kw_openrd_init_uart1=485" is ignored on OpenRD-Base as it doesn't have RS485 port. Signed-off-by: Tanmay Upadhyay Acked-by: Alexander Clouter Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/openrd-setup.c | 101 +++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c index fd06be618815..38017c8ac43f 100644 --- a/arch/arm/mach-kirkwood/openrd-setup.c +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -57,7 +58,22 @@ static struct mvsdio_platform_data openrd_mvsdio_data = { }; static unsigned int openrd_mpp_config[] __initdata = { + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP28_GPIO, MPP29_GPIO, + MPP34_GPIO, + 0 +}; + +/* Configure MPP for UART1 */ +static unsigned int openrd_uart1_mpp_config[] __initdata = { + MPP13_UART1_TXD, + MPP14_UART1_RXD, 0 }; @@ -67,6 +83,68 @@ static struct i2c_board_info i2c_board_info[] __initdata = { }, }; +static int __initdata uart1; + +static int __init sd_uart_selection(char *str) +{ + uart1 = -EINVAL; + + /* Default is SD. Change if required, for UART */ + if (!str) + return 0; + + if (!strncmp(str, "232", 3)) { + uart1 = 232; + } else if (!strncmp(str, "485", 3)) { + /* OpenRD-Base doesn't have RS485. Treat is as an + * unknown argument & just have default setting - + * which is SD */ + if (machine_is_openrd_base()) { + uart1 = -ENODEV; + return 1; + } + + uart1 = 485; + } + return 1; +} +/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */ +__setup("kw_openrd_init_uart1=", sd_uart_selection); + +static int __init uart1_mpp_config(void) +{ + kirkwood_mpp_conf(openrd_uart1_mpp_config); + + if (gpio_request(34, "SD_UART1_SEL")) { + printk(KERN_ERR "GPIO request failed for SD/UART1 selection" + ", gpio: 34\n"); + return -EIO; + } + + if (gpio_request(28, "RS232_RS485_SEL")) { + printk(KERN_ERR "GPIO request failed for RS232/RS485 selection" + ", gpio# 28\n"); + gpio_free(34); + return -EIO; + } + + /* Select UART1 + * Pin # 34: 0 => UART1, 1 => SD */ + gpio_direction_output(34, 0); + + /* Select RS232 OR RS485 + * Pin # 28: 0 => RS232, 1 => RS485 */ + if (uart1 == 232) + gpio_direction_output(28, 0); + else + gpio_direction_output(28, 1); + + gpio_free(34); + gpio_free(28); + + return 0; +} + static void __init openrd_init(void) { /* @@ -90,7 +168,6 @@ static void __init openrd_init(void) kirkwood_ge01_init(&openrd_ge01_data); kirkwood_sata_init(&openrd_sata_data); - kirkwood_sdio_init(&openrd_mvsdio_data); kirkwood_i2c_init(); @@ -99,6 +176,28 @@ static void __init openrd_init(void) ARRAY_SIZE(i2c_board_info)); kirkwood_audio_init(); } + + if (uart1 <= 0) { + if (uart1 < 0) + printk(KERN_ERR "Invalid kernel parameter to select " + "UART1. Defaulting to SD. ERROR CODE: %d\n", + uart1); + + /* Select SD + * Pin # 34: 0 => UART1, 1 => SD */ + if (gpio_request(34, "SD_UART1_SEL")) { + printk(KERN_ERR "GPIO request failed for SD/UART1 " + "selection, gpio: 34\n"); + } else { + + gpio_direction_output(34, 1); + gpio_free(34); + kirkwood_sdio_init(&openrd_mvsdio_data); + } + } else { + if (!uart1_mpp_config()) + kirkwood_uart1_init(); + } } static int __init openrd_pci_init(void) -- cgit v1.2.3 From 709406494c0ed7da843bad624f6b16f9a2df4a6c Mon Sep 17 00:00:00 2001 From: Eric Cooper Date: Wed, 15 Sep 2010 10:49:41 -0400 Subject: [ARM] Kirkwood: support for Seagate DockStar This patch adds support for the Seagate FreeAgent DockStar, a Marvell SheevaPlug variant. Signed-off-by: Eric Cooper Signed-off-by: Nicolas Pitre --- arch/arm/configs/kirkwood_defconfig | 1 + arch/arm/mach-kirkwood/Kconfig | 6 ++ arch/arm/mach-kirkwood/Makefile | 1 + arch/arm/mach-kirkwood/dockstar-setup.c | 112 ++++++++++++++++++++++++++++++++ 4 files changed, 120 insertions(+) create mode 100644 arch/arm/mach-kirkwood/dockstar-setup.c (limited to 'arch/arm') diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index ccc9c9959b82..2f7042813765 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -15,6 +15,7 @@ CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_ESATA_SHEEVAPLUG=y CONFIG_MACH_GURUPLUG=y +CONFIG_MACH_DOCKSTAR=y CONFIG_MACH_TS219=y CONFIG_MACH_TS41X=y CONFIG_MACH_OPENRD_BASE=y diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index cc25501b57fa..3d5d66e7aaa0 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -58,6 +58,12 @@ config MACH_TS41X QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS devices. +config MACH_DOCKSTAR + bool "Seagate FreeAgent DockStar" + help + Say 'Y' here if you want your kernel to support the + Seagate FreeAgent DockStar. + config MACH_OPENRD bool diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 295d7baa6ae1..9e43e953226e 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o +obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c new file mode 100644 index 000000000000..a90475d5059c --- /dev/null +++ b/arch/arm/mach-kirkwood/dockstar-setup.c @@ -0,0 +1,112 @@ +/* + * arch/arm/mach-kirkwood/dockstar-setup.c + * + * Seagate FreeAgent DockStar Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + +static struct mtd_partition dockstar_nand_parts[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_1M + }, { + .name = "uImage", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_4M + }, { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + }, +}; + +static struct mv643xx_eth_platform_data dockstar_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static struct gpio_led dockstar_led_pins[] = { + { + .name = "dockstar:green:health", + .default_trigger = "default-on", + .gpio = 46, + .active_low = 1, + }, + { + .name = "dockstar:orange:misc", + .default_trigger = "none", + .gpio = 47, + .active_low = 1, + }, +}; + +static struct gpio_led_platform_data dockstar_led_data = { + .leds = dockstar_led_pins, + .num_leds = ARRAY_SIZE(dockstar_led_pins), +}; + +static struct platform_device dockstar_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &dockstar_led_data, + } +}; + +static unsigned int dockstar_mpp_config[] __initdata = { + MPP29_GPIO, /* USB Power Enable */ + MPP46_GPIO, /* LED green */ + MPP47_GPIO, /* LED orange */ + 0 +}; + +static void __init dockstar_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + + /* setup gpio pin select */ + kirkwood_mpp_conf(dockstar_mpp_config); + + kirkwood_uart0_init(); + kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25); + + if (gpio_request(29, "USB Power Enable") != 0 || + gpio_direction_output(29, 1) != 0) + printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n"); + kirkwood_ehci_init(); + + kirkwood_ge00_init(&dockstar_ge00_data); + + platform_device_register(&dockstar_leds); +} + +MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = dockstar_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END -- cgit v1.2.3 From 84712e9aa43862ded44e47acfaa93612a7eeaf7c Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Sun, 19 Sep 2010 15:33:58 +0200 Subject: [ARM] Kirkwood: add LaCie d2 Network v2 support Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Kconfig | 6 + arch/arm/mach-kirkwood/Makefile | 1 + arch/arm/mach-kirkwood/d2net_v2-setup.c | 323 ++++++++++++++++++++++++++++++++ drivers/leds/Kconfig | 2 +- 4 files changed, 331 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-kirkwood/d2net_v2-setup.c (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3d5d66e7aaa0..34106335c728 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -106,6 +106,12 @@ config MACH_NETSPACE_MAX_V2 Say 'Y' here if you want your kernel to support the LaCie Network Space Max v2 NAS. +config MACH_D2NET_V2 + bool "LaCie d2 Network v2 NAS Board" + help + Say 'Y' here if you want your kernel to support the + LaCie d2 Network v2 NAS. + config MACH_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" help diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 9e43e953226e..b84de6a576db 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o obj-$(CONFIG_MACH_T5325) += t5325-setup.o diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c new file mode 100644 index 000000000000..310c6a0331f6 --- /dev/null +++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c @@ -0,0 +1,323 @@ +/* + * arch/arm/mach-kirkwood/d2net_v2-setup.c + * + * LaCie d2 Network Space v2 Board Setup + * + * Copyright (C) 2010 Simon Guinot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * 512KB SPI Flash on Boot Device + ****************************************************************************/ + +static struct mtd_partition d2net_v2_flash_parts[] = { + { + .name = "u-boot", + .size = MTDPART_SIZ_FULL, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, +}; + +static const struct flash_platform_data d2net_v2_flash = { + .type = "mx25l4005a", + .name = "spi_flash", + .parts = d2net_v2_flash_parts, + .nr_parts = ARRAY_SIZE(d2net_v2_flash_parts), +}; + +static struct spi_board_info __initdata d2net_v2_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &d2net_v2_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data d2net_v2_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +/***************************************************************************** + * I2C devices + ****************************************************************************/ + +static struct at24_platform_data at24c04 = { + .byte_len = SZ_4K / 8, + .page_size = 16, +}; + +/* + * i2c addr | chip | description + * 0x50 | HT24LC04 | eeprom (512B) + */ + +static struct i2c_board_info __initdata d2net_v2_i2c_info[] = { + { + I2C_BOARD_INFO("24c04", 0x50), + .platform_data = &at24c04, + } +}; + +/***************************************************************************** + * SATA + ****************************************************************************/ + +static struct mv_sata_platform_data d2net_v2_sata_data = { + .n_ports = 2, +}; + +#define D2NET_V2_GPIO_SATA0_POWER 16 + +static void __init d2net_v2_sata_power_init(void) +{ + int err; + + err = gpio_request(D2NET_V2_GPIO_SATA0_POWER, "SATA0 power"); + if (err == 0) { + err = gpio_direction_output(D2NET_V2_GPIO_SATA0_POWER, 1); + if (err) + gpio_free(D2NET_V2_GPIO_SATA0_POWER); + } + if (err) + pr_err("d2net_v2: failed to configure SATA0 power GPIO\n"); +} + +/***************************************************************************** + * GPIO keys + ****************************************************************************/ + +#define D2NET_V2_GPIO_PUSH_BUTTON 34 +#define D2NET_V2_GPIO_POWER_SWITCH_ON 13 +#define D2NET_V2_GPIO_POWER_SWITCH_OFF 15 + +#define D2NET_V2_SWITCH_POWER_ON 0x1 +#define D2NET_V2_SWITCH_POWER_OFF 0x2 + +static struct gpio_keys_button d2net_v2_buttons[] = { + [0] = { + .type = EV_SW, + .code = D2NET_V2_SWITCH_POWER_ON, + .gpio = D2NET_V2_GPIO_POWER_SWITCH_ON, + .desc = "Back power switch (on|auto)", + .active_low = 0, + }, + [1] = { + .type = EV_SW, + .code = D2NET_V2_SWITCH_POWER_OFF, + .gpio = D2NET_V2_GPIO_POWER_SWITCH_OFF, + .desc = "Back power switch (auto|off)", + .active_low = 0, + }, + [2] = { + .code = KEY_POWER, + .gpio = D2NET_V2_GPIO_PUSH_BUTTON, + .desc = "Front Push Button", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data d2net_v2_button_data = { + .buttons = d2net_v2_buttons, + .nbuttons = ARRAY_SIZE(d2net_v2_buttons), +}; + +static struct platform_device d2net_v2_gpio_buttons = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &d2net_v2_button_data, + }, +}; + +/***************************************************************************** + * GPIO LEDs + ****************************************************************************/ + +#define D2NET_V2_GPIO_RED_LED 12 + +static struct gpio_led d2net_v2_gpio_led_pins[] = { + { + .name = "d2net_v2:red:fail", + .gpio = D2NET_V2_GPIO_RED_LED, + }, +}; + +static struct gpio_led_platform_data d2net_v2_gpio_leds_data = { + .num_leds = ARRAY_SIZE(d2net_v2_gpio_led_pins), + .leds = d2net_v2_gpio_led_pins, +}; + +static struct platform_device d2net_v2_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &d2net_v2_gpio_leds_data, + }, +}; + +/***************************************************************************** + * Dual-GPIO CPLD LEDs + ****************************************************************************/ + +#define D2NET_V2_GPIO_BLUE_LED_SLOW 29 +#define D2NET_V2_GPIO_BLUE_LED_CMD 30 + +static struct ns2_led d2net_v2_led_pins[] = { + { + .name = "d2net_v2:blue:sata", + .cmd = D2NET_V2_GPIO_BLUE_LED_CMD, + .slow = D2NET_V2_GPIO_BLUE_LED_SLOW, + }, +}; + +static struct ns2_led_platform_data d2net_v2_leds_data = { + .num_leds = ARRAY_SIZE(d2net_v2_led_pins), + .leds = d2net_v2_led_pins, +}; + +static struct platform_device d2net_v2_leds = { + .name = "leds-ns2", + .id = -1, + .dev = { + .platform_data = &d2net_v2_leds_data, + }, +}; + +/***************************************************************************** + * Timer + ****************************************************************************/ + +static void d2net_v2_timer_init(void) +{ + kirkwood_tclk = 166666667; + orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); +} + +struct sys_timer d2net_v2_timer = { + .init = d2net_v2_timer_init, +}; + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +static unsigned int d2net_v2_mpp_config[] __initdata = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Request power-off */ + MPP8_TW0_SDA, + MPP9_TW0_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* Red led */ + MPP13_GPIO, /* Rear power switch (on|auto) */ + MPP14_GPIO, /* USB fuse */ + MPP15_GPIO, /* Rear power switch (auto|off) */ + MPP16_GPIO, /* SATA 0 power */ + MPP21_SATA0_ACTn, + MPP24_GPIO, /* USB mode select */ + MPP26_GPIO, /* USB device vbus */ + MPP28_GPIO, /* USB enable host vbus */ + MPP29_GPIO, /* Blue led (slow register) */ + MPP30_GPIO, /* Blue led (command register) */ + MPP34_GPIO, /* Power button (1 = Released, 0 = Pushed) */ + MPP35_GPIO, /* Inhibit power-off */ + 0 +}; + +#define D2NET_V2_GPIO_POWER_OFF 7 + +static void d2net_v2_power_off(void) +{ + gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1); +} + +static void __init d2net_v2_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(d2net_v2_mpp_config); + + d2net_v2_sata_power_init(); + + kirkwood_ehci_init(); + kirkwood_ge00_init(&d2net_v2_ge00_data); + kirkwood_sata_init(&d2net_v2_sata_data); + kirkwood_uart0_init(); + spi_register_board_info(d2net_v2_spi_slave_info, + ARRAY_SIZE(d2net_v2_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_i2c_init(); + i2c_register_board_info(0, d2net_v2_i2c_info, + ARRAY_SIZE(d2net_v2_i2c_info)); + + platform_device_register(&d2net_v2_leds); + platform_device_register(&d2net_v2_gpio_leds); + platform_device_register(&d2net_v2_gpio_buttons); + + if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 && + gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0) + pm_power_off = d2net_v2_power_off; + else + pr_err("d2net_v2: failed to configure power-off GPIO\n"); +} + +MACHINE_START(D2NET_V2, "LaCie d2 Network v2") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = d2net_v2_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &d2net_v2_timer, +MACHINE_END diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index e4112622e5a2..4206ee0c9cc4 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -304,7 +304,7 @@ config LEDS_MC13783 config LEDS_NS2 tristate "LED support for Network Space v2 GPIO LEDs" - depends on MACH_NETSPACE_V2 || MACH_INETSPACE_V2 || MACH_NETSPACE_MAX_V2 + depends on MACH_NETSPACE_V2 || MACH_INETSPACE_V2 || MACH_NETSPACE_MAX_V2 || D2NET_V2 default y help This option enable support for the dual-GPIO LED found on the -- cgit v1.2.3 From b51d92da4ebb52b61fdc99c911171562673e88ef Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Sun, 19 Sep 2010 15:33:59 +0200 Subject: [ARM] Kirkwood: remove duplicated code in LaCie setup files Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Makefile | 12 +-- arch/arm/mach-kirkwood/d2net_v2-setup.c | 102 ++--------------------- arch/arm/mach-kirkwood/lacie_v2-common.c | 127 +++++++++++++++++++++++++++++ arch/arm/mach-kirkwood/lacie_v2-common.h | 18 ++++ arch/arm/mach-kirkwood/netspace_v2-setup.c | 122 +++------------------------ arch/arm/mach-kirkwood/netxbig_v2-setup.c | 119 ++------------------------- 6 files changed, 175 insertions(+), 325 deletions(-) create mode 100644 arch/arm/mach-kirkwood/lacie_v2-common.c create mode 100644 arch/arm/mach-kirkwood/lacie_v2-common.h (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index b84de6a576db..5dcaa81a2ec3 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -11,12 +11,12 @@ obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o -obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o -obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o -obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o -obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o -obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o -obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o +obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o +obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o +obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o +obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o +obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o +obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o obj-$(CONFIG_MACH_T5325) += t5325-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c index 310c6a0331f6..cd62d0f82a73 100644 --- a/arch/arm/mach-kirkwood/d2net_v2-setup.c +++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c @@ -23,56 +23,19 @@ #include #include #include -#include -#include -#include #include #include -#include -#include #include #include #include #include #include #include -#include #include #include -#include #include "common.h" #include "mpp.h" - -/***************************************************************************** - * 512KB SPI Flash on Boot Device - ****************************************************************************/ - -static struct mtd_partition d2net_v2_flash_parts[] = { - { - .name = "u-boot", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static const struct flash_platform_data d2net_v2_flash = { - .type = "mx25l4005a", - .name = "spi_flash", - .parts = d2net_v2_flash_parts, - .nr_parts = ARRAY_SIZE(d2net_v2_flash_parts), -}; - -static struct spi_board_info __initdata d2net_v2_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &d2net_v2_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; +#include "lacie_v2-common.h" /***************************************************************************** * Ethernet @@ -82,27 +45,6 @@ static struct mv643xx_eth_platform_data d2net_v2_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -static struct at24_platform_data at24c04 = { - .byte_len = SZ_4K / 8, - .page_size = 16, -}; - -/* - * i2c addr | chip | description - * 0x50 | HT24LC04 | eeprom (512B) - */ - -static struct i2c_board_info __initdata d2net_v2_i2c_info[] = { - { - I2C_BOARD_INFO("24c04", 0x50), - .platform_data = &at24c04, - } -}; - /***************************************************************************** * SATA ****************************************************************************/ @@ -111,22 +53,6 @@ static struct mv_sata_platform_data d2net_v2_sata_data = { .n_ports = 2, }; -#define D2NET_V2_GPIO_SATA0_POWER 16 - -static void __init d2net_v2_sata_power_init(void) -{ - int err; - - err = gpio_request(D2NET_V2_GPIO_SATA0_POWER, "SATA0 power"); - if (err == 0) { - err = gpio_direction_output(D2NET_V2_GPIO_SATA0_POWER, 1); - if (err) - gpio_free(D2NET_V2_GPIO_SATA0_POWER); - } - if (err) - pr_err("d2net_v2: failed to configure SATA0 power GPIO\n"); -} - /***************************************************************************** * GPIO keys ****************************************************************************/ @@ -228,20 +154,6 @@ static struct platform_device d2net_v2_leds = { }, }; -/***************************************************************************** - * Timer - ****************************************************************************/ - -static void d2net_v2_timer_init(void) -{ - kirkwood_tclk = 166666667; - orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); -} - -struct sys_timer d2net_v2_timer = { - .init = d2net_v2_timer_init, -}; - /***************************************************************************** * General Setup ****************************************************************************/ @@ -288,18 +200,14 @@ static void __init d2net_v2_init(void) kirkwood_init(); kirkwood_mpp_conf(d2net_v2_mpp_config); - d2net_v2_sata_power_init(); + lacie_v2_hdd_power_init(1); kirkwood_ehci_init(); kirkwood_ge00_init(&d2net_v2_ge00_data); kirkwood_sata_init(&d2net_v2_sata_data); kirkwood_uart0_init(); - spi_register_board_info(d2net_v2_spi_slave_info, - ARRAY_SIZE(d2net_v2_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_i2c_init(); - i2c_register_board_info(0, d2net_v2_i2c_info, - ARRAY_SIZE(d2net_v2_i2c_info)); + lacie_v2_register_flash(); + lacie_v2_register_i2c_devices(); platform_device_register(&d2net_v2_leds); platform_device_register(&d2net_v2_gpio_leds); @@ -319,5 +227,5 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2") .init_machine = d2net_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &d2net_v2_timer, + .timer = &lacie_v2_timer, MACHINE_END diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c new file mode 100644 index 000000000000..d3ea1b6c8a02 --- /dev/null +++ b/arch/arm/mach-kirkwood/lacie_v2-common.c @@ -0,0 +1,127 @@ +/* + * arch/arm/mach-kirkwood/lacie_v2-common.c + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) + ****************************************************************************/ + +static struct mtd_partition lacie_v2_flash_parts[] = { + { + .name = "u-boot", + .size = MTDPART_SIZ_FULL, + .offset = 0, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, +}; + +static const struct flash_platform_data lacie_v2_flash = { + .type = "mx25l4005a", + .name = "spi_flash", + .parts = lacie_v2_flash_parts, + .nr_parts = ARRAY_SIZE(lacie_v2_flash_parts), +}; + +static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &lacie_v2_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +void __init lacie_v2_register_flash(void) +{ + spi_register_board_info(lacie_v2_spi_slave_info, + ARRAY_SIZE(lacie_v2_spi_slave_info)); + kirkwood_spi_init(); +} + +/***************************************************************************** + * I2C devices + ****************************************************************************/ + +static struct at24_platform_data at24c04 = { + .byte_len = SZ_4K / 8, + .page_size = 16, +}; + +/* + * i2c addr | chip | description + * 0x50 | HT24LC04 | eeprom (512B) + */ + +static struct i2c_board_info __initdata lacie_v2_i2c_info[] = { + { + I2C_BOARD_INFO("24c04", 0x50), + .platform_data = &at24c04, + } +}; + +void __init lacie_v2_register_i2c_devices(void) +{ + kirkwood_i2c_init(); + i2c_register_board_info(0, lacie_v2_i2c_info, + ARRAY_SIZE(lacie_v2_i2c_info)); +} + +/***************************************************************************** + * Hard Disk power + ****************************************************************************/ + +static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 }; + +void __init lacie_v2_hdd_power_init(int hdd_num) +{ + int i; + int err; + + /* Power up all hard disks. */ + for (i = 0; i < hdd_num; i++) { + err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL); + if (err == 0) { + err = gpio_direction_output( + lacie_v2_gpio_hdd_power[i], 1); + /* Free the HDD power GPIOs. This allow user-space to + * configure them via the gpiolib sysfs interface. */ + gpio_free(lacie_v2_gpio_hdd_power[i]); + } + if (err) + pr_err("Failed to power up HDD%d\n", i + 1); + } +} + +/***************************************************************************** + * Timer + ****************************************************************************/ + +static void lacie_v2_timer_init(void) +{ + kirkwood_tclk = 166666667; + orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); +} + +struct sys_timer lacie_v2_timer = { + .init = lacie_v2_timer_init, +}; diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h new file mode 100644 index 000000000000..af521315b87b --- /dev/null +++ b/arch/arm/mach-kirkwood/lacie_v2-common.h @@ -0,0 +1,18 @@ +/* + * arch/arm/mach-kirkwood/lacie_v2-common.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H +#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H + +void lacie_v2_register_flash(void); +void lacie_v2_register_i2c_devices(void); +void lacie_v2_hdd_power_init(int hdd_num); + +extern struct sys_timer lacie_v2_timer; + +#endif diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index d26bf324738b..fed264d28f4a 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -24,56 +24,19 @@ #include #include #include -#include -#include -#include #include #include -#include -#include #include #include #include #include #include #include -#include #include #include -#include #include "common.h" #include "mpp.h" - -/***************************************************************************** - * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) - ****************************************************************************/ - -static struct mtd_partition netspace_v2_flash_parts[] = { - { - .name = "u-boot", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, -}; - -static const struct flash_platform_data netspace_v2_flash = { - .type = "mx25l4005a", - .name = "spi_flash", - .parts = netspace_v2_flash_parts, - .nr_parts = ARRAY_SIZE(netspace_v2_flash_parts), -}; - -static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &netspace_v2_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; +#include "lacie_v2-common.h" /***************************************************************************** * Ethernet @@ -83,27 +46,6 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(8), }; -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -static struct at24_platform_data at24c04 = { - .byte_len = SZ_4K / 8, - .page_size = 16, -}; - -/* - * i2c addr | chip | description - * 0x50 | HT24LC04 | eeprom (512B) - */ - -static struct i2c_board_info __initdata netspace_v2_i2c_info[] = { - { - I2C_BOARD_INFO("24c04", 0x50), - .platform_data = &at24c04, - } -}; - /***************************************************************************** * SATA ****************************************************************************/ @@ -112,35 +54,6 @@ static struct mv_sata_platform_data netspace_v2_sata_data = { .n_ports = 2, }; -#define NETSPACE_V2_GPIO_SATA0_POWER 16 -#define NETSPACE_V2_GPIO_SATA1_POWER 17 - -static void __init netspace_v2_sata_power_init(void) -{ - int err; - - err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power"); - if (err == 0) { - err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1); - if (err) - gpio_free(NETSPACE_V2_GPIO_SATA0_POWER); - } - if (err) - pr_err("netspace_v2: failed to setup SATA0 power\n"); - - if (machine_is_netspace_max_v2()) { - err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power"); - if (err == 0) { - err = gpio_direction_output( - NETSPACE_V2_GPIO_SATA1_POWER, 1); - if (err) - gpio_free(NETSPACE_V2_GPIO_SATA1_POWER); - } - if (err) - pr_err("netspace_v2: failed to setup SATA1 power\n"); - } -} - /***************************************************************************** * GPIO keys ****************************************************************************/ @@ -223,20 +136,6 @@ static struct platform_device netspace_v2_leds = { }, }; -/***************************************************************************** - * Timer - ****************************************************************************/ - -static void netspace_v2_timer_init(void) -{ - kirkwood_tclk = 166666667; - orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); -} - -struct sys_timer netspace_v2_timer = { - .init = netspace_v2_timer_init, -}; - /***************************************************************************** * General Setup ****************************************************************************/ @@ -291,18 +190,17 @@ static void __init netspace_v2_init(void) kirkwood_init(); kirkwood_mpp_conf(netspace_v2_mpp_config); - netspace_v2_sata_power_init(); + if (machine_is_netspace_max_v2()) + lacie_v2_hdd_power_init(2); + else + lacie_v2_hdd_power_init(1); kirkwood_ehci_init(); kirkwood_ge00_init(&netspace_v2_ge00_data); kirkwood_sata_init(&netspace_v2_sata_data); kirkwood_uart0_init(); - spi_register_board_info(netspace_v2_spi_slave_info, - ARRAY_SIZE(netspace_v2_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_i2c_init(); - i2c_register_board_info(0, netspace_v2_i2c_info, - ARRAY_SIZE(netspace_v2_i2c_info)); + lacie_v2_register_flash(); + lacie_v2_register_i2c_devices(); platform_device_register(&netspace_v2_leds); platform_device_register(&netspace_v2_gpio_leds); @@ -323,7 +221,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .init_machine = netspace_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &netspace_v2_timer, + .timer = &lacie_v2_timer, MACHINE_END #endif @@ -335,7 +233,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") .init_machine = netspace_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &netspace_v2_timer, + .timer = &lacie_v2_timer, MACHINE_END #endif @@ -347,6 +245,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") .init_machine = netspace_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &netspace_v2_timer, + .timer = &lacie_v2_timer, MACHINE_END #endif diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c index 2bd14c5079de..aec528d6081f 100644 --- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c +++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -23,55 +23,18 @@ #include #include #include -#include -#include -#include #include #include -#include -#include #include #include #include #include #include #include -#include #include -#include #include "common.h" #include "mpp.h" - -/***************************************************************************** - * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) - ****************************************************************************/ - -static struct mtd_partition netxbig_v2_flash_parts[] = { - { - .name = "u-boot", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, -}; - -static const struct flash_platform_data netxbig_v2_flash = { - .type = "mx25l4005a", - .name = "spi_flash", - .parts = netxbig_v2_flash_parts, - .nr_parts = ARRAY_SIZE(netxbig_v2_flash_parts), -}; - -static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &netxbig_v2_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; +#include "lacie_v2-common.h" /***************************************************************************** * Ethernet @@ -85,27 +48,6 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -static struct at24_platform_data at24c04 = { - .byte_len = SZ_4K / 8, - .page_size = 16, -}; - -/* - * i2c addr | chip | description - * 0x50 | HT24LC04 | eeprom (512B) - */ - -static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = { - { - I2C_BOARD_INFO("24c04", 0x50), - .platform_data = &at24c04, - } -}; - /***************************************************************************** * SATA ****************************************************************************/ @@ -114,34 +56,6 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = { .n_ports = 2, }; -static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 }; - -static void __init netxbig_v2_sata_power_init(void) -{ - int i; - int err; - int hdd_nb; - - if (machine_is_net2big_v2()) - hdd_nb = 2; - else - hdd_nb = 5; - - /* Power up all hard disks. */ - for (i = 0; i < hdd_nb; i++) { - err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL); - if (err == 0) { - err = gpio_direction_output( - netxbig_v2_gpio_hdd_power[i], 1); - /* Free the HDD power GPIOs. This allow user-space to - * configure them via the gpiolib sysfs interface. */ - gpio_free(netxbig_v2_gpio_hdd_power[i]); - } - if (err) - pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1); - } -} - /***************************************************************************** * GPIO keys ****************************************************************************/ @@ -245,20 +159,6 @@ static struct platform_device netxbig_v2_gpio_buttons = { * 7 | blink blue on=0.5 sec and blue off=2.5 sec */ -/***************************************************************************** - * Timer - ****************************************************************************/ - -static void netxbig_v2_timer_init(void) -{ - kirkwood_tclk = 166666667; - orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); -} - -struct sys_timer netxbig_v2_timer = { - .init = netxbig_v2_timer_init, -}; - /***************************************************************************** * General Setup ****************************************************************************/ @@ -366,7 +266,10 @@ static void __init netxbig_v2_init(void) else kirkwood_mpp_conf(net5big_v2_mpp_config); - netxbig_v2_sata_power_init(); + if (machine_is_net2big_v2()) + lacie_v2_hdd_power_init(2); + else + lacie_v2_hdd_power_init(5); kirkwood_ehci_init(); kirkwood_ge00_init(&netxbig_v2_ge00_data); @@ -374,12 +277,8 @@ static void __init netxbig_v2_init(void) kirkwood_ge01_init(&netxbig_v2_ge01_data); kirkwood_sata_init(&netxbig_v2_sata_data); kirkwood_uart0_init(); - spi_register_board_info(netxbig_v2_spi_slave_info, - ARRAY_SIZE(netxbig_v2_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_i2c_init(); - i2c_register_board_info(0, netxbig_v2_i2c_info, - ARRAY_SIZE(netxbig_v2_i2c_info)); + lacie_v2_register_flash(); + lacie_v2_register_i2c_devices(); platform_device_register(&netxbig_v2_gpio_buttons); @@ -398,7 +297,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2") .init_machine = netxbig_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &netxbig_v2_timer, + .timer = &lacie_v2_timer, MACHINE_END #endif @@ -410,6 +309,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2") .init_machine = netxbig_v2_init, .map_io = kirkwood_map_io, .init_irq = kirkwood_init_irq, - .timer = &netxbig_v2_timer, + .timer = &lacie_v2_timer, MACHINE_END #endif -- cgit v1.2.3 From c1f9a095600e07fefe64eb94eb711f410100824a Mon Sep 17 00:00:00 2001 From: Ohad Ben-Cohen Date: Thu, 16 Sep 2010 13:16:02 +0200 Subject: wl12xx: make wl12xx.h common to both spi and sdio Move wl12xx.h outside of the spi-specific location, so it can be shared with both spi and sdio solutions. Update all users of spi/wl12xx.h accordingly Signed-off-by: Ohad Ben-Cohen Acked-by: Luciano Coelho Acked-by: Tony Lindgren Signed-off-by: John W. Linville --- MAINTAINERS | 2 +- arch/arm/mach-omap2/board-omap3pandora.c | 1 + arch/arm/mach-omap2/board-rx51-peripherals.c | 2 +- drivers/net/wireless/wl12xx/wl1251_sdio.c | 2 +- drivers/net/wireless/wl12xx/wl1251_spi.c | 2 +- drivers/net/wireless/wl12xx/wl1271_spi.c | 2 +- include/linux/spi/wl12xx.h | 34 ---------------------------- include/linux/wl12xx.h | 34 ++++++++++++++++++++++++++++ 8 files changed, 40 insertions(+), 39 deletions(-) delete mode 100644 include/linux/spi/wl12xx.h create mode 100644 include/linux/wl12xx.h (limited to 'arch/arm') diff --git a/MAINTAINERS b/MAINTAINERS index 80cea03a737e..e9aec08e575a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6324,7 +6324,7 @@ W: http://wireless.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-testing.git S: Maintained F: drivers/net/wireless/wl12xx/wl1271* -F: include/linux/spi/wl12xx.h +F: include/linux/wl12xx.h WL3501 WIRELESS PCMCIA CARD DRIVER M: Arnaldo Carvalho de Melo diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index c0f4f12eba54..9b62b6283c6e 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 03483920ed6e..1cf994299cbe 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/net/wireless/wl12xx/wl1251_sdio.c b/drivers/net/wireless/wl12xx/wl1251_sdio.c index c0b68b0a9aa8..74ba9ced5393 100644 --- a/drivers/net/wireless/wl12xx/wl1251_sdio.c +++ b/drivers/net/wireless/wl12xx/wl1251_sdio.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include "wl1251.h" diff --git a/drivers/net/wireless/wl12xx/wl1251_spi.c b/drivers/net/wireless/wl12xx/wl1251_spi.c index 334ded9881c0..320de79667a6 100644 --- a/drivers/net/wireless/wl12xx/wl1251_spi.c +++ b/drivers/net/wireless/wl12xx/wl1251_spi.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include "wl1251.h" #include "wl1251_reg.h" diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.c b/drivers/net/wireless/wl12xx/wl1271_spi.c index 4cb99c541e2a..c3fdab75ad2a 100644 --- a/drivers/net/wireless/wl12xx/wl1271_spi.c +++ b/drivers/net/wireless/wl12xx/wl1271_spi.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include "wl1271.h" diff --git a/include/linux/spi/wl12xx.h b/include/linux/spi/wl12xx.h deleted file mode 100644 index a20bccf0b5c2..000000000000 --- a/include/linux/spi/wl12xx.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of wl12xx - * - * Copyright (C) 2009 Nokia Corporation - * - * Contact: Luciano Coelho - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef _LINUX_SPI_WL12XX_H -#define _LINUX_SPI_WL12XX_H - -struct wl12xx_platform_data { - void (*set_power)(bool enable); - /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ - int irq; - bool use_eeprom; -}; - -#endif diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h new file mode 100644 index 000000000000..015687a1776d --- /dev/null +++ b/include/linux/wl12xx.h @@ -0,0 +1,34 @@ +/* + * This file is part of wl12xx + * + * Copyright (C) 2009 Nokia Corporation + * + * Contact: Luciano Coelho + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef _LINUX_WL12XX_H +#define _LINUX_WL12XX_H + +struct wl12xx_platform_data { + void (*set_power)(bool enable); + /* SDIO only: IRQ number if WLAN_IRQ line is used, 0 for SDIO IRQs */ + int irq; + bool use_eeprom; +}; + +#endif -- cgit v1.2.3 From b642fde7f137566c993991fd2e7bf6b8274bf625 Mon Sep 17 00:00:00 2001 From: Ohad Ben-Cohen Date: Thu, 16 Sep 2010 01:32:09 +0200 Subject: omap: zoom: add fixed regulator device for wlan Add a fixed regulator vmmc device to enable power control of the wl1271 wlan device. Signed-off-by: Ohad Ben-Cohen Acked-by: Tony Lindgren Signed-off-by: John W. Linville --- arch/arm/mach-omap2/board-zoom-peripherals.c | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6b3984964cc5..f5df9a2b1465 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,8 @@ #include "mux.h" #include "hsmmc.h" +#define OMAP_ZOOM_WLAN_PMENA_GPIO (101) + /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { KEY(0, 0, KEY_E), @@ -106,6 +109,11 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = { .supply = "vmmc", }; +static struct regulator_consumer_supply zoom_vmmc3_supply = { + .supply = "vmmc", + .dev_name = "mmci-omap-hs.2", +}; + /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ static struct regulator_init_data zoom_vmmc1 = { .constraints = { @@ -151,6 +159,32 @@ static struct regulator_init_data zoom_vsim = { .consumer_supplies = &zoom_vsim_supply, }; +static struct regulator_init_data zoom_vmmc3 = { + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &zoom_vmmc3_supply, +}; + +static struct fixed_voltage_config zoom_vwlan = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.8V */ + .gpio = OMAP_ZOOM_WLAN_PMENA_GPIO, + .startup_delay = 70000, /* 70msec */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &zoom_vmmc3, +}; + +static struct platform_device omap_vwlan_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &zoom_vwlan, + }, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -280,6 +314,7 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { omap_i2c_init(); + platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); enable_board_wakeup_source(); } -- cgit v1.2.3 From 80b517f362605f2b6a6cfe086604534290aab2de Mon Sep 17 00:00:00 2001 From: Ohad Ben-Cohen Date: Thu, 16 Sep 2010 01:32:30 +0200 Subject: omap: zoom: add mmc3/wl1271 device support Add MMC3 support on ZOOM, which has the wl1271 device hardwired to. The wl1271 is a 4-wire, 1.8V, embedded SDIO WLAN device with an external IRQ line, and power-controlled by a GPIO-based fixed regulator. Signed-off-by: Ohad Ben-Cohen Acked-by: Tony Lindgren Signed-off-by: John W. Linville --- arch/arm/mach-omap2/board-zoom-peripherals.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index f5df9a2b1465..6aa0728fa15d 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -29,6 +30,7 @@ #include "hsmmc.h" #define OMAP_ZOOM_WLAN_PMENA_GPIO (101) +#define OMAP_ZOOM_WLAN_IRQ_GPIO (162) /* Zoom2 has Qwerty keyboard*/ static int board_keymap[] = { @@ -185,6 +187,12 @@ static struct platform_device omap_vwlan_device = { }, }; +struct wl12xx_platform_data omap_zoom_wlan_data __initdata = { + .irq = OMAP_GPIO_IRQ(OMAP_ZOOM_WLAN_IRQ_GPIO), + /* ZOOM ref clock is 26 MHz */ + .board_ref_clock = 1, +}; + static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "external", @@ -202,6 +210,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = { .nonremovable = true, .power_saving = true, }, + { + .name = "wl1271", + .mmc = 3, + .wires = 4, + .gpio_wp = -EINVAL, + .gpio_cd = -EINVAL, + .nonremovable = true, + }, {} /* Terminator */ }; @@ -313,6 +329,9 @@ static void enable_board_wakeup_source(void) void __init zoom_peripherals_init(void) { + if (wl12xx_set_platform_data(&omap_zoom_wlan_data)) + pr_err("error setting wl12xx data\n"); + omap_i2c_init(); platform_device_register(&omap_vwlan_device); usb_musb_init(&musb_board_data); -- cgit v1.2.3 From 0b1974de66f9ed44f1423449628f4926bf95b854 Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Thu, 23 Sep 2010 11:46:48 +0200 Subject: Fix typo: configuation => configuration Signed-off-by: Thomas Weber Acked-by: David S. Miller Signed-off-by: Jiri Kosina --- arch/arm/mach-omap2/hsmmc.h | 2 +- arch/mips/sibyte/common/sb_tbprof.c | 2 +- drivers/net/bnx2x/bnx2x_link.c | 2 +- drivers/net/irda/ali-ircc.c | 2 +- drivers/net/sb1250-mac.c | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h index 36f0ba8d89e2..6536c31eaba3 100644 --- a/arch/arm/mach-omap2/hsmmc.h +++ b/arch/arm/mach-omap2/hsmmc.h @@ -21,7 +21,7 @@ struct omap2_hsmmc_info { char *name; /* or NULL for default */ struct device *dev; /* returned: pointer to mmc adapter */ int ocr_mask; /* temporary HACK */ - /* Remux (pad configuation) when powering on/off */ + /* Remux (pad configuration) when powering on/off */ void (*remux)(struct device *dev, int slot, int power_on); }; diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index d4ed7a9156f5..a2bdb2e964c0 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -43,7 +43,7 @@ #include #include #else -#error invalid SiByte UART configuation +#error invalid SiByte UART configuration #endif #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c index 0383e3066313..c2146e78d6b1 100644 --- a/drivers/net/bnx2x/bnx2x_link.c +++ b/drivers/net/bnx2x/bnx2x_link.c @@ -3735,7 +3735,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) /* Clear first 3 bits of the control */ val &= ~0x7; /* Set control bits according to - configuation */ + configuration */ val |= (params->xgxs_config_rx[i] & 0x7); DP(NETIF_MSG_LINK, "Setting RX" diff --git a/drivers/net/irda/ali-ircc.c b/drivers/net/irda/ali-ircc.c index a3cb109006a5..92631eb6f6a3 100644 --- a/drivers/net/irda/ali-ircc.c +++ b/drivers/net/irda/ali-ircc.c @@ -142,7 +142,7 @@ static void SetCOMInterrupts(struct ali_ircc_cb *self , unsigned char enable); * Function ali_ircc_init () * * Initialize chip. Find out whay kinds of chips we are dealing with - * and their configuation registers address + * and their configuration registers address */ static int __init ali_ircc_init(void) { diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c index 8e6bd45b9f31..a3f36be459b8 100644 --- a/drivers/net/sb1250-mac.c +++ b/drivers/net/sb1250-mac.c @@ -95,7 +95,7 @@ MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); #include #include #else -#error invalid SiByte MAC configuation +#error invalid SiByte MAC configuration #endif #include #include @@ -106,7 +106,7 @@ MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #define UNIT_INT(n) (K_INT_MAC_0 + (n)) #else -#error invalid SiByte MAC configuation +#error invalid SiByte MAC configuration #endif #ifdef K_INT_PHY @@ -1568,7 +1568,7 @@ static void sbmac_channel_start(struct sbmac_softc *s) M_MAC_RX_ENABLE | M_MAC_TX_ENABLE, s->sbm_macenable); #else -#error invalid SiByte MAC configuation +#error invalid SiByte MAC configuration #endif #ifdef CONFIG_SBMAC_COALESCE -- cgit v1.2.3 From aa88bc0a072b9f02891592d0aa6d0e8d138abf8f Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 6 Aug 2010 09:36:42 -0700 Subject: arm: scoop.c: remove C99 comments Comments should be /* */ not //. Signed-off-by: H Hartley Sweeten Cc: Jiri Kosina Signed-off-by: Jiri Kosina --- arch/arm/common/scoop.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 9012004321dd..c11af1e4bad3 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -44,12 +44,12 @@ void reset_scoop(struct device *dev) { struct scoop_dev *sdev = dev_get_drvdata(dev); - iowrite16(0x0100, sdev->base + SCOOP_MCR); // 00 - iowrite16(0x0000, sdev->base + SCOOP_CDR); // 04 - iowrite16(0x0000, sdev->base + SCOOP_CCR); // 10 - iowrite16(0x0000, sdev->base + SCOOP_IMR); // 18 - iowrite16(0x00FF, sdev->base + SCOOP_IRM); // 14 - iowrite16(0x0000, sdev->base + SCOOP_ISR); // 1C + iowrite16(0x0100, sdev->base + SCOOP_MCR); /* 00 */ + iowrite16(0x0000, sdev->base + SCOOP_CDR); /* 04 */ + iowrite16(0x0000, sdev->base + SCOOP_CCR); /* 10 */ + iowrite16(0x0000, sdev->base + SCOOP_IMR); /* 18 */ + iowrite16(0x00FF, sdev->base + SCOOP_IRM); /* 14 */ + iowrite16(0x0000, sdev->base + SCOOP_ISR); /* 1C */ iowrite16(0x0000, sdev->base + SCOOP_IRM); } -- cgit v1.2.3 From 909ea93b12541a0bac27c495c810ac6d79343986 Mon Sep 17 00:00:00 2001 From: H Hartley Sweeten Date: Fri, 6 Aug 2010 09:40:42 -0700 Subject: arm: uengine.c: remove C99 comments Comments should be /* */ not //. Signed-off-by: H Hartley Sweeten Cc: Jiri Kosina Signed-off-by: Jiri Kosina --- arch/arm/common/uengine.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c index b520e56216a9..bef408f3d76c 100644 --- a/arch/arm/common/uengine.c +++ b/arch/arm/common/uengine.c @@ -312,16 +312,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) b1 = (gpr_a[i] >> 8) & 0xff; b0 = gpr_a[i] & 0xff; - // immed[@ai, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII + /* immed[@ai, (b1 << 8) | b0] */ + /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */ ucode[offset++] = 0xf0; ucode[offset++] = (b1 >> 4); ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6); ucode[offset++] = (b0 << 2); ucode[offset++] = 0x80 | i; - // immed_w1[@ai, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII + /* immed_w1[@ai, (b3 << 8) | b2] */ + /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */ ucode[offset++] = 0xf4; ucode[offset++] = 0x40 | (b3 >> 4); ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6); @@ -340,16 +340,16 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) b1 = (gpr_b[i] >> 8) & 0xff; b0 = gpr_b[i] & 0xff; - // immed[@bi, (b1 << 8) | b0] - // 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV + /* immed[@bi, (b1 << 8) | b0] */ + /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */ ucode[offset++] = 0xf0; ucode[offset++] = (b1 >> 4); ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6); ucode[offset++] = (i << 2) | 0x03; ucode[offset++] = b0; - // immed_w1[@bi, (b3 << 8) | b2] - // 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV + /* immed_w1[@bi, (b3 << 8) | b2] */ + /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */ ucode[offset++] = 0xf4; ucode[offset++] = 0x40 | (b3 >> 4); ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6); @@ -357,7 +357,7 @@ static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b) ucode[offset++] = b2; } - // ctx_arb[kill] + /* ctx_arb[kill] */ ucode[offset++] = 0xe0; ucode[offset++] = 0x00; ucode[offset++] = 0x01; -- cgit v1.2.3 From d1ea13c6e2cce0106531852daaa93dd97aec9580 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 23 Sep 2010 18:40:07 +0200 Subject: genirq: Cleanup irq_chip->typename leftovers 3 years transition phase is enough. Cleanup the last users and remove the cruft. Signed-off-by: Thomas Gleixner Cc: Leo Chen Cc: Hirokazu Takata Cc: Chris Metcalf Cc: Jeff Dike Cc: Chris Zankel --- arch/arm/mach-bcmring/irq.c | 6 +++--- arch/m32r/kernel/irq.c | 2 +- arch/m32r/platforms/m32104ut/setup.c | 2 +- arch/m32r/platforms/m32700ut/setup.c | 8 ++++---- arch/m32r/platforms/mappi/setup.c | 2 +- arch/m32r/platforms/mappi2/setup.c | 2 +- arch/m32r/platforms/mappi3/setup.c | 2 +- arch/m32r/platforms/oaks32r/setup.c | 2 +- arch/m32r/platforms/opsput/setup.c | 6 +++--- arch/m32r/platforms/usrv/setup.c | 4 ++-- arch/tile/kernel/irq.c | 4 ++-- arch/um/kernel/irq.c | 6 +++--- arch/xtensa/kernel/irq.c | 2 +- include/linux/irq.h | 6 ------ kernel/irq/chip.c | 2 -- 15 files changed, 24 insertions(+), 32 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index dc1c4939b0ce..e3152631eb37 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c @@ -67,21 +67,21 @@ static void bcmring_unmask_irq2(unsigned int irq) } static struct irq_chip bcmring_irq0_chip = { - .typename = "ARM-INTC0", + .name = "ARM-INTC0", .ack = bcmring_mask_irq0, .mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */ .unmask = bcmring_unmask_irq0, /* unmaks an interrupt */ }; static struct irq_chip bcmring_irq1_chip = { - .typename = "ARM-INTC1", + .name = "ARM-INTC1", .ack = bcmring_mask_irq1, .mask = bcmring_mask_irq1, .unmask = bcmring_unmask_irq1, }; static struct irq_chip bcmring_irq2_chip = { - .typename = "ARM-SINTC", + .name = "ARM-SINTC", .ack = bcmring_mask_irq2, .mask = bcmring_mask_irq2, .unmask = bcmring_unmask_irq2, diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index 3c71f776872c..7db26f1f082d 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c @@ -51,7 +51,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 922fdfdadeaa..402a59d7219b 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c @@ -65,7 +65,7 @@ static void shutdown_m32104ut_irq(unsigned int irq) static struct irq_chip m32104ut_irq_type = { - .typename = "M32104UT-IRQ", + .name = "M32104UT-IRQ", .startup = startup_m32104ut_irq, .shutdown = shutdown_m32104ut_irq, .enable = enable_m32104ut_irq, diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 9c1bc7487c1e..80b1a026795a 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c @@ -71,7 +71,7 @@ static void shutdown_m32700ut_irq(unsigned int irq) static struct irq_chip m32700ut_irq_type = { - .typename = "M32700UT-IRQ", + .name = "M32700UT-IRQ", .startup = startup_m32700ut_irq, .shutdown = shutdown_m32700ut_irq, .enable = enable_m32700ut_irq, @@ -148,7 +148,7 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq) static struct irq_chip m32700ut_pld_irq_type = { - .typename = "M32700UT-PLD-IRQ", + .name = "M32700UT-PLD-IRQ", .startup = startup_m32700ut_pld_irq, .shutdown = shutdown_m32700ut_pld_irq, .enable = enable_m32700ut_pld_irq, @@ -217,7 +217,7 @@ static void shutdown_m32700ut_lanpld_irq(unsigned int irq) static struct irq_chip m32700ut_lanpld_irq_type = { - .typename = "M32700UT-PLD-LAN-IRQ", + .name = "M32700UT-PLD-LAN-IRQ", .startup = startup_m32700ut_lanpld_irq, .shutdown = shutdown_m32700ut_lanpld_irq, .enable = enable_m32700ut_lanpld_irq, @@ -286,7 +286,7 @@ static void shutdown_m32700ut_lcdpld_irq(unsigned int irq) static struct irq_chip m32700ut_lcdpld_irq_type = { - .typename = "M32700UT-PLD-LCD-IRQ", + .name = "M32700UT-PLD-LCD-IRQ", .startup = startup_m32700ut_lcdpld_irq, .shutdown = shutdown_m32700ut_lcdpld_irq, .enable = enable_m32700ut_lcdpld_irq, diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index fb4b17799b66..ea00c84d6b1b 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c @@ -65,7 +65,7 @@ static void shutdown_mappi_irq(unsigned int irq) static struct irq_chip mappi_irq_type = { - .typename = "MAPPI-IRQ", + .name = "MAPPI-IRQ", .startup = startup_mappi_irq, .shutdown = shutdown_mappi_irq, .enable = enable_mappi_irq, diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index 6a65eda0a056..c049376d0270 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c @@ -72,7 +72,7 @@ static void shutdown_mappi2_irq(unsigned int irq) static struct irq_chip mappi2_irq_type = { - .typename = "MAPPI2-IRQ", + .name = "MAPPI2-IRQ", .startup = startup_mappi2_irq, .shutdown = shutdown_mappi2_irq, .enable = enable_mappi2_irq, diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index 9c337aeac94b..882de25c6e8c 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c @@ -72,7 +72,7 @@ static void shutdown_mappi3_irq(unsigned int irq) static struct irq_chip mappi3_irq_type = { - .typename = "MAPPI3-IRQ", + .name = "MAPPI3-IRQ", .startup = startup_mappi3_irq, .shutdown = shutdown_mappi3_irq, .enable = enable_mappi3_irq, diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index ed865741c38d..d11d93bf74f5 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -63,7 +63,7 @@ static void shutdown_oaks32r_irq(unsigned int irq) static struct irq_chip oaks32r_irq_type = { - .typename = "OAKS32R-IRQ", + .name = "OAKS32R-IRQ", .startup = startup_oaks32r_irq, .shutdown = shutdown_oaks32r_irq, .enable = enable_oaks32r_irq, diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 80d680657019..5f3402a2fbaf 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c @@ -72,7 +72,7 @@ static void shutdown_opsput_irq(unsigned int irq) static struct irq_chip opsput_irq_type = { - .typename = "OPSPUT-IRQ", + .name = "OPSPUT-IRQ", .startup = startup_opsput_irq, .shutdown = shutdown_opsput_irq, .enable = enable_opsput_irq, @@ -149,7 +149,7 @@ static void shutdown_opsput_pld_irq(unsigned int irq) static struct irq_chip opsput_pld_irq_type = { - .typename = "OPSPUT-PLD-IRQ", + .name = "OPSPUT-PLD-IRQ", .startup = startup_opsput_pld_irq, .shutdown = shutdown_opsput_pld_irq, .enable = enable_opsput_pld_irq, @@ -218,7 +218,7 @@ static void shutdown_opsput_lanpld_irq(unsigned int irq) static struct irq_chip opsput_lanpld_irq_type = { - .typename = "OPSPUT-PLD-LAN-IRQ", + .name = "OPSPUT-PLD-LAN-IRQ", .startup = startup_opsput_lanpld_irq, .shutdown = shutdown_opsput_lanpld_irq, .enable = enable_opsput_lanpld_irq, diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index 757302660af8..1beac7a51ed4 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c @@ -63,7 +63,7 @@ static void shutdown_mappi_irq(unsigned int irq) static struct irq_chip mappi_irq_type = { - .typename = "M32700-IRQ", + .name = "M32700-IRQ", .startup = startup_mappi_irq, .shutdown = shutdown_mappi_irq, .enable = enable_mappi_irq, @@ -136,7 +136,7 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq) static struct irq_chip m32700ut_pld_irq_type = { - .typename = "USRV-PLD-IRQ", + .name = "USRV-PLD-IRQ", .startup = startup_m32700ut_pld_irq, .shutdown = shutdown_m32700ut_pld_irq, .enable = enable_m32700ut_pld_irq, diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c index 596c60086930..9a27d563fc30 100644 --- a/arch/tile/kernel/irq.c +++ b/arch/tile/kernel/irq.c @@ -208,7 +208,7 @@ static void tile_irq_chip_eoi(unsigned int irq) } static struct irq_chip tile_irq_chip = { - .typename = "tile_irq_chip", + .name = "tile_irq_chip", .ack = tile_irq_chip_ack, .eoi = tile_irq_chip_eoi, .mask = tile_irq_chip_mask, @@ -288,7 +288,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %s", action->name); for (action = action->next; action; action = action->next) diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index a3f0b04d7101..a746e3037a5b 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c @@ -46,7 +46,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) @@ -369,7 +369,7 @@ static void dummy(unsigned int irq) /* This is used for everything else than the timer. */ static struct irq_chip normal_irq_type = { - .typename = "SIGIO", + .name = "SIGIO", .release = free_irq_by_irq_and_dev, .disable = dummy, .enable = dummy, @@ -378,7 +378,7 @@ static struct irq_chip normal_irq_type = { }; static struct irq_chip SIGVTALRM_irq_type = { - .typename = "SIGVTALRM", + .name = "SIGVTALRM", .release = free_irq_by_irq_and_dev, .shutdown = dummy, /* never called */ .disable = dummy, diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index c64a5d387de5..87508886cbbd 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c @@ -92,7 +92,7 @@ int show_interrupts(struct seq_file *p, void *v) for_each_online_cpu(j) seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->typename); + seq_printf(p, " %14s", irq_desc[i].chip->name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) diff --git a/include/linux/irq.h b/include/linux/irq.h index c03243ad84b4..06273a2a17e7 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -106,7 +106,6 @@ struct msi_desc; * @bus_sync_unlock: function to sync and unlock slow bus (i2c) chips * * @release: release function solely used by UML - * @typename: obsoleted by name, kept as migration helper */ struct irq_chip { const char *name; @@ -135,11 +134,6 @@ struct irq_chip { #ifdef CONFIG_IRQ_RELEASE_METHOD void (*release)(unsigned int irq, void *dev_id); #endif - /* - * For compatibility, ->typename is copied into ->name. - * Will disappear. - */ - const char *typename; }; struct timer_rand_state; diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index b7091d5ca2f8..4ea775cc60f0 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -344,8 +344,6 @@ void irq_chip_set_defaults(struct irq_chip *chip) if (!chip->shutdown) chip->shutdown = chip->disable != default_disable ? chip->disable : default_shutdown; - if (!chip->name) - chip->name = chip->typename; if (!chip->end) chip->end = dummy_irq_chip.end; } -- cgit v1.2.3 From cb922d2596593bac0bf0597eb305cc9bc136cec5 Mon Sep 17 00:00:00 2001 From: Scott Ellis Date: Thu, 23 Sep 2010 18:47:23 -0700 Subject: omap: McBSP: tx_irq_completion used in rx_irq_handler Looks like a typo from commit d6d834b010. Signed-off-by: Scott Ellis Acked-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/mcbsp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e31496e35b0f..0c8612fd8312 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -156,7 +156,7 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) /* Writing zero to RSYNC_ERR clears the IRQ */ MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1)); } else { - complete(&mcbsp_rx->tx_irq_completion); + complete(&mcbsp_rx->rx_irq_completion); } return IRQ_HANDLED; -- cgit v1.2.3 From 3b161e51b254fa7bd3a9b0bd7ca7a2ac8ceaae8b Mon Sep 17 00:00:00 2001 From: Javier Martin Date: Fri, 30 Jul 2010 10:06:01 +0200 Subject: ARM: imx: Add support for Vista Silicon Visstrim_m10 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vista Silicon Visstrim_m10 i.MX27 based board is used as multimedia streaming server, access control and other custom applications. Signed-off-by: Javier Martin Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-imx/Kconfig | 9 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 263 ++++++++++++++++++++++++++++ 3 files changed, 273 insertions(+) create mode 100644 arch/arm/mach-imx/mach-imx27_visstrim_m10.c (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c5c0369bb481..19ed16d0017e 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -163,6 +163,15 @@ config MACH_MX27_3DS Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. +config MACH_IMX27_VISSTRIM_M10 + bool "Vista Silicon i.MX27 Visstrim_m10" + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART + help + Include support for Visstrim_m10 platform and its different variants. + This includes specific configurations for the board and its + peripherals. + config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" select IMX_HAVE_PLATFORM_IMX_UART diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 46a9fdfbbd15..5582692bb176 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o +obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += mach-pca100.o diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c new file mode 100644 index 000000000000..6dad632b83d6 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -0,0 +1,263 @@ +/* + * mach-imx27_visstrim_m10.c + * + * Copyright 2010 Javier Martin + * + * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices-imx27.h" +#include "devices.h" + +#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) +#define SDHC1_IRQ IRQ_GPIOB(25) + +static int visstrim_m10_pins[] = { + /* UART1 (console) */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + /* SDHC1 */ + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + /* Both I2Cs */ + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + /* USB OTG */ + OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, + PC9_PF_USBOTG_DATA0, + PC11_PF_USBOTG_DATA1, + PC10_PF_USBOTG_DATA2, + PC13_PF_USBOTG_DATA3, + PC12_PF_USBOTG_DATA4, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PE25_PF_USBOTG_DATA7, + PE24_PF_USBOTG_CLK, + PE2_PF_USBOTG_DIR, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PB23_PF_USB_PWR, + PB24_PF_USB_OC, +}; + +/* GPIOs used as events for applications */ +static struct gpio_keys_button visstrim_gpio_keys[] = { + { + .type = EV_KEY, + .code = KEY_RESTART, + .gpio = (GPIO_PORTC + 15), + .desc = "Default config", + .active_low = 0, + .wakeup = 1, + }, + { + .type = EV_KEY, + .code = KEY_RECORD, + .gpio = (GPIO_PORTF + 14), + .desc = "Record", + .active_low = 0, + .wakeup = 1, + }, + { + .type = EV_KEY, + .code = KEY_STOP, + .gpio = (GPIO_PORTF + 13), + .desc = "Stop", + .active_low = 0, + .wakeup = 1, + } +}; + +static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = { + .buttons = visstrim_gpio_keys, + .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), +}; + +static struct platform_device visstrim_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &visstrim_gpio_keys_platform_data, + }, +}; + +/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ +static int visstrim_m10_sdhc1_init(struct device *dev, + irq_handler_t detect_irq, void *data) +{ + int ret; + + ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING, + "mmc-detect", data); + return ret; +} + +static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) +{ + free_irq(SDHC1_IRQ, data); +} + +static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { + .init = visstrim_m10_sdhc1_init, + .exit = visstrim_m10_sdhc1_exit, +}; + +/* Visstrim_SM10 NOR flash */ +static struct physmap_flash_data visstrim_m10_flash_data = { + .width = 2, +}; + +static struct resource visstrim_m10_flash_resource = { + .start = 0xc0000000, + .end = 0xc0000000 + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device visstrim_m10_nor_mtd_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &visstrim_m10_flash_data, + }, + .num_resources = 1, + .resource = &visstrim_m10_flash_resource, +}; + +static struct platform_device *platform_devices[] __initdata = { + &visstrim_gpio_keys_device, + &visstrim_m10_nor_mtd_device, + &mxc_fec_device, +}; + +/* Visstrim_M10 uses UART0 as console */ +static const struct imxuart_platform_data uart_pdata __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +/* I2C */ +static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { + .bitrate = 100000, +}; + +static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { + .gpio_base = 240, /* After MX27 internal GPIOs */ + .invert = 0, +}; + +static struct i2c_board_info visstrim_m10_i2c_devices[] = { + { + I2C_BOARD_INFO("pca9555", 0x20), + .platform_data = &visstrim_m10_pca9555_pdata, + }, +}; + +/* USB OTG */ +static int otg_phy_init(struct platform_device *pdev) +{ + gpio_set_value(OTG_PHY_CS_GPIO, 0); + return 0; +} + +static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { + .init = otg_phy_init, + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + +static void __init visstrim_m10_board_init(void) +{ + int ret; + + ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, + ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); + if (ret) + pr_err("Failed to setup pins (%d)\n", ret); + + imx27_add_imx_uart0(&uart_pdata); + + i2c_register_board_info(0, visstrim_m10_i2c_devices, + ARRAY_SIZE(visstrim_m10_i2c_devices)); + imx27_add_i2c_imx0(&visstrim_m10_i2c_data); + imx27_add_i2c_imx1(&visstrim_m10_i2c_data); + mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); + mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} + +static void __init visstrim_m10_timer_init(void) +{ + mx27_clocks_init((unsigned long)25000000); +} + +static struct sys_timer visstrim_m10_timer = { + .init = visstrim_m10_timer_init, +}; + +MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_irq = mx27_init_irq, + .init_machine = visstrim_m10_board_init, + .timer = &visstrim_m10_timer, +MACHINE_END -- cgit v1.2.3 From d17e1c1ac3a1e4befecb34c20dc8cb901aa72aba Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 18 Aug 2010 18:20:24 +0200 Subject: ARM: mx3/mx35_3ds: add physmap-flash NOR at CS0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mx35_3ds comes with 64 MiByte for NOR flash at CS0, add physmap-flash platform device for it. Signed-off-by: Marc Kleine-Budde Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx3/mach-mx35_3ds.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index 1c30d7212f17..73149b8fe92c 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -1,5 +1,6 @@ /* * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix * * Author: Fabio Estevam * @@ -27,6 +28,8 @@ #include #include +#include + #include #include #include @@ -43,8 +46,29 @@ static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static struct physmap_flash_data mx35pdk_flash_data = { + .width = 2, +}; + +static struct resource mx35pdk_flash_resource = { + .start = MX35_CS0_BASE_ADDR, + .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device mx35pdk_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &mx35pdk_flash_data, + }, + .resource = &mx35pdk_flash_resource, + .num_resources = 1, +}; + static struct platform_device *devices[] __initdata = { &mxc_fec_device, + &mx35pdk_flash, }; static struct pad_desc mx35pdk_pads[] = { -- cgit v1.2.3 From 81aa17207b3c50f32be31a1be949e98c660da5f1 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 18 Aug 2010 18:22:59 +0200 Subject: ARM: mx3/mx35_3ds: add NAND flash MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mx35_3ds comes with 2 GiByte NAND flash. This adds the corresponding platform device. Signed-off-by: Marc Kleine-Budde Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx3/Kconfig | 1 + arch/arm/mach-mx3/mach-mx35_3ds.c | 8 ++++++++ 2 files changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 85beece802aa..2ae10885635a 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -140,6 +140,7 @@ config MACH_MX35_3DS bool "Support MX35PDK platform" select ARCH_MX35 select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_MXC_NAND default n help Include support for MX35PDK platform. This includes specific diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index 73149b8fe92c..b3629e735606 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -66,6 +66,12 @@ static struct platform_device mx35pdk_flash = { .num_resources = 1, }; +static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + static struct platform_device *devices[] __initdata = { &mxc_fec_device, &mx35pdk_flash, @@ -119,6 +125,8 @@ static void __init mxc_board_init(void) imx35_add_imx_uart0(&uart_pdata); mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + + imx35_add_mxc_nand(&mx35pdk_nand_board_info); } static void __init mx35pdk_timer_init(void) -- cgit v1.2.3 From 79a11b0ba4a4e2f042b143e6ac0813d6fab90626 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 18 Aug 2010 17:56:44 +0200 Subject: ARM: mx3/mx35_3ds: rename usb otg platform data variable name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the variable holding the usb otg platform data to avoid clash with usb host platform data variable. usb_pdata -> usb_otg_pdata Signed-off-by: Marc Kleine-Budde Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx3/mach-mx35_3ds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index b3629e735606..ae0f17cc8d73 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -108,7 +108,7 @@ static struct pad_desc mx35pdk_pads[] = { }; /* OTG config */ -static struct fsl_usb2_platform_data usb_pdata = { +static struct fsl_usb2_platform_data usb_otg_pdata = { .operating_mode = FSL_USB2_DR_DEVICE, .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; @@ -124,7 +124,7 @@ static void __init mxc_board_init(void) imx35_add_imx_uart0(&uart_pdata); - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); imx35_add_mxc_nand(&mx35pdk_nand_board_info); } -- cgit v1.2.3 From ab3d8b5859234d1d60b9592e9e9c5eaa9bb55678 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 18 Aug 2010 18:26:42 +0200 Subject: ARM: mx3/mx35_3ds: add usb host2 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit we still have to toggle two pins on the mc9sdz60: /* MUX3_CTR to be low for USB Host2 DP&DM */ pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 6, 0); /* CAN_PWDN to be high for USB Host2 Power&OC */ pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 1, 1); until we've a proper driver for the mx9sdz60 in linux we'll do this in barebox (a.k.a. u-boot-v2) Signed-off-by: Marc Kleine-Budde Signed-off-by: Michael Grzeschik Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx3/mach-mx35_3ds.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c index ae0f17cc8d73..1dd7baae4507 100644 --- a/arch/arm/mach-mx3/mach-mx35_3ds.c +++ b/arch/arm/mach-mx3/mach-mx35_3ds.c @@ -38,6 +38,7 @@ #include #include #include +#include #include "devices-imx35.h" #include "devices.h" @@ -105,6 +106,9 @@ static struct pad_desc mx35pdk_pads[] = { /* USBOTG */ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, + /* USBH1 */ + MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, + MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, }; /* OTG config */ @@ -113,6 +117,13 @@ static struct fsl_usb2_platform_data usb_otg_pdata = { .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; +/* USB HOST config */ +static struct mxc_usbh_platform_data usb_host_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | + MXC_EHCI_INTERNAL_PHY, +}; + /* * Board specific initialization. */ @@ -126,6 +137,8 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); + mxc_register_device(&mxc_usbh1, &usb_host_pdata); + imx35_add_mxc_nand(&mx35pdk_nand_board_info); } -- cgit v1.2.3 From f2b8901d3efe5e1603c8f6a102b2d5c851c108c6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 19 Aug 2010 14:08:04 +0200 Subject: ARM: imx: Add EPIT support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Enhanced Periodic Interrupt Timer (EPIT) is found on newer i.MX SoCs and can be used as an alternative system timer. Signed-off-by: Sascha Hauer Signed-off-by: Michael Grzeschik Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/Kconfig | 12 ++ arch/arm/plat-mxc/Makefile | 1 + arch/arm/plat-mxc/epit.c | 242 ++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/common.h | 1 + 4 files changed, 256 insertions(+) create mode 100644 arch/arm/plat-mxc/epit.c (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 6785db4179b8..95f8d614d4fc 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD data/address de-multiplexing and decode, signal level shift, interrupt control and various board functions. +config HAVE_EPIT + bool + +config MXC_USE_EPIT + bool "Use EPIT instead of GPT" + depends on HAVE_EPIT + help + Use EPIT as the system timer on systems that have it. Normally you + don't have a reason to do so as the EPIT has the same features and + uses the same clocks as the GPT. Anyway, on some systems the GPT + may be in use for other purposes. + config MXC_ULPI bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 78d405ed8616..bb3443f9751a 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o obj-$(CONFIG_MXC_ULPI) += ulpi.o +obj-$(CONFIG_MXC_USE_EPIT) += epit.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c new file mode 100644 index 000000000000..ee9582f4972e --- /dev/null +++ b/arch/arm/plat-mxc/epit.c @@ -0,0 +1,242 @@ +/* + * linux/arch/arm/plat-mxc/epit.c + * + * Copyright (C) 2010 Sascha Hauer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#define EPITCR 0x00 +#define EPITSR 0x04 +#define EPITLR 0x08 +#define EPITCMPR 0x0c +#define EPITCNR 0x10 + +#define EPITCR_EN (1 << 0) +#define EPITCR_ENMOD (1 << 1) +#define EPITCR_OCIEN (1 << 2) +#define EPITCR_RLD (1 << 3) +#define EPITCR_PRESC(x) (((x) & 0xfff) << 4) +#define EPITCR_SWR (1 << 16) +#define EPITCR_IOVW (1 << 17) +#define EPITCR_DBGEN (1 << 18) +#define EPITCR_WAITEN (1 << 19) +#define EPITCR_RES (1 << 20) +#define EPITCR_STOPEN (1 << 21) +#define EPITCR_OM_DISCON (0 << 22) +#define EPITCR_OM_TOGGLE (1 << 22) +#define EPITCR_OM_CLEAR (2 << 22) +#define EPITCR_OM_SET (3 << 22) +#define EPITCR_CLKSRC_OFF (0 << 24) +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24) +#define EPITCR_CLKSRC_REF_HIGH (1 << 24) +#define EPITCR_CLKSRC_REF_LOW (3 << 24) + +#define EPITSR_OCIF (1 << 0) + +#include +#include +#include +#include + +#include +#include +#include + +static struct clock_event_device clockevent_epit; +static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; + +static void __iomem *timer_base; + +static inline void epit_irq_disable(void) +{ + u32 val; + + val = __raw_readl(timer_base + EPITCR); + val &= ~EPITCR_OCIEN; + __raw_writel(val, timer_base + EPITCR); +} + +static inline void epit_irq_enable(void) +{ + u32 val; + + val = __raw_readl(timer_base + EPITCR); + val |= EPITCR_OCIEN; + __raw_writel(val, timer_base + EPITCR); +} + +static void epit_irq_acknowledge(void) +{ + __raw_writel(EPITSR_OCIF, timer_base + EPITSR); +} + +static cycle_t epit_read(struct clocksource *cs) +{ + return 0 - __raw_readl(timer_base + EPITCNR); +} + +static struct clocksource clocksource_epit = { + .name = "epit", + .rating = 200, + .read = epit_read, + .mask = CLOCKSOURCE_MASK(32), + .shift = 20, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static int __init epit_clocksource_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clocksource_epit.mult = clocksource_hz2mult(c, + clocksource_epit.shift); + clocksource_register(&clocksource_epit); + + return 0; +} + +/* clock event */ + +static int epit_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long tcmp; + + tcmp = __raw_readl(timer_base + EPITCNR); + + __raw_writel(tcmp - evt, timer_base + EPITCMPR); + + return 0; +} + +static void epit_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + unsigned long flags; + + /* + * The timer interrupt generation is disabled at least + * for enough time to call epit_set_next_event() + */ + local_irq_save(flags); + + /* Disable interrupt in GPT module */ + epit_irq_disable(); + + if (mode != clockevent_mode) { + /* Set event time into far-far future */ + + /* Clear pending interrupt */ + epit_irq_acknowledge(); + } + + /* Remember timer mode */ + clockevent_mode = mode; + local_irq_restore(flags); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + printk(KERN_ERR "epit_set_mode: Periodic mode is not " + "supported for i.MX EPIT\n"); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* + * Do not put overhead of interrupt enable/disable into + * epit_set_next_event(), the core has about 4 minutes + * to call epit_set_next_event() or shutdown clock after + * mode switching + */ + local_irq_save(flags); + epit_irq_enable(); + local_irq_restore(flags); + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_RESUME: + /* Left event sources disabled, no more interrupts appear */ + break; + } +} + +/* + * IRQ handler for the timer + */ +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clockevent_epit; + + epit_irq_acknowledge(); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction epit_timer_irq = { + .name = "i.MX EPIT Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = epit_timer_interrupt, +}; + +static struct clock_event_device clockevent_epit = { + .name = "epit", + .features = CLOCK_EVT_FEAT_ONESHOT, + .shift = 32, + .set_mode = epit_set_mode, + .set_next_event = epit_set_next_event, + .rating = 200, +}; + +static int __init epit_clockevent_init(struct clk *timer_clk) +{ + unsigned int c = clk_get_rate(timer_clk); + + clockevent_epit.mult = div_sc(c, NSEC_PER_SEC, + clockevent_epit.shift); + clockevent_epit.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &clockevent_epit); + clockevent_epit.min_delta_ns = + clockevent_delta2ns(0x800, &clockevent_epit); + + clockevent_epit.cpumask = cpumask_of(0); + + clockevents_register_device(&clockevent_epit); + + return 0; +} + +void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq) +{ + clk_enable(timer_clk); + + timer_base = base; + + /* + * Initialise to a known state (all timers off, and timing reset) + */ + __raw_writel(0x0, timer_base + EPITCR); + + __raw_writel(0xffffffff, timer_base + EPITLR); + __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, + timer_base + EPITCR); + + /* init and register the timer to the framework */ + epit_clocksource_init(timer_clk); + epit_clockevent_init(timer_clk); + + /* Make irqs happen */ + setup_irq(irq, &epit_timer_irq); +} diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 2941472582d2..7a1e1f89ff09 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -32,6 +32,7 @@ extern void mx31_init_irq(void); extern void mx35_init_irq(void); extern void mx51_init_irq(void); extern void mxc91231_init_irq(void); +extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); extern int mx21_clocks_init(unsigned long lref, unsigned long fref); -- cgit v1.2.3 From bd45140d98b60c8ddef8f053ad1645dc1572a15a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 19 Aug 2010 14:08:05 +0200 Subject: ARM: mx3/imx35: Add EPIT support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sascha Hauer Signed-off-by: Michael Grzeschik Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx3/Kconfig | 1 + arch/arm/mach-mx3/clock-imx35.c | 13 +++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 2ae10885635a..5cee1a5c4bd2 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -9,6 +9,7 @@ config ARCH_MX35 bool select ARCH_MXC_IOMUX_V3 select ARCH_MXC_AUDMUX_V2 + select HAVE_EPIT comment "MX3 platforms:" diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 7a62e744a8b0..f11ef990120c 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); -DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); -DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); +DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL); +DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL); DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); @@ -456,8 +456,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ect", ect_clk) _REGISTER_CLOCK(NULL, "edio", edio_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK(NULL, "epit", epit1_clk) - _REGISTER_CLOCK(NULL, "epit", epit2_clk) + _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk) + _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk) _REGISTER_CLOCK(NULL, "esai", esai_clk) _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) @@ -535,8 +535,13 @@ int __init mx35_clocks_init() __raw_writel(cgr2, CCM_BASE + CCM_CGR2); __raw_writel(cgr3, CCM_BASE + CCM_CGR3); +#ifdef CONFIG_MXC_USE_EPIT + epit_timer_init(&epit1_clk, + MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); +#else mxc_timer_init(&gpt_clk, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); +#endif return 0; } -- cgit v1.2.3 From 3efee47db7a191443b529740b35240d63ae1ad20 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Aug 2010 07:32:09 -0700 Subject: ARM: mx5/mx51_babbage: Add FEC support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested it by booting a rootfs via NFS. Signed-off-by: Fabio Estevam Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx5/board-mx51_babbage.c | 43 ++++++++++++++++++++++++++++- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 24 ++++++++++++++++ 2 files changed, 66 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 6e384d92e625..10d2f6bde172 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -35,7 +36,8 @@ #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ -#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ +#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ +#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ /* USB_CTRL_1 */ #define MX51_USB_CTRL_1_OFFSET 0x10 @@ -93,6 +95,28 @@ static struct pad_desc mx51babbage_pads[] = { /* USB HUB reset line*/ MX51_PAD_GPIO_1_7__GPIO_1_7, + + /* FEC */ + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDAT1, + MX51_PAD_EIM_CS2__FEC_RDAT2, + MX51_PAD_EIM_CS3__FEC_RDAT3, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_NANDF_RB3__FEC_RXCLK, + MX51_PAD_NANDF_RB6__FEC_RDAT0, + MX51_PAD_NANDF_RB7__FEC_TDAT0, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_CS3__FEC_MDC, + MX51_PAD_NANDF_CS4__FEC_TDAT1, + MX51_PAD_NANDF_CS5__FEC_TDAT2, + MX51_PAD_NANDF_CS6__FEC_TDAT3, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + + /* FEC PHY reset line */ + MX51_PAD_EIM_A20__GPIO_2_14, }; /* Serial ports */ @@ -171,6 +195,22 @@ static inline void babbage_usbhub_reset(void) gpio_set_value(BABBAGE_USB_HUB_RESET, 1); } +static inline void babbage_fec_reset(void) +{ + int ret; + + /* reset FEC PHY */ + ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); + return; + } + gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); + gpio_set_value(BABBAGE_FEC_PHY_RESET, 0); + msleep(1); + gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); +} + /* This function is board specific as the bit mask for the plldiv will also be different for other Freescale SoCs, thus a common bitmask is not possible and cannot get place in /plat-mxc/ehci.c.*/ @@ -250,6 +290,7 @@ static void __init mxc_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, ARRAY_SIZE(mx51babbage_pads)); mxc_init_imx_uart(); + babbage_fec_reset(); platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 21bfa46785bb..0d77be3a2374 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -46,6 +46,13 @@ typedef enum iomux_config { #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ PAD_CTL_SRE_FAST) +#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ + PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE) +#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + /* * The naming convention for the pad modes is MX51_PAD___ * If or refers to a GPIO, it is named GPIO__ @@ -106,14 +113,20 @@ typedef enum iomux_config { #define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) #define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) @@ -126,17 +139,28 @@ typedef enum iomux_config { #define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) +#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) +#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) -- cgit v1.2.3 From 556cbdbf23fb43433dba9657ad194a36be18f81b Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Sat, 14 Aug 2010 14:00:16 +0200 Subject: ARM: imx: remove #ifdefery for unmerged flexcan driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The flexcan driver was merged as e955cead. Cc: Sascha Hauer Acked-by: Marc Kleine-Budde Cc: Wolfgang Grandegger Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/devices/Makefile | 5 +---- arch/arm/plat-mxc/include/mach/devices-common.h | 12 ------------ 2 files changed, 1 insertion(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 347da5161f7e..2062ab4d094d 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,7 +1,4 @@ -ifdef CONFIG_CAN_FLEXCAN -# the ifdef can be removed once the flexcan driver has been merged -obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o -endif +obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index c5f68c587309..4a170a8da26c 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -14,23 +14,11 @@ struct platform_device *imx_add_platform_device(const char *name, int id, const struct resource *res, unsigned int num_resources, const void *data, size_t size_data); -#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE) #include struct platform_device *__init imx_add_flexcan(int id, resource_size_t iobase, resource_size_t iosize, resource_size_t irq, const struct flexcan_platform_data *pdata); -#else -/* the ifdef can be removed once the flexcan driver has been merged */ -struct flexcan_platform_data; -static inline struct platform_device *__init imx_add_flexcan(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, - const struct flexcan_platform_data *pdata) -{ - return NULL; -} -#endif #include struct platform_device *__init imx_add_imx_i2c(int id, -- cgit v1.2.3 From a060656240af125b22b1c011944377ff4216ac3e Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 13 Aug 2010 17:34:05 +0200 Subject: ARM: imx: ehci: use void __iomem * to hold i/o addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm/plat-mxc/ehci.c: In function 'mxc_initialize_usb_hw': arch/arm/plat-mxc/ehci.c:260: warning: assignment makes integer from pointer without a cast arch/arm/plat-mxc/ehci.c:263: warning: assignment makes integer from pointer without a cast arch/arm/plat-mxc/ehci.c:270: warning: assignment makes integer from pointer without a cast Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/ehci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 35a064ff02ba..9915607683de 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags) #ifdef CONFIG_ARCH_MX51 if (cpu_is_mx51()) { void __iomem *usb_base; - u32 usbotg_base; - u32 usbother_base; + void __iomem *usbotg_base; + void __iomem *usbother_base; int ret = 0; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); -- cgit v1.2.3 From e7a895bf64e9360499d04b80fa33b0ad93546d44 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 19 Aug 2010 11:37:31 +0200 Subject: ARM: mx5/mx51_babbage: fix compiler warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Sascha Hauer Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx5/board-mx51_babbage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 10d2f6bde172..3ef1214cb0d4 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -218,7 +218,7 @@ static int initialize_otg_port(struct platform_device *pdev) { u32 v; void __iomem *usb_base; - u32 usbother_base; + void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; @@ -236,7 +236,7 @@ static int initialize_usbh1_port(struct platform_device *pdev) { u32 v; void __iomem *usb_base; - u32 usbother_base; + void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; -- cgit v1.2.3 From e16ddb3ad2b42d7c906748dc3bc3f393ddb94c67 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 24 Aug 2010 12:33:23 +0200 Subject: ARM: mx5/mx51_babbage: don't use PHYS_OFFSET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/mach-mx5/board-mx51_babbage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 3ef1214cb0d4..caa8f680649e 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -324,7 +324,7 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") /* Maintainer: Amit Kucheria */ .phys_io = MX51_AIPS1_BASE_ADDR, .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX51_PHYS_OFFSET + 0x100, .map_io = mx51_map_io, .init_irq = mx51_init_irq, .init_machine = mxc_board_init, -- cgit v1.2.3 From 0ac15c884eceaf5b0917d4d28d86ff1bb4845d37 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 21 Sep 2010 12:35:41 +0200 Subject: ARM: mx27_defconfig: enable switches used in mx27 code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - enable all mx27 machines (MACH_CPUIMX27, MACH_IMX27_VISSTRIM_M10, MACH_PCA100, MACH_MXT_TD60) including optional features for CPUIMX27 - eukrea_mbimx27-baseboard.c uses TOUCHSCREEN_ADS7846 - mach-cpuimx27.c uses SERIAL_8250 - several machines make use of SPI_IMX (selects SPI_BITBANG) - drop VGA_CONSOLE as this isn't selectable anymore since fb78b51cb11e - several machines make use of USB_ULPI (depends on USB, but don't enable USB_DEVICE_CLASS as it's deprecated) Signed-off-by: Uwe Kleine-König --- arch/arm/configs/mx27_defconfig | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig index b2038b0e266f..813cfb366c18 100644 --- a/arch/arm/configs/mx27_defconfig +++ b/arch/arm/configs/mx27_defconfig @@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y CONFIG_MACH_MX27=y CONFIG_MACH_MX27ADS=y CONFIG_MACH_PCM038=y +CONFIG_MACH_CPUIMX27=y +CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y +CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y CONFIG_MACH_MX27_3DS=y +CONFIG_MACH_IMX27_VISSTRIM_M10=y CONFIG_MACH_IMX27LITE=y +CONFIG_MACH_PCA100=y +CONFIG_MACH_MXT_TD60=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y CONFIG_NO_HZ=y @@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_SERIO is not set +CONFIG_SERIAL_8250=m CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y # CONFIG_LEGACY_PTYS is not set @@ -85,19 +93,20 @@ CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_IMX=y CONFIG_SPI=y -CONFIG_SPI_BITBANG=y +CONFIG_SPI_IMX=y CONFIG_W1=y CONFIG_W1_MASTER_MXC=y CONFIG_W1_SLAVE_THERM=y # CONFIG_HWMON is not set CONFIG_FB=y CONFIG_FB_IMX=y -# CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FONTS=y CONFIG_FONT_8x8=y # CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set +CONFIG_USB=m +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_ULPI=y CONFIG_MMC=y CONFIG_MMC_MXC=y CONFIG_RTC_CLASS=y -- cgit v1.2.3 From 801561cdda3027a0d1e0e15a3772e5dab5af7c65 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 13 Aug 2010 12:38:56 +0200 Subject: ARM: mx3_defconfig: add new machine MACH_EUKREA_CPUIMX35 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Furthermore INOTIFY is gone since 2dfc1ca (inotify: remove inotify in kernel interface) Signed-off-by: Uwe Kleine-König --- arch/arm/configs/mx3_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index 161f907b611f..f0c339fd5d21 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y CONFIG_MACH_ARMADILLO5X0=y CONFIG_MACH_MX35_3DS=y CONFIG_MACH_KZM_ARM11_01=y +CONFIG_MACH_EUKREA_CPUIMX35=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y CONFIG_NO_HZ=y @@ -108,7 +109,6 @@ CONFIG_MMC=y CONFIG_MMC_MXC=y CONFIG_DMADEVICES=y # CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y CONFIG_TMPFS=y CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y -- cgit v1.2.3 From ea9a9b2ba239792be57d8601f57a4971958ebad5 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 11 Aug 2010 07:32:33 +0200 Subject: ARM: remove mx31pdk_defconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This machine is enabled in mx3_defconfig and so mx31pdk_defconfig isn't really useful. Signed-off-by: Uwe Kleine-König --- arch/arm/configs/mx31pdk_defconfig | 44 -------------------------------------- 1 file changed, 44 deletions(-) delete mode 100644 arch/arm/configs/mx31pdk_defconfig (limited to 'arch/arm') diff --git a/arch/arm/configs/mx31pdk_defconfig b/arch/arm/configs/mx31pdk_defconfig deleted file mode 100644 index 2d29329749e4..000000000000 --- a/arch/arm/configs/mx31pdk_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_COMPAT_BRK is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -CONFIG_ARCH_MXC=y -# CONFIG_MACH_MX31ADS is not set -CONFIG_MACH_MX31_3DS=y -CONFIG_AEABI=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_LRO is not set -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FIRMWARE_IN_KERNEL is not set -# CONFIG_BLK_DEV is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_HID_SUPPORT is not set -# CONFIG_USB_SUPPORT is not set -# CONFIG_DNOTIFY is not set -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRC32 is not set -- cgit v1.2.3 From 6470310865dc8d7ed78f0df8f4c7f7e39c7bab99 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 21 Sep 2010 10:46:15 +0200 Subject: ARM: mx51_defconfig: add new boards MACH_MX51_3DS and MACH_EUKREA_CPUIMX51 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Further remove FIXED_PHY as it breaks the ethernet. VGA_CONSOLE isn't selectable anymore since fb78b51cb11e. EXT3_DEFAULTS_TO_ORDERED defaults to y since aa32a796389b. INOTIFY is gone since 2dfc1cae4c42. CONFIG_DETECT_SOFTLOCKUP is gone since e16bb1d7fe07. Enable TMPFS for udev. KEYS is selected by NFS_USE_KERNEL_DNS Signed-off-by: Uwe Kleine-König --- arch/arm/configs/mx51_defconfig | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index a665ecbbe2bc..163cfee7644c 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig @@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_ARCH_MXC=y CONFIG_ARCH_MX5=y CONFIG_MACH_MX51_BABBAGE=y +CONFIG_MACH_MX51_3DS=y +CONFIG_MACH_EUKREA_CPUIMX51=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT_VOLUNTARY=y @@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y CONFIG_NATIONAL_PHY=y CONFIG_STE10XP=y CONFIG_LSI_ET1011C_PHY=y -CONFIG_FIXED_PHY=y CONFIG_MDIO_BITBANG=y CONFIG_MDIO_GPIO=y CONFIG_NET_ETHERNET=y @@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m CONFIG_I2C_ALGOPCA=m CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set # CONFIG_HID_SUPPORT is not set CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y -CONFIG_EXT3_DEFAULTS_TO_ORDERED=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -CONFIG_INOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set @@ -136,6 +134,7 @@ CONFIG_ZISOFS=y CONFIG_UDF_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=y +CONFIG_TMPFS=y CONFIG_CONFIGFS_FS=m CONFIG_NFS_FS=y CONFIG_NFS_V3=y @@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set @@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_ARM_UNWIND is not set CONFIG_DEBUG_LL=y CONFIG_EARLY_PRINTK=y -CONFIG_KEYS=y CONFIG_SECURITYFS=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y -- cgit v1.2.3 From 5a2db4e3865868c3bf230435fb312524c0e10bd4 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 3 Aug 2010 16:03:26 +0200 Subject: ARM: mx51: clean up mx51 header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the header more look like the other ones, i.e. - sort #defines by value - use lowercase hex constants - use a consistently named header guard Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx51.h | 608 +++++++++++++++++----------------- 1 file changed, 300 insertions(+), 308 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 5aad344d5651..92b39f7256e9 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -1,5 +1,5 @@ -#ifndef __ASM_ARCH_MXC_MX51_H__ -#define __ASM_ARCH_MXC_MX51_H__ +#ifndef __MACH_MX51_H__ +#define __MACH_MX51_H__ /* * MX51 memory map: @@ -7,24 +7,23 @@ * * Virt Phys Size What * --------------------------------------------------------------------------- - * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) + * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM) * 30000000 256M GPU * 40000000 512M IPU - * FA200000 60000000 1M DEBUG - * FB100000 70000000 1M SPBA 0 - * FB000000 73F00000 1M AIPS 1 - * FB200000 83F00000 1M AIPS 2 - * 8FFFC000 16K TZIC (interrupt controller) + * fa200000 60000000 1M DEBUG + * fb100000 70000000 1M SPBA 0 + * fb000000 73f00000 1M AIPS 1 + * fb200000 83f00000 1M AIPS 2 + * 8fffc000 16K TZIC (interrupt controller) * 90000000 256M CSD0 SDRAM/DDR - * A0000000 256M CSD1 SDRAM/DDR - * B0000000 128M CS0 Flash - * B8000000 128M CS1 Flash - * C0000000 128M CS2 Flash - * C8000000 64M CS3 Flash - * CC000000 32M CS4 SRAM - * CE000000 32M CS5 SRAM - * CFFF0000 64K NFC (NAND Flash AXI) - * + * a0000000 256M CSD1 SDRAM/DDR + * b0000000 128M CS0 Flash + * b8000000 128M CS1 Flash + * c0000000 128M CS2 Flash + * c8000000 64M CS3 Flash + * cc000000 32M CS4 SRAM + * ce000000 32M CS5 SRAM + * cfff0000 64K NFC (NAND Flash AXI) */ /* @@ -36,65 +35,140 @@ /* * IRAM */ -#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ -#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 +#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ +#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000 #define MX51_IRAM_PARTITIONS 16 -#define MX51_IRAM_PARTITIONS_TO1 12 #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ +#define MX51_GPU_BASE_ADDR 0x20000000 +#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 + +#define MX51_DEBUG_BASE_ADDR 0x60000000 +#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000 +#define MX51_DEBUG_SIZE SZ_1M + +#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) +#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000) +#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000) +#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000) +#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000) +#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000) +#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000) +#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000) + /* - * NFC + * SPBA global module enabled #0 */ -#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ -#define MX51_NFC_AXI_SIZE SZ_64K +#define MX51_SPBA0_BASE_ADDR 0x70000000 +#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000 +#define MX51_SPBA0_SIZE SZ_1M + +#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) +#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) +#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) +#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) +#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) /* - * Graphics Memory of GPU + * AIPS 1 */ -#define MX51_GPU_BASE_ADDR 0x20000000 -#define MX51_GPU2D_BASE_ADDR 0xD0000000 +#define MX51_AIPS1_BASE_ADDR 0x73f00000 +#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000 +#define MX51_AIPS1_SIZE SZ_1M + +#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) +#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) +#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) +#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) +#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) +#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) +#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) +#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) +#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) +#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) +#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) +#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) +#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) +#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) +#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) +#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) +#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) +#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) +#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) +#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) -#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000 -#define MX51_TZIC_BASE_ADDR 0xE0000000 +/* + * AIPS 2 + */ +#define MX51_AIPS2_BASE_ADDR 0x83f00000 +#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000 +#define MX51_AIPS2_SIZE SZ_1M -#define MX51_DEBUG_BASE_ADDR 0x60000000 -#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 -#define MX51_DEBUG_SIZE SZ_1M -#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000) -#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) -#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) -#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) -#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) -#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) -#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) -#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) +#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) +#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) +#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) +#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) +#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) +#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) +#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) +#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) +#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) +#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) +#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) +#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) +#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) +#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) +#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) +#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) +#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) +#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) +#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) +#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) +#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) +#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) +#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) +#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) +#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) +#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) +#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) +#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) +#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) +#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) +#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) +#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) + +#define MX51_CSD0_BASE_ADDR 0x90000000 +#define MX51_CSD1_BASE_ADDR 0xa0000000 +#define MX51_CS0_BASE_ADDR 0xb0000000 +#define MX51_CS1_BASE_ADDR 0xb8000000 +#define MX51_CS2_BASE_ADDR 0xc0000000 +#define MX51_CS3_BASE_ADDR 0xc8000000 +#define MX51_CS4_BASE_ADDR 0xcc000000 +#define MX51_CS5_BASE_ADDR 0xce000000 /* - * SPBA global module enabled #0 + * NFC */ -#define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 -#define MX51_SPBA0_SIZE SZ_1M +#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ +#define MX51_NFC_AXI_SIZE SZ_64K -#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) -#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) -#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) -#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) -#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) -#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) -#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) -#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) -#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) -#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) -#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) -#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) +#define MX51_GPU2D_BASE_ADDR 0xd0000000 +#define MX51_TZIC_BASE_ADDR 0xe0000000 /* * defines for SPBA modules */ #define MX51_SPBA_SDHC1 0x04 #define MX51_SPBA_SDHC2 0x08 -#define MX51_SPBA_UART3 0x0C +#define MX51_SPBA_UART3 0x0c #define MX51_SPBA_CSPI1 0x10 #define MX51_SPBA_SSI2 0x14 #define MX51_SPBA_SDHC3 0x20 @@ -103,35 +177,7 @@ #define MX51_SPBA_ATA 0x30 #define MX51_SPBA_SLIM 0x34 #define MX51_SPBA_HSI2C 0x38 -#define MX51_SPBA_CTRL 0x3C - -/* - * AIPS 1 - */ -#define MX51_AIPS1_BASE_ADDR 0x73F00000 -#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000 -#define MX51_AIPS1_SIZE SZ_1M - -#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000) -#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000) -#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000) -#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000) -#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000) -#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000) -#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000) -#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000) -#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000) -#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000) -#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000) -#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000) -#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000) -#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000) -#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000) -#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000) -#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000) -#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000) -#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000) -#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000) +#define MX51_SPBA_CTRL 0x3c /* * Defines for modules using static and dynamic DMA channels @@ -164,60 +210,6 @@ #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL -/* - * AIPS 2 - */ -#define MX51_AIPS2_BASE_ADDR 0x83F00000 -#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000 -#define MX51_AIPS2_SIZE SZ_1M - -#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000) -#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000) -#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000) -#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000) -#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000) -#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000) -#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000) -#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000) -#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000) -#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000) -#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000) -#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000) -#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000) -#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000) -#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000) -#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000) -#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000) -#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000) -#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000) -#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000) -#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000) -#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000) -#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000) -#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00) -#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000) -#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000) -#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000) -#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000) -#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000) -#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000) -#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000) -#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) - -/* - * Memory regions and CS - */ -#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 -#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 -#define MX51_CSD0_BASE_ADDR 0x90000000 -#define MX51_CSD1_BASE_ADDR 0xA0000000 -#define MX51_CS0_BASE_ADDR 0xB0000000 -#define MX51_CS1_BASE_ADDR 0xB8000000 -#define MX51_CS2_BASE_ADDR 0xC0000000 -#define MX51_CS3_BASE_ADDR 0xC8000000 -#define MX51_CS4_BASE_ADDR 0xCC000000 -#define MX51_CS5_BASE_ADDR 0xCE000000 - /* Does given address belongs to the specified memory region? */ #define ADDRESS_IN_REGION(addr, start, size) \ (((addr) >= (start)) && ((addr) < (start)+(size))) @@ -230,7 +222,7 @@ * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF + * it returns 0xdeadbeef */ #define MX51_IO_ADDRESS(x) \ @@ -240,7 +232,7 @@ MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ - 0xDEADBEEF) + 0xdeadbeef) /* * define the address mapping macros: in physical address order @@ -265,181 +257,181 @@ /* * DMA request assignments */ -#define MX51_DMA_REQ_SSI3_TX1 47 -#define MX51_DMA_REQ_SSI3_RX1 46 -#define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_UART3_TX 44 -#define MX51_DMA_REQ_UART3_RX 43 -#define MX51_DMA_REQ_SLIM_B_TX 42 -#define MX51_DMA_REQ_SDHC4 41 -#define MX51_DMA_REQ_SDHC3 40 -#define MX51_DMA_REQ_CSPI_TX 39 -#define MX51_DMA_REQ_CSPI_RX 38 -#define MX51_DMA_REQ_SSI3_TX2 37 -#define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_RX2 35 -#define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_CTI2_1 33 -#define MX51_DMA_REQ_EMI_WR 32 -#define MX51_DMA_REQ_CTI2_0 31 -#define MX51_DMA_REQ_EMI_RD 30 -#define MX51_DMA_REQ_SSI1_TX1 29 -#define MX51_DMA_REQ_SSI1_RX1 28 -#define MX51_DMA_REQ_SSI1_TX2 27 -#define MX51_DMA_REQ_SSI1_RX2 26 -#define MX51_DMA_REQ_SSI2_TX1 25 -#define MX51_DMA_REQ_SSI2_RX1 24 -#define MX51_DMA_REQ_SSI2_TX2 23 -#define MX51_DMA_REQ_SSI2_RX2 22 -#define MX51_DMA_REQ_SDHC2 21 -#define MX51_DMA_REQ_SDHC1 20 -#define MX51_DMA_REQ_UART1_TX 19 -#define MX51_DMA_REQ_UART1_RX 18 -#define MX51_DMA_REQ_UART2_TX 17 -#define MX51_DMA_REQ_UART2_RX 16 -#define MX51_DMA_REQ_GPU 15 -#define MX51_DMA_REQ_EXTREQ1 14 -#define MX51_DMA_REQ_FIRI_TX 13 -#define MX51_DMA_REQ_FIRI_RX 12 -#define MX51_DMA_REQ_HS_I2C_RX 11 -#define MX51_DMA_REQ_HS_I2C_TX 10 -#define MX51_DMA_REQ_CSPI2_TX 9 -#define MX51_DMA_REQ_CSPI2_RX 8 -#define MX51_DMA_REQ_CSPI1_TX 7 -#define MX51_DMA_REQ_CSPI1_RX 6 -#define MX51_DMA_REQ_SLIM_B 5 -#define MX51_DMA_REQ_ATA_TX_END 4 -#define MX51_DMA_REQ_ATA_TX 3 -#define MX51_DMA_REQ_ATA_RX 2 -#define MX51_DMA_REQ_GPC 1 -#define MX51_DMA_REQ_VPU 0 +#define MX51_DMA_REQ_VPU 0 +#define MX51_DMA_REQ_GPC 1 +#define MX51_DMA_REQ_ATA_RX 2 +#define MX51_DMA_REQ_ATA_TX 3 +#define MX51_DMA_REQ_ATA_TX_END 4 +#define MX51_DMA_REQ_SLIM_B 5 +#define MX51_DMA_REQ_CSPI1_RX 6 +#define MX51_DMA_REQ_CSPI1_TX 7 +#define MX51_DMA_REQ_CSPI2_RX 8 +#define MX51_DMA_REQ_CSPI2_TX 9 +#define MX51_DMA_REQ_HS_I2C_TX 10 +#define MX51_DMA_REQ_HS_I2C_RX 11 +#define MX51_DMA_REQ_FIRI_RX 12 +#define MX51_DMA_REQ_FIRI_TX 13 +#define MX51_DMA_REQ_EXTREQ1 14 +#define MX51_DMA_REQ_GPU 15 +#define MX51_DMA_REQ_UART2_RX 16 +#define MX51_DMA_REQ_UART2_TX 17 +#define MX51_DMA_REQ_UART1_RX 18 +#define MX51_DMA_REQ_UART1_TX 19 +#define MX51_DMA_REQ_SDHC1 20 +#define MX51_DMA_REQ_SDHC2 21 +#define MX51_DMA_REQ_SSI2_RX2 22 +#define MX51_DMA_REQ_SSI2_TX2 23 +#define MX51_DMA_REQ_SSI2_RX1 24 +#define MX51_DMA_REQ_SSI2_TX1 25 +#define MX51_DMA_REQ_SSI1_RX2 26 +#define MX51_DMA_REQ_SSI1_TX2 27 +#define MX51_DMA_REQ_SSI1_RX1 28 +#define MX51_DMA_REQ_SSI1_TX1 29 +#define MX51_DMA_REQ_EMI_RD 30 +#define MX51_DMA_REQ_CTI2_0 31 +#define MX51_DMA_REQ_EMI_WR 32 +#define MX51_DMA_REQ_CTI2_1 33 +#define MX51_DMA_REQ_EPIT2 34 +#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_IPU 36 +#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_CSPI_RX 38 +#define MX51_DMA_REQ_CSPI_TX 39 +#define MX51_DMA_REQ_SDHC3 40 +#define MX51_DMA_REQ_SDHC4 41 +#define MX51_DMA_REQ_SLIM_B_TX 42 +#define MX51_DMA_REQ_UART3_RX 43 +#define MX51_DMA_REQ_UART3_TX 44 +#define MX51_DMA_REQ_SPDIF 45 +#define MX51_DMA_REQ_SSI3_RX1 46 +#define MX51_DMA_REQ_SSI3_TX1 47 /* * Interrupt numbers */ -#define MX51_MXC_INT_BASE 0 -#define MX51_MXC_INT_RESV0 0 -#define MX51_MXC_INT_MMC_SDHC1 1 -#define MX51_MXC_INT_MMC_SDHC2 2 -#define MX51_MXC_INT_MMC_SDHC3 3 -#define MX51_MXC_INT_MMC_SDHC4 4 -#define MX51_MXC_INT_RESV5 5 -#define MX51_MXC_INT_SDMA 6 -#define MX51_MXC_INT_IOMUX 7 -#define MX51_MXC_INT_NFC 8 -#define MX51_MXC_INT_VPU 9 -#define MX51_MXC_INT_IPU_ERR 10 -#define MX51_MXC_INT_IPU_SYN 11 -#define MX51_MXC_INT_GPU 12 -#define MX51_MXC_INT_RESV13 13 -#define MX51_MXC_INT_USB_H1 14 -#define MX51_MXC_INT_EMI 15 -#define MX51_MXC_INT_USB_H2 16 -#define MX51_MXC_INT_USB_H3 17 -#define MX51_MXC_INT_USB_OTG 18 -#define MX51_MXC_INT_SAHARA_H0 19 -#define MX51_MXC_INT_SAHARA_H1 20 -#define MX51_MXC_INT_SCC_SMN 21 -#define MX51_MXC_INT_SCC_STZ 22 -#define MX51_MXC_INT_SCC_SCM 23 -#define MX51_MXC_INT_SRTC_NTZ 24 -#define MX51_MXC_INT_SRTC_TZ 25 -#define MX51_MXC_INT_RTIC 26 -#define MX51_MXC_INT_CSU 27 -#define MX51_MXC_INT_SLIM_B 28 -#define MX51_MXC_INT_SSI1 29 -#define MX51_MXC_INT_SSI2 30 -#define MX51_MXC_INT_UART1 31 -#define MX51_MXC_INT_UART2 32 -#define MX51_MXC_INT_UART3 33 -#define MX51_MXC_INT_RESV34 34 -#define MX51_MXC_INT_RESV35 35 -#define MX51_MXC_INT_CSPI1 36 -#define MX51_MXC_INT_CSPI2 37 -#define MX51_MXC_INT_CSPI 38 -#define MX51_MXC_INT_GPT 39 -#define MX51_MXC_INT_EPIT1 40 -#define MX51_MXC_INT_EPIT2 41 -#define MX51_MXC_INT_GPIO1_INT7 42 -#define MX51_MXC_INT_GPIO1_INT6 43 -#define MX51_MXC_INT_GPIO1_INT5 44 -#define MX51_MXC_INT_GPIO1_INT4 45 -#define MX51_MXC_INT_GPIO1_INT3 46 -#define MX51_MXC_INT_GPIO1_INT2 47 -#define MX51_MXC_INT_GPIO1_INT1 48 -#define MX51_MXC_INT_GPIO1_INT0 49 -#define MX51_MXC_INT_GPIO1_LOW 50 -#define MX51_MXC_INT_GPIO1_HIGH 51 -#define MX51_MXC_INT_GPIO2_LOW 52 -#define MX51_MXC_INT_GPIO2_HIGH 53 -#define MX51_MXC_INT_GPIO3_LOW 54 -#define MX51_MXC_INT_GPIO3_HIGH 55 -#define MX51_MXC_INT_GPIO4_LOW 56 -#define MX51_MXC_INT_GPIO4_HIGH 57 -#define MX51_MXC_INT_WDOG1 58 -#define MX51_MXC_INT_WDOG2 59 -#define MX51_MXC_INT_KPP 60 -#define MX51_MXC_INT_PWM1 61 -#define MX51_MXC_INT_I2C1 62 -#define MX51_MXC_INT_I2C2 63 -#define MX51_MXC_INT_HS_I2C 64 -#define MX51_MXC_INT_RESV65 65 -#define MX51_MXC_INT_RESV66 66 -#define MX51_MXC_INT_SIM_IPB 67 -#define MX51_MXC_INT_SIM_DAT 68 -#define MX51_MXC_INT_IIM 69 -#define MX51_MXC_INT_ATA 70 -#define MX51_MXC_INT_CCM1 71 -#define MX51_MXC_INT_CCM2 72 -#define MX51_MXC_INT_GPC1 73 -#define MX51_MXC_INT_GPC2 74 -#define MX51_MXC_INT_SRC 75 -#define MX51_MXC_INT_NM 76 -#define MX51_MXC_INT_PMU 77 -#define MX51_MXC_INT_CTI_IRQ 78 -#define MX51_MXC_INT_CTI1_TG0 79 -#define MX51_MXC_INT_CTI1_TG1 80 -#define MX51_MXC_INT_MCG_ERR 81 -#define MX51_MXC_INT_MCG_TMR 82 -#define MX51_MXC_INT_MCG_FUNC 83 -#define MX51_MXC_INT_GPU2_IRQ 84 -#define MX51_MXC_INT_GPU2_BUSY 85 -#define MX51_MXC_INT_RESV86 86 -#define MX51_MXC_INT_FEC 87 -#define MX51_MXC_INT_OWIRE 88 -#define MX51_MXC_INT_CTI1_TG2 89 -#define MX51_MXC_INT_SJC 90 -#define MX51_MXC_INT_SPDIF 91 -#define MX51_MXC_INT_TVE 92 -#define MX51_MXC_INT_FIRI 93 -#define MX51_MXC_INT_PWM2 94 -#define MX51_MXC_INT_SLIM_EXP 95 -#define MX51_MXC_INT_SSI3 96 -#define MX51_MXC_INT_EMI_BOOT 97 -#define MX51_MXC_INT_CTI1_TG3 98 -#define MX51_MXC_INT_SMC_RX 99 -#define MX51_MXC_INT_VPU_IDLE 100 -#define MX51_MXC_INT_EMI_NFC 101 -#define MX51_MXC_INT_GPU_IDLE 102 +#define MX51_MXC_INT_BASE 0 +#define MX51_MXC_INT_RESV0 0 +#define MX51_MXC_INT_MMC_SDHC1 1 +#define MX51_MXC_INT_MMC_SDHC2 2 +#define MX51_MXC_INT_MMC_SDHC3 3 +#define MX51_MXC_INT_MMC_SDHC4 4 +#define MX51_MXC_INT_RESV5 5 +#define MX51_MXC_INT_SDMA 6 +#define MX51_MXC_INT_IOMUX 7 +#define MX51_MXC_INT_NFC 8 +#define MX51_MXC_INT_VPU 9 +#define MX51_MXC_INT_IPU_ERR 10 +#define MX51_MXC_INT_IPU_SYN 11 +#define MX51_MXC_INT_GPU 12 +#define MX51_MXC_INT_RESV13 13 +#define MX51_MXC_INT_USB_H1 14 +#define MX51_MXC_INT_EMI 15 +#define MX51_MXC_INT_USB_H2 16 +#define MX51_MXC_INT_USB_H3 17 +#define MX51_MXC_INT_USB_OTG 18 +#define MX51_MXC_INT_SAHARA_H0 19 +#define MX51_MXC_INT_SAHARA_H1 20 +#define MX51_MXC_INT_SCC_SMN 21 +#define MX51_MXC_INT_SCC_STZ 22 +#define MX51_MXC_INT_SCC_SCM 23 +#define MX51_MXC_INT_SRTC_NTZ 24 +#define MX51_MXC_INT_SRTC_TZ 25 +#define MX51_MXC_INT_RTIC 26 +#define MX51_MXC_INT_CSU 27 +#define MX51_MXC_INT_SLIM_B 28 +#define MX51_MXC_INT_SSI1 29 +#define MX51_MXC_INT_SSI2 30 +#define MX51_MXC_INT_UART1 31 +#define MX51_MXC_INT_UART2 32 +#define MX51_MXC_INT_UART3 33 +#define MX51_MXC_INT_RESV34 34 +#define MX51_MXC_INT_RESV35 35 +#define MX51_MXC_INT_CSPI1 36 +#define MX51_MXC_INT_CSPI2 37 +#define MX51_MXC_INT_CSPI 38 +#define MX51_MXC_INT_GPT 39 +#define MX51_MXC_INT_EPIT1 40 +#define MX51_MXC_INT_EPIT2 41 +#define MX51_MXC_INT_GPIO1_INT7 42 +#define MX51_MXC_INT_GPIO1_INT6 43 +#define MX51_MXC_INT_GPIO1_INT5 44 +#define MX51_MXC_INT_GPIO1_INT4 45 +#define MX51_MXC_INT_GPIO1_INT3 46 +#define MX51_MXC_INT_GPIO1_INT2 47 +#define MX51_MXC_INT_GPIO1_INT1 48 +#define MX51_MXC_INT_GPIO1_INT0 49 +#define MX51_MXC_INT_GPIO1_LOW 50 +#define MX51_MXC_INT_GPIO1_HIGH 51 +#define MX51_MXC_INT_GPIO2_LOW 52 +#define MX51_MXC_INT_GPIO2_HIGH 53 +#define MX51_MXC_INT_GPIO3_LOW 54 +#define MX51_MXC_INT_GPIO3_HIGH 55 +#define MX51_MXC_INT_GPIO4_LOW 56 +#define MX51_MXC_INT_GPIO4_HIGH 57 +#define MX51_MXC_INT_WDOG1 58 +#define MX51_MXC_INT_WDOG2 59 +#define MX51_MXC_INT_KPP 60 +#define MX51_MXC_INT_PWM1 61 +#define MX51_MXC_INT_I2C1 62 +#define MX51_MXC_INT_I2C2 63 +#define MX51_MXC_INT_HS_I2C 64 +#define MX51_MXC_INT_RESV65 65 +#define MX51_MXC_INT_RESV66 66 +#define MX51_MXC_INT_SIM_IPB 67 +#define MX51_MXC_INT_SIM_DAT 68 +#define MX51_MXC_INT_IIM 69 +#define MX51_MXC_INT_ATA 70 +#define MX51_MXC_INT_CCM1 71 +#define MX51_MXC_INT_CCM2 72 +#define MX51_MXC_INT_GPC1 73 +#define MX51_MXC_INT_GPC2 74 +#define MX51_MXC_INT_SRC 75 +#define MX51_MXC_INT_NM 76 +#define MX51_MXC_INT_PMU 77 +#define MX51_MXC_INT_CTI_IRQ 78 +#define MX51_MXC_INT_CTI1_TG0 79 +#define MX51_MXC_INT_CTI1_TG1 80 +#define MX51_MXC_INT_MCG_ERR 81 +#define MX51_MXC_INT_MCG_TMR 82 +#define MX51_MXC_INT_MCG_FUNC 83 +#define MX51_MXC_INT_GPU2_IRQ 84 +#define MX51_MXC_INT_GPU2_BUSY 85 +#define MX51_MXC_INT_RESV86 86 +#define MX51_MXC_INT_FEC 87 +#define MX51_MXC_INT_OWIRE 88 +#define MX51_MXC_INT_CTI1_TG2 89 +#define MX51_MXC_INT_SJC 90 +#define MX51_MXC_INT_SPDIF 91 +#define MX51_MXC_INT_TVE 92 +#define MX51_MXC_INT_FIRI 93 +#define MX51_MXC_INT_PWM2 94 +#define MX51_MXC_INT_SLIM_EXP 95 +#define MX51_MXC_INT_SSI3 96 +#define MX51_MXC_INT_EMI_BOOT 97 +#define MX51_MXC_INT_CTI1_TG3 98 +#define MX51_MXC_INT_SMC_RX 99 +#define MX51_MXC_INT_VPU_IDLE 100 +#define MX51_MXC_INT_EMI_NFC 101 +#define MX51_MXC_INT_GPU_IDLE 102 /* silicon revisions specific to i.MX51 */ -#define MX51_CHIP_REV_1_0 0x10 -#define MX51_CHIP_REV_1_1 0x11 -#define MX51_CHIP_REV_1_2 0x12 -#define MX51_CHIP_REV_1_3 0x13 -#define MX51_CHIP_REV_2_0 0x20 -#define MX51_CHIP_REV_2_1 0x21 -#define MX51_CHIP_REV_2_2 0x22 -#define MX51_CHIP_REV_2_3 0x23 -#define MX51_CHIP_REV_3_0 0x30 -#define MX51_CHIP_REV_3_1 0x31 -#define MX51_CHIP_REV_3_2 0x32 - -/* Mandatory defines used globally */ +#define MX51_CHIP_REV_1_0 0x10 +#define MX51_CHIP_REV_1_1 0x11 +#define MX51_CHIP_REV_1_2 0x12 +#define MX51_CHIP_REV_1_3 0x13 +#define MX51_CHIP_REV_2_0 0x20 +#define MX51_CHIP_REV_2_1 0x21 +#define MX51_CHIP_REV_2_2 0x22 +#define MX51_CHIP_REV_2_3 0x23 +#define MX51_CHIP_REV_3_0 0x30 +#define MX51_CHIP_REV_3_1 0x31 +#define MX51_CHIP_REV_3_2 0x32 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) - extern int mx51_revision(void); #endif -#endif /* __ASM_ARCH_MXC_MX51_H__ */ +/* tape-out 1 defines */ +#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000 + +#endif /* ifndef __MACH_MX51_H__ */ -- cgit v1.2.3 From 68b5e858dde8dcb0413b7c1d699c1056ecc0934d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 3 Aug 2010 16:15:29 +0200 Subject: ARM: mx51: fix naming of spi related defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The names used now match the processor's reference manual. Also remove MXC from the interrupt defines to match the other imx platforms. Acked-by: Wolfram Sang Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx51.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 92b39f7256e9..d0fda396adf2 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -67,7 +67,7 @@ #define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) #define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) -#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) +#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) #define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) #define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) @@ -121,12 +121,12 @@ #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) -#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) +#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) #define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) #define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) #define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) #define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) -#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) +#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) #define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) #define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) #define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) @@ -346,9 +346,9 @@ #define MX51_MXC_INT_UART3 33 #define MX51_MXC_INT_RESV34 34 #define MX51_MXC_INT_RESV35 35 -#define MX51_MXC_INT_CSPI1 36 -#define MX51_MXC_INT_CSPI2 37 -#define MX51_MXC_INT_CSPI 38 +#define MX51_INT_ECSPI1 36 +#define MX51_INT_ECSPI2 37 +#define MX51_INT_CSPI 38 #define MX51_MXC_INT_GPT 39 #define MX51_MXC_INT_EPIT1 40 #define MX51_MXC_INT_EPIT2 41 -- cgit v1.2.3 From a8a05b855291defb1d97a1c3681480e4ca330254 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 3 Aug 2010 16:09:35 +0200 Subject: ARM: mx51: use IMX_IO_ADDRESS to define MX51_IO_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx51.h | 53 ++++++++--------------------------- 1 file changed, 11 insertions(+), 42 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index d0fda396adf2..f6026506c5ef 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -163,6 +163,17 @@ #define MX51_GPU2D_BASE_ADDR 0xd0000000 #define MX51_TZIC_BASE_ADDR 0xe0000000 +#define MX51_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ + IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \ + IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \ + IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX51_AIPS2)) + +/* This is currently used in , but should go away */ +#define MX51_AIPS1_IO_ADDRESS(x) \ + (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) + /* * defines for SPBA modules */ @@ -210,48 +221,6 @@ #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL -/* Does given address belongs to the specified memory region? */ -#define ADDRESS_IN_REGION(addr, start, size) \ - (((addr) >= (start)) && ((addr) < (start)+(size))) - -/* Does given address belongs to the specified named `module'? */ -#define MX51_IS_MODULE(addr, module) \ - ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \ - MX51_ ## module ## _SIZE) -/* - * This macro defines the physical to virtual address mapping for all the - * peripheral modules. It is used by passing in the physical address as x - * and returning the virtual address. If the physical address is not mapped, - * it returns 0xdeadbeef - */ - -#define MX51_IO_ADDRESS(x) \ - (void __iomem *) \ - (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ - MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ - MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ - MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ - MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ - 0xdeadbeef) - -/* - * define the address mapping macros: in physical address order - */ -#define MX51_IRAM_IO_ADDRESS(x) \ - (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) - -#define MX51_DEBUG_IO_ADDRESS(x) \ - (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) - -#define MX51_SPBA0_IO_ADDRESS(x) \ - (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT) - -#define MX51_AIPS1_IO_ADDRESS(x) \ - (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) - -#define MX51_AIPS2_IO_ADDRESS(x) \ - (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) - #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 /* -- cgit v1.2.3 From 35bab0589b9a71533b37280eefa430c21dc102fe Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 9 Sep 2010 21:02:02 +0200 Subject: ARM: imx: change the way spi-imx devices are registered MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group soc specific data in a global struct instead of repeating it for each call to imxXX_add_spi_imxX. The structs holding the actual data are placed in .init.constdata and so don't do much harm. Compared to the previous approach this reduces code size to call imx_add_spi_imx. Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König --- arch/arm/mach-imx/devices-imx21.h | 9 +-- arch/arm/mach-imx/devices-imx27.h | 12 ++-- arch/arm/mach-mx25/devices-imx25.h | 12 ++-- arch/arm/mach-mx3/devices-imx31.h | 12 ++-- arch/arm/mach-mx3/devices-imx35.h | 9 +-- arch/arm/plat-mxc/devices/platform-spi_imx.c | 76 ++++++++++++++++++++++--- arch/arm/plat-mxc/include/mach/devices-common.h | 10 +++- 7 files changed, 103 insertions(+), 37 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 42788e99d127..2b45d3316267 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -24,7 +24,8 @@ #define imx21_add_mxc_nand(pdata) \ imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) -#define imx21_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata) -#define imx21_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata) +extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; +#define imx21_add_cspi(id, pdata) \ + imx_add_spi_imx(&imx21_cspi_data[id], pdata) +#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) +#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 65e7bb7ec2e8..04bfcf0f63d2 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -30,9 +30,9 @@ #define imx27_add_mxc_nand(pdata) \ imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) -#define imx27_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata) -#define imx27_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata) -#define imx27_add_spi_imx2(pdata) \ - imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata) +extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; +#define imx27_add_cspi(id, pdata) \ + imx_add_spi_imx(&imx27_cspi_data[id], pdata) +#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) +#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) +#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h index d86a7c3ca8b0..34a706105064 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -35,9 +35,9 @@ #define imx25_add_mxc_nand(pdata) \ imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) -#define imx25_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata) -#define imx25_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata) -#define imx25_add_spi_imx2(pdata) \ - imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata) +extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst; +#define imx25_add_spi_imx(id, pdata) \ + imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) +#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) +#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) +#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index 3b1a44a20585..7b4d022a59fa 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -30,9 +30,9 @@ #define imx31_add_mxc_nand(pdata) \ imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) -#define imx31_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata) -#define imx31_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata) -#define imx31_add_spi_imx2(pdata) \ - imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata) +extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; +#define imx31_add_cspi(id, pdata) \ + imx_add_spi_imx(&imx31_cspi_data[id], pdata) +#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) +#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) +#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index f6a431a4c3d2..af0bc1f86237 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -31,7 +31,8 @@ #define imx35_add_mxc_nand(pdata) \ imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) -#define imx35_add_spi_imx0(pdata) \ - imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata) -#define imx35_add_spi_imx1(pdata) \ - imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata) +extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; +#define imx35_add_cspi(id, pdata) \ + imx_add_spi_imx(&imx35_cspi_data[id], pdata) +#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) +#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 2831a6d3eb4b..412a81f24101 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -6,25 +6,83 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ -#include +#include #include -struct platform_device *__init imx_add_spi_imx(int id, - resource_size_t iobase, resource_size_t iosize, int irq, +#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_ ## type ## hwid, \ + } + +#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ + [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) + +#ifdef CONFIG_SOC_IMX21 +const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { +#define imx21_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K) + imx21_cspi_data_entry(0, 1), + imx21_cspi_data_entry(1, 2), +#endif + +#ifdef CONFIG_ARCH_MX25 +const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { +#define imx25_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) + imx25_cspi_data_entry(0, 1), + imx25_cspi_data_entry(1, 2), + imx25_cspi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { +#define imx27_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K) + imx27_cspi_data_entry(0, 1), + imx27_cspi_data_entry(1, 2), + imx27_cspi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { +#define imx31_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) + imx31_cspi_data_entry(0, 1), + imx31_cspi_data_entry(1, 2), + imx31_cspi_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX31 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { +#define imx35_cspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) + imx35_cspi_data_entry(0, 1), + imx35_cspi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX35 */ + +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, const struct spi_imx_master *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + return imx_add_platform_device("spi_imx", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 4a170a8da26c..e654287f0ba8 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -43,6 +43,12 @@ struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, int irq, const struct mxc_nand_platform_data *pdata); #include -struct platform_device *__init imx_add_spi_imx(int id, - resource_size_t iobase, resource_size_t iosize, int irq, +struct imx_spi_imx_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + int irq; +}; +struct platform_device *__init imx_add_spi_imx( + const struct imx_spi_imx_data *data, const struct spi_imx_master *pdata); -- cgit v1.2.3 From 5162de08d116fe7bbb912b17d84169983bfa16a8 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Aug 2010 22:57:24 +0200 Subject: ARM: imx: change the way imx-uarts are registered MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For mx1_defconfig this yields: add/remove: 1/0 grow/shrink: 1/4 up/down: 49/-108 (-59) function old new delta imx1_imx_uart_data - 48 +48 kernel_config_data 7277 7278 +1 imx_add_imx_uart_1irq 132 128 -4 imx_add_imx_uart_3irq 164 156 -8 scb9328_init 96 64 -32 mx1ads_init 220 156 -64 for mx21_defconfig this yields: add/remove: 1/0 grow/shrink: 0/3 up/down: 64/-52 (12) function old new delta imx21_imx_uart_data - 64 +64 imx_add_imx_uart_3irq 160 156 -4 imx_add_imx_uart_1irq 140 136 -4 mx21ads_board_init 220 176 -44 for a random mx25 config this yields: add/remove: 1/0 grow/shrink: 0/5 up/down: 80/-56 (24) function old new delta imx25_imx_uart_data - 80 +80 imx_add_imx_uart_3irq 160 156 -4 imx_add_imx_uart_1irq 140 136 -4 mx25pdk_init 288 272 -16 eukrea_mbimxsd_baseboard_init 272 256 -16 eukrea_cpuimx25_init 252 236 -16 for mx27_defconfig this yields: add/remove: 1/0 grow/shrink: 0/10 up/down: 96/-280 (-184) function old new delta imx27_imx_uart_data - 96 +96 imx_add_imx_uart_3irq 160 156 -4 imx_add_imx_uart_1irq 140 136 -4 pca100_init 560 544 -16 mx27pdk_init 112 96 -16 mx27lite_init 92 76 -16 eukrea_cpuimx27_init 332 316 -16 pcm038_init 388 348 -40 mxt_td60_board_init 320 280 -40 eukrea_mbimx27_baseboard_init 476 436 -40 mx27ads_board_init 368 280 -88 and finally for mx3_defconfig: add/remove: 2/0 grow/shrink: 0/9 up/down: 128/-344 (-216) function old new delta imx31_imx_uart_data - 80 +80 imx35_imx_uart_data - 48 +48 imx_add_imx_uart_1irq 132 128 -4 imx_add_imx_uart_3irq 164 152 -12 mx31moboard_devboard_init 360 344 -16 mx31lite_db_init 176 160 -16 mx31moboard_smartbot_init 384 360 -24 kzm_board_init 232 208 -24 armadillo5x0_init 392 364 -28 mx31lilly_db_init 248 208 -40 mxc_board_init 3760 3580 -180 Signed-off-by: Uwe Kleine-König --- arch/arm/mach-imx/devices-imx1.h | 9 +- arch/arm/mach-imx/devices-imx21.h | 15 ++- arch/arm/mach-imx/devices-imx27.h | 21 ++-- arch/arm/mach-mx25/devices-imx25.h | 18 ++-- arch/arm/mach-mx3/devices-imx31.h | 18 ++-- arch/arm/mach-mx3/devices-imx35.h | 12 +-- arch/arm/plat-mxc/devices/platform-imx-uart.c | 127 ++++++++++++++++++++---- arch/arm/plat-mxc/include/mach/devices-common.h | 26 +++-- 8 files changed, 167 insertions(+), 79 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h index a8d94f078196..2861cb8b100a 100644 --- a/arch/arm/mach-imx/devices-imx1.h +++ b/arch/arm/mach-imx/devices-imx1.h @@ -12,7 +12,8 @@ #define imx1_add_i2c_imx(pdata) \ imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) -#define imx1_add_imx_uart0(pdata) \ - imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata) -#define imx1_add_imx_uart1(pdata) \ - imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata) +extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; +#define imx1_add_imx_uart(id, pdata) \ + imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) +#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) +#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 2b45d3316267..f75b5e4d0ed5 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -12,14 +12,13 @@ #define imx21_add_i2c_imx(pdata) \ imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) -#define imx21_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata) -#define imx21_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata) -#define imx21_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata) -#define imx21_add_imx_uart3(pdata) \ - imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata) +extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; +#define imx21_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) +#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) +#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata) +#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) +#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) #define imx21_add_mxc_nand(pdata) \ imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 04bfcf0f63d2..bf9dab3a0858 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -14,18 +14,15 @@ #define imx27_add_i2c_imx1(pdata) \ imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) -#define imx27_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata) -#define imx27_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata) -#define imx27_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata) -#define imx27_add_imx_uart3(pdata) \ - imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata) -#define imx27_add_imx_uart4(pdata) \ - imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata) -#define imx27_add_imx_uart5(pdata) \ - imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata) +extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; +#define imx27_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) +#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) +#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata) +#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata) +#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata) +#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) +#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) #define imx27_add_mxc_nand(pdata) \ imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h index 34a706105064..439400b5d275 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -21,16 +21,14 @@ #define imx25_add_imx_i2c2(pdata) \ imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) -#define imx25_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata) -#define imx25_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata) -#define imx25_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata) -#define imx25_add_imx_uart3(pdata) \ - imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata) -#define imx25_add_imx_uart4(pdata) \ - imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata) +extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; +#define imx25_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) +#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) +#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata) +#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata) +#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) +#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) #define imx25_add_mxc_nand(pdata) \ imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index 7b4d022a59fa..a8c5f1bfce3b 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -16,16 +16,14 @@ #define imx31_add_imx_i2c2(pdata) \ imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) -#define imx31_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata) -#define imx31_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata) -#define imx31_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata) -#define imx31_add_imx_uart3(pdata) \ - imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata) -#define imx31_add_imx_uart4(pdata) \ - imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata) +extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; +#define imx31_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) +#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) +#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata) +#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata) +#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) +#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) #define imx31_add_mxc_nand(pdata) \ imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index af0bc1f86237..6a76b4d72e49 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -21,12 +21,12 @@ #define imx35_add_imx_i2c2(pdata) \ imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) -#define imx35_add_imx_uart0(pdata) \ - imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata) -#define imx35_add_imx_uart1(pdata) \ - imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata) -#define imx35_add_imx_uart2(pdata) \ - imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata) +extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; +#define imx35_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) +#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) +#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) +#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) #define imx35_add_mxc_nand(pdata) \ imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index fa3dff1433e8..af7fabba4e71 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -6,55 +6,138 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ +#include #include -struct platform_device *__init imx_add_imx_uart_3irq(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irqrx, resource_size_t irqtx, - resource_size_t irqrts, +#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irqrx = soc ## _INT_UART ## _hwid ## RX, \ + .irqtx = soc ## _INT_UART ## _hwid ## TX, \ + .irqrts = soc ## _INT_UART ## _hwid ## RTS, \ + } + +#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_UART ## _hwid, \ + } + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = { +#define imx1_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0) + imx1_imx_uart_data_entry(0, 1), + imx1_imx_uart_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX1 */ + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { +#define imx21_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_imx_uart_data_entry(0, 1), + imx21_imx_uart_data_entry(1, 2), + imx21_imx_uart_data_entry(2, 3), + imx21_imx_uart_data_entry(3, 4), +}; +#endif + +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { +#define imx25_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_imx_uart_data_entry(0, 1), + imx25_imx_uart_data_entry(1, 2), + imx25_imx_uart_data_entry(2, 3), + imx25_imx_uart_data_entry(3, 4), + imx25_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { +#define imx27_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_uart_data_entry(0, 1), + imx27_imx_uart_data_entry(1, 2), + imx27_imx_uart_data_entry(2, 3), + imx27_imx_uart_data_entry(3, 4), + imx27_imx_uart_data_entry(4, 5), + imx27_imx_uart_data_entry(5, 6), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { +#define imx31_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_uart_data_entry(0, 1), + imx31_imx_uart_data_entry(1, 2), + imx31_imx_uart_data_entry(2, 3), + imx31_imx_uart_data_entry(3, 4), + imx31_imx_uart_data_entry(4, 5), +}; +#endif /* ifdef CONFIG_ARCH_MX31 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { +#define imx35_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) + imx35_imx_uart_data_entry(0, 1), + imx35_imx_uart_data_entry(1, 2), + imx35_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX35 */ + +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, const struct imxuart_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irqrx, - .end = irqrx, + .start = data->irqrx, + .end = data->irqrx, .flags = IORESOURCE_IRQ, }, { - .start = irqtx, - .end = irqtx, + .start = data->irqtx, + .end = data->irqtx, .flags = IORESOURCE_IRQ, }, { - .start = irqrts, - .end = irqrx, + .start = data->irqrts, + .end = data->irqrx, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); + return imx_add_platform_device("imx-uart", data->id, res, + ARRAY_SIZE(res), pdata, sizeof(*pdata)); } -struct platform_device *__init imx_add_imx_uart_1irq(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, const struct imxuart_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), + return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index e654287f0ba8..12bdc7d027c7 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -26,14 +26,26 @@ struct platform_device *__init imx_add_imx_i2c(int id, const struct imxi2c_platform_data *pdata); #include -struct platform_device *__init imx_add_imx_uart_3irq(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irqrx, resource_size_t irqtx, - resource_size_t irqrts, +struct imx_imx_uart_3irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irqrx; + resource_size_t irqtx; + resource_size_t irqrts; +}; +struct platform_device *__init imx_add_imx_uart_3irq( + const struct imx_imx_uart_3irq_data *data, const struct imxuart_platform_data *pdata); -struct platform_device *__init imx_add_imx_uart_1irq(int id, - resource_size_t iobase, resource_size_t iosize, - resource_size_t irq, + +struct imx_imx_uart_1irq_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_uart_1irq( + const struct imx_imx_uart_1irq_data *data, const struct imxuart_platform_data *pdata); #include -- cgit v1.2.3 From 4697bb926f43b8012ebd111ef43834f42126a0ef Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 25 Aug 2010 17:37:45 +0200 Subject: ARM: imx: dynamically allocate imx-ssi devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/mach-imx/Kconfig | 5 +- arch/arm/mach-imx/devices-imx21.h | 4 + arch/arm/mach-imx/devices-imx27.h | 4 + arch/arm/mach-imx/devices.c | 35 --------- arch/arm/mach-imx/devices.h | 2 - arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 6 +- arch/arm/mach-imx/mach-pca100.c | 5 +- arch/arm/mach-mx25/Kconfig | 4 +- arch/arm/mach-mx25/devices-imx25.h | 4 + arch/arm/mach-mx25/devices.c | 38 ---------- arch/arm/mach-mx25/devices.h | 2 - arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c | 6 +- arch/arm/mach-mx3/Kconfig | 6 +- arch/arm/mach-mx3/devices-imx31.h | 4 + arch/arm/mach-mx3/devices-imx35.h | 4 + arch/arm/mach-mx3/devices.c | 42 ----------- arch/arm/mach-mx3/devices.h | 3 - arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c | 6 +- arch/arm/mach-mx3/mach-mx31ads.c | 2 +- arch/arm/mach-mx3/mach-pcm043.c | 5 +- arch/arm/plat-mxc/devices/Kconfig | 3 + arch/arm/plat-mxc/devices/Makefile | 1 + arch/arm/plat-mxc/devices/platform-imx-ssi.c | 98 +++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/devices-common.h | 15 ++++ arch/arm/plat-mxc/include/mach/mx25.h | 9 +++ arch/arm/plat-mxc/include/mach/mx31.h | 9 +++ arch/arm/plat-mxc/include/mach/mx35.h | 9 +++ 27 files changed, 187 insertions(+), 144 deletions(-) create mode 100644 arch/arm/plat-mxc/devices/platform-imx-ssi.c (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 19ed16d0017e..9b45f1f523fa 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -146,8 +146,8 @@ choice default MACH_EUKREA_MBIMX27_BASEBOARD config MACH_EUKREA_MBIMX27_BASEBOARD - prompt "Eukrea MBIMX27 development board" - bool + bool "Eukrea MBIMX27 development board" + select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SPI_IMX help @@ -182,6 +182,7 @@ config MACH_IMX27LITE config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_SPI_IMX diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index f75b5e4d0ed5..24868c36d824 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -12,6 +12,10 @@ #define imx21_add_i2c_imx(pdata) \ imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) +extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; +#define imx21_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) + extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; #define imx21_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index bf9dab3a0858..2972e6912af4 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -14,6 +14,10 @@ #define imx27_add_i2c_imx1(pdata) \ imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) +extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; +#define imx27_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) + extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; #define imx27_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c index 9c271a752b84..423fa05dabd0 100644 --- a/arch/arm/mach-imx/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -480,41 +480,6 @@ struct platform_device mxc_usbh2 = { }; #endif -#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ - { \ - .name = _name, \ - .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ - .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ - .flags = IORESOURCE_DMA, \ - } - -#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ - static struct resource imx_ssi_resources ## n[] = { \ - { \ - .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ - .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ - .flags = IORESOURCE_MEM, \ - }, { \ - .start = MX2x_INT_SSI1, \ - .end = MX2x_INT_SSI1, \ - .flags = IORESOURCE_IRQ, \ - }, \ - DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ - DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ - DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ - DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ - }; \ - \ - struct platform_device imx_ssi_device ## n = { \ - .name = "imx-ssi", \ - .id = n, \ - .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ - .resource = imx_ssi_resources ## n, \ - } - -DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); -DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); - /* GPIO port description */ #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ { \ diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h index efd4527506a5..57d4b1cac039 100644 --- a/arch/arm/mach-imx/devices.h +++ b/arch/arm/mach-imx/devices.h @@ -26,7 +26,5 @@ extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mx21_usbhc_device; -extern struct platform_device imx_ssi_device0; -extern struct platform_device imx_ssi_device1; extern struct platform_device imx_kpp_device; #endif diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index 4edc5f439201..cb433aeec939 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include "devices-imx27.h" @@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = { .dat3_card_detect = 1, }; -struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = { +static const +struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = { .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, }; @@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void) i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); - mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata); + imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata); #if defined(CONFIG_TOUCHSCREEN_ADS7846) \ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 23c9e1f37b9c..93e0d66e37dc 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include #include @@ -252,7 +251,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) msleep(2); } -static struct imx_ssi_platform_data pca100_ssi_pdata = { +static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = { .ac97_reset = pca100_ac97_cold_reset, .ac97_warm_reset = pca100_ac97_warm_reset, .flags = IMX_SSI_USE_AC97, @@ -389,7 +388,7 @@ static void __init pca100_init(void) if (ret) printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); - mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); + imx27_add_imx_ssi(0, &pca100_ssi_pdata); imx27_add_imx_uart0(&uart_pdata); diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig index c71a7bc19284..326bb648f466 100644 --- a/arch/arm/mach-mx25/Kconfig +++ b/arch/arm/mach-mx25/Kconfig @@ -20,8 +20,8 @@ choice default MACH_EUKREA_MBIMXSD25_BASEBOARD config MACH_EUKREA_MBIMXSD25_BASEBOARD - prompt "Eukrea MBIMXSD development board" - bool + bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_IMX_SSI help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h index 439400b5d275..bf93facef3d0 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -21,6 +21,10 @@ #define imx25_add_imx_i2c2(pdata) \ imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) +extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; +#define imx25_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) + extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; #define imx25_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 3468eb15b236..bc19e8cc26df 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -305,44 +305,6 @@ struct platform_device mx25_kpp_device = { .resource = mx25_kpp_resources, }; -static struct resource imx_ssi_resources0[] = { - { - .start = MX25_SSI1_BASE_ADDR, - .end = MX25_SSI1_BASE_ADDR + 0x3fff, - .flags = IORESOURCE_MEM, - }, { - .start = MX25_INT_SSI1, - .end = MX25_INT_SSI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource imx_ssi_resources1[] = { - { - .start = MX25_SSI2_BASE_ADDR, - .end = MX25_SSI2_BASE_ADDR + 0x3fff, - .flags = IORESOURCE_MEM - }, { - .start = MX25_INT_SSI2, - .end = MX25_INT_SSI2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", - .id = 0, - .num_resources = ARRAY_SIZE(imx_ssi_resources0), - .resource = imx_ssi_resources0, -}; - -struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", - .id = 1, - .num_resources = ARRAY_SIZE(imx_ssi_resources1), - .resource = imx_ssi_resources1, -}; - static struct resource mx25_csi_resources[] = { { .start = MX25_CSI_BASE_ADDR, diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index 4aceb68e35a7..f6e6d3a5f640 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -11,6 +11,4 @@ extern struct platform_device mx25_rtc_device; extern struct platform_device mx25_fb_device; extern struct platform_device mxc_wdt; extern struct platform_device mx25_kpp_device; -extern struct platform_device imx_ssi_device0; -extern struct platform_device imx_ssi_device1; extern struct platform_device mx25_csi_device; diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c index 4aaadc753d3e..2062dd930955 100644 --- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include "devices-imx25.h" @@ -205,7 +204,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { }, }; -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { +static const +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; @@ -239,7 +239,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void) imx25_add_imx_uart1(&uart_pdata); mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); - mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); + imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 5cee1a5c4bd2..d762bf8e539b 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -17,6 +17,7 @@ config MACH_MX31ADS bool "Support MX31ADS platforms" select ARCH_MX31 select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART default y help @@ -118,6 +119,7 @@ config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select ARCH_MX35 select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_SSI select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_MXC_NAND select IMX_HAVE_PLATFORM_FLEXCAN @@ -172,8 +174,8 @@ choice default MACH_EUKREA_MBIMXSD35_BASEBOARD config MACH_EUKREA_MBIMXSD35_BASEBOARD - prompt "Eukrea MBIMXSD development board" - bool + bool "Eukrea MBIMXSD development board" + select IMX_HAVE_PLATFORM_IMX_SSI help This adds board specific devices that can be found on Eukrea's MBIMXSD evaluation board. diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index a8c5f1bfce3b..b8568a1af81d 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -16,6 +16,10 @@ #define imx31_add_imx_i2c2(pdata) \ imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) +extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; +#define imx31_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) + extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; #define imx31_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index 6a76b4d72e49..813e570fd3ba 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -21,6 +21,10 @@ #define imx35_add_imx_i2c2(pdata) \ imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) +extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; +#define imx35_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) + extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; #define imx35_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index a4fd1a26fc91..87a9a21457b9 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -302,44 +302,6 @@ struct platform_device mxc_fec_device = { }; #endif -static struct resource imx_ssi_resources0[] = { - { - .start = SSI1_BASE_ADDR, - .end = SSI1_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MX31_INT_SSI1, - .end = MX31_INT_SSI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource imx_ssi_resources1[] = { - { - .start = SSI2_BASE_ADDR, - .end = SSI2_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM - }, { - .start = MX31_INT_SSI2, - .end = MX31_INT_SSI2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", - .id = 0, - .num_resources = ARRAY_SIZE(imx_ssi_resources0), - .resource = imx_ssi_resources0, -}; - -struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", - .id = 1, - .num_resources = ARRAY_SIZE(imx_ssi_resources1), - .resource = imx_ssi_resources1, -}; - static struct resource imx_wdt_resources[] = { { .flags = IORESOURCE_MEM, @@ -410,10 +372,6 @@ static int __init mx3_devices_init(void) mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; mxc_usbh1_resources[1].start = MXC_INT_USBHS; mxc_usbh1_resources[1].end = MXC_INT_USBHS; - imx_ssi_resources0[1].start = MX35_INT_SSI1; - imx_ssi_resources0[1].end = MX35_INT_SSI1; - imx_ssi_resources1[1].start = MX35_INT_SSI2; - imx_ssi_resources1[1].end = MX35_INT_SSI2; imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; } diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index e5535234839f..2a69465bc542 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -10,9 +10,6 @@ extern struct platform_device mxc_otg_host; extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_rnga_device; -extern struct platform_device imx_ssi_device0; -extern struct platform_device imx_ssi_device1; -extern struct platform_device imx_ssi_device1; extern struct platform_device imx_wdt_device0; extern struct platform_device imx_rtc_device0; extern struct platform_device imx_kpp_device; diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index f8f15e3ac7a0..cb667b6f17ae 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c @@ -43,7 +43,6 @@ #include #include #include -#include #include "devices-imx35.h" #include "devices.h" @@ -206,7 +205,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { }, }; -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { +static const +struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, }; @@ -242,7 +242,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); - mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); + imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); gpio_request(GPIO_LED1, "LED1"); gpio_direction_output(GPIO_LED1, 1); diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 94b3e7c42404..96cedc4a47f5 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -517,7 +517,7 @@ static unsigned int ssi_pins[] = { static void mxc_init_audio(void) { - mxc_register_device(&imx_ssi_device0, NULL); + imx31_add_imx_ssi(0, NULL); mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); } diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 28886f0e62f9..dcc216bb3952 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -42,7 +42,6 @@ #include #include #include -#include #include "devices-imx35.h" #include "devices.h" @@ -293,7 +292,7 @@ err1: mdelay(1); } -static struct imx_ssi_platform_data pcm043_ssi_pdata = { +static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { .ac97_reset = pcm043_ac97_cold_reset, .ac97_warm_reset = pcm043_ac97_warm_reset, .flags = IMX_SSI_USE_AC97, @@ -361,7 +360,7 @@ static void __init mxc_board_init(void) imx35_add_imx_uart0(&uart_pdata); imx35_add_mxc_nand(&pcm037_nand_board_info); - mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); + imx35_add_imx_ssi(0, &pcm043_ssi_pdata); imx35_add_imx_uart1(&uart_pdata); diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 9ab784b776f9..d736c3d4e292 100644 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -5,6 +5,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN config IMX_HAVE_PLATFORM_IMX_I2C bool +config IMX_HAVE_PLATFORM_IMX_SSI + bool + config IMX_HAVE_PLATFORM_IMX_UART bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index 2062ab4d094d..ac7738379374 100644 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c new file mode 100644 index 000000000000..1535bc9f0601 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \ + [_id] = { \ + .id = _id, \ + .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_SSI ## _hwid, \ + .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \ + .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \ + .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \ + .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { +#define imx21_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K) + imx21_imx_ssi_data_entry(0, 1), + imx21_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { +#define imx25_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) + imx25_imx_ssi_data_entry(0, 1), + imx25_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { +#define imx27_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_ssi_data_entry(0, 1), + imx27_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { +#define imx31_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_ssi_data_entry(0, 1), + imx31_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX31 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { +#define imx35_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) + imx35_imx_ssi_data_entry(0, 1), + imx35_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX35 */ + +struct platform_device *__init imx_add_imx_ssi( + const struct imx_imx_ssi_data *data, + const struct imx_ssi_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, +#define DMARES(_name) { \ + .name = #_name, \ + .start = data->dma ## _name, \ + .end = data->dma ## _name, \ + .flags = IORESOURCE_DMA, \ +} + DMARES(tx0), + DMARES(rx0), + DMARES(tx1), + DMARES(rx1), + }; + + return imx_add_platform_device("imx-ssi", data->id, + res, ARRAY_SIZE(res), + pdata, sizeof(*pdata)); +} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 12bdc7d027c7..84bfe44ec2cd 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -25,6 +25,21 @@ struct platform_device *__init imx_add_imx_i2c(int id, resource_size_t iobase, resource_size_t iosize, int irq, const struct imxi2c_platform_data *pdata); +#include +struct imx_imx_ssi_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; + resource_size_t dmatx0; + resource_size_t dmarx0; + resource_size_t dmatx1; + resource_size_t dmarx1; +}; +struct platform_device *__init imx_add_imx_ssi( + const struct imx_imx_ssi_data *data, + const struct imx_ssi_platform_data *pdata); + #include struct imx_imx_uart_3irq_data { int id; diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 4a6f800990f8..8f809eb084df 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -77,4 +77,13 @@ #define MX25_INT_UART1 45 #define MX25_INT_FEC 57 +#define MX25_DMA_REQ_SSI2_RX1 22 +#define MX25_DMA_REQ_SSI2_TX1 23 +#define MX25_DMA_REQ_SSI2_RX0 24 +#define MX25_DMA_REQ_SSI2_TX0 25 +#define MX25_DMA_REQ_SSI1_RX1 26 +#define MX25_DMA_REQ_SSI1_TX1 27 +#define MX25_DMA_REQ_SSI1_RX0 28 +#define MX25_DMA_REQ_SSI1_TX0 29 + #endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index afee3ab9d62e..eb8bbc7eedfa 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_EXT_WDOG 62 #define MX31_INT_EXT_TV 63 +#define MX31_DMA_REQ_SSI2_RX1 22 +#define MX31_DMA_REQ_SSI2_TX1 23 +#define MX31_DMA_REQ_SSI2_RX0 24 +#define MX31_DMA_REQ_SSI2_TX0 25 +#define MX31_DMA_REQ_SSI1_RX1 26 +#define MX31_DMA_REQ_SSI1_TX1 27 +#define MX31_DMA_REQ_SSI1_RX0 28 +#define MX31_DMA_REQ_SSI1_TX0 29 + #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index af3038c12e39..867b8c0ca105 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -173,6 +173,15 @@ #define MX35_INT_EXT_WDOG 62 #define MX35_INT_EXT_TV 63 +#define MX35_DMA_REQ_SSI2_RX1 22 +#define MX35_DMA_REQ_SSI2_TX1 23 +#define MX35_DMA_REQ_SSI2_RX0 24 +#define MX35_DMA_REQ_SSI2_TX0 25 +#define MX35_DMA_REQ_SSI1_RX1 26 +#define MX35_DMA_REQ_SSI1_TX1 27 +#define MX35_DMA_REQ_SSI1_RX0 28 +#define MX35_DMA_REQ_SSI1_TX0 29 + #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ -- cgit v1.2.3 From 64de5ec168d9743903e6ec482c3e9f37af49f9c1 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 21 Sep 2010 12:13:34 +0200 Subject: ARM: imx: reorganize imx-i2c device registration to use a struct per SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/mach-imx/devices-imx1.h | 3 +- arch/arm/mach-imx/devices-imx21.h | 3 +- arch/arm/mach-imx/devices-imx27.h | 9 +-- arch/arm/mach-mx25/devices-imx25.h | 12 ++-- arch/arm/mach-mx3/devices-imx31.h | 12 ++-- arch/arm/mach-mx3/devices-imx35.h | 12 ++-- arch/arm/plat-mxc/devices/platform-imx-i2c.c | 75 ++++++++++++++++++++++--- arch/arm/plat-mxc/include/mach/devices-common.h | 10 +++- arch/arm/plat-mxc/include/mach/mx51.h | 4 +- 9 files changed, 105 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h index 2861cb8b100a..6cf08640dae9 100644 --- a/arch/arm/mach-imx/devices-imx1.h +++ b/arch/arm/mach-imx/devices-imx1.h @@ -9,8 +9,9 @@ #include #include +extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; #define imx1_add_i2c_imx(pdata) \ - imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) + imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; #define imx1_add_imx_uart(id, pdata) \ diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 24868c36d824..d3d2b2669b96 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -9,8 +9,9 @@ #include #include +extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; #define imx21_add_i2c_imx(pdata) \ - imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) + imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; #define imx21_add_imx_ssi(id, pdata) \ diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 2972e6912af4..193dfb55023b 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -9,10 +9,11 @@ #include #include -#define imx27_add_i2c_imx0(pdata) \ - imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata) -#define imx27_add_i2c_imx1(pdata) \ - imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata) +extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; +#define imx27_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) +#define imx27_add_i2c_imx0(pdata) imx27_add_imx_i2c(0, pdata) +#define imx27_add_i2c_imx1(pdata) imx27_add_imx_i2c(1, pdata) extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; #define imx27_add_imx_ssi(id, pdata) \ diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h index bf93facef3d0..1dd95721d9f5 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -14,12 +14,12 @@ #define imx25_add_flexcan1(pdata) \ imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) -#define imx25_add_imx_i2c0(pdata) \ - imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata) -#define imx25_add_imx_i2c1(pdata) \ - imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata) -#define imx25_add_imx_i2c2(pdata) \ - imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) +extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; +#define imx25_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) +#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) +#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) +#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; #define imx25_add_imx_ssi(id, pdata) \ diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index b8568a1af81d..eea425ff074e 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -9,12 +9,12 @@ #include #include -#define imx31_add_imx_i2c0(pdata) \ - imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata) -#define imx31_add_imx_i2c1(pdata) \ - imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata) -#define imx31_add_imx_i2c2(pdata) \ - imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) +extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; +#define imx31_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) +#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) +#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) +#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; #define imx31_add_imx_ssi(id, pdata) \ diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index 813e570fd3ba..f187d3552738 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -14,12 +14,12 @@ #define imx35_add_flexcan1(pdata) \ imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) -#define imx35_add_imx_i2c0(pdata) \ - imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata) -#define imx35_add_imx_i2c1(pdata) \ - imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata) -#define imx35_add_imx_i2c2(pdata) \ - imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) +extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; +#define imx35_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) +#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) +#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) +#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; #define imx35_add_imx_ssi(id, pdata) \ diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index d0af9f7d8aed..ab9670b96c8a 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -6,24 +6,85 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. */ +#include #include -struct platform_device *__init imx_add_imx_i2c(int id, - resource_size_t iobase, resource_size_t iosize, int irq, +#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) \ + { \ + .id = _id, \ + .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_I2C ## _hwid, \ + } + +#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size) \ + [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) + +#ifdef CONFIG_SOC_IMX1 +const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst = + imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX1 */ + +#ifdef CONFIG_SOC_IMX21 +const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = + imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_ARCH_MX25 +const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { +#define imx25_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) + imx25_imx_i2c_data_entry(0, 1), + imx25_imx_i2c_data_entry(1, 2), + imx25_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { +#define imx27_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K) + imx27_imx_i2c_data_entry(0, 1), + imx27_imx_i2c_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { +#define imx31_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) + imx31_imx_i2c_data_entry(0, 1), + imx31_imx_i2c_data_entry(1, 2), + imx31_imx_i2c_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX31 */ + +#ifdef CONFIG_ARCH_MX35 +const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { +#define imx35_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) + imx35_imx_i2c_data_entry(0, 1), + imx35_imx_i2c_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX35 */ + +struct platform_device *__init imx_add_imx_i2c( + const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata) { struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), + return imx_add_platform_device("imx-i2c", data->id, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 84bfe44ec2cd..490fe7c3ed5f 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -21,8 +21,14 @@ struct platform_device *__init imx_add_flexcan(int id, const struct flexcan_platform_data *pdata); #include -struct platform_device *__init imx_add_imx_i2c(int id, - resource_size_t iobase, resource_size_t iosize, int irq, +struct imx_imx_i2c_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_imx_i2c( + const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata); #include diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index f6026506c5ef..b919235768a0 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -341,8 +341,8 @@ #define MX51_MXC_INT_WDOG2 59 #define MX51_MXC_INT_KPP 60 #define MX51_MXC_INT_PWM1 61 -#define MX51_MXC_INT_I2C1 62 -#define MX51_MXC_INT_I2C2 63 +#define MX51_INT_I2C1 62 +#define MX51_INT_I2C2 63 #define MX51_MXC_INT_HS_I2C 64 #define MX51_MXC_INT_RESV65 65 #define MX51_MXC_INT_RESV66 66 -- cgit v1.2.3 From b42a81ca0fa7b3b442a0731ffc4e7db44464b5f2 Mon Sep 17 00:00:00 2001 From: Jassi Brar Date: Wed, 29 Sep 2010 17:31:33 +0900 Subject: spi/s3c64xx: Consider the clk_from_cmu flag Newer SoCs have the SPI clock scaling control in platform's clock management unit. Inorder for such SoCs to work, we need to check the flag clk_from_cmu before making any clock changes. Signed-off-by: Jassi Brar Signed-off-by: Grant Likely --- arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | 3 + drivers/spi/spi_s3c64xx.c | 94 ++++++++++++++---------- 2 files changed, 59 insertions(+), 38 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index e5aba8f95b79..b226f7405e6b 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -32,6 +32,8 @@ struct s3c64xx_spi_csinfo { * struct s3c64xx_spi_info - SPI Controller defining structure * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. * @src_clk_name: Platform name of the corresponding clock. + * @clk_from_cmu: If the SPI clock/prescalar control block is present + * by the platform's clock-management-unit and not in SPI controller. * @num_cs: Number of CS this controller emulates. * @cfg_gpio: Configure pins for this SPI controller. * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 @@ -41,6 +43,7 @@ struct s3c64xx_spi_csinfo { struct s3c64xx_spi_info { int src_clk_nr; char *src_clk_name; + bool clk_from_cmu; int num_cs; diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c index e7b893f2a21b..9e0aa3c7b4d1 100644 --- a/drivers/spi/spi_s3c64xx.c +++ b/drivers/spi/spi_s3c64xx.c @@ -399,13 +399,18 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) { + struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; u32 val; /* Disable Clock */ - val = readl(regs + S3C64XX_SPI_CLK_CFG); - val &= ~S3C64XX_SPI_ENCLK_ENABLE; - writel(val, regs + S3C64XX_SPI_CLK_CFG); + if (sci->clk_from_cmu) { + clk_disable(sdd->src_clk); + } else { + val = readl(regs + S3C64XX_SPI_CLK_CFG); + val &= ~S3C64XX_SPI_ENCLK_ENABLE; + writel(val, regs + S3C64XX_SPI_CLK_CFG); + } /* Set Polarity and Phase */ val = readl(regs + S3C64XX_SPI_CH_CFG); @@ -441,17 +446,25 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); - /* Configure Clock */ - val = readl(regs + S3C64XX_SPI_CLK_CFG); - val &= ~S3C64XX_SPI_PSR_MASK; - val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) - & S3C64XX_SPI_PSR_MASK); - writel(val, regs + S3C64XX_SPI_CLK_CFG); - - /* Enable Clock */ - val = readl(regs + S3C64XX_SPI_CLK_CFG); - val |= S3C64XX_SPI_ENCLK_ENABLE; - writel(val, regs + S3C64XX_SPI_CLK_CFG); + if (sci->clk_from_cmu) { + /* Configure Clock */ + /* There is half-multiplier before the SPI */ + clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); + /* Enable Clock */ + clk_enable(sdd->src_clk); + } else { + /* Configure Clock */ + val = readl(regs + S3C64XX_SPI_CLK_CFG); + val &= ~S3C64XX_SPI_PSR_MASK; + val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) + & S3C64XX_SPI_PSR_MASK); + writel(val, regs + S3C64XX_SPI_CLK_CFG); + + /* Enable Clock */ + val = readl(regs + S3C64XX_SPI_CLK_CFG); + val |= S3C64XX_SPI_ENCLK_ENABLE; + writel(val, regs + S3C64XX_SPI_CLK_CFG); + } } static void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id, @@ -806,7 +819,6 @@ static int s3c64xx_spi_setup(struct spi_device *spi) struct s3c64xx_spi_driver_data *sdd; struct s3c64xx_spi_info *sci; struct spi_message *msg; - u32 psr, speed; unsigned long flags; int err = 0; @@ -849,32 +861,37 @@ static int s3c64xx_spi_setup(struct spi_device *spi) } /* Check if we can provide the requested rate */ - speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); /* Max possible */ - - if (spi->max_speed_hz > speed) - spi->max_speed_hz = speed; - - psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; - psr &= S3C64XX_SPI_PSR_MASK; - if (psr == S3C64XX_SPI_PSR_MASK) - psr--; + if (!sci->clk_from_cmu) { + u32 psr, speed; + + /* Max possible */ + speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); + + if (spi->max_speed_hz > speed) + spi->max_speed_hz = speed; + + psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; + psr &= S3C64XX_SPI_PSR_MASK; + if (psr == S3C64XX_SPI_PSR_MASK) + psr--; + + speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + if (spi->max_speed_hz < speed) { + if (psr+1 < S3C64XX_SPI_PSR_MASK) { + psr++; + } else { + err = -EINVAL; + goto setup_exit; + } + } - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); - if (spi->max_speed_hz < speed) { - if (psr+1 < S3C64XX_SPI_PSR_MASK) { - psr++; - } else { + speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); + if (spi->max_speed_hz >= speed) + spi->max_speed_hz = speed; + else err = -EINVAL; - goto setup_exit; - } } - speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); - if (spi->max_speed_hz >= speed) - spi->max_speed_hz = speed; - else - err = -EINVAL; - setup_exit: /* setup() returns with device de-selected */ @@ -896,7 +913,8 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) /* Disable Interrupts - we use Polling if not DMA mode */ writel(0, regs + S3C64XX_SPI_INT_EN); - writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, + if (!sci->clk_from_cmu) + writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, regs + S3C64XX_SPI_CLK_CFG); writel(0, regs + S3C64XX_SPI_MODE_CFG); writel(0, regs + S3C64XX_SPI_PACKET_CNT); -- cgit v1.2.3 From 98d943b02f6f1b57787ff1aa6f34d019a407e3ee Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Wed, 29 Sep 2010 16:52:25 +0200 Subject: oprofile, ARM: Release resources on failure This patch fixes a resource leak on failure, where the oprofilefs and some counters may not released properly. Signed-off-by: Robert Richter Acked-by: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: # .35.x LKML-Reference: <20100929145225.GJ13563@erda.amd.com> Signed-off-by: Ingo Molnar --- arch/arm/oprofile/common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 0691176899ff..72e09eb642dd 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -102,6 +102,7 @@ static int op_create_counter(int cpu, int event) if (IS_ERR(pevent)) { ret = PTR_ERR(pevent); } else if (pevent->state != PERF_EVENT_STATE_ACTIVE) { + perf_event_release_kernel(pevent); pr_warning("oprofile: failed to enable event %d " "on CPU %d\n", event, cpu); ret = -EBUSY; @@ -365,6 +366,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) ret = init_driverfs(); if (ret) { kfree(counter_config); + counter_config = NULL; return ret; } @@ -402,7 +404,6 @@ void oprofile_arch_exit(void) struct perf_event *event; if (*perf_events) { - exit_driverfs(); for_each_possible_cpu(cpu) { for (id = 0; id < perf_num_counters; ++id) { event = perf_events[cpu][id]; @@ -413,8 +414,10 @@ void oprofile_arch_exit(void) } } - if (counter_config) + if (counter_config) { kfree(counter_config); + exit_driverfs(); + } } #else int __init oprofile_arch_init(struct oprofile_operations *ops) -- cgit v1.2.3 From 44505c0768971f4aa94ca09c8155448a46a7ff8a Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 30 Sep 2010 16:44:53 +0200 Subject: ARM: mx5: dynamically register imx-i2c devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/Kconfig | 2 ++ arch/arm/mach-mx5/board-cpuimx51.c | 6 ++--- arch/arm/mach-mx5/board-mx51_babbage.c | 7 +++-- arch/arm/mach-mx5/devices-imx51.h | 14 ++++++++++ arch/arm/mach-mx5/devices.c | 38 ---------------------------- arch/arm/mach-mx5/devices.h | 2 -- arch/arm/plat-mxc/devices/platform-imx-i2c.c | 9 +++++++ 7 files changed, 31 insertions(+), 47 deletions(-) create mode 100644 arch/arm/mach-mx5/devices-imx51.h (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 0848db5dd364..e57caefb1f28 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -10,6 +10,7 @@ comment "MX5 platforms:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" + select IMX_HAVE_PLATFORM_IMX_I2C help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its @@ -24,6 +25,7 @@ config MACH_MX51_3DS config MACH_EUKREA_CPUIMX51 bool "Support Eukrea CPUIMX51 module" + select IMX_HAVE_PLATFORM_IMX_I2C help Include support for Eukrea CPUIMX51 platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index 623607a20f57..d52f2527f6bf 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include @@ -152,7 +151,8 @@ static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; -static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = { +static const +struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = { .bitrate = 100000, }; @@ -255,7 +255,7 @@ static void __init eukrea_cpuimx51_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data); + imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data); i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index caa8f680649e..3f3075d7768f 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -137,7 +136,7 @@ static inline void mxc_init_imx_uart(void) } #endif /* SERIAL_IMX */ -static struct imxi2c_platform_data babbage_i2c_data = { +static const struct imxi2c_platform_data babbage_i2c_data __initconst = { .bitrate = 100000, }; @@ -293,8 +292,8 @@ static void __init mxc_board_init(void) babbage_fec_reset(); platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); - mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data); + imx51_add_imx_i2c(0, &babbage_i2c_data); + imx51_add_imx_i2c(1, &babbage_i2c_data); mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); if (otg_mode_host) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h new file mode 100644 index 000000000000..a3cc3834c9fe --- /dev/null +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2010 Pengutronix + * Uwe Kleine-Koenig + * + * This program is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License version 2 as published by the + * Free Software Foundation. + */ +#include +#include + +extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; +#define imx51_add_imx_i2c(id, pdata) \ + imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 1920ff4963b2..70b76d16391c 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -93,44 +93,6 @@ struct platform_device mxc_fec_device = { .resource = mxc_fec_resources, }; -static struct resource mxc_i2c0_resources[] = { - { - .start = MX51_I2C1_BASE_ADDR, - .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_I2C1, - .end = MX51_MXC_INT_I2C1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c0_resources), - .resource = mxc_i2c0_resources, -}; - -static struct resource mxc_i2c1_resources[] = { - { - .start = MX51_I2C2_BASE_ADDR, - .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_I2C2, - .end = MX51_MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c1_resources), - .resource = mxc_i2c1_resources, -}; - static struct resource mxc_hsi2c_resources[] = { { .start = MX51_HSI2C_DMA_BASE_ADDR, diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index e509cfaad1d4..5c2918fcec0d 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -6,7 +6,5 @@ extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbdr_udc_device; extern struct platform_device mxc_wdt; -extern struct platform_device mxc_i2c_device0; -extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_hsi2c_device; extern struct platform_device mxc_keypad_device; diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c index ab9670b96c8a..ca988d40a3d7 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c +++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c @@ -68,6 +68,15 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { }; #endif /* ifdef CONFIG_ARCH_MX35 */ +#ifdef CONFIG_ARCH_MX51 +const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { +#define imx51_imx_i2c_data_entry(_id, _hwid) \ + imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_i2c_data_entry(0, 1), + imx51_imx_i2c_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + struct platform_device *__init imx_add_imx_i2c( const struct imx_imx_i2c_data *data, const struct imxi2c_platform_data *pdata) -- cgit v1.2.3 From 77a406da5a5b76445a816d5f043fc9aef4026ff1 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 25 Aug 2010 12:19:50 +0200 Subject: ARM: imx: fix name of macros to add imx-i2c devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a follow up to c698715 (ARM: imx: dynamically register imx-i2c devices (imx27)) 2b92084 (ARM: imx: dynamically register imx-i2c devices (imx21)) 6348e6b (ARM: imx: dynamically register imx-i2c devices (imx1)) Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/devices-imx1.h | 2 +- arch/arm/mach-imx/devices-imx21.h | 2 +- arch/arm/mach-imx/devices-imx27.h | 2 -- arch/arm/mach-imx/mach-cpuimx27.c | 2 +- arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 4 ++-- arch/arm/mach-imx/mach-mx1ads.c | 2 +- arch/arm/mach-imx/mach-mx27ads.c | 2 +- arch/arm/mach-imx/mach-mxt_td60.c | 4 ++-- arch/arm/mach-imx/mach-pca100.c | 2 +- arch/arm/mach-imx/mach-pcm038.c | 2 +- 10 files changed, 11 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h index 6cf08640dae9..81979486218e 100644 --- a/arch/arm/mach-imx/devices-imx1.h +++ b/arch/arm/mach-imx/devices-imx1.h @@ -10,7 +10,7 @@ #include extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; -#define imx1_add_i2c_imx(pdata) \ +#define imx1_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst; diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index d3d2b2669b96..4795d70314db 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -10,7 +10,7 @@ #include extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; -#define imx21_add_i2c_imx(pdata) \ +#define imx21_add_imx_i2c(pdata) \ imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 193dfb55023b..176552199abc 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -12,8 +12,6 @@ extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; #define imx27_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) -#define imx27_add_i2c_imx0(pdata) imx27_add_imx_i2c(0, pdata) -#define imx27_add_i2c_imx1(pdata) imx27_add_imx_i2c(1, pdata) extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; #define imx27_add_imx_ssi(id, pdata) \ diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index 339150ab0ea5..f00ddd9829b5 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -259,7 +259,7 @@ static void __init eukrea_cpuimx27_init(void) i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); - imx27_add_i2c_imx1(&cpuimx27_i2c1_data); + imx27_add_imx_i2c(1, &cpuimx27_i2c1_data); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 6dad632b83d6..7b3eed043ef1 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -236,8 +236,8 @@ static void __init visstrim_m10_board_init(void) i2c_register_board_info(0, visstrim_m10_i2c_devices, ARRAY_SIZE(visstrim_m10_i2c_devices)); - imx27_add_i2c_imx0(&visstrim_m10_i2c_data); - imx27_add_i2c_imx1(&visstrim_m10_i2c_data); + imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); + imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 77a760cfadc0..6e2f24952f1b 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -131,7 +131,7 @@ static void __init mx1ads_init(void) i2c_register_board_info(0, mx1ads_i2c_devices, ARRAY_SIZE(mx1ads_i2c_devices)); - imx1_add_i2c_imx(&mx1ads_i2c_data); + imx1_add_imx_i2c(&mx1ads_i2c_data); } static void __init mx1ads_timer_init(void) diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 9c77da98a10e..6be6033c876d 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -308,7 +308,7 @@ static void __init mx27ads_board_init(void) /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, mx27ads_i2c_devices, ARRAY_SIZE(mx27ads_i2c_devices)); - imx27_add_i2c_imx1(&mx27ads_i2c1_data); + imx27_add_imx_i2c(1, &mx27ads_i2c1_data); mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index a3a1e452d4c5..d878bb99be7e 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -255,8 +255,8 @@ static void __init mxt_td60_board_init(void) i2c_register_board_info(1, mxt_td60_i2c2_devices, ARRAY_SIZE(mxt_td60_i2c2_devices)); - imx27_add_i2c_imx0(&mxt_td60_i2c0_data); - imx27_add_i2c_imx1(&mxt_td60_i2c1_data); + imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); + imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 93e0d66e37dc..cccf521de6b1 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -400,7 +400,7 @@ static void __init pca100_init(void) i2c_register_board_info(1, pca100_i2c_devices, ARRAY_SIZE(pca100_i2c_devices)); - imx27_add_i2c_imx1(&pca100_i2c1_data); + imx27_add_imx_i2c(1, &pca100_i2c1_data); #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 9212e8f37001..641f9bb08b26 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -309,7 +309,7 @@ static void __init pcm038_init(void) i2c_register_board_info(1, pcm038_i2c_devices, ARRAY_SIZE(pcm038_i2c_devices)); - imx27_add_i2c_imx1(&pcm038_i2c1_data); + imx27_add_imx_i2c(1, &pcm038_i2c1_data); /* PE18 for user-LED D40 */ mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); -- cgit v1.2.3 From ab5605037c119f1bde0f01786ede16d0ea5dcd8a Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 9 Sep 2010 21:02:02 +0200 Subject: ARM: imx: use platform ids for spi_imx devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver recently learned to handle platform ids. Make use of this new feature. The up side is that the driver needs less knowledge about the spi interfaces used on different SoCs. Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clock-imx1.c | 2 +- arch/arm/mach-imx/clock-imx21.c | 6 +++--- arch/arm/mach-imx/clock-imx27.c | 6 +++--- arch/arm/mach-mx25/clock.c | 6 +++--- arch/arm/mach-mx3/clock-imx31.c | 6 +++--- arch/arm/mach-mx3/clock-imx35.c | 4 ++-- arch/arm/plat-mxc/devices/platform-spi_imx.c | 3 ++- arch/arm/plat-mxc/include/mach/devices-common.h | 1 + 8 files changed, 18 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c index c05096c38301..daca30b2d5b1 100644 --- a/arch/arm/mach-imx/clock-imx1.c +++ b/arch/arm/mach-imx/clock-imx1.c @@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = { _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk) _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) - _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk) + _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk) _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) _REGISTER_CLOCK(NULL, "mshc", mshc_clk) diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c index bb419ef4d133..cf15ea516a72 100644 --- a/arch/arm/mach-imx/clock-imx21.c +++ b/arch/arm/mach-imx/clock-imx21.c @@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) - _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0]) - _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1]) - _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) + _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0]) + _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1]) + _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2]) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0]) diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 5a1aa15c8a16..07bf315bc078 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) - _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) - _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) - _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) + _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk) + _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk) + _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk) _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 40c7cc41cee3..039464a8dacc 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -261,9 +261,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) - _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) - _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) - _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) + _REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk) + _REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk) + _REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk) _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk) _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c index 9a9eb6de6127..18e98f1d4de0 100644 --- a/arch/arm/mach-mx3/clock-imx31.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "emi", emi_clk) - _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) - _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) - _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) + _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk) + _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk) + _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) _REGISTER_CLOCK(NULL, "gpt", gpt_clk) _REGISTER_CLOCK(NULL, "pwm", pwm_clk) _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index f11ef990120c..708c2b36cf06 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -451,8 +451,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) - _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) - _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) + _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk) + _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk) _REGISTER_CLOCK(NULL, "ect", ect_clk) _REGISTER_CLOCK(NULL, "edio", edio_clk) _REGISTER_CLOCK(NULL, "emi", emi_clk) diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index 412a81f24101..bd30d4b2b2f9 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -11,6 +11,7 @@ #define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \ { \ + .devid = _devid, \ .id = _id, \ .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \ .iosize = _size, \ @@ -83,6 +84,6 @@ struct platform_device *__init imx_add_spi_imx( }, }; - return imx_add_platform_device("spi_imx", data->id, + return imx_add_platform_device(data->devid, data->id, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 490fe7c3ed5f..32b8f3674cc9 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -77,6 +77,7 @@ struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, #include struct imx_spi_imx_data { + const char *devid; int id; resource_size_t iobase; resource_size_t iosize; -- cgit v1.2.3 From 9f0c11ee67d9a5ab76c27d2f9dbdd9ee85fbce10 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Sep 2010 16:57:07 +0200 Subject: ARM: mx5: add spi_imx device registration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/devices-imx51.h | 8 ++++++++ arch/arm/plat-mxc/devices/platform-spi_imx.c | 12 ++++++++++++ 2 files changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index a3cc3834c9fe..09d2b5c8b4f5 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -12,3 +12,11 @@ extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; #define imx51_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) + +extern const struct imx_spi_imx_data imx51_cspi_data __initconst; +#define imx51_add_cspi(pdata) \ + imx_add_spi_imx(&imx51_cspi_data, pdata) + +extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst; +#define imx51_add_ecspi(id, pdata) \ + imx_add_spi_imx(&imx51_ecspi_data[id], pdata) diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c index bd30d4b2b2f9..e48340ec331e 100644 --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c @@ -68,6 +68,18 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { }; #endif /* ifdef CONFIG_ARCH_MX35 */ +#ifdef CONFIG_ARCH_MX51 +const struct imx_spi_imx_data imx51_cspi_data __initconst = + imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); + +const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { +#define imx51_ecspi_data_entry(_id, _hwid) \ + imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) + imx51_ecspi_data_entry(0, 1), + imx51_ecspi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + struct platform_device *__init imx_add_spi_imx( const struct imx_spi_imx_data *data, const struct spi_imx_master *pdata) -- cgit v1.2.3 From 79901478e0a2854c4becbb2e77f176bd7fa37caa Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Sep 2010 16:58:42 +0200 Subject: ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 57c10a9926cc..fe658bf5b490 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -41,34 +41,36 @@ static struct clk usboh3_clk; #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ -static int _clk_ccgr_enable(struct clk *clk) +static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) { - u32 reg; + u32 reg = __raw_readl(clk->enable_reg); + + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= mode << clk->enable_shift; - reg = __raw_readl(clk->enable_reg); - reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; __raw_writel(reg, clk->enable_reg); +} +static int _clk_ccgr_enable(struct clk *clk) +{ + _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON); return 0; } static void _clk_ccgr_disable(struct clk *clk) { - u32 reg; - reg = __raw_readl(clk->enable_reg); - reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); - __raw_writel(reg, clk->enable_reg); + _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF); +} +static int _clk_ccgr_enable_inrun(struct clk *clk) +{ + _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); + return 0; } static void _clk_ccgr_disable_inwait(struct clk *clk) { - u32 reg; - - reg = __raw_readl(clk->enable_reg); - reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); - reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; - __raw_writel(reg, clk->enable_reg); + _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); } /* -- cgit v1.2.3 From 74d99f395901502747a44a1379f3b4fdb638dafa Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 10 Sep 2010 17:01:26 +0200 Subject: ARM: mx5/clock-mx51: new macro that defines a clk with all members MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index fe658bf5b490..0e396981c27c 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -764,21 +764,21 @@ static struct clk kpp_clk = { .id = 0, }; -#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ - static struct clk name = { \ - .id = i, \ - .enable_reg = er, \ - .enable_shift = es, \ - .get_rate = gr, \ - .set_rate = sr, \ - .enable = _clk_ccgr_enable, \ - .disable = _clk_ccgr_disable, \ - .parent = p, \ - .secondary = s, \ +#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ + static struct clk name = { \ + .id = i, \ + .enable_reg = er, \ + .enable_shift = es, \ + .get_rate = gr, \ + .set_rate = sr, \ + .enable = e, \ + .disable = d, \ + .parent = p, \ + .secondary = s, \ } -/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, - get_rate, set_rate, parent, secondary); */ +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ + DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s) /* Shared peripheral bus arbiter */ DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, -- cgit v1.2.3 From 8d83db81affd71af0fb6f054ab552d16a7cb805b Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 2 Sep 2010 15:52:00 +0800 Subject: ARM: mx5/clock-mx51: add spi clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51.c | 57 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 0e396981c27c..68aef2d58484 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -764,6 +764,42 @@ static struct clk kpp_clk = { .id = 0, }; +/* eCSPI */ +static unsigned long clk_ecspi_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CSCDR2); + + pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >> + MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + + return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), + (pred + 1) * (podf + 1)); +} + +static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ecspi_main_clk = { + .parent = &pll3_sw_clk, + .get_rate = clk_ecspi_get_rate, + .set_parent = clk_ecspi_set_parent, +}; + #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ static struct clk name = { \ .id = i, \ @@ -816,6 +852,24 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, NULL, NULL, &ipg_clk, NULL); +/* eCSPI */ +DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, + &ipg_clk, &spba_clk); +DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET, + NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk); +DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET, + NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, + &ipg_clk, &aips_tz2_clk); +DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET, + NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk); + +/* CSPI */ +DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_clk, &aips_tz2_clk); +DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET, + NULL, NULL, &ipg_clk, &cspi_ipg_clk); + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -839,6 +893,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) + _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) + _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) + _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) }; static void clk_tree_init(void) -- cgit v1.2.3 From eaa4fd0b4022bd4d2ff0c38b3cc936ee5a441711 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 2 Sep 2010 15:52:02 +0800 Subject: ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the imx51_3ds board, eCSPI2 is connected to a SPI NOR flash, now add iomux definitions for those used pins. Signed-off-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 0d77be3a2374..d0ef881c3776 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -45,6 +45,8 @@ typedef enum iomux_config { PAD_CTL_PKE | PAD_CTL_HYS) #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ PAD_CTL_SRE_FAST) +#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) #define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) @@ -139,8 +141,10 @@ typedef enum iomux_config { #define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) @@ -162,6 +166,7 @@ typedef enum iomux_config { #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) #define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -- cgit v1.2.3 From 988916e1a9af1994d510138e7201acf7b425fb46 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 2 Sep 2010 15:52:03 +0800 Subject: ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/Kconfig | 1 + arch/arm/mach-mx5/board-mx51_3ds.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index e57caefb1f28..2735314a78e0 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -18,6 +18,7 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" + select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD help Include support for MX51PDK (3DS) platform. This includes specific diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index f95c2fd94667..c9c41282c996 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -24,9 +24,11 @@ #include #include +#include "devices-imx51.h" #include "devices.h" #define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) +#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) static struct pad_desc mx51_3ds_pads[] = { /* UART1 */ @@ -61,6 +63,12 @@ static struct pad_desc mx51_3ds_pads[] = { MX51_PAD_KEY_COL3__KEY_COL3, MX51_PAD_KEY_COL4__KEY_COL4, MX51_PAD_KEY_COL5__KEY_COL5, + + /* eCSPI2 */ + MX51_PAD_NANDF_RB2__ECSPI2_SCLK, + MX51_PAD_NANDF_RB3__ECSPI2_MISO, + MX51_PAD_NANDF_D15__ECSPI2_MOSI, + MX51_PAD_NANDF_D12__GPIO_3_28, }; /* Serial ports */ @@ -127,6 +135,16 @@ static inline void mxc_init_keypad(void) } #endif +static int mx51_3ds_spi2_cs[] = { + MXC_SPI_CS(0), + MX51_3DS_ECSPI2_CS, +}; + +static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = { + .chipselect = mx51_3ds_spi2_cs, + .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs), +}; + /* * Board specific initialization. */ @@ -136,6 +154,8 @@ static void __init mxc_board_init(void) ARRAY_SIZE(mx51_3ds_pads)); mxc_init_imx_uart(); + imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); + if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) printk(KERN_WARNING "Init of the debugboard failed, all " "devices on the board are unusable.\n"); -- cgit v1.2.3 From 8005cf2eb39786a0a3592fe178603ee1caccc5eb Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 2 Sep 2010 15:52:04 +0800 Subject: ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A 2M bytes SPI NOR flash(sst25vf016b) is soldered on the mx51_3ds board. So add the corresponding device for it. Signed-off-by: Jason Wang Acked-by: Grant Likely Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/board-mx51_3ds.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index c9c41282c996..b9d3331ba308 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -145,6 +146,16 @@ static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = { .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs), }; +static struct spi_board_info mx51_3ds_spi_nor_device[] = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 1, + .mode = SPI_MODE_0, + .platform_data = NULL,}, +}; + /* * Board specific initialization. */ @@ -155,6 +166,8 @@ static void __init mxc_board_init(void) mxc_init_imx_uart(); imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); + spi_register_board_info(mx51_3ds_spi_nor_device, + ARRAY_SIZE(mx51_3ds_spi_nor_device)); if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) printk(KERN_WARNING "Init of the debugboard failed, all " -- cgit v1.2.3 From 8efd9271fae0a735db5660330e14022031c88e77 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 20 Aug 2010 10:45:11 +0200 Subject: ARM: mx5/iomux-mx51: Add SPI controller pads MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index d0ef881c3776..2bd09feb19ca 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -218,11 +218,17 @@ typedef enum iomux_config { #define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) #define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) -- cgit v1.2.3 From 2e35bab5fd8b19a8eabbb4c57b3ddd305057eed4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 20 Aug 2010 18:35:51 +0200 Subject: ARM: mx5/iomux-mx51: Add aud3 primary function defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 2bd09feb19ca..197cd1ff7c60 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -214,9 +214,13 @@ typedef enum iomux_config { #define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) -- cgit v1.2.3 From f781bc8aa44c8676ad84b69fc4553e8f035c6e89 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 24 Aug 2010 14:49:09 +0200 Subject: ARM: mx5/iomux-mx51: Fix input path of some pins in gpio mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx51.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 197cd1ff7c60..633650d3f814 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -275,14 +275,14 @@ typedef enum iomux_config { #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) #define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) +#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) +#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) -- cgit v1.2.3 From 2b82e64d787f9d1a5d304da137c2b1bdbe3b2d9d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 3 Aug 2010 11:59:07 +0200 Subject: ARM: mx5: Add Nand clock support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51.c | 98 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 68aef2d58484..0cef8c4f84ba 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -573,6 +573,64 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) return 0; } +#define clk_nfc_set_parent NULL + +static unsigned long clk_nfc_get_rate(struct clk *clk) +{ + unsigned long rate; + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> + MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; + rate = clk_get_rate(clk->parent) / div; + WARN_ON(rate == 0); + return rate; +} + +static unsigned long clk_nfc_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + unsigned long parent_rate = clk_get_rate(clk->parent); + + if (!rate) + return -EINVAL; + + div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + if (div > 8) + return -EINVAL; + + return parent_rate / div; + +} + +static int clk_nfc_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk_get_rate(clk->parent) / rate; + if (div == 0) + div++; + if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & + MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){ + } + + return 0; +} + static unsigned long clk_usboh3_get_rate(struct clk *clk) { u32 reg, prediv, podf; @@ -622,6 +680,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) return ckih2_reference; } +static unsigned long clk_emi_slow_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> + MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + /* External high frequency clock */ static struct clk ckih_clk = { .get_rate = get_high_reference_clock_rate, @@ -764,6 +833,30 @@ static struct clk kpp_clk = { .id = 0, }; +static struct clk emi_slow_clk = { + .parent = &pll2_sw_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, + .get_rate = clk_emi_slow_get_rate, +}; + +#define DEFINE_CLOCK1(name, i, er, es, pfx, p, s) \ + static struct clk name = { \ + .id = i, \ + .enable_reg = er, \ + .enable_shift = es, \ + .get_rate = pfx##_get_rate, \ + .set_rate = pfx##_set_rate, \ + .round_rate = pfx##_round_rate, \ + .set_parent = pfx##_set_parent, \ + .enable = _clk_ccgr_enable, \ + .disable = _clk_ccgr_disable, \ + .parent = p, \ + .secondary = s, \ + } + /* eCSPI */ static unsigned long clk_ecspi_get_rate(struct clk *clk) { @@ -852,6 +945,10 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, NULL, NULL, &ipg_clk, NULL); +/* NFC */ +DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, + clk_nfc, &emi_slow_clk, NULL); + /* eCSPI */ DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, @@ -893,6 +990,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) + _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) -- cgit v1.2.3 From 04b73b1571c26d491c62c42cb06b96bf482fa7a2 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 11 Aug 2010 22:23:06 +0200 Subject: ARM: mx51: dynamically register imx-uart devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/Kconfig | 3 ++ arch/arm/mach-mx5/board-cpuimx51.c | 6 +-- arch/arm/mach-mx5/board-mx51_3ds.c | 9 ++--- arch/arm/mach-mx5/board-mx51_babbage.c | 10 ++--- arch/arm/mach-mx5/devices-imx51.h | 4 ++ arch/arm/mach-mx5/devices.c | 57 --------------------------- arch/arm/mach-mx5/devices.h | 3 -- arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c | 7 ++-- arch/arm/plat-mxc/devices/platform-imx-uart.c | 10 +++++ arch/arm/plat-mxc/include/mach/mx51.h | 6 +-- 10 files changed, 36 insertions(+), 79 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 2735314a78e0..65bf34e1a4f6 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -11,6 +11,7 @@ comment "MX5 platforms:" config MACH_MX51_BABBAGE bool "Support MX51 BABBAGE platforms" select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART help Include support for MX51 Babbage platform, also known as MX51EVK in u-boot. This includes specific configurations for the board and its @@ -18,6 +19,7 @@ config MACH_MX51_BABBAGE config MACH_MX51_3DS bool "Support MX51PDK (3DS)" + select IMX_HAVE_PLATFORM_IMX_UART select IMX_HAVE_PLATFORM_SPI_IMX select MXC_DEBUG_BOARD help @@ -27,6 +29,7 @@ config MACH_MX51_3DS config MACH_EUKREA_CPUIMX51 bool "Support Eukrea CPUIMX51 module" select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_IMX_UART help Include support for Eukrea CPUIMX51 platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c index d52f2527f6bf..a6c09c7ff728 100644 --- a/arch/arm/mach-mx5/board-cpuimx51.c +++ b/arch/arm/mach-mx5/board-cpuimx51.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -38,6 +37,7 @@ #include #include +#include "devices-imx51.h" #include "devices.h" #define CPUIMX51_USBH1_STP (0*32 + 27) @@ -147,7 +147,7 @@ static struct pad_desc eukrea_cpuimx51_pads[] = { MX51_PAD_USBH1_STP__USBH1_STP, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -239,7 +239,7 @@ static void __init eukrea_cpuimx51_init(void) mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); + imx51_add_imx_uart(0, &uart_pdata); gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); gpio_direction_input(CPUIMX51_QUARTA_GPIO); gpio_free(CPUIMX51_QUARTA_GPIO); diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c index b9d3331ba308..ed08a2352a1a 100644 --- a/arch/arm/mach-mx5/board-mx51_3ds.c +++ b/arch/arm/mach-mx5/board-mx51_3ds.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include "devices-imx51.h" @@ -74,15 +73,15 @@ static struct pad_desc mx51_3ds_pads[] = { /* Serial ports */ #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static inline void mxc_init_imx_uart(void) { - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_imx_uart(1, &uart_pdata); + imx51_add_imx_uart(2, &uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index 3f3075d7768f..7c0b6618a164 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -21,7 +21,6 @@ #include #include -#include #include #include @@ -31,6 +30,7 @@ #include #include +#include "devices-imx51.h" #include "devices.h" #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ @@ -120,15 +120,15 @@ static struct pad_desc mx51babbage_pads[] = { /* Serial ports */ #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; static inline void mxc_init_imx_uart(void) { - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device1, &uart_pdata); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx51_add_imx_uart(0, &uart_pdata); + imx51_add_imx_uart(1, &uart_pdata); + imx51_add_imx_uart(2, &uart_pdata); } #else /* !SERIAL_IMX */ static inline void mxc_init_imx_uart(void) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 09d2b5c8b4f5..8235b8c6729b 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -13,6 +13,10 @@ extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; #define imx51_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) +extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; +#define imx51_add_imx_uart(id, pdata) \ + imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) + extern const struct imx_spi_imx_data imx51_cspi_data __initconst; #define imx51_add_cspi(pdata) \ imx_add_spi_imx(&imx51_cspi_data, pdata) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 70b76d16391c..5f40082d9e61 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -17,63 +17,6 @@ #include #include -static struct resource uart0[] = { - { - .start = MX51_UART1_BASE_ADDR, - .end = MX51_UART1_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_UART1, - .end = MX51_MXC_INT_UART1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device0 = { - .name = "imx-uart", - .id = 0, - .resource = uart0, - .num_resources = ARRAY_SIZE(uart0), -}; - -static struct resource uart1[] = { - { - .start = MX51_UART2_BASE_ADDR, - .end = MX51_UART2_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_UART2, - .end = MX51_MXC_INT_UART2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device1 = { - .name = "imx-uart", - .id = 1, - .resource = uart1, - .num_resources = ARRAY_SIZE(uart1), -}; - -static struct resource uart2[] = { - { - .start = MX51_UART3_BASE_ADDR, - .end = MX51_UART3_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MX51_MXC_INT_UART3, - .end = MX51_MXC_INT_UART3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mxc_uart_device2 = { - .name = "imx-uart", - .id = 2, - .resource = uart2, - .num_resources = ARRAY_SIZE(uart2), -}; - static struct resource mxc_fec_resources[] = { { .start = MX51_MXC_FEC_BASE_ADDR, diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index 5c2918fcec0d..67a6d6910530 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -1,6 +1,3 @@ -extern struct platform_device mxc_uart_device0; -extern struct platform_device mxc_uart_device1; -extern struct platform_device mxc_uart_device2; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index ffa93d1d6ef8..d0e417ce2c08 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c @@ -30,6 +30,7 @@ #include +#include "devices-imx51.h" #include "devices.h" #define MBIMX51_TSC2007_GPIO (2*32 + 30) @@ -114,7 +115,7 @@ static struct pad_desc mbimx51_pads[] = { MX51_PAD_KEY_COL3__KEY_COL3, }; -static struct imxuart_platform_data uart_pdata = { +static const struct imxuart_platform_data uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -172,8 +173,8 @@ void __init eukrea_mbimx51_baseboard_init(void) mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, ARRAY_SIZE(mbimx51_pads)); - mxc_register_device(&mxc_uart_device1, NULL); - mxc_register_device(&mxc_uart_device2, &uart_pdata); + imx51_add_imx_uart(1, NULL); + imx51_add_imx_uart(2, &uart_pdata); gpio_request(MBIMX51_LED0, "LED0"); gpio_direction_output(MBIMX51_LED0, 1); diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c index af7fabba4e71..2039640adf27 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-uart.c +++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c @@ -94,6 +94,16 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { }; #endif /* ifdef CONFIG_ARCH_MX35 */ +#ifdef CONFIG_ARCH_MX51 +const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { +#define imx51_imx_uart_data_entry(_id, _hwid) \ + imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_uart_data_entry(0, 1), + imx51_imx_uart_data_entry(1, 2), + imx51_imx_uart_data_entry(2, 3), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + struct platform_device *__init imx_add_imx_uart_3irq( const struct imx_imx_uart_3irq_data *data, const struct imxuart_platform_data *pdata) diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index b919235768a0..b7359d7d54e2 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -310,9 +310,9 @@ #define MX51_MXC_INT_SLIM_B 28 #define MX51_MXC_INT_SSI1 29 #define MX51_MXC_INT_SSI2 30 -#define MX51_MXC_INT_UART1 31 -#define MX51_MXC_INT_UART2 32 -#define MX51_MXC_INT_UART3 33 +#define MX51_INT_UART1 31 +#define MX51_INT_UART2 32 +#define MX51_INT_UART3 33 #define MX51_MXC_INT_RESV34 34 #define MX51_MXC_INT_RESV35 35 #define MX51_INT_ECSPI1 36 -- cgit v1.2.3 From b86186610f639344a7db54da89267f645afc30ec Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 20 Aug 2010 16:43:54 +0200 Subject: ARM: mx51: add imx-ssi devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51.c | 12 ++++++++++++ arch/arm/mach-mx5/devices-imx51.h | 4 ++++ arch/arm/plat-mxc/devices/platform-imx-ssi.c | 9 +++++++++ arch/arm/plat-mxc/include/mach/mx51.h | 20 ++++++++++---------- 4 files changed, 35 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 0cef8c4f84ba..5c7901180c8e 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -949,6 +949,16 @@ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, clk_nfc, &emi_slow_clk, NULL); +/* SSI */ +DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk); +DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, + NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, + NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); + /* eCSPI */ DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, @@ -991,6 +1001,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 8235b8c6729b..782b45bd916b 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -13,6 +13,10 @@ extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; #define imx51_add_imx_i2c(id, pdata) \ imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) +extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst; +#define imx51_add_imx_ssi(id, pdata) \ + imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) + extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; #define imx51_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index 1535bc9f0601..38a7a0b8f2f1 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c @@ -66,6 +66,15 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { }; #endif /* ifdef CONFIG_ARCH_MX35 */ +#ifdef CONFIG_ARCH_MX51 +const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { +#define imx51_imx_ssi_data_entry(_id, _hwid) \ + imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) + imx51_imx_ssi_data_entry(0, 1), + imx51_imx_ssi_data_entry(1, 2), +}; +#endif /* ifdef CONFIG_ARCH_MX51 */ + struct platform_device *__init imx_add_imx_ssi( const struct imx_imx_ssi_data *data, const struct imx_ssi_platform_data *pdata) diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index b7359d7d54e2..b47d65b1c112 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -248,14 +248,14 @@ #define MX51_DMA_REQ_UART1_TX 19 #define MX51_DMA_REQ_SDHC1 20 #define MX51_DMA_REQ_SDHC2 21 -#define MX51_DMA_REQ_SSI2_RX2 22 -#define MX51_DMA_REQ_SSI2_TX2 23 -#define MX51_DMA_REQ_SSI2_RX1 24 -#define MX51_DMA_REQ_SSI2_TX1 25 -#define MX51_DMA_REQ_SSI1_RX2 26 -#define MX51_DMA_REQ_SSI1_TX2 27 -#define MX51_DMA_REQ_SSI1_RX1 28 -#define MX51_DMA_REQ_SSI1_TX1 29 +#define MX51_DMA_REQ_SSI2_RX1 22 +#define MX51_DMA_REQ_SSI2_TX1 23 +#define MX51_DMA_REQ_SSI2_RX0 24 +#define MX51_DMA_REQ_SSI2_TX0 25 +#define MX51_DMA_REQ_SSI1_RX1 26 +#define MX51_DMA_REQ_SSI1_TX1 27 +#define MX51_DMA_REQ_SSI1_RX0 28 +#define MX51_DMA_REQ_SSI1_TX0 29 #define MX51_DMA_REQ_EMI_RD 30 #define MX51_DMA_REQ_CTI2_0 31 #define MX51_DMA_REQ_EMI_WR 32 @@ -308,8 +308,8 @@ #define MX51_MXC_INT_RTIC 26 #define MX51_MXC_INT_CSU 27 #define MX51_MXC_INT_SLIM_B 28 -#define MX51_MXC_INT_SSI1 29 -#define MX51_MXC_INT_SSI2 30 +#define MX51_INT_SSI1 29 +#define MX51_INT_SSI2 30 #define MX51_INT_UART1 31 #define MX51_INT_UART2 32 #define MX51_INT_UART3 33 -- cgit v1.2.3 From 40e2eda92178f58fd7da2866d3f346dcd2baafed Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 20 Aug 2010 16:44:34 +0200 Subject: ARM: mx51: Add audmux support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/Kconfig | 1 + arch/arm/plat-mxc/audmux-v2.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 65bf34e1a4f6..3a4c3b32a6e7 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -5,6 +5,7 @@ config ARCH_MX51 default y select MXC_TZIC select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 comment "MX5 platforms:" diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index f9e7cdbd0005..62920490c0d6 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -186,7 +186,13 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); static int mxc_audmux_v2_init(void) { int ret; - +#if defined(CONFIG_ARCH_MX5) + if (cpu_is_mx51()) { + audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR); + ret = 0; + return ret; + } +#endif #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); -- cgit v1.2.3 From 00b57bf9786ca701508333112c8917d1e0860129 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 23 Aug 2010 11:25:52 +0200 Subject: ARM: imx: reorganize nand registration to use a struct MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Addiontionally make the interrupt #defines match the base address defines MX.._NFC_BASE_ADDR. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/devices-imx21.h | 3 +- arch/arm/mach-imx/devices-imx27.h | 3 +- arch/arm/mach-mx25/devices-imx25.h | 3 +- arch/arm/mach-mx3/devices-imx31.h | 3 +- arch/arm/mach-mx3/devices-imx35.h | 3 +- arch/arm/plat-mxc/devices/platform-mxc_nand.c | 64 ++++++++++++++++--------- arch/arm/plat-mxc/include/mach/devices-common.h | 12 +++-- arch/arm/plat-mxc/include/mach/mx21.h | 2 +- arch/arm/plat-mxc/include/mach/mx25.h | 2 +- arch/arm/plat-mxc/include/mach/mx27.h | 2 +- arch/arm/plat-mxc/include/mach/mx31.h | 2 +- arch/arm/plat-mxc/include/mach/mx35.h | 2 +- 12 files changed, 64 insertions(+), 37 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 4795d70314db..d189039749b0 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h @@ -25,8 +25,9 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst; #define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) #define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) +extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; #define imx21_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) + imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; #define imx21_add_cspi(id, pdata) \ diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 176552199abc..e11606b4d31c 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h @@ -27,8 +27,9 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst; #define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) #define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) +extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; #define imx27_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) + imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; #define imx27_add_cspi(id, pdata) \ diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h index 1dd95721d9f5..eab19c0a9429 100644 --- a/arch/arm/mach-mx25/devices-imx25.h +++ b/arch/arm/mach-mx25/devices-imx25.h @@ -34,8 +34,9 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst; #define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) #define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) +extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; #define imx25_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) + imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst; #define imx25_add_spi_imx(id, pdata) \ diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h index eea425ff074e..de9598590eba 100644 --- a/arch/arm/mach-mx3/devices-imx31.h +++ b/arch/arm/mach-mx3/devices-imx31.h @@ -29,8 +29,9 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst; #define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) #define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) +extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; #define imx31_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) + imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; #define imx31_add_cspi(id, pdata) \ diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h index f187d3552738..56404de907f9 100644 --- a/arch/arm/mach-mx3/devices-imx35.h +++ b/arch/arm/mach-mx3/devices-imx35.h @@ -32,8 +32,9 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst; #define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) #define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) +extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; #define imx35_add_mxc_nand(pdata) \ - imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) + imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; #define imx35_add_cspi(id, pdata) \ diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 1c286418d123..6d3a4785f95b 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -7,38 +7,56 @@ * Free Software Foundation. */ #include +#include #include -static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, - int irq, const struct mxc_nand_platform_data *pdata, - resource_size_t iosize) +#define imx_mxc_nand_data_entry_single(soc, _size) \ + { \ + .iobase = soc ## _NFC_BASE_ADDR, \ + .iosize = _size, \ + .irq = soc ## _INT_NFC \ + } + +#ifdef CONFIG_SOC_IMX21 +const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX21, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX21 */ + +#ifdef CONFIG_ARCH_MX25 +const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX25, SZ_8K); +#endif /* ifdef CONFIG_ARCH_MX25 */ + +#ifdef CONFIG_SOC_IMX27 +const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX27, SZ_4K); +#endif /* ifdef CONFIG_SOC_IMX27 */ + +#ifdef CONFIG_ARCH_MX31 +const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX31, SZ_4K); +#endif + +#ifdef CONFIG_ARCH_MX35 +const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = + imx_mxc_nand_data_entry_single(MX35, SZ_8K); +#endif + +struct platform_device *__init imx_add_mxc_nand( + const struct imx_mxc_nand_data *data, + const struct mxc_nand_platform_data *pdata) { - static int id = 0; - struct resource res[] = { { - .start = iobase, - .end = iobase + iosize - 1, + .start = data->iobase, + .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, }, { - .start = irq, - .end = irq, + .start = data->irq, + .end = data->irq, .flags = IORESOURCE_IRQ, }, }; - - return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), + return imx_add_platform_device("mxc_nand", 0, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); } - -struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, - int irq, const struct mxc_nand_platform_data *pdata) -{ - return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K); -} - -struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, - int irq, const struct mxc_nand_platform_data *pdata) -{ - return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K); -} diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 32b8f3674cc9..371336ee9d7f 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -70,10 +70,14 @@ struct platform_device *__init imx_add_imx_uart_1irq( const struct imxuart_platform_data *pdata); #include -struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, - int irq, const struct mxc_nand_platform_data *pdata); -struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, - int irq, const struct mxc_nand_platform_data *pdata); +struct imx_mxc_nand_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init imx_add_mxc_nand( + const struct imx_mxc_nand_data *data, + const struct mxc_nand_platform_data *pdata); #include struct imx_spi_imx_data { diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index ed98b9c9f389..8bc59720b6e4 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -120,7 +120,7 @@ #define MX21_INT_GPT1 26 #define MX21_INT_WDOG 27 #define MX21_INT_PCMCIA 28 -#define MX21_INT_NANDFC 29 +#define MX21_INT_NFC 29 #define MX21_INT_BMI 30 #define MX21_INT_CSI 31 #define MX21_INT_DMACH0 32 diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 8f809eb084df..a9e1095d7486 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -69,7 +69,7 @@ #define MX25_INT_KPP 24 #define MX25_INT_DRYICE 25 #define MX25_INT_UART2 32 -#define MX25_INT_NANDFC 33 +#define MX25_INT_NFC 33 #define MX25_INT_LCDC 39 #define MX25_INT_UART5 40 #define MX25_INT_CAN1 43 diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index a8ab2e02a8ca..2237ba2e5351 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs, #define MX27_INT_GPT1 26 #define MX27_INT_WDOG 27 #define MX27_INT_PCMCIA 28 -#define MX27_INT_NANDFC 29 +#define MX27_INT_NFC 29 #define MX27_INT_ATA 30 #define MX27_INT_CSI 31 #define MX27_INT_DMACH0 32 diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index eb8bbc7eedfa..03e2afabc9fc 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs, #define MX31_INT_POWER_FAIL 30 #define MX31_INT_CCM_DVFS 31 #define MX31_INT_UART2 32 -#define MX31_INT_NANDFC 33 +#define MX31_INT_NFC 33 #define MX31_INT_SDMA 34 #define MX31_INT_USB1 35 #define MX31_INT_USB2 36 diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 867b8c0ca105..9f0a1ee126ee 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -145,7 +145,7 @@ #define MX35_INT_GPT 29 #define MX35_INT_POWER_FAIL 30 #define MX35_INT_UART2 32 -#define MX35_INT_NANDFC 33 +#define MX35_INT_NFC 33 #define MX35_INT_SDMA 34 #define MX35_INT_USBHS 35 #define MX35_INT_USBOTG 37 -- cgit v1.2.3 From 63a7c6d7507ed6f4ea24a8ed008efa1bb22a2a97 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 3 Aug 2010 11:59:46 +0200 Subject: ARM: mx5: dynamically register mxc-nand device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/devices-imx51.h | 4 ++++ arch/arm/plat-mxc/devices/platform-mxc_nand.c | 23 ++++++++++++++++++++++- arch/arm/plat-mxc/include/mach/devices-common.h | 7 +++++++ arch/arm/plat-mxc/include/mach/mx51.h | 2 +- 4 files changed, 34 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h index 782b45bd916b..41d93c3d7d0b 100644 --- a/arch/arm/mach-mx5/devices-imx51.h +++ b/arch/arm/mach-mx5/devices-imx51.h @@ -21,6 +21,10 @@ extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; #define imx51_add_imx_uart(id, pdata) \ imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) +extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst; +#define imx51_add_mxc_nand(pdata) \ + imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) + extern const struct imx_spi_imx_data imx51_cspi_data __initconst; #define imx51_add_cspi(pdata) \ imx_add_spi_imx(&imx51_cspi_data, pdata) diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c index 6d3a4785f95b..3fdcc32e3d67 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c @@ -17,6 +17,15 @@ .irq = soc ## _INT_NFC \ } +#define imx_mxc_nandv3_data_entry_single(soc, _size) \ + { \ + .id = -1, \ + .iobase = soc ## _NFC_BASE_ADDR, \ + .iosize = _size, \ + .axibase = soc ## _NFC_AXI_BASE_ADDR, \ + .irq = soc ## _INT_NFC \ + } + #ifdef CONFIG_SOC_IMX21 const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX21, SZ_4K); @@ -42,12 +51,22 @@ const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = imx_mxc_nand_data_entry_single(MX35, SZ_8K); #endif +#ifdef CONFIG_ARCH_MX51 +const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = + imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); +#endif + struct platform_device *__init imx_add_mxc_nand( const struct imx_mxc_nand_data *data, const struct mxc_nand_platform_data *pdata) { + /* AXI has to come first, that's how the mxc_nand driver expect it */ struct resource res[] = { { + .start = data->axibase, + .end = data->axibase + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { .start = data->iobase, .end = data->iobase + data->iosize - 1, .flags = IORESOURCE_MEM, @@ -57,6 +76,8 @@ struct platform_device *__init imx_add_mxc_nand( .flags = IORESOURCE_IRQ, }, }; - return imx_add_platform_device("mxc_nand", 0, res, ARRAY_SIZE(res), + return imx_add_platform_device("mxc_nand", data->id, + res + !data->axibase, + ARRAY_SIZE(res) - !data->axibase, pdata, sizeof(*pdata)); } diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 371336ee9d7f..f87aa1ad6685 100644 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -71,8 +71,15 @@ struct platform_device *__init imx_add_imx_uart_1irq( #include struct imx_mxc_nand_data { + /* + * id is traditionally 0, but -1 is more appropriate. We use -1 for new + * machines but don't change existing devices as the nand device usually + * appears in the kernel command line to pass its partitioning. + */ + int id; resource_size_t iobase; resource_size_t iosize; + resource_size_t axibase; resource_size_t irq; }; struct platform_device *__init imx_add_mxc_nand( diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index b47d65b1c112..c99eeab6fe09 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -287,7 +287,7 @@ #define MX51_MXC_INT_RESV5 5 #define MX51_MXC_INT_SDMA 6 #define MX51_MXC_INT_IOMUX 7 -#define MX51_MXC_INT_NFC 8 +#define MX51_INT_NFC 8 #define MX51_MXC_INT_VPU 9 #define MX51_MXC_INT_IPU_ERR 10 #define MX51_MXC_INT_IPU_SYN 11 -- cgit v1.2.3 From 8f6e900a661881f9585d9b3a7173a44020c3c0b2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 25 Aug 2010 11:56:26 +0200 Subject: ARM: mx5: clock-imx51: make *ipg clocks secondary clocks of their corresponding peripheral clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently the uarts and timer only work because they are turned on by reset default. Make them secondary clocks of their corresponding peripheral clocks to make sure they are turned on when necessary. Also, register some clocks to get rid of compiler warnings Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-mx5/clock-mx51.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 5c7901180c8e..e6c17d78189c 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -914,24 +914,24 @@ DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, NULL, NULL, &ipg_clk, NULL); /* UART */ -DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, - NULL, NULL, &uart_root_clk, NULL); -DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, - NULL, NULL, &uart_root_clk, NULL); -DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, - NULL, NULL, &uart_root_clk, NULL); DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &ipg_clk, &aips_tz1_clk); DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, &ipg_clk, &aips_tz1_clk); DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, NULL, NULL, &ipg_clk, &spba_clk); +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, + NULL, NULL, &uart_root_clk, &uart1_ipg_clk); +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &uart_root_clk, &uart2_ipg_clk); +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, + NULL, NULL, &uart_root_clk, &uart3_ipg_clk); /* GPT */ -DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, - NULL, NULL, &ipg_clk, NULL); DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, NULL, NULL, &ipg_clk, NULL); +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_clk, &gpt_ipg_clk); /* I2C */ DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, @@ -1003,6 +1003,9 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) + _REGISTER_CLOCK(NULL, "ckih", ckih_clk) + _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) + _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk) _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) -- cgit v1.2.3 From 13040066e28688b635801cdd5c6587fddae0e232 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 28 Sep 2010 21:37:20 +0200 Subject: ARM: imx/clock-imx27: Pass NULL as function callback, not 0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes many sparse warnings like: arch/arm/mach-imx/clock-imx27.c:597:1: warning: Using plain integer as NULL pointer Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/clock-imx27.c | 42 ++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 07bf315bc078..98a25bada783 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk); DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); /* Clocks we cannot directly gate, but drivers need their rates */ -DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk); -DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk); -DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk); -DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk); -DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk); -DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk); -DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk); -DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk); -DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk); -DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk); -DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk); -DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk); -DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk); -DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk); -DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk); -DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk); -DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk); -DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk); -DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk); -DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk); -DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); +DEFINE_CLOCK(cspi1_clk, 0, NULL, 0, NULL, &cspi1_clk1, &per2_clk); +DEFINE_CLOCK(cspi2_clk, 1, NULL, 0, NULL, &cspi2_clk1, &per2_clk); +DEFINE_CLOCK(cspi3_clk, 2, NULL, 0, NULL, &cspi13_clk1, &per2_clk); +DEFINE_CLOCK(sdhc1_clk, 0, NULL, 0, NULL, &sdhc1_clk1, &per2_clk); +DEFINE_CLOCK(sdhc2_clk, 1, NULL, 0, NULL, &sdhc2_clk1, &per2_clk); +DEFINE_CLOCK(sdhc3_clk, 2, NULL, 0, NULL, &sdhc3_clk1, &per2_clk); +DEFINE_CLOCK(pwm_clk, 0, NULL, 0, NULL, &pwm_clk1, &per1_clk); +DEFINE_CLOCK(gpt1_clk, 0, NULL, 0, NULL, &gpt1_clk1, &per1_clk); +DEFINE_CLOCK(gpt2_clk, 1, NULL, 0, NULL, &gpt2_clk1, &per1_clk); +DEFINE_CLOCK(gpt3_clk, 2, NULL, 0, NULL, &gpt3_clk1, &per1_clk); +DEFINE_CLOCK(gpt4_clk, 3, NULL, 0, NULL, &gpt4_clk1, &per1_clk); +DEFINE_CLOCK(gpt5_clk, 4, NULL, 0, NULL, &gpt5_clk1, &per1_clk); +DEFINE_CLOCK(gpt6_clk, 5, NULL, 0, NULL, &gpt6_clk1, &per1_clk); +DEFINE_CLOCK(uart1_clk, 0, NULL, 0, NULL, &uart1_clk1, &per1_clk); +DEFINE_CLOCK(uart2_clk, 1, NULL, 0, NULL, &uart2_clk1, &per1_clk); +DEFINE_CLOCK(uart3_clk, 2, NULL, 0, NULL, &uart3_clk1, &per1_clk); +DEFINE_CLOCK(uart4_clk, 3, NULL, 0, NULL, &uart4_clk1, &per1_clk); +DEFINE_CLOCK(uart5_clk, 4, NULL, 0, NULL, &uart5_clk1, &per1_clk); +DEFINE_CLOCK(uart6_clk, 5, NULL, 0, NULL, &uart6_clk1, &per1_clk); +DEFINE_CLOCK1(lcdc_clk, 0, NULL, 0, parent, &lcdc_clk1, &per3_clk); +DEFINE_CLOCK1(csi_clk, 0, NULL, 0, parent, &csi_clk1, &per4_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ -- cgit v1.2.3 From 7ad211e35b41166ccf8448345726f324f26260f7 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 28 Sep 2010 21:39:49 +0200 Subject: ARM: imx/pcm038: make regulator platform data static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the following sparse warning: arch/arm/mach-imx/pcm970-baseboard.c:203:30: warning: symbol 'pcm970_sja1000_platform_data' was not declared. Should it be static? Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/mach-pcm038.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 641f9bb08b26..a3d645ff4467 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -257,7 +257,7 @@ static struct regulator_init_data cam_data = { .consumer_supplies = cam_consumers, }; -struct mc13783_regulator_init_data pcm038_regulators[] = { +static struct mc13783_regulator_init_data pcm038_regulators[] = { { .id = MC13783_REGU_VCAM, .init_data = &cam_data, -- cgit v1.2.3 From 6c80ee51707ec9fcf137bc7b511d2853b772eae6 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 28 Sep 2010 21:53:31 +0200 Subject: ARM: imx: make all pin lists const and signed, move to .init where possible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Making the lists signed fixes sparse warnings like: arch/arm/mach-imx/mach-mx27_3ds.c:94:31: warning: incorrect type in argument 1 (different signedness) arch/arm/mach-imx/mach-mx27_3ds.c:94:31: expected int const *pin_list arch/arm/mach-imx/mach-mx27_3ds.c:94:31: got unsigned int static [toplevel] * Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/eukrea_mbimx27-baseboard.c | 2 +- arch/arm/mach-imx/mach-cpuimx27.c | 2 +- arch/arm/mach-imx/mach-imx27_visstrim_m10.c | 2 +- arch/arm/mach-imx/mach-imx27lite.c | 2 +- arch/arm/mach-imx/mach-mx1ads.c | 2 +- arch/arm/mach-imx/mach-mx21ads.c | 2 +- arch/arm/mach-imx/mach-mx27_3ds.c | 2 +- arch/arm/mach-imx/mach-mx27ads.c | 2 +- arch/arm/mach-imx/mach-mxt_td60.c | 2 +- arch/arm/mach-imx/mach-pca100.c | 2 +- arch/arm/mach-imx/mach-pcm038.c | 2 +- arch/arm/mach-imx/mach-scb9328.c | 2 +- arch/arm/mach-imx/pcm970-baseboard.c | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c index cb433aeec939..026263c665ca 100644 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c @@ -41,7 +41,7 @@ #include "devices-imx27.h" #include "devices.h" -static int eukrea_mbimx27_pins[] = { +static const int eukrea_mbimx27_pins[] __initconst = { /* UART2 */ PE3_PF_UART2_CTS, PE4_PF_UART2_RTS, diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index f00ddd9829b5..d4cb592ffaed 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c @@ -46,7 +46,7 @@ #include "devices-imx27.h" #include "devices.h" -static int eukrea_cpuimx27_pins[] = { +static const int eukrea_cpuimx27_pins[] __initconst = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c index 7b3eed043ef1..21904f32740c 100644 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c @@ -44,7 +44,7 @@ #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) #define SDHC1_IRQ IRQ_GPIOB(25) -static int visstrim_m10_pins[] = { +static const int visstrim_m10_pins[] __initconst = { /* UART1 (console) */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c index 22a2b5d91213..67480b639e2c 100644 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ b/arch/arm/mach-imx/mach-imx27lite.c @@ -27,7 +27,7 @@ #include "devices-imx27.h" #include "devices.h" -static unsigned int mx27lite_pins[] = { +static const int mx27lite_pins[] __initconst = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c index 6e2f24952f1b..85e2877572b5 100644 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ b/arch/arm/mach-imx/mach-mx1ads.c @@ -32,7 +32,7 @@ #include "devices-imx1.h" #include "devices.h" -static int mx1ads_pins[] = { +static const int mx1ads_pins[] __initconst = { /* UART1 */ PC9_PF_UART1_CTS, PC10_PF_UART1_RTS, diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c index 96d7f8189f32..7f021e6f6acd 100644 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ b/arch/arm/mach-imx/mach-mx21ads.c @@ -67,7 +67,7 @@ #define MX21ADS_IO_LED4_ON 0x4000 #define MX21ADS_IO_LED3_ON 0x8000 -static unsigned int mx21ads_pins[] = { +static const int mx21ads_pins[] __initconst = { /* CS8900A */ (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index e66ffaa1c26c..9f6832d5f7f7 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c @@ -33,7 +33,7 @@ #include "devices-imx27.h" #include "devices.h" -static unsigned int mx27pdk_pins[] = { +static const int mx27pdk_pins[] __initconst = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 6be6033c876d..1a33288787a8 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c @@ -66,7 +66,7 @@ /* to determine the correct external crystal reference */ #define CKIH_27MHZ_BIT_SET (1 << 3) -static unsigned int mx27ads_pins[] = { +static const int mx27ads_pins[] __initconst = { /* UART0 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c index d878bb99be7e..58fb0d653981 100644 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ b/arch/arm/mach-imx/mach-mxt_td60.c @@ -37,7 +37,7 @@ #include "devices-imx27.h" #include "devices.h" -static unsigned int mxt_td60_pins[] __initdata = { +static const int mxt_td60_pins[] __initconst = { /* UART0 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index cccf521de6b1..197dbb8afe9f 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -54,7 +54,7 @@ #define SPI1_SS1 (GPIO_PORTD + 27) #define SD2_CD (GPIO_PORTC + 29) -static int pca100_pins[] = { +static const int pca100_pins[] __initconst = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index a3d645ff4467..3fbed661f612 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c @@ -43,7 +43,7 @@ #include "devices-imx27.h" #include "devices.h" -static int pcm038_pins[] = { +static const int pcm038_pins[] __initconst = { /* UART1 */ PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c index 88bf0d1e26e6..fb2e5f3d37f6 100644 --- a/arch/arm/mach-imx/mach-scb9328.c +++ b/arch/arm/mach-imx/mach-scb9328.c @@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = { } }; -static int mxc_uart1_pins[] = { +static const int mxc_uart1_pins[] = { PC9_PF_UART1_CTS, PC10_PF_UART1_RTS, PC11_PF_UART1_TXD, diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index f490a406d57e..7cffad880e42 100644 --- a/arch/arm/mach-imx/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c @@ -31,7 +31,7 @@ #include "devices.h" -static int pcm970_pins[] = { +static const int pcm970_pins[] __initconst = { /* SDHC */ PB4_PF_SD2_D0, PB5_PF_SD2_D1, -- cgit v1.2.3 From 214b43100fd59e55fcd265329aafd14ab01ec30d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 28 Sep 2010 21:55:22 +0200 Subject: ARM: imx/pcm970: make platform_data static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the following sparse warning: arch/arm/mach-imx/pcm970-baseboard.c:224:13: warning: symbol 'pcm970_baseboard_init' was not declared. Should it be static? Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/pcm970-baseboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c index 7cffad880e42..9110d9cca7a2 100644 --- a/arch/arm/mach-imx/pcm970-baseboard.c +++ b/arch/arm/mach-imx/pcm970-baseboard.c @@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = { }, }; -struct sja1000_platform_data pcm970_sja1000_platform_data = { +static struct sja1000_platform_data pcm970_sja1000_platform_data = { .osc_freq = 16000000, .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, .cdr = CDR_CBP, -- cgit v1.2.3 From bd9e310dca15c9987256f67af19f9f42426e7493 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 28 Sep 2010 22:04:01 +0200 Subject: ARM: imx/pca100: only specify i2c device type once MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The first argument to I2C_BOARD_INFO is used to assign .type, so it should not be specified a second time. For the rtc-pcf8563/pcf8563 entry gcc preferred pcf8563, so did I. Signed-off-by: Uwe Kleine-König Signed-off-by: Sascha Hauer --- arch/arm/mach-imx/mach-pca100.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 197dbb8afe9f..1247ce9dabad 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c @@ -192,11 +192,9 @@ static struct i2c_board_info pca100_i2c_devices[] = { I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ .platform_data = &board_eeprom, }, { - I2C_BOARD_INFO("rtc-pcf8563", 0x51), - .type = "pcf8563" + I2C_BOARD_INFO("pcf8563", 0x51), }, { I2C_BOARD_INFO("lm75", 0x4a), - .type = "lm75" } }; -- cgit v1.2.3 From c62d0f2ac18d38265ccf0e821e6afee60a0c89b5 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 1 Sep 2010 09:37:05 -0400 Subject: ARM: link board specific files after core files This allows for board specific issues to override decisions made in generic code that might not be suitable due to some errata or the like, by making the initcall hooks from those board specific files run after the core ones, therefore avoiding ugly #ifdef's in core code. Signed-off-by: Nicolas Pitre Tested-by: Dave Martin Tested-by: Jason Hui --- arch/arm/Makefile | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 59c1ce858fc8..30a21dddccb9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -245,13 +245,14 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE))) FASTFPE_OBJ :=$(FASTFPE)/ endif -# If we have a machine-specific directory, then include it in the build. -core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ -core-y += $(machdirs) $(platdirs) core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) core-$(CONFIG_VFP) += arch/arm/vfp/ +# If we have a machine-specific directory, then include it in the build. +core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ +core-y += $(machdirs) $(platdirs) + drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ libs-y := arch/arm/lib/ $(libs-y) -- cgit v1.2.3 From 33d7c5c1c808ea47d85630ac2dd98490d7df0ff4 Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Wed, 1 Sep 2010 22:49:13 +0300 Subject: ARM: mxc: turn off HWCAP_NEON for older versions of imx51 silicon Versions of silicon older than TO3 have broken NEON implementation. Turn off NEON in such cases. Signed-off-by: Amit Kucheria Tested-by: Dave Martin Tested-by: Jason Hui Signed-off-by: Nicolas Pitre --- arch/arm/mach-mx5/cpu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 2d37785e3857..eaacb6e9b5d0 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -70,6 +70,25 @@ int mx51_revision(void) } EXPORT_SYMBOL(mx51_revision); +#ifdef CONFIG_NEON + +/* + * All versions of the silicon before Rev. 3 have broken NEON implementations. + * Dependent on link order - so the assumption is that vfp_init is called + * before us. + */ +static int __init mx51_neon_fixup(void) +{ + if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { + elf_hwcap &= ~HWCAP_NEON; + pr_info("Turning off NEON support, detected broken NEON implementation\n"); + } + return 0; +} + +late_initcall(mx51_neon_fixup); +#endif + static int __init post_cpu_init(void) { unsigned int reg; -- cgit v1.2.3 From 7c63984b86f96c71c541132c74c4b56fe2a13e1a Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 23 Sep 2010 16:52:40 -0400 Subject: ARM: do not define VMALLOC_END relative to PAGE_OFFSET VMALLOC_END is supposed to be an absolute value, while PAGE_OFFSET may vary depending on the selected user:kernel memory split mode through CONFIG_VMSPLIT_*. In fact, the goal of moving PAGE_OFFSET down is to accommodate more directly addressed RAM by the kernel below the vmalloc area, and having VMALLOC_END move along PAGE_OFFSET is rather against the very reason why PAGE_OFFSET can be moved in the first place. Signed-off-by: Nicolas Pitre --- arch/arm/mach-aaec2000/include/mach/vmalloc.h | 2 +- arch/arm/mach-bcmring/include/mach/vmalloc.h | 2 +- arch/arm/mach-clps711x/include/mach/vmalloc.h | 2 +- arch/arm/mach-ebsa110/include/mach/vmalloc.h | 2 +- arch/arm/mach-footbridge/include/mach/vmalloc.h | 2 +- arch/arm/mach-h720x/include/mach/vmalloc.h | 2 +- arch/arm/mach-integrator/include/mach/vmalloc.h | 2 +- arch/arm/mach-msm/include/mach/vmalloc.h | 2 +- arch/arm/mach-netx/include/mach/vmalloc.h | 2 +- arch/arm/mach-omap1/include/mach/vmalloc.h | 2 +- arch/arm/mach-omap2/include/mach/vmalloc.h | 2 +- arch/arm/mach-pnx4008/include/mach/vmalloc.h | 2 +- arch/arm/mach-rpc/include/mach/vmalloc.h | 2 +- arch/arm/mach-shark/include/mach/vmalloc.h | 2 +- arch/arm/mach-versatile/include/mach/vmalloc.h | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h index 551f68f666bf..cff4e0a996ce 100644 --- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h +++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h @@ -11,6 +11,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h index 35e2ead8395c..3db3a09fd398 100644 --- a/arch/arm/mach-bcmring/include/mach/vmalloc.h +++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h @@ -22,4 +22,4 @@ * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles * larger physical memory designs better. */ -#define VMALLOC_END (PAGE_OFFSET + 0x30000000) +#define VMALLOC_END 0xf0000000 diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h index ea6cc7beff28..30b3a287ed88 100644 --- a/arch/arm/mach-clps711x/include/mach/vmalloc.h +++ b/arch/arm/mach-clps711x/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h index 9b44c19e95ec..60bde56fba4c 100644 --- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h +++ b/arch/arm/mach-ebsa110/include/mach/vmalloc.h @@ -7,4 +7,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#define VMALLOC_END (PAGE_OFFSET + 0x1f000000) +#define VMALLOC_END 0xdf000000 diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h index d0958d860a3c..0ffbb7c85e59 100644 --- a/arch/arm/mach-footbridge/include/mach/vmalloc.h +++ b/arch/arm/mach-footbridge/include/mach/vmalloc.h @@ -7,4 +7,4 @@ */ -#define VMALLOC_END (PAGE_OFFSET + 0x30000000) +#define VMALLOC_END 0xf0000000 diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h index ff1460d6841b..a45915b88756 100644 --- a/arch/arm/mach-h720x/include/mach/vmalloc.h +++ b/arch/arm/mach-h720x/include/mach/vmalloc.h @@ -5,6 +5,6 @@ #ifndef __ARCH_ARM_VMALLOC_H #define __ARCH_ARM_VMALLOC_H -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 #endif diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h index e87ab0b37bdd..e056e7cf5645 100644 --- a/arch/arm/mach-integrator/include/mach/vmalloc.h +++ b/arch/arm/mach-integrator/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h index 05f81fd8623c..31a32ad062dc 100644 --- a/arch/arm/mach-msm/include/mach/vmalloc.h +++ b/arch/arm/mach-msm/include/mach/vmalloc.h @@ -16,7 +16,7 @@ #ifndef __ASM_ARCH_MSM_VMALLOC_H #define __ASM_ARCH_MSM_VMALLOC_H -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 #endif diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h index 25d5cc676e0f..7cca3574308f 100644 --- a/arch/arm/mach-netx/include/mach/vmalloc.h +++ b/arch/arm/mach-netx/include/mach/vmalloc.h @@ -16,4 +16,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h index 1b2af14df151..b001f67d695b 100644 --- a/arch/arm/mach-omap1/include/mach/vmalloc.h +++ b/arch/arm/mach-omap1/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x18000000) +#define VMALLOC_END 0xd8000000 diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h index 9ce9b6e8ad23..4da31e997efe 100644 --- a/arch/arm/mach-omap2/include/mach/vmalloc.h +++ b/arch/arm/mach-omap2/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x38000000) +#define VMALLOC_END 0xf8000000 diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h index 2ad398378aed..31b65ee07b0b 100644 --- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h +++ b/arch/arm/mach-pnx4008/include/mach/vmalloc.h @@ -17,4 +17,4 @@ * The vmalloc() routines leaves a hole of 4kB between each vmalloced * area for the same reason. ;) */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h index 9a96fd69e705..3bcd86fadb81 100644 --- a/arch/arm/mach-rpc/include/mach/vmalloc.h +++ b/arch/arm/mach-rpc/include/mach/vmalloc.h @@ -7,4 +7,4 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#define VMALLOC_END (PAGE_OFFSET + 0x1c000000) +#define VMALLOC_END 0xdc000000 diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h index f6c6837c5451..8e845b6a7cb5 100644 --- a/arch/arm/mach-shark/include/mach/vmalloc.h +++ b/arch/arm/mach-shark/include/mach/vmalloc.h @@ -1,4 +1,4 @@ /* * arch/arm/mach-shark/include/mach/vmalloc.h */ -#define VMALLOC_END (PAGE_OFFSET + 0x10000000) +#define VMALLOC_END 0xd0000000 diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h index 427e3612db5d..ebd8a2543d3b 100644 --- a/arch/arm/mach-versatile/include/mach/vmalloc.h +++ b/arch/arm/mach-versatile/include/mach/vmalloc.h @@ -18,4 +18,4 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#define VMALLOC_END (PAGE_OFFSET + 0x18000000) +#define VMALLOC_END 0xd8000000 -- cgit v1.2.3 From 087aaffcdf9c91667c93923fbc05fa8fb6bc7d3a Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 22 Sep 2010 18:34:36 -0400 Subject: ARM: implement CONFIG_STRICT_DEVMEM by disabling access to RAM via /dev/mem There are very few legitimate use cases, if any, for directly accessing system RAM through /dev/mem. So let's mimic what they do on x86 and forbid it when CONFIG_STRICT_DEVMEM is turned on. Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig.debug | 14 ++++++++++++++ arch/arm/include/asm/io.h | 1 + arch/arm/mm/mmap.c | 22 ++++++++++++++++++++++ 3 files changed, 37 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 91344af75f39..c29fb382aeee 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -2,6 +2,20 @@ menu "Kernel hacking" source "lib/Kconfig.debug" +config STRICT_DEVMEM + bool "Filter access to /dev/mem" + depends on MMU + ---help--- + If this option is disabled, you allow userspace (root) access to all + of memory, including kernel and userspace memory. Accidental + access to this is obviously disastrous, but specific access can + be used by people debugging the kernel. + + If this option is switched on, the /dev/mem file only allows + userspace access to memory mapped peripherals. + + If in doubt, say Y. + # RMK wants arm kernels compiled with frame pointers or stack unwinding. # If you know what you are doing and are willing to live without stack # traces, you can get a slightly smaller kernel by setting this option to diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 1261b1f928d9..815efa2d4e07 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -294,6 +294,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr); #define ARCH_HAS_VALID_PHYS_ADDR_RANGE extern int valid_phys_addr_range(unsigned long addr, size_t size); extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); +extern int devmem_is_allowed(unsigned long pfn); #endif /* diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 4f5b39687df5..b0a98305055c 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c @@ -144,3 +144,25 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size) { return !(pfn + (size >> PAGE_SHIFT) > 0x00100000); } + +#ifdef CONFIG_STRICT_DEVMEM + +#include + +/* + * devmem_is_allowed() checks to see if /dev/mem access to a certain + * address is valid. The argument is a physical page number. + * We mimic x86 here by disallowing access to system RAM as well as + * device-exclusive MMIO regions. This effectively disable read()/write() + * on /dev/mem. + */ +int devmem_is_allowed(unsigned long pfn) +{ + if (iomem_is_exclusive(pfn << PAGE_SHIFT)) + return 0; + if (!page_is_ram(pfn)) + return 1; + return 0; +} + +#endif -- cgit v1.2.3 From 70c70d97809c3cdb8ff04f38ee3718c5385a2a4d Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 26 Aug 2010 15:08:35 -0700 Subject: ARM: SECCOMP support Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig | 14 ++++++++++++++ arch/arm/include/asm/seccomp.h | 11 +++++++++++ arch/arm/include/asm/thread_info.h | 2 ++ arch/arm/kernel/entry-common.S | 15 +++++++++++++-- 4 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/seccomp.h (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 88c97bc7a6f5..1273ee8756be 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1463,6 +1463,20 @@ config UACCESS_WITH_MEMCPY However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain. +config SECCOMP + bool + prompt "Enable seccomp to safely compute untrusted bytecode" + ---help--- + This kernel feature is useful for number crunching applications + that may need to compute untrusted bytecode during their + execution. By using pipes or other transports made available to + the process as file descriptors supporting the read/write + syscalls, it's possible to isolate those applications in + their own address space using seccomp. Once seccomp is + enabled via prctl(PR_SET_SECCOMP), it cannot be disabled + and the task is only allowed to execute a few safe syscalls + defined by each seccomp mode. + config CC_STACKPROTECTOR bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" help diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h new file mode 100644 index 000000000000..52b156b341f5 --- /dev/null +++ b/arch/arm/include/asm/seccomp.h @@ -0,0 +1,11 @@ +#ifndef _ASM_ARM_SECCOMP_H +#define _ASM_ARM_SECCOMP_H + +#include + +#define __NR_seccomp_read __NR_read +#define __NR_seccomp_write __NR_write +#define __NR_seccomp_exit __NR_exit +#define __NR_seccomp_sigreturn __NR_rt_sigreturn + +#endif /* _ASM_ARM_SECCOMP_H */ diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 763e29fa8530..7b5cc8dae06e 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -144,6 +144,7 @@ extern void vfp_flush_hwstate(struct thread_info *); #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_FREEZE 19 #define TIF_RESTORE_SIGMASK 20 +#define TIF_SECCOMP 21 #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) @@ -153,6 +154,7 @@ extern void vfp_flush_hwstate(struct thread_info *); #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) #define _TIF_FREEZE (1 << TIF_FREEZE) #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) +#define _TIF_SECCOMP (1 << TIF_SECCOMP) /* * Change these and you break ASM code in entry-common.S diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 7885722bdf4e..0385a8207b67 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -295,7 +295,6 @@ ENTRY(vector_swi) get_thread_info tsk adr tbl, sys_call_table @ load syscall table pointer - ldr ip, [tsk, #TI_FLAGS] @ check for syscall tracing #if defined(CONFIG_OABI_COMPAT) /* @@ -312,8 +311,20 @@ ENTRY(vector_swi) eor scno, scno, #__NR_SYSCALL_BASE @ check OS number #endif + ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing stmdb sp!, {r4, r5} @ push fifth and sixth args - tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? + +#ifdef CONFIG_SECCOMP + tst r10, #_TIF_SECCOMP + beq 1f + mov r0, scno + bl __secure_computing + add r0, sp, #S_R0 + S_OFF @ pointer to regs + ldmia r0, {r0 - r3} @ have to reload r0 - r3 +1: +#endif + + tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? bne __sys_trace cmp scno, #NR_syscalls @ check upper syscall limit -- cgit v1.2.3 From ec706dab290c486837d4a825870ab052bf200279 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 26 Aug 2010 23:10:50 -0400 Subject: ARM: add a vma entry for the user accessible vector page The kernel makes the high vector page visible to user space. This page contains (amongst others) small code segments that can be executed in user space. Make this page visible through ptrace and /proc//mem in order to let gdb perform code parsing needed for proper unwinding. For example, the ERESTART_RESTARTBLOCK handler actually has a stack frame -- it returns to a PC value stored on the user's stack. To unwind after a "sleep" system call was interrupted twice, GDB would have to recognize this situation and understand that stack frame layout -- which it currently cannot do. We could fix this by hard-coding addresses in the vector page range into GDB, but that isn't really portable as not all of those addresses are guaranteed to remain stable across kernel releases. And having the gdb process make an exception for this page and get content from its own address space for it looks strange, and it is not future proof either. Being located above PAGE_OFFSET, this vma cannot be deleted by user space code. Signed-off-by: Nicolas Pitre --- arch/arm/include/asm/elf.h | 4 ++++ arch/arm/include/asm/mmu_context.h | 29 ++++++++++++++++++++++++++++- arch/arm/kernel/process.c | 21 +++++++++++++++++++++ 3 files changed, 53 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index 5747a8baa413..8bb66bca2e3e 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -127,4 +127,8 @@ struct mm_struct; extern unsigned long arch_randomize_brk(struct mm_struct *mm); #define arch_randomize_brk arch_randomize_brk +extern int vectors_user_mapping(void); +#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping() +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES + #endif diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index a0b3cac0547c..71605d9f8e42 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -18,7 +18,6 @@ #include #include #include -#include void __check_kvm_seq(struct mm_struct *mm); @@ -134,4 +133,32 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #define deactivate_mm(tsk,mm) do { } while (0) #define activate_mm(prev,next) switch_mm(prev, next, NULL) +/* + * We are inserting a "fake" vma for the user-accessible vector page so + * gdb and friends can get to it through ptrace and /proc//mem. + * But we also want to remove it before the generic code gets to see it + * during process exit or the unmapping of it would cause total havoc. + * (the macro is used as remove_vma() is static to mm/mmap.c) + */ +#define arch_exit_mmap(mm) \ +do { \ + struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \ + if (high_vma) { \ + BUG_ON(high_vma->vm_next); /* it should be last */ \ + if (high_vma->vm_prev) \ + high_vma->vm_prev->vm_next = NULL; \ + else \ + mm->mmap = NULL; \ + rb_erase(&high_vma->vm_rb, &mm->mm_rb); \ + mm->mmap_cache = NULL; \ + mm->map_count--; \ + remove_vma(high_vma); \ + } \ +} while (0) + +static inline void arch_dup_mmap(struct mm_struct *oldmm, + struct mm_struct *mm) +{ +} + #endif diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 401e38be1f78..66ac9c926200 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -458,3 +458,24 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) unsigned long range_end = mm->brk + 0x02000000; return randomize_range(mm->brk, range_end, 0) ? : mm->brk; } + +/* + * The vectors page is always readable from user space for the + * atomic helpers and the signal restart code. Let's declare a mapping + * for it so it is visible through ptrace and /proc//mem. + */ + +int vectors_user_mapping(void) +{ + struct mm_struct *mm = current->mm; + return install_special_mapping(mm, 0xffff0000, PAGE_SIZE, + VM_READ | VM_EXEC | + VM_MAYREAD | VM_MAYEXEC | + VM_ALWAYSDUMP | VM_RESERVED, + NULL); +} + +const char *arch_vma_name(struct vm_area_struct *vma) +{ + return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL; +} -- cgit v1.2.3 From 54dc3f4674fbaf362d6e969904bfcece3cfebef1 Mon Sep 17 00:00:00 2001 From: Eric Bénard Date: Sat, 2 Oct 2010 17:15:26 +0200 Subject: mach-cpuimx35: remove unecessary tsc2007 functions + style cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - remove functions which are no more necessary for tsc2007 - indent platform_data for better readability Signed-off-by: Eric Bénard Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mach-cpuimx35.c | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c index 2a4f8b781ba4..ea0a85f1c9aa 100644 --- a/arch/arm/mach-mx3/mach-cpuimx35.c +++ b/arch/arm/mach-mx3/mach-cpuimx35.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -53,39 +54,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = { }; static const struct imxi2c_platform_data -eukrea_cpuimx35_i2c0_data __initconst = { - .bitrate = 50000, + eukrea_cpuimx35_i2c0_data __initconst = { + .bitrate = 100000, }; -#define TSC2007_IRQGPIO (2 * 32 + 2) -static int ts_get_pendown_state(void) -{ - int val = 0; - gpio_free(TSC2007_IRQGPIO); - gpio_request(TSC2007_IRQGPIO, NULL); - gpio_direction_input(TSC2007_IRQGPIO); - - val = gpio_get_value(TSC2007_IRQGPIO); - - gpio_free(TSC2007_IRQGPIO); - gpio_request(TSC2007_IRQGPIO, NULL); - - return val ? 0 : 1; -} - -static int ts_init(void) -{ - gpio_request(TSC2007_IRQGPIO, NULL); - return 0; -} - static struct tsc2007_platform_data tsc2007_info = { .model = 2007, .x_plate_ohms = 180, - .get_pendown_state = ts_get_pendown_state, - .init_platform_hw = ts_init, }; +#define TSC2007_IRQGPIO (2 * 32 + 2) static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { { I2C_BOARD_INFO("pcf8563", 0x51), @@ -135,7 +113,7 @@ static struct pad_desc eukrea_cpuimx35_pads[] = { }; static const struct mxc_nand_platform_data -eukrea_cpuimx35_nand_board_info __initconst = { + eukrea_cpuimx35_nand_board_info __initconst = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, -- cgit v1.2.3 From 475d92fc6e72cd123dc5dbb9e70cdb80b0cfdf2d Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 28 Sep 2010 14:02:02 +0100 Subject: ARM: 6416/1: errata: faulty hazard checking in the Store Buffer may lead to data corruption On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur under very rare conditions due to a store buffer optimisation. This workaround sets a bit in the diagnostic register of the Cortex-A9, disabling the optimisation and preventing the problem from occurring. Acked-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/Kconfig | 14 ++++++++++++++ arch/arm/mm/proc-v7.S | 8 ++++++++ 2 files changed, 22 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 88c97bc7a6f5..9c26ba7244fb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1101,6 +1101,20 @@ config ARM_ERRATA_720789 invalidated are not, resulting in an incoherency in the system page tables. The workaround changes the TLB flushing routines to invalidate entries regardless of the ASID. + +config ARM_ERRATA_743622 + bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" + depends on CPU_V7 + help + This option enables the workaround for the 743622 Cortex-A9 + (r2p0..r2p2) erratum. Under very rare conditions, a faulty + optimisation in the Cortex-A9 Store Buffer may lead to data + corruption. This workaround sets a specific bit in the diagnostic + register of the Cortex-A9 which disables the Store Buffer + optimisation, preventing the defect from occurring. This has no + visible impact on the overall performance or power consumption of the + processor. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7563ff0141bd..75619c55f137 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -253,6 +253,14 @@ __v7_setup: orreq r10, r10, #1 << 22 @ set bit #22 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_743622 + teq r6, #0x20 @ present in r2p0 + teqne r6, #0x21 @ present in r2p1 + teqne r6, #0x22 @ present in r2p2 + mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register + orreq r10, r10, #1 << 6 @ set bit #6 + mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 #ifdef HARVARD_CACHE -- cgit v1.2.3 From 7f58217bb6d39edac68ae0988cdb96a520ad916f Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 30 Sep 2010 09:02:17 +0100 Subject: ARM: 6419/1: mmu: Fix MT_MEMORY and MT_MEMORY_NONCACHED pte flags The commit f1a2481c0 sets up the default flags for MT_MEMORY and MT_MEMORY_NONCACHED memory types. L_PTE_USER flag is wrongly set as default for these entries so remove it. Also adding the 'L_PTE_WRITE' flag so that these pages become read-write instead of just being read-only [this stops them being exposed to userspace, which is the main concern here --rmk] Reported-by: Catalin Marinas Signed-off-by: Santosh Shilimkar Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mm/mmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 6a3a2d0cd6db..e8ed9dc461fe 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -248,7 +248,7 @@ static struct mem_type mem_types[] = { }, [MT_MEMORY] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | - L_PTE_USER | L_PTE_EXEC, + L_PTE_WRITE | L_PTE_EXEC, .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, @@ -259,7 +259,7 @@ static struct mem_type mem_types[] = { }, [MT_MEMORY_NONCACHED] = { .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | - L_PTE_USER | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, + L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, .prot_l1 = PMD_TYPE_TABLE, .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, -- cgit v1.2.3 From ccdf2e1bca8a45eaf89eb142dbed3551886413fe Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 27 Sep 2010 18:12:12 +0100 Subject: ARM: 6412/1: kprobes-decode: add support for MOVW instruction The MOVW instruction moves a 16-bit immediate into the bottom halfword of the destination register. This patch ensures that kprobes leaves the 16-bit immediate intact, rather than assume a 12-bit immediate and mask out the upper 4 bits. Acked-by: Nicolas Pitre Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/kernel/kprobes-decode.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index 8bccbfa693ff..2c1f0050c9c4 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c @@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) { /* * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx - * Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx + * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx * ALU op with S bit and Rd == 15 : * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */ - if ((insn & 0x0f900000) == 0x03200000 || /* MSR & Undef */ + if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */ + (insn & 0x0ff00000) == 0x03400000 || /* Undef */ (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */ return INSN_REJECTED; @@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi) * *S (bit 20) updates condition codes * ADC/SBC/RSC reads the C flag */ - insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */ + insn &= 0xffff0fff; /* Rd = r0 */ asi->insn[0] = insn; asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */ emulate_alu_imm_rwflags : emulate_alu_imm_rflags; -- cgit v1.2.3 From 4d4a4b037c5d3620b8c55504a8c9e0cbf949f7fa Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 27 Sep 2010 22:09:52 +0100 Subject: ARM: 6413/1: ux500: resources for DB5500 mbox driver and modem irq handler Platform resources found in the DB5500 for mailboxes and the modem IRQ controller. Signed-off-by: Stefan Nilsson XK Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/cpu-db5500.c | 88 ++++++++++++++++++++++++++ arch/arm/mach-ux500/include/mach/db5500-regs.h | 14 ++++ arch/arm/mach-ux500/include/mach/irqs-db5500.h | 1 + arch/arm/mach-ux500/include/mach/irqs.h | 15 ++++- 4 files changed, 117 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c index e9278f6d67aa..2f87075e9d6f 100644 --- a/arch/arm/mach-ux500/cpu-db5500.c +++ b/arch/arm/mach-ux500/cpu-db5500.c @@ -14,6 +14,7 @@ #include #include #include +#include static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), @@ -24,6 +25,90 @@ static struct map_desc u5500_io_desc[] __initdata = { __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), }; +static struct resource mbox0_resources[] = { + { + .name = "mbox_peer", + .start = U5500_MBOX0_PEER_START, + .end = U5500_MBOX0_PEER_END, + .flags = IORESOURCE_MEM, + }, + { + .name = "mbox_local", + .start = U5500_MBOX0_LOCAL_START, + .end = U5500_MBOX0_LOCAL_END, + .flags = IORESOURCE_MEM, + }, + { + .name = "mbox_irq", + .start = MBOX_PAIR0_VIRT_IRQ, + .end = MBOX_PAIR0_VIRT_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource mbox1_resources[] = { + { + .name = "mbox_peer", + .start = U5500_MBOX1_PEER_START, + .end = U5500_MBOX1_PEER_END, + .flags = IORESOURCE_MEM, + }, + { + .name = "mbox_local", + .start = U5500_MBOX1_LOCAL_START, + .end = U5500_MBOX1_LOCAL_END, + .flags = IORESOURCE_MEM, + }, + { + .name = "mbox_irq", + .start = MBOX_PAIR1_VIRT_IRQ, + .end = MBOX_PAIR1_VIRT_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource mbox2_resources[] = { + { + .name = "mbox_peer", + .start = U5500_MBOX2_PEER_START, + .end = U5500_MBOX2_PEER_END, + .flags = IORESOURCE_MEM, + }, + { + .name = "mbox_local", + .start = U5500_MBOX2_LOCAL_START, + .end = U5500_MBOX2_LOCAL_END, + .flags = IORESOURCE_MEM, + }, + { + .name = "mbox_irq", + .start = MBOX_PAIR2_VIRT_IRQ, + .end = MBOX_PAIR2_VIRT_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device mbox0_device = { + .id = 0, + .name = "mbox", + .resource = mbox0_resources, + .num_resources = ARRAY_SIZE(mbox0_resources), +}; + +static struct platform_device mbox1_device = { + .id = 1, + .name = "mbox", + .resource = mbox1_resources, + .num_resources = ARRAY_SIZE(mbox1_resources), +}; + +static struct platform_device mbox2_device = { + .id = 2, + .name = "mbox", + .resource = mbox2_resources, + .num_resources = ARRAY_SIZE(mbox2_resources), +}; + static struct platform_device *u5500_platform_devs[] __initdata = { &u5500_gpio_devs[0], &u5500_gpio_devs[1], @@ -33,6 +118,9 @@ static struct platform_device *u5500_platform_devs[] __initdata = { &u5500_gpio_devs[5], &u5500_gpio_devs[6], &u5500_gpio_devs[7], + &mbox0_device, + &mbox1_device, + &mbox2_device, }; void __init u5500_map_io(void) diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h index 545c80fc8024..3eafc0e24ba5 100644 --- a/arch/arm/mach-ux500/include/mach/db5500-regs.h +++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h @@ -100,4 +100,18 @@ #define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) #define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) +#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000) +#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40) +#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F) +#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60) +#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F) +#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80) +#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F) +#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0) +#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF) +#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00) +#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F) +#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20) +#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F) + #endif diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h index 6fbfe5e2065a..bfa123dbec3b 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h +++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h @@ -61,6 +61,7 @@ #define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) #define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) #define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) +#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65) #define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) #define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) #define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h index 0d552d9c9c00..693aa57de88d 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/include/mach/irqs.h @@ -84,6 +84,19 @@ #include #endif -#define NR_IRQS IRQ_BOARD_END +/* + * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual + * IRQ:s representing modem IRQ:s can be allocated + */ +#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1) +#define IRQ_MODEM_EVENTS_NBR 72 +#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR) + +/* List of virtual IRQ:s that are allocated from the range above */ +#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43) +#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45) +#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41) + +#define NR_IRQS IRQ_MODEM_EVENTS_END #endif /* ASM_ARCH_IRQS_H */ -- cgit v1.2.3 From b84ccd776fedee8b28f736662cd045bf893ed633 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 27 Sep 2010 22:10:55 +0100 Subject: ARM: 6414/1: ux500: DB5500 generic modem IRQ handler This is a (threaded) IRQ handler for the modems that appear from the modem part of the DB5500 ASIC. Signed-off-by: Stefan Nilsson XK Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/modem_irq.c | 139 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 arch/arm/mach-ux500/modem_irq.c (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem_irq.c new file mode 100644 index 000000000000..3187f8871169 --- /dev/null +++ b/arch/arm/mach-ux500/modem_irq.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Author: Stefan Nilsson for ST-Ericsson. + * Author: Martin Persson for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2. + */ + +#include +#include +#include +#include +#include +#include + +#define MODEM_INTCON_BASE_ADDR 0xBFFD3000 +#define MODEM_INTCON_SIZE 0xFFF + +#define DEST_IRQ41_OFFSET 0x2A4 +#define DEST_IRQ43_OFFSET 0x2AC +#define DEST_IRQ45_OFFSET 0x2B4 + +#define PRIO_IRQ41_OFFSET 0x6A4 +#define PRIO_IRQ43_OFFSET 0x6AC +#define PRIO_IRQ45_OFFSET 0x6B4 + +#define ALLOW_IRQ_OFFSET 0x104 + +#define MODEM_INTCON_CPU_NBR 0x1 +#define MODEM_INTCON_PRIO_HIGH 0x0 + +#define MODEM_INTCON_ALLOW_IRQ41 0x0200 +#define MODEM_INTCON_ALLOW_IRQ43 0x0800 +#define MODEM_INTCON_ALLOW_IRQ45 0x2000 + +#define MODEM_IRQ_REG_OFFSET 0x4 + +struct modem_irq { + void __iomem *modem_intcon_base; +}; + + +static void setup_modem_intcon(void __iomem *modem_intcon_base) +{ + /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */ + writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET); + writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET); + writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET); + + /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */ + writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET); + writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET); + writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET); + + /* IC_ALLOW_ARRAY - IRQ enable */ + writel(MODEM_INTCON_ALLOW_IRQ41 | + MODEM_INTCON_ALLOW_IRQ43 | + MODEM_INTCON_ALLOW_IRQ45, + modem_intcon_base + ALLOW_IRQ_OFFSET); +} + +static irqreturn_t modem_cpu_irq_handler(int irq, void *data) +{ + int real_irq; + int virt_irq; + struct modem_irq *mi = (struct modem_irq *)data; + + /* Read modem side IRQ number from modem IRQ controller */ + real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF; + virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq; + + pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X " + "which will be 0x%X (%d) which translates to " + "virtual IRQ 0x%X (%d)!\n", + (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET, + real_irq, + real_irq & 0xFF, + real_irq & 0xFF, + virt_irq, + virt_irq); + + if (virt_irq != 0) + generic_handle_irq(virt_irq); + + pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq); + + return IRQ_HANDLED; +} + +static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) +{ + set_irq_chip(irq, modem_irq_chip); + set_irq_handler(irq, handle_simple_irq); + set_irq_flags(irq, IRQF_VALID); + + pr_debug("modem_irq: Created virtual IRQ %d\n", irq); +} + +static int modem_irq_init(void) +{ + int err; + static struct irq_chip modem_irq_chip; + struct modem_irq *mi; + + pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n", + IRQ_DB5500_MODEM); + + mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL); + if (!mi) { + pr_err("modem_irq: Could not allocate device\n"); + return -ENOMEM; + } + + mi->modem_intcon_base = + ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE); + pr_debug("modem_irq: ioremapped modem_intcon_base from " + "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR, + (u32)mi->modem_intcon_base); + + setup_modem_intcon(mi->modem_intcon_base); + + modem_irq_chip = dummy_irq_chip; + modem_irq_chip.name = "modem_irq"; + + /* Create the virtual IRQ:s needed */ + create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip); + create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip); + create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip); + + err = request_threaded_irq(IRQ_DB5500_MODEM, NULL, + modem_cpu_irq_handler, IRQF_ONESHOT, + "modem_irq", mi); + if (err) + pr_err("modem_irq: Could not register IRQ %d\n", + IRQ_DB5500_MODEM); + + return 0; +} + +arch_initcall(modem_irq_init); -- cgit v1.2.3 From 38cdfe06630a109a7a38b70c3cd208defd9f5711 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 27 Sep 2010 22:11:57 +0100 Subject: ARM: 6415/1: ux500: DB5500 mailbox driver This is a driver for the mailboxes used to communicate with the DB5500 modem portions. Signed-off-by: Stefan Nilsson XK Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/include/mach/mbox.h | 88 +++++ arch/arm/mach-ux500/mbox.c | 567 ++++++++++++++++++++++++++++++++ 2 files changed, 655 insertions(+) create mode 100644 arch/arm/mach-ux500/include/mach/mbox.h create mode 100644 arch/arm/mach-ux500/mbox.c (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox.h new file mode 100644 index 000000000000..7f9da4d2fbda --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/mbox.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Author: Stefan Nilsson for ST-Ericsson. + * Author: Martin Persson for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2. + */ + +#ifndef __INC_STE_MBOX_H +#define __INC_STE_MBOX_H + +#define MBOX_BUF_SIZE 16 +#define MBOX_NAME_SIZE 8 + +/** + * mbox_recv_cb_t - Definition of the mailbox callback. + * @mbox_msg: The mailbox message. + * @priv: The clients private data as specified in the call to mbox_setup. + * + * This function will be called upon reception of new mailbox messages. + */ +typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv); + +/** + * struct mbox - Mailbox instance struct + * @list: Linked list head. + * @pdev: Pointer to device struct. + * @cb: Callback function. Will be called + * when new data is received. + * @client_data: Clients private data. Will be sent back + * in the callback function. + * @virtbase_peer: Virtual address for outgoing mailbox. + * @virtbase_local: Virtual address for incoming mailbox. + * @buffer: Then internal queue for outgoing messages. + * @name: Name of this mailbox. + * @buffer_available: Completion variable to achieve "blocking send". + * This variable will be signaled when there is + * internal buffer space available. + * @client_blocked: To keep track if any client is currently + * blocked. + * @lock: Spinlock to protect this mailbox instance. + * @write_index: Index in internal buffer to write to. + * @read_index: Index in internal buffer to read from. + * @allocated: Indicates whether this particular mailbox + * id has been allocated by someone. + */ +struct mbox { + struct list_head list; + struct platform_device *pdev; + mbox_recv_cb_t *cb; + void *client_data; + void __iomem *virtbase_peer; + void __iomem *virtbase_local; + u32 buffer[MBOX_BUF_SIZE]; + char name[MBOX_NAME_SIZE]; + struct completion buffer_available; + u8 client_blocked; + spinlock_t lock; + u8 write_index; + u8 read_index; + bool allocated; +}; + +/** + * mbox_setup - Set up a mailbox and return its instance. + * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU, + * 2 for modem DSP. + * @mbox_cb: Pointer to the callback function to be called when a new message + * is received. + * @priv: Client user data which will be returned in the callback. + * + * Returns a mailbox instance to be specified in subsequent calls to mbox_send. + */ +struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv); + +/** + * mbox_send - Send a mailbox message. + * @mbox: Mailbox instance (returned by mbox_setup) + * @mbox_msg: The mailbox message to send. + * @block: Specifies whether this call will block until send is possible, + * or return an error if the mailbox buffer is full. + * + * Returns 0 on success or a negative error code on error. -ENOMEM indicates + * that the internal buffer is full and you have to try again later (or + * specify "block" in order to block until send is possible). + */ +int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block); + +#endif /*INC_STE_MBOX_H*/ diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox.c new file mode 100644 index 000000000000..63435389c544 --- /dev/null +++ b/arch/arm/mach-ux500/mbox.c @@ -0,0 +1,567 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Author: Stefan Nilsson for ST-Ericsson. + * Author: Martin Persson for ST-Ericsson. + * License terms: GNU General Public License (GPL), version 2. + */ + +/* + * Mailbox nomenclature: + * + * APE MODEM + * mbox pairX + * .......................... + * . . + * . peer . + * . send ---- . + * . --> | | . + * . | | . + * . ---- . + * . . + * . local . + * . rec ---- . + * . | | <-- . + * . | | . + * . ---- . + * ......................... + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MBOX_NAME "mbox" + +#define MBOX_FIFO_DATA 0x000 +#define MBOX_FIFO_ADD 0x004 +#define MBOX_FIFO_REMOVE 0x008 +#define MBOX_FIFO_THRES_FREE 0x00C +#define MBOX_FIFO_THRES_OCCUP 0x010 +#define MBOX_FIFO_STATUS 0x014 + +#define MBOX_DISABLE_IRQ 0x4 +#define MBOX_ENABLE_IRQ 0x0 +#define MBOX_LATCH 1 + +/* Global list of all mailboxes */ +static struct list_head mboxs = LIST_HEAD_INIT(mboxs); + +static struct mbox *get_mbox_with_id(u8 id) +{ + u8 i; + struct list_head *pos = &mboxs; + for (i = 0; i <= id; i++) + pos = pos->next; + + return (struct mbox *) list_entry(pos, struct mbox, list); +} + +int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block) +{ + int res = 0; + + spin_lock(&mbox->lock); + + dev_dbg(&(mbox->pdev->dev), + "About to buffer 0x%X to mailbox 0x%X." + " ri = %d, wi = %d\n", + mbox_msg, (u32)mbox, mbox->read_index, + mbox->write_index); + + /* Check if write buffer is full */ + while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) { + if (!block) { + dev_dbg(&(mbox->pdev->dev), + "Buffer full in non-blocking call! " + "Returning -ENOMEM!\n"); + res = -ENOMEM; + goto exit; + } + spin_unlock(&mbox->lock); + dev_dbg(&(mbox->pdev->dev), + "Buffer full in blocking call! Sleeping...\n"); + mbox->client_blocked = 1; + wait_for_completion(&mbox->buffer_available); + dev_dbg(&(mbox->pdev->dev), + "Blocking send was woken up! Trying again...\n"); + spin_lock(&mbox->lock); + } + + mbox->buffer[mbox->write_index] = mbox_msg; + mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE; + + /* + * Indicate that we want an IRQ as soon as there is a slot + * in the FIFO + */ + writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); + +exit: + spin_unlock(&mbox->lock); + return res; +} +EXPORT_SYMBOL(mbox_send); + +#if defined(CONFIG_DEBUG_FS) +/* + * Expected input: + * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times + */ +static ssize_t mbox_write_fifo(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + unsigned long mbox_mess; + unsigned long nbr_sends; + unsigned long i; + char int_buf[16]; + char *token; + char *val; + + struct mbox *mbox = (struct mbox *) dev->platform_data; + + strncpy((char *) &int_buf, buf, sizeof(int_buf)); + token = (char *) &int_buf; + + /* Parse message */ + val = strsep(&token, " "); + if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0)) + mbox_mess = 0xDEADBEEF; + + val = strsep(&token, " "); + if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0)) + nbr_sends = 1; + + dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n", + mbox_mess, nbr_sends, (u32) mbox); + + for (i = 0; i < nbr_sends; i++) + mbox_send(mbox, mbox_mess, true); + + return count; +} + +static ssize_t mbox_read_fifo(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int mbox_value; + struct mbox *mbox = (struct mbox *) dev->platform_data; + + if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0) + return sprintf(buf, "Mailbox is empty\n"); + + mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); + writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); + + return sprintf(buf, "0x%X\n", mbox_value); +} + +static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo); + +static int mbox_show(struct seq_file *s, void *data) +{ + struct list_head *pos; + u8 mbox_index = 0; + + list_for_each(pos, &mboxs) { + struct mbox *m = + (struct mbox *) list_entry(pos, struct mbox, list); + if (m == NULL) { + seq_printf(s, + "Unable to retrieve mailbox %d\n", + mbox_index); + continue; + } + + spin_lock(&m->lock); + if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) { + seq_printf(s, "MAILBOX %d not setup or corrupt\n", + mbox_index); + spin_unlock(&m->lock); + continue; + } + + seq_printf(s, + "===========================\n" + " MAILBOX %d\n" + " PEER MAILBOX DUMP\n" + "---------------------------\n" + "FIFO: 0x%X (%d)\n" + "Free Threshold: 0x%.2X (%d)\n" + "Occupied Threshold: 0x%.2X (%d)\n" + "Status: 0x%.2X (%d)\n" + " Free spaces (ot): %d (%d)\n" + " Occup spaces (ot): %d (%d)\n" + "===========================\n" + " LOCAL MAILBOX DUMP\n" + "---------------------------\n" + "FIFO: 0x%.X (%d)\n" + "Free Threshold: 0x%.2X (%d)\n" + "Occupied Threshold: 0x%.2X (%d)\n" + "Status: 0x%.2X (%d)\n" + " Free spaces (ot): %d (%d)\n" + " Occup spaces (ot): %d (%d)\n" + "===========================\n" + "write_index: %d\n" + "read_index : %d\n" + "===========================\n" + "\n", + mbox_index, + readl(m->virtbase_peer + MBOX_FIFO_DATA), + readl(m->virtbase_peer + MBOX_FIFO_DATA), + readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), + readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE), + readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), + readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP), + readl(m->virtbase_peer + MBOX_FIFO_STATUS), + readl(m->virtbase_peer + MBOX_FIFO_STATUS), + (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7, + (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1, + (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7, + (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1, + readl(m->virtbase_local + MBOX_FIFO_DATA), + readl(m->virtbase_local + MBOX_FIFO_DATA), + readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), + readl(m->virtbase_local + MBOX_FIFO_THRES_FREE), + readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), + readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP), + readl(m->virtbase_local + MBOX_FIFO_STATUS), + readl(m->virtbase_local + MBOX_FIFO_STATUS), + (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7, + (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1, + (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7, + (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1, + m->write_index, m->read_index); + mbox_index++; + spin_unlock(&m->lock); + } + + return 0; +} + +static int mbox_open(struct inode *inode, struct file *file) +{ + return single_open(file, mbox_show, NULL); +} + +static const struct file_operations mbox_operations = { + .owner = THIS_MODULE, + .open = mbox_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; +#endif + +static irqreturn_t mbox_irq(int irq, void *arg) +{ + u32 mbox_value; + int nbr_occup; + int nbr_free; + struct mbox *mbox = (struct mbox *) arg; + + spin_lock(&mbox->lock); + + dev_dbg(&(mbox->pdev->dev), + "mbox IRQ [%d] received. ri = %d, wi = %d\n", + irq, mbox->read_index, mbox->write_index); + + /* + * Check if we have any outgoing messages, and if there is space for + * them in the FIFO. + */ + if (mbox->read_index != mbox->write_index) { + /* + * Check by reading FREE for LOCAL since that indicates + * OCCUP for PEER + */ + nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS) + >> 4) & 0x7; + dev_dbg(&(mbox->pdev->dev), + "Status indicates %d empty spaces in the FIFO!\n", + nbr_free); + + while ((nbr_free > 0) && + (mbox->read_index != mbox->write_index)) { + /* Write the message and latch it into the FIFO */ + writel(mbox->buffer[mbox->read_index], + (mbox->virtbase_peer + MBOX_FIFO_DATA)); + writel(MBOX_LATCH, + (mbox->virtbase_peer + MBOX_FIFO_ADD)); + dev_dbg(&(mbox->pdev->dev), + "Wrote message 0x%X to addr 0x%X\n", + mbox->buffer[mbox->read_index], + (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA)); + + nbr_free--; + mbox->read_index = + (mbox->read_index + 1) % MBOX_BUF_SIZE; + } + + /* + * Check if we still want IRQ:s when there is free + * space to send + */ + if (mbox->read_index != mbox->write_index) { + dev_dbg(&(mbox->pdev->dev), + "Still have messages to send, but FIFO full. " + "Request IRQ again!\n"); + writel(MBOX_ENABLE_IRQ, + mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); + } else { + dev_dbg(&(mbox->pdev->dev), + "No more messages to send. " + "Do not request IRQ again!\n"); + writel(MBOX_DISABLE_IRQ, + mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); + } + + /* + * Check if we can signal any blocked clients that it is OK to + * start buffering again + */ + if (mbox->client_blocked && + (((mbox->write_index + 1) % MBOX_BUF_SIZE) + != mbox->read_index)) { + dev_dbg(&(mbox->pdev->dev), + "Waking up blocked client\n"); + complete(&mbox->buffer_available); + mbox->client_blocked = 0; + } + } + + /* Check if we have any incoming messages */ + nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7; + if (nbr_occup == 0) + goto exit; + + if (mbox->cb == NULL) { + dev_dbg(&(mbox->pdev->dev), "No receive callback registered, " + "leaving %d incoming messages in fifo!\n", nbr_occup); + goto exit; + } + + /* Read and acknowledge the message */ + mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA); + writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE)); + + /* Notify consumer of new mailbox message */ + dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n", + mbox_value); + mbox->cb(mbox_value, mbox->client_data); + +exit: + dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n", + mbox->read_index, mbox->write_index); + spin_unlock(&mbox->lock); + + return IRQ_HANDLED; +} + +/* Setup is executed once for each mbox pair */ +struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv) +{ + struct resource *resource; + int irq; + int res; + struct mbox *mbox; + + mbox = get_mbox_with_id(mbox_id); + if (mbox == NULL) { + dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n", + mbox_id); + goto exit; + } + + /* + * Check if mailbox has been allocated to someone else, + * otherwise allocate it + */ + if (mbox->allocated) { + dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n", + mbox_id); + mbox = NULL; + goto exit; + } + mbox->allocated = true; + + dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n", + mbox_id, (u32)mbox); + + mbox->client_data = priv; + mbox->cb = mbox_cb; + + /* Get addr for peer mailbox and ioremap it */ + resource = platform_get_resource_byname(mbox->pdev, + IORESOURCE_MEM, + "mbox_peer"); + if (resource == NULL) { + dev_err(&(mbox->pdev->dev), + "Unable to retrieve mbox peer resource\n"); + mbox = NULL; + goto exit; + } + dev_dbg(&(mbox->pdev->dev), + "Resource name: %s start: 0x%X, end: 0x%X\n", + resource->name, resource->start, resource->end); + mbox->virtbase_peer = + ioremap(resource->start, resource->end - resource->start); + if (!mbox->virtbase_peer) { + dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n"); + mbox = NULL; + goto exit; + } + dev_dbg(&(mbox->pdev->dev), + "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n", + resource->start, resource->end, (u32) mbox->virtbase_peer); + + /* Get addr for local mailbox and ioremap it */ + resource = platform_get_resource_byname(mbox->pdev, + IORESOURCE_MEM, + "mbox_local"); + if (resource == NULL) { + dev_err(&(mbox->pdev->dev), + "Unable to retrieve mbox local resource\n"); + mbox = NULL; + goto exit; + } + dev_dbg(&(mbox->pdev->dev), + "Resource name: %s start: 0x%X, end: 0x%X\n", + resource->name, resource->start, resource->end); + mbox->virtbase_local = + ioremap(resource->start, resource->end - resource->start); + if (!mbox->virtbase_local) { + dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n"); + mbox = NULL; + goto exit; + } + dev_dbg(&(mbox->pdev->dev), + "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n", + resource->start, resource->end, (u32) mbox->virtbase_peer); + + init_completion(&mbox->buffer_available); + mbox->client_blocked = 0; + + /* Get IRQ for mailbox and allocate it */ + irq = platform_get_irq_byname(mbox->pdev, "mbox_irq"); + if (irq < 0) { + dev_err(&(mbox->pdev->dev), + "Unable to retrieve mbox irq resource\n"); + mbox = NULL; + goto exit; + } + + dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq); + res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox); + if (res < 0) { + dev_err(&(mbox->pdev->dev), + "Unable to allocate mbox irq %d\n", irq); + mbox = NULL; + goto exit; + } + + /* Set up mailbox to not launch IRQ on free space in mailbox */ + writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE); + + /* + * Set up mailbox to launch IRQ on new message if we have + * a callback set. If not, do not raise IRQ, but keep message + * in FIFO for manual retrieval + */ + if (mbox_cb != NULL) + writel(MBOX_ENABLE_IRQ, + mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); + else + writel(MBOX_DISABLE_IRQ, + mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP); + +#if defined(CONFIG_DEBUG_FS) + res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo); + if (res != 0) + dev_warn(&(mbox->pdev->dev), + "Unable to create mbox sysfs entry"); + + (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL, + NULL, &mbox_operations); +#endif + + dev_info(&(mbox->pdev->dev), + "Mailbox driver with index %d initated!\n", mbox_id); + +exit: + return mbox; +} +EXPORT_SYMBOL(mbox_setup); + + +int __init mbox_probe(struct platform_device *pdev) +{ + struct mbox local_mbox; + struct mbox *mbox; + int res = 0; + dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev); + + memset(&local_mbox, 0x0, sizeof(struct mbox)); + + /* Associate our mbox data with the platform device */ + res = platform_device_add_data(pdev, + (void *) &local_mbox, + sizeof(struct mbox)); + if (res != 0) { + dev_err(&(pdev->dev), + "Unable to allocate driver platform data!\n"); + goto exit; + } + + mbox = (struct mbox *) pdev->dev.platform_data; + mbox->pdev = pdev; + mbox->write_index = 0; + mbox->read_index = 0; + + INIT_LIST_HEAD(&(mbox->list)); + list_add_tail(&(mbox->list), &mboxs); + + sprintf(mbox->name, "%s", MBOX_NAME); + spin_lock_init(&mbox->lock); + + dev_info(&(pdev->dev), "Mailbox driver loaded\n"); + +exit: + return res; +} + +static struct platform_driver mbox_driver = { + .driver = { + .name = MBOX_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init mbox_init(void) +{ + return platform_driver_probe(&mbox_driver, mbox_probe); +} + +module_init(mbox_init); + +void __exit mbox_exit(void) +{ + platform_driver_unregister(&mbox_driver); +} + +module_exit(mbox_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MBOX driver"); -- cgit v1.2.3 From e81fcc97350755e021c85b816877ae292b8f28d0 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 28 Sep 2010 15:45:41 +0100 Subject: ARM: 6417/1: ux500: build configuration for DB5500 mbox and modem irq handler This rounds of the DB5500 mailbox patches by adding the Kconfig options to enable the modem IRQs and mailboxes. Signed-off-by: Stefan Nilsson XK Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-ux500/Kconfig | 14 ++++++++++++++ arch/arm/mach-ux500/Makefile | 2 ++ 2 files changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 6625e5bbf4d6..23fe018cd10b 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -39,4 +39,18 @@ config UX500_DEBUG_UART Choose the UART on which kernel low-level debug messages should be output. +config U5500_MODEM_IRQ + bool "Modem IRQ support" + depends on MACH_U5500 + default y + help + Add support for handling IRQ:s from modem side + +config U5500_MBOX + bool "Mailbox support" + depends on MACH_U5500 && U5500_MODEM_IRQ + default y + help + Add support for U5500 mailbox communication with modem side + endif diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index 46dbaf640422..9e27a84433cb 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -11,3 +11,5 @@ obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o +obj-$(CONFIG_U5500_MODEM_IRQ) += modem_irq.o +obj-$(CONFIG_U5500_MBOX) += mbox.o -- cgit v1.2.3 From 1d7e3565946bf23fef5b3219be7df63b314478a2 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Wed, 29 Sep 2010 16:01:08 +0100 Subject: ARM: 6418/1: ux500: rename DB8500 DMA event line macros Change the DMA event line macros to have the name of the SoC. Also, have the event line number encoded in the macro since on DB5500 several event lines are present at multiple alternate numbers. Acked-by: Linus Walleij Signed-off-by: Rabin Vincent Signed-off-by: Russell King --- arch/arm/mach-ux500/devices-db8500.c | 18 +-- arch/arm/mach-ux500/ste-dma40-db8500.h | 258 ++++++++++++++++----------------- 2 files changed, 133 insertions(+), 143 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index f2e01a6dafe7..40032fecbc16 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -246,23 +246,23 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = { * Mapping between destination event lines and physical device address. * The event line is tied to a device and therefor the address is constant. */ -static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV]; +static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV]; /* Mapping between source event lines and physical device address */ -static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV]; +static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV]; /* Reserved event lines for memcpy only */ static int dma40_memcpy_event[] = { - STEDMA40_MEMCPY_TX_0, - STEDMA40_MEMCPY_TX_1, - STEDMA40_MEMCPY_TX_2, - STEDMA40_MEMCPY_TX_3, - STEDMA40_MEMCPY_TX_4, - STEDMA40_MEMCPY_TX_5, + DB8500_DMA_MEMCPY_TX_0, + DB8500_DMA_MEMCPY_TX_1, + DB8500_DMA_MEMCPY_TX_2, + DB8500_DMA_MEMCPY_TX_3, + DB8500_DMA_MEMCPY_TX_4, + DB8500_DMA_MEMCPY_TX_5, }; static struct stedma40_platform_data dma40_plat_data = { - .dev_len = STEDMA40_NR_DEV, + .dev_len = DB8500_DMA_NR_DEV, .dev_rx = dma40_rx_map, .dev_tx = dma40_tx_map, .memcpy = dma40_memcpy_event, diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h index 9d9d3797b3b0..a616419bea76 100644 --- a/arch/arm/mach-ux500/ste-dma40-db8500.h +++ b/arch/arm/mach-ux500/ste-dma40-db8500.h @@ -10,145 +10,135 @@ #ifndef STE_DMA40_DB8500_H #define STE_DMA40_DB8500_H -#define STEDMA40_NR_DEV 64 +#define DB8500_DMA_NR_DEV 64 enum dma_src_dev_type { - STEDMA40_DEV_SPI0_RX = 0, - STEDMA40_DEV_SD_MMC0_RX = 1, - STEDMA40_DEV_SD_MMC1_RX = 2, - STEDMA40_DEV_SD_MMC2_RX = 3, - STEDMA40_DEV_I2C1_RX = 4, - STEDMA40_DEV_I2C3_RX = 5, - STEDMA40_DEV_I2C2_RX = 6, - STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */ - STEDMA40_DEV_SSP0_RX = 8, - STEDMA40_DEV_SSP1_RX = 9, - STEDMA40_DEV_MCDE_RX = 10, - STEDMA40_DEV_UART2_RX = 11, - STEDMA40_DEV_UART1_RX = 12, - STEDMA40_DEV_UART0_RX = 13, - STEDMA40_DEV_MSP2_RX = 14, - STEDMA40_DEV_I2C0_RX = 15, - STEDMA40_DEV_USB_OTG_IEP_8 = 16, - STEDMA40_DEV_USB_OTG_IEP_1_9 = 17, - STEDMA40_DEV_USB_OTG_IEP_2_10 = 18, - STEDMA40_DEV_USB_OTG_IEP_3_11 = 19, - STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20, - STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21, - STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22, - STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23, - STEDMA40_DEV_SRC_SXA0_RX_TX = 24, - STEDMA40_DEV_SRC_SXA1_RX_TX = 25, - STEDMA40_DEV_SRC_SXA2_RX_TX = 26, - STEDMA40_DEV_SRC_SXA3_RX_TX = 27, - STEDMA40_DEV_SD_MM2_RX = 28, - STEDMA40_DEV_SD_MM0_RX = 29, - STEDMA40_DEV_MSP1_RX = 30, - /* - * This channel is either SlimBus or MSP, - * never both at the same time. - */ - STEDMA40_SLIM0_CH0_RX = 31, - STEDMA40_DEV_MSP0_RX = 31, - STEDMA40_DEV_SD_MM1_RX = 32, - STEDMA40_DEV_SPI2_RX = 33, - STEDMA40_DEV_I2C3_RX2 = 34, - STEDMA40_DEV_SPI1_RX = 35, - STEDMA40_DEV_USB_OTG_IEP_4_12 = 36, - STEDMA40_DEV_USB_OTG_IEP_5_13 = 37, - STEDMA40_DEV_USB_OTG_IEP_6_14 = 38, - STEDMA40_DEV_USB_OTG_IEP_7_15 = 39, - STEDMA40_DEV_SPI3_RX = 40, - STEDMA40_DEV_SD_MM3_RX = 41, - STEDMA40_DEV_SD_MM4_RX = 42, - STEDMA40_DEV_SD_MM5_RX = 43, - STEDMA40_DEV_SRC_SXA4_RX_TX = 44, - STEDMA40_DEV_SRC_SXA5_RX_TX = 45, - STEDMA40_DEV_SRC_SXA6_RX_TX = 46, - STEDMA40_DEV_SRC_SXA7_RX_TX = 47, - STEDMA40_DEV_CAC1_RX = 48, - /* RX channels 49 and 50 are unused */ - STEDMA40_DEV_MSHC_RX = 51, - STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52, - STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53, - STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54, - STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55, - /* RX channels 56 thru 60 are unused */ - STEDMA40_DEV_CAC0_RX = 61, - /* RX channels 62 and 63 are unused */ + DB8500_DMA_DEV0_SPI0_RX = 0, + DB8500_DMA_DEV1_SD_MMC0_RX = 1, + DB8500_DMA_DEV2_SD_MMC1_RX = 2, + DB8500_DMA_DEV3_SD_MMC2_RX = 3, + DB8500_DMA_DEV4_I2C1_RX = 4, + DB8500_DMA_DEV5_I2C3_RX = 5, + DB8500_DMA_DEV6_I2C2_RX = 6, + DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */ + DB8500_DMA_DEV8_SSP0_RX = 8, + DB8500_DMA_DEV9_SSP1_RX = 9, + DB8500_DMA_DEV10_MCDE_RX = 10, + DB8500_DMA_DEV11_UART2_RX = 11, + DB8500_DMA_DEV12_UART1_RX = 12, + DB8500_DMA_DEV13_UART0_RX = 13, + DB8500_DMA_DEV14_MSP2_RX = 14, + DB8500_DMA_DEV15_I2C0_RX = 15, + DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16, + DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17, + DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18, + DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19, + DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20, + DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21, + DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22, + DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23, + DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24, + DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25, + DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26, + DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27, + DB8500_DMA_DEV28_SD_MM2_RX = 28, + DB8500_DMA_DEV29_SD_MM0_RX = 29, + DB8500_DMA_DEV30_MSP1_RX = 30, + /* On DB8500v2, MSP3 RX replaces MSP1 RX */ + DB8500_DMA_DEV30_MSP3_RX = 30, + DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31, + DB8500_DMA_DEV32_SD_MM1_RX = 32, + DB8500_DMA_DEV33_SPI2_RX = 33, + DB8500_DMA_DEV34_I2C3_RX2 = 34, + DB8500_DMA_DEV35_SPI1_RX = 35, + DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36, + DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37, + DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38, + DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39, + DB8500_DMA_DEV40_SPI3_RX = 40, + DB8500_DMA_DEV41_SD_MM3_RX = 41, + DB8500_DMA_DEV42_SD_MM4_RX = 42, + DB8500_DMA_DEV43_SD_MM5_RX = 43, + DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44, + DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45, + DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46, + DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47, + DB8500_DMA_DEV48_CAC1_RX = 48, + /* 49, 50 and 51 are not used */ + DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52, + DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53, + DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54, + DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55, + /* 56, 57, 58, 59 and 60 are not used */ + DB8500_DMA_DEV61_CAC0_RX = 61, + /* 62 and 63 are not used */ }; enum dma_dest_dev_type { - STEDMA40_DEV_SPI0_TX = 0, - STEDMA40_DEV_SD_MMC0_TX = 1, - STEDMA40_DEV_SD_MMC1_TX = 2, - STEDMA40_DEV_SD_MMC2_TX = 3, - STEDMA40_DEV_I2C1_TX = 4, - STEDMA40_DEV_I2C3_TX = 5, - STEDMA40_DEV_I2C2_TX = 6, - STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */ - STEDMA40_DEV_SSP0_TX = 8, - STEDMA40_DEV_SSP1_TX = 9, - /* TX channel 10 is unused */ - STEDMA40_DEV_UART2_TX = 11, - STEDMA40_DEV_UART1_TX = 12, - STEDMA40_DEV_UART0_TX= 13, - STEDMA40_DEV_MSP2_TX = 14, - STEDMA40_DEV_I2C0_TX = 15, - STEDMA40_DEV_USB_OTG_OEP_8 = 16, - STEDMA40_DEV_USB_OTG_OEP_1_9 = 17, - STEDMA40_DEV_USB_OTG_OEP_2_10= 18, - STEDMA40_DEV_USB_OTG_OEP_3_11 = 19, - STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20, - STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21, - STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22, - STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23, - STEDMA40_DEV_DST_SXA0_RX_TX = 24, - STEDMA40_DEV_DST_SXA1_RX_TX = 25, - STEDMA40_DEV_DST_SXA2_RX_TX = 26, - STEDMA40_DEV_DST_SXA3_RX_TX = 27, - STEDMA40_DEV_SD_MM2_TX = 28, - STEDMA40_DEV_SD_MM0_TX = 29, - STEDMA40_DEV_MSP1_TX = 30, - /* - * This channel is either SlimBus or MSP, - * never both at the same time. - */ - STEDMA40_SLIM0_CH0_TX = 31, - STEDMA40_DEV_MSP0_TX = 31, - STEDMA40_DEV_SD_MM1_TX = 32, - STEDMA40_DEV_SPI2_TX = 33, - /* Secondary I2C3 channel */ - STEDMA40_DEV_I2C3_TX2 = 34, - STEDMA40_DEV_SPI1_TX = 35, - STEDMA40_DEV_USB_OTG_OEP_4_12 = 36, - STEDMA40_DEV_USB_OTG_OEP_5_13 = 37, - STEDMA40_DEV_USB_OTG_OEP_6_14 = 38, - STEDMA40_DEV_USB_OTG_OEP_7_15 = 39, - STEDMA40_DEV_SPI3_TX = 40, - STEDMA40_DEV_SD_MM3_TX = 41, - STEDMA40_DEV_SD_MM4_TX = 42, - STEDMA40_DEV_SD_MM5_TX = 43, - STEDMA40_DEV_DST_SXA4_RX_TX = 44, - STEDMA40_DEV_DST_SXA5_RX_TX = 45, - STEDMA40_DEV_DST_SXA6_RX_TX = 46, - STEDMA40_DEV_DST_SXA7_RX_TX = 47, - STEDMA40_DEV_CAC1_TX = 48, - STEDMA40_DEV_CAC1_TX_HAC1_TX = 49, - STEDMA40_DEV_HAC1_TX = 50, - STEDMA40_MEMCPY_TX_0 = 51, - STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52, - STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53, - STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54, - STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55, - STEDMA40_MEMCPY_TX_1 = 56, - STEDMA40_MEMCPY_TX_2 = 57, - STEDMA40_MEMCPY_TX_3 = 58, - STEDMA40_MEMCPY_TX_4 = 59, - STEDMA40_MEMCPY_TX_5 = 60, - STEDMA40_DEV_CAC0_TX = 61, - STEDMA40_DEV_CAC0_TX_HAC0_TX = 62, - STEDMA40_DEV_HAC0_TX = 63, + DB8500_DMA_DEV0_SPI0_TX = 0, + DB8500_DMA_DEV1_SD_MMC0_TX = 1, + DB8500_DMA_DEV2_SD_MMC1_TX = 2, + DB8500_DMA_DEV3_SD_MMC2_TX = 3, + DB8500_DMA_DEV4_I2C1_TX = 4, + DB8500_DMA_DEV5_I2C3_TX = 5, + DB8500_DMA_DEV6_I2C2_TX = 6, + DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */ + DB8500_DMA_DEV8_SSP0_TX = 8, + DB8500_DMA_DEV9_SSP1_TX = 9, + /* 10 is not used*/ + DB8500_DMA_DEV11_UART2_TX = 11, + DB8500_DMA_DEV12_UART1_TX = 12, + DB8500_DMA_DEV13_UART0_TX = 13, + DB8500_DMA_DEV14_MSP2_TX = 14, + DB8500_DMA_DEV15_I2C0_TX = 15, + DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16, + DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17, + DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18, + DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19, + DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20, + DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21, + DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22, + DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23, + DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24, + DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25, + DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26, + DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27, + DB8500_DMA_DEV28_SD_MM2_TX = 28, + DB8500_DMA_DEV29_SD_MM0_TX = 29, + DB8500_DMA_DEV30_MSP1_TX = 30, + DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31, + DB8500_DMA_DEV32_SD_MM1_TX = 32, + DB8500_DMA_DEV33_SPI2_TX = 33, + DB8500_DMA_DEV34_I2C3_TX2 = 34, + DB8500_DMA_DEV35_SPI1_TX = 35, + DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36, + DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37, + DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38, + DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39, + DB8500_DMA_DEV40_SPI3_TX = 40, + DB8500_DMA_DEV41_SD_MM3_TX = 41, + DB8500_DMA_DEV42_SD_MM4_TX = 42, + DB8500_DMA_DEV43_SD_MM5_TX = 43, + DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44, + DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45, + DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46, + DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47, + DB8500_DMA_DEV48_CAC1_TX = 48, + DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, + DB8500_DMA_DEV50_HAC1_TX = 50, + DB8500_DMA_MEMCPY_TX_0 = 51, + DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52, + DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53, + DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54, + DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55, + DB8500_DMA_MEMCPY_TX_1 = 56, + DB8500_DMA_MEMCPY_TX_2 = 57, + DB8500_DMA_MEMCPY_TX_3 = 58, + DB8500_DMA_MEMCPY_TX_4 = 59, + DB8500_DMA_MEMCPY_TX_5 = 60, + DB8500_DMA_DEV61_CAC0_TX = 61, + DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, + DB8500_DMA_DEV63_HAC0_TX = 63, }; #endif -- cgit v1.2.3 From 8234eaef8002cb8ba30920949b338d692508137a Mon Sep 17 00:00:00 2001 From: Alexander Shishkin Date: Wed, 4 Aug 2010 11:22:43 +0100 Subject: ARM: 6291/1: coresight: move struct tracectx inside etm driver This is done so as to be able to make use of the coresight components' registers in assembler code (like omap sleep code). Also, there shouldn't be any users of this structure outside the etm driver. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Alexander Shishkin Signed-off-by: Russell King --- arch/arm/include/asm/hardware/coresight.h | 12 ------------ arch/arm/kernel/etm.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index 212e47828c79..d84605175fc4 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -21,18 +21,6 @@ #define TRACER_RUNNING BIT(TRACER_RUNNING_BIT) #define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT) -struct tracectx { - unsigned int etb_bufsz; - void __iomem *etb_regs; - void __iomem *etm_regs; - unsigned long flags; - int ncmppairs; - int etm_portsz; - struct device *dev; - struct clk *emu_clk; - struct mutex mutex; -}; - #define TRACER_TIMEOUT 10000 #define etm_writel(t, v, x) \ diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 33c7077174db..a48d51257988 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c @@ -30,6 +30,21 @@ MODULE_LICENSE("GPL"); MODULE_AUTHOR("Alexander Shishkin"); +/* + * ETM tracer state + */ +struct tracectx { + unsigned int etb_bufsz; + void __iomem *etb_regs; + void __iomem *etm_regs; + unsigned long flags; + int ncmppairs; + int etm_portsz; + struct device *dev; + struct clk *emu_clk; + struct mutex mutex; +}; + static struct tracectx tracer; static inline bool trace_isrunning(struct tracectx *t) -- cgit v1.2.3 From 9f5336915bc47947230290a1a384de95803f815a Mon Sep 17 00:00:00 2001 From: Alexander Shishkin Date: Wed, 4 Aug 2010 11:26:27 +0100 Subject: ARM: 6293/1: coresight: cosmetic fixes Use BIT() macro whenever it is sensible to do so. Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Alexander Shishkin Signed-off-by: Russell King --- arch/arm/include/asm/hardware/coresight.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index d84605175fc4..7ecd793b8f5a 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -100,10 +100,10 @@ /* ETM status register, "ETM Architecture", 3.3.2 */ #define ETMR_STATUS (0x10) -#define ETMST_OVERFLOW (1 << 0) -#define ETMST_PROGBIT (1 << 1) -#define ETMST_STARTSTOP (1 << 2) -#define ETMST_TRIGGER (1 << 3) +#define ETMST_OVERFLOW BIT(0) +#define ETMST_PROGBIT BIT(1) +#define ETMST_STARTSTOP BIT(2) +#define ETMST_TRIGGER BIT(3) #define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) #define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) @@ -111,7 +111,7 @@ #define ETMR_TRACEENCTRL2 0x1c #define ETMR_TRACEENCTRL 0x24 -#define ETMTE_INCLEXCL (1 << 24) +#define ETMTE_INCLEXCL BIT(24) #define ETMR_TRACEENEVT 0x20 #define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ ETMCTRL_DATA_DO_ADDR | \ @@ -134,12 +134,12 @@ #define ETBR_CTRL 0x20 #define ETBR_FORMATTERCTRL 0x304 #define ETBFF_ENFTC 1 -#define ETBFF_ENFCONT (1 << 1) -#define ETBFF_FONFLIN (1 << 4) -#define ETBFF_MANUAL_FLUSH (1 << 6) -#define ETBFF_TRIGIN (1 << 8) -#define ETBFF_TRIGEVT (1 << 9) -#define ETBFF_TRIGFL (1 << 10) +#define ETBFF_ENFCONT BIT(1) +#define ETBFF_FONFLIN BIT(4) +#define ETBFF_MANUAL_FLUSH BIT(6) +#define ETBFF_TRIGIN BIT(8) +#define ETBFF_TRIGEVT BIT(9) +#define ETBFF_TRIGFL BIT(10) #define etb_writel(t, v, x) \ (__raw_writel((v), (t)->etb_regs + (x))) -- cgit v1.2.3 From 055d1965161bde96207371e7d31eb776c0f7790d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 2 Sep 2010 09:14:21 +0100 Subject: ARM: 6349/1: sa1111: move __sa1111_probe() to .devinit.text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit __sa1111_probe is only called by sa1111_probe that lives in .devinit.text. So it's save to move the former to .devinit.text, too. Acked-by: Kristoffer Ericson Signed-off-by: Uwe Kleine-König Signed-off-by: Russell King --- arch/arm/common/sa1111.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 517d50ddbeb3..c0258a8c103b 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -678,7 +678,7 @@ out: * %-EBUSY physical address already marked in-use. * %0 successful. */ -static int +static int __devinit __sa1111_probe(struct device *me, struct resource *mem, int irq) { struct sa1111 *sachip; -- cgit v1.2.3 From 971acb9b420ea1662dd3c48184c4315f87643be5 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Sep 2010 08:16:30 +0100 Subject: ARM: Simplify SMP/SCU/TWD dependencies All platforms which currently support SMP also support the ARM SCU and ARM TWD blocks, so it's pointless to make these config symbols conditional on the platform symbols which SMP is already conditional on. Signed-off-by: Russell King --- arch/arm/Kconfig | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 88c97bc7a6f5..6a939e64cbd7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1167,13 +1167,13 @@ source "kernel/time/Kconfig" config SMP bool "Symmetric Multi-Processing (EXPERIMENTAL)" - depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\ - MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\ - ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4) + depends on EXPERIMENTAL depends on GENERIC_CLOCKEVENTS + depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ + MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\ + ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 select USE_GENERIC_SMP_HELPERS - select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\ - ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 + select HAVE_ARM_SCU help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If @@ -1241,12 +1241,9 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" - depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ - REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ - ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4) + depends on SMP default y - select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 || \ - ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS + select HAVE_ARM_TWD help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system -- cgit v1.2.3 From 067173526c3bbc2eaeefcf6b7b2a9d998b9e8042 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Sep 2010 16:14:20 +0100 Subject: ARM: Provide common header for hard_smp_processor_id() Provide a common header to read the SMP CPU number from the MPIDR. Signed-off-by: Russell King --- arch/arm/include/asm/smp_mpidr.h | 12 ++++++++++++ arch/arm/mach-realview/include/mach/smp.h | 10 +--------- arch/arm/mach-s5pv310/include/mach/smp.h | 9 +-------- arch/arm/mach-tegra/include/mach/smp.h | 10 +--------- arch/arm/mach-ux500/include/mach/smp.h | 9 +-------- arch/arm/mach-vexpress/include/mach/smp.h | 9 +-------- arch/arm/plat-omap/include/plat/smp.h | 12 +----------- 7 files changed, 18 insertions(+), 53 deletions(-) create mode 100644 arch/arm/include/asm/smp_mpidr.h (limited to 'arch/arm') diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h new file mode 100644 index 000000000000..7da7105e83e5 --- /dev/null +++ b/arch/arm/include/asm/smp_mpidr.h @@ -0,0 +1,12 @@ +#ifndef ASMARM_SMP_MIDR_H +#define ASMARM_SMP_MIDR_H + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5\n" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +#endif diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h index dd53892d44a7..d3cd265cb058 100644 --- a/arch/arm/mach-realview/include/mach/smp.h +++ b/arch/arm/mach-realview/include/mach/smp.h @@ -1,16 +1,8 @@ #ifndef ASMARM_ARCH_SMP_H #define ASMARM_ARCH_SMP_H - #include - -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) +#include /* * We use IRQ1 as the IPI diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h index 990f3ba88a1f..b7ec252384f4 100644 --- a/arch/arm/mach-s5pv310/include/mach/smp.h +++ b/arch/arm/mach-s5pv310/include/mach/smp.h @@ -7,17 +7,10 @@ #define ASM_ARCH_SMP_H __FILE__ #include +#include extern void __iomem *gic_cpu_base_addr; -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x03; \ - }) - /* * We use IRQ1 as the IPI */ diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h index 8b42dab79a70..e4a34a35a544 100644 --- a/arch/arm/mach-tegra/include/mach/smp.h +++ b/arch/arm/mach-tegra/include/mach/smp.h @@ -1,16 +1,8 @@ #ifndef ASMARM_ARCH_SMP_H #define ASMARM_ARCH_SMP_H - #include - -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) +#include /* * We use IRQ1 as the IPI diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h index b59f7bc9725d..197e8417375e 100644 --- a/arch/arm/mach-ux500/include/mach/smp.h +++ b/arch/arm/mach-ux500/include/mach/smp.h @@ -10,18 +10,11 @@ #define ASMARM_ARCH_SMP_H #include +#include /* This is required to wakeup the secondary core */ extern void u8500_secondary_startup(void); -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) - /* * We use IRQ1 as the IPI */ diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h index 72a9621ed087..5a6da4fd247e 100644 --- a/arch/arm/mach-vexpress/include/mach/smp.h +++ b/arch/arm/mach-vexpress/include/mach/smp.h @@ -2,14 +2,7 @@ #define __MACH_SMP_H #include - -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) +#include /* * We use IRQ1 as the IPI diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h index 5177a9c5a25a..ecd6a488c497 100644 --- a/arch/arm/plat-omap/include/plat/smp.h +++ b/arch/arm/plat-omap/include/plat/smp.h @@ -18,6 +18,7 @@ #define OMAP_ARCH_SMP_H #include +#include /* Needed for secondary core boot */ extern void omap_secondary_startup(void); @@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask) gic_raise_softirq(mask, 1); } -/* - * Read MPIDR: Multiprocessor affinity register - */ -#define hard_smp_processor_id() \ - ({ \ - unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5" \ - : "=r" (cpunum)); \ - cpunum &= 0x0F; \ - }) - #endif -- cgit v1.2.3 From f00ec48fadf5e37e7889f14cff900aa70d18b644 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Sep 2010 10:47:48 +0100 Subject: ARM: Allow SMP kernels to boot on UP systems UP systems do not implement all the instructions that SMP systems have, so in order to boot a SMP kernel on a UP system, we need to rewrite parts of the kernel. Do this using an 'alternatives' scheme, where the kernel code and data is modified prior to initialization to replace the SMP instructions, thereby rendering the problematical code ineffectual. We use the linker to generate a list of 32-bit word locations and their replacement values, and run through these replacements when we detect a UP system. Signed-off-by: Russell King --- arch/arm/Kconfig | 13 +++++++++++ arch/arm/include/asm/assembler.h | 27 ++++++++++++++++++++-- arch/arm/include/asm/smp_mpidr.h | 7 +++++- arch/arm/include/asm/smp_plat.h | 15 ++++++++++++ arch/arm/include/asm/tlbflush.h | 24 +++++++++++++------ arch/arm/kernel/entry-armv.S | 11 ++++----- arch/arm/kernel/head.S | 50 ++++++++++++++++++++++++++++++++++++++++ arch/arm/kernel/setup.c | 4 +++- arch/arm/kernel/vmlinux.lds.S | 11 +++++++++ arch/arm/mm/cache-v7.S | 14 ++++------- arch/arm/mm/mmu.c | 46 +++++++++++++++++------------------- arch/arm/mm/proc-v6.S | 43 ++++++++++++++++++++++------------ arch/arm/mm/proc-v7.S | 41 +++++++++++++++++++++----------- arch/arm/mm/tlb-v7.S | 33 ++++++++++---------------- 14 files changed, 237 insertions(+), 102 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6a939e64cbd7..f6cdc21b562c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1191,6 +1191,19 @@ config SMP If you don't know what to do here, say N. +config SMP_ON_UP + bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)" + depends on EXPERIMENTAL + depends on SMP && !XIP && !THUMB2_KERNEL + default y + help + SMP kernels contain instructions which fail on non-SMP processors. + Enabling this option allows the kernel to modify itself to make + these instructions safe. Disabling it allows about 1K of space + savings. + + If you don't know what to do here, say Y. + config HAVE_ARM_SCU bool depends on SMP diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 6e8f05c8a1c8..062b58c029ab 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -154,16 +154,39 @@ .long 9999b,9001f; \ .popsection +#ifdef CONFIG_SMP +#define ALT_SMP(instr...) \ +9998: instr +#define ALT_UP(instr...) \ + .pushsection ".alt.smp.init", "a" ;\ + .long 9998b ;\ + instr ;\ + .popsection +#define ALT_UP_B(label) \ + .equ up_b_offset, label - 9998b ;\ + .pushsection ".alt.smp.init", "a" ;\ + .long 9998b ;\ + b . + up_b_offset ;\ + .popsection +#else +#define ALT_SMP(instr...) +#define ALT_UP(instr...) instr +#define ALT_UP_B(label) b label +#endif + /* * SMP data memory barrier */ .macro smp_dmb #ifdef CONFIG_SMP #if __LINUX_ARM_ARCH__ >= 7 - dmb + ALT_SMP(dmb) #elif __LINUX_ARM_ARCH__ == 6 - mcr p15, 0, r0, c7, c10, 5 @ dmb + ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb +#else +#error Incompatible SMP platform #endif + ALT_UP(nop) #endif .endm diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h index 7da7105e83e5..6a9307d64900 100644 --- a/arch/arm/include/asm/smp_mpidr.h +++ b/arch/arm/include/asm/smp_mpidr.h @@ -4,7 +4,12 @@ #define hard_smp_processor_id() \ ({ \ unsigned int cpunum; \ - __asm__("mrc p15, 0, %0, c0, c0, 5\n" \ + __asm__("\n" \ + "1: mrc p15, 0, %0, c0, c0, 5\n" \ + " .pushsection \".alt.smp.init\", \"a\"\n"\ + " .long 1b\n" \ + " mov %0, #0\n" \ + " .popsection" \ : "=r" (cpunum)); \ cpunum &= 0x0F; \ }) diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h index e6215305544a..7de5aa56c18b 100644 --- a/arch/arm/include/asm/smp_plat.h +++ b/arch/arm/include/asm/smp_plat.h @@ -18,4 +18,19 @@ static inline int cache_ops_need_broadcast(void) return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1; } +/* + * Return true if we are running on a SMP platform + */ +static inline bool is_smp(void) +{ +#ifndef CONFIG_SMP + return false; +#elif defined(CONFIG_SMP_ON_UP) + extern unsigned int smp_on_up; + return !!smp_on_up; +#else + return true; +#endif +} + #endif diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 33b546ae72d4..cf2f018492e0 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -70,6 +70,10 @@ #undef _TLB #undef MULTI_TLB +#ifdef CONFIG_SMP_ON_UP +#define MULTI_TLB 1 +#endif + #define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) #ifdef CONFIG_CPU_TLB_V3 @@ -185,17 +189,23 @@ # define v6wbi_always_flags (-1UL) #endif -#ifdef CONFIG_SMP -#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \ +#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \ TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) -#else -#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \ +#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \ TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) -#endif #ifdef CONFIG_CPU_TLB_V7 -# define v7wbi_possible_flags v7wbi_tlb_flags -# define v7wbi_always_flags v7wbi_tlb_flags + +# ifdef CONFIG_SMP_ON_UP +# define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up) +# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up) +# elif defined(CONFIG_SMP) +# define v7wbi_possible_flags v7wbi_tlb_flags_smp +# define v7wbi_always_flags v7wbi_tlb_flags_smp +# else +# define v7wbi_possible_flags v7wbi_tlb_flags_up +# define v7wbi_always_flags v7wbi_tlb_flags_up +# endif # ifdef _TLB # define MULTI_TLB 1 # else diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index bb8e93a76407..c09e3573c5de 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -46,7 +46,8 @@ * this macro assumes that irqstat (r6) and base (r5) are * preserved from get_irqnr_and_base above */ - test_for_ipi r0, r6, r5, lr + ALT_SMP(test_for_ipi r0, r6, r5, lr) + ALT_UP_B(9997f) movne r0, sp adrne lr, BSYM(1b) bne do_IPI @@ -57,6 +58,7 @@ adrne lr, BSYM(1b) bne do_local_timer #endif +9997: #endif .endm @@ -965,11 +967,8 @@ kuser_cmpxchg_fixup: beq 1b rsbs r0, r3, #0 /* beware -- each __kuser slot must be 8 instructions max */ -#ifdef CONFIG_SMP - b __kuser_memory_barrier -#else - usr_ret lr -#endif + ALT_SMP(b __kuser_memory_barrier) + ALT_UP(usr_ret lr) #endif diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index eb62bf947212..b44d21e1e344 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -86,6 +86,9 @@ ENTRY(stext) movs r8, r5 @ invalid machine (r5=0)? beq __error_a @ yes, error 'a' bl __vet_atags +#ifdef CONFIG_SMP_ON_UP + bl __fixup_smp +#endif bl __create_page_tables /* @@ -333,4 +336,51 @@ __create_page_tables: ENDPROC(__create_page_tables) .ltorg +#ifdef CONFIG_SMP_ON_UP +__fixup_smp: + mov r7, #0x00070000 + orr r6, r7, #0xff000000 @ mask 0xff070000 + orr r7, r7, #0x41000000 @ val 0x41070000 + and r0, r9, r6 + teq r0, r7 @ ARM CPU and ARMv6/v7? + bne __fixup_smp_on_up @ no, assume UP + + orr r6, r6, #0x0000ff00 + orr r6, r6, #0x000000f0 @ mask 0xff07fff0 + orr r7, r7, #0x0000b000 + orr r7, r7, #0x00000020 @ val 0x4107b020 + and r0, r9, r6 + teq r0, r7 @ ARM 11MPCore? + moveq pc, lr @ yes, assume SMP + + mrc p15, 0, r0, c0, c0, 5 @ read MPIDR + tst r0, #1 << 31 + movne pc, lr @ bit 31 => SMP + +__fixup_smp_on_up: + adr r0, 1f + ldmia r0, {r3, r6, r7} + sub r3, r0, r3 + add r6, r6, r3 + add r7, r7, r3 +2: cmp r6, r7 + ldmia r6!, {r0, r4} + strlo r4, [r0, r3] + blo 2b + mov pc, lr +ENDPROC(__fixup_smp) + +1: .word . + .word __smpalt_begin + .word __smpalt_end + + .pushsection .data + .globl smp_on_up +smp_on_up: + ALT_SMP(.long 1) + ALT_UP(.long 0) + .popsection + +#endif + #include "head-common.S" diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d5231ae7355a..5a82c39ca85e 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -825,7 +826,8 @@ void __init setup_arch(char **cmdline_p) request_standard_resources(&meminfo, mdesc); #ifdef CONFIG_SMP - smp_init_cpus(); + if (is_smp()) + smp_init_cpus(); #endif reserve_crashkernel(); diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index b16c07914b55..fd5750b8ac84 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -40,6 +40,11 @@ SECTIONS __tagtable_begin = .; *(.taglist.init) __tagtable_end = .; +#ifdef CONFIG_SMP_ON_UP + __smpalt_begin = .; + *(.alt.smp.init) + __smpalt_end = .; +#endif INIT_SETUP(16) @@ -237,6 +242,12 @@ SECTIONS /* Default discards */ DISCARDS + +#ifndef CONFIG_SMP_ON_UP + /DISCARD/ : { + *(.alt.smp.init) + } +#endif } /* diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 37c8157e116e..e8ea1a071f43 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all) THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) bl v7_flush_dcache_all mov r0, #0 -#ifdef CONFIG_SMP - mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable -#else - mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate -#endif + ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable + ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) mov pc, lr @@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range) cmp r0, r1 blo 1b mov r0, #0 -#ifdef CONFIG_SMP - mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable -#else - mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB -#endif + ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable + ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB dsb isb mov pc, lr diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 6a3a2d0cd6db..e2335811c02e 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -310,9 +310,8 @@ static void __init build_mem_type_table(void) cachepolicy = CPOLICY_WRITEBACK; ecc_mask = 0; } -#ifdef CONFIG_SMP - cachepolicy = CPOLICY_WRITEALLOC; -#endif + if (is_smp()) + cachepolicy = CPOLICY_WRITEALLOC; /* * Strip out features not present on earlier architectures. @@ -406,13 +405,11 @@ static void __init build_mem_type_table(void) cp = &cache_policies[cachepolicy]; vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; -#ifndef CONFIG_SMP /* * Only use write-through for non-SMP systems */ - if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) + if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; -#endif /* * Enable CPU-specific coherency if supported. @@ -436,22 +433,23 @@ static void __init build_mem_type_table(void) mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; -#ifdef CONFIG_SMP - /* - * Mark memory with the "shared" attribute for SMP systems - */ - user_pgprot |= L_PTE_SHARED; - kern_pgprot |= L_PTE_SHARED; - vecs_pgprot |= L_PTE_SHARED; - mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; - mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; - mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; - mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; - mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; - mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; - mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; - mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; -#endif + if (is_smp()) { + /* + * Mark memory with the "shared" attribute + * for SMP systems + */ + user_pgprot |= L_PTE_SHARED; + kern_pgprot |= L_PTE_SHARED; + vecs_pgprot |= L_PTE_SHARED; + mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; + mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; + mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; + mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; + } } /* @@ -829,8 +827,7 @@ static void __init sanity_check_meminfo(void) * rather difficult. */ reason = "with VIPT aliasing cache"; -#ifdef CONFIG_SMP - } else if (tlb_ops_need_broadcast()) { + } else if (is_smp() && tlb_ops_need_broadcast()) { /* * kmap_high needs to occasionally flush TLB entries, * however, if the TLB entries need to be broadcast @@ -840,7 +837,6 @@ static void __init sanity_check_meminfo(void) * (must not be called with irqs off) */ reason = "without hardware TLB ops broadcasting"; -#endif } if (reason) { printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 22aac8515196..b95662dedb64 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -30,13 +30,10 @@ #define TTB_RGN_WT (2 << 3) #define TTB_RGN_WB (3 << 3) -#ifndef CONFIG_SMP -#define TTB_FLAGS TTB_RGN_WBWA -#define PMD_FLAGS PMD_SECT_WB -#else -#define TTB_FLAGS TTB_RGN_WBWA|TTB_S -#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S -#endif +#define TTB_FLAGS_UP TTB_RGN_WBWA +#define PMD_FLAGS_UP PMD_SECT_WB +#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S +#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S ENTRY(cpu_v6_proc_init) mov pc, lr @@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm) #ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id - orr r0, r0, #TTB_FLAGS + ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) + ALT_UP(orr r0, r0, #TTB_FLAGS_UP) mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB mcr p15, 0, r2, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 @@ -156,9 +154,11 @@ cpu_pj4_name: */ __v6_setup: #ifdef CONFIG_SMP - mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode + ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode + ALT_UP(nop) orr r0, r0, #0x20 - mcr p15, 0, r0, c1, c0, 1 + ALT_SMP(mcr p15, 0, r0, c1, c0, 1) + ALT_UP(nop) #endif mov r0, #0 @@ -169,7 +169,8 @@ __v6_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r0, c2, c0, 2 @ TTB control register - orr r4, r4, #TTB_FLAGS + ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) + ALT_UP(orr r4, r4, #TTB_FLAGS_UP) mcr p15, 0, r4, c2, c0, 1 @ load TTB1 #endif /* CONFIG_MMU */ adr r5, v6_crval @@ -225,10 +226,16 @@ cpu_elf_name: __v6_proc_info: .long 0x0007b000 .long 0x0007f000 - .long PMD_TYPE_SECT | \ + ALT_SMP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_FLAGS_SMP) + ALT_UP(.long \ + PMD_TYPE_SECT | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ | \ - PMD_FLAGS + PMD_FLAGS_UP) .long PMD_TYPE_SECT | \ PMD_SECT_XN | \ PMD_SECT_AP_WRITE | \ @@ -249,10 +256,16 @@ __v6_proc_info: __pj4_v6_proc_info: .long 0x560f5810 .long 0xff0ffff0 - .long PMD_TYPE_SECT | \ + ALT_SMP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_FLAGS_SMP) + ALT_UP(.long \ + PMD_TYPE_SECT | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ | \ - PMD_FLAGS + PMD_FLAGS_UP) .long PMD_TYPE_SECT | \ PMD_SECT_XN | \ PMD_SECT_AP_WRITE | \ diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7563ff0141bd..df422fee1cb6 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -30,15 +30,13 @@ #define TTB_IRGN_WT ((1 << 0) | (0 << 6)) #define TTB_IRGN_WB ((1 << 0) | (1 << 6)) -#ifndef CONFIG_SMP /* PTWs cacheable, inner WB not shareable, outer WB not shareable */ -#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB -#define PMD_FLAGS PMD_SECT_WB -#else +#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB +#define PMD_FLAGS_UP PMD_SECT_WB + /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ -#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA -#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S -#endif +#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA +#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S ENTRY(cpu_v7_proc_init) mov pc, lr @@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id - orr r0, r0, #TTB_FLAGS + ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) + ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB #endif @@ -188,7 +187,8 @@ cpu_v7_name: */ __v7_ca9mp_setup: #ifdef CONFIG_SMP - mrc p15, 0, r0, c1, c0, 1 + ALT_SMP(mrc p15, 0, r0, c1, c0, 1) + ALT_UP(mov r0, #(1 << 6)) @ fake it for UP tst r0, #(1 << 6) @ SMP/nAMP mode enabled? orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting @@ -262,7 +262,8 @@ __v7_setup: #ifdef CONFIG_MMU mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r10, c2, c0, 2 @ TTB control register - orr r4, r4, #TTB_FLAGS + ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) + ALT_UP(orr r4, r4, #TTB_FLAGS_UP) mcr p15, 0, r4, c2, c0, 1 @ load TTB1 mov r10, #0x1f @ domains 0, 1 = manager mcr p15, 0, r10, c3, c0, 0 @ load domain access register @@ -354,10 +355,16 @@ cpu_elf_name: __v7_ca9mp_proc_info: .long 0x410fc090 @ Required ID value .long 0xff0ffff0 @ Mask for ID - .long PMD_TYPE_SECT | \ + ALT_SMP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_FLAGS_SMP) + ALT_UP(.long \ + PMD_TYPE_SECT | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ | \ - PMD_FLAGS + PMD_FLAGS_UP) .long PMD_TYPE_SECT | \ PMD_SECT_XN | \ PMD_SECT_AP_WRITE | \ @@ -380,10 +387,16 @@ __v7_ca9mp_proc_info: __v7_proc_info: .long 0x000f0000 @ Required ID value .long 0x000f0000 @ Mask for ID - .long PMD_TYPE_SECT | \ + ALT_SMP(.long \ + PMD_TYPE_SECT | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ | \ + PMD_FLAGS_SMP) + ALT_UP(.long \ + PMD_TYPE_SECT | \ PMD_SECT_AP_WRITE | \ PMD_SECT_AP_READ | \ - PMD_FLAGS + PMD_FLAGS_UP) .long PMD_TYPE_SECT | \ PMD_SECT_XN | \ PMD_SECT_AP_WRITE | \ diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index f3f288a9546d..53cd5b454673 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -13,6 +13,7 @@ */ #include #include +#include #include #include #include @@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range) orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA mov r1, r1, lsl #PAGE_SHIFT 1: -#ifdef CONFIG_SMP - mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) -#else - mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA -#endif + ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) + ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA + add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b mov ip, #0 -#ifdef CONFIG_SMP - mcr p15, 0, ip, c7, c1, 6 @ flush BTAC/BTB Inner Shareable -#else - mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB -#endif + ALT_SMP(mcr p15, 0, ip, c7, c1, 6) @ flush BTAC/BTB Inner Shareable + ALT_UP(mcr p15, 0, ip, c7, c5, 6) @ flush BTAC/BTB dsb mov pc, lr ENDPROC(v7wbi_flush_user_tlb_range) @@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range) mov r0, r0, lsl #PAGE_SHIFT mov r1, r1, lsl #PAGE_SHIFT 1: -#ifdef CONFIG_SMP - mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) -#else - mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA -#endif + ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) + ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b mov r2, #0 -#ifdef CONFIG_SMP - mcr p15, 0, r2, c7, c1, 6 @ flush BTAC/BTB Inner Shareable -#else - mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB -#endif + ALT_SMP(mcr p15, 0, r2, c7, c1, 6) @ flush BTAC/BTB Inner Shareable + ALT_UP(mcr p15, 0, r2, c7, c5, 6) @ flush BTAC/BTB dsb isb mov pc, lr @@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range) ENTRY(v7wbi_tlb_fns) .long v7wbi_flush_user_tlb_range .long v7wbi_flush_kern_tlb_range - .long v7wbi_tlb_flags + ALT_SMP(.long v7wbi_tlb_flags_smp) + ALT_UP(.long v7wbi_tlb_flags_up) .size v7wbi_tlb_fns, . - v7wbi_tlb_fns -- cgit v1.2.3 From f9e417e901e891d139f4d5fd750959e4a862d9f7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 21 Sep 2010 00:43:19 +0100 Subject: ARM: 6402/1: Don't send IPI in smp_send_stop if there's only one CPU No need to send IPI if there's one CPU, especially when booting systems with CONFIG_SMP_ON_UP that may not even support IPI. Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/kernel/smp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 40dc74f2b27f..32e16da5cbce 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -567,7 +567,8 @@ void smp_send_stop(void) { cpumask_t mask = cpu_online_map; cpu_clear(smp_processor_id(), mask); - send_ipi_message(&mask, IPI_CPU_STOP); + if (!cpus_empty(mask)) + send_ipi_message(&mask, IPI_CPU_STOP); } /* -- cgit v1.2.3 From 81d11955bf0b5ae25e3adbec930cd84840385dae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 21 Sep 2010 17:16:40 +0100 Subject: ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UP Do this by adding flush_icache_all to cache_fns for ARMv6 and 7. As flush_icache_all may neeed to be called from flush_kern_cache_all, add it as the first entry in the cache_fns. Note that now we can remove the ARM_ERRATA_411920 dependency to !SMP so it can be selected on UP ARMv6 processors, such as omap2. Signed-off-by: Tony Lindgren Signed-off-by: Anand Gadiyar Signed-off-by: Russell King --- arch/arm/Kconfig | 2 +- arch/arm/include/asm/cacheflush.h | 56 ++++++++++++++++++++++++++++----------- arch/arm/mm/cache-v6.S | 30 +++++++++++++-------- arch/arm/mm/cache-v7.S | 16 +++++++++++ 4 files changed, 77 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f6cdc21b562c..7562f884f2c5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1002,7 +1002,7 @@ endif config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" - depends on CPU_V6 && !SMP + depends on CPU_V6 help Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 4656a24058d2..a3db768ee5cc 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -156,6 +156,12 @@ * Please note that the implementation of these, and the required * effects are cache-type (VIVT/VIPT/PIPT) specific. * + * flush_icache_all() + * + * Unconditionally clean and invalidate the entire icache. + * Currently only needed for cache-v6.S and cache-v7.S, see + * __flush_icache_all for the generic implementation. + * * flush_kern_all() * * Unconditionally clean and invalidate the entire cache. @@ -206,6 +212,7 @@ */ struct cpu_cache_fns { + void (*flush_icache_all)(void); void (*flush_kern_all)(void); void (*flush_user_all)(void); void (*flush_user_range)(unsigned long, unsigned long, unsigned int); @@ -227,6 +234,7 @@ struct cpu_cache_fns { extern struct cpu_cache_fns cpu_cache; +#define __cpuc_flush_icache_all cpu_cache.flush_icache_all #define __cpuc_flush_kern_all cpu_cache.flush_kern_all #define __cpuc_flush_user_all cpu_cache.flush_user_all #define __cpuc_flush_user_range cpu_cache.flush_user_range @@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache; #else +#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) @@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache; #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) +extern void __cpuc_flush_icache_all(void); extern void __cpuc_flush_kern_all(void); extern void __cpuc_flush_user_all(void); extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); @@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, /* * Convert calls to our calling convention. */ + +/* Invalidate I-cache */ +#define __flush_icache_all_generic() \ + asm("mcr p15, 0, %0, c7, c5, 0" \ + : : "r" (0)); + +/* Invalidate I-cache inner shareable */ +#define __flush_icache_all_v7_smp() \ + asm("mcr p15, 0, %0, c7, c1, 0" \ + : : "r" (0)); + +/* + * Optimized __flush_icache_all for the common cases. Note that UP ARMv7 + * will fall through to use __flush_icache_all_generic. + */ +#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) || \ + defined(CONFIG_SMP_ON_UP) +#define __flush_icache_preferred __cpuc_flush_icache_all +#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) +#define __flush_icache_preferred __flush_icache_all_v7_smp +#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920) +#define __flush_icache_preferred __cpuc_flush_icache_all +#else +#define __flush_icache_preferred __flush_icache_all_generic +#endif + +static inline void __flush_icache_all(void) +{ + __flush_icache_preferred(); +} + #define flush_cache_all() __cpuc_flush_kern_all() static inline void vivt_flush_cache_mm(struct mm_struct *mm) @@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 extern void flush_dcache_page(struct page *); -static inline void __flush_icache_all(void) -{ -#ifdef CONFIG_ARM_ERRATA_411920 - extern void v6_icache_inval_all(void); - v6_icache_inval_all(); -#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7 - asm("mcr p15, 0, %0, c7, c1, 0 @ invalidate I-cache inner shareable\n" - : - : "r" (0)); -#else - asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" - : - : "r" (0)); -#endif -} static inline void flush_kernel_vmap_range(void *addr, int size) { if ((cache_is_vivt() || cache_is_vipt_aliasing())) diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 86aa689ef1aa..99fa688dfadd 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -21,18 +21,22 @@ #define D_CACHE_LINE_SIZE 32 #define BTB_FLUSH_SIZE 8 -#ifdef CONFIG_ARM_ERRATA_411920 /* - * Invalidate the entire I cache (this code is a workaround for the ARM1136 - * erratum 411920 - Invalidate Instruction Cache operation can fail. This - * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore. + * v6_flush_icache_all() + * + * Flush the whole I-cache. * - * Registers: - * r0 - set to 0 - * r1 - corrupted + * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail. + * This erratum is present in 1136, 1156 and 1176. It does not affect the + * MPCore. + * + * Registers: + * r0 - set to 0 + * r1 - corrupted */ -ENTRY(v6_icache_inval_all) +ENTRY(v6_flush_icache_all) mov r0, #0 +#ifdef CONFIG_ARM_ERRATA_411920 mrs r1, cpsr cpsid ifa @ disable interrupts mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache @@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all) .rept 11 @ ARM Ltd recommends at least nop @ 11 NOPs .endr - mov pc, lr +#else + mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache #endif + mov pc, lr +ENDPROC(v6_flush_icache_all) /* * v6_flush_cache_all() @@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all) #ifndef CONFIG_ARM_ERRATA_411920 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate #else - b v6_icache_inval_all + b v6_flush_icache_all #endif #else mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate @@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range) #ifndef CONFIG_ARM_ERRATA_411920 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate #else - b v6_icache_inval_all + b v6_flush_icache_all #endif #else mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB @@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area) .type v6_cache_fns, #object ENTRY(v6_cache_fns) + .long v6_flush_icache_all .long v6_flush_kern_cache_all .long v6_flush_user_cache_all .long v6_flush_user_cache_range diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index e8ea1a071f43..a3ebf7a4f49b 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -17,6 +17,21 @@ #include "proc-macros.S" +/* + * v7_flush_icache_all() + * + * Flush the whole I-cache. + * + * Registers: + * r0 - set to 0 + */ +ENTRY(v7_flush_icache_all) + mov r0, #0 + ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable + ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate + mov pc, lr +ENDPROC(v7_flush_icache_all) + /* * v7_flush_dcache_all() * @@ -303,6 +318,7 @@ ENDPROC(v7_dma_unmap_area) .type v7_cache_fns, #object ENTRY(v7_cache_fns) + .long v7_flush_icache_all .long v7_flush_kern_cache_all .long v7_flush_user_cache_all .long v7_flush_user_cache_range -- cgit v1.2.3 From 8ed9059533eb89b4372d7fc31b6565c053e5253b Mon Sep 17 00:00:00 2001 From: Maxim Osipov Date: Wed, 15 Sep 2010 11:54:49 +0100 Subject: ARM: 6393/1: AT91: Add flexibity board support This patch adds support for Flexibity Connect platform from http://www.flexibity.com/ (AT91SAM9260 based). Signed-off-by: Maxim Osipov Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Andrew Victor Signed-off-by: Russell King --- arch/arm/mach-at91/Kconfig | 6 ++ arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/board-flexibity.c | 164 +++++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm/mach-at91/board-flexibity.c (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 939bccd70569..ca33862b4bf4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -248,6 +248,12 @@ config MACH_CPU9260 Select this if you are using a Eukrea Electromatique's CPU9260 Board +config MACH_FLEXIBITY + bool "Flexibity Connect board" + help + Select this if you are using Flexibity Connect board + + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index ca2ac003f41f..7cbe06d7cee9 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o +obj-$(CONFIG_MACH_FLEXIBITY) += board-flexibity.o # AT91SAM9261 board-specific support obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c new file mode 100644 index 000000000000..216c8ca985f4 --- /dev/null +++ b/arch/arm/mach-at91/board-flexibity.c @@ -0,0 +1,164 @@ +/* + * linux/arch/arm/mach-at91/board-flexibity.c + * + * Copyright (C) 2010 Flexibity + * Copyright (C) 2005 SAN People + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + +static void __init flexibity_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* DBGU on ttyS0. (Rx & Tx only) */ + at91_register_uart(0, 0, 0); + + /* set serial console to ttyS0 (ie, DBGU) */ + at91_set_serial_console(0); +} + +static void __init flexibity_init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + +/* USB Host port */ +static struct at91_usbh_data __initdata flexibity_usbh_data = { + .ports = 2, +}; + +/* USB Device port */ +static struct at91_udc_data __initdata flexibity_udc_data = { + .vbus_pin = AT91_PIN_PC5, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + +/* SPI devices */ +static struct spi_board_info flexibity_spi_devices[] = { + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +}; + +/* MCI (SD/MMC) */ +static struct at91_mmc_data __initdata flexibity_mmc_data = { + .slot_b = 0, + .wire4 = 1, + .det_pin = AT91_PIN_PC9, + .wp_pin = AT91_PIN_PC4, +}; + +/* LEDs */ +static struct gpio_led flexibity_leds[] = { + { + .name = "usb1:green", + .gpio = AT91_PIN_PA12, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb1:red", + .gpio = AT91_PIN_PA13, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb2:green", + .gpio = AT91_PIN_PB26, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb2:red", + .gpio = AT91_PIN_PB27, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb3:green", + .gpio = AT91_PIN_PC8, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb3:red", + .gpio = AT91_PIN_PC6, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb4:green", + .gpio = AT91_PIN_PB4, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "usb4:red", + .gpio = AT91_PIN_PB5, + .active_low = 1, + .default_trigger = "default-on", + } +}; + +static void __init flexibity_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&flexibity_usbh_data); + /* USB Device */ + at91_add_device_udc(&flexibity_udc_data); + /* SPI */ + at91_add_device_spi(flexibity_spi_devices, + ARRAY_SIZE(flexibity_spi_devices)); + /* MMC */ + at91_add_device_mmc(0, &flexibity_mmc_data); + /* LEDs */ + at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds)); +} + +MACHINE_START(FLEXIBITY, "Flexibity Connect") + /* Maintainer: Maxim Osipov */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = flexibity_map_io, + .init_irq = flexibity_init_irq, + .init_machine = flexibity_board_init, +MACHINE_END -- cgit v1.2.3 From 100642c7b6971fb4ab69a662f4f60970e3a16dfd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 6 Sep 2010 09:16:44 +0100 Subject: ARM: 6366/1: Update U300 defconfig This mainly removes a lot of unused subsystems (as for the mainline drivers) in the U300 defconfig, switch of MMC debugging by default and enables debugfs on the builds. Once we merge the drivers we'll configure it on again. Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/configs/u300_defconfig | 37 ++----------------------------------- 1 file changed, 2 insertions(+), 35 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig index 46e5e0747269..c1c252cdca60 100644 --- a/arch/arm/configs/u300_defconfig +++ b/arch/arm/configs/u300_defconfig @@ -28,26 +28,9 @@ CONFIG_CPU_IDLE=y CONFIG_FPE_NWFPE=y CONFIG_PM=y # CONFIG_SUSPEND is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_WIRELESS is not set CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" # CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_MTD=y -CONFIG_MTD_PARTITIONS=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC_SMC=y +# CONFIG_MISC_DEVICES is not set # CONFIG_INPUT_MOUSEDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_KEYBOARD_ATKBD is not set @@ -58,7 +41,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_HW_RANDOM is not set CONFIG_I2C=y -CONFIG_POWER_SUPPLY=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_REGULATOR=y @@ -66,24 +48,10 @@ CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_SOC=y # CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set CONFIG_MMC=y -CONFIG_MMC_DEBUG=y CONFIG_MMC_ARMMMCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set CONFIG_RTC_DRV_COH901331=y @@ -93,12 +61,11 @@ CONFIG_COH901318=y CONFIG_FUSE_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -# CONFIG_NETWORK_FILESYSTEMS is not set CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y -# CONFIG_DETECT_SOFTLOCKUP is not set # CONFIG_SCHED_DEBUG is not set CONFIG_TIMER_STATS=y # CONFIG_DEBUG_PREEMPT is not set -- cgit v1.2.3 From 8925ec4c530094b878e7e28a1fd78e7122afd973 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 13 Sep 2010 16:18:30 +0100 Subject: ARM: 6385/1: setup: detect aliasing I-cache when D-cache is non-aliasing Currently, the Kernel assumes that if a CPU has a non-aliasing D-cache then the I-cache is also non-aliasing. This may not be true on ARM cores from v6 onwards, which may have aliasing I-caches but non-aliasing D-caches. This patch adds a cpu_has_aliasing_icache function, which is called from cacheid_init and adds CACHEID_VIPT_I_ALIASING to the cacheid when appropriate. A utility macro, icache_is_vipt_aliasing(), is also provided. Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/cachetype.h | 8 ++++++-- arch/arm/kernel/setup.c | 39 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 42 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index d3a4c2cb9f2f..c023db09fcc1 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -6,6 +6,7 @@ #define CACHEID_VIPT_ALIASING (1 << 2) #define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING) #define CACHEID_ASID_TAGGED (1 << 3) +#define CACHEID_VIPT_I_ALIASING (1 << 4) extern unsigned int cacheid; @@ -14,15 +15,18 @@ extern unsigned int cacheid; #define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING) #define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING) #define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED) +#define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING) /* * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture * Mask out support which will never be present on newer CPUs. * - v6+ is never VIVT - * - v7+ VIPT never aliases + * - v7+ VIPT never aliases on D-side */ #if __LINUX_ARM_ARCH__ >= 7 -#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING | CACHEID_ASID_TAGGED) +#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\ + CACHEID_ASID_TAGGED |\ + CACHEID_VIPT_I_ALIASING) #elif __LINUX_ARM_ARCH__ >= 6 #define __CACHEID_ARCH_MIN (~CACHEID_VIVT) #else diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d5231ae7355a..9fc483393bae 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -238,6 +238,34 @@ int cpu_architecture(void) return cpu_arch; } +static int cpu_has_aliasing_icache(unsigned int arch) +{ + int aliasing_icache; + unsigned int id_reg, num_sets, line_size; + + /* arch specifies the register format */ + switch (arch) { + case CPU_ARCH_ARMv7: + asm("mcr p15, 2, %1, c0, c0, 0 @ set CSSELR\n" + "isb\n" + "mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" + : "=r" (id_reg) + : "r" (1)); + line_size = 4 << ((id_reg & 0x7) + 2); + num_sets = ((id_reg >> 13) & 0x7fff) + 1; + aliasing_icache = (line_size * num_sets) > PAGE_SIZE; + break; + case CPU_ARCH_ARMv6: + aliasing_icache = read_cpuid_cachetype() & (1 << 11); + break; + default: + /* I-cache aliases will be handled by D-cache aliasing code */ + aliasing_icache = 0; + } + + return aliasing_icache; +} + static void __init cacheid_init(void) { unsigned int cachetype = read_cpuid_cachetype(); @@ -249,10 +277,15 @@ static void __init cacheid_init(void) cacheid = CACHEID_VIPT_NONALIASING; if ((cachetype & (3 << 14)) == 1 << 14) cacheid |= CACHEID_ASID_TAGGED; - } else if (cachetype & (1 << 23)) + else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7)) + cacheid |= CACHEID_VIPT_I_ALIASING; + } else if (cachetype & (1 << 23)) { cacheid = CACHEID_VIPT_ALIASING; - else + } else { cacheid = CACHEID_VIPT_NONALIASING; + if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6)) + cacheid |= CACHEID_VIPT_I_ALIASING; + } } else { cacheid = CACHEID_VIVT; } @@ -263,7 +296,7 @@ static void __init cacheid_init(void) cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown", cache_is_vivt() ? "VIVT" : icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : - cache_is_vipt_aliasing() ? "VIPT aliasing" : + icache_is_vipt_aliasing() ? "VIPT aliasing" : cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); } -- cgit v1.2.3 From c4e259c859538e94007d1f04a488540375189551 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 13 Sep 2010 16:19:41 +0100 Subject: ARM: 6386/1: flush_ptrace_access: invalidate correct I-cache alias copy_to_user_page can be used by access_process_vm to write to an executable page of a process using a mapping acquired by kmap. For systems with I-cache aliasing, flushing the I-cache using the Kernel mapping may leave stale data in the I-cache if the user mapping is of a different colour. This patch introduces a flush_icache_alias function to flush.c, which calls flush_icache_range with a mapping of the specified colour. flush_ptrace_access is then modified to call this new function instead of coherent_kern_range in the case of an aliasing I-cache and a non-aliasing D-cache. Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/mm/flush.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 2332b774c6b9..391ffae75098 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -40,6 +40,18 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) : "cc"); } +static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len) +{ + unsigned long colour = CACHE_COLOUR(vaddr); + unsigned long offset = vaddr & (PAGE_SIZE - 1); + unsigned long to; + + set_pte_ext(TOP_PTE(ALIAS_FLUSH_START) + colour, pfn_pte(pfn, PAGE_KERNEL), 0); + to = ALIAS_FLUSH_START + (colour << PAGE_SHIFT) + offset; + flush_tlb_kernel_page(to); + flush_icache_range(to, to + len); +} + void flush_cache_mm(struct mm_struct *mm) { if (cache_is_vivt()) { @@ -90,8 +102,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged()) __flush_icache_all(); } + #else -#define flush_pfn_alias(pfn,vaddr) do { } while (0) +#define flush_pfn_alias(pfn,vaddr) do { } while (0) +#define flush_icache_alias(pfn,vaddr,len) do { } while (0) #endif static void flush_ptrace_access_other(void *args) @@ -117,10 +131,13 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, return; } - /* VIPT non-aliasing cache */ + /* VIPT non-aliasing D-cache */ if (vma->vm_flags & VM_EXEC) { unsigned long addr = (unsigned long)kaddr; - __cpuc_coherent_kern_range(addr, addr + len); + if (icache_is_vipt_aliasing()) + flush_icache_alias(page_to_pfn(page), uaddr, len); + else + __cpuc_coherent_kern_range(addr, addr + len); if (cache_ops_need_broadcast()) smp_call_function(flush_ptrace_access_other, NULL, 1); -- cgit v1.2.3 From cdaf9a2f280b25dd2fb1e04da5d3899411766e1b Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 5 Oct 2010 11:29:28 +0100 Subject: ARM: fix section mismatch warnings in Versatile Express WARNING: vmlinux.o(.text+0xbf30): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clocksource_init() The function v2m_timer_init() references the function __init sp804_clocksource_init(). This is often because v2m_timer_init lacks a __init annotation or the annotation of sp804_clocksource_init is wrong. WARNING: vmlinux.o(.text+0xbf3c): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clockevents_init() The function v2m_timer_init() references the function __init sp804_clockevents_init(). This is often because v2m_timer_init lacks a __init annotation or the annotation of sp804_clockevents_init is wrong. WARNING: vmlinux.o(.text+0xc524): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:l2x0_init() The function ct_ca9x4_init() references the function __init l2x0_init(). This is often because ct_ca9x4_init lacks a __init annotation or the annotation of l2x0_init is wrong. WARNING: vmlinux.o(.text+0xc530): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:clkdev_add_table() The function ct_ca9x4_init() references the function __init clkdev_add_table(). This is often because ct_ca9x4_init lacks a __init annotation or the annotation of clkdev_add_table is wrong. WARNING: vmlinux.o(.text+0xc578): Section mismatch in reference from the function ct_ca9x4_init() to the (unknown reference) .init.data:(unknown) The function ct_ca9x4_init() references the (unknown reference) __initdata (unknown). This is often because ct_ca9x4_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Fix these by making ct_ca9x4_init() and v2m_timer_init() both __init. Signed-off-by: Russell King --- arch/arm/mach-vexpress/ct-ca9x4.c | 4 ++-- arch/arm/mach-vexpress/v2m.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index efb127022d42..71fb17349520 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c @@ -68,7 +68,7 @@ static void __init ct_ca9x4_init_irq(void) } #if 0 -static void ct_ca9x4_timer_init(void) +static void __init ct_ca9x4_timer_init(void) { writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL); @@ -222,7 +222,7 @@ static struct platform_device pmu_device = { .resource = pmu_resources, }; -static void ct_ca9x4_init(void) +static void __init ct_ca9x4_init(void) { int i; diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 817f0ad38a0b..7eaa232180a5 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -48,7 +48,7 @@ void __init v2m_map_io(struct map_desc *tile, size_t num) } -static void v2m_timer_init(void) +static void __init v2m_timer_init(void) { writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL); writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL); -- cgit v1.2.3 From 4b48e6876b641e1138f37a0fc11fb6a4fc3e24e1 Mon Sep 17 00:00:00 2001 From: ext Anand Gadiyar Date: Fri, 1 Oct 2010 22:33:26 +0200 Subject: omap: zoom2/3: fix build caused by wl1271 support Patch "omap: zoom: add mmc3/wl1271 device support" in the wireless tree still uses .wires in struct omap2_hsmmc_info. .wires has now been replaced with .caps in patch "omap: mmc: extended to pass host capabilities from board file" in the OMAP tree. This causes linux-next as of 20101001 build to break as below. Fix this. CC arch/arm/mach-omap2/board-zoom-peripherals.o arch/arm/mach-omap2/board-zoom-peripherals.c:217: error: unknown field 'wires' specified in initializer make[1]: *** [arch/arm/mach-omap2/board-zoom-peripherals.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 Signed-off-by: Anand Gadiyar Cc: Ohad Ben-Cohen Cc: Tony Lindgren Acked-by: Tony Lindgren Signed-off-by: Luciano Coelho --- arch/arm/mach-omap2/board-zoom-peripherals.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c index 6aa0728fa15d..189a6d1600b2 100644 --- a/arch/arm/mach-omap2/board-zoom-peripherals.c +++ b/arch/arm/mach-omap2/board-zoom-peripherals.c @@ -213,7 +213,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { { .name = "wl1271", .mmc = 3, - .wires = 4, + .caps = MMC_CAP_4_BIT_DATA, .gpio_wp = -EINVAL, .gpio_cd = -EINVAL, .nonremovable = true, -- cgit v1.2.3 From 0fa035e52373386381fcdfbd506e32eac0c662f0 Mon Sep 17 00:00:00 2001 From: Hari Kanigeri Date: Fri, 20 Aug 2010 13:50:18 +0000 Subject: omap: iommu-load cam register before flushing the entry The flush_iotlb_page is not loading the cam register before flushing the cam entry. This causes wrong entry to be flushed out from the TLB, and if the entry happens to be a locked TLB entry it would lead to MMU faults. The fix is to load the cam register with the address to be flushed before flushing the TLB entry. Signed-off-by: Hari Kanigeri Acked-by: Hiroshi DOYU Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/iommu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index a202a2ce6e3d..6cd151b31bc5 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -320,6 +320,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da) if ((start <= da) && (da < start + bytes)) { dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", __func__, start, da, bytes); + iotlb_load_cr(obj, &cr); iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); } } -- cgit v1.2.3 From 846afbd1fe015e082c89d56dd42c484d896ef58e Mon Sep 17 00:00:00 2001 From: Abhijeet Dharmapurikar Date: Tue, 24 Aug 2010 21:57:33 -0700 Subject: GIC: Dont disable INT in ack callback Masking in the ack callback fails to work with handle_percpu_irq and handle_edge_irq. The interrupt stays disabled after the first invocation since percpu and edge irq do not unmask an interrupt after handling it. For handle_level_irq masking in the ack is redundant because ack is always called after mask in the mask_ack function. Masking in the ack function is required only when __do_IRQ was used instead of flow handlers, but using __do_IRQ has been deprecated. Remove the masking of interrupt from the ack callback. Signed-off-by: Abhijeet Dharmapurikar Signed-off-by: Jeff Ohlstein Signed-off-by: Daniel Walker --- arch/arm/common/gic.c | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 7dfa9a85bc0c..ada6359160eb 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq) /* * Routines to acknowledge, disable and enable interrupts - * - * Linux assumes that when we're done with an interrupt we need to - * unmask it, in the same way we need to unmask an interrupt when - * we first enable it. - * - * The GIC has a separate notion of "end of interrupt" to re-enable - * an interrupt after handling, in order to support hardware - * prioritisation. - * - * We can make the GIC behave in the way that Linux expects by making - * our "acknowledge" routine disable the interrupt, then mark it as - * complete. */ static void gic_ack_irq(unsigned int irq) { - u32 mask = 1 << (irq % 32); spin_lock(&irq_controller_lock); - writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } -- cgit v1.2.3 From 1963a2afc81afe6d85e7a12538b74a9919d958ae Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Sat, 28 Aug 2010 10:05:44 -0700 Subject: msm: add gpiomux api for gpio multiplex & configuration. Add the 'gpiomux' api, which addresses the following shortcomings of existing tlmm api: - gpio power-collapse, which is managed by a peripheral processor on other targets, must be managed by the application processor on the 8x60. - The enable/disable flag of the legacy gpio_tlmm_config api is not applicable on the 8x60, and causes confusion. - The gpio 'direction' bits are meaningless for all func_sel configurations except for generic-gpio mode (func_sel 0), in which case the gpio_direction_* functions should be used. Having these bits in the tlmm api leads to confusion and misuse of the gpiolib api, and they have been removed in gpiomux. - The functional api of the legacy system ran contrary to the typical use-case, which is a single massive configuration at boot. Rather than forcing hundreds of 'config' function calls, the new api allows data to be configured with a single table. gpiomux_get and gpiomux_put are meant to be called automatically when gpio_request and gpio_free are called, giving automatic gpiomux/tlmm control to those drivers/lines with simple power profiles - in the simplest cases, an entry in the gpiomux table and the correct usage of gpiolib is all that is required to get proper gpio power control. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Kconfig | 2 + arch/arm/mach-msm/Makefile | 3 + arch/arm/mach-msm/gpiomux-7x30.c | 19 +++++ arch/arm/mach-msm/gpiomux-8x50.c | 19 +++++ arch/arm/mach-msm/gpiomux-8x60.c | 19 +++++ arch/arm/mach-msm/gpiomux-v1.c | 33 +++++++++ arch/arm/mach-msm/gpiomux-v1.h | 67 +++++++++++++++++ arch/arm/mach-msm/gpiomux-v2.c | 25 +++++++ arch/arm/mach-msm/gpiomux-v2.h | 61 ++++++++++++++++ arch/arm/mach-msm/gpiomux.c | 96 +++++++++++++++++++++++++ arch/arm/mach-msm/gpiomux.h | 94 ++++++++++++++++++++++++ arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 42 +++++++++++ arch/arm/mach-msm/include/mach/msm_iomap.h | 2 + 13 files changed, 482 insertions(+) create mode 100644 arch/arm/mach-msm/gpiomux-7x30.c create mode 100644 arch/arm/mach-msm/gpiomux-8x50.c create mode 100644 arch/arm/mach-msm/gpiomux-8x60.c create mode 100644 arch/arm/mach-msm/gpiomux-v1.c create mode 100644 arch/arm/mach-msm/gpiomux-v1.h create mode 100644 arch/arm/mach-msm/gpiomux-v2.c create mode 100644 arch/arm/mach-msm/gpiomux-v2.h create mode 100644 arch/arm/mach-msm/gpiomux.c create mode 100644 arch/arm/mach-msm/gpiomux.h create mode 100644 arch/arm/mach-msm/include/mach/msm_iomap-8x60.h (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 47264a76eeb3..4e79580af628 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -106,4 +106,6 @@ config MSM_SMD_PKG3 config MSM_SMD bool +config MSM_V2_TLMM + bool endif diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 704610648a25..78424e3f3802 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -20,3 +20,6 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o +obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o +obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o +obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c new file mode 100644 index 000000000000..7b380b31bd0e --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-7x30.c @@ -0,0 +1,19 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#include "gpiomux.h" + +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c new file mode 100644 index 000000000000..7b380b31bd0e --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-8x50.c @@ -0,0 +1,19 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#include "gpiomux.h" + +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c new file mode 100644 index 000000000000..7b380b31bd0e --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-8x60.c @@ -0,0 +1,19 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#include "gpiomux.h" + +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; diff --git a/arch/arm/mach-msm/gpiomux-v1.c b/arch/arm/mach-msm/gpiomux-v1.c new file mode 100644 index 000000000000..27de2abd7144 --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-v1.c @@ -0,0 +1,33 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#include +#include "gpiomux.h" +#include "proc_comm.h" + +void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val) +{ + unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) | + ((gpio & 0x3ff) << 4); + unsigned tlmm_disable = 0; + int rc; + + rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, + &tlmm_config, &tlmm_disable); + if (rc) + pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n", + __func__, rc, tlmm_config, tlmm_disable); +} diff --git a/arch/arm/mach-msm/gpiomux-v1.h b/arch/arm/mach-msm/gpiomux-v1.h new file mode 100644 index 000000000000..71d86feba450 --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-v1.h @@ -0,0 +1,67 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H +#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H + +#if defined(CONFIG_ARCH_MSM7X30) +#define GPIOMUX_NGPIOS 182 +#elif defined(CONFIG_ARCH_QSD8X50) +#define GPIOMUX_NGPIOS 165 +#else +#define GPIOMUX_NGPIOS 133 +#endif + +typedef u32 gpiomux_config_t; + +enum { + GPIOMUX_DRV_2MA = 0UL << 17, + GPIOMUX_DRV_4MA = 1UL << 17, + GPIOMUX_DRV_6MA = 2UL << 17, + GPIOMUX_DRV_8MA = 3UL << 17, + GPIOMUX_DRV_10MA = 4UL << 17, + GPIOMUX_DRV_12MA = 5UL << 17, + GPIOMUX_DRV_14MA = 6UL << 17, + GPIOMUX_DRV_16MA = 7UL << 17, +}; + +enum { + GPIOMUX_FUNC_GPIO = 0UL, + GPIOMUX_FUNC_1 = 1UL, + GPIOMUX_FUNC_2 = 2UL, + GPIOMUX_FUNC_3 = 3UL, + GPIOMUX_FUNC_4 = 4UL, + GPIOMUX_FUNC_5 = 5UL, + GPIOMUX_FUNC_6 = 6UL, + GPIOMUX_FUNC_7 = 7UL, + GPIOMUX_FUNC_8 = 8UL, + GPIOMUX_FUNC_9 = 9UL, + GPIOMUX_FUNC_A = 10UL, + GPIOMUX_FUNC_B = 11UL, + GPIOMUX_FUNC_C = 12UL, + GPIOMUX_FUNC_D = 13UL, + GPIOMUX_FUNC_E = 14UL, + GPIOMUX_FUNC_F = 15UL, +}; + +enum { + GPIOMUX_PULL_NONE = 0UL << 15, + GPIOMUX_PULL_DOWN = 1UL << 15, + GPIOMUX_PULL_KEEPER = 2UL << 15, + GPIOMUX_PULL_UP = 3UL << 15, +}; + +#endif diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c new file mode 100644 index 000000000000..273396d2b127 --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-v2.c @@ -0,0 +1,25 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#include +#include +#include "gpiomux.h" + +void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val) +{ + writel(val & ~GPIOMUX_CTL_MASK, + MSM_TLMM_BASE + 0x1000 + (0x10 * gpio)); +} diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h new file mode 100644 index 000000000000..3bf10e7f0381 --- /dev/null +++ b/arch/arm/mach-msm/gpiomux-v2.h @@ -0,0 +1,61 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H +#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H + +#define GPIOMUX_NGPIOS 173 + +typedef u16 gpiomux_config_t; + +enum { + GPIOMUX_DRV_2MA = 0UL << 6, + GPIOMUX_DRV_4MA = 1UL << 6, + GPIOMUX_DRV_6MA = 2UL << 6, + GPIOMUX_DRV_8MA = 3UL << 6, + GPIOMUX_DRV_10MA = 4UL << 6, + GPIOMUX_DRV_12MA = 5UL << 6, + GPIOMUX_DRV_14MA = 6UL << 6, + GPIOMUX_DRV_16MA = 7UL << 6, +}; + +enum { + GPIOMUX_FUNC_GPIO = 0UL << 2, + GPIOMUX_FUNC_1 = 1UL << 2, + GPIOMUX_FUNC_2 = 2UL << 2, + GPIOMUX_FUNC_3 = 3UL << 2, + GPIOMUX_FUNC_4 = 4UL << 2, + GPIOMUX_FUNC_5 = 5UL << 2, + GPIOMUX_FUNC_6 = 6UL << 2, + GPIOMUX_FUNC_7 = 7UL << 2, + GPIOMUX_FUNC_8 = 8UL << 2, + GPIOMUX_FUNC_9 = 9UL << 2, + GPIOMUX_FUNC_A = 10UL << 2, + GPIOMUX_FUNC_B = 11UL << 2, + GPIOMUX_FUNC_C = 12UL << 2, + GPIOMUX_FUNC_D = 13UL << 2, + GPIOMUX_FUNC_E = 14UL << 2, + GPIOMUX_FUNC_F = 15UL << 2, +}; + +enum { + GPIOMUX_PULL_NONE = 0UL, + GPIOMUX_PULL_DOWN = 1UL, + GPIOMUX_PULL_KEEPER = 2UL, + GPIOMUX_PULL_UP = 3UL, +}; + +#endif diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c new file mode 100644 index 000000000000..53af21abd155 --- /dev/null +++ b/arch/arm/mach-msm/gpiomux.c @@ -0,0 +1,96 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#include +#include +#include "gpiomux.h" + +static DEFINE_SPINLOCK(gpiomux_lock); + +int msm_gpiomux_write(unsigned gpio, + gpiomux_config_t active, + gpiomux_config_t suspended) +{ + struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio; + unsigned long irq_flags; + gpiomux_config_t setting; + + if (gpio >= GPIOMUX_NGPIOS) + return -EINVAL; + + spin_lock_irqsave(&gpiomux_lock, irq_flags); + + if (active & GPIOMUX_VALID) + cfg->active = active; + + if (suspended & GPIOMUX_VALID) + cfg->suspended = suspended; + + setting = cfg->ref ? active : suspended; + if (setting & GPIOMUX_VALID) + __msm_gpiomux_write(gpio, setting); + + spin_unlock_irqrestore(&gpiomux_lock, irq_flags); + return 0; +} +EXPORT_SYMBOL(msm_gpiomux_write); + +int msm_gpiomux_get(unsigned gpio) +{ + struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio; + unsigned long irq_flags; + + if (gpio >= GPIOMUX_NGPIOS) + return -EINVAL; + + spin_lock_irqsave(&gpiomux_lock, irq_flags); + if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID) + __msm_gpiomux_write(gpio, cfg->active); + spin_unlock_irqrestore(&gpiomux_lock, irq_flags); + return 0; +} +EXPORT_SYMBOL(msm_gpiomux_get); + +int msm_gpiomux_put(unsigned gpio) +{ + struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio; + unsigned long irq_flags; + + if (gpio >= GPIOMUX_NGPIOS) + return -EINVAL; + + spin_lock_irqsave(&gpiomux_lock, irq_flags); + BUG_ON(cfg->ref == 0); + if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID) + __msm_gpiomux_write(gpio, cfg->suspended); + spin_unlock_irqrestore(&gpiomux_lock, irq_flags); + return 0; +} +EXPORT_SYMBOL(msm_gpiomux_put); + +static int __init gpiomux_init(void) +{ + unsigned n; + + for (n = 0; n < GPIOMUX_NGPIOS; ++n) { + msm_gpiomux_configs[n].ref = 0; + if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID)) + continue; + __msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended); + } + return 0; +} +postcore_initcall(gpiomux_init); diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h new file mode 100644 index 000000000000..bb0acf0c9644 --- /dev/null +++ b/arch/arm/mach-msm/gpiomux.h @@ -0,0 +1,94 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ +#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H +#define __ARCH_ARM_MACH_MSM_GPIOMUX_H + +#include + +#if defined(CONFIG_MSM_V2_TLMM) +#include "gpiomux-v2.h" +#else +#include "gpiomux-v1.h" +#endif + +/** + * struct msm_gpiomux_config: gpiomux settings for one gpio line. + * + * A complete gpiomux config is the bitwise-or of a drive-strength, + * function, and pull. For functions other than GPIO, the OE + * is hard-wired according to the function. For GPIO mode, + * OE is controlled by gpiolib. + * + * Available settings differ by target; see the gpiomux header + * specific to your target arch for available configurations. + * + * @active: The configuration to be installed when the line is + * active, or its reference count is > 0. + * @suspended: The configuration to be installed when the line + * is suspended, or its reference count is 0. + * @ref: The reference count of the line. For internal use of + * the gpiomux framework only. + */ +struct msm_gpiomux_config { + gpiomux_config_t active; + gpiomux_config_t suspended; + unsigned ref; +}; + +/** + * @GPIOMUX_VALID: If set, the config field contains 'good data'. + * The absence of this bit will prevent the gpiomux + * system from applying the configuration under all + * circumstances. + */ +enum { + GPIOMUX_VALID = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1), + GPIOMUX_CTL_MASK = GPIOMUX_VALID, +}; + +/* Each architecture must provide its own instance of this table. + * To avoid having gpiomux manage any given gpio, one or both of + * the entries can avoid setting GPIOMUX_VALID - the absence + * of that flag will prevent the configuration from being applied + * during state transitions. + */ +extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS]; + +/* Increment a gpio's reference count, possibly activating the line. */ +int __must_check msm_gpiomux_get(unsigned gpio); + +/* Decrement a gpio's reference count, possibly suspending the line. */ +int msm_gpiomux_put(unsigned gpio); + +/* Install a new configuration to the gpio line. To avoid overwriting + * a configuration, leave the VALID bit out. + */ +int msm_gpiomux_write(unsigned gpio, + gpiomux_config_t active, + gpiomux_config_t suspended); + +/* Architecture-internal function for use by the framework only. + * This function can assume the following: + * - the gpio value has passed a bounds-check + * - the gpiomux spinlock has been obtained + * + * This function is not for public consumption. External users + * should use msm_gpiomux_write. + */ +void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val); + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h new file mode 100644 index 000000000000..17209f78d4a8 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * The MSM peripherals are spread all over across 768MB of physical + * space, which makes just having a simple IO_ADDRESS macro to slide + * them into the right virtual location rough. Instead, we will + * provide a master phys->virt mapping for peripherals here. + * + */ + +#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H +#define __ASM_ARCH_MSM_IOMAP_8X60_H + +/* Physical base address and size of peripherals. + * Ordered by the virtual base addresses they will be mapped at. + * + * MSM_VIC_BASE must be an value that can be loaded via a "mov" + * instruction, otherwise entry-macro.S will not compile. + * + * If you add or remove entries here, you'll want to edit the + * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your + * changes. + * + */ + +#define MSM_TLMM_BASE IOMEM(0xF0004000) +#define MSM_TLMM_PHYS 0x00800000 +#define MSM_TLMM_SIZE SZ_16K + +#endif diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index e6b1821cc4ea..39c8fbcf33e7 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -47,6 +47,8 @@ #include "msm_iomap-7x30.h" #elif defined(CONFIG_ARCH_QSD8X50) #include "msm_iomap-8x50.h" +#elif defined(CONFIG_ARCH_MSM8X60) +#include "msm_iomap-8x60.h" #else #include "msm_iomap-7x00.h" #endif -- cgit v1.2.3 From dd22b8f703d7a9aa5e40a7741b7e84fb0bb025d6 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Sat, 28 Aug 2010 10:05:46 -0700 Subject: msm: convert 8x50 to gpiomux. Change the gpio-init code from deprecated gpio_tlmm_config to the new gpiomux api. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/board-qsd8x50.c | 12 ------------ arch/arm/mach-msm/gpiomux-8x50.c | 11 ++++++++++- 2 files changed, 10 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index e3cc80792d6c..fb0fe6771e56 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -35,21 +35,10 @@ extern struct sys_timer msm_timer; -static struct msm_gpio uart3_config_data[] = { - { GPIO_CFG(86, 1, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"}, - { GPIO_CFG(87, 1, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"}, -}; - static struct platform_device *devices[] __initdata = { &msm_device_uart3, }; -static void msm8x50_init_uart3(void) -{ - msm_gpios_request_enable(uart3_config_data, - ARRAY_SIZE(uart3_config_data)); -} - static void __init qsd8x50_map_io(void) { msm_map_qsd8x50_io(); @@ -64,7 +53,6 @@ static void __init qsd8x50_init_irq(void) static void __init qsd8x50_init(void) { - msm8x50_init_uart3(); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c index 7b380b31bd0e..4406e0f4ae95 100644 --- a/arch/arm/mach-msm/gpiomux-8x50.c +++ b/arch/arm/mach-msm/gpiomux-8x50.c @@ -16,4 +16,13 @@ */ #include "gpiomux.h" -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { + [86] = { /* UART3 RX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_1 | GPIOMUX_VALID, + }, + [87] = { /* UART3 TX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_1 | GPIOMUX_VALID, + }, +}; -- cgit v1.2.3 From 224f6de46ab05677f1fbfa7e384938639ff3f691 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Sat, 28 Aug 2010 10:05:47 -0700 Subject: msm: convert 7x30 to gpiomux. Change deprecated gpio_tlmm_config calls to gpiomux calls. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/board-msm7x30.c | 20 -------------------- arch/arm/mach-msm/gpiomux-7x30.c | 21 ++++++++++++++++++++- 2 files changed, 20 insertions(+), 21 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index e32981928c77..74abb74b4983 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c @@ -39,22 +39,6 @@ extern struct sys_timer msm_timer; -#ifdef CONFIG_SERIAL_MSM_CONSOLE -static struct msm_gpio uart2_config_data[] = { - { GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"}, - { GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"}, - { GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"}, - { GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"}, -}; - -static void msm7x30_init_uart2(void) -{ - msm_gpios_request_enable(uart2_config_data, - ARRAY_SIZE(uart2_config_data)); - -} -#endif - static struct platform_device *devices[] __initdata = { #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) &msm_device_uart2, @@ -70,10 +54,6 @@ static void __init msm7x30_init_irq(void) static void __init msm7x30_init(void) { platform_add_devices(devices, ARRAY_SIZE(devices)); -#ifdef CONFIG_SERIAL_MSM_CONSOLE - msm7x30_init_uart2(); -#endif - } static void __init msm7x30_map_io(void) diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c index 7b380b31bd0e..6ce41c5241a5 100644 --- a/arch/arm/mach-msm/gpiomux-7x30.c +++ b/arch/arm/mach-msm/gpiomux-7x30.c @@ -16,4 +16,23 @@ */ #include "gpiomux.h" -struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {}; +struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { +#ifdef CONFIG_SERIAL_MSM_CONSOLE + [49] = { /* UART2 RFR */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [50] = { /* UART2 CTS */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [51] = { /* UART2 RX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, + [52] = { /* UART2 TX */ + .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | + GPIOMUX_FUNC_2 | GPIOMUX_VALID, + }, +#endif +}; -- cgit v1.2.3 From 10c4580e798838fd63eafec5ed304b7ace6db020 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Sat, 28 Aug 2010 10:05:48 -0700 Subject: msm: gpio: Remove tlmm routines obsoleted by gpiomux. Now that all supported gpio_tlmm_config-using boards are using gpiomux, remove the deprecated code. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Makefile | 1 - arch/arm/mach-msm/gpio.c | 85 ----------------------- arch/arm/mach-msm/include/mach/gpio.h | 123 ---------------------------------- 3 files changed, 209 deletions(-) delete mode 100644 arch/arm/mach-msm/gpio.c (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 78424e3f3802..2263b8ffd6b9 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -3,7 +3,6 @@ obj-y += io.o idle.o timer.o dma.o obj-y += vreg.o obj-y += acpuclock-arm11.o obj-y += clock.o clock-pcom.o -obj-y += gpio.o ifdef CONFIG_MSM_VIC obj-y += irq-vic.o diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c deleted file mode 100644 index bc32c845c7b0..000000000000 --- a/arch/arm/mach-msm/gpio.c +++ /dev/null @@ -1,85 +0,0 @@ -/* linux/arch/arm/mach-msm/gpio.c - * - * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2009, Code Aurora Forum. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include "proc_comm.h" - -int gpio_tlmm_config(unsigned config, unsigned disable) -{ - return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable); -} -EXPORT_SYMBOL(gpio_tlmm_config); - -int msm_gpios_enable(const struct msm_gpio *table, int size) -{ - int rc; - int i; - const struct msm_gpio *g; - for (i = 0; i < size; i++) { - g = table + i; - rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE); - if (rc) { - pr_err("gpio_tlmm_config(0x%08x, GPIO_ENABLE)" - " <%s> failed: %d\n", - g->gpio_cfg, g->label ?: "?", rc); - pr_err("pin %d func %d dir %d pull %d drvstr %d\n", - GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), - GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), - GPIO_DRVSTR(g->gpio_cfg)); - goto err; - } - } - return 0; -err: - msm_gpios_disable(table, i); - return rc; -} -EXPORT_SYMBOL(msm_gpios_enable); - -void msm_gpios_disable(const struct msm_gpio *table, int size) -{ - int rc; - int i; - const struct msm_gpio *g; - for (i = size-1; i >= 0; i--) { - g = table + i; - rc = gpio_tlmm_config(g->gpio_cfg, GPIO_DISABLE); - if (rc) { - pr_err("gpio_tlmm_config(0x%08x, GPIO_DISABLE)" - " <%s> failed: %d\n", - g->gpio_cfg, g->label ?: "?", rc); - pr_err("pin %d func %d dir %d pull %d drvstr %d\n", - GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), - GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), - GPIO_DRVSTR(g->gpio_cfg)); - } - } -} -EXPORT_SYMBOL(msm_gpios_disable); - -int msm_gpios_request_enable(const struct msm_gpio *table, int size) -{ - int rc = msm_gpios_enable(table, size); - return rc; -} -EXPORT_SYMBOL(msm_gpios_request_enable); - -void msm_gpios_disable_free(const struct msm_gpio *table, int size) -{ - msm_gpios_disable(table, size); -} -EXPORT_SYMBOL(msm_gpios_disable_free); diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h index 83e47c0d5c2e..36ad50d3bfaa 100644 --- a/arch/arm/mach-msm/include/mach/gpio.h +++ b/arch/arm/mach-msm/include/mach/gpio.h @@ -23,127 +23,4 @@ #define gpio_cansleep __gpio_cansleep #define gpio_to_irq __gpio_to_irq -/** - * struct msm_gpio - GPIO pin description - * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() - * @label - textual label - * - * Usually, GPIO's are operated by sets. - * This struct accumulate all GPIO information in single source - * and facilitete group operations provided by msm_gpios_xxx() - */ -struct msm_gpio { - u32 gpio_cfg; - const char *label; -}; - -/** - * msm_gpios_request_enable() - request and enable set of GPIOs - * - * Request and configure set of GPIO's - * In case of error, all operations rolled back. - * Return error code. - * - * @table: GPIO table - * @size: number of entries in @table - */ -int msm_gpios_request_enable(const struct msm_gpio *table, int size); - -/** - * msm_gpios_disable_free() - disable and free set of GPIOs - * - * @table: GPIO table - * @size: number of entries in @table - */ -void msm_gpios_disable_free(const struct msm_gpio *table, int size); - -/** - * msm_gpios_request() - request set of GPIOs - * In case of error, all operations rolled back. - * Return error code. - * - * @table: GPIO table - * @size: number of entries in @table - */ -int msm_gpios_request(const struct msm_gpio *table, int size); - -/** - * msm_gpios_free() - free set of GPIOs - * - * @table: GPIO table - * @size: number of entries in @table - */ -void msm_gpios_free(const struct msm_gpio *table, int size); - -/** - * msm_gpios_enable() - enable set of GPIOs - * In case of error, all operations rolled back. - * Return error code. - * - * @table: GPIO table - * @size: number of entries in @table - */ -int msm_gpios_enable(const struct msm_gpio *table, int size); - -/** - * msm_gpios_disable() - disable set of GPIOs - * - * @table: GPIO table - * @size: number of entries in @table - */ -void msm_gpios_disable(const struct msm_gpio *table, int size); - -/* GPIO TLMM (Top Level Multiplexing) Definitions */ - -/* GPIO TLMM: Function -- GPIO specific */ - -/* GPIO TLMM: Direction */ -enum { - GPIO_INPUT, - GPIO_OUTPUT, -}; - -/* GPIO TLMM: Pullup/Pulldown */ -enum { - GPIO_NO_PULL, - GPIO_PULL_DOWN, - GPIO_KEEPER, - GPIO_PULL_UP, -}; - -/* GPIO TLMM: Drive Strength */ -enum { - GPIO_2MA, - GPIO_4MA, - GPIO_6MA, - GPIO_8MA, - GPIO_10MA, - GPIO_12MA, - GPIO_14MA, - GPIO_16MA, -}; - -enum { - GPIO_ENABLE, - GPIO_DISABLE, -}; - -#define GPIO_CFG(gpio, func, dir, pull, drvstr) \ - ((((gpio) & 0x3FF) << 4) | \ - ((func) & 0xf) | \ - (((dir) & 0x1) << 14) | \ - (((pull) & 0x3) << 15) | \ - (((drvstr) & 0xF) << 17)) - -/** - * extract GPIO pin from bit-field used for gpio_tlmm_config - */ -#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff) -#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf) -#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1) -#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3) -#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf) - -int gpio_tlmm_config(unsigned config, unsigned disable); - #endif /* __ASM_ARCH_MSM_GPIO_H */ -- cgit v1.2.3 From ab78cde589e89afa039a13bc75d23d249f1c1200 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Wed, 1 Sep 2010 16:26:12 -0700 Subject: msm: Featurize gpiomux. Featurize gpiomux so that systems like 7x00 which do not wish to use it do not have to be saddled with the configuration tables. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Kconfig | 5 +++++ arch/arm/mach-msm/gpiomux.h | 20 ++++++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 4e79580af628..f09ffef4cda8 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -18,6 +18,7 @@ config ARCH_MSM7X30 select MSM_VIC select CPU_V7 select MSM_REMOTE_SPINLOCK_DEKKERS + select MSM_GPIOMUX config ARCH_QSD8X50 bool "QSD8X50" @@ -26,6 +27,7 @@ config ARCH_QSD8X50 select MSM_VIC select CPU_V7 select MSM_REMOTE_SPINLOCK_LDREX + select MSM_GPIOMUX endchoice config MSM_SOC_REV_A @@ -106,6 +108,9 @@ config MSM_SMD_PKG3 config MSM_SMD bool +config MSM_GPIOMUX + bool + config MSM_V2_TLMM bool endif diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h index bb0acf0c9644..b178d9cb742f 100644 --- a/arch/arm/mach-msm/gpiomux.h +++ b/arch/arm/mach-msm/gpiomux.h @@ -18,6 +18,7 @@ #define __ARCH_ARM_MACH_MSM_GPIOMUX_H #include +#include #if defined(CONFIG_MSM_V2_TLMM) #include "gpiomux-v2.h" @@ -60,6 +61,8 @@ enum { GPIOMUX_CTL_MASK = GPIOMUX_VALID, }; +#ifdef CONFIG_MSM_GPIOMUX + /* Each architecture must provide its own instance of this table. * To avoid having gpiomux manage any given gpio, one or both of * the entries can avoid setting GPIOMUX_VALID - the absence @@ -90,5 +93,22 @@ int msm_gpiomux_write(unsigned gpio, * should use msm_gpiomux_write. */ void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val); +#else +static inline int __must_check msm_gpiomux_get(unsigned gpio) +{ + return -ENOSYS; +} +static inline int msm_gpiomux_put(unsigned gpio) +{ + return -ENOSYS; +} + +static inline int msm_gpiomux_write(unsigned gpio, + gpiomux_config_t active, + gpiomux_config_t suspended) +{ + return -ENOSYS; +} +#endif #endif -- cgit v1.2.3 From 2783cc265cc57c4bbf788b75fa8c3f06259dffd1 Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Fri, 10 Sep 2010 15:03:36 -0700 Subject: msm: add gpio driver for single-core SoCs. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Install a gpiolib driver supporting the on-chip gpios for single-core MSMs in the 7x00 family, including 7x00A, 7x25, 7x27, 7x30, 8x50, and 8x50a. As part of the ongoing effort to converge on a common code base, this driver is based on the Google-Android msmgpio driver, whose authors include Brian Swetland and Arve Hjønnevåg. Cc: Arve Hjønnevåg Cc: H Hartley Sweeten Cc: Ryan Mallon Cc: Ben Dooks Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/Makefile | 3 + arch/arm/mach-msm/gpio.c | 358 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-msm/gpio_hw.h | 278 ++++++++++++++++++++++++++++++++++ 3 files changed, 639 insertions(+) create mode 100644 arch/arm/mach-msm/gpio.c create mode 100644 arch/arm/mach-msm/gpio_hw.h (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 2263b8ffd6b9..c95d19a9045d 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -22,3 +22,6 @@ obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o +ifndef CONFIG_MSM_V2_TLMM +obj-y += gpio.o +endif diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c new file mode 100644 index 000000000000..5040f1cb64f9 --- /dev/null +++ b/arch/arm/mach-msm/gpio.c @@ -0,0 +1,358 @@ +/* linux/arch/arm/mach-msm/gpio.c + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include "gpio_hw.h" + +#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) + +#define MSM_GPIO_BANK(bank, first, last) \ + { \ + .regs = { \ + .out = MSM_GPIO_OUT_##bank, \ + .in = MSM_GPIO_IN_##bank, \ + .int_status = MSM_GPIO_INT_STATUS_##bank, \ + .int_clear = MSM_GPIO_INT_CLEAR_##bank, \ + .int_en = MSM_GPIO_INT_EN_##bank, \ + .int_edge = MSM_GPIO_INT_EDGE_##bank, \ + .int_pos = MSM_GPIO_INT_POS_##bank, \ + .oe = MSM_GPIO_OE_##bank, \ + }, \ + .chip = { \ + .base = (first), \ + .ngpio = (last) - (first) + 1, \ + .get = msm_gpio_get, \ + .set = msm_gpio_set, \ + .direction_input = msm_gpio_direction_input, \ + .direction_output = msm_gpio_direction_output, \ + .to_irq = msm_gpio_to_irq, \ + } \ + } + +#define MSM_GPIO_BROKEN_INT_CLEAR 1 + +struct msm_gpio_regs { + void __iomem *out; + void __iomem *in; + void __iomem *int_status; + void __iomem *int_clear; + void __iomem *int_en; + void __iomem *int_edge; + void __iomem *int_pos; + void __iomem *oe; +}; + +struct msm_gpio_chip { + spinlock_t lock; + struct gpio_chip chip; + struct msm_gpio_regs regs; +#if MSM_GPIO_BROKEN_INT_CLEAR + unsigned int_status_copy; +#endif + unsigned int both_edge_detect; + unsigned int int_enable[2]; /* 0: awake, 1: sleep */ +}; + +static int msm_gpio_write(struct msm_gpio_chip *msm_chip, + unsigned offset, unsigned on) +{ + unsigned mask = BIT(offset); + unsigned val; + + val = readl(msm_chip->regs.out); + if (on) + writel(val | mask, msm_chip->regs.out); + else + writel(val & ~mask, msm_chip->regs.out); + return 0; +} + +static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip) +{ + int loop_limit = 100; + unsigned pol, val, val2, intstat; + do { + val = readl(msm_chip->regs.in); + pol = readl(msm_chip->regs.int_pos); + pol = (pol & ~msm_chip->both_edge_detect) | + (~val & msm_chip->both_edge_detect); + writel(pol, msm_chip->regs.int_pos); + intstat = readl(msm_chip->regs.int_status); + val2 = readl(msm_chip->regs.in); + if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) + return; + } while (loop_limit-- > 0); + printk(KERN_ERR "msm_gpio_update_both_edge_detect, " + "failed to reach stable state %x != %x\n", val, val2); +} + +static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip, + unsigned offset) +{ + unsigned bit = BIT(offset); + +#if MSM_GPIO_BROKEN_INT_CLEAR + /* Save interrupts that already triggered before we loose them. */ + /* Any interrupt that triggers between the read of int_status */ + /* and the write to int_clear will still be lost though. */ + msm_chip->int_status_copy |= readl(msm_chip->regs.int_status); + msm_chip->int_status_copy &= ~bit; +#endif + writel(bit, msm_chip->regs.int_clear); + msm_gpio_update_both_edge_detect(msm_chip); + return 0; +} + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct msm_gpio_chip *msm_chip; + unsigned long irq_flags; + + msm_chip = container_of(chip, struct msm_gpio_chip, chip); + spin_lock_irqsave(&msm_chip->lock, irq_flags); + writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe); + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); + return 0; +} + +static int +msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + struct msm_gpio_chip *msm_chip; + unsigned long irq_flags; + + msm_chip = container_of(chip, struct msm_gpio_chip, chip); + spin_lock_irqsave(&msm_chip->lock, irq_flags); + msm_gpio_write(msm_chip, offset, value); + writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe); + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); + return 0; +} + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct msm_gpio_chip *msm_chip; + + msm_chip = container_of(chip, struct msm_gpio_chip, chip); + return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0; +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct msm_gpio_chip *msm_chip; + unsigned long irq_flags; + + msm_chip = container_of(chip, struct msm_gpio_chip, chip); + spin_lock_irqsave(&msm_chip->lock, irq_flags); + msm_gpio_write(msm_chip, offset, value); + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); +} + +static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return MSM_GPIO_TO_INT(chip->base + offset); +} + +struct msm_gpio_chip msm_gpio_chips[] = { +#if defined(CONFIG_ARCH_MSM7X00A) + MSM_GPIO_BANK(0, 0, 15), + MSM_GPIO_BANK(1, 16, 42), + MSM_GPIO_BANK(2, 43, 67), + MSM_GPIO_BANK(3, 68, 94), + MSM_GPIO_BANK(4, 95, 106), + MSM_GPIO_BANK(5, 107, 121), +#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27) + MSM_GPIO_BANK(0, 0, 15), + MSM_GPIO_BANK(1, 16, 42), + MSM_GPIO_BANK(2, 43, 67), + MSM_GPIO_BANK(3, 68, 94), + MSM_GPIO_BANK(4, 95, 106), + MSM_GPIO_BANK(5, 107, 132), +#elif defined(CONFIG_ARCH_MSM7X30) + MSM_GPIO_BANK(0, 0, 15), + MSM_GPIO_BANK(1, 16, 43), + MSM_GPIO_BANK(2, 44, 67), + MSM_GPIO_BANK(3, 68, 94), + MSM_GPIO_BANK(4, 95, 106), + MSM_GPIO_BANK(5, 107, 133), + MSM_GPIO_BANK(6, 134, 150), + MSM_GPIO_BANK(7, 151, 181), +#elif defined(CONFIG_ARCH_QSD8X50) + MSM_GPIO_BANK(0, 0, 15), + MSM_GPIO_BANK(1, 16, 42), + MSM_GPIO_BANK(2, 43, 67), + MSM_GPIO_BANK(3, 68, 94), + MSM_GPIO_BANK(4, 95, 103), + MSM_GPIO_BANK(5, 104, 121), + MSM_GPIO_BANK(6, 122, 152), + MSM_GPIO_BANK(7, 153, 164), +#endif +}; + +static void msm_gpio_irq_ack(unsigned int irq) +{ + unsigned long irq_flags; + struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + spin_lock_irqsave(&msm_chip->lock, irq_flags); + msm_gpio_clear_detect_status(msm_chip, + irq - gpio_to_irq(msm_chip->chip.base)); + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); +} + +static void msm_gpio_irq_mask(unsigned int irq) +{ + unsigned long irq_flags; + struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + + spin_lock_irqsave(&msm_chip->lock, irq_flags); + /* level triggered interrupts are also latched */ + if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) + msm_gpio_clear_detect_status(msm_chip, offset); + msm_chip->int_enable[0] &= ~BIT(offset); + writel(msm_chip->int_enable[0], msm_chip->regs.int_en); + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); +} + +static void msm_gpio_irq_unmask(unsigned int irq) +{ + unsigned long irq_flags; + struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + + spin_lock_irqsave(&msm_chip->lock, irq_flags); + /* level triggered interrupts are also latched */ + if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) + msm_gpio_clear_detect_status(msm_chip, offset); + msm_chip->int_enable[0] |= BIT(offset); + writel(msm_chip->int_enable[0], msm_chip->regs.int_en); + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); +} + +static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) +{ + unsigned long irq_flags; + struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + + spin_lock_irqsave(&msm_chip->lock, irq_flags); + + if (on) + msm_chip->int_enable[1] |= BIT(offset); + else + msm_chip->int_enable[1] &= ~BIT(offset); + + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); + return 0; +} + +static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +{ + unsigned long irq_flags; + struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq); + unsigned offset = irq - gpio_to_irq(msm_chip->chip.base); + unsigned val, mask = BIT(offset); + + spin_lock_irqsave(&msm_chip->lock, irq_flags); + val = readl(msm_chip->regs.int_edge); + if (flow_type & IRQ_TYPE_EDGE_BOTH) { + writel(val | mask, msm_chip->regs.int_edge); + irq_desc[irq].handle_irq = handle_edge_irq; + } else { + writel(val & ~mask, msm_chip->regs.int_edge); + irq_desc[irq].handle_irq = handle_level_irq; + } + if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + msm_chip->both_edge_detect |= mask; + msm_gpio_update_both_edge_detect(msm_chip); + } else { + msm_chip->both_edge_detect &= ~mask; + val = readl(msm_chip->regs.int_pos); + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) + writel(val | mask, msm_chip->regs.int_pos); + else + writel(val & ~mask, msm_chip->regs.int_pos); + } + spin_unlock_irqrestore(&msm_chip->lock, irq_flags); + return 0; +} + +static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + int i, j, mask; + unsigned val; + + for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { + struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; + val = readl(msm_chip->regs.int_status); + val &= msm_chip->int_enable[0]; + while (val) { + mask = val & -val; + j = fls(mask) - 1; + /* printk("%s %08x %08x bit %d gpio %d irq %d\n", + __func__, v, m, j, msm_chip->chip.start + j, + FIRST_GPIO_IRQ + msm_chip->chip.start + j); */ + val &= ~mask; + generic_handle_irq(FIRST_GPIO_IRQ + + msm_chip->chip.base + j); + } + } + desc->chip->ack(irq); +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .ack = msm_gpio_irq_ack, + .mask = msm_gpio_irq_mask, + .unmask = msm_gpio_irq_unmask, + .set_wake = msm_gpio_irq_set_wake, + .set_type = msm_gpio_irq_set_type, +}; + +static int __init msm_init_gpio(void) +{ + int i, j = 0; + + for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { + if (i - FIRST_GPIO_IRQ >= + msm_gpio_chips[j].chip.base + + msm_gpio_chips[j].chip.ngpio) + j++; + set_irq_chip_data(i, &msm_gpio_chips[j]); + set_irq_chip(i, &msm_gpio_irq_chip); + set_irq_handler(i, handle_edge_irq); + set_irq_flags(i, IRQF_VALID); + } + + for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { + spin_lock_init(&msm_gpio_chips[i].lock); + writel(0, msm_gpio_chips[i].regs.int_en); + gpiochip_add(&msm_gpio_chips[i].chip); + } + + set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); + set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); + set_irq_wake(INT_GPIO_GROUP1, 1); + set_irq_wake(INT_GPIO_GROUP2, 2); + return 0; +} + +postcore_initcall(msm_init_gpio); diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h new file mode 100644 index 000000000000..6b5066038baa --- /dev/null +++ b/arch/arm/mach-msm/gpio_hw.h @@ -0,0 +1,278 @@ +/* arch/arm/mach-msm/gpio_hw.h + * + * Copyright (C) 2007 Google, Inc. + * Author: Brian Swetland + * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H +#define __ARCH_ARM_MACH_MSM_GPIO_HW_H + +#include + +/* see 80-VA736-2 Rev C pp 695-751 +** +** These are actually the *shadow* gpio registers, since the +** real ones (which allow full access) are only available to the +** ARM9 side of the world. +** +** Since the _BASE need to be page-aligned when we're mapping them +** to virtual addresses, adjust for the additional offset in these +** macros. +*/ + +#if defined(CONFIG_ARCH_MSM7X30) +#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) +#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) +#else +#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) +#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) +#endif + +#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\ + defined(CONFIG_ARCH_MSM7X27) + +/* output value */ +#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ +#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ +#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ +#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ +#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ +#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */ + +/* same pin map as above, output enable */ +#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) +#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) +#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) +#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) +#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) +#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) + +/* same pin map as above, input read */ +#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) +#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) +#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) +#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) +#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) +#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) + +/* same pin map as above, 1=edge 0=level interrup */ +#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) +#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) +#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) +#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) +#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) +#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) + +/* same pin map as above, 1=positive 0=negative */ +#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) +#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) +#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) +#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) +#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) +#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) + +/* same pin map as above, interrupt enable */ +#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) +#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) +#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) +#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) +#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) +#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) + +/* same pin map as above, write 1 to clear interrupt */ +#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) +#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) +#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) +#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) +#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) +#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) + +/* same pin map as above, 1=interrupt pending */ +#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) +#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) +#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) +#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) +#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) +#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) + +#endif + +#if defined(CONFIG_ARCH_QSD8X50) +/* output value */ +#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ +#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ +#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ +#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ +#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */ +#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */ +#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */ +#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */ + +/* same pin map as above, output enable */ +#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20) +#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) +#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24) +#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28) +#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C) +#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30) +#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34) +#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38) + +/* same pin map as above, input read */ +#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50) +#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) +#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54) +#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58) +#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C) +#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60) +#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64) +#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68) + +/* same pin map as above, 1=edge 0=level interrup */ +#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70) +#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) +#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74) +#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78) +#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C) +#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80) +#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84) +#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88) + +/* same pin map as above, 1=positive 0=negative */ +#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90) +#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) +#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94) +#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98) +#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C) +#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0) +#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4) +#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8) + +/* same pin map as above, interrupt enable */ +#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0) +#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) +#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4) +#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8) +#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC) +#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0) +#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4) +#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8) + +/* same pin map as above, write 1 to clear interrupt */ +#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0) +#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) +#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4) +#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8) +#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC) +#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0) +#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4) +#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8) + +/* same pin map as above, 1=interrupt pending */ +#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0) +#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) +#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4) +#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8) +#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC) +#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100) +#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104) +#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108) + +#endif + +#if defined(CONFIG_ARCH_MSM7X30) + +/* output value */ +#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ +#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ +#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ +#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ +#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ +#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ +#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ +#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ + +/* same pin map as above, output enable */ +#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) +#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) +#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) +#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) +#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) +#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) +#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8) +#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218) + +/* same pin map as above, input read */ +#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) +#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) +#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) +#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) +#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) +#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) +#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC) +#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C) + +/* same pin map as above, 1=edge 0=level interrup */ +#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) +#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) +#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) +#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) +#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) +#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) +#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) +#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) + +/* same pin map as above, 1=positive 0=negative */ +#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) +#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) +#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) +#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) +#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) +#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) +#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) +#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) + +/* same pin map as above, interrupt enable */ +#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) +#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) +#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) +#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) +#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) +#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) +#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) +#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) + +/* same pin map as above, write 1 to clear interrupt */ +#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) +#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) +#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) +#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) +#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) +#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) +#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) +#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) + +/* same pin map as above, 1=interrupt pending */ +#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) +#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) +#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) +#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) +#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) +#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) +#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) +#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) + +#endif + +#endif -- cgit v1.2.3 From 26cc66607189ac544edad04927f506599d990f0f Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Fri, 10 Sep 2010 15:03:37 -0700 Subject: msm: gpio: Add gpiomux calls to request and free. Add gpiomux get and put calls to msmgpio request and free, in order to allow gpio lines to be properly reference-counted and power-managed. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/gpio.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 5040f1cb64f9..33051b509e88 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -21,6 +21,7 @@ #include #include #include "gpio_hw.h" +#include "gpiomux.h" #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) @@ -44,6 +45,8 @@ .direction_input = msm_gpio_direction_input, \ .direction_output = msm_gpio_direction_output, \ .to_irq = msm_gpio_to_irq, \ + .request = msm_gpio_request, \ + .free = msm_gpio_free, \ } \ } @@ -171,6 +174,21 @@ static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) return MSM_GPIO_TO_INT(chip->base + offset); } +#ifdef CONFIG_MSM_GPIOMUX +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return msm_gpiomux_get(chip->base + offset); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + msm_gpiomux_put(chip->base + offset); +} +#else +#define msm_gpio_request NULL +#define msm_gpio_free NULL +#endif + struct msm_gpio_chip msm_gpio_chips[] = { #if defined(CONFIG_ARCH_MSM7X00A) MSM_GPIO_BANK(0, 0, 15), -- cgit v1.2.3 From 5d73c53b786665f991f70be01a51a23233aeb44f Mon Sep 17 00:00:00 2001 From: Gregory Bean Date: Wed, 29 Sep 2010 13:46:45 -0700 Subject: msm: qsd8x50: enable ethernet. Configure the smc91x ethernet chip on the qsd8x50 SURF. Signed-off-by: Gregory Bean Signed-off-by: Daniel Walker --- arch/arm/mach-msm/board-qsd8x50.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index fb0fe6771e56..9e4cf2441122 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c @@ -35,6 +35,45 @@ extern struct sys_timer msm_timer; +static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300; +static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156; + +/* Leave smc91x resources empty here, as we'll fill them in + * at run-time: they vary from board to board, and the true + * configuration won't be known until boot. + */ +static struct resource smc91x_resources[] __initdata = { + [0] = { + .flags = IORESOURCE_MEM, + }, + [1] = { + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device __initdata = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static int __init msm_init_smc91x(void) +{ + if (machine_is_qsd8x50_surf()) { + smc91x_resources[0].start = qsd8x50_surf_smc91x_base; + smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff; + smc91x_resources[1].start = + gpio_to_irq(qsd8x50_surf_smc91x_gpio); + smc91x_resources[1].end = + gpio_to_irq(qsd8x50_surf_smc91x_gpio); + platform_device_register(&smc91x_device); + } + + return 0; +} +module_init(msm_init_smc91x); + static struct platform_device *devices[] __initdata = { &msm_device_uart3, }; -- cgit v1.2.3 From df9ee29270c11dba7d0fe0b83ce47a4d8e8d2101 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 7 Oct 2010 14:08:55 +0100 Subject: Fix IRQ flag handling naming Fix the IRQ flag handling naming. In linux/irqflags.h under one configuration, it maps: local_irq_enable() -> raw_local_irq_enable() local_irq_disable() -> raw_local_irq_disable() local_irq_save() -> raw_local_irq_save() ... and under the other configuration, it maps: raw_local_irq_enable() -> local_irq_enable() raw_local_irq_disable() -> local_irq_disable() raw_local_irq_save() -> local_irq_save() ... This is quite confusing. There should be one set of names expected of the arch, and this should be wrapped to give another set of names that are expected by users of this facility. Change this to have the arch provide: flags = arch_local_save_flags() flags = arch_local_irq_save() arch_local_irq_restore(flags) arch_local_irq_disable() arch_local_irq_enable() arch_irqs_disabled_flags(flags) arch_irqs_disabled() arch_safe_halt() Then linux/irqflags.h wraps these to provide: raw_local_save_flags(flags) raw_local_irq_save(flags) raw_local_irq_restore(flags) raw_local_irq_disable() raw_local_irq_enable() raw_irqs_disabled_flags(flags) raw_irqs_disabled() raw_safe_halt() with type checking on the flags 'arguments', and then wraps those to provide: local_save_flags(flags) local_irq_save(flags) local_irq_restore(flags) local_irq_disable() local_irq_enable() irqs_disabled_flags(flags) irqs_disabled() safe_halt() with tracing included if enabled. The arch functions can now all be inline functions rather than some of them having to be macros. Signed-off-by: David Howells [X86, FRV, MN10300] Signed-off-by: Chris Metcalf [Tile] Signed-off-by: Michal Simek [Microblaze] Tested-by: Catalin Marinas [ARM] Acked-by: Thomas Gleixner Acked-by: Haavard Skinnemoen [AVR] Acked-by: Tony Luck [IA-64] Acked-by: Hirokazu Takata [M32R] Acked-by: Greg Ungerer [M68K/M68KNOMMU] Acked-by: Ralf Baechle [MIPS] Acked-by: Kyle McMartin [PA-RISC] Acked-by: Paul Mackerras [PowerPC] Acked-by: Martin Schwidefsky [S390] Acked-by: Chen Liqin [Score] Acked-by: Matt Fleming [SH] Acked-by: David S. Miller [Sparc] Acked-by: Chris Zankel [Xtensa] Reviewed-by: Richard Henderson [Alpha] Reviewed-by: Yoshinori Sato [H8300] Cc: starvik@axis.com [CRIS] Cc: jesper.nilsson@axis.com [CRIS] Cc: linux-cris-kernel@axis.com --- arch/alpha/include/asm/irqflags.h | 67 ++++++++++ arch/alpha/include/asm/system.h | 28 ----- arch/arm/include/asm/irqflags.h | 145 +++++++++++++--------- arch/avr32/include/asm/irqflags.h | 29 ++--- arch/blackfin/include/asm/irqflags.h | 12 -- arch/blackfin/kernel/trace.c | 1 + arch/cris/include/arch-v10/arch/irqflags.h | 45 +++++++ arch/cris/include/arch-v10/arch/system.h | 16 --- arch/cris/include/arch-v32/arch/irqflags.h | 46 +++++++ arch/cris/include/arch-v32/arch/system.h | 22 ---- arch/cris/include/asm/irqflags.h | 1 + arch/cris/include/asm/system.h | 1 + arch/frv/include/asm/irqflags.h | 158 +++++++++++++++++++++++ arch/frv/include/asm/system.h | 136 -------------------- arch/h8300/include/asm/irqflags.h | 43 +++++++ arch/h8300/include/asm/system.h | 24 +--- arch/ia64/include/asm/irqflags.h | 94 ++++++++++++++ arch/ia64/include/asm/system.h | 76 ------------ arch/m32r/include/asm/irqflags.h | 104 ++++++++++++++++ arch/m32r/include/asm/system.h | 66 +--------- arch/m68k/include/asm/entry_no.h | 2 +- arch/m68k/include/asm/irqflags.h | 76 ++++++++++++ arch/m68k/include/asm/system_mm.h | 25 +--- arch/m68k/include/asm/system_no.h | 57 +-------- arch/m68knommu/kernel/asm-offsets.c | 2 - arch/m68knommu/platform/coldfire/head.S | 1 + arch/microblaze/include/asm/irqflags.h | 193 +++++++++++++++-------------- arch/mips/include/asm/irqflags.h | 53 ++++---- arch/mips/kernel/smtc.c | 4 +- arch/mn10300/include/asm/irqflags.h | 123 ++++++++++++++++++ arch/mn10300/include/asm/system.h | 109 +--------------- arch/mn10300/kernel/entry.S | 1 + arch/parisc/include/asm/irqflags.h | 46 +++++++ arch/parisc/include/asm/system.h | 19 +-- arch/powerpc/include/asm/hw_irq.h | 113 ++++++++++------- arch/powerpc/include/asm/irqflags.h | 2 +- arch/powerpc/kernel/exceptions-64s.S | 4 +- arch/powerpc/kernel/irq.c | 4 +- arch/s390/include/asm/irqflags.h | 51 ++++---- arch/s390/include/asm/system.h | 2 +- arch/s390/kernel/mem_detect.c | 4 +- arch/s390/mm/init.c | 3 +- arch/s390/mm/maccess.c | 4 +- arch/score/include/asm/irqflags.h | 187 +++++++++++++++------------- arch/sh/include/asm/irqflags.h | 4 +- arch/sh/kernel/irq_32.c | 12 +- arch/sparc/include/asm/irqflags_32.h | 35 +++--- arch/sparc/include/asm/irqflags_64.h | 29 ++--- arch/sparc/kernel/irq_32.c | 13 +- arch/sparc/prom/p1275.c | 2 +- arch/tile/include/asm/irqflags.h | 36 +++--- arch/x86/include/asm/irqflags.h | 32 ++--- arch/x86/include/asm/paravirt.h | 16 +-- arch/x86/xen/spinlock.c | 2 +- arch/xtensa/include/asm/irqflags.h | 58 +++++++++ arch/xtensa/include/asm/system.h | 33 +---- drivers/s390/char/sclp.c | 2 +- include/asm-generic/atomic.h | 5 +- include/asm-generic/cmpxchg-local.h | 1 + include/asm-generic/hardirq.h | 1 - include/asm-generic/irqflags.h | 52 ++++---- include/linux/irqflags.h | 107 +++++++++------- include/linux/spinlock.h | 1 + 63 files changed, 1482 insertions(+), 1158 deletions(-) create mode 100644 arch/alpha/include/asm/irqflags.h create mode 100644 arch/cris/include/arch-v10/arch/irqflags.h create mode 100644 arch/cris/include/arch-v32/arch/irqflags.h create mode 100644 arch/cris/include/asm/irqflags.h create mode 100644 arch/frv/include/asm/irqflags.h create mode 100644 arch/h8300/include/asm/irqflags.h create mode 100644 arch/ia64/include/asm/irqflags.h create mode 100644 arch/m32r/include/asm/irqflags.h create mode 100644 arch/m68k/include/asm/irqflags.h create mode 100644 arch/mn10300/include/asm/irqflags.h create mode 100644 arch/parisc/include/asm/irqflags.h create mode 100644 arch/xtensa/include/asm/irqflags.h (limited to 'arch/arm') diff --git a/arch/alpha/include/asm/irqflags.h b/arch/alpha/include/asm/irqflags.h new file mode 100644 index 000000000000..299bbc7e9d71 --- /dev/null +++ b/arch/alpha/include/asm/irqflags.h @@ -0,0 +1,67 @@ +#ifndef __ALPHA_IRQFLAGS_H +#define __ALPHA_IRQFLAGS_H + +#include + +#define IPL_MIN 0 +#define IPL_SW0 1 +#define IPL_SW1 2 +#define IPL_DEV0 3 +#define IPL_DEV1 4 +#define IPL_TIMER 5 +#define IPL_PERF 6 +#define IPL_POWERFAIL 6 +#define IPL_MCHECK 7 +#define IPL_MAX 7 + +#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK +#undef IPL_MIN +#define IPL_MIN __min_ipl +extern int __min_ipl; +#endif + +#define getipl() (rdps() & 7) +#define setipl(ipl) ((void) swpipl(ipl)) + +static inline unsigned long arch_local_save_flags(void) +{ + return rdps(); +} + +static inline void arch_local_irq_disable(void) +{ + setipl(IPL_MAX); + barrier(); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = swpipl(IPL_MAX); + barrier(); + return flags; +} + +static inline void arch_local_irq_enable(void) +{ + barrier(); + setipl(IPL_MIN); +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + barrier(); + setipl(flags); + barrier(); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return flags == IPL_MAX; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(getipl()); +} + +#endif /* __ALPHA_IRQFLAGS_H */ diff --git a/arch/alpha/include/asm/system.h b/arch/alpha/include/asm/system.h index 5aa40cca4f23..9f78e6934637 100644 --- a/arch/alpha/include/asm/system.h +++ b/arch/alpha/include/asm/system.h @@ -259,34 +259,6 @@ __CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long); __CALL_PAL_W1(wrusp, unsigned long); __CALL_PAL_W1(wrvptptr, unsigned long); -#define IPL_MIN 0 -#define IPL_SW0 1 -#define IPL_SW1 2 -#define IPL_DEV0 3 -#define IPL_DEV1 4 -#define IPL_TIMER 5 -#define IPL_PERF 6 -#define IPL_POWERFAIL 6 -#define IPL_MCHECK 7 -#define IPL_MAX 7 - -#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK -#undef IPL_MIN -#define IPL_MIN __min_ipl -extern int __min_ipl; -#endif - -#define getipl() (rdps() & 7) -#define setipl(ipl) ((void) swpipl(ipl)) - -#define local_irq_disable() do { setipl(IPL_MAX); barrier(); } while(0) -#define local_irq_enable() do { barrier(); setipl(IPL_MIN); } while(0) -#define local_save_flags(flags) ((flags) = rdps()) -#define local_irq_save(flags) do { (flags) = swpipl(IPL_MAX); barrier(); } while(0) -#define local_irq_restore(flags) do { barrier(); setipl(flags); barrier(); } while(0) - -#define irqs_disabled() (getipl() == IPL_MAX) - /* * TB routines.. */ diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h index 6d09974e6646..1e6cca55c750 100644 --- a/arch/arm/include/asm/irqflags.h +++ b/arch/arm/include/asm/irqflags.h @@ -10,66 +10,85 @@ */ #if __LINUX_ARM_ARCH__ >= 6 -#define raw_local_irq_save(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ - "cpsid i" \ - : "=r" (x) : : "memory", "cc"); \ - }) +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + + asm volatile( + " mrs %0, cpsr @ arch_local_irq_save\n" + " cpsid i" + : "=r" (flags) : : "memory", "cc"); + return flags; +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile( + " cpsie i @ arch_local_irq_enable" + : + : + : "memory", "cc"); +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile( + " cpsid i @ arch_local_irq_disable" + : + : + : "memory", "cc"); +} -#define raw_local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") -#define raw_local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") #define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") #define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") - #else /* * Save the current interrupt enable state & disable IRQs */ -#define raw_local_irq_save(x) \ - ({ \ - unsigned long temp; \ - (void) (&temp == &x); \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_save\n" \ -" orr %1, %0, #128\n" \ -" msr cpsr_c, %1" \ - : "=r" (x), "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) - +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags, temp; + + asm volatile( + " mrs %0, cpsr @ arch_local_irq_save\n" + " orr %1, %0, #128\n" + " msr cpsr_c, %1" + : "=r" (flags), "=r" (temp) + : + : "memory", "cc"); + return flags; +} + /* * Enable IRQs */ -#define raw_local_irq_enable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_enable\n" \ -" bic %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) +static inline void arch_local_irq_enable(void) +{ + unsigned long temp; + asm volatile( + " mrs %0, cpsr @ arch_local_irq_enable\n" + " bic %0, %0, #128\n" + " msr cpsr_c, %0" + : "=r" (temp) + : + : "memory", "cc"); +} /* * Disable IRQs */ -#define raw_local_irq_disable() \ - ({ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_irq_disable\n" \ -" orr %0, %0, #128\n" \ -" msr cpsr_c, %0" \ - : "=r" (temp) \ - : \ - : "memory", "cc"); \ - }) +static inline void arch_local_irq_disable(void) +{ + unsigned long temp; + asm volatile( + " mrs %0, cpsr @ arch_local_irq_disable\n" + " orr %0, %0, #128\n" + " msr cpsr_c, %0" + : "=r" (temp) + : + : "memory", "cc"); +} /* * Enable FIQs @@ -106,27 +125,31 @@ /* * Save the current interrupt enable state. */ -#define raw_local_save_flags(x) \ - ({ \ - __asm__ __volatile__( \ - "mrs %0, cpsr @ local_save_flags" \ - : "=r" (x) : : "memory", "cc"); \ - }) +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile( + " mrs %0, cpsr @ local_save_flags" + : "=r" (flags) : : "memory", "cc"); + return flags; +} /* * restore saved IRQ & FIQ state */ -#define raw_local_irq_restore(x) \ - __asm__ __volatile__( \ - "msr cpsr_c, %0 @ local_irq_restore\n" \ - : \ - : "r" (x) \ - : "memory", "cc") +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile( + " msr cpsr_c, %0 @ local_irq_restore" + : + : "r" (flags) + : "memory", "cc"); +} -#define raw_irqs_disabled_flags(flags) \ -({ \ - (int)((flags) & PSR_I_BIT); \ -}) +static inline int arch_irqs_disabled_flags(unsigned long flags) +{ + return flags & PSR_I_BIT; +} #endif #endif diff --git a/arch/avr32/include/asm/irqflags.h b/arch/avr32/include/asm/irqflags.h index 93570daac38a..006e9487372d 100644 --- a/arch/avr32/include/asm/irqflags.h +++ b/arch/avr32/include/asm/irqflags.h @@ -8,16 +8,14 @@ #ifndef __ASM_AVR32_IRQFLAGS_H #define __ASM_AVR32_IRQFLAGS_H +#include #include -static inline unsigned long __raw_local_save_flags(void) +static inline unsigned long arch_local_save_flags(void) { return sysreg_read(SR); } -#define raw_local_save_flags(x) \ - do { (x) = __raw_local_save_flags(); } while (0) - /* * This will restore ALL status register flags, not only the interrupt * mask flag. @@ -25,44 +23,39 @@ static inline unsigned long __raw_local_save_flags(void) * The empty asm statement informs the compiler of this fact while * also serving as a barrier. */ -static inline void raw_local_irq_restore(unsigned long flags) +static inline void arch_local_irq_restore(unsigned long flags) { sysreg_write(SR, flags); asm volatile("" : : : "memory", "cc"); } -static inline void raw_local_irq_disable(void) +static inline void arch_local_irq_disable(void) { asm volatile("ssrf %0" : : "n"(SYSREG_GM_OFFSET) : "memory"); } -static inline void raw_local_irq_enable(void) +static inline void arch_local_irq_enable(void) { asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET) : "memory"); } -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline bool arch_irqs_disabled_flags(unsigned long flags) { return (flags & SYSREG_BIT(GM)) != 0; } -static inline int raw_irqs_disabled(void) +static inline bool arch_irqs_disabled(void) { - unsigned long flags = __raw_local_save_flags(); - - return raw_irqs_disabled_flags(flags); + return arch_irqs_disabled_flags(arch_local_save_flags()); } -static inline unsigned long __raw_local_irq_save(void) +static inline unsigned long arch_local_irq_save(void) { - unsigned long flags = __raw_local_save_flags(); + unsigned long flags = arch_local_save_flags(); - raw_local_irq_disable(); + arch_local_irq_disable(); return flags; } -#define raw_local_irq_save(flags) \ - do { (flags) = __raw_local_irq_save(); } while (0) - #endif /* __ASM_AVR32_IRQFLAGS_H */ diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 994d76791016..41c4d70544ef 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -218,16 +218,4 @@ static inline void hard_local_irq_restore(unsigned long flags) #endif /* !CONFIG_IPIPE */ - -/* - * Raw interface to linux/irqflags.h. - */ -#define raw_local_save_flags(flags) do { (flags) = arch_local_save_flags(); } while (0) -#define raw_local_irq_save(flags) do { (flags) = arch_local_irq_save(); } while (0) -#define raw_local_irq_restore(flags) arch_local_irq_restore(flags) -#define raw_local_irq_enable() arch_local_irq_enable() -#define raw_local_irq_disable() arch_local_irq_disable() -#define raw_irqs_disabled_flags(flags) arch_irqs_disabled_flags(flags) -#define raw_irqs_disabled() arch_irqs_disabled() - #endif diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c index 59fcdf6b0138..05b550891ce5 100644 --- a/arch/blackfin/kernel/trace.c +++ b/arch/blackfin/kernel/trace.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/cris/include/arch-v10/arch/irqflags.h b/arch/cris/include/arch-v10/arch/irqflags.h new file mode 100644 index 000000000000..75ef18991240 --- /dev/null +++ b/arch/cris/include/arch-v10/arch/irqflags.h @@ -0,0 +1,45 @@ +#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H +#define __ASM_CRIS_ARCH_IRQFLAGS_H + +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("move $ccr,%0" : "=rm" (flags) : : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile("di" : : : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile("ei" : : : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("move %0,$ccr" : : "rm" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & (1 << 5)); +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */ diff --git a/arch/cris/include/arch-v10/arch/system.h b/arch/cris/include/arch-v10/arch/system.h index 4a9cd36c9e16..935fde34aa15 100644 --- a/arch/cris/include/arch-v10/arch/system.h +++ b/arch/cris/include/arch-v10/arch/system.h @@ -44,20 +44,4 @@ static inline unsigned long _get_base(char * addr) struct __xchg_dummy { unsigned long a[100]; }; #define __xg(x) ((struct __xchg_dummy *)(x)) -/* interrupt control.. */ -#define local_save_flags(x) __asm__ __volatile__ ("move $ccr,%0" : "=rm" (x) : : "memory"); -#define local_irq_restore(x) __asm__ __volatile__ ("move %0,$ccr" : : "rm" (x) : "memory"); -#define local_irq_disable() __asm__ __volatile__ ( "di" : : :"memory"); -#define local_irq_enable() __asm__ __volatile__ ( "ei" : : :"memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - !(flags & (1<<5)); \ -}) - -/* For spinlocks etc */ -#define local_irq_save(x) __asm__ __volatile__ ("move $ccr,%0\n\tdi" : "=rm" (x) : : "memory"); - #endif diff --git a/arch/cris/include/arch-v32/arch/irqflags.h b/arch/cris/include/arch-v32/arch/irqflags.h new file mode 100644 index 000000000000..041851f8ec6f --- /dev/null +++ b/arch/cris/include/arch-v32/arch/irqflags.h @@ -0,0 +1,46 @@ +#ifndef __ASM_CRIS_ARCH_IRQFLAGS_H +#define __ASM_CRIS_ARCH_IRQFLAGS_H + +#include +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("move $ccs,%0" : "=rm" (flags) : : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile("di" : : : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile("ei" : : : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("move %0,$ccs" : : "rm" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & (1 << I_CCS_BITNR)); +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* __ASM_CRIS_ARCH_IRQFLAGS_H */ diff --git a/arch/cris/include/arch-v32/arch/system.h b/arch/cris/include/arch-v32/arch/system.h index 6ca90f1f110a..76cea99eaa60 100644 --- a/arch/cris/include/arch-v32/arch/system.h +++ b/arch/cris/include/arch-v32/arch/system.h @@ -44,26 +44,4 @@ static inline unsigned long rdsp(void) struct __xchg_dummy { unsigned long a[100]; }; #define __xg(x) ((struct __xchg_dummy *)(x)) -/* Used for interrupt control. */ -#define local_save_flags(x) \ - __asm__ __volatile__ ("move $ccs, %0" : "=rm" (x) : : "memory"); - -#define local_irq_restore(x) \ - __asm__ __volatile__ ("move %0, $ccs" : : "rm" (x) : "memory"); - -#define local_irq_disable() __asm__ __volatile__ ("di" : : : "memory"); -#define local_irq_enable() __asm__ __volatile__ ("ei" : : : "memory"); - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - \ - local_save_flags(flags);\ - !(flags & (1 << I_CCS_BITNR)); \ -}) - -/* Used for spinlocks, etc. */ -#define local_irq_save(x) \ - __asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory"); - #endif /* _ASM_CRIS_ARCH_SYSTEM_H */ diff --git a/arch/cris/include/asm/irqflags.h b/arch/cris/include/asm/irqflags.h new file mode 100644 index 000000000000..943ba5ca6d2c --- /dev/null +++ b/arch/cris/include/asm/irqflags.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/asm/system.h b/arch/cris/include/asm/system.h index 8657b084a922..ea10592f7d75 100644 --- a/arch/cris/include/asm/system.h +++ b/arch/cris/include/asm/system.h @@ -1,6 +1,7 @@ #ifndef __ASM_CRIS_SYSTEM_H #define __ASM_CRIS_SYSTEM_H +#include #include /* the switch_to macro calls resume, an asm function in entry.S which does the actual diff --git a/arch/frv/include/asm/irqflags.h b/arch/frv/include/asm/irqflags.h new file mode 100644 index 000000000000..82f0b5363f42 --- /dev/null +++ b/arch/frv/include/asm/irqflags.h @@ -0,0 +1,158 @@ +/* FR-V interrupt handling + * + * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_IRQFLAGS_H +#define _ASM_IRQFLAGS_H + +/* + * interrupt flag manipulation + * - use virtual interrupt management since touching the PSR is slow + * - ICC2.Z: T if interrupts virtually disabled + * - ICC2.C: F if interrupts really disabled + * - if Z==1 upon interrupt: + * - C is set to 0 + * - interrupts are really disabled + * - entry.S returns immediately + * - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts + * - if taken, the trap: + * - sets ICC2.C + * - enables interrupts + */ +static inline void arch_local_irq_disable(void) +{ + /* set Z flag, but don't change the C flag */ + asm volatile(" andcc gr0,gr0,gr0,icc2 \n" + : + : + : "memory", "icc2" + ); +} + +static inline void arch_local_irq_enable(void) +{ + /* clear Z flag and then test the C flag */ + asm volatile(" oricc gr0,#1,gr0,icc2 \n" + " tihi icc2,gr0,#2 \n" + : + : + : "memory", "icc2" + ); +} + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + + asm volatile("movsg ccr,%0" + : "=r"(flags) + : + : "memory"); + + /* shift ICC2.Z to bit 0 */ + flags >>= 26; + + /* make flags 1 if interrupts disabled, 0 otherwise */ + return flags & 1UL; + +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + /* load the Z flag by turning 1 if disabled into 0 if disabled + * and thus setting the Z flag but not the C flag */ + asm volatile(" xoricc %0,#1,gr0,icc2 \n" + /* then trap if Z=0 and C=0 */ + " tihi icc2,gr0,#2 \n" + : + : "r"(flags) + : "memory", "icc2" + ); + +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return flags; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +/* + * real interrupt flag manipulation + */ +#define __arch_local_irq_disable() \ +do { \ + unsigned long psr; \ + asm volatile(" movsg psr,%0 \n" \ + " andi %0,%2,%0 \n" \ + " ori %0,%1,%0 \n" \ + " movgs %0,psr \n" \ + : "=r"(psr) \ + : "i" (PSR_PIL_14), "i" (~PSR_PIL) \ + : "memory"); \ +} while (0) + +#define __arch_local_irq_enable() \ +do { \ + unsigned long psr; \ + asm volatile(" movsg psr,%0 \n" \ + " andi %0,%1,%0 \n" \ + " movgs %0,psr \n" \ + : "=r"(psr) \ + : "i" (~PSR_PIL) \ + : "memory"); \ +} while (0) + +#define __arch_local_save_flags(flags) \ +do { \ + typecheck(unsigned long, flags); \ + asm("movsg psr,%0" \ + : "=r"(flags) \ + : \ + : "memory"); \ +} while (0) + +#define __arch_local_irq_save(flags) \ +do { \ + unsigned long npsr; \ + typecheck(unsigned long, flags); \ + asm volatile(" movsg psr,%0 \n" \ + " andi %0,%3,%1 \n" \ + " ori %1,%2,%1 \n" \ + " movgs %1,psr \n" \ + : "=r"(flags), "=r"(npsr) \ + : "i" (PSR_PIL_14), "i" (~PSR_PIL) \ + : "memory"); \ +} while (0) + +#define __arch_local_irq_restore(flags) \ +do { \ + typecheck(unsigned long, flags); \ + asm volatile(" movgs %0,psr \n" \ + : \ + : "r" (flags) \ + : "memory"); \ +} while (0) + +#define __arch_irqs_disabled() \ + ((__get_PSR() & PSR_PIL) >= PSR_PIL_14) + +#endif /* _ASM_IRQFLAGS_H */ diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h index efd22d9077ac..0a6d8d9ca45b 100644 --- a/arch/frv/include/asm/system.h +++ b/arch/frv/include/asm/system.h @@ -36,142 +36,6 @@ do { \ mb(); \ } while(0) -/* - * interrupt flag manipulation - * - use virtual interrupt management since touching the PSR is slow - * - ICC2.Z: T if interrupts virtually disabled - * - ICC2.C: F if interrupts really disabled - * - if Z==1 upon interrupt: - * - C is set to 0 - * - interrupts are really disabled - * - entry.S returns immediately - * - uses TIHI (TRAP if Z==0 && C==0) #2 to really reenable interrupts - * - if taken, the trap: - * - sets ICC2.C - * - enables interrupts - */ -#define local_irq_disable() \ -do { \ - /* set Z flag, but don't change the C flag */ \ - asm volatile(" andcc gr0,gr0,gr0,icc2 \n" \ - : \ - : \ - : "memory", "icc2" \ - ); \ -} while(0) - -#define local_irq_enable() \ -do { \ - /* clear Z flag and then test the C flag */ \ - asm volatile(" oricc gr0,#1,gr0,icc2 \n" \ - " tihi icc2,gr0,#2 \n" \ - : \ - : \ - : "memory", "icc2" \ - ); \ -} while(0) - -#define local_save_flags(flags) \ -do { \ - typecheck(unsigned long, flags); \ - asm volatile("movsg ccr,%0" \ - : "=r"(flags) \ - : \ - : "memory"); \ - \ - /* shift ICC2.Z to bit 0 */ \ - flags >>= 26; \ - \ - /* make flags 1 if interrupts disabled, 0 otherwise */ \ - flags &= 1UL; \ -} while(0) - -#define irqs_disabled() \ - ({unsigned long flags; local_save_flags(flags); !!flags; }) - -#define local_irq_save(flags) \ -do { \ - typecheck(unsigned long, flags); \ - local_save_flags(flags); \ - local_irq_disable(); \ -} while(0) - -#define local_irq_restore(flags) \ -do { \ - typecheck(unsigned long, flags); \ - \ - /* load the Z flag by turning 1 if disabled into 0 if disabled \ - * and thus setting the Z flag but not the C flag */ \ - asm volatile(" xoricc %0,#1,gr0,icc2 \n" \ - /* then test Z=0 and C=0 */ \ - " tihi icc2,gr0,#2 \n" \ - : \ - : "r"(flags) \ - : "memory", "icc2" \ - ); \ - \ -} while(0) - -/* - * real interrupt flag manipulation - */ -#define __local_irq_disable() \ -do { \ - unsigned long psr; \ - asm volatile(" movsg psr,%0 \n" \ - " andi %0,%2,%0 \n" \ - " ori %0,%1,%0 \n" \ - " movgs %0,psr \n" \ - : "=r"(psr) \ - : "i" (PSR_PIL_14), "i" (~PSR_PIL) \ - : "memory"); \ -} while(0) - -#define __local_irq_enable() \ -do { \ - unsigned long psr; \ - asm volatile(" movsg psr,%0 \n" \ - " andi %0,%1,%0 \n" \ - " movgs %0,psr \n" \ - : "=r"(psr) \ - : "i" (~PSR_PIL) \ - : "memory"); \ -} while(0) - -#define __local_save_flags(flags) \ -do { \ - typecheck(unsigned long, flags); \ - asm("movsg psr,%0" \ - : "=r"(flags) \ - : \ - : "memory"); \ -} while(0) - -#define __local_irq_save(flags) \ -do { \ - unsigned long npsr; \ - typecheck(unsigned long, flags); \ - asm volatile(" movsg psr,%0 \n" \ - " andi %0,%3,%1 \n" \ - " ori %1,%2,%1 \n" \ - " movgs %1,psr \n" \ - : "=r"(flags), "=r"(npsr) \ - : "i" (PSR_PIL_14), "i" (~PSR_PIL) \ - : "memory"); \ -} while(0) - -#define __local_irq_restore(flags) \ -do { \ - typecheck(unsigned long, flags); \ - asm volatile(" movgs %0,psr \n" \ - : \ - : "r" (flags) \ - : "memory"); \ -} while(0) - -#define __irqs_disabled() \ - ((__get_PSR() & PSR_PIL) >= PSR_PIL_14) - /* * Force strict CPU ordering. */ diff --git a/arch/h8300/include/asm/irqflags.h b/arch/h8300/include/asm/irqflags.h new file mode 100644 index 000000000000..9617cd57aebd --- /dev/null +++ b/arch/h8300/include/asm/irqflags.h @@ -0,0 +1,43 @@ +#ifndef _H8300_IRQFLAGS_H +#define _H8300_IRQFLAGS_H + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile ("stc ccr,%w0" : "=r" (flags)); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile ("orc #0x80,ccr" : : : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile ("andc #0x7f,ccr" : : : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile ("ldc %w0,ccr" : : "r" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & 0x80) == 0x80; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* _H8300_IRQFLAGS_H */ diff --git a/arch/h8300/include/asm/system.h b/arch/h8300/include/asm/system.h index 16bf1560ff68..2c2382e50d93 100644 --- a/arch/h8300/include/asm/system.h +++ b/arch/h8300/include/asm/system.h @@ -2,6 +2,7 @@ #define _H8300_SYSTEM_H #include +#include struct pt_regs; @@ -51,31 +52,8 @@ asmlinkage void resume(void); (last) = _last; \ } -#define __sti() asm volatile ("andc #0x7f,ccr") -#define __cli() asm volatile ("orc #0x80,ccr") - -#define __save_flags(x) \ - asm volatile ("stc ccr,%w0":"=r" (x)) - -#define __restore_flags(x) \ - asm volatile ("ldc %w0,ccr": :"r" (x)) - -#define irqs_disabled() \ -({ \ - unsigned char flags; \ - __save_flags(flags); \ - ((flags & 0x80) == 0x80); \ -}) - #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc") -/* For spinlocks etc */ -#define local_irq_disable() __cli() -#define local_irq_enable() __sti() -#define local_irq_save(x) ({ __save_flags(x); local_irq_disable(); }) -#define local_irq_restore(x) __restore_flags(x) -#define local_save_flags(x) __save_flags(x) - /* * Force strict CPU ordering. * Not really required on H8... diff --git a/arch/ia64/include/asm/irqflags.h b/arch/ia64/include/asm/irqflags.h new file mode 100644 index 000000000000..f82d6be2ecd2 --- /dev/null +++ b/arch/ia64/include/asm/irqflags.h @@ -0,0 +1,94 @@ +/* + * IRQ flags defines. + * + * Copyright (C) 1998-2003 Hewlett-Packard Co + * David Mosberger-Tang + * Copyright (C) 1999 Asit Mallick + * Copyright (C) 1999 Don Dugger + */ + +#ifndef _ASM_IA64_IRQFLAGS_H +#define _ASM_IA64_IRQFLAGS_H + +#ifdef CONFIG_IA64_DEBUG_IRQ +extern unsigned long last_cli_ip; +static inline void arch_maybe_save_ip(unsigned long flags) +{ + if (flags & IA64_PSR_I) + last_cli_ip = ia64_getreg(_IA64_REG_IP); +} +#else +#define arch_maybe_save_ip(flags) do {} while (0) +#endif + +/* + * - clearing psr.i is implicitly serialized (visible by next insn) + * - setting psr.i requires data serialization + * - we need a stop-bit before reading PSR because we sometimes + * write a floating-point register right before reading the PSR + * and that writes to PSR.mfl + */ + +static inline unsigned long arch_local_save_flags(void) +{ + ia64_stop(); +#ifdef CONFIG_PARAVIRT + return ia64_get_psr_i(); +#else + return ia64_getreg(_IA64_REG_PSR); +#endif +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + + ia64_stop(); + ia64_rsm(IA64_PSR_I); + arch_maybe_save_ip(flags); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ +#ifdef CONFIG_IA64_DEBUG_IRQ + arch_local_irq_save(); +#else + ia64_stop(); + ia64_rsm(IA64_PSR_I); +#endif +} + +static inline void arch_local_irq_enable(void) +{ + ia64_stop(); + ia64_ssm(IA64_PSR_I); + ia64_srlz_d(); +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ +#ifdef CONFIG_IA64_DEBUG_IRQ + unsigned long old_psr = arch_local_save_flags(); +#endif + ia64_intrin_local_irq_restore(flags & IA64_PSR_I); + arch_maybe_save_ip(old_psr & ~flags); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & IA64_PSR_I) == 0; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +static inline void arch_safe_halt(void) +{ + ia64_pal_halt_light(); /* PAL_HALT_LIGHT */ +} + + +#endif /* _ASM_IA64_IRQFLAGS_H */ diff --git a/arch/ia64/include/asm/system.h b/arch/ia64/include/asm/system.h index 9f342a574ce8..2feb7f64c035 100644 --- a/arch/ia64/include/asm/system.h +++ b/arch/ia64/include/asm/system.h @@ -107,87 +107,11 @@ extern struct ia64_boot_param { */ #define set_mb(var, value) do { (var) = (value); mb(); } while (0) -#define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */ - /* * The group barrier in front of the rsm & ssm are necessary to ensure * that none of the previous instructions in the same group are * affected by the rsm/ssm. */ -/* For spinlocks etc */ - -/* - * - clearing psr.i is implicitly serialized (visible by next insn) - * - setting psr.i requires data serialization - * - we need a stop-bit before reading PSR because we sometimes - * write a floating-point register right before reading the PSR - * and that writes to PSR.mfl - */ -#ifdef CONFIG_PARAVIRT -#define __local_save_flags() ia64_get_psr_i() -#else -#define __local_save_flags() ia64_getreg(_IA64_REG_PSR) -#endif - -#define __local_irq_save(x) \ -do { \ - ia64_stop(); \ - (x) = __local_save_flags(); \ - ia64_stop(); \ - ia64_rsm(IA64_PSR_I); \ -} while (0) - -#define __local_irq_disable() \ -do { \ - ia64_stop(); \ - ia64_rsm(IA64_PSR_I); \ -} while (0) - -#define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I) - -#ifdef CONFIG_IA64_DEBUG_IRQ - - extern unsigned long last_cli_ip; - -# define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP) - -# define local_irq_save(x) \ -do { \ - unsigned long __psr; \ - \ - __local_irq_save(__psr); \ - if (__psr & IA64_PSR_I) \ - __save_ip(); \ - (x) = __psr; \ -} while (0) - -# define local_irq_disable() do { unsigned long __x; local_irq_save(__x); } while (0) - -# define local_irq_restore(x) \ -do { \ - unsigned long __old_psr, __psr = (x); \ - \ - local_save_flags(__old_psr); \ - __local_irq_restore(__psr); \ - if ((__old_psr & IA64_PSR_I) && !(__psr & IA64_PSR_I)) \ - __save_ip(); \ -} while (0) - -#else /* !CONFIG_IA64_DEBUG_IRQ */ -# define local_irq_save(x) __local_irq_save(x) -# define local_irq_disable() __local_irq_disable() -# define local_irq_restore(x) __local_irq_restore(x) -#endif /* !CONFIG_IA64_DEBUG_IRQ */ - -#define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); }) -#define local_save_flags(flags) ({ ia64_stop(); (flags) = __local_save_flags(); }) - -#define irqs_disabled() \ -({ \ - unsigned long __ia64_id_flags; \ - local_save_flags(__ia64_id_flags); \ - (__ia64_id_flags & IA64_PSR_I) == 0; \ -}) #ifdef __KERNEL__ diff --git a/arch/m32r/include/asm/irqflags.h b/arch/m32r/include/asm/irqflags.h new file mode 100644 index 000000000000..1f92d29982ae --- /dev/null +++ b/arch/m32r/include/asm/irqflags.h @@ -0,0 +1,104 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto + * Copyright (C) 2004, 2006 Hirokazu Takata + */ + +#ifndef _ASM_M32R_IRQFLAGS_H +#define _ASM_M32R_IRQFLAGS_H + +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("mvfc %0,psw" : "=r"(flags)); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ +#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) + asm volatile ( + "clrpsw #0x40 -> nop" + : : : "memory"); +#else + unsigned long tmpreg0, tmpreg1; + asm volatile ( + "ld24 %0, #0 ; Use 32-bit insn. \n\t" + "mvfc %1, psw ; No interrupt can be accepted here. \n\t" + "mvtc %0, psw \n\t" + "and3 %0, %1, #0xffbf \n\t" + "mvtc %0, psw \n\t" + : "=&r" (tmpreg0), "=&r" (tmpreg1) + : + : "cbit", "memory"); +#endif +} + +static inline void arch_local_irq_enable(void) +{ +#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) + asm volatile ( + "setpsw #0x40 -> nop" + : : : "memory"); +#else + unsigned long tmpreg; + asm volatile ( + "mvfc %0, psw; \n\t" + "or3 %0, %0, #0x0040; \n\t" + "mvtc %0, psw; \n\t" + : "=&r" (tmpreg) + : + : "cbit", "memory"); +#endif +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + +#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) + asm volatile ( + "mvfc %0, psw; \n\t" + "clrpsw #0x40 -> nop; \n\t" + : "=r" (flags) + : + : "memory"); +#else + unsigned long tmpreg; + asm volatile ( + "ld24 %1, #0 \n\t" + "mvfc %0, psw \n\t" + "mvtc %1, psw \n\t" + "and3 %1, %0, #0xffbf \n\t" + "mvtc %1, psw \n\t" + : "=r" (flags), "=&r" (tmpreg) + : + : "cbit", "memory"); +#endif + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("mvtc %0,psw" + : + : "r" (flags) + : "cbit", "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return !(flags & 0x40); +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* _ASM_M32R_IRQFLAGS_H */ diff --git a/arch/m32r/include/asm/system.h b/arch/m32r/include/asm/system.h index c980f5ba8de7..13c46794ccb1 100644 --- a/arch/m32r/include/asm/system.h +++ b/arch/m32r/include/asm/system.h @@ -11,6 +11,7 @@ */ #include +#include #include #ifdef __KERNEL__ @@ -54,71 +55,6 @@ ); \ } while(0) -/* Interrupt Control */ -#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) -#define local_irq_enable() \ - __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") -#define local_irq_disable() \ - __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") -#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ -static inline void local_irq_enable(void) -{ - unsigned long tmpreg; - __asm__ __volatile__( - "mvfc %0, psw; \n\t" - "or3 %0, %0, #0x0040; \n\t" - "mvtc %0, psw; \n\t" - : "=&r" (tmpreg) : : "cbit", "memory"); -} - -static inline void local_irq_disable(void) -{ - unsigned long tmpreg0, tmpreg1; - __asm__ __volatile__( - "ld24 %0, #0 ; Use 32-bit insn. \n\t" - "mvfc %1, psw ; No interrupt can be accepted here. \n\t" - "mvtc %0, psw \n\t" - "and3 %0, %1, #0xffbf \n\t" - "mvtc %0, psw \n\t" - : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); -} -#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ - -#define local_save_flags(x) \ - __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) - -#define local_irq_restore(x) \ - __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ - : "r" (x) : "cbit", "memory") - -#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) -#define local_irq_save(x) \ - __asm__ __volatile__( \ - "mvfc %0, psw; \n\t" \ - "clrpsw #0x40 -> nop; \n\t" \ - : "=r" (x) : /* no input */ : "memory") -#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ -#define local_irq_save(x) \ - ({ \ - unsigned long tmpreg; \ - __asm__ __volatile__( \ - "ld24 %1, #0 \n\t" \ - "mvfc %0, psw \n\t" \ - "mvtc %1, psw \n\t" \ - "and3 %1, %0, #0xffbf \n\t" \ - "mvtc %1, psw \n\t" \ - : "=r" (x), "=&r" (tmpreg) \ - : : "cbit", "memory"); \ - }) -#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ - -#define irqs_disabled() \ - ({ \ - unsigned long flags; \ - local_save_flags(flags); \ - !(flags & 0x40); \ - }) - #define nop() __asm__ __volatile__ ("nop" : : ) #define xchg(ptr, x) \ diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h index 907ed03d792f..80e41492aa2a 100644 --- a/arch/m68k/include/asm/entry_no.h +++ b/arch/m68k/include/asm/entry_no.h @@ -28,7 +28,7 @@ * M68K COLDFIRE */ -#define ALLOWINT 0xf8ff +#define ALLOWINT (~0x700) #ifdef __ASSEMBLY__ diff --git a/arch/m68k/include/asm/irqflags.h b/arch/m68k/include/asm/irqflags.h new file mode 100644 index 000000000000..4a5b284a1550 --- /dev/null +++ b/arch/m68k/include/asm/irqflags.h @@ -0,0 +1,76 @@ +#ifndef _M68K_IRQFLAGS_H +#define _M68K_IRQFLAGS_H + +#include +#include +#include +#include +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile ("movew %%sr,%0" : "=d" (flags) : : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ +#ifdef CONFIG_COLDFIRE + asm volatile ( + "move %/sr,%%d0 \n\t" + "ori.l #0x0700,%%d0 \n\t" + "move %%d0,%/sr \n" + : /* no outputs */ + : + : "cc", "%d0", "memory"); +#else + asm volatile ("oriw #0x0700,%%sr" : : : "memory"); +#endif +} + +static inline void arch_local_irq_enable(void) +{ +#if defined(CONFIG_COLDFIRE) + asm volatile ( + "move %/sr,%%d0 \n\t" + "andi.l #0xf8ff,%%d0 \n\t" + "move %%d0,%/sr \n" + : /* no outputs */ + : + : "cc", "%d0", "memory"); +#else +# if defined(CONFIG_MMU) + if (MACH_IS_Q40 || !hardirq_count()) +# endif + asm volatile ( + "andiw %0,%%sr" + : + : "i" (ALLOWINT) + : "memory"); +#endif +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile ("movew %0,%%sr" : : "d" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & ~ALLOWINT) != 0; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* _M68K_IRQFLAGS_H */ diff --git a/arch/m68k/include/asm/system_mm.h b/arch/m68k/include/asm/system_mm.h index dbb6515ffd5b..12053c44cccf 100644 --- a/arch/m68k/include/asm/system_mm.h +++ b/arch/m68k/include/asm/system_mm.h @@ -3,6 +3,7 @@ #include #include +#include #include #include @@ -62,30 +63,6 @@ asmlinkage void resume(void); #define smp_wmb() barrier() #define smp_read_barrier_depends() ((void)0) -/* interrupt control.. */ -#if 0 -#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") -#else -#include -#define local_irq_enable() ({ \ - if (MACH_IS_Q40 || !hardirq_count()) \ - asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \ -}) -#endif -#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory") -#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory") -#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory") - -static inline int irqs_disabled(void) -{ - unsigned long flags; - local_save_flags(flags); - return flags & ~ALLOWINT; -} - -/* For spinlocks etc */ -#define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); }) - #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) struct __xchg_dummy { unsigned long a[100]; }; diff --git a/arch/m68k/include/asm/system_no.h b/arch/m68k/include/asm/system_no.h index 3c0718d74398..20126c09794e 100644 --- a/arch/m68k/include/asm/system_no.h +++ b/arch/m68k/include/asm/system_no.h @@ -2,6 +2,7 @@ #define _M68KNOMMU_SYSTEM_H #include +#include #include #include @@ -46,54 +47,6 @@ asmlinkage void resume(void); (last) = _last; \ } -#ifdef CONFIG_COLDFIRE -#define local_irq_enable() __asm__ __volatile__ ( \ - "move %/sr,%%d0\n\t" \ - "andi.l #0xf8ff,%%d0\n\t" \ - "move %%d0,%/sr\n" \ - : /* no outputs */ \ - : \ - : "cc", "%d0", "memory") -#define local_irq_disable() __asm__ __volatile__ ( \ - "move %/sr,%%d0\n\t" \ - "ori.l #0x0700,%%d0\n\t" \ - "move %%d0,%/sr\n" \ - : /* no outputs */ \ - : \ - : "cc", "%d0", "memory") -/* For spinlocks etc */ -#define local_irq_save(x) __asm__ __volatile__ ( \ - "movew %%sr,%0\n\t" \ - "movew #0x0700,%%d0\n\t" \ - "or.l %0,%%d0\n\t" \ - "movew %%d0,%/sr" \ - : "=d" (x) \ - : \ - : "cc", "%d0", "memory") -#else - -/* portable version */ /* FIXME - see entry.h*/ -#define ALLOWINT 0xf8ff - -#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") -#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory") -#endif - -#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory") -#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory") - -/* For spinlocks etc */ -#ifndef local_irq_save -#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0) -#endif - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - ((flags & 0x0700) == 0x0700); \ -}) - #define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc") /* @@ -206,12 +159,4 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz #define arch_align_stack(x) (x) -static inline int irqs_disabled_flags(unsigned long flags) -{ - if (flags & 0x0700) - return 0; - else - return 1; -} - #endif /* _M68KNOMMU_SYSTEM_H */ diff --git a/arch/m68knommu/kernel/asm-offsets.c b/arch/m68knommu/kernel/asm-offsets.c index 9a8876f715d8..24335022fa2c 100644 --- a/arch/m68knommu/kernel/asm-offsets.c +++ b/arch/m68knommu/kernel/asm-offsets.c @@ -74,8 +74,6 @@ int main(void) DEFINE(PT_PTRACED, PT_PTRACED); - DEFINE(THREAD_SIZE, THREAD_SIZE); - /* Offsets in thread_info structure */ DEFINE(TI_TASK, offsetof(struct thread_info, task)); DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain)); diff --git a/arch/m68knommu/platform/coldfire/head.S b/arch/m68knommu/platform/coldfire/head.S index 4b91aa24eb00..0b2d7c7adf79 100644 --- a/arch/m68knommu/platform/coldfire/head.S +++ b/arch/m68knommu/platform/coldfire/head.S @@ -15,6 +15,7 @@ #include #include #include +#include /*****************************************************************************/ diff --git a/arch/microblaze/include/asm/irqflags.h b/arch/microblaze/include/asm/irqflags.h index 2c38c6d80176..5fd31905775d 100644 --- a/arch/microblaze/include/asm/irqflags.h +++ b/arch/microblaze/include/asm/irqflags.h @@ -9,103 +9,114 @@ #ifndef _ASM_MICROBLAZE_IRQFLAGS_H #define _ASM_MICROBLAZE_IRQFLAGS_H -#include +#include #include -# if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR - -# define raw_local_irq_save(flags) \ - do { \ - asm volatile (" msrclr %0, %1; \ - nop;" \ - : "=r"(flags) \ - : "i"(MSR_IE) \ - : "memory"); \ - } while (0) - -# define raw_local_irq_disable() \ - do { \ - asm volatile (" msrclr r0, %0; \ - nop;" \ - : \ - : "i"(MSR_IE) \ - : "memory"); \ - } while (0) - -# define raw_local_irq_enable() \ - do { \ - asm volatile (" msrset r0, %0; \ - nop;" \ - : \ - : "i"(MSR_IE) \ - : "memory"); \ - } while (0) - -# else /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 0 */ - -# define raw_local_irq_save(flags) \ - do { \ - register unsigned tmp; \ - asm volatile (" mfs %0, rmsr; \ - nop; \ - andi %1, %0, %2; \ - mts rmsr, %1; \ - nop;" \ - : "=r"(flags), "=r" (tmp) \ - : "i"(~MSR_IE) \ - : "memory"); \ - } while (0) - -# define raw_local_irq_disable() \ - do { \ - register unsigned tmp; \ - asm volatile (" mfs %0, rmsr; \ - nop; \ - andi %0, %0, %1; \ - mts rmsr, %0; \ - nop;" \ - : "=r"(tmp) \ - : "i"(~MSR_IE) \ - : "memory"); \ - } while (0) - -# define raw_local_irq_enable() \ - do { \ - register unsigned tmp; \ - asm volatile (" mfs %0, rmsr; \ - nop; \ - ori %0, %0, %1; \ - mts rmsr, %0; \ - nop;" \ - : "=r"(tmp) \ - : "i"(MSR_IE) \ - : "memory"); \ - } while (0) - -# endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ - -#define raw_local_irq_restore(flags) \ - do { \ - asm volatile (" mts rmsr, %0; \ - nop;" \ - : \ - : "r"(flags) \ - : "memory"); \ - } while (0) - -static inline unsigned long get_msr(void) +#ifdef CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + asm volatile(" msrclr %0, %1 \n" + " nop \n" + : "=r"(flags) + : "i"(MSR_IE) + : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + /* this uses r0 without declaring it - is that correct? */ + asm volatile(" msrclr r0, %0 \n" + " nop \n" + : + : "i"(MSR_IE) + : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + /* this uses r0 without declaring it - is that correct? */ + asm volatile(" msrset r0, %0 \n" + " nop \n" + : + : "i"(MSR_IE) + : "memory"); +} + +#else /* !CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags, tmp; + asm volatile (" mfs %0, rmsr \n" + " nop \n" + " andi %1, %0, %2 \n" + " mts rmsr, %1 \n" + " nop \n" + : "=r"(flags), "=r"(tmp) + : "i"(~MSR_IE) + : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + unsigned long tmp; + asm volatile(" mfs %0, rmsr \n" + " nop \n" + " andi %0, %0, %1 \n" + " mts rmsr, %0 \n" + " nop \n" + : "=r"(tmp) + : "i"(~MSR_IE) + : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + unsigned long tmp; + asm volatile(" mfs %0, rmsr \n" + " nop \n" + " ori %0, %0, %1 \n" + " mts rmsr, %0 \n" + " nop \n" + : "=r"(tmp) + : "i"(MSR_IE) + : "memory"); +} + +#endif /* CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR */ + +static inline unsigned long arch_local_save_flags(void) { unsigned long flags; - asm volatile (" mfs %0, rmsr; \ - nop;" \ - : "=r"(flags) \ - : \ - : "memory"); \ + asm volatile(" mfs %0, rmsr \n" + " nop \n" + : "=r"(flags) + : + : "memory"); return flags; } -#define raw_local_save_flags(flags) ((flags) = get_msr()) -#define raw_irqs_disabled() ((get_msr() & MSR_IE) == 0) -#define raw_irqs_disabled_flags(flags) ((flags & MSR_IE) == 0) +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile(" mts rmsr, %0 \n" + " nop \n" + : + : "r"(flags) + : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & MSR_IE) == 0; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} #endif /* _ASM_MICROBLAZE_IRQFLAGS_H */ diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h index 701ec0ba8fa9..9ef3b0d17896 100644 --- a/arch/mips/include/asm/irqflags.h +++ b/arch/mips/include/asm/irqflags.h @@ -17,7 +17,7 @@ #include __asm__( - " .macro raw_local_irq_enable \n" + " .macro arch_local_irq_enable \n" " .set push \n" " .set reorder \n" " .set noat \n" @@ -40,7 +40,7 @@ __asm__( extern void smtc_ipi_replay(void); -static inline void raw_local_irq_enable(void) +static inline void arch_local_irq_enable(void) { #ifdef CONFIG_MIPS_MT_SMTC /* @@ -50,7 +50,7 @@ static inline void raw_local_irq_enable(void) smtc_ipi_replay(); #endif __asm__ __volatile__( - "raw_local_irq_enable" + "arch_local_irq_enable" : /* no outputs */ : /* no inputs */ : "memory"); @@ -76,7 +76,7 @@ static inline void raw_local_irq_enable(void) * Workaround: mask EXL bit of the result or place a nop before mfc0. */ __asm__( - " .macro raw_local_irq_disable\n" + " .macro arch_local_irq_disable\n" " .set push \n" " .set noat \n" #ifdef CONFIG_MIPS_MT_SMTC @@ -97,17 +97,17 @@ __asm__( " .set pop \n" " .endm \n"); -static inline void raw_local_irq_disable(void) +static inline void arch_local_irq_disable(void) { __asm__ __volatile__( - "raw_local_irq_disable" + "arch_local_irq_disable" : /* no outputs */ : /* no inputs */ : "memory"); } __asm__( - " .macro raw_local_save_flags flags \n" + " .macro arch_local_save_flags flags \n" " .set push \n" " .set reorder \n" #ifdef CONFIG_MIPS_MT_SMTC @@ -118,13 +118,15 @@ __asm__( " .set pop \n" " .endm \n"); -#define raw_local_save_flags(x) \ -__asm__ __volatile__( \ - "raw_local_save_flags %0" \ - : "=r" (x)) +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("arch_local_save_flags %0" : "=r" (flags)); + return flags; +} __asm__( - " .macro raw_local_irq_save result \n" + " .macro arch_local_irq_save result \n" " .set push \n" " .set reorder \n" " .set noat \n" @@ -148,15 +150,18 @@ __asm__( " .set pop \n" " .endm \n"); -#define raw_local_irq_save(x) \ -__asm__ __volatile__( \ - "raw_local_irq_save\t%0" \ - : "=r" (x) \ - : /* no inputs */ \ - : "memory") +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + asm volatile("arch_local_irq_save\t%0" + : "=r" (flags) + : /* no inputs */ + : "memory"); + return flags; +} __asm__( - " .macro raw_local_irq_restore flags \n" + " .macro arch_local_irq_restore flags \n" " .set push \n" " .set noreorder \n" " .set noat \n" @@ -196,7 +201,7 @@ __asm__( " .endm \n"); -static inline void raw_local_irq_restore(unsigned long flags) +static inline void arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; @@ -211,24 +216,24 @@ static inline void raw_local_irq_restore(unsigned long flags) #endif __asm__ __volatile__( - "raw_local_irq_restore\t%0" + "arch_local_irq_restore\t%0" : "=r" (__tmp1) : "0" (flags) : "memory"); } -static inline void __raw_local_irq_restore(unsigned long flags) +static inline void __arch_local_irq_restore(unsigned long flags) { unsigned long __tmp1; __asm__ __volatile__( - "raw_local_irq_restore\t%0" + "arch_local_irq_restore\t%0" : "=r" (__tmp1) : "0" (flags) : "memory"); } -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline int arch_irqs_disabled_flags(unsigned long flags) { #ifdef CONFIG_MIPS_MT_SMTC /* diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index cfeb2c155896..39c08254b0f1 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -1038,7 +1038,7 @@ void deferred_smtc_ipi(void) * but it's more efficient, given that we're already * running down the IPI queue. */ - __raw_local_irq_restore(flags); + __arch_local_irq_restore(flags); } } @@ -1190,7 +1190,7 @@ void smtc_ipi_replay(void) /* ** But use a raw restore here to avoid recursion. */ - __raw_local_irq_restore(flags); + __arch_local_irq_restore(flags); if (pipi) { self_ipi(pipi); diff --git a/arch/mn10300/include/asm/irqflags.h b/arch/mn10300/include/asm/irqflags.h new file mode 100644 index 000000000000..5e529a117cb2 --- /dev/null +++ b/arch/mn10300/include/asm/irqflags.h @@ -0,0 +1,123 @@ +/* MN10300 IRQ flag handling + * + * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public Licence + * as published by the Free Software Foundation; either version + * 2 of the Licence, or (at your option) any later version. + */ + +#ifndef _ASM_IRQFLAGS_H +#define _ASM_IRQFLAGS_H + +#include + +/* + * interrupt control + * - "disabled": run in IM1/2 + * - level 0 - GDB stub + * - level 1 - virtual serial DMA (if present) + * - level 5 - normal interrupt priority + * - level 6 - timer interrupt + * - "enabled": run in IM7 + */ +#ifdef CONFIG_MN10300_TTYSM +#define MN10300_CLI_LEVEL EPSW_IM_2 +#else +#define MN10300_CLI_LEVEL EPSW_IM_1 +#endif + +#ifndef __ASSEMBLY__ + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + + asm volatile("mov epsw,%0" : "=d"(flags)); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile( + " and %0,epsw \n" + " or %1,epsw \n" + " nop \n" + " nop \n" + " nop \n" + : + : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL) + : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + + flags = arch_local_save_flags(); + arch_local_irq_disable(); + return flags; +} + +/* + * we make sure arch_irq_enable() doesn't cause priority inversion + */ +extern unsigned long __mn10300_irq_enabled_epsw; + +static inline void arch_local_irq_enable(void) +{ + unsigned long tmp; + + asm volatile( + " mov epsw,%0 \n" + " and %1,%0 \n" + " or %2,%0 \n" + " mov %0,epsw \n" + : "=&d"(tmp) + : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw) + : "memory"); +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile( + " mov %0,epsw \n" + " nop \n" + " nop \n" + " nop \n" + : + : "d"(flags) + : "memory", "cc"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & EPSW_IM) <= MN10300_CLI_LEVEL; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +/* + * Hook to save power by halting the CPU + * - called from the idle loop + * - must reenable interrupts (which takes three instruction cycles to complete) + */ +static inline void arch_safe_halt(void) +{ + asm volatile( + " or %0,epsw \n" + " nop \n" + " nop \n" + " bset %2,(%1) \n" + : + : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP) + : "cc"); +} + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_IRQFLAGS_H */ diff --git a/arch/mn10300/include/asm/system.h b/arch/mn10300/include/asm/system.h index 3636c054dcd5..9f7c7e17c01e 100644 --- a/arch/mn10300/include/asm/system.h +++ b/arch/mn10300/include/asm/system.h @@ -17,6 +17,7 @@ #ifndef __ASSEMBLY__ #include +#include struct task_struct; struct thread_struct; @@ -79,114 +80,6 @@ do { \ #define read_barrier_depends() do {} while (0) #define smp_read_barrier_depends() do {} while (0) -/*****************************************************************************/ -/* - * interrupt control - * - "disabled": run in IM1/2 - * - level 0 - GDB stub - * - level 1 - virtual serial DMA (if present) - * - level 5 - normal interrupt priority - * - level 6 - timer interrupt - * - "enabled": run in IM7 - */ -#ifdef CONFIG_MN10300_TTYSM -#define MN10300_CLI_LEVEL EPSW_IM_2 -#else -#define MN10300_CLI_LEVEL EPSW_IM_1 -#endif - -#define local_save_flags(x) \ -do { \ - typecheck(unsigned long, x); \ - asm volatile( \ - " mov epsw,%0 \n" \ - : "=d"(x) \ - ); \ -} while (0) - -#define local_irq_disable() \ -do { \ - asm volatile( \ - " and %0,epsw \n" \ - " or %1,epsw \n" \ - " nop \n" \ - " nop \n" \ - " nop \n" \ - : \ - : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL) \ - ); \ -} while (0) - -#define local_irq_save(x) \ -do { \ - local_save_flags(x); \ - local_irq_disable(); \ -} while (0) - -/* - * we make sure local_irq_enable() doesn't cause priority inversion - */ -#ifndef __ASSEMBLY__ - -extern unsigned long __mn10300_irq_enabled_epsw; - -#endif - -#define local_irq_enable() \ -do { \ - unsigned long tmp; \ - \ - asm volatile( \ - " mov epsw,%0 \n" \ - " and %1,%0 \n" \ - " or %2,%0 \n" \ - " mov %0,epsw \n" \ - : "=&d"(tmp) \ - : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw) \ - : "cc" \ - ); \ -} while (0) - -#define local_irq_restore(x) \ -do { \ - typecheck(unsigned long, x); \ - asm volatile( \ - " mov %0,epsw \n" \ - " nop \n" \ - " nop \n" \ - " nop \n" \ - : \ - : "d"(x) \ - : "memory", "cc" \ - ); \ -} while (0) - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - (flags & EPSW_IM) <= MN10300_CLI_LEVEL; \ -}) - -/* hook to save power by halting the CPU - * - called from the idle loop - * - must reenable interrupts (which takes three instruction cycles to complete) - */ -#define safe_halt() \ -do { \ - asm volatile(" or %0,epsw \n" \ - " nop \n" \ - " nop \n" \ - " bset %2,(%1) \n" \ - : \ - : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)\ - : "cc" \ - ); \ -} while (0) - -#define STI or EPSW_IE|EPSW_IM,epsw -#define CLI and ~EPSW_IM,epsw; or EPSW_IE|MN10300_CLI_LEVEL,epsw; nop; nop; nop - /*****************************************************************************/ /* * MN10300 doesn't actually have an exchange instruction diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S index d9ed5a15c547..3d394b4eefba 100644 --- a/arch/mn10300/kernel/entry.S +++ b/arch/mn10300/kernel/entry.S @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/parisc/include/asm/irqflags.h b/arch/parisc/include/asm/irqflags.h new file mode 100644 index 000000000000..34f9cb9b4754 --- /dev/null +++ b/arch/parisc/include/asm/irqflags.h @@ -0,0 +1,46 @@ +#ifndef __PARISC_IRQFLAGS_H +#define __PARISC_IRQFLAGS_H + +#include +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("ssm 0, %0" : "=r" (flags) : : "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + asm volatile("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory"); +} + +static inline void arch_local_irq_enable(void) +{ + asm volatile("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory"); +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + asm volatile("rsm %1,%0" : "=r" (flags) : "i" (PSW_I) : "memory"); + return flags; +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("mtsm %0" : : "r" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & PSW_I) == 0; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* __PARISC_IRQFLAGS_H */ diff --git a/arch/parisc/include/asm/system.h b/arch/parisc/include/asm/system.h index 2ab4af58ecb9..b19e63a8e848 100644 --- a/arch/parisc/include/asm/system.h +++ b/arch/parisc/include/asm/system.h @@ -1,7 +1,7 @@ #ifndef __PARISC_SYSTEM_H #define __PARISC_SYSTEM_H -#include +#include /* The program status word as bitfields. */ struct pa_psw { @@ -48,23 +48,6 @@ extern struct task_struct *_switch_to(struct task_struct *, struct task_struct * (last) = _switch_to(prev, next); \ } while(0) -/* interrupt control */ -#define local_save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory") -#define local_irq_disable() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) -#define local_irq_enable() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" ) - -#define local_irq_save(x) \ - __asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" ) -#define local_irq_restore(x) \ - __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" ) - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - (flags & PSW_I) == 0; \ -}) - #define mfctl(reg) ({ \ unsigned long cr; \ __asm__ __volatile__( \ diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index bd100fcf40d0..ff08b70b36d4 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -16,42 +16,57 @@ extern void timer_interrupt(struct pt_regs *); #ifdef CONFIG_PPC64 #include -static inline unsigned long local_get_flags(void) +static inline unsigned long arch_local_save_flags(void) { unsigned long flags; - __asm__ __volatile__("lbz %0,%1(13)" - : "=r" (flags) - : "i" (offsetof(struct paca_struct, soft_enabled))); + asm volatile( + "lbz %0,%1(13)" + : "=r" (flags) + : "i" (offsetof(struct paca_struct, soft_enabled))); return flags; } -static inline unsigned long raw_local_irq_disable(void) +static inline unsigned long arch_local_irq_disable(void) { unsigned long flags, zero; - __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)" - : "=r" (flags), "=&r" (zero) - : "i" (offsetof(struct paca_struct, soft_enabled)) - : "memory"); + asm volatile( + "li %1,0; lbz %0,%2(13); stb %1,%2(13)" + : "=r" (flags), "=&r" (zero) + : "i" (offsetof(struct paca_struct, soft_enabled)) + : "memory"); return flags; } -extern void raw_local_irq_restore(unsigned long); +extern void arch_local_irq_restore(unsigned long); extern void iseries_handle_interrupts(void); -#define raw_local_irq_enable() raw_local_irq_restore(1) -#define raw_local_save_flags(flags) ((flags) = local_get_flags()) -#define raw_local_irq_save(flags) ((flags) = raw_local_irq_disable()) +static inline void arch_local_irq_enable(void) +{ + arch_local_irq_restore(1); +} + +static inline unsigned long arch_local_irq_save(void) +{ + return arch_local_irq_disable(); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return flags == 0; +} -#define raw_irqs_disabled() (local_get_flags() == 0) -#define raw_irqs_disabled_flags(flags) ((flags) == 0) +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} #ifdef CONFIG_PPC_BOOK3E -#define __hard_irq_enable() __asm__ __volatile__("wrteei 1": : :"memory"); -#define __hard_irq_disable() __asm__ __volatile__("wrteei 0": : :"memory"); +#define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory"); +#define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory"); #else #define __hard_irq_enable() __mtmsrd(mfmsr() | MSR_EE, 1) #define __hard_irq_disable() __mtmsrd(mfmsr() & ~MSR_EE, 1) @@ -64,64 +79,66 @@ extern void iseries_handle_interrupts(void); get_paca()->hard_enabled = 0; \ } while(0) -#else +#else /* CONFIG_PPC64 */ -#if defined(CONFIG_BOOKE) #define SET_MSR_EE(x) mtmsr(x) -#define raw_local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory") + +static inline unsigned long arch_local_save_flags(void) +{ + return mfmsr(); +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ +#if defined(CONFIG_BOOKE) + asm volatile("wrtee %0" : : "r" (flags) : "memory"); #else -#define SET_MSR_EE(x) mtmsr(x) -#define raw_local_irq_restore(flags) mtmsr(flags) + mtmsr(flags); #endif +} -static inline void raw_local_irq_disable(void) +static inline unsigned long arch_local_irq_save(void) { + unsigned long flags = arch_local_save_flags(); #ifdef CONFIG_BOOKE - __asm__ __volatile__("wrteei 0": : :"memory"); + asm volatile("wrteei 0" : : : "memory"); #else - unsigned long msr; - - msr = mfmsr(); - SET_MSR_EE(msr & ~MSR_EE); + SET_MSR_EE(flags & ~MSR_EE); #endif + return flags; } -static inline void raw_local_irq_enable(void) +static inline void arch_local_irq_disable(void) { #ifdef CONFIG_BOOKE - __asm__ __volatile__("wrteei 1": : :"memory"); + asm volatile("wrteei 0" : : : "memory"); #else - unsigned long msr; - - msr = mfmsr(); - SET_MSR_EE(msr | MSR_EE); + arch_local_irq_save(); #endif } -static inline void raw_local_irq_save_ptr(unsigned long *flags) +static inline void arch_local_irq_enable(void) { - unsigned long msr; - msr = mfmsr(); - *flags = msr; #ifdef CONFIG_BOOKE - __asm__ __volatile__("wrteei 0": : :"memory"); + asm volatile("wrteei 1" : : : "memory"); #else - SET_MSR_EE(msr & ~MSR_EE); + unsigned long msr = mfmsr(); + SET_MSR_EE(msr | MSR_EE); #endif } -#define raw_local_save_flags(flags) ((flags) = mfmsr()) -#define raw_local_irq_save(flags) raw_local_irq_save_ptr(&flags) -#define raw_irqs_disabled() ((mfmsr() & MSR_EE) == 0) -#define raw_irqs_disabled_flags(flags) (((flags) & MSR_EE) == 0) - -#define hard_irq_disable() raw_local_irq_disable() - -static inline int irqs_disabled_flags(unsigned long flags) +static inline bool arch_irqs_disabled_flags(unsigned long flags) { return (flags & MSR_EE) == 0; } +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#define hard_irq_disable() arch_local_irq_disable() + #endif /* CONFIG_PPC64 */ /* diff --git a/arch/powerpc/include/asm/irqflags.h b/arch/powerpc/include/asm/irqflags.h index 5f68ecfdf516..b85d8ddbb666 100644 --- a/arch/powerpc/include/asm/irqflags.h +++ b/arch/powerpc/include/asm/irqflags.h @@ -6,7 +6,7 @@ #ifndef __ASSEMBLY__ /* - * Get definitions for raw_local_save_flags(x), etc. + * Get definitions for arch_local_save_flags(x), etc. */ #include diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index f53029a01554..39b0c48872d2 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -818,12 +818,12 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) /* * hash_page couldn't handle it, set soft interrupt enable back - * to what it was before the trap. Note that .raw_local_irq_restore + * to what it was before the trap. Note that .arch_local_irq_restore * handles any interrupts pending at this point. */ ld r3,SOFTE(r1) TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f) - bl .raw_local_irq_restore + bl .arch_local_irq_restore b 11f /* We have a data breakpoint exception - handle it */ diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 4a65386995d7..1903290f5469 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c @@ -116,7 +116,7 @@ static inline notrace void set_soft_enabled(unsigned long enable) : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled))); } -notrace void raw_local_irq_restore(unsigned long en) +notrace void arch_local_irq_restore(unsigned long en) { /* * get_paca()->soft_enabled = en; @@ -192,7 +192,7 @@ notrace void raw_local_irq_restore(unsigned long en) __hard_irq_enable(); } -EXPORT_SYMBOL(raw_local_irq_restore); +EXPORT_SYMBOL(arch_local_irq_restore); #endif /* CONFIG_PPC64 */ static int show_other_interrupts(struct seq_file *p, int prec) diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h index 15b3ac253898..865d6d891ace 100644 --- a/arch/s390/include/asm/irqflags.h +++ b/arch/s390/include/asm/irqflags.h @@ -8,8 +8,8 @@ #include -/* store then or system mask. */ -#define __raw_local_irq_stosm(__or) \ +/* store then OR system mask. */ +#define __arch_local_irq_stosm(__or) \ ({ \ unsigned long __mask; \ asm volatile( \ @@ -18,8 +18,8 @@ __mask; \ }) -/* store then and system mask. */ -#define __raw_local_irq_stnsm(__and) \ +/* store then AND system mask. */ +#define __arch_local_irq_stnsm(__and) \ ({ \ unsigned long __mask; \ asm volatile( \ @@ -29,39 +29,44 @@ }) /* set system mask. */ -#define __raw_local_irq_ssm(__mask) \ -({ \ - asm volatile("ssm %0" : : "Q" (__mask) : "memory"); \ -}) +static inline void __arch_local_irq_ssm(unsigned long flags) +{ + asm volatile("ssm %0" : : "Q" (flags) : "memory"); +} -/* interrupt control.. */ -static inline unsigned long raw_local_irq_enable(void) +static inline unsigned long arch_local_save_flags(void) { - return __raw_local_irq_stosm(0x03); + return __arch_local_irq_stosm(0x00); } -static inline unsigned long raw_local_irq_disable(void) +static inline unsigned long arch_local_irq_save(void) { - return __raw_local_irq_stnsm(0xfc); + return __arch_local_irq_stnsm(0xfc); } -#define raw_local_save_flags(x) \ -do { \ - typecheck(unsigned long, x); \ - (x) = __raw_local_irq_stosm(0x00); \ -} while (0) +static inline void arch_local_irq_disable(void) +{ + arch_local_irq_save(); +} -static inline void raw_local_irq_restore(unsigned long flags) +static inline void arch_local_irq_enable(void) { - __raw_local_irq_ssm(flags); + __arch_local_irq_stosm(0x03); } -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline void arch_local_irq_restore(unsigned long flags) +{ + __arch_local_irq_ssm(flags); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) { return !(flags & (3UL << (BITS_PER_LONG - 8))); } -/* For spinlocks etc */ -#define raw_local_irq_save(x) ((x) = raw_local_irq_disable()) +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} #endif /* __ASM_IRQFLAGS_H */ diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h index cef66210c846..8e8a50eeed92 100644 --- a/arch/s390/include/asm/system.h +++ b/arch/s390/include/asm/system.h @@ -399,7 +399,7 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr, static inline void __set_psw_mask(unsigned long mask) { - __load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8))); + __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8))); } #define local_mcck_enable() __set_psw_mask(psw_kernel_bits) diff --git a/arch/s390/kernel/mem_detect.c b/arch/s390/kernel/mem_detect.c index 559af0d07878..0fbe4e32f7ba 100644 --- a/arch/s390/kernel/mem_detect.c +++ b/arch/s390/kernel/mem_detect.c @@ -54,11 +54,11 @@ void detect_memory_layout(struct mem_chunk chunk[]) * right thing and we don't get scheduled away with low address * protection disabled. */ - flags = __raw_local_irq_stnsm(0xf8); + flags = __arch_local_irq_stnsm(0xf8); __ctl_store(cr0, 0, 0); __ctl_clear_bit(0, 28); find_memory_chunks(chunk); __ctl_load(cr0, 0, 0); - __raw_local_irq_ssm(flags); + arch_local_irq_restore(flags); } EXPORT_SYMBOL(detect_memory_layout); diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c index 30eb6d02ddb8..94b8ba2ec857 100644 --- a/arch/s390/mm/init.c +++ b/arch/s390/mm/init.c @@ -50,7 +50,6 @@ EXPORT_SYMBOL(empty_zero_page); */ void __init paging_init(void) { - static const int ssm_mask = 0x04000000L; unsigned long max_zone_pfns[MAX_NR_ZONES]; unsigned long pgd_type; @@ -72,7 +71,7 @@ void __init paging_init(void) __ctl_load(S390_lowcore.kernel_asce, 1, 1); __ctl_load(S390_lowcore.kernel_asce, 7, 7); __ctl_load(S390_lowcore.kernel_asce, 13, 13); - __raw_local_irq_ssm(ssm_mask); + arch_local_irq_restore(4UL << (BITS_PER_LONG - 8)); atomic_set(&init_mm.context.attach_count, 1); diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index a8c2af8c650f..71a4b0d34be0 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -71,7 +71,7 @@ int memcpy_real(void *dest, void *src, size_t count) if (!count) return 0; - flags = __raw_local_irq_stnsm(0xf8UL); + flags = __arch_local_irq_stnsm(0xf8UL); asm volatile ( "0: mvcle %1,%2,0x0\n" "1: jo 0b\n" @@ -82,6 +82,6 @@ int memcpy_real(void *dest, void *src, size_t count) "+d" (_len2), "=m" (*((long *) dest)) : "m" (*((long *) src)) : "cc", "memory"); - __raw_local_irq_ssm(flags); + arch_local_irq_restore(flags); return rc; } diff --git a/arch/score/include/asm/irqflags.h b/arch/score/include/asm/irqflags.h index 690a6cae7294..5c7563891e28 100644 --- a/arch/score/include/asm/irqflags.h +++ b/arch/score/include/asm/irqflags.h @@ -3,107 +3,118 @@ #ifndef __ASSEMBLY__ -#define raw_local_irq_save(x) \ -{ \ - __asm__ __volatile__( \ - "mfcr r8, cr0;" \ - "li r9, 0xfffffffe;" \ - "nop;" \ - "mv %0, r8;" \ - "and r8, r8, r9;" \ - "mtcr r8, cr0;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - : "=r" (x) \ - : \ - : "r8", "r9" \ - ); \ +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + + asm volatile( + " mfcr r8, cr0 \n" + " nop \n" + " nop \n" + " mv %0, r8 \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " ldi r9, 0x1 \n" + " and %0, %0, r9 \n" + : "=r" (flags) + : + : "r8", "r9"); + return flags; } -#define raw_local_irq_restore(x) \ -{ \ - __asm__ __volatile__( \ - "mfcr r8, cr0;" \ - "ldi r9, 0x1;" \ - "and %0, %0, r9;" \ - "or r8, r8, %0;" \ - "mtcr r8, cr0;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - : \ - : "r"(x) \ - : "r8", "r9" \ - ); \ +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags + + asm volatile( + " mfcr r8, cr0 \n" + " li r9, 0xfffffffe \n" + " nop \n" + " mv %0, r8 \n" + " and r8, r8, r9 \n" + " mtcr r8, cr0 \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + : "=r" (flags) + : + : "r8", "r9", "memory"); + + return flags; } -#define raw_local_irq_enable(void) \ -{ \ - __asm__ __volatile__( \ - "mfcr\tr8,cr0;" \ - "nop;" \ - "nop;" \ - "ori\tr8,0x1;" \ - "mtcr\tr8,cr0;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - : \ - : \ - : "r8"); \ +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile( + " mfcr r8, cr0 \n" + " ldi r9, 0x1 \n" + " and %0, %0, r9 \n" + " or r8, r8, %0 \n" + " mtcr r8, cr0 \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + : + : "r"(flags) + : "r8", "r9", "memory"); } -#define raw_local_irq_disable(void) \ -{ \ - __asm__ __volatile__( \ - "mfcr\tr8,cr0;" \ - "nop;" \ - "nop;" \ - "srli\tr8,r8,1;" \ - "slli\tr8,r8,1;" \ - "mtcr\tr8,cr0;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - : \ - : \ - : "r8"); \ +static inline void arch_local_irq_enable(void) +{ + asm volatile( + " mfcr r8,cr0 \n" + " nop \n" + " nop \n" + " ori r8,0x1 \n" + " mtcr r8,cr0 \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + : + : + : "r8", "memory"); } -#define raw_local_save_flags(x) \ -{ \ - __asm__ __volatile__( \ - "mfcr r8, cr0;" \ - "nop;" \ - "nop;" \ - "mv %0, r8;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "nop;" \ - "ldi r9, 0x1;" \ - "and %0, %0, r9;" \ - : "=r" (x) \ - : \ - : "r8", "r9" \ - ); \ +static inline void arch_local_irq_disable(void) +{ + asm volatile( + " mfcr r8,cr0 \n" + " nop \n" + " nop \n" + " srli r8,r8,1 \n" + " slli r8,r8,1 \n" + " mtcr r8,cr0 \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + : + : + : "r8", "memory"); } -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline bool arch_irqs_disabled_flags(unsigned long flags) { return !(flags & 1); } -#endif +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* __ASSEMBLY__ */ #endif /* _ASM_SCORE_IRQFLAGS_H */ diff --git a/arch/sh/include/asm/irqflags.h b/arch/sh/include/asm/irqflags.h index a741153b41c2..43b7608606c3 100644 --- a/arch/sh/include/asm/irqflags.h +++ b/arch/sh/include/asm/irqflags.h @@ -1,8 +1,8 @@ #ifndef __ASM_SH_IRQFLAGS_H #define __ASM_SH_IRQFLAGS_H -#define RAW_IRQ_DISABLED 0xf0 -#define RAW_IRQ_ENABLED 0x00 +#define ARCH_IRQ_DISABLED 0xf0 +#define ARCH_IRQ_ENABLED 0x00 #include diff --git a/arch/sh/kernel/irq_32.c b/arch/sh/kernel/irq_32.c index e33ab15831f9..e5a755be9129 100644 --- a/arch/sh/kernel/irq_32.c +++ b/arch/sh/kernel/irq_32.c @@ -10,11 +10,11 @@ #include #include -void notrace raw_local_irq_restore(unsigned long flags) +void notrace arch_local_irq_restore(unsigned long flags) { unsigned long __dummy0, __dummy1; - if (flags == RAW_IRQ_DISABLED) { + if (flags == ARCH_IRQ_DISABLED) { __asm__ __volatile__ ( "stc sr, %0\n\t" "or #0xf0, %0\n\t" @@ -33,14 +33,14 @@ void notrace raw_local_irq_restore(unsigned long flags) #endif "ldc %0, sr\n\t" : "=&r" (__dummy0), "=r" (__dummy1) - : "1" (~RAW_IRQ_DISABLED) + : "1" (~ARCH_IRQ_DISABLED) : "memory" ); } } -EXPORT_SYMBOL(raw_local_irq_restore); +EXPORT_SYMBOL(arch_local_irq_restore); -unsigned long notrace __raw_local_save_flags(void) +unsigned long notrace arch_local_save_flags(void) { unsigned long flags; @@ -54,4 +54,4 @@ unsigned long notrace __raw_local_save_flags(void) return flags; } -EXPORT_SYMBOL(__raw_local_save_flags); +EXPORT_SYMBOL(arch_local_save_flags); diff --git a/arch/sparc/include/asm/irqflags_32.h b/arch/sparc/include/asm/irqflags_32.h index 0fca9d97d44f..d4d0711de0f9 100644 --- a/arch/sparc/include/asm/irqflags_32.h +++ b/arch/sparc/include/asm/irqflags_32.h @@ -5,33 +5,40 @@ * * This file gets included from lowlevel asm headers too, to provide * wrapped versions of the local_irq_*() APIs, based on the - * raw_local_irq_*() functions from the lowlevel headers. + * arch_local_irq_*() functions from the lowlevel headers. */ #ifndef _ASM_IRQFLAGS_H #define _ASM_IRQFLAGS_H #ifndef __ASSEMBLY__ -extern void raw_local_irq_restore(unsigned long); -extern unsigned long __raw_local_irq_save(void); -extern void raw_local_irq_enable(void); +#include -static inline unsigned long getipl(void) +extern void arch_local_irq_restore(unsigned long); +extern unsigned long arch_local_irq_save(void); +extern void arch_local_irq_enable(void); + +static inline unsigned long arch_local_save_flags(void) { - unsigned long retval; + unsigned long flags; + + asm volatile("rd %%psr, %0" : "=r" (flags)); + return flags; +} - __asm__ __volatile__("rd %%psr, %0" : "=r" (retval)); - return retval; +static inline void arch_local_irq_disable(void) +{ + arch_local_irq_save(); } -#define raw_local_save_flags(flags) ((flags) = getipl()) -#define raw_local_irq_save(flags) ((flags) = __raw_local_irq_save()) -#define raw_local_irq_disable() ((void) __raw_local_irq_save()) -#define raw_irqs_disabled() ((getipl() & PSR_PIL) != 0) +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & PSR_PIL) != 0; +} -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline bool arch_irqs_disabled(void) { - return ((flags & PSR_PIL) != 0); + return arch_irqs_disabled_flags(arch_local_save_flags()); } #endif /* (__ASSEMBLY__) */ diff --git a/arch/sparc/include/asm/irqflags_64.h b/arch/sparc/include/asm/irqflags_64.h index bfa1ea45b4cd..aab969c82c2b 100644 --- a/arch/sparc/include/asm/irqflags_64.h +++ b/arch/sparc/include/asm/irqflags_64.h @@ -5,7 +5,7 @@ * * This file gets included from lowlevel asm headers too, to provide * wrapped versions of the local_irq_*() APIs, based on the - * raw_local_irq_*() functions from the lowlevel headers. + * arch_local_irq_*() functions from the lowlevel headers. */ #ifndef _ASM_IRQFLAGS_H #define _ASM_IRQFLAGS_H @@ -14,7 +14,7 @@ #ifndef __ASSEMBLY__ -static inline unsigned long __raw_local_save_flags(void) +static inline unsigned long arch_local_save_flags(void) { unsigned long flags; @@ -26,10 +26,7 @@ static inline unsigned long __raw_local_save_flags(void) return flags; } -#define raw_local_save_flags(flags) \ - do { (flags) = __raw_local_save_flags(); } while (0) - -static inline void raw_local_irq_restore(unsigned long flags) +static inline void arch_local_irq_restore(unsigned long flags) { __asm__ __volatile__( "wrpr %0, %%pil" @@ -39,7 +36,7 @@ static inline void raw_local_irq_restore(unsigned long flags) ); } -static inline void raw_local_irq_disable(void) +static inline void arch_local_irq_disable(void) { __asm__ __volatile__( "wrpr %0, %%pil" @@ -49,7 +46,7 @@ static inline void raw_local_irq_disable(void) ); } -static inline void raw_local_irq_enable(void) +static inline void arch_local_irq_enable(void) { __asm__ __volatile__( "wrpr 0, %%pil" @@ -59,22 +56,17 @@ static inline void raw_local_irq_enable(void) ); } -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline int arch_irqs_disabled_flags(unsigned long flags) { return (flags > 0); } -static inline int raw_irqs_disabled(void) +static inline int arch_irqs_disabled(void) { - unsigned long flags = __raw_local_save_flags(); - - return raw_irqs_disabled_flags(flags); + return arch_irqs_disabled_flags(arch_local_save_flags()); } -/* - * For spinlocks, etc: - */ -static inline unsigned long __raw_local_irq_save(void) +static inline unsigned long arch_local_irq_save(void) { unsigned long flags, tmp; @@ -100,9 +92,6 @@ static inline unsigned long __raw_local_irq_save(void) return flags; } -#define raw_local_irq_save(flags) \ - do { (flags) = __raw_local_irq_save(); } while (0) - #endif /* (__ASSEMBLY__) */ #endif /* !(_ASM_IRQFLAGS_H) */ diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c index e1af43728329..0116d8d10def 100644 --- a/arch/sparc/kernel/irq_32.c +++ b/arch/sparc/kernel/irq_32.c @@ -57,7 +57,7 @@ #define SMP_NOP2 #define SMP_NOP3 #endif /* SMP */ -unsigned long __raw_local_irq_save(void) +unsigned long arch_local_irq_save(void) { unsigned long retval; unsigned long tmp; @@ -74,8 +74,9 @@ unsigned long __raw_local_irq_save(void) return retval; } +EXPORT_SYMBOL(arch_local_irq_save); -void raw_local_irq_enable(void) +void arch_local_irq_enable(void) { unsigned long tmp; @@ -89,8 +90,9 @@ void raw_local_irq_enable(void) : "i" (PSR_PIL) : "memory"); } +EXPORT_SYMBOL(arch_local_irq_enable); -void raw_local_irq_restore(unsigned long old_psr) +void arch_local_irq_restore(unsigned long old_psr) { unsigned long tmp; @@ -105,10 +107,7 @@ void raw_local_irq_restore(unsigned long old_psr) : "i" (PSR_PIL), "r" (old_psr) : "memory"); } - -EXPORT_SYMBOL(__raw_local_irq_save); -EXPORT_SYMBOL(raw_local_irq_enable); -EXPORT_SYMBOL(raw_local_irq_restore); +EXPORT_SYMBOL(arch_local_irq_restore); /* * Dave Redman (djhr@tadpole.co.uk) diff --git a/arch/sparc/prom/p1275.c b/arch/sparc/prom/p1275.c index fa6e4e219b9c..d9850c2b9bf2 100644 --- a/arch/sparc/prom/p1275.c +++ b/arch/sparc/prom/p1275.c @@ -39,7 +39,7 @@ void p1275_cmd_direct(unsigned long *args) unsigned long flags; raw_local_save_flags(flags); - raw_local_irq_restore(PIL_NMI); + raw_local_irq_restore((unsigned long)PIL_NMI); raw_spin_lock(&prom_entry_lock); prom_world(1); diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h index 45cf67c2f286..a11d4837ee4d 100644 --- a/arch/tile/include/asm/irqflags.h +++ b/arch/tile/include/asm/irqflags.h @@ -103,55 +103,57 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask); #define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR) /* Disable interrupts. */ -#define raw_local_irq_disable() \ +#define arch_local_irq_disable() \ interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS) /* Disable all interrupts, including NMIs. */ -#define raw_local_irq_disable_all() \ +#define arch_local_irq_disable_all() \ interrupt_mask_set_mask(-1UL) /* Re-enable all maskable interrupts. */ -#define raw_local_irq_enable() \ +#define arch_local_irq_enable() \ interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask)) /* Disable or enable interrupts based on flag argument. */ -#define raw_local_irq_restore(disabled) do { \ +#define arch_local_irq_restore(disabled) do { \ if (disabled) \ - raw_local_irq_disable(); \ + arch_local_irq_disable(); \ else \ - raw_local_irq_enable(); \ + arch_local_irq_enable(); \ } while (0) /* Return true if "flags" argument means interrupts are disabled. */ -#define raw_irqs_disabled_flags(flags) ((flags) != 0) +#define arch_irqs_disabled_flags(flags) ((flags) != 0) /* Return true if interrupts are currently disabled. */ -#define raw_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR) +#define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR) /* Save whether interrupts are currently disabled. */ -#define raw_local_save_flags(flags) ((flags) = raw_irqs_disabled()) +#define arch_local_save_flags() arch_irqs_disabled() /* Save whether interrupts are currently disabled, then disable them. */ -#define raw_local_irq_save(flags) \ - do { raw_local_save_flags(flags); raw_local_irq_disable(); } while (0) +#define arch_local_irq_save() ({ \ + unsigned long __flags = arch_local_save_flags(); \ + arch_local_irq_disable(); \ + __flags; }) /* Prevent the given interrupt from being enabled next time we enable irqs. */ -#define raw_local_irq_mask(interrupt) \ +#define arch_local_irq_mask(interrupt) \ (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt)) /* Prevent the given interrupt from being enabled immediately. */ -#define raw_local_irq_mask_now(interrupt) do { \ - raw_local_irq_mask(interrupt); \ +#define arch_local_irq_mask_now(interrupt) do { \ + arch_local_irq_mask(interrupt); \ interrupt_mask_set(interrupt); \ } while (0) /* Allow the given interrupt to be enabled next time we enable irqs. */ -#define raw_local_irq_unmask(interrupt) \ +#define arch_local_irq_unmask(interrupt) \ (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt)) /* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */ -#define raw_local_irq_unmask_now(interrupt) do { \ - raw_local_irq_unmask(interrupt); \ +#define arch_local_irq_unmask_now(interrupt) do { \ + arch_local_irq_unmask(interrupt); \ if (!irqs_disabled()) \ interrupt_mask_reset(interrupt); \ } while (0) diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h index 9e2b952f810a..5745ce8bf108 100644 --- a/arch/x86/include/asm/irqflags.h +++ b/arch/x86/include/asm/irqflags.h @@ -61,22 +61,22 @@ static inline void native_halt(void) #else #ifndef __ASSEMBLY__ -static inline unsigned long __raw_local_save_flags(void) +static inline unsigned long arch_local_save_flags(void) { return native_save_fl(); } -static inline void raw_local_irq_restore(unsigned long flags) +static inline void arch_local_irq_restore(unsigned long flags) { native_restore_fl(flags); } -static inline void raw_local_irq_disable(void) +static inline void arch_local_irq_disable(void) { native_irq_disable(); } -static inline void raw_local_irq_enable(void) +static inline void arch_local_irq_enable(void) { native_irq_enable(); } @@ -85,7 +85,7 @@ static inline void raw_local_irq_enable(void) * Used in the idle loop; sti takes one instruction cycle * to complete: */ -static inline void raw_safe_halt(void) +static inline void arch_safe_halt(void) { native_safe_halt(); } @@ -102,12 +102,10 @@ static inline void halt(void) /* * For spinlocks, etc: */ -static inline unsigned long __raw_local_irq_save(void) +static inline unsigned long arch_local_irq_save(void) { - unsigned long flags = __raw_local_save_flags(); - - raw_local_irq_disable(); - + unsigned long flags = arch_local_save_flags(); + arch_local_irq_disable(); return flags; } #else @@ -153,22 +151,16 @@ static inline unsigned long __raw_local_irq_save(void) #endif /* CONFIG_PARAVIRT */ #ifndef __ASSEMBLY__ -#define raw_local_save_flags(flags) \ - do { (flags) = __raw_local_save_flags(); } while (0) - -#define raw_local_irq_save(flags) \ - do { (flags) = __raw_local_irq_save(); } while (0) - -static inline int raw_irqs_disabled_flags(unsigned long flags) +static inline int arch_irqs_disabled_flags(unsigned long flags) { return !(flags & X86_EFLAGS_IF); } -static inline int raw_irqs_disabled(void) +static inline int arch_irqs_disabled(void) { - unsigned long flags = __raw_local_save_flags(); + unsigned long flags = arch_local_save_flags(); - return raw_irqs_disabled_flags(flags); + return arch_irqs_disabled_flags(flags); } #else diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 5653f43d90e5..499954c530da 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -105,7 +105,7 @@ static inline void write_cr8(unsigned long x) } #endif -static inline void raw_safe_halt(void) +static inline void arch_safe_halt(void) { PVOP_VCALL0(pv_irq_ops.safe_halt); } @@ -829,32 +829,32 @@ static __always_inline void arch_spin_unlock(struct arch_spinlock *lock) #define __PV_IS_CALLEE_SAVE(func) \ ((struct paravirt_callee_save) { func }) -static inline unsigned long __raw_local_save_flags(void) +static inline unsigned long arch_local_save_flags(void) { return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl); } -static inline void raw_local_irq_restore(unsigned long f) +static inline void arch_local_irq_restore(unsigned long f) { PVOP_VCALLEE1(pv_irq_ops.restore_fl, f); } -static inline void raw_local_irq_disable(void) +static inline void arch_local_irq_disable(void) { PVOP_VCALLEE0(pv_irq_ops.irq_disable); } -static inline void raw_local_irq_enable(void) +static inline void arch_local_irq_enable(void) { PVOP_VCALLEE0(pv_irq_ops.irq_enable); } -static inline unsigned long __raw_local_irq_save(void) +static inline unsigned long arch_local_irq_save(void) { unsigned long f; - f = __raw_local_save_flags(); - raw_local_irq_disable(); + f = arch_local_save_flags(); + arch_local_irq_disable(); return f; } diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c index e0500646585d..23e061b9327b 100644 --- a/arch/x86/xen/spinlock.c +++ b/arch/x86/xen/spinlock.c @@ -224,7 +224,7 @@ static noinline int xen_spin_lock_slow(struct arch_spinlock *lock, bool irq_enab goto out; } - flags = __raw_local_save_flags(); + flags = arch_local_save_flags(); if (irq_enable) { ADD_STATS(taken_slow_irqenable, 1); raw_local_irq_enable(); diff --git a/arch/xtensa/include/asm/irqflags.h b/arch/xtensa/include/asm/irqflags.h new file mode 100644 index 000000000000..dae9a8bdcb17 --- /dev/null +++ b/arch/xtensa/include/asm/irqflags.h @@ -0,0 +1,58 @@ +/* + * Xtensa IRQ flags handling functions + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 - 2005 Tensilica Inc. + */ + +#ifndef _XTENSA_IRQFLAGS_H +#define _XTENSA_IRQFLAGS_H + +#include + +static inline unsigned long arch_local_save_flags(void) +{ + unsigned long flags; + asm volatile("rsr %0,"__stringify(PS) : "=a" (flags)); + return flags; +} + +static inline unsigned long arch_local_irq_save(void) +{ + unsigned long flags; + asm volatile("rsil %0, "__stringify(LOCKLEVEL) + : "=a" (flags) :: "memory"); + return flags; +} + +static inline void arch_local_irq_disable(void) +{ + arch_local_irq_save(); +} + +static inline void arch_local_irq_enable(void) +{ + unsigned long flags; + asm volatile("rsil %0, 0" : "=a" (flags) :: "memory"); +} + +static inline void arch_local_irq_restore(unsigned long flags) +{ + asm volatile("wsr %0, "__stringify(PS)" ; rsync" + :: "a" (flags) : "memory"); +} + +static inline bool arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags & 0xf) != 0; +} + +static inline bool arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +#endif /* _XTENSA_IRQFLAGS_H */ diff --git a/arch/xtensa/include/asm/system.h b/arch/xtensa/include/asm/system.h index 62b1e8f3c13c..1e7e09ab6cd7 100644 --- a/arch/xtensa/include/asm/system.h +++ b/arch/xtensa/include/asm/system.h @@ -12,41 +12,10 @@ #define _XTENSA_SYSTEM_H #include +#include #include -/* interrupt control */ - -#define local_save_flags(x) \ - __asm__ __volatile__ ("rsr %0,"__stringify(PS) : "=a" (x)); -#define local_irq_restore(x) do { \ - __asm__ __volatile__ ("wsr %0, "__stringify(PS)" ; rsync" \ - :: "a" (x) : "memory"); } while(0); -#define local_irq_save(x) do { \ - __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL) \ - : "=a" (x) :: "memory");} while(0); - -static inline void local_irq_disable(void) -{ - unsigned long flags; - __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL) - : "=a" (flags) :: "memory"); -} -static inline void local_irq_enable(void) -{ - unsigned long flags; - __asm__ __volatile__ ("rsil %0, 0" : "=a" (flags) :: "memory"); - -} - -static inline int irqs_disabled(void) -{ - unsigned long flags; - local_save_flags(flags); - return flags & 0xf; -} - - #define smp_read_barrier_depends() do { } while(0) #define read_barrier_depends() do { } while(0) diff --git a/drivers/s390/char/sclp.c b/drivers/s390/char/sclp.c index f6d72e1f2a38..5707a80b96b6 100644 --- a/drivers/s390/char/sclp.c +++ b/drivers/s390/char/sclp.c @@ -468,7 +468,7 @@ sclp_sync_wait(void) cr0_sync &= 0xffff00a0; cr0_sync |= 0x00000200; __ctl_load(cr0_sync, 0, 0); - __raw_local_irq_stosm(0x01); + __arch_local_irq_stosm(0x01); /* Loop until driver state indicates finished request */ while (sclp_running_state != sclp_running_state_idle) { /* Check for expired request timer */ diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h index e53347fbf1da..fd57b8477fab 100644 --- a/include/asm-generic/atomic.h +++ b/include/asm-generic/atomic.h @@ -43,6 +43,7 @@ */ #define atomic_set(v, i) (((v)->counter) = (i)) +#include #include /** @@ -57,7 +58,7 @@ static inline int atomic_add_return(int i, atomic_t *v) unsigned long flags; int temp; - raw_local_irq_save(flags); /* Don't trace it in a irqsoff handler */ + raw_local_irq_save(flags); /* Don't trace it in an irqsoff handler */ temp = v->counter; temp += i; v->counter = temp; @@ -78,7 +79,7 @@ static inline int atomic_sub_return(int i, atomic_t *v) unsigned long flags; int temp; - raw_local_irq_save(flags); /* Don't trace it in a irqsoff handler */ + raw_local_irq_save(flags); /* Don't trace it in an irqsoff handler */ temp = v->counter; temp -= i; v->counter = temp; diff --git a/include/asm-generic/cmpxchg-local.h b/include/asm-generic/cmpxchg-local.h index b2ba2fc8829a..2533fddd34a6 100644 --- a/include/asm-generic/cmpxchg-local.h +++ b/include/asm-generic/cmpxchg-local.h @@ -2,6 +2,7 @@ #define __ASM_GENERIC_CMPXCHG_LOCAL_H #include +#include extern unsigned long wrong_size_cmpxchg(volatile void *ptr); diff --git a/include/asm-generic/hardirq.h b/include/asm-generic/hardirq.h index 62f59080e5cc..c0771aa248cf 100644 --- a/include/asm-generic/hardirq.h +++ b/include/asm-generic/hardirq.h @@ -3,7 +3,6 @@ #include #include -#include typedef struct { unsigned int __softirq_pending; diff --git a/include/asm-generic/irqflags.h b/include/asm-generic/irqflags.h index 9aebf618275a..1f40d0024cf3 100644 --- a/include/asm-generic/irqflags.h +++ b/include/asm-generic/irqflags.h @@ -5,68 +5,62 @@ * All architectures should implement at least the first two functions, * usually inline assembly will be the best way. */ -#ifndef RAW_IRQ_DISABLED -#define RAW_IRQ_DISABLED 0 -#define RAW_IRQ_ENABLED 1 +#ifndef ARCH_IRQ_DISABLED +#define ARCH_IRQ_DISABLED 0 +#define ARCH_IRQ_ENABLED 1 #endif /* read interrupt enabled status */ -#ifndef __raw_local_save_flags -unsigned long __raw_local_save_flags(void); +#ifndef arch_local_save_flags +unsigned long arch_local_save_flags(void); #endif /* set interrupt enabled status */ -#ifndef raw_local_irq_restore -void raw_local_irq_restore(unsigned long flags); +#ifndef arch_local_irq_restore +void arch_local_irq_restore(unsigned long flags); #endif /* get status and disable interrupts */ -#ifndef __raw_local_irq_save -static inline unsigned long __raw_local_irq_save(void) +#ifndef arch_local_irq_save +static inline unsigned long arch_local_irq_save(void) { unsigned long flags; - flags = __raw_local_save_flags(); - raw_local_irq_restore(RAW_IRQ_DISABLED); + flags = arch_local_save_flags(); + arch_local_irq_restore(ARCH_IRQ_DISABLED); return flags; } #endif /* test flags */ -#ifndef raw_irqs_disabled_flags -static inline int raw_irqs_disabled_flags(unsigned long flags) +#ifndef arch_irqs_disabled_flags +static inline int arch_irqs_disabled_flags(unsigned long flags) { - return flags == RAW_IRQ_DISABLED; + return flags == ARCH_IRQ_DISABLED; } #endif /* unconditionally enable interrupts */ -#ifndef raw_local_irq_enable -static inline void raw_local_irq_enable(void) +#ifndef arch_local_irq_enable +static inline void arch_local_irq_enable(void) { - raw_local_irq_restore(RAW_IRQ_ENABLED); + arch_local_irq_restore(ARCH_IRQ_ENABLED); } #endif /* unconditionally disable interrupts */ -#ifndef raw_local_irq_disable -static inline void raw_local_irq_disable(void) +#ifndef arch_local_irq_disable +static inline void arch_local_irq_disable(void) { - raw_local_irq_restore(RAW_IRQ_DISABLED); + arch_local_irq_restore(ARCH_IRQ_DISABLED); } #endif /* test hardware interrupt enable bit */ -#ifndef raw_irqs_disabled -static inline int raw_irqs_disabled(void) +#ifndef arch_irqs_disabled +static inline int arch_irqs_disabled(void) { - return raw_irqs_disabled_flags(__raw_local_save_flags()); + return arch_irqs_disabled_flags(arch_local_save_flags()); } #endif -#define raw_local_save_flags(flags) \ - do { (flags) = __raw_local_save_flags(); } while (0) - -#define raw_local_irq_save(flags) \ - do { (flags) = __raw_local_irq_save(); } while (0) - #endif /* __ASM_GENERIC_IRQFLAGS_H */ diff --git a/include/linux/irqflags.h b/include/linux/irqflags.h index 006bf45eae30..d176d658fe25 100644 --- a/include/linux/irqflags.h +++ b/include/linux/irqflags.h @@ -12,6 +12,7 @@ #define _LINUX_TRACE_IRQFLAGS_H #include +#include #ifdef CONFIG_TRACE_IRQFLAGS extern void trace_softirqs_on(unsigned long ip); @@ -52,17 +53,45 @@ # define start_critical_timings() do { } while (0) #endif -#ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT - -#include +/* + * Wrap the arch provided IRQ routines to provide appropriate checks. + */ +#define raw_local_irq_disable() arch_local_irq_disable() +#define raw_local_irq_enable() arch_local_irq_enable() +#define raw_local_irq_save(flags) \ + do { \ + typecheck(unsigned long, flags); \ + flags = arch_local_irq_save(); \ + } while (0) +#define raw_local_irq_restore(flags) \ + do { \ + typecheck(unsigned long, flags); \ + arch_local_irq_restore(flags); \ + } while (0) +#define raw_local_save_flags(flags) \ + do { \ + typecheck(unsigned long, flags); \ + flags = arch_local_save_flags(); \ + } while (0) +#define raw_irqs_disabled_flags(flags) \ + ({ \ + typecheck(unsigned long, flags); \ + arch_irqs_disabled_flags(flags); \ + }) +#define raw_irqs_disabled() (arch_irqs_disabled()) +#define raw_safe_halt() arch_safe_halt() +/* + * The local_irq_*() APIs are equal to the raw_local_irq*() + * if !TRACE_IRQFLAGS. + */ +#ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT #define local_irq_enable() \ do { trace_hardirqs_on(); raw_local_irq_enable(); } while (0) #define local_irq_disable() \ do { raw_local_irq_disable(); trace_hardirqs_off(); } while (0) #define local_irq_save(flags) \ do { \ - typecheck(unsigned long, flags); \ raw_local_irq_save(flags); \ trace_hardirqs_off(); \ } while (0) @@ -70,7 +99,6 @@ #define local_irq_restore(flags) \ do { \ - typecheck(unsigned long, flags); \ if (raw_irqs_disabled_flags(flags)) { \ raw_local_irq_restore(flags); \ trace_hardirqs_off(); \ @@ -79,51 +107,44 @@ raw_local_irq_restore(flags); \ } \ } while (0) -#else /* !CONFIG_TRACE_IRQFLAGS_SUPPORT */ -/* - * The local_irq_*() APIs are equal to the raw_local_irq*() - * if !TRACE_IRQFLAGS. - */ -# define raw_local_irq_disable() local_irq_disable() -# define raw_local_irq_enable() local_irq_enable() -# define raw_local_irq_save(flags) \ - do { \ - typecheck(unsigned long, flags); \ - local_irq_save(flags); \ - } while (0) -# define raw_local_irq_restore(flags) \ +#define local_save_flags(flags) \ do { \ - typecheck(unsigned long, flags); \ - local_irq_restore(flags); \ + raw_local_save_flags(flags); \ } while (0) -#endif /* CONFIG_TRACE_IRQFLAGS_SUPPORT */ -#ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT -#define safe_halt() \ - do { \ - trace_hardirqs_on(); \ - raw_safe_halt(); \ - } while (0) +#define irqs_disabled_flags(flags) \ + ({ \ + raw_irqs_disabled_flags(flags); \ + }) -#define local_save_flags(flags) \ - do { \ - typecheck(unsigned long, flags); \ - raw_local_save_flags(flags); \ +#define irqs_disabled() \ + ({ \ + unsigned long _flags; \ + raw_local_save_flags(_flags); \ + raw_irqs_disabled_flags(_flags); \ + }) + +#define safe_halt() \ + do { \ + trace_hardirqs_on(); \ + raw_safe_halt(); \ } while (0) -#define irqs_disabled() \ -({ \ - unsigned long _flags; \ - \ - raw_local_save_flags(_flags); \ - raw_irqs_disabled_flags(_flags); \ -}) -#define irqs_disabled_flags(flags) \ -({ \ - typecheck(unsigned long, flags); \ - raw_irqs_disabled_flags(flags); \ -}) +#else /* !CONFIG_TRACE_IRQFLAGS_SUPPORT */ + +#define local_irq_enable() do { raw_local_irq_enable(); } while (0) +#define local_irq_disable() do { raw_local_irq_disable(); } while (0) +#define local_irq_save(flags) \ + do { \ + raw_local_irq_save(flags); \ + } while (0) +#define local_irq_restore(flags) do { raw_local_irq_restore(flags); } while (0) +#define local_save_flags(flags) do { raw_local_save_flags(flags); } while (0) +#define irqs_disabled() (raw_irqs_disabled()) +#define irqs_disabled_flags(flags) (raw_irqs_disabled_flags(flags)) +#define safe_halt() do { raw_safe_halt(); } while (0) + #endif /* CONFIG_TRACE_IRQFLAGS_SUPPORT */ #endif diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h index f8854655860e..80e535897de6 100644 --- a/include/linux/spinlock.h +++ b/include/linux/spinlock.h @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From 67dd8995fd60bab890b9c3c4cd3e9f00d5811c25 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Wed, 22 Sep 2010 07:55:59 +0200 Subject: AT91: at91sam9m10g45ek: use the right machine id Today the board use 2 machines id AT91SAM9G45EKES and AT91SAM9M10G45EK now will use only AT91SAM9M10G45EK. The other boards revision will be specified via system_rev. for 9g45ekes, m10g45ekes and m10g45ek boards and revisions Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: Patrice Vilchez Acked-by: Nicolas Ferre --- arch/arm/mach-at91/Kconfig | 4 ++-- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 939bccd70569..7b6ae6d274b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -383,8 +383,8 @@ if ARCH_AT91SAM9G45 comment "AT91SAM9G45 Board Type" -config MACH_AT91SAM9G45EKES - bool "Atmel AT91SAM9G45-EKES Evaluation Kit" +config MACH_AT91SAM9M10G45EK + bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index ca2ac003f41f..585ede048966 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -70,7 +70,7 @@ obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o # AT91SAM9G45 board-specific support -obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o +obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o # AT91CAP9 board-specific support obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index ee800595594d..f9bf45e65cb2 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -399,7 +399,7 @@ static void __init ek_board_init(void) at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led)); } -MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES") +MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") /* Maintainer: Atmel */ .phys_io = AT91_BASE_SYS, .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -- cgit v1.2.3 From 9a400da84ffe7205b9921c87ac24069217442c84 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 1 Jul 2010 10:55:45 +0200 Subject: AT91: Correct configuration define value The MTD nand driver for Atmel chips is atmel_nand and not at91_nand anymore. Change wrong configuration variables that were remaining. Reported-by: Christoph Egger Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/board-at572d940hf_ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c index 5daff277f53e..46651623f208 100644 --- a/arch/arm/mach-at91/board-at572d940hf_ek.c +++ b/arch/arm/mach-at91/board-at572d940hf_ek.c @@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = { /* .rdy_pin = AT91_PIN_PC16, */ .enable_pin = AT91_PIN_PA15, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) .bus_width_16 = 1, #else .bus_width_16 = 0, diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index f9bf45e65cb2..ae0e0843e5f5 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c @@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = { .rdy_pin = AT91_PIN_PC8, .enable_pin = AT91_PIN_PC14, .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) .bus_width_16 = 1, #else .bus_width_16 = 0, -- cgit v1.2.3 From a6e016f19d393fbe4e040bee8155b03b840fa689 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 21 Sep 2010 18:01:37 +0200 Subject: AT91: at91sam9g20ek: merge 2mmc version in one board The board-sam9g20ek-2slot-mmc.c was a revision of the at91sam9g20ek since board revision C. It contains 2 sd/mmc slots. This merge keep the support of the old machine ID MACH_AT91SAM9G20EK_2MMC for backward compatibility. Now we use the ATAG to pass the hardware functionality to kernel with this board revision encoding bit 0: 0 => 1 sd/mmc slot 1 => 2 sd/mmc slots connectors (board from revision C) system_rev tested on Barebox commit d8f3ee103a9f4bd Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre --- arch/arm/configs/at91sam9g20ek_defconfig | 1 + arch/arm/mach-at91/Kconfig | 1 + arch/arm/mach-at91/Makefile | 1 - arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c | 329 ------------------------- arch/arm/mach-at91/board-sam9g20ek.c | 74 +++++- 5 files changed, 70 insertions(+), 336 deletions(-) delete mode 100644 arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c (limited to 'arch/arm') diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig index f1bac70d6ce9..9e90e6d79297 100644 --- a/arch/arm/configs/at91sam9g20ek_defconfig +++ b/arch/arm/configs/at91sam9g20ek_defconfig @@ -13,6 +13,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9G20=y CONFIG_MACH_AT91SAM9G20EK=y +CONFIG_MACH_AT91SAM9G20EK_2MMC=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 7b6ae6d274b4..23bf5c2c0fab 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -338,6 +338,7 @@ config MACH_AT91SAM9G20EK that embeds only one SD/MMC slot. config MACH_AT91SAM9G20EK_2MMC + depends on MACH_AT91SAM9G20EK bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" select HAVE_NAND_ATMEL_BUSWIDTH_16 help diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 585ede048966..3a07a3696441 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -61,7 +61,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o # AT91SAM9G20 board-specific support obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o -obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c deleted file mode 100644 index c49f5c003ee1..000000000000 --- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright (C) 2005 SAN People - * Copyright (C) 2008 Atmel - * Copyright (C) 2009 Rob Emanuele - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "sam9_smc.h" -#include "generic.h" - - -static void __init ek_map_io(void) -{ - /* Initialize processor: 18.432 MHz crystal */ - at91sam9260_initialize(18432000); - - /* DGBU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* set serial console to ttyS0 (ie, DBGU) */ - at91_set_serial_console(0); -} - -static void __init ek_init_irq(void) -{ - at91sam9260_init_interrupts(NULL); -} - - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PC5, - .pullup_pin = 0, /* pull-up driven by UDC */ -}; - - -/* - * SPI devices. - */ -static struct spi_board_info ek_spi_devices[] = { -#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91)) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .chip_select = 1, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) - { /* DataFlash card */ - .modalias = "mtd_dataflash", - .chip_select = 0, - .max_speed_hz = 15 * 1000 * 1000, - .bus_num = 0, - }, -#endif -#endif -}; - - -/* - * MACB Ethernet device - */ -static struct at91_eth_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PB0, - .is_rmii = 1, -}; - - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Bootstrap", - .offset = 0, - .size = 4 * SZ_1M, - }, - { - .name = "Partition 1", - .offset = MTDPART_OFS_NXTBLK, - .size = 60 * SZ_1M, - }, - { - .name = "Partition 2", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) -{ - *num_partitions = ARRAY_SIZE(ek_nand_partition); - return ek_nand_partition; -} - -/* det_pin is not connected */ -static struct atmel_nand_data __initdata ek_nand_data = { - .ale = 21, - .cle = 22, - .rdy_pin = AT91_PIN_PC13, - .enable_pin = AT91_PIN_PC14, - .partition_info = nand_partitions, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#else - .bus_width_16 = 0, -#endif -}; - -static struct sam9_smc_config __initdata ek_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 2, - .ncs_write_setup = 0, - .nwe_setup = 2, - - .ncs_read_pulse = 4, - .nrd_pulse = 4, - .ncs_write_pulse = 4, - .nwe_pulse = 4, - - .read_cycle = 7, - .write_cycle = 7, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 3, -}; - -static void __init ek_add_device_nand(void) -{ - /* setup bus-width (8 or 16) */ - if (ek_nand_data.bus_width_16) - ek_nand_smc_config.mode |= AT91_SMC_DBW_16; - else - ek_nand_smc_config.mode |= AT91_SMC_DBW_8; - - /* configure chip-select 3 (NAND) */ - sam9_smc_configure(3, &ek_nand_smc_config); - - at91_add_device_nand(&ek_nand_data); -} - - -/* - * MCI (SD/MMC) - * wp_pin is not connected - */ -#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) -static struct mci_platform_data __initdata ek_mmc_data = { - .slot[0] = { - .bus_width = 4, - .detect_pin = AT91_PIN_PC2, - .wp_pin = -ENODEV, - }, - .slot[1] = { - .bus_width = 4, - .detect_pin = AT91_PIN_PC9, - .wp_pin = -ENODEV, - }, - -}; -#else -static struct at91_mmc_data __initdata ek_mmc_data = { - .slot_b = 1, /* Only one slot so use slot B */ - .wire4 = 1, - .det_pin = AT91_PIN_PC9, -}; -#endif - -/* - * LEDs - */ -static struct gpio_led ek_leds[] = { - { /* "bottom" led, green, userled1 to be defined */ - .name = "ds5", - .gpio = AT91_PIN_PB8, - .active_low = 1, - .default_trigger = "none", - }, - { /* "power" led, yellow */ - .name = "ds1", - .gpio = AT91_PIN_PB9, - .default_trigger = "heartbeat", - } -}; - -#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) -static struct regulator_consumer_supply ek_audio_consumer_supplies[] = { - REGULATOR_SUPPLY("AVDD", "0-001b"), - REGULATOR_SUPPLY("HPVDD", "0-001b"), - REGULATOR_SUPPLY("DBVDD", "0-001b"), - REGULATOR_SUPPLY("DCVDD", "0-001b"), -}; - -static struct regulator_init_data ek_avdd_reg_init_data = { - .constraints = { - .name = "3V3", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .consumer_supplies = ek_audio_consumer_supplies, - .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies), -}; - -static struct fixed_voltage_config ek_vdd_pdata = { - .supply_name = "board-3V3", - .microvolts = 3300000, - .gpio = -EINVAL, - .enabled_at_boot = 0, - .init_data = &ek_avdd_reg_init_data, -}; -static struct platform_device ek_voltage_regulator = { - .name = "reg-fixed-voltage", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_vdd_pdata, - }, -}; -static void __init ek_add_regulators(void) -{ - platform_device_register(&ek_voltage_regulator); -} -#else -static void __init ek_add_regulators(void) {} -#endif - -static struct i2c_board_info __initdata ek_i2c_devices[] = { - { - I2C_BOARD_INFO("24c512", 0x50), - }, -}; - - -static void __init ek_board_init(void) -{ - /* Serial */ - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - /* NAND */ - ek_add_device_nand(); - /* Ethernet */ - at91_add_device_eth(&ek_macb_data); - /* Regulators */ - ek_add_regulators(); - /* MMC */ -#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) - at91_add_device_mci(0, &ek_mmc_data); -#else - at91_add_device_mmc(0, &ek_mmc_data); -#endif - /* I2C */ - at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); - /* LEDs */ - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* PCK0 provides MCLK to the WM8731 */ - at91_set_B_periph(AT91_PIN_PC1, 0); - /* SSC (for WM8731) */ - at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); -} - -MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") - /* Maintainer: Rob Emanuele */ - .phys_io = AT91_BASE_SYS, - .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, - .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, - .map_io = ek_map_io, - .init_irq = ek_init_irq, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 6ea9808b8868..b463e340c4a0 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c @@ -47,6 +47,18 @@ #include "sam9_smc.h" #include "generic.h" +/* + * board revision encoding + * bit 0: + * 0 => 1 sd/mmc slot + * 1 => 2 sd/mmc slots connectors (board from revision C) + */ +#define HAVE_2MMC (1 << 0) +static int inline ek_have_2mmc(void) +{ + return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC); +} + static void __init ek_map_io(void) { @@ -94,7 +106,7 @@ static struct at91_udc_data __initdata ek_udc_data = { * SPI devices. */ static struct spi_board_info ek_spi_devices[] = { -#if !defined(CONFIG_MMC_AT91) +#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91)) { /* DataFlash chip */ .modalias = "mtd_dataflash", .chip_select = 1, @@ -121,6 +133,13 @@ static struct at91_eth_data __initdata ek_macb_data = { .is_rmii = 1, }; +static void __init ek_add_device_macb(void) +{ + if (ek_have_2mmc()) + ek_macb_data.phy_irq_pin = AT91_PIN_PB0; + + at91_add_device_eth(&ek_macb_data); +} /* * NAND flash @@ -198,13 +217,36 @@ static void __init ek_add_device_nand(void) /* * MCI (SD/MMC) - * det_pin, wp_pin and vcc_pin are not connected + * wp_pin and vcc_pin are not connected */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) +static struct mci_platform_data __initdata ek_mmc_data = { + .slot[1] = { + .bus_width = 4, + .detect_pin = AT91_PIN_PC9, + }, + +}; +#else static struct at91_mmc_data __initdata ek_mmc_data = { - .slot_b = 1, + .slot_b = 1, /* Only one slot so use slot B */ .wire4 = 1, + .det_pin = AT91_PIN_PC9, }; +#endif +static void __init ek_add_device_mmc(void) +{ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) + if (ek_have_2mmc()) { + ek_mmc_data.slot[0].bus_width = 4; + ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2; + } + at91_add_device_mci(0, &ek_mmc_data); +#else + at91_add_device_mmc(0, &ek_mmc_data); +#endif +} /* * LEDs @@ -223,6 +265,15 @@ static struct gpio_led ek_leds[] = { } }; +static void __init ek_add_device_gpio_leds(void) +{ + if (ek_have_2mmc()) { + ek_leds[0].gpio = AT91_PIN_PB8; + ek_leds[1].gpio = AT91_PIN_PB9; + } + + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); +} /* * GPIO Buttons @@ -336,15 +387,15 @@ static void __init ek_board_init(void) /* NAND */ ek_add_device_nand(); /* Ethernet */ - at91_add_device_eth(&ek_macb_data); + ek_add_device_macb(); /* Regulators */ ek_add_regulators(); /* MMC */ - at91_add_device_mmc(0, &ek_mmc_data); + ek_add_device_mmc(); /* I2C */ at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); /* LEDs */ - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); + ek_add_device_gpio_leds(); /* Push Buttons */ ek_add_device_buttons(); /* PCK0 provides MCLK to the WM8731 */ @@ -363,3 +414,14 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") .init_irq = ek_init_irq, .init_machine = ek_board_init, MACHINE_END + +MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") + /* Maintainer: Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END -- cgit v1.2.3 From cb809b1a5ebffca8cf0314b788919989e8e4ab5f Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Tue, 21 Sep 2010 20:39:40 +1000 Subject: AT91: fix use of clock disable on idle for AT91x40 devices The simpler AT91x40 processors do not have the same power management controller as the new AT91 devices. They do have a simpler power controller module that we can use to disable the CPU clock at idle time. Add code to support that. Signed-off-by: Greg Ungerer Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Nicolas Ferre --- arch/arm/mach-at91/include/mach/at91x40.h | 6 ++++++ arch/arm/mach-at91/include/mach/system.h | 4 ++++ 2 files changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h index d34cdb8abdca..063ac44a0204 100644 --- a/arch/arm/mach-at91/include/mach/at91x40.h +++ b/arch/arm/mach-at91/include/mach/at91x40.h @@ -52,4 +52,10 @@ #define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ #define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ +/* + * Support defines for the simple Power Controller module. + */ +#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */ +#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */ + #endif /* AT91X40_H */ diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h index c80e090b3670..bfbb612265d6 100644 --- a/arch/arm/mach-at91/include/mach/system.h +++ b/arch/arm/mach-at91/include/mach/system.h @@ -33,7 +33,11 @@ static inline void arch_idle(void) * Disable the processor clock. The processor will be automatically * re-enabled by an interrupt or by a reset. */ +#ifdef AT91_PS + at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU); +#else at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); +#endif #else /* * Set the processor (CP15) into 'Wait for Interrupt' mode. -- cgit v1.2.3 From ee621dd619b9a85eced150fc06e352fef54cfda0 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 8 Aug 2010 06:21:33 +0200 Subject: net: atmel_macb Kconfig: remove long dependency line Many Atmel SOC are embedding a MACB controller. This patch removes the long dependency line for this Atmel MACB ethernet driver configuration entry. The HAVE_NET_MACB configuration option is located in the net Kconfig file as it may be setup by ARM/AT91 and AVR32 chips. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: David Miller Cc: Haavard Skinnemoen Acked-by: Nicolas Ferre Acked-by: Andrew Victor --- arch/arm/mach-at91/Kconfig | 4 ++++ arch/avr32/Kconfig | 1 + drivers/net/Kconfig | 5 ++++- 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 23bf5c2c0fab..bbd5efa65099 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -33,6 +33,7 @@ config ARCH_AT91SAM9260 select HAVE_AT91_USART3 select HAVE_AT91_USART4 select HAVE_AT91_USART5 + select HAVE_NET_MACB config ARCH_AT91SAM9261 bool "AT91SAM9261" @@ -51,6 +52,7 @@ config ARCH_AT91SAM9263 select CPU_ARM926T select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL + select HAVE_NET_MACB config ARCH_AT91SAM9RL bool "AT91SAM9RL" @@ -66,6 +68,7 @@ config ARCH_AT91SAM9G20 select HAVE_AT91_USART3 select HAVE_AT91_USART4 select HAVE_AT91_USART5 + select HAVE_NET_MACB config ARCH_AT91SAM9G45 bool "AT91SAM9G45" @@ -73,6 +76,7 @@ config ARCH_AT91SAM9G45 select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 select HAVE_FB_ATMEL + select HAVE_NET_MACB config ARCH_AT91CAP9 bool "AT91CAP9" diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index f51572772e21..9ac87255a03a 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -90,6 +90,7 @@ config PLATFORM_AT32AP select ARCH_REQUIRE_GPIOLIB select GENERIC_ALLOCATOR select HAVE_FB_ATMEL + select HAVE_NET_MACB # # CPU types diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2cc81a54cbf3..1c767ade7ef8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2,6 +2,9 @@ # Network device configuration # +config HAVE_NET_MACB + bool + menuconfig NETDEVICES default y if UML depends on NET @@ -221,7 +224,7 @@ config MII config MACB tristate "Atmel MACB support" - depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 + depends on HAVE_NET_MACB select PHYLIB help The Atmel MACB ethernet interface is found on many AT32 and AT91 -- cgit v1.2.3 From 2446783250fc12ba9bc39771e04988692742ed90 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Thu, 7 Oct 2010 16:38:49 +0200 Subject: leds: add LED driver for Big Network series LEDs This patch add a LED class driver for LEDs found on the LaCie 2Big and 5Big Network v2 boards. The LEDs are wired to a CPLD and are controlled through a GPIO extension bus. Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/include/mach/leds-netxbig.h | 55 +++ drivers/leds/Kconfig | 9 + drivers/leds/Makefile | 1 + drivers/leds/leds-netxbig.c | 449 +++++++++++++++++++++ 4 files changed, 514 insertions(+) create mode 100644 arch/arm/mach-kirkwood/include/mach/leds-netxbig.h create mode 100644 drivers/leds/leds-netxbig.c (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h new file mode 100644 index 000000000000..24b536ebdf13 --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h @@ -0,0 +1,55 @@ +/* + * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h + * + * Platform data structure for netxbig LED driver + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_LEDS_NETXBIG_H +#define __MACH_LEDS_NETXBIG_H + +struct netxbig_gpio_ext { + unsigned *addr; + int num_addr; + unsigned *data; + int num_data; + unsigned enable; +}; + +enum netxbig_led_mode { + NETXBIG_LED_OFF, + NETXBIG_LED_ON, + NETXBIG_LED_SATA, + NETXBIG_LED_TIMER1, + NETXBIG_LED_TIMER2, + NETXBIG_LED_MODE_NUM, +}; + +#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM + +struct netxbig_led_timer { + unsigned long delay_on; + unsigned long delay_off; + enum netxbig_led_mode mode; +}; + +struct netxbig_led { + const char *name; + const char *default_trigger; + int mode_addr; + int *mode_val; + int bright_addr; +}; + +struct netxbig_led_platform_data { + struct netxbig_gpio_ext *gpio_ext; + struct netxbig_led_timer *timer; + int num_timer; + struct netxbig_led *leds; + int num_leds; +}; + +#endif /* __MACH_LEDS_NETXBIG_H */ diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 4206ee0c9cc4..cc2a88d5192f 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -311,6 +311,15 @@ config LEDS_NS2 Network Space v2 board (and parents). This include Internet Space v2, Network Space (Max) v2 and d2 Network v2 boards. +config LEDS_NETXBIG + tristate "LED support for Big Network series LEDs" + depends on MACH_NET2BIG_V2 || MACH_NET5BIG_V2 + default y + help + This option enable support for LEDs found on the LaCie 2Big + and 5Big Network v2 boards. The LEDs are wired to a CPLD and are + controlled through a GPIO extension bus. + config LEDS_TRIGGERS bool "LED Trigger support" help diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 7d6b95831f8e..9c96db40ef6d 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_LEDS_ADP5520) += leds-adp5520.o obj-$(CONFIG_LEDS_DELL_NETBOOKS) += dell-led.o obj-$(CONFIG_LEDS_MC13783) += leds-mc13783.o obj-$(CONFIG_LEDS_NS2) += leds-ns2.o +obj-$(CONFIG_LEDS_NETXBIG) += leds-netxbig.o # LED SPI Drivers obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o diff --git a/drivers/leds/leds-netxbig.c b/drivers/leds/leds-netxbig.c new file mode 100644 index 000000000000..f2e51c134399 --- /dev/null +++ b/drivers/leds/leds-netxbig.c @@ -0,0 +1,449 @@ +/* + * leds-netxbig.c - Driver for the 2Big and 5Big Network series LEDs + * + * Copyright (C) 2010 LaCie + * + * Author: Simon Guinot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * GPIO extension bus. + */ + +static DEFINE_SPINLOCK(gpio_ext_lock); + +static void gpio_ext_set_addr(struct netxbig_gpio_ext *gpio_ext, int addr) +{ + int pin; + + for (pin = 0; pin < gpio_ext->num_addr; pin++) + gpio_set_value(gpio_ext->addr[pin], (addr >> pin) & 1); +} + +static void gpio_ext_set_data(struct netxbig_gpio_ext *gpio_ext, int data) +{ + int pin; + + for (pin = 0; pin < gpio_ext->num_data; pin++) + gpio_set_value(gpio_ext->data[pin], (data >> pin) & 1); +} + +static void gpio_ext_enable_select(struct netxbig_gpio_ext *gpio_ext) +{ + /* Enable select is done on the raising edge. */ + gpio_set_value(gpio_ext->enable, 0); + gpio_set_value(gpio_ext->enable, 1); +} + +static void gpio_ext_set_value(struct netxbig_gpio_ext *gpio_ext, + int addr, int value) +{ + unsigned long flags; + + spin_lock_irqsave(&gpio_ext_lock, flags); + gpio_ext_set_addr(gpio_ext, addr); + gpio_ext_set_data(gpio_ext, value); + gpio_ext_enable_select(gpio_ext); + spin_unlock_irqrestore(&gpio_ext_lock, flags); +} + +static int __devinit gpio_ext_init(struct netxbig_gpio_ext *gpio_ext) +{ + int err; + int i; + + if (unlikely(!gpio_ext)) + return -EINVAL; + + /* Configure address GPIOs. */ + for (i = 0; i < gpio_ext->num_addr; i++) { + err = gpio_request(gpio_ext->addr[i], "GPIO extension addr"); + if (err) + goto err_free_addr; + err = gpio_direction_output(gpio_ext->addr[i], 0); + if (err) { + gpio_free(gpio_ext->addr[i]); + goto err_free_addr; + } + } + /* Configure data GPIOs. */ + for (i = 0; i < gpio_ext->num_data; i++) { + err = gpio_request(gpio_ext->data[i], "GPIO extension data"); + if (err) + goto err_free_data; + err = gpio_direction_output(gpio_ext->data[i], 0); + if (err) { + gpio_free(gpio_ext->data[i]); + goto err_free_data; + } + } + /* Configure "enable select" GPIO. */ + err = gpio_request(gpio_ext->enable, "GPIO extension enable"); + if (err) + goto err_free_data; + err = gpio_direction_output(gpio_ext->enable, 0); + if (err) { + gpio_free(gpio_ext->enable); + goto err_free_data; + } + + return 0; + +err_free_data: + for (i = i - 1; i >= 0; i--) + gpio_free(gpio_ext->data[i]); + i = gpio_ext->num_addr; +err_free_addr: + for (i = i - 1; i >= 0; i--) + gpio_free(gpio_ext->addr[i]); + + return err; +} + +static void __devexit gpio_ext_free(struct netxbig_gpio_ext *gpio_ext) +{ + int i; + + gpio_free(gpio_ext->enable); + for (i = gpio_ext->num_addr - 1; i >= 0; i--) + gpio_free(gpio_ext->addr[i]); + for (i = gpio_ext->num_data - 1; i >= 0; i--) + gpio_free(gpio_ext->data[i]); +} + +/* + * Class LED driver. + */ + +struct netxbig_led_data { + struct netxbig_gpio_ext *gpio_ext; + struct led_classdev cdev; + int mode_addr; + int *mode_val; + int bright_addr; + int bright_max; + struct netxbig_led_timer *timer; + int num_timer; + enum netxbig_led_mode mode; + int sata; + spinlock_t lock; +}; + +static int netxbig_led_get_timer_mode(enum netxbig_led_mode *mode, + unsigned long delay_on, + unsigned long delay_off, + struct netxbig_led_timer *timer, + int num_timer) +{ + int i; + + for (i = 0; i < num_timer; i++) { + if (timer[i].delay_on == delay_on && + timer[i].delay_off == delay_off) { + *mode = timer[i].mode; + return 0; + } + } + return -EINVAL; +} + +static int netxbig_led_blink_set(struct led_classdev *led_cdev, + unsigned long *delay_on, + unsigned long *delay_off) +{ + struct netxbig_led_data *led_dat = + container_of(led_cdev, struct netxbig_led_data, cdev); + enum netxbig_led_mode mode; + int mode_val; + int ret; + + /* Look for a LED mode with the requested timer frequency. */ + ret = netxbig_led_get_timer_mode(&mode, *delay_on, *delay_off, + led_dat->timer, led_dat->num_timer); + if (ret < 0) + return ret; + + mode_val = led_dat->mode_val[mode]; + if (mode_val == NETXBIG_LED_INVALID_MODE) + return -EINVAL; + + spin_lock_irq(&led_dat->lock); + + gpio_ext_set_value(led_dat->gpio_ext, led_dat->mode_addr, mode_val); + led_dat->mode = mode; + + spin_unlock_irq(&led_dat->lock); + + return 0; +} + +static void netxbig_led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct netxbig_led_data *led_dat = + container_of(led_cdev, struct netxbig_led_data, cdev); + enum netxbig_led_mode mode; + int mode_val, bright_val; + int set_brightness = 1; + unsigned long flags; + + spin_lock_irqsave(&led_dat->lock, flags); + + if (value == LED_OFF) { + mode = NETXBIG_LED_OFF; + set_brightness = 0; + } else { + if (led_dat->sata) + mode = NETXBIG_LED_SATA; + else if (led_dat->mode == NETXBIG_LED_OFF) + mode = NETXBIG_LED_ON; + else /* Keep 'timer' mode. */ + mode = led_dat->mode; + } + mode_val = led_dat->mode_val[mode]; + + gpio_ext_set_value(led_dat->gpio_ext, led_dat->mode_addr, mode_val); + led_dat->mode = mode; + /* + * Note that the brightness register is shared between all the + * SATA LEDs. So, change the brightness setting for a single + * SATA LED will affect all the others. + */ + if (set_brightness) { + bright_val = DIV_ROUND_UP(value * led_dat->bright_max, + LED_FULL); + gpio_ext_set_value(led_dat->gpio_ext, + led_dat->bright_addr, bright_val); + } + + spin_unlock_irqrestore(&led_dat->lock, flags); +} + +static ssize_t netxbig_led_sata_store(struct device *dev, + struct device_attribute *attr, + const char *buff, size_t count) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct netxbig_led_data *led_dat = + container_of(led_cdev, struct netxbig_led_data, cdev); + unsigned long enable; + enum netxbig_led_mode mode; + int mode_val; + int ret; + + ret = strict_strtoul(buff, 10, &enable); + if (ret < 0) + return ret; + + enable = !!enable; + + spin_lock_irq(&led_dat->lock); + + if (led_dat->sata == enable) { + ret = count; + goto exit_unlock; + } + + if (led_dat->mode != NETXBIG_LED_ON && + led_dat->mode != NETXBIG_LED_SATA) + mode = led_dat->mode; /* Keep modes 'off' and 'timer'. */ + else if (enable) + mode = NETXBIG_LED_SATA; + else + mode = NETXBIG_LED_ON; + + mode_val = led_dat->mode_val[mode]; + if (mode_val == NETXBIG_LED_INVALID_MODE) { + ret = -EINVAL; + goto exit_unlock; + } + + gpio_ext_set_value(led_dat->gpio_ext, led_dat->mode_addr, mode_val); + led_dat->mode = mode; + led_dat->sata = enable; + + ret = count; + +exit_unlock: + spin_unlock_irq(&led_dat->lock); + + return ret; +} + +static ssize_t netxbig_led_sata_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct led_classdev *led_cdev = dev_get_drvdata(dev); + struct netxbig_led_data *led_dat = + container_of(led_cdev, struct netxbig_led_data, cdev); + + return sprintf(buf, "%d\n", led_dat->sata); +} + +static DEVICE_ATTR(sata, 0644, netxbig_led_sata_show, netxbig_led_sata_store); + +static void __devexit delete_netxbig_led(struct netxbig_led_data *led_dat) +{ + if (led_dat->mode_val[NETXBIG_LED_SATA] != NETXBIG_LED_INVALID_MODE) + device_remove_file(led_dat->cdev.dev, &dev_attr_sata); + led_classdev_unregister(&led_dat->cdev); +} + +static int __devinit +create_netxbig_led(struct platform_device *pdev, + struct netxbig_led_data *led_dat, + const struct netxbig_led *template) +{ + struct netxbig_led_platform_data *pdata = pdev->dev.platform_data; + int ret; + + spin_lock_init(&led_dat->lock); + led_dat->gpio_ext = pdata->gpio_ext; + led_dat->cdev.name = template->name; + led_dat->cdev.default_trigger = template->default_trigger; + led_dat->cdev.blink_set = netxbig_led_blink_set; + led_dat->cdev.brightness_set = netxbig_led_set; + /* + * Because the GPIO extension bus don't allow to read registers + * value, there is no way to probe the LED initial state. + * So, the initial sysfs LED value for the "brightness" and "sata" + * attributes are inconsistent. + * + * Note that the initial LED state can't be reconfigured. + * The reason is that the LED behaviour must stay uniform during + * the whole boot process (bootloader+linux). + */ + led_dat->sata = 0; + led_dat->cdev.brightness = LED_OFF; + led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME; + led_dat->mode_addr = template->mode_addr; + led_dat->mode_val = template->mode_val; + led_dat->bright_addr = template->bright_addr; + led_dat->bright_max = (1 << pdata->gpio_ext->num_data) - 1; + led_dat->timer = pdata->timer; + led_dat->num_timer = pdata->num_timer; + + ret = led_classdev_register(&pdev->dev, &led_dat->cdev); + if (ret < 0) + return ret; + + /* + * If available, expose the SATA activity blink capability through + * a "sata" sysfs attribute. + */ + if (led_dat->mode_val[NETXBIG_LED_SATA] != NETXBIG_LED_INVALID_MODE) { + ret = device_create_file(led_dat->cdev.dev, &dev_attr_sata); + if (ret) + led_classdev_unregister(&led_dat->cdev); + } + + return ret; +} + +static int __devinit netxbig_led_probe(struct platform_device *pdev) +{ + struct netxbig_led_platform_data *pdata = pdev->dev.platform_data; + struct netxbig_led_data *leds_data; + int i; + int ret; + + if (!pdata) + return -EINVAL; + + leds_data = kzalloc(sizeof(struct netxbig_led_data) * pdata->num_leds, + GFP_KERNEL); + if (!leds_data) + return -ENOMEM; + + ret = gpio_ext_init(pdata->gpio_ext); + if (ret < 0) + goto err_free_data; + + for (i = 0; i < pdata->num_leds; i++) { + ret = create_netxbig_led(pdev, &leds_data[i], &pdata->leds[i]); + if (ret < 0) + goto err_free_leds; + } + + platform_set_drvdata(pdev, leds_data); + + return 0; + +err_free_leds: + for (i = i - 1; i >= 0; i--) + delete_netxbig_led(&leds_data[i]); + + gpio_ext_free(pdata->gpio_ext); +err_free_data: + kfree(leds_data); + + return ret; +} + +static int __devexit netxbig_led_remove(struct platform_device *pdev) +{ + struct netxbig_led_platform_data *pdata = pdev->dev.platform_data; + struct netxbig_led_data *leds_data; + int i; + + leds_data = platform_get_drvdata(pdev); + + for (i = 0; i < pdata->num_leds; i++) + delete_netxbig_led(&leds_data[i]); + + gpio_ext_free(pdata->gpio_ext); + kfree(leds_data); + + return 0; +} + +static struct platform_driver netxbig_led_driver = { + .probe = netxbig_led_probe, + .remove = __devexit_p(netxbig_led_remove), + .driver = { + .name = "leds-netxbig", + .owner = THIS_MODULE, + }, +}; +MODULE_ALIAS("platform:leds-netxbig"); + +static int __init netxbig_led_init(void) +{ + return platform_driver_register(&netxbig_led_driver); +} + +static void __exit netxbig_led_exit(void) +{ + platform_driver_unregister(&netxbig_led_driver); +} + +module_init(netxbig_led_init); +module_exit(netxbig_led_exit); + +MODULE_AUTHOR("Simon Guinot "); +MODULE_DESCRIPTION("LED driver for LaCie xBig Network boards"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From af9a2d006611124eb1de9d7fee160b25b252ad98 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Thu, 7 Oct 2010 16:38:50 +0200 Subject: [ARM] Kirkwood: add LED support for netxbig_v2 boards Signed-off-by: Simon Guinot Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/netxbig_v2-setup.c | 158 +++++++++++++++++++++++++----- 1 file changed, 133 insertions(+), 25 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c index aec528d6081f..d970e1eee37d 100644 --- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c +++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "common.h" #include "mpp.h" #include "lacie_v2-common.h" @@ -104,7 +105,7 @@ static struct platform_device netxbig_v2_gpio_buttons = { }; /***************************************************************************** - * GPIO LEDs + * GPIO extension LEDs ****************************************************************************/ /* @@ -114,19 +115,32 @@ static struct platform_device netxbig_v2_gpio_buttons = { * - address register : bit [0-2] -> GPIO [47-49] * - data register : bit [0-2] -> GPIO [44-46] * - enable register : GPIO 29 - * + */ + +static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 }; +static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 }; + +static struct netxbig_gpio_ext netxbig_v2_gpio_ext = { + .addr = netxbig_v2_gpio_ext_addr, + .num_addr = ARRAY_SIZE(netxbig_v2_gpio_ext_addr), + .data = netxbig_v2_gpio_ext_data, + .num_data = ARRAY_SIZE(netxbig_v2_gpio_ext_data), + .enable = 29, +}; + +/* * Address register selection: * * addr | register * ---------------------------- * 0 | front LED * 1 | front LED brightness - * 2 | HDD LED brightness - * 3 | HDD1 LED - * 4 | HDD2 LED - * 5 | HDD3 LED - * 6 | HDD4 LED - * 7 | HDD5 LED + * 2 | SATA LED brightness + * 3 | SATA0 LED + * 4 | SATA1 LED + * 5 | SATA2 LED + * 6 | SATA3 LED + * 7 | SATA4 LED * * Data register configuration: * @@ -147,18 +161,109 @@ static struct platform_device netxbig_v2_gpio_buttons = { * 6 | blink blue on=1 sec and red on=1 sec * 7 | blink blue on=0.5 sec and blue off=2.5 sec * - * data | HDD LED mode + * data | SATA LED mode * ------------------------------------------------- - * 0 | fix blue on + * 0 | fix off * 1 | SATA activity blink * 2 | fix red on * 3 | blink blue on=1 sec and blue off=1 sec * 4 | blink red on=1 sec and red off=1 sec * 5 | blink blue on=2.5 sec and red on=0.5 sec * 6 | blink blue on=1 sec and red on=1 sec - * 7 | blink blue on=0.5 sec and blue off=2.5 sec + * 7 | fix blue on */ +static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = { + [NETXBIG_LED_OFF] = 0, + [NETXBIG_LED_ON] = 2, + [NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE, + [NETXBIG_LED_TIMER1] = 4, + [NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE, +}; + +static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = { + [NETXBIG_LED_OFF] = 0, + [NETXBIG_LED_ON] = 1, + [NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE, + [NETXBIG_LED_TIMER1] = 3, + [NETXBIG_LED_TIMER2] = 7, +}; + +static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = { + [NETXBIG_LED_OFF] = 0, + [NETXBIG_LED_ON] = 7, + [NETXBIG_LED_SATA] = 1, + [NETXBIG_LED_TIMER1] = 3, + [NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE, +}; + +static struct netxbig_led_timer netxbig_v2_led_timer[] = { + [0] = { + .delay_on = 500, + .delay_off = 500, + .mode = NETXBIG_LED_TIMER1, + }, + [1] = { + .delay_on = 500, + .delay_off = 1000, + .mode = NETXBIG_LED_TIMER2, + }, +}; + +#define NETXBIG_LED(_name, maddr, mval, baddr) \ + { .name = _name, \ + .mode_addr = maddr, \ + .mode_val = mval, \ + .bright_addr = baddr } + +static struct netxbig_led net2big_v2_leds_ctrl[] = { + NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1), + NETXBIG_LED("net2big-v2:red:power", 0, netxbig_v2_red_mled, 1), + NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net2big-v2:red:sata0", 3, netxbig_v2_red_mled, 2), + NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net2big-v2:red:sata1", 4, netxbig_v2_red_mled, 2), +}; + +static struct netxbig_led_platform_data net2big_v2_leds_data = { + .gpio_ext = &netxbig_v2_gpio_ext, + .timer = netxbig_v2_led_timer, + .num_timer = ARRAY_SIZE(netxbig_v2_led_timer), + .leds = net2big_v2_leds_ctrl, + .num_leds = ARRAY_SIZE(net2big_v2_leds_ctrl), +}; + +static struct netxbig_led net5big_v2_leds_ctrl[] = { + NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1), + NETXBIG_LED("net5big-v2:red:power", 0, netxbig_v2_red_mled, 1), + NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net5big-v2:red:sata0", 3, netxbig_v2_red_mled, 2), + NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net5big-v2:red:sata1", 4, netxbig_v2_red_mled, 2), + NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net5big-v2:red:sata2", 5, netxbig_v2_red_mled, 2), + NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net5big-v2:red:sata3", 6, netxbig_v2_red_mled, 2), + NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2), + NETXBIG_LED("net5big-v2:red:sata5", 7, netxbig_v2_red_mled, 2), +}; + +static struct netxbig_led_platform_data net5big_v2_leds_data = { + .gpio_ext = &netxbig_v2_gpio_ext, + .timer = netxbig_v2_led_timer, + .num_timer = ARRAY_SIZE(netxbig_v2_led_timer), + .leds = net5big_v2_leds_ctrl, + .num_leds = ARRAY_SIZE(net5big_v2_leds_ctrl), +}; + +static struct platform_device netxbig_v2_leds = { + .name = "leds-netxbig", + .id = -1, + .dev = { + .platform_data = &net2big_v2_leds_data, + }, +}; + /***************************************************************************** * General Setup ****************************************************************************/ @@ -184,18 +289,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = { MPP24_GPIO, /* USB mode select */ MPP26_GPIO, /* USB device vbus */ MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* CPLD extension ALE */ + MPP29_GPIO, /* GPIO extension ALE */ MPP34_GPIO, /* Rear Push button */ MPP35_GPIO, /* Inhibit switch power-off */ MPP36_GPIO, /* SATA HDD1 presence */ MPP37_GPIO, /* SATA HDD2 presence */ MPP40_GPIO, /* eSATA presence */ - MPP44_GPIO, /* CPLD extension (data 0) */ - MPP45_GPIO, /* CPLD extension (data 1) */ - MPP46_GPIO, /* CPLD extension (data 2) */ - MPP47_GPIO, /* CPLD extension (addr 0) */ - MPP48_GPIO, /* CPLD extension (addr 1) */ - MPP49_GPIO, /* CPLD extension (addr 2) */ + MPP44_GPIO, /* GPIO extension (data 0) */ + MPP45_GPIO, /* GPIO extension (data 1) */ + MPP46_GPIO, /* GPIO extension (data 2) */ + MPP47_GPIO, /* GPIO extension (addr 0) */ + MPP48_GPIO, /* GPIO extension (addr 1) */ + MPP49_GPIO, /* GPIO extension (addr 2) */ 0 }; @@ -224,7 +329,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP26_GE1_RXD2, MPP27_GE1_RXD3, MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* CPLD extension ALE */ + MPP29_GPIO, /* GPIO extension ALE */ MPP30_GE1_RXCTL, MPP31_GE1_RXCLK, MPP32_GE1_TCLKOUT, @@ -239,12 +344,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = { MPP41_GPIO, /* SATA HDD3 power */ MPP42_GPIO, /* SATA HDD4 power */ MPP43_GPIO, /* SATA HDD5 power */ - MPP44_GPIO, /* CPLD extension (data 0) */ - MPP45_GPIO, /* CPLD extension (data 1) */ - MPP46_GPIO, /* CPLD extension (data 2) */ - MPP47_GPIO, /* CPLD extension (addr 0) */ - MPP48_GPIO, /* CPLD extension (addr 1) */ - MPP49_GPIO, /* CPLD extension (addr 2) */ + MPP44_GPIO, /* GPIO extension (data 0) */ + MPP45_GPIO, /* GPIO extension (data 1) */ + MPP46_GPIO, /* GPIO extension (data 2) */ + MPP47_GPIO, /* GPIO extension (addr 0) */ + MPP48_GPIO, /* GPIO extension (addr 1) */ + MPP49_GPIO, /* GPIO extension (addr 2) */ 0 }; @@ -280,6 +385,9 @@ static void __init netxbig_v2_init(void) lacie_v2_register_flash(); lacie_v2_register_i2c_devices(); + if (machine_is_net5big_v2()) + netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data; + platform_device_register(&netxbig_v2_leds); platform_device_register(&netxbig_v2_gpio_buttons); if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 && -- cgit v1.2.3 From 1a95036465e6abdcb639f0d7bb1ec612663caf5b Mon Sep 17 00:00:00 2001 From: Kukjin Kim Date: Thu, 9 Sep 2010 08:56:15 +0900 Subject: ARM: SAMSUNG: Fix build warnings because of unused codes This patch removes following unused codes for removing build warnings. arch/arm/plat-samsung/adc.c:438: warning: unused variable 'flags' arch/arm/mach-s5pv210/clock.c:176: warning: 's5pv210_clk_ip4_ctrl' defined but not used Signed-off-by: Kukjin Kim --- arch/arm/mach-s5pv210/clock.c | 5 ----- arch/arm/plat-samsung/adc.c | 1 - 2 files changed, 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index cfecd70657cb..d562670e1b0b 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -173,11 +173,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); } -static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); -} - static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 04d9521ddc9f..e8f2be2d67f2 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -435,7 +435,6 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) static int s3c_adc_resume(struct platform_device *pdev) { struct adc_device *adc = platform_get_drvdata(pdev); - unsigned long flags; clk_enable(adc->clk); enable_irq(adc->irq); -- cgit v1.2.3 From 4341f9b38fe33aab51439ae59593e149a6f61d9f Mon Sep 17 00:00:00 2001 From: SeungChull Suh Date: Sat, 2 Oct 2010 12:48:12 +0900 Subject: ARM: S5P: Bug fix on errors of build with CONFIG_PREEMPT_NONE This patch adds header into the below files for build with CONFIG_PREEMPT_NONE. arch/arm/mach-s5p6440/cpu.c arch/arm/mach-s5p6442/cpu.c arch/arm/mach-s5pc100/cpu.c arch/arm/mach-s5pv210/cpu.c Following is error message of in case of s5pv210_defconfig with CONFIG_PREEMPT_NONE. arch/arm/mach-s5pv210/cpu.c:91: error: implicit declaration of function 'need_resched' Signed-off-by: SeungChull Suh [kgene.kim@samsung.com: removed mach-s5p64x0/cpu.c] [kgene.kim@samsung.com: added fix mach-s5p6440/cpu.c] Signed-off-by: Kukjin Kim --- arch/arm/mach-s5p6440/cpu.c | 1 + arch/arm/mach-s5p6442/cpu.c | 1 + arch/arm/mach-s5pc100/cpu.c | 1 + arch/arm/mach-s5pv210/cpu.c | 1 + 4 files changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c index 526f33adb31d..ec592e866054 100644 --- a/arch/arm/mach-s5p6440/cpu.c +++ b/arch/arm/mach-s5p6440/cpu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c index a48fb553fd01..70ac681af72b 100644 --- a/arch/arm/mach-s5p6442/cpu.c +++ b/arch/arm/mach-s5p6442/cpu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index 251c92ac5b22..cd1afbce83e2 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 77f456c91ad3..245b82b53df4 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 7cf4b482f06df0b590a9bc1561a5a81d67e0fe4c Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 7 Oct 2010 17:19:10 +0900 Subject: ARM: SAMSUNG: Add a workaround for get_clock() for serial driver Serial drivers call get_clock() very early, before platform bus has been set up, this requires a special check to let them get a proper clock. Without this patch, a serial console is broken on S5PV310 and S5PC210 boards. Signed-off-by: Marek Szyprowski Signed-off-by: Kyungmin Park [kgene.kim@samsung.com: fix coding-style] Signed-off-by: Kukjin Kim Cc: Ben Dooks --- arch/arm/plat-samsung/clock.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c index 90a20512d68d..e8d20b0bc50e 100644 --- a/arch/arm/plat-samsung/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -48,6 +48,9 @@ #include #include +#include +#include /* for s3c24xx_uart_devs */ + /* clock information */ static LIST_HEAD(clocks); @@ -65,6 +68,28 @@ static int clk_null_enable(struct clk *clk, int enable) return 0; } +static int dev_is_s3c_uart(struct device *dev) +{ + struct platform_device **pdev = s3c24xx_uart_devs; + int i; + for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++) + if (*pdev && dev == &(*pdev)->dev) + return 1; + return 0; +} + +/* + * Serial drivers call get_clock() very early, before platform bus + * has been set up, this requires a special check to let them get + * a proper clock + */ + +static int dev_is_platform_device(struct device *dev) +{ + return dev->bus == &platform_bus_type || + (dev->bus == NULL && dev_is_s3c_uart(dev)); +} + /* Clock API calls */ struct clk *clk_get(struct device *dev, const char *id) @@ -73,7 +98,7 @@ struct clk *clk_get(struct device *dev, const char *id) struct clk *clk = ERR_PTR(-ENOENT); int idno; - if (dev == NULL || dev->bus != &platform_bus_type) + if (dev == NULL || !dev_is_platform_device(dev)) idno = -1; else idno = to_platform_device(dev)->id; -- cgit v1.2.3 From 5fd03ddab7fdbc44bfb2d183a4531c26a8dbca5a Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Tue, 5 Oct 2010 21:28:10 -0700 Subject: memblock/arm: Fix memblock_region_is_memory() typo Fix typo in commit dbe3039 ("memblock/arm: Use memblock_region_is_memory() for omap fb") - it should be memblock_is_region_memory(). Reported-by: Tomi Valkeinen Signed-off-by: Yinghai Lu Cc: Benjamin Herrenschmidt Cc: Felipe Balbi Cc: Kevin Hilman Cc: ext Grazvydas Ignotas LKML-Reference: <4CABFADA.9020305@kernel.org> Signed-off-by: Ingo Molnar --- arch/arm/plat-omap/fb.c | 2 +- drivers/video/omap2/vram.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index 441af2bdfd15..71934817e172 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c @@ -173,7 +173,7 @@ static int check_fbmem_region(int region_idx, struct omapfb_mem_region *rg, static int valid_sdram(unsigned long addr, unsigned long size) { - return memblock_region_is_memory(addr, size); + return memblock_is_region_memory(addr, size); } static int reserve_sdram(unsigned long addr, unsigned long size) diff --git a/drivers/video/omap2/vram.c b/drivers/video/omap2/vram.c index 34514a899d13..fed2a72bc6b6 100644 --- a/drivers/video/omap2/vram.c +++ b/drivers/video/omap2/vram.c @@ -555,7 +555,7 @@ void __init omap_vram_reserve_sdram_memblock(void) if (paddr) { if ((paddr & ~PAGE_MASK) || - !memblock_region_is_memory(paddr, size)) { + !memblock_is_region_memory(paddr, size)) { pr_err("Illegal SDRAM region for VRAM\n"); return; } -- cgit v1.2.3 From 69f22be7b10684ade3808de22db87c536ed135f3 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 27 Jul 2010 15:06:58 +0300 Subject: ARM: pxa: add U2D controller and ULPI driver for pxa3xx USB2.0 Device Controller (U2DC) which is found in Marvell PXA3xx. U2DC supports both High and Full speed modes. PXA320 and PXA300 U2DC supports only UTMI interface. PXA310 U2DC supports only ULPI interface and has the OTG capability. U2D Controller ULPI driver introduced in this patch supports only the PXA310 USB Host via the ULPI. Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 4 + arch/arm/mach-pxa/Makefile | 2 +- arch/arm/mach-pxa/devices.c | 28 ++ arch/arm/mach-pxa/devices.h | 1 + arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h | 35 +++ arch/arm/mach-pxa/pxa3xx-ulpi.c | 392 ++++++++++++++++++++++++++++ arch/arm/mach-pxa/pxa3xx.c | 2 +- 7 files changed, 462 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h create mode 100644 arch/arm/mach-pxa/pxa3xx-ulpi.c (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 7aefb9074852..3d4926edb675 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -643,6 +643,7 @@ config CPU_PXA300 config CPU_PXA310 bool select CPU_PXA300 + select PXA310_ULPI if USB_ULPI help PXA310 (codename Monahans-LV) @@ -698,4 +699,7 @@ config PXA_HAVE_BOARD_IRQS config PXA_HAVE_ISA_IRQS bool +config PXA310_ULPI + bool + endif diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 85c7fb324dbb..a1db59b124f9 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -18,7 +18,7 @@ endif # SoC-specific code obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o -obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o +obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 65447dc736c2..a2fc859251da 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -134,6 +135,33 @@ struct platform_device pxa27x_device_udc = { } }; +#ifdef CONFIG_PXA3xx +static struct resource pxa3xx_u2d_resources[] = { + [0] = { + .start = 0x54100000, + .end = 0x54100fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_USB2, + .end = IRQ_USB2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device pxa3xx_device_u2d = { + .name = "pxa3xx-u2d", + .id = -1, + .resource = pxa3xx_u2d_resources, + .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources), +}; + +void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info) +{ + pxa_register_device(&pxa3xx_device_u2d, info); +} +#endif /* CONFIG_PXA3xx */ + static struct resource pxafb_resources[] = { [0] = { .start = 0x44000000, diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 50353ea49ba4..715e8bd02e24 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -4,6 +4,7 @@ extern struct platform_device pxa3xx_device_mci2; extern struct platform_device pxa3xx_device_mci3; extern struct platform_device pxa25x_device_udc; extern struct platform_device pxa27x_device_udc; +extern struct platform_device pxa3xx_device_u2d; extern struct platform_device pxa_device_fb; extern struct platform_device pxa_device_ffuart; extern struct platform_device pxa_device_btuart; diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h new file mode 100644 index 000000000000..9d82cb65ea56 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h @@ -0,0 +1,35 @@ +/* + * PXA3xx U2D header + * + * Copyright (C) 2010 CompuLab Ltd. + * + * Igor Grinberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __PXA310_U2D__ +#define __PXA310_U2D__ + +#include + +struct pxa3xx_u2d_platform_data { + +#define ULPI_SER_6PIN (1 << 0) +#define ULPI_SER_3PIN (1 << 1) + unsigned int ulpi_mode; + + int (*init)(struct device *); + void (*exit)(struct device *); +}; + + +/* Start PXA3xx U2D host */ +int pxa3xx_u2d_start_hc(struct usb_bus *host); +/* Stop PXA3xx U2D host */ +void pxa3xx_u2d_stop_hc(struct usb_bus *host); + +extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info); + +#endif /* __PXA310_U2D__ */ diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c new file mode 100644 index 000000000000..e57439e01171 --- /dev/null +++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c @@ -0,0 +1,392 @@ +/* + * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c + * + * code specific to pxa3xx aka Monahans + * + * Copyright (C) 2010 CompuLab Ltd. + * + * 2010-13-07: Igor Grinberg + * initial version: pxa310 USB Host mode support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +struct pxa3xx_u2d_ulpi { + struct clk *clk; + void __iomem *mmio_base; + + struct otg_transceiver *otg; + unsigned int ulpi_mode; +}; + +static struct pxa3xx_u2d_ulpi *u2d; + +static inline u32 u2d_readl(u32 reg) +{ + return __raw_readl(u2d->mmio_base + reg); +} + +static inline void u2d_writel(u32 reg, u32 val) +{ + __raw_writel(val, u2d->mmio_base + reg); +} + +#if defined(CONFIG_PXA310_ULPI) +enum u2d_ulpi_phy_mode { + SYNCH = 0, + CARKIT = (1 << 0), + SER_3PIN = (1 << 1), + SER_6PIN = (1 << 2), + LOWPOWER = (1 << 3), +}; + +static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void) +{ + return (u2d_readl(U2DOTGUSR) >> 28) & 0xF; +} + +static int pxa310_ulpi_poll(void) +{ + int timeout = 50000; + + while (timeout--) { + if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN)) + return 0; + + cpu_relax(); + } + + pr_warning("%s: ULPI access timed out!\n", __func__); + + return -ETIMEDOUT; +} + +static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg) +{ + int err; + + if (pxa310_ulpi_get_phymode() != SYNCH) { + pr_warning("%s: PHY is not in SYNCH mode!\n", __func__); + return -EBUSY; + } + + u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16)); + msleep(5); + + err = pxa310_ulpi_poll(); + if (err) + return err; + + return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA; +} + +static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) +{ + if (pxa310_ulpi_get_phymode() != SYNCH) { + pr_warning("%s: PHY is not in SYNCH mode!\n", __func__); + return -EBUSY; + } + + u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8)); + msleep(5); + + return pxa310_ulpi_poll(); +} + +struct otg_io_access_ops pxa310_ulpi_access_ops = { + .read = pxa310_ulpi_read, + .write = pxa310_ulpi_write, +}; + +static void pxa310_otg_transceiver_rtsm(void) +{ + u32 u2dotgcr; + + /* put PHY to sync mode */ + u2dotgcr = u2d_readl(U2DOTGCR); + u2dotgcr |= U2DOTGCR_RTSM | U2DOTGCR_UTMID; + u2d_writel(U2DOTGCR, u2dotgcr); + msleep(10); + + /* setup OTG sync mode */ + u2dotgcr = u2d_readl(U2DOTGCR); + u2dotgcr |= U2DOTGCR_ULAF; + u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF); + u2d_writel(U2DOTGCR, u2dotgcr); +} + +static int pxa310_start_otg_host_transcvr(struct usb_bus *host) +{ + int err; + + pxa310_otg_transceiver_rtsm(); + + err = otg_init(u2d->otg); + if (err) { + pr_err("OTG transceiver init failed"); + return err; + } + + err = otg_set_vbus(u2d->otg, 1); + if (err) { + pr_err("OTG transceiver VBUS set failed"); + return err; + } + + err = otg_set_host(u2d->otg, host); + if (err) + pr_err("OTG transceiver Host mode set failed"); + + return err; +} + +static int pxa310_start_otg_hc(struct usb_bus *host) +{ + u32 u2dotgcr; + int err; + + /* disable USB device controller */ + u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE); + u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID); + u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F); + + err = pxa310_start_otg_host_transcvr(host); + if (err) + return err; + + /* set xceiver mode */ + if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL) + u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS); + else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL) + u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS); + + /* start OTG host controller */ + u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF; + u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF)); + + return 0; +} + +static void pxa310_stop_otg_hc(void) +{ + pxa310_otg_transceiver_rtsm(); + + otg_set_host(u2d->otg, NULL); + otg_set_vbus(u2d->otg, 0); + otg_shutdown(u2d->otg); +} + +static void pxa310_u2d_setup_otg_hc(void) +{ + u32 u2dotgcr; + + u2dotgcr = u2d_readl(U2DOTGCR); + u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID; + u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF); + u2d_writel(U2DOTGCR, u2dotgcr); + msleep(5); + u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE); + msleep(5); + u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F); +} + +static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata) +{ + unsigned int ulpi_mode = ULPI_OTG_DRVVBUS; + + if (pdata) { + if (pdata->ulpi_mode & ULPI_SER_6PIN) + ulpi_mode |= ULPI_IC_6PIN_SERIAL; + else if (pdata->ulpi_mode & ULPI_SER_3PIN) + ulpi_mode |= ULPI_IC_3PIN_SERIAL; + } + + u2d->ulpi_mode = ulpi_mode; + + u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode); + if (!u2d->otg) + return -ENOMEM; + + u2d->otg->io_priv = u2d->mmio_base; + + return 0; +} + +static void pxa310_otg_exit(void) +{ + kfree(u2d->otg); +} +#else +static inline void pxa310_u2d_setup_otg_hc(void) {} +static inline int pxa310_start_otg_hc(struct usb_bus *host) +{ + return 0; +} +static inline void pxa310_stop_otg_hc(void) {} +static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata) +{ + return 0; +} +static inline void pxa310_otg_exit(void) {} +#endif /* CONFIG_PXA310_ULPI */ + +int pxa3xx_u2d_start_hc(struct usb_bus *host) +{ + int err = 0; + + clk_enable(u2d->clk); + + if (cpu_is_pxa310()) { + pxa310_u2d_setup_otg_hc(); + err = pxa310_start_otg_hc(host); + } + + return err; +} + +void pxa3xx_u2d_stop_hc(struct usb_bus *host) +{ + if (cpu_is_pxa310()) + pxa310_stop_otg_hc(); + + clk_disable(u2d->clk); +} + +static int pxa3xx_u2d_probe(struct platform_device *pdev) +{ + struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data; + struct resource *r; + int err; + + u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL); + if (!u2d) { + dev_err(&pdev->dev, "failed to allocate memory\n"); + return -ENOMEM; + } + + u2d->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(u2d->clk)) { + dev_err(&pdev->dev, "failed to get u2d clock\n"); + err = PTR_ERR(u2d->clk); + goto err_free_mem; + } + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "no IO memory resource defined\n"); + err = -ENODEV; + goto err_put_clk; + } + + r = request_mem_region(r->start, resource_size(r), pdev->name); + if (!r) { + dev_err(&pdev->dev, "failed to request memory resource\n"); + err = -EBUSY; + goto err_put_clk; + } + + u2d->mmio_base = ioremap(r->start, resource_size(r)); + if (!u2d->mmio_base) { + dev_err(&pdev->dev, "ioremap() failed\n"); + err = -ENODEV; + goto err_free_res; + } + + if (pdata->init) { + err = pdata->init(&pdev->dev); + if (err) + goto err_free_io; + } + + /* Only PXA310 U2D has OTG functionality */ + if (cpu_is_pxa310()) { + err = pxa310_otg_init(pdata); + if (err) + goto err_free_plat; + } + + platform_set_drvdata(pdev, &u2d); + + return 0; + +err_free_plat: + if (pdata->exit) + pdata->exit(&pdev->dev); +err_free_io: + iounmap(u2d->mmio_base); +err_free_res: + release_mem_region(r->start, resource_size(r)); +err_put_clk: + clk_put(u2d->clk); +err_free_mem: + kfree(u2d); + return err; +} + +static int pxa3xx_u2d_remove(struct platform_device *pdev) +{ + struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data; + struct resource *r; + + if (cpu_is_pxa310()) { + pxa310_stop_otg_hc(); + pxa310_otg_exit(); + } + + if (pdata->exit) + pdata->exit(&pdev->dev); + + platform_set_drvdata(pdev, NULL); + iounmap(u2d->mmio_base); + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(r->start, resource_size(r)); + + clk_put(u2d->clk); + + kfree(u2d); + + return 0; +} + +static struct platform_driver pxa3xx_u2d_ulpi_driver = { + .driver = { + .name = "pxa3xx-u2d", + .owner = THIS_MODULE, + }, + .probe = pxa3xx_u2d_probe, + .remove = pxa3xx_u2d_remove, +}; + +static int pxa3xx_u2d_ulpi_init(void) +{ + return platform_driver_register(&pxa3xx_u2d_ulpi_driver); +} +module_init(pxa3xx_u2d_ulpi_init); + +static void __exit pxa3xx_u2d_ulpi_exit(void) +{ + platform_driver_unregister(&pxa3xx_u2d_ulpi_driver); +} +module_exit(pxa3xx_u2d_ulpi_exit); + +MODULE_DESCRIPTION("PXA3xx U2D ULPI driver"); +MODULE_AUTHOR("Igor Grinberg"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index fa0014847c71..cf2bd26dcbab 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -265,7 +265,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), - INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"), + INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL), INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), -- cgit v1.2.3 From 1b43d8eda71bc953c9005afd63952e0666169553 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 27 Jul 2010 15:07:00 +0300 Subject: ARM: pxa/cm-x300: enable USB host port2 Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 77 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index c70e6c2f4e7c..8e0b5622b277 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -50,6 +51,7 @@ #include #include #include +#include #include @@ -68,6 +70,8 @@ #define GPIO97_RTC_RD (97) #define GPIO98_RTC_IO (98) +#define GPIO_ULPI_PHY_RST (127) + static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = { /* LCD */ GPIO54_LCD_LDD_0, @@ -472,6 +476,78 @@ static void __init cm_x300_init_mmc(void) static inline void cm_x300_init_mmc(void) {} #endif +#if defined(CONFIG_PXA310_ULPI) +static struct clk *pout_clk; + +static int cm_x300_ulpi_phy_reset(void) +{ + int err; + + /* reset the PHY */ + err = gpio_request(GPIO_ULPI_PHY_RST, "ulpi reset"); + if (err) { + pr_err("%s: failed to request ULPI reset GPIO: %d\n", + __func__, err); + return err; + } + + gpio_direction_output(GPIO_ULPI_PHY_RST, 0); + msleep(10); + gpio_set_value(GPIO_ULPI_PHY_RST, 1); + msleep(10); + + gpio_free(GPIO_ULPI_PHY_RST); + + return 0; +} + +static inline int cm_x300_u2d_init(struct device *dev) +{ + int err = 0; + + if (cpu_is_pxa310()) { + /* CLK_POUT is connected to the ULPI PHY */ + pout_clk = clk_get(NULL, "CLK_POUT"); + if (IS_ERR(pout_clk)) { + err = PTR_ERR(pout_clk); + pr_err("%s: failed to get CLK_POUT: %d\n", + __func__, err); + return err; + } + clk_enable(pout_clk); + + err = cm_x300_ulpi_phy_reset(); + if (err) { + clk_disable(pout_clk); + clk_put(pout_clk); + } + } + + return err; +} + +static void cm_x300_u2d_exit(struct device *dev) +{ + if (cpu_is_pxa310()) { + clk_disable(pout_clk); + clk_put(pout_clk); + } +} + +static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = { + .ulpi_mode = ULPI_SER_6PIN, + .init = cm_x300_u2d_init, + .exit = cm_x300_u2d_exit, +}; + +static void cm_x300_init_u2d(void) +{ + pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data); +} +#else +static inline void cm_x300_init_u2d(void) {} +#endif + #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) static int cm_x300_ohci_init(struct device *dev) { @@ -754,6 +830,7 @@ static void __init cm_x300_init(void) cm_x300_init_da9030(); cm_x300_init_dm9000(); cm_x300_init_lcd(); + cm_x300_init_u2d(); cm_x300_init_ohci(); cm_x300_init_mmc(); cm_x300_init_nand(); -- cgit v1.2.3 From 6ac6b817f3f4c23c5febd960d8deb343e13af5f3 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 20 Aug 2010 15:23:59 +0800 Subject: ARM: pxa: encode IRQ number into .nr_irqs Signed-off-by: Haojian Zhuang Acked-by: Antonio Ospite Signed-off-by: Eric Miao --- arch/arm/Kconfig | 1 + arch/arm/mach-pxa/Kconfig | 21 -------------- arch/arm/mach-pxa/balloon3.c | 1 + arch/arm/mach-pxa/cm-x2xx.c | 4 +++ arch/arm/mach-pxa/eseries.c | 7 +++++ arch/arm/mach-pxa/ezx.c | 8 ++++++ arch/arm/mach-pxa/hx4700.c | 1 + arch/arm/mach-pxa/include/mach/balloon3.h | 2 ++ arch/arm/mach-pxa/include/mach/eseries-irq.h | 1 + arch/arm/mach-pxa/include/mach/hx4700.h | 1 + arch/arm/mach-pxa/include/mach/irqs.h | 42 ++-------------------------- arch/arm/mach-pxa/include/mach/littleton.h | 2 ++ arch/arm/mach-pxa/include/mach/lpd270.h | 1 + arch/arm/mach-pxa/include/mach/lubbock.h | 3 ++ arch/arm/mach-pxa/include/mach/magician.h | 2 ++ arch/arm/mach-pxa/include/mach/mainstone.h | 2 ++ arch/arm/mach-pxa/include/mach/pcm027.h | 2 ++ arch/arm/mach-pxa/include/mach/poodle.h | 2 ++ arch/arm/mach-pxa/include/mach/tosa.h | 1 + arch/arm/mach-pxa/include/mach/zeus.h | 2 ++ arch/arm/mach-pxa/include/mach/zylonite.h | 2 ++ arch/arm/mach-pxa/littleton.c | 1 + arch/arm/mach-pxa/lpd270.c | 1 + arch/arm/mach-pxa/lubbock.c | 3 +- arch/arm/mach-pxa/magician.c | 1 + arch/arm/mach-pxa/mainstone.c | 1 + arch/arm/mach-pxa/pcm027.c | 1 + arch/arm/mach-pxa/poodle.c | 1 + arch/arm/mach-pxa/stargate2.c | 3 ++ arch/arm/mach-pxa/tosa.c | 1 + arch/arm/mach-pxa/zeus.c | 1 + arch/arm/mach-pxa/zylonite.c | 1 + 32 files changed, 62 insertions(+), 61 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 88c97bc7a6f5..95ad5f913a73 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -587,6 +587,7 @@ config ARCH_PXA select GENERIC_CLOCKEVENTS select TICK_ONESHOT select PLAT_PXA + select SPARSE_IRQ help Support for Intel/Marvell's PXA2xx/PXA3xx processor line. diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 3d4926edb675..e2453dba5171 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -8,19 +8,16 @@ config ARCH_LUBBOCK bool "Intel DBPXA250 Development Platform (aka Lubbock)" select PXA25x select SA1111 - select PXA_HAVE_BOARD_IRQS config MACH_MAINSTONE bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" select PXA27x select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_ZYLONITE bool select PXA3xx select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_ZYLONITE300 bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" @@ -61,7 +58,6 @@ config ARCH_VIPER select ISA select I2C_GPIO select HAVE_PWM - select PXA_HAVE_BOARD_IRQS select PXA_HAVE_ISA_IRQS select ARCOM_PCMCIA @@ -69,7 +65,6 @@ config MACH_ARCOM_ZEUS bool "Arcom/Eurotech ZEUS SBC" select PXA27x select ISA - select PXA_HAVE_BOARD_IRQS select PXA_HAVE_ISA_IRQS select ARCOM_PCMCIA @@ -77,7 +72,6 @@ config MACH_BALLOON3 bool "Balloon 3 board" select PXA27x select IWMMXT - select PXA_HAVE_BOARD_IRQS config MACH_CSB726 bool "Enable Cogent CSB726 System On a Module" @@ -140,13 +134,11 @@ config MACH_INTELMOTE2 bool "Intel Mote 2 Platform" select PXA27x select IWMMXT - select PXA_HAVE_BOARD_IRQS config MACH_STARGATE2 bool "Intel Stargate 2 Platform" select PXA27x select IWMMXT - select PXA_HAVE_BOARD_IRQS config MACH_XCEP bool "Iskratel Electronics XCEP" @@ -206,13 +198,11 @@ config MACH_LOGICPD_PXA270 bool "LogicPD PXA270 Card Engine Development Platform" select PXA27x select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_PCM027 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" select PXA27x select IWMMXT - select PXA_HAVE_BOARD_IRQS config MACH_PCM990_BASEBOARD bool "PHYTEC PCM-990 development board" @@ -247,7 +237,6 @@ config MACH_COLIBRI_PXA270_INCOME depends on MACH_COLIBRI select PXA27x select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_COLIBRI300 bool "Toradex Colibri PXA300/310" @@ -274,7 +263,6 @@ config MACH_H4700 select PXA27x select IWMMXT select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_H5000 bool "HP iPAQ h5000" @@ -289,7 +277,6 @@ config MACH_MAGICIAN select PXA27x select IWMMXT select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_MIOA701 bool "Mitac Mio A701 Support" @@ -307,7 +294,6 @@ config PXA_EZX select PXA27x select IWMMXT select HAVE_PWM - select PXA_HAVE_BOARD_IRQS config MACH_EZX_A780 bool "Motorola EZX A780" @@ -478,7 +464,6 @@ config MACH_POODLE depends on PXA_SHARPSL select PXA25x select SHARP_LOCOMO - select PXA_HAVE_BOARD_IRQS config MACH_CORGI bool "Enable Sharp SL-C700 (Corgi) Support" @@ -523,7 +508,6 @@ config MACH_TOSA bool "Enable Sharp SL-6000x (Tosa) Support" depends on PXA_SHARPSL select PXA25x - select PXA_HAVE_BOARD_IRQS config TOSA_BT tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" @@ -552,7 +536,6 @@ config MACH_ICONTROL config ARCH_PXA_ESERIES bool "PXA based Toshiba e-series PDAs" select PXA25x - select PXA_HAVE_BOARD_IRQS config MACH_E330 bool "Toshiba e330" @@ -606,7 +589,6 @@ config MACH_ZIPIT2 bool "Zipit Z2 Handheld" select PXA27x select HAVE_PWM - select PXA_HAVE_BOARD_IRQS endmenu @@ -693,9 +675,6 @@ config SHARPSL_PM_MAX1111 select HWMON select SENSORS_MAX1111 -config PXA_HAVE_BOARD_IRQS - bool - config PXA_HAVE_ISA_IRQS bool diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index 9041340fee1d..2b81e64beb42 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -779,6 +779,7 @@ MACHINE_START(BALLOON3, "Balloon3") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = balloon3_map_io, + .nr_irqs = BALLOON3_NR_IRQS, .init_irq = balloon3_init_irq, .timer = &pxa_timer, .init_machine = balloon3_init, diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index bff6e78f033d..ad40e7b141e0 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -33,6 +33,9 @@ extern void cmx255_init(void); extern void cmx270_init(void); +/* reserve IRQs for IT8152 */ +#define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40) + /* virtual addresses for statically mapped regions */ #define CMX2XX_VIRT_BASE (0xe8000000) #define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE) @@ -514,6 +517,7 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = cmx2xx_map_io, + .nr_irqs = CMX2XX_NR_IRQS, .init_irq = cmx2xx_init_irq, .timer = &pxa_timer, .init_machine = cmx2xx_init, diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index 349212a1cbd3..4971ce119501 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -183,6 +184,7 @@ MACHINE_START(E330, "Toshiba e330") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, .init_machine = e330_init, @@ -233,6 +235,7 @@ MACHINE_START(E350, "Toshiba e350") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, .init_machine = e350_init, @@ -356,6 +359,7 @@ MACHINE_START(E400, "Toshiba e400") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, .init_machine = e400_init, @@ -545,6 +549,7 @@ MACHINE_START(E740, "Toshiba e740") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, .init_machine = e740_init, @@ -737,6 +742,7 @@ MACHINE_START(E750, "Toshiba e750") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, .init_machine = e750_init, @@ -933,6 +939,7 @@ MACHINE_START(E800, "Toshiba e800") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = ESERIES_NR_IRQS, .init_irq = pxa25x_init_irq, .fixup = eseries_fixup, .init_machine = e800_init, diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 626c82b13970..3fe61f4ac790 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -38,6 +38,8 @@ #include "devices.h" #include "generic.h" +#define EZX_NR_IRQS (IRQ_BOARD_START + 24) + #define GPIO12_A780_FLIP_LID 12 #define GPIO15_A1200_FLIP_LID 15 #define GPIO15_A910_FLIP_LID 15 @@ -800,6 +802,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = a780_init, @@ -866,6 +869,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = e680_init, @@ -932,6 +936,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = a1200_init, @@ -1124,6 +1129,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = a910_init, @@ -1190,6 +1196,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = e6_init, @@ -1230,6 +1237,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = EZX_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = e2_init, diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 848c861dd23f..10104f16e6e4 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -874,6 +874,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = HX4700_NR_IRQS, .init_irq = pxa27x_init_irq, .init_machine = hx4700_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index eec92e6fd7cf..561562b4360b 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -174,6 +174,8 @@ enum balloon3_features { #define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) #define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) +#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 4) + extern int balloon3_has(enum balloon3_features feature); #endif diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h index f2a93d5e31d3..de292b269c63 100644 --- a/arch/arm/mach-pxa/include/mach/eseries-irq.h +++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h @@ -25,3 +25,4 @@ #define TMIO_SD_IRQ IRQ_TMIO(1) #define TMIO_USB_IRQ IRQ_TMIO(2) +#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16) diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h index 9eaeed1f87f1..37408449ec25 100644 --- a/arch/arm/mach-pxa/include/mach/hx4700.h +++ b/arch/arm/mach-pxa/include/mach/hx4700.h @@ -17,6 +17,7 @@ #define HX4700_ASIC3_GPIO_BASE NR_BUILTIN_GPIO #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) +#define HX4700_NR_IRQS (IRQ_BOARD_START + 70) /* * PXA GPIOs diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index ffc8314520f2..d372caa75dc7 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -117,48 +117,12 @@ /* * The following interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use - * these. There will be 16 IRQs by default. If it is not enough, - * IRQ_BOARD_END is allowed be customized for each board, but keep - * the numbers within sensible limits and in descending order, so - * when multiple config options are selected, the maximum will be - * used. + * these. + * By default, no board IRQ is reserved. It should be finished in + * custom board since sparse IRQ is already enabled. */ #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) -#if defined(CONFIG_MACH_H4700) -#define IRQ_BOARD_END (IRQ_BOARD_START + 70) -#elif defined(CONFIG_MACH_ZYLONITE) -#define IRQ_BOARD_END (IRQ_BOARD_START + 32) -#elif defined(CONFIG_PXA_EZX) -#define IRQ_BOARD_END (IRQ_BOARD_START + 23) -#else -#define IRQ_BOARD_END (IRQ_BOARD_START + 16) -#endif - -/* - * Figure out the MAX IRQ number. - * - * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. - * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 - * Otherwise, we have the standard IRQs only. - */ -#ifdef CONFIG_SA1111 -#define NR_IRQS (IRQ_BOARD_END + 55) -#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS) -#define NR_IRQS (IRQ_BOARD_END) -#else #define NR_IRQS (IRQ_BOARD_START) -#endif - -/* add IT8152 IRQs beyond BOARD_END */ -#ifdef CONFIG_PCI_HOST_ITE8152 -#define IT8152_LAST_IRQ (IRQ_BOARD_END + 40) - -#if NR_IRQS < (IT8152_LAST_IRQ+1) -#undef NR_IRQS -#define NR_IRQS (IT8152_LAST_IRQ+1) -#endif - -#endif /* CONFIG_PCI_HOST_ITE8152 */ #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h index 6c9b21c51322..2a5726c15e0e 100644 --- a/arch/arm/mach-pxa/include/mach/littleton.h +++ b/arch/arm/mach-pxa/include/mach/littleton.h @@ -10,4 +10,6 @@ #define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) #define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) +#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8) + #endif /* __ASM_ARCH_LITTLETON_H */ diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h index 0e6440c81683..cd070092b6eb 100644 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ b/arch/arm/mach-pxa/include/mach/lpd270.h @@ -38,5 +38,6 @@ #define LPD270_USBC_IRQ LPD270_IRQ(2) #define LPD270_ETHERNET_IRQ LPD270_IRQ(3) #define LPD270_AC97_IRQ LPD270_IRQ(4) +#define LPD270_NR_IRQS (IRQ_BOARD_START + 5) #endif diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index a0d4247f08fc..2a086e8373eb 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h @@ -45,6 +45,9 @@ #define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ #define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) +#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16) +#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55) + #ifndef __ASSEMBLY__ extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); #endif diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h index 20ef37d4a9a7..0a2efcf7947c 100644 --- a/arch/arm/mach-pxa/include/mach/magician.h +++ b/arch/arm/mach-pxa/include/mach/magician.h @@ -71,6 +71,8 @@ #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) #define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) +#define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8) + /* * CPLD EGPIOs */ diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h index 86e623abd64d..4c2d11cd824d 100644 --- a/arch/arm/mach-pxa/include/mach/mainstone.h +++ b/arch/arm/mach-pxa/include/mach/mainstone.h @@ -134,4 +134,6 @@ #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) +#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16) + #endif diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h index 04083263167e..4bac588478a8 100644 --- a/arch/arm/mach-pxa/include/mach/pcm027.h +++ b/arch/arm/mach-pxa/include/mach/pcm027.h @@ -30,6 +30,8 @@ #define PCM027_MMCDET_IRQ PCM027_IRQ(2) #define PCM027_PM_5V_IRQ PCM027_IRQ(3) +#define PCM027_NR_IRQS (IRQ_BOARD_START + 32) + /* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 #define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h index 0b3e6d051c64..83d1cfd00fc9 100644 --- a/arch/arm/mach-pxa/include/mach/poodle.h +++ b/arch/arm/mach-pxa/include/mach/poodle.h @@ -85,6 +85,8 @@ #define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) #define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) +#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */ + extern struct platform_device poodle_locomo_device; #endif /* __ASM_ARCH_POODLE_H */ diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h index 1bbd1f2e4beb..1272c4b56ceb 100644 --- a/arch/arm/mach-pxa/include/mach/tosa.h +++ b/arch/arm/mach-pxa/include/mach/tosa.h @@ -20,6 +20,7 @@ /* Jacket Scoop */ #define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) +#define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS) /* * SCOOP2 internal GPIOs */ diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index 6e119976003e..faa408ab7ad7 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -15,6 +15,8 @@ #ifndef _MACH_ZEUS_H #define _MACH_ZEUS_H +#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48) + /* Physical addresses */ #define ZEUS_FLASH_PHYS PXA_CS0_PHYS #define ZEUS_ETH0_PHYS PXA_CS1_PHYS diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h index 9edf645368d6..ea24998b923c 100644 --- a/arch/arm/mach-pxa/include/mach/zylonite.h +++ b/arch/arm/mach-pxa/include/mach/zylonite.h @@ -5,6 +5,8 @@ #define EXT_GPIO(x) (128 + (x)) +#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32) + /* the following variables are processor specific and initialized * by the corresponding zylonite_pxa3xx_init() */ diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 9b9046185b00..83f3236893b3 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -441,6 +441,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto .boot_params = 0xa0000100, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = pxa_map_io, + .nr_irqs = LITTLETON_NR_IRQS, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = littleton_init, diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index d279507fc748..fc9502ef4024 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -509,6 +509,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = lpd270_map_io, + .nr_irqs = LPD270_NR_IRQS, .init_irq = lpd270_init_irq, .timer = &pxa_timer, .init_machine = lpd270_init, diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 330c3282856e..1956c23093d1 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -229,7 +229,7 @@ static struct resource sa1111_resources[] = { }; static struct sa1111_platform_data sa1111_info = { - .irq_base = IRQ_BOARD_END, + .irq_base = LUBBOCK_SA1111_IRQ_BASE, }; static struct platform_device sa1111_device = { @@ -560,6 +560,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = lubbock_map_io, + .nr_irqs = LUBBOCK_NR_IRQS, .init_irq = lubbock_init_irq, .timer = &pxa_timer, .init_machine = lubbock_init, diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index e81dd0c8e40d..42a0c2b41281 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -768,6 +768,7 @@ MACHINE_START(MAGICIAN, "HTC Magician") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .boot_params = 0xa0000100, .map_io = pxa_map_io, + .nr_irqs = MAGICIAN_NR_IRQS, .init_irq = pxa27x_init_irq, .init_machine = magician_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 5543c64da9ef..c2a8717e463d 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -628,6 +628,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") .boot_params = 0xa0000100, /* BLOB boot parameter setting */ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = mainstone_map_io, + .nr_irqs = MAINSTONE_NR_IRQS, .init_irq = mainstone_init_irq, .timer = &pxa_timer, .init_machine = mainstone_init, diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 2190af066470..90b08ba8ad1a 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -262,6 +262,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = pcm027_map_io, + .nr_irqs = PCM027_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = pcm027_init, diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 55e8fcde0141..c04e025cd790 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -469,6 +469,7 @@ MACHINE_START(POODLE, "SHARP Poodle") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_poodle, .map_io = pxa_map_io, + .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */ .init_irq = pxa25x_init_irq, .timer = &pxa_timer, .init_machine = poodle_init, diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index a654d1e6b38a..62de07341cc6 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -56,6 +56,8 @@ #include "devices.h" #include "generic.h" +#define STARGATE_NR_IRQS (IRQ_BOARD_START + 8) + /* Bluetooth */ #define SG2_BT_RESET 81 @@ -1011,6 +1013,7 @@ MACHINE_START(STARGATE2, "Stargate 2") .phys_io = 0x40000000, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = pxa_map_io, + .nr_irqs = STARGATE_NR_IRQS, .init_irq = pxa27x_init_irq, .timer = &pxa_timer, .init_machine = stargate2_init, diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 83cc3a18c2e9..3a06e98b4920 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -956,6 +956,7 @@ MACHINE_START(TOSA, "SHARP Tosa") .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .fixup = fixup_tosa, .map_io = pxa_map_io, + .nr_irqs = TOSA_NR_IRQS, .init_irq = pxa25x_init_irq, .init_machine = tosa_init, .timer = &pxa_timer, diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 03b9cb910e08..9da2b624ba20 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -904,6 +904,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc), .boot_params = 0xa0000100, .map_io = zeus_map_io, + .nr_irqs = ZEUS_NR_IRQS, .init_irq = zeus_init_irq, .timer = &pxa_timer, .init_machine = zeus_init, diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index c479cbecf784..2edad61539a8 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -415,6 +415,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") .boot_params = 0xa0000100, .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, .map_io = pxa_map_io, + .nr_irqs = ZYLONITE_NR_IRQS, .init_irq = pxa3xx_init_irq, .timer = &pxa_timer, .init_machine = zylonite_init, -- cgit v1.2.3 From 58cf68b88ce3fc48e345e756c07770e1d6e4cbe9 Mon Sep 17 00:00:00 2001 From: "Mark F. Brown" Date: Wed, 25 Aug 2010 23:51:54 -0400 Subject: ARM: pxa168: added framebuffer support code Signed-off-by: Mark F. Brown Signed-off-by: Eric Miao --- arch/arm/mach-mmp/include/mach/pxa168.h | 8 ++++++++ arch/arm/mach-mmp/pxa168.c | 3 +++ 2 files changed, 11 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 27e1bc758623..220738f9c5e0 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -10,6 +10,7 @@ extern void __init pxa168_init_irq(void); #include #include #include +#include