From 95b840afe420bb4152fde11473e7ce370b058c1b Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 5 Apr 2017 16:06:11 +0200 Subject: ARM: dts: rockchip: Setup usb vbus-supply on rk3288-rock2 Now that the rockchip usb phy has a vbus-supply property use that to control the vbus regulator on rock2. Signed-off-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-square.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index a23a94811be8..8ed25e9f60bc 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -125,10 +125,6 @@ gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; - /* Always on as the rockchip usb phy doesn't have a vbus-supply - * property - */ - regulator-always-on; regulator-name = "vcc_host"; }; @@ -279,6 +275,10 @@ status = "okay"; }; +&usbphy1 { + vbus-supply = <&vcc_usb_host>; +}; + &usb_host0_ehci { status = "okay"; }; -- cgit v1.2.3 From 96800f036813c648cdd64918399bdd6768e68273 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 17 Mar 2017 18:18:39 +0100 Subject: ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108 Rockchip finally named the SOC as RV1108, so change it for compatible. Signed-off-by: Andy Yan [adapt include in rk1108-evb.dts to not introduce errors] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk1108-evb.dts | 2 +- arch/arm/boot/dts/rk1108.dtsi | 452 --------------------------------------- arch/arm/boot/dts/rv1108.dtsi | 452 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 453 insertions(+), 453 deletions(-) delete mode 100644 arch/arm/boot/dts/rk1108.dtsi create mode 100644 arch/arm/boot/dts/rv1108.dtsi (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts index 3956cff4ca79..88fe0a8c4faa 100644 --- a/arch/arm/boot/dts/rk1108-evb.dts +++ b/arch/arm/boot/dts/rk1108-evb.dts @@ -40,7 +40,7 @@ /dts-v1/; -#include "rk1108.dtsi" +#include "rv1108.dtsi" / { model = "Rockchip RK1108 Evaluation board"; diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi deleted file mode 100644 index 1297924db6ad..000000000000 --- a/arch/arm/boot/dts/rk1108.dtsi +++ /dev/null @@ -1,452 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include -#include -/ { - #address-cells = <1>; - #size-cells = <1>; - - compatible = "rockchip,rk1108"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = ; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - bus_intmem@10080000 { - compatible = "mmio-sram"; - reg = <0x10080000 0x2000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x10080000 0x2000>; - }; - - uart2: serial@10210000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10210000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart1: serial@10220000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10220000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - status = "disabled"; - }; - - uart0: serial@10230000 { - compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - grf: syscon@10300000 { - compatible = "rockchip,rk1108-grf", "syscon"; - reg = <0x10300000 0x1000>; - }; - - pmugrf: syscon@20060000 { - compatible = "rockchip,rk1108-pmugrf", "syscon"; - reg = <0x20060000 0x1000>; - }; - - cru: clock-controller@20200000 { - compatible = "rockchip,rk1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - emmc: dwmmc@30110000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30110000 0x4000>; - status = "disabled"; - }; - - sdio: dwmmc@30120000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30120000 0x4000>; - status = "disabled"; - }; - - sdmmc: dwmmc@30130000 { - compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc"; - clock-freq-min-max = <400000 100000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - interrupts = ; - reg = <0x30130000 0x4000>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rv1108-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20030000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20030000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@10310000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10310000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@10320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10320000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@10330000 { - compatible = "rockchip,gpio-bank"; - reg = <0x10330000 0x100>; - interrupts = ; - clocks = <&xin24m>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { - drive-strength = <4>; - }; - - pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; - }; - }; - - i2c2m1 { - i2c2m1_xfer: i2c2m1-xfer { - rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; - }; - - i2c2m1_gpio: i2c2m1-gpio { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, - <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c2m05v { - i2c2m05v_xfer: i2c2m05v-xfer { - rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; - }; - - i2c2m05v_gpio: i2c2m05v-gpio { - rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, - <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_cd: sdmmc-cd { - rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts_gpio: uart0-rts-gpio { - rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, - <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, - <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, - <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart2_5v { - uart2_5v_cts: uart2_5v-cts { - rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_5v_rts: uart2_5v-rts { - rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi new file mode 100644 index 000000000000..437098b556eb --- /dev/null +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -0,0 +1,452 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1108"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + + uart2: serial@10210000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10210000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart1: serial@10220000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10220000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart0: serial@10230000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + grf: syscon@10300000 { + compatible = "rockchip,rv1108-grf", "syscon"; + reg = <0x10300000 0x1000>; + }; + + pmugrf: syscon@20060000 { + compatible = "rockchip,rv1108-pmugrf", "syscon"; + reg = <0x20060000 0x1000>; + }; + + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + emmc: dwmmc@30110000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30110000 0x4000>; + status = "disabled"; + }; + + sdio: dwmmc@30120000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30120000 0x4000>; + status = "disabled"; + }; + + sdmmc: dwmmc@30130000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 100000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + reg = <0x30130000 0x4000>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x2000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1108-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20030000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20030000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@10310000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10310000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@10320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10320000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@10330000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10330000 0x100>; + interrupts = ; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { + drive-strength = <4>; + }; + + pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; + }; + + i2c2m1_gpio: i2c2m1-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c2m05v { + i2c2m05v_xfer: i2c2m05v-xfer { + rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; + }; + + i2c2m05v_gpio: i2c2m05v-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2_5v { + uart2_5v_cts: uart2_5v-cts { + rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_5v_rts: uart2_5v-rts { + rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; -- cgit v1.2.3 From 5be21d0a0f487f779d6e1e72790852769e9d976f Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 17 Mar 2017 18:18:40 +0100 Subject: ARM: dts: rockchip: rename RK1108-evb to RV1108-evb Rockchip finally named the SOC as RV1108, so change it for compatible. The rk1108/rv1108 is completely new to the market, so there no real devices exist in the wild, only the Rockchip internal evaluation board. Therefore we're not breaking any existing devices when changing compatible values. Signed-off-by: Andy Yan Acked-by: Rob Herring [added paragraph about no real devices existing] Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 +- arch/arm/boot/dts/Makefile | 2 +- arch/arm/boot/dts/rk1108-evb.dts | 69 ---------------------- arch/arm/boot/dts/rv1108-evb.dts | 69 ++++++++++++++++++++++ 4 files changed, 72 insertions(+), 72 deletions(-) delete mode 100644 arch/arm/boot/dts/rk1108-evb.dts create mode 100644 arch/arm/boot/dts/rv1108-evb.dts (limited to 'arch/arm') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index c965d99e86c2..7b4847420ab5 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -138,9 +138,9 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; -- Rockchip RK1108 Evaluation board +- Rockchip RV1108 Evaluation board Required root node properties: - - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; + - compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; - Rockchip RK3368 evb: Required root node properties: diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9c5e1d944d1c..32537f8c9e41 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -718,7 +718,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7794-silk.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk1108-evb.dtb \ + rv1108-evb.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts deleted file mode 100644 index 88fe0a8c4faa..000000000000 --- a/arch/arm/boot/dts/rk1108-evb.dts +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; - -#include "rv1108.dtsi" - -/ { - model = "Rockchip RK1108 Evaluation board"; - compatible = "rockchip,rk1108-evb", "rockchip,rk1108"; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x08000000>; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts new file mode 100644 index 000000000000..58cf4ac079c3 --- /dev/null +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -0,0 +1,69 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Rockchip RV1108 Evaluation board"; + compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- cgit v1.2.3 From 9d420e9b4140f8938ad6aa0d29e2428a2af6122b Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Wed, 17 May 2017 17:52:24 +0800 Subject: ARM: dts: rockchip: fix rk322x i2s1 pinctrl error Refer to Chapter 5.3.2 of rk3229 TRM, we can see that GPIO1A[2,4,5] using RK_FUNC_2 not RK_FUNC_1. This patch fixes it. Signed-off-by: Sugar Zhang Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 48a0c1cf4301..cc6a27dbcc29 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -621,9 +621,9 @@ <0 12 RK_FUNC_1 &pcfg_pull_none>, <0 13 RK_FUNC_1 &pcfg_pull_none>, <0 14 RK_FUNC_1 &pcfg_pull_none>, - <1 2 RK_FUNC_1 &pcfg_pull_none>, - <1 4 RK_FUNC_1 &pcfg_pull_none>, - <1 5 RK_FUNC_1 &pcfg_pull_none>; + <1 2 RK_FUNC_2 &pcfg_pull_none>, + <1 4 RK_FUNC_2 &pcfg_pull_none>, + <1 5 RK_FUNC_2 &pcfg_pull_none>; }; }; -- cgit v1.2.3 From fa206984331b2fd5c8821f0ca63c8f0eec837f2b Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:26 +0800 Subject: ARM: dts: rockchip: add watchdog device node on rk322x Add watchdog device node for rk322x SoC. Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index cc6a27dbcc29..1b46bf81932a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -280,6 +280,14 @@ status = "disabled"; }; + wdt: watchdog@110a0000 { + compatible = "snps,dw-wdt"; + reg = <0x110a0000 0x100>; + interrupts = ; + clocks = <&cru PCLK_CPU>; + status = "disabled"; + }; + pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; -- cgit v1.2.3 From 02131477b9028720037438948047a6233e8bdb81 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:25 +0800 Subject: ARM: dts: rockchip: correct rk322x uart2 pinctrl Correct UART2 PINCTRL flag to use the correct pull up setting Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 1b46bf81932a..5300a1e765ec 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -701,7 +701,7 @@ uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, + rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, <1 19 RK_FUNC_2 &pcfg_pull_none>; }; -- cgit v1.2.3 From 738e451174d428881910b9b7558965668216ed5b Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 17 May 2017 17:52:25 +0800 Subject: ARM: dts: rockchip: add second uart2 pinctrl on rk322x Add secondary pinctrl set for UART2 which can be used to prevent conflicts with sdmmc pins. Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 5300a1e765ec..816b0796d816 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -705,6 +705,11 @@ <1 19 RK_FUNC_2 &pcfg_pull_none>; }; + uart21_xfer: uart21-xfer { + rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>, + <1 9 RK_FUNC_2 &pcfg_pull_none>; + }; + uart2_cts: uart2-cts { rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; }; -- cgit v1.2.3 From 30ee58146b53d83e90fc5326488e1e48a5a3aba4 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 17 May 2017 18:16:14 +0800 Subject: ARM: dts: rockchip: set default rates for core clocks on rk322x Set sane default frequencies for CPLL, GPLL and some other core clocks on the rk322x. Signed-off-by: Elaine Zhang Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 816b0796d816..c256df9a2cd8 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -346,8 +346,18 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru ARMCLK>, + <&cru PLL_CPLL>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>; + assigned-clock-rates = + <594000000>, <816000000>, + <500000000>, <150000000>, + <150000000>, <75000000>, + <150000000>, <150000000>, + <75000000>; }; thermal-zones { -- cgit v1.2.3 From 9f12da43c327b4eed4c7dc47a8ac37b05e39c3d0 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 17 May 2017 18:16:15 +0800 Subject: ARM: dts: rockchip: add operating-points-v2 for cpu on rk322x This patch adds a new opp table for cpu on rk322x SoC. Signed-off-by: Finley Xiao Signed-off-by: Frank Wang Acked-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index c256df9a2cd8..c09e17cc4ab0 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -66,10 +66,7 @@ compatible = "arm,cortex-a7"; reg = <0xf00>; resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; + operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; @@ -80,6 +77,7 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu2: cpu@f02 { @@ -87,6 +85,7 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu3: cpu@f03 { @@ -94,6 +93,35 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000>; }; }; -- cgit v1.2.3 From 2b3f2f37ef4d7b9f233d7dc9529b789709b6c988 Mon Sep 17 00:00:00 2001 From: Rocky Hao Date: Wed, 17 May 2017 18:16:17 +0800 Subject: ARM: dts: rockchip: set a sane frequence for tsadc on rk322x Update freq of tsadc's working clock as 32768 hz, if not set, tsadc will work at a default frequence. Signed-off-by: Rocky Hao Signed-off-by: Frank Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index c09e17cc4ab0..df574135797a 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -434,6 +434,8 @@ interrupts = ; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <32768>; resets = <&cru SRST_TSADC>; reset-names = "tsadc-apb"; pinctrl-names = "init", "default", "sleep"; -- cgit v1.2.3 From e3df026c594c77f0de1bdaa413d591b4345e4b6a Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:26 +0100 Subject: ARM: dts: rockchip: add ARM Mali GPU node for rk3288 Add Mali GPU device tree node for the rk3288 SoC, with devfreq opp table. Signed-off-by: Guillaume Tucker Tested-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index ad5d6022e95f..2484f11761ea 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -1125,6 +1126,48 @@ }; }; + gpu: mali@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + qos_gpu_r: qos@ffaa0000 { compatible = "syscon"; reg = <0xffaa0000 0x20>; -- cgit v1.2.3 From d6823b67288aad6810336b963140059721c83644 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:27 +0100 Subject: ARM: dts: rockchip: enable ARM Mali GPU on rk3288-rock2-som Add reference to the Mali GPU device tree node on the rk3288-rock2-som platform. Tested on a Radxa Rock2 Square board. Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index f0778a46bca9..749a9b86e6e2 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -113,6 +113,11 @@ tx_delay = <0x30>; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit v1.2.3 From 93dedf52894e360731de17bdd9358873b36c3e0f Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Wed, 3 May 2017 10:56:28 +0100 Subject: ARM: dts: rockchip: enable ARM Mali GPU on rk3288-firefly Add reference to the Mali GPU device tree node on rk3288-firefly. Tested on Firefly board. Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 10793ac18599..864747342e3e 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -219,6 +219,11 @@ status = "ok"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; -- cgit v1.2.3 From 08e779e59950affaec4f677b22fda6a1ab150a43 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 3 May 2017 10:56:29 +0100 Subject: ARM: dts: rockchip: enable ARM Mali GPU on rk3288-veyron Add reference to the Mali GPU device tree node on rk3288-veyron. Tested on Minnie and Jerry boards. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5d1eb0a25827..d709fa1847f9 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -161,6 +161,11 @@ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c5>; status = "okay"; -- cgit v1.2.3 From 23c0c210a1adcfca27a52808d1a0cbd807e86518 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Tue, 30 May 2017 23:52:46 +0800 Subject: ARM: dts: rockchip: add adc button for Firefly The only adc button connected to adc input is recovery button. Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly-reload.dts | 17 +++++++++++++++++ arch/arm/boot/dts/rk3288-firefly.dtsi | 13 +++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index d0b3204a4799..b11a282c334c 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -48,6 +48,19 @@ model = "Firefly-RK3288-reload"; compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -246,6 +259,10 @@ status = "okay"; }; +&saradc { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 864747342e3e..32dabae12e67 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -49,6 +49,19 @@ reg = <0 0x80000000>; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + dovdd_1v8: dovdd-1v8-regulator { compatible = "regulator-fixed"; regulator-name = "dovdd_1v8"; -- cgit v1.2.3 From 3880af4541a178b38cce0456c9afa3ab96534e90 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 2 Jun 2017 15:04:24 +0800 Subject: ARM: dts: rockchip: add usb nodes on rk322x This patch adds usb otg/host controllers and phys nodes on rk322x. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk322x.dtsi | 138 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index df574135797a..f3e4ffd9f818 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -210,8 +210,61 @@ }; grf: syscon@11000000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x11000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@760 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0760 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@800 { + compatible = "rockchip,rk3228-usb2phy"; + reg = <0x0800 0x0c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; uart0: serial@11010000 { @@ -467,6 +520,89 @@ status = "disabled"; }; + usb_otg: usb@30040000 { + compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x30040000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + g-use-dma; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@30080000 { + compatible = "generic-ehci"; + reg = <0x30080000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@300a0000 { + compatible = "generic-ohci"; + reg = <0x300a0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&u2phy0>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@300c0000 { + compatible = "generic-ehci"; + reg = <0x300c0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@300e0000 { + compatible = "generic-ohci"; + reg = <0x300e0000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host2_ehci: usb@30100000 { + compatible = "generic-ehci"; + reg = <0x30100000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + clock-names = "usbhost", "utmi"; + status = "disabled"; + }; + + usb_host2_ohci: usb@30120000 { + compatible = "generic-ohci"; + reg = <0x30120000 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST2>, <&u2phy1>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + gmac: ethernet@30200000 { compatible = "rockchip,rk3228-gmac"; reg = <0x30200000 0x10000>; -- cgit v1.2.3 From 81b61d37705173b8b9eb52c4566a8fc7c7099520 Mon Sep 17 00:00:00 2001 From: William Wu Date: Fri, 2 Jun 2017 15:04:25 +0800 Subject: ARM: dts: rockchip: enable usb for rk3229 evb board Rockchip's rk3229 evaluation board has one usb otg controller and three usb host controllers. Each usb controller connect with one usb2 phy port through UTMI+ interface. And the three usb host interfaces use the same GPIO VBUS drive. Let's enable them to support usb on rk3229 evb board. Signed-off-by: William Wu Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3229-evb.dts | 74 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts index 275092a950ef..1b55192b7d04 100644 --- a/arch/arm/boot/dts/rk3229-evb.dts +++ b/arch/arm/boot/dts/rk3229-evb.dts @@ -58,6 +58,17 @@ #clock-cells = <0>; }; + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + }; + vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -85,6 +96,69 @@ status = "okay"; }; +&pinctrl { + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &uart2 { status = "okay"; }; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_ehci { + status = "okay"; +}; + +&usb_host2_ohci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; -- cgit v1.2.3