From 47f28b41df6ba2efd05db705689617b969589168 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 27 Jun 2019 13:55:53 +0200 Subject: ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210 The PMU module of Mali400 GPU is optional and it looks that it is not present on Exynos4210, because any access to its registers causes external abort. This patch removes "pmu" interrupt for Exynos4210 SoCs, so the driver will skip the PMU module. This fixes following fault during kernel boot: Unhandled fault: imprecise external abort (0x1406) at 0x00000000 (lima_pmu_init) from [] (lima_device_init+0x244/0x5a0) (lima_device_init) from [] (lima_pdev_probe+0x7c/0xd8) (lima_pdev_probe) from [] (platform_drv_probe+0x48/0x9c) (platform_drv_probe) from [] (really_probe+0x1c4/0x400) (really_probe) from [] (driver_probe_device+0x78/0x1b8) (driver_probe_device) from [] (device_driver_attach+0x58/0x60) (device_driver_attach) from [] (__driver_attach+0xfc/0x160) (__driver_attach) from [] (bus_for_each_dev+0x68/0xb4) (bus_for_each_dev) from [] (bus_add_driver+0x104/0x20c) (bus_add_driver) from [] (driver_register+0x78/0x10c) (driver_register) from [] (do_one_initcall+0x8c/0x430) (do_one_initcall) from [] (kernel_init_freeable+0x3c8/0x4d0) (kernel_init_freeable) from [] (kernel_init+0x8/0x10c) (kernel_init) from [] (ret_from_fork+0x14/0x20) The PMU module seems to work fine on Exynos4412 SoCs, so the patch also moves the interrupt definitions to exynos4210.dtsi and exynos4412.dtsi respectively, to keep only the common part in exynos4.dtsi. Fixes: 13efd80acaa4 ("ARM: dts: exynos: Add GPU/Mali 400 node to Exynos4") Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4.dtsi | 22 ---------------------- arch/arm/boot/dts/exynos4210.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/exynos4412.dtsi | 22 ++++++++++++++++++++++ 3 files changed, 42 insertions(+), 22 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 6005cfbbed89..7863a21a7a64 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -54,28 +54,6 @@ gpu: gpu@13000000 { compatible = "samsung,exynos4210-mali", "arm,mali-400"; reg = <0x13000000 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; /* * CLK_G3D is not actually bus clock but a IP-level clock. * The bus clock is not described in hardware manual. diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 6122da368092..f220716239db 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -450,6 +450,26 @@ }; &gpu { + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; operating-points-v2 = <&gpu_opp_table>; gpu_opp_table: opp_table { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7bed6842575a..d20db2dfe8e2 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -717,6 +717,28 @@ }; &gpu { + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; operating-points-v2 = <&gpu_opp_table>; gpu_opp_table: opp_table { -- cgit v1.2.3 From 8386e6a7b07c51b8b9e2d3c0bb08e551db5c5ae5 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 27 Jun 2019 13:57:25 +0200 Subject: ARM: dts: exynos: Move Mali400 GPU node to "/soc" Mali400 GPU hardware module is a standard hardware module integrated to Exynos3210/4210/4412 SoCs, so it should reside under the "/soc" node. The only SoC components which are placed in the DT root, are those, which are a part of CPUs: like ARM architected timers and ARM performance measurement units. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 66 +++++++++++++++++++-------------------- arch/arm/boot/dts/exynos4.dtsi | 28 ++++++++--------- 2 files changed, 47 insertions(+), 47 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index c17870a54acf..5659c4a10729 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -126,39 +126,6 @@ }; }; - gpu: gpu@13000000 { - compatible = "samsung,exynos4210-mali", "arm,mali-400"; - reg = <0x13000000 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - clocks = <&cmu CLK_G3D>, - <&cmu CLK_SCLK_G3D>; - clock-names = "bus", "core"; - power-domains = <&pd_g3d>; - status = "disabled"; - /* TODO: operating points for DVFS, assigned clock as 134 MHz */ - }; - pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -495,6 +462,39 @@ status = "disabled"; }; + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + clocks = <&cmu CLK_G3D>, + <&cmu CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + /* TODO: operating points for DVFS, assigned clock as 134 MHz */ + }; + mfc: codec@13400000 { compatible = "samsung,mfc-v7"; reg = <0x13400000 0x10000>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 7863a21a7a64..1264cc431ff6 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -51,20 +51,6 @@ serial3 = &serial_3; }; - gpu: gpu@13000000 { - compatible = "samsung,exynos4210-mali", "arm,mali-400"; - reg = <0x13000000 0x10000>; - /* - * CLK_G3D is not actually bus clock but a IP-level clock. - * The bus clock is not described in hardware manual. - */ - clocks = <&clock CLK_G3D>, - <&clock CLK_SCLK_G3D>; - clock-names = "bus", "core"; - power-domains = <&pd_g3d>; - status = "disabled"; - }; - pmu: pmu { compatible = "arm,cortex-a9-pmu"; interrupt-parent = <&combiner>; @@ -429,6 +415,20 @@ }; }; + gpu: gpu@13000000 { + compatible = "samsung,exynos4210-mali", "arm,mali-400"; + reg = <0x13000000 0x10000>; + /* + * CLK_G3D is not actually bus clock but a IP-level clock. + * The bus clock is not described in hardware manual. + */ + clocks = <&clock CLK_G3D>, + <&clock CLK_SCLK_G3D>; + clock-names = "bus", "core"; + power-domains = <&pd_g3d>; + status = "disabled"; + }; + i2s1: i2s@13960000 { compatible = "samsung,s3c6410-i2s"; reg = <0x13960000 0x100>; -- cgit v1.2.3 From a19a209ee420f95626451034ba287c33d0d64ce0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jun 2019 13:47:38 +0200 Subject: ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family The datasheet of S2MPS11 PMIC is slightly non-consistent in buck[78] voltage regulators values. 1. The voltage tables for configuring their registers mention range of voltages: 0.750 V to 3.55 V, 2. The constrains in electrical specifications say output voltage range to be different (buck7: 1.2 V to 1.5 V, buck8: 1.8 V to 2.1 V). Adjust the ranges to match the electrical specifications to stay on the safe side. Also change the name of regulators to match reality. Anyway these regulators stay at default value so this should not have effect. Reported-by: Anand Moon Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 9843d21d6924..829147e320e0 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -551,17 +551,17 @@ }; buck7_reg: BUCK7 { - regulator-name = "vdd_1.0v_ldo"; - regulator-min-microvolt = <800000>; + regulator-name = "vdd_1.35v_ldo"; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; }; buck8_reg: BUCK8 { - regulator-name = "vdd_1.8v_ldo"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2.0v_ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; regulator-always-on; regulator-boot-on; }; -- cgit v1.2.3 From 841ed60264b3d37d5bf3e32cff168920e4923f88 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 29 Jun 2019 13:47:39 +0200 Subject: ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa The datasheet of S2MPS11 PMIC is slightly non-consistent in buck[78] voltage regulators values. 1. The voltage tables for configuring their registers mention range of voltages: 0.750 V to 3.55 V, 2. The constrains in electrical specifications say output voltage range to be different (buck7: 1.2 V to 1.5 V, buck8: 1.8 V to 2.1 V). Adjust the ranges to match the electrical specifications to stay on the safe side. Anyway these regulators stay at default value so this should not have effect. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index ac7f2fa0ba22..592d7b45ecc8 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -723,15 +723,15 @@ buck7_reg: BUCK7 { regulator-name = "VIN_LLDO_1V4"; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-always-on; }; buck8_reg: BUCK8 { regulator-name = "VIN_MLDO_2V0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; regulator-always-on; }; -- cgit v1.2.3