From 4a183020d35c6100095605e2c4a47b80f6e301f3 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 21 Jul 2020 12:43:43 +0530 Subject: arm64: dts: qcom: sdm845: Support ETMv4 power management Add "arm,coresight-loses-context-with-cpu" property to coresight ETM nodes to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by: Mathieu Poirier Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20200721071343.2898-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e506793407d8..0b5f063dcaea 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3016,6 +3016,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3035,6 +3036,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3054,6 +3056,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3073,6 +3076,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3092,6 +3096,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3111,6 +3116,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3130,6 +3136,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -3149,6 +3156,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; out-ports { port { -- cgit v1.2.3 From d3d245aee0b149b5e3034b8790c9d7688526fc70 Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Tue, 21 Jul 2020 13:14:49 +0530 Subject: arm64: dts: qcom: sc7180: Add maximum speed property for DWC3 USB node Adding maximum speed property for DWC3 USB node which can be used for setting interconnect bandwidth. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1595317489-18432-3-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 16df08d9ef8f..3fe759b68c87 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2656,6 +2656,7 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; }; }; -- cgit v1.2.3 From be45eac21294845ca56694377fe20b36f119718f Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Fri, 10 Jul 2020 07:35:20 -0700 Subject: arm64: dts: qcom: sc7180: Add properties to qfprom for fuse blowing This patch adds properties to the qfprom node to enable fuse blowing. Signed-off-by: Ravi Kumar Bokka Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20200710073439.v5.4.I70c17309f8b433e900656d7c53a2e6b61888bb68@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 4 ++++ arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 26cc4913d3dd..d8b550723b32 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -288,6 +288,10 @@ }; }; +&qfprom { + vcc-supply = <&vreg_l11a_1p8>; +}; + &qspi { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3fe759b68c87..65614e66575c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -658,9 +658,15 @@ #power-domain-cells = <1>; }; - qfprom@784000 { + qfprom: efuse@784000 { compatible = "qcom,qfprom"; - reg = <0 0x00784000 0 0x8ff>; + reg = <0 0x00784000 0 0x8ff>, + <0 0x00780000 0 0x7a0>, + <0 0x00782000 0 0x100>, + <0 0x00786000 0 0x1fff>; + + clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; + clock-names = "core"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 072ce1722684f3da8e16bc1ee6471a2a8affb9bd Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 9 Jun 2020 19:00:28 +0530 Subject: arm64: dts: qcom: sc7180: Add support to skip powering up of ETM Add "qcom,skip-power-up" property to skip powering up ETM on SC7180 SoC to workaround a hardware errata where CPU watchdog counter is stopped when ETM power up bit is set (i.e., when TRCPDCR.PU = 1). Reviewed-by: Mathieu Poirier Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/8c5ff297d8c89d9d451352f189baf26c8938842a.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 65614e66575c..7097907a8379 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2226,6 +2226,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2245,6 +2246,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2264,6 +2266,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2283,6 +2286,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2302,6 +2306,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2321,6 +2326,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2340,6 +2346,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { @@ -2359,6 +2366,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; out-ports { port { -- cgit v1.2.3 From 015156e689aa1f0c836f9ef4d342b6f6897afd74 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 9 Jun 2020 19:00:29 +0530 Subject: arm64: dts: qcom: sc7180: Add iommus property to ETR Define iommus property for Coresight ETR component in SC7180 SoC with the SID and mask to enable SMMU translation for this master. Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/2312c9a10e7251d69e31e4f51c0f1d70e6f2f2f5.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 7097907a8379..9ad6752c57f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2127,6 +2127,7 @@ etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; + iommus = <&apps_smmu 0x04a0 0x20>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; -- cgit v1.2.3 From 8aa6ac22e52693173a71b3e58cb9f361b0bd6d3c Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 9 Jun 2020 19:00:30 +0530 Subject: arm64: dts: qcom: sc7180: Add support for context losing replicator Add "qcom,replicator-loses-context" property to the replicator in Always-on domain in SC7180 SoC to enable coresight replicator driver to handle this variation of replicator designs. Reviewed-by: Mathieu Poirier Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/5072d94849cfaee46748d26ac997212fb2d783c2.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 9ad6752c57f7..5688cbb96bdd 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2200,6 +2200,7 @@ clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + qcom,replicator-loses-context; out-ports { port { -- cgit v1.2.3 From 338bdbcc598a7c2228739f41c697f126c9db384c Mon Sep 17 00:00:00 2001 From: Sharat Masetty Date: Fri, 17 Jul 2020 18:59:37 +0530 Subject: arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/1594992579-20662-5-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0b5f063dcaea..2884577dcb77 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4007,42 +4007,52 @@ qcom,gmu = <&gmu>; + interconnects = <&mem_noc MASTER_GFX3D &mem_noc SLAVE_EBI1>; + interconnect-names = "gfx-mem"; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-710000000 { opp-hz = /bits/ 64 <710000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-596000000 { opp-hz = /bits/ 64 <596000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-520000000 { opp-hz = /bits/ 64 <520000000>; opp-level = ; + opp-peak-kBps = <6220000>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = ; + opp-peak-kBps = <4068000>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = ; + opp-peak-kBps = <2724000>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-peak-kBps = <1648000>; }; }; }; -- cgit v1.2.3 From dd7dc299f303f215bb7ab9b2105ee50f591e5013 Mon Sep 17 00:00:00 2001 From: Sharat Masetty Date: Fri, 17 Jul 2020 18:59:38 +0530 Subject: arm64: dts: qcom: sc7180: Add interconnects property for GPU This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/1594992579-20662-6-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 5688cbb96bdd..3255d3768cc0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1886,6 +1886,9 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; + interconnect-names = "gfx-mem"; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; -- cgit v1.2.3 From c8c6c187d05876c41d5c2ed09a2a13077f38ae1f Mon Sep 17 00:00:00 2001 From: Sharat Masetty Date: Fri, 17 Jul 2020 18:59:39 +0530 Subject: arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty Reviewed-by: Matthias Kaehlcke Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/1594992579-20662-7-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3255d3768cc0..d46b3833e52f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1895,36 +1895,43 @@ opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-level = ; + opp-peak-kBps = <8532000>; }; opp-650000000 { opp-hz = /bits/ 64 <650000000>; opp-level = ; + opp-peak-kBps = <7216000>; }; opp-565000000 { opp-hz = /bits/ 64 <565000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-430000000 { opp-hz = /bits/ 64 <430000000>; opp-level = ; + opp-peak-kBps = <5412000>; }; opp-355000000 { opp-hz = /bits/ 64 <355000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-level = ; + opp-peak-kBps = <3072000>; }; opp-180000000 { opp-hz = /bits/ 64 <180000000>; opp-level = ; + opp-peak-kBps = <1804000>; }; }; }; -- cgit v1.2.3 From f30ac26def181e655d1f1d40b9ec2c9e3b333bb5 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Thu, 9 Jul 2020 09:52:44 -0400 Subject: arm64: dts: qcom: add sm8150 GPU nodes This brings up the GPU. Tested on HDK855 by running vulkan CTS. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200709135251.643-14-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 135 +++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 7a0c5b419ff0..b86a7ead3006 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -547,6 +547,141 @@ }; }; + gpu: gpu@2c00000 { + /* + * note: the amd,imageon compatible makes it possible + * to use the drm/msm driver without the display node, + * make sure to remove it when display node is added + */ + compatible = "qcom,adreno-640.1", + "qcom,adreno", + "amd,imageon"; + #stream-id-cells = <16>; + + reg = <0 0x02c00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x401>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + /* note: downstream checks gpu binning for 675 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-level = ; + }; + + opp-585000000 { + opp-hz = /bits/ 64 <585000000>; + opp-level = ; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-level = ; + }; + + opp-427000000 { + opp-hz = /bits/ 64 <427000000>; + opp-level = ; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + opp-level = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@2c6a000 { + compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; + + reg = <0 0x02c6a000 0 0x30000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc 0>, + <&gpucc 3>, + <&gpucc 6>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc 0>, + <&gpucc 1>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sm8150-gpucc"; + reg = <0 0x02c90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@2ca0000 { + compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + reg = <0 0x02ca0000 0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&gpucc 0>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc 0>; + }; + tlmm: pinctrl@3100000 { compatible = "qcom,sm8150-pinctrl"; reg = <0x0 0x03100000 0x0 0x300000>, -- cgit v1.2.3 From 04a3605b184e151744b6adecd1a60654e46f3d2e Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Thu, 9 Jul 2020 09:52:45 -0400 Subject: arm64: dts: qcom: add sm8250 GPU nodes This brings up the GPU. Tested on HDK865 by running vulkan CTS. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200709135251.643-15-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 142 +++++++++++++++++++++++++++++++++++ 1 file changed, 142 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 551a3cef356e..377172e8967b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1047,6 +1047,148 @@ #hwlock-cells = <1>; }; + gpu: gpu@3d00000 { + /* + * note: the amd,imageon compatible makes it possible + * to use the drm/msm driver without the display node, + * make sure to remove it when display node is added + */ + compatible = "qcom,adreno-650.2", + "qcom,adreno", + "amd,imageon"; + #stream-id-cells = <16>; + + reg = <0 0x03d00000 0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x401>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + zap-shader { + memory-region = <&gpu_mem>; + }; + + /* note: downstream checks gpu binning for 670 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + opp-level = ; + }; + + opp-587000000 { + opp-hz = /bits/ 64 <587000000>; + opp-level = ; + }; + + opp-525000000 { + opp-hz = /bits/ 64 <525000000>; + opp-level = ; + }; + + opp-490000000 { + opp-hz = /bits/ 64 <490000000>; + opp-level = ; + }; + + opp-441600000 { + opp-hz = /bits/ 64 <441600000>; + opp-level = ; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-level = ; + }; + + opp-305000000 { + opp-hz = /bits/ 64 <305000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; + + reg = <0 0x03d6a000 0 0x30000>, + <0 0x3de0000 0 0x10000>, + <0 0xb290000 0 0x10000>, + <0 0xb490000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc 0>, + <&gpucc 3>, + <&gpucc 6>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&gpucc 0>, + <&gpucc 1>; + power-domain-names = "cx", "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8250-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc 0>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", "bus", "iface"; + + power-domains = <&gpucc 0>; + }; + slpi: remoteproc@5c00000 { compatible = "qcom,sm8250-slpi-pas"; reg = <0 0x05c00000 0 0x4000>; -- cgit v1.2.3 From aef9a119dfb91706a71399ca39f61dfe79bdc027 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 27 Jul 2020 13:25:32 +0530 Subject: arm64: dts: qcom: sdm845-db845c: Add hdmi bridge nodes Enable MDSS and DSI and add the LT9611 HDMI bridge. Also add the HDMI audio nodes. Signed-off-by: Bjorn Andersson Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20200727075532.1932134-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 118 +++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index c00797bd3b07..a2a98680ccf5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -74,6 +74,17 @@ }; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + lt9611_1v8: lt9611-vdd18-regulator { compatible = "regulator-fixed"; regulator-name = "LT9611_1V8"; @@ -382,6 +393,25 @@ firmware-name = "qcom/sdm845/cdsp.mdt"; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &gcc { protected-clocks = , , @@ -395,6 +425,48 @@ }; }; +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + lt9611_codec: hdmi-bridge@3b { + compatible = "lontium,lt9611"; + reg = <0x3b>; + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v8>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin>, <&dsi_sw_sel>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + port@1 { + reg = <1>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +}; + &i2c11 { /* On Low speed expansion */ label = "LS-I2C1"; @@ -407,6 +479,14 @@ status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; @@ -612,6 +692,21 @@ }; }; + hdmi-dai-link { + link-name = "HDMI Playback"; + cpu { + sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <<9611_codec 0>; + }; + }; + slim-dai-link { link-name = "SLIM Playback"; cpu { @@ -686,6 +781,21 @@ }; }; + dsi_sw_sel: dsi-sw-sel { + pins = "gpio120"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + output-high; + }; + + lt9611_irq_pin: lt9611-irq { + pins = "gpio84"; + function = "gpio"; + bias-disable; + }; + pcie0_default_state: pcie0-default { clkreq { pins = "gpio36"; @@ -943,6 +1053,14 @@ }; }; +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + &qup_uart6_default { pinmux { pins = "gpio45", "gpio46", "gpio47", "gpio48"; -- cgit v1.2.3 From e4faf75d6c2465dc878acaeb1c22cd87a308c2f1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 24 Jun 2020 17:01:00 +0200 Subject: arm64: dts: qcom: msm8994: Add SCM node Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200624150107.76234-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 1d1ae6f9ba1b..4e23ec38ebb3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -142,6 +142,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-msm8994", "qcom,scm"; + }; + }; + memory { device_type = "memory"; /* We expect the bootloader to fill in the reg */ -- cgit v1.2.3 From 95087f61639e2c167752f05eeed7b7e87876c417 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 24 Jun 2020 17:01:01 +0200 Subject: arm64: dts: qcom: msm8992: Add a label to rpm-requests This enables the node to be referenced directly from other DTs. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200624150107.76234-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 2021795c99ad..8e5a3ae79997 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -258,7 +258,7 @@ qcom,local-pid = <0>; qcom,remote-pid = <6>; - rpm-requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8994"; qcom,smd-channels = "rpm_requests"; -- cgit v1.2.3 From 01104518b4162ba889c0ca7eb8f882cbad865171 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 24 Jun 2020 17:01:04 +0200 Subject: arm64: dts: qcom: msm8994: Add support for SMD RPM Add support for SMD RPM, including pm8994 and pmi8994 regulators. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200624150107.76234-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 4e23ec38ebb3..6707f898607f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -175,9 +175,31 @@ }; }; + smd { + compatible = "qcom,smd"; + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + qcom,local-pid = <0>; + qcom,remote-pid = <6>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8994"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: rpmcc { + compatible = "qcom,rpmcc-msm8994"; + #clock-cells = <1>; + }; + }; + }; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; hwlocks = <&tcsr_mutex 3>; }; @@ -196,6 +218,12 @@ <0xf9002000 0x1000>; }; + apcs: mailbox@f900d000 { + compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; + reg = <0xf900d000 0x2000>; + #mbox-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -449,6 +477,11 @@ reg = <0xfc400000 0x2000>; }; + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + restart@fc4ab000 { compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; @@ -666,5 +699,15 @@ , ; }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; }; -- cgit v1.2.3 From f007210d96be51700d7dce2ccaeedb15e01ce33d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 24 Jun 2020 17:01:02 +0200 Subject: arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead. This was the only device using that dtsi, so no point keeping it separate AND with a confusing name (bullhead is based on msm8992 and the file contains regulator values for that specific board). Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200624150107.76234-8-konradybcio@gmail.com [bjorn: Squashed with change that remove regulators from msm8992.dtsi] Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 225 ++++++++++++++++- arch/arm64/boot/dts/qcom/msm8992.dtsi | 46 ---- arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi | 268 --------------------- 3 files changed, 224 insertions(+), 315 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index 32670d5afdd6..a2de69292d28 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -47,4 +47,227 @@ }; }; -#include "msm8994-smd-rpm.dtsi" +&rpm_requests { + pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_l1-supply = <&pm8994_s1>; + vdd_l2_26_28-supply = <&pm8994_s3>; + vdd_l3_11-supply = <&pm8994_s3>; + vdd_l4_27_31-supply = <&pm8994_s3>; + vdd_l5_7-supply = <&pm8994_s3>; + vdd_l6_12_32-supply = <&pm8994_s5>; + vdd_l8_16_30-supply = <&vreg_vph_pwr>; + vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; + vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; + vdd_l14_15-supply = <&pm8994_s5>; + vdd_l17_29-supply = <&vreg_vph_pwr>; + vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; + vdd_lvs1_2 = <&pm8994_s4>; + + pm8994_s1: s1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + pm8994_s2: s2 { + /* TODO */ + }; + + pm8994_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8994_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-system-load = <325000>; + }; + + pm8994_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8994_s7: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l2: l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + pm8994_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8994_l5: l5 { + /* TODO */ + }; + + pm8994_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l7: l7 { + /* TODO */ + }; + + pm8994_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l11: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8994_l14: l14 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l18: l18 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8994_l19: l19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <570000>; + }; + + pm8994_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8994_l22: l22 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + }; + + pm8994_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8994_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3150000>; + }; + + pm8994_l25: l25 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l26: l26 { + /* TODO: value from downstream + regulator-min-microvolt = <987500>; + fails to apply */ + }; + + pm8994_l27: l27 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8994_l28: l28 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l29: l29 { + /* TODO: Unsupported voltage range. + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2800000>; + */ + }; + + pm8994_l30: l30 { + /* TODO: get this verified + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + */ + }; + + pm8994_l31: l31 { + regulator-min-microvolt = <1262500>; + regulator-max-microvolt = <1262500>; + }; + + pm8994_l32: l32 { + /* TODO: get this verified + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 8e5a3ae79997..d41ba1ef687a 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -261,52 +261,6 @@ rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8994"; qcom,smd-channels = "rpm_requests"; - - pm8994-regulators { - compatible = "qcom,rpm-pm8994-regulators"; - - pm8994_s1: s1 {}; - pm8994_s2: s2 {}; - pm8994_s3: s3 {}; - pm8994_s4: s4 {}; - pm8994_s5: s5 {}; - pm8994_s6: s6 {}; - pm8994_s7: s7 {}; - - pm8994_l1: l1 {}; - pm8994_l2: l2 {}; - pm8994_l3: l3 {}; - pm8994_l4: l4 {}; - pm8994_l6: l6 {}; - pm8994_l8: l8 {}; - pm8994_l9: l9 {}; - pm8994_l10: l10 {}; - pm8994_l11: l11 {}; - pm8994_l12: l12 {}; - pm8994_l13: l13 {}; - pm8994_l14: l14 {}; - pm8994_l15: l15 {}; - pm8994_l16: l16 {}; - pm8994_l17: l17 {}; - pm8994_l18: l18 {}; - pm8994_l19: l19 {}; - pm8994_l20: l20 {}; - pm8994_l21: l21 {}; - pm8994_l22: l22 {}; - pm8994_l23: l23 {}; - pm8994_l24: l24 {}; - pm8994_l25: l25 {}; - pm8994_l26: l26 {}; - pm8994_l27: l27 {}; - pm8994_l28: l28 {}; - pm8994_l29: l29 {}; - pm8994_l30: l30 {}; - pm8994_l31: l31 {}; - pm8994_l32: l32 {}; - - pm8994_lvs1: lvs1 {}; - pm8994_lvs2: lvs2 {}; - }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi b/arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi deleted file mode 100644 index 31e3eb6ab515..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8994-smd-rpm.dtsi +++ /dev/null @@ -1,268 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015, LGE Inc. All rights reserved. - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - */ - -&smd_rpm { - rpm { - rpm_requests { - pm8994-regulators { - - vdd_l1-supply = <&pm8994_s1>; - vdd_l2_26_28-supply = <&pm8994_s3>; - vdd_l3_11-supply = <&pm8994_s3>; - vdd_l4_27_31-supply = <&pm8994_s3>; - vdd_l5_7-supply = <&pm8994_s3>; - vdd_l6_12_32-supply = <&pm8994_s5>; - vdd_l8_16_30-supply = <&vreg_vph_pwr>; - vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; - vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; - vdd_l14_15-supply = <&pm8994_s5>; - vdd_l17_29-supply = <&vreg_vph_pwr>; - vdd_l20_21-supply = <&vreg_vph_pwr>; - vdd_l25-supply = <&pm8994_s5>; - vdd_lvs1_2 = <&pm8994_s4>; - - s1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - s2 { - /* TODO */ - }; - - s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-allow-set-load; - regulator-system-load = <325000>; - }; - - s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - s7 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - l1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - l2 { - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - - l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l5 { - /* TODO */ - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - /* TODO */ - }; - - l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - }; - - l11 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - proxy-supply = <&pm8994_l12>; - qcom,proxy-consumer-enable; - qcom,proxy-consumer-current = <10000>; - status = "okay"; - }; - - l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - qcom,init-voltage = <2950000>; - status = "okay"; - }; - - l14 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - qcom,init-voltage = <1200000>; - proxy-supply = <&pm8994_l14>; - qcom,proxy-consumer-enable; - qcom,proxy-consumer-current = <10000>; - status = "okay"; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - status = "okay"; - }; - - l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - qcom,init-voltage = <2700000>; - status = "okay"; - }; - - l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - qcom,init-voltage = <2700000>; - status = "okay"; - }; - - l18 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - qcom,init-voltage = <3000000>; - qcom,init-ldo-mode = <1>; - }; - - l19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - status = "okay"; - }; - - l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; - regulator-system-load = <570000>; - }; - - l21 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - qcom,init-voltage = <1800000>; - }; - - l22 { - regulator-min-microvolt = <3100000>; - regulator-max-microvolt = <3100000>; - qcom,init-voltage = <3100000>; - }; - - l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - }; - - l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3150000>; - qcom,init-voltage = <3075000>; - }; - - l25 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - }; - - l26 { - /* TODO: value from downstream - regulator-min-microvolt = <987500>; - fails to apply */ - }; - - l27 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - qcom,init-voltage = <1050000>; - }; - - l28 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - qcom,init-voltage = <1000000>; - proxy-supply = <&pm8994_l28>; - qcom,proxy-consumer-enable; - qcom,proxy-consumer-current = <10000>; - }; - - l29 { - /* TODO: Unsupported voltage range. - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,init-voltage = <2800000>; - */ - }; - - l30 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - - l31 { - regulator-min-microvolt = <1262500>; - regulator-max-microvolt = <1262500>; - qcom,init-voltage = <1262500>; - }; - - l32 { - /* TODO: get this verified - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,init-voltage = <1800000>; - */ - }; - }; - }; - }; -}; -- cgit v1.2.3 From 551969ad9b6d6b6a69750edb3bec50ed07741d1c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 24 Jun 2020 17:01:06 +0200 Subject: arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW) Add device tree support for the Sony Xperia Z5 smartphone. It's based on Sony Kitakami platform (msm8994) and hence a Kitakami-common DTSI has been created so as to reduce clutter when remaining devices are added. The board currently supports * Serial * SDHCI * I2C * Regulator configuration * pstore log dump * GPIO keys Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200624150107.76234-9-konradybcio@gmail.com [bjorn: Changed vendor identifier in board compatible from somc to sony] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/msm8994-sony-xperia-kitakami-sumire.dts | 13 ++ .../dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 235 +++++++++++++++++++++ 3 files changed, 249 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c98bafe03a96..1ea25cefe48b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts new file mode 100644 index 000000000000..5d6bbbf6c119 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994-sony-xperia-kitakami.dtsi" + +/ { + model = "Sony Xperia Z5"; + compatible = "sony,sumire-row", "qcom,msm8994"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi new file mode 100644 index 000000000000..4032b7478f04 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +#include "msm8994.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include +#include + +/ { + /* required for bootloader to select correct board */ + qcom,msm-id = <0xcf 0x20001>; + qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>; + qcom,board-id = <8 0>; + + /* Kitakami firmware doesn't support PSCI */ + /delete-node/ psci; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@0 { + label = "Volume Down"; + gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + button@1 { + label = "Volume Up"; + gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + button@2 { + label = "Camera Snapshot"; + gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + button@3 { + label = "Camera Focus"; + gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* This is for getting crash logs using Android downstream kernels */ + ramoops@1fe00000 { + compatible = "ramoops"; + reg = <0x0 0x1fe00000 0x0 0x200000>; + console-size = <0x100000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x80000>; + }; + + continuous_splash: framebuffer@3401000{ + reg = <0x0 0x3401000 0x0 0x2200000>; + no-map; + }; + + dfps_data_mem: dfps_data_mem@3400000 { + reg = <0x0 0x3400000 0x0 0x1000>; + no-map; + }; + + peripheral_region: peripheral_region@7400000 { + reg = <0x0 0x7400000 0x0 0x1c00000>; + no-map; + }; + + modem_region: modem_region@9000000 { + reg = <0x0 0x9000000 0x0 0x5a00000>; + no-map; + }; + + tzapp: modem_region@ea00000 { + reg = <0x0 0xea00000 0x0 0x1900000>; + no-map; + }; + + fb_region: fb_region@40000000 { + reg = <0x00 0x40000000 0x00 0x1000000>; + no-map; + }; + }; +}; + +&blsp_spi0 { + status = "okay"; + + /* FPC fingerprint reader */ +}; + +/* I2C1 is disabled on this board */ + +&blsp_i2c2 { + status = "okay"; + + /* NXP NFC */ +}; + +&blsp_i2c4 { + status = "okay"; + + /* Empty but active */ +}; + +&blsp_i2c5 { + status = "okay"; + + /* SMB1357 charger and sii8620 HDMI/MHL bridge */ +}; + +&blsp_i2c6 { + status = "okay"; + + /* Synaptics touchscreen */ +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&rpm_requests { + pm8994_regulators: pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + vdd_l1-supply = <&pm8994_s1>; + vdd_l2_26_28-supply = <&pm8994_s3>; + vdd_l3_11-supply = <&pm8994_s3>; + vdd_l4_27_31-supply = <&pm8994_s3>; + vdd_l5_7-supply = <&pm8994_s3>; + vdd_l6_12_32-supply = <&pm8994_s5>; + vdd_l8_16_30-supply = <&vreg_vph_pwr>; + vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; + vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; + vdd_l14_15-supply = <&pm8994_s5>; + vdd_l17_29-supply = <&vreg_vph_pwr>; + vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; + vdd_lvs1_2 = <&pm8994_s4>; + + pm8994_s1: s1 {}; + pm8994_s2: s2 {}; + pm8994_s3: s3 {}; + pm8994_s4: s4 {}; + pm8994_s5: s5 {}; + pm8994_s6: s6 {}; + pm8994_s7: s7 {}; + + pm8994_l1: l1 {}; + pm8994_l2: l2 {}; + pm8994_l3: l3 {}; + pm8994_l4: l4 {}; + pm8994_l6: l6 {}; + pm8994_l8: l8 {}; + pm8994_l9: l9 {}; + pm8994_l10: l10 {}; + pm8994_l11: l11 {}; + pm8994_l12: l12 {}; + pm8994_l13: l13 {}; + pm8994_l14: l14 {}; + pm8994_l15: l15 {}; + pm8994_l16: l16 {}; + pm8994_l17: l17 {}; + pm8994_l18: l18 {}; + pm8994_l19: l19 {}; + pm8994_l20: l20 {}; + pm8994_l21: l21 {}; + pm8994_l22: l22 {}; + pm8994_l23: l23 {}; + pm8994_l24: l24 {}; + pm8994_l25: l25 {}; + pm8994_l26: l26 {}; + pm8994_l27: l27 {}; + pm8994_l28: l28 {}; + pm8994_l29: l29 {}; + pm8994_l30: l30 {}; + pm8994_l31: l31 {}; + pm8994_l32: l32 {}; + + pm8994_lvs1: lvs1 {}; + pm8994_lvs2: lvs2 {}; + }; + + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + pmi8994_s1: s1 {}; + pmi8994_s2: s2 {}; + pmi8994_s3: s3 {}; + pmi8994_bby: boost-bypass {}; + }; +}; + +&sdhc1 { + status = "okay"; + + /* Downstream pushes 2.95V to the sdhci device, + * but upstream driver REALLY wants to make vmmc 1.8v + * cause of the hs400-1_8v mode. MMC works fine without + * that regulator, so let's not use it for now. + * vqmmc is also disabled cause driver stll complains. + * + * vmmc-supply = <&pm8994_l20>; + * vqmmc-supply = <&pm8994_s4>; + */ +}; -- cgit v1.2.3 From d99c1c2a1acb7f0b56fdf0e8db36d4983d36a578 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:05 +0200 Subject: arm64: dts: qcom: msm8992: Modernize the DTS style Following changes have been made: - remove name, compatible and msm-id - wrap clocks in clocks{} - order nodes by name and by address - clock_gcc -> gcc - msmgpio -> tlmm - retire msm8992-pins.dtsi - add some of the missing pins - make comments C-style - make apcs a mailbox Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-2-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 90 ----------- arch/arm64/boot/dts/qcom/msm8992.dtsi | 246 ++++++++++++++++++++--------- 2 files changed, 168 insertions(+), 168 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi deleted file mode 100644 index c543c718c22d..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8992-pins.dtsi +++ /dev/null @@ -1,90 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. - */ - -&msmgpio { - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - function = "blsp_uart2"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart2_sleep: blsp1_uart2_sleep { - pinmux { - function = "gpio"; - pins = "gpio4", "gpio5"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - /* 0-3 for sdc1 4-6 for sdc2 */ - /* Order of pins */ - /* SDC1: CLK -> 0, CMD -> 1, DATA -> 2, RCLK -> 3 */ - /* SDC2: CLK -> 4, CMD -> 5, DATA -> 6 */ - sdc1_clk_on: clk-on { - pinconf { - pins = "sdc1_clk"; - bias-disable = <0>; /* No pull */ - drive-strength = <16>; /* 16mA */ - }; - }; - - sdc1_clk_off: clk-off { - pinconf { - pins = "sdc1_clk"; - bias-disable = <0>; /* No pull */ - drive-strength = <2>; /* 2mA */ - }; - }; - - sdc1_cmd_on: cmd-on { - pinconf { - pins = "sdc1_cmd"; - bias-pull-up; - drive-strength = <8>; - }; - }; - - sdc1_cmd_off: cmd-off { - pinconf { - pins = "sdc1_cmd"; - bias-pull-up = <0x3>; /* same as 3.10 ?? */ - drive-strength = <2>; /* 2mA */ - }; - }; - - sdc1_data_on: data-on { - pinconf { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <8>; /* 8mA */ - }; - }; - - sdc1_data_off: data-off { - pinconf { - pins = "sdc1_data"; - bias-pull-up; - drive-strength = <2>; - }; - }; - - sdc1_rclk_on: rclk-on { - bias-pull-down; /* pull down */ - }; - - sdc1_rclk_off: rclk-off { - bias-pull-down; /* pull down */ - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index d41ba1ef687a..43b2e4cd26f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -6,10 +6,6 @@ #include / { - model = "Qualcomm Technologies, Inc. MSM 8992"; - compatible = "qcom,msm8992"; - // msm-id needed by bootloader for selecting correct blob - qcom,msm-id = <251 0>, <252 0>; interrupt-parent = <&intc>; #address-cells = <2>; @@ -40,35 +36,35 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; }; - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - status = "okay"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - regulator-always-on; + smem_region: smem@6a00000 { + reg = <0x0 0x6a00000 0x0 0x200000>; + no-map; + }; }; sfpb_mutex: hwmutex { @@ -98,9 +94,10 @@ <0xf9002000 0x1000>; }; - apcs: syscon@f900d000 { - compatible = "syscon"; + apcs: mailbox@f900d000 { + compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; reg = <0xf900d000 0x2000>; + #mbox-cells = <1>; }; timer@f9020000 { @@ -161,40 +158,6 @@ }; }; - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - gpio-ranges = <&msmgpio 0 0 146>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - blsp1_uart2: serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = ; - status = "disabled"; - clock-names = "core", "iface"; - clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>; - }; - - clock_gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8994"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x2000>; - }; - sdhci1: mmc@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; @@ -204,8 +167,8 @@ ; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>, - <&clock_gcc GCC_SDCC1_AHB_CLK>; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; @@ -220,32 +183,141 @@ status = "okay"; }; + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + status = "disabled"; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8994"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x2000>; + }; + rpm_msg_ram: memory@fc428000 { compatible = "qcom,rpm-msg-ram"; reg = <0xfc428000 0x4000>; }; + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + sfpb_mutex_regs: syscon@fd484000 { #address-cells = <1>; #size-cells = <1>; compatible = "syscon"; reg = <0xfd484000 0x400>; }; - }; - memory { - device_type = "memory"; - reg = <0 0 0 0>; // bootloader will update - }; + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; + blsp1_uart2_default: blsp1-uart2-default { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; - smem_region: smem@6a00000 { - reg = <0x0 0x6a00000 0x0 0x200000>; - no-map; + blsp1_uart2_sleep: blsp1-uart2-sleep { + function = "gpio"; + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc1_clk_on: clk-on { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <6>; + }; + + sdc1_clk_off: clk-off { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc1_cmd_on: cmd-on { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <6>; + }; + + sdc1_cmd_off: cmd-off { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc1_data_on: data-on { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <6>; + }; + + sdc1_data_off: data-off { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc1_rclk_on: rclk-on { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: rclk-off { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + i2c2_default: i2c2-default { + function = "blsp_i2c2"; + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep { + function = "gpio"; + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + + i2c6_default: i2c6-default { + function = "blsp_i2c6"; + pins = "gpio28", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + + i2c6_sleep: i2c6-sleep { + function = "gpio"; + pins = "gpio28", "gpio27"; + drive-strength = <2>; + bias-disable; + }; }; }; @@ -264,6 +336,24 @@ }; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; }; -#include "msm8992-pins.dtsi" -- cgit v1.2.3 From c83e0951bcad645df15b348ebb43e34b687baf78 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:06 +0200 Subject: arm64: dts: qcom: msm8992: Fix SDHCI1 This commit ensures the correct IRQ type is set and disables the device by default. The mmc-hs400-1_8v property is also moved to Bullhead as it might not be present on all boards. The node has been renamed to sdhci@ instead of mmc@ and the phandle was changed to sdhc_1 to comply with the newer DTS style. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts | 6 ++++++ arch/arm64/boot/dts/qcom/msm8992.dtsi | 16 +++++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index a2de69292d28..1061fd5404aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -271,3 +271,9 @@ }; }; }; + +&sdhc_1 { + status = "okay"; + + mmc-hs400-1_8v; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 43b2e4cd26f0..8ef1cb8ba8ef 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -158,18 +158,19 @@ }; }; - sdhci1: mmc@f9824900 { + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on @@ -179,8 +180,9 @@ regulator-always-on; bus-width = <8>; - mmc-hs400-1_8v; - status = "okay"; + non-removable; + + status = "disabled"; }; blsp1_uart2: serial@f991e000 { -- cgit v1.2.3 From 4acc8d64e56e70d0af319d7decafad2ad4e10f58 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:07 +0200 Subject: arm64: dts: qcom: bullhead: Add qcom,msm-id Add the property required for the bootloader to select the correct device tree blob. It has been removed from the SoC device tree as it should be set on a per-device basis. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index 1061fd5404aa..4f70681e730d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -11,6 +11,7 @@ model = "LG Nexus 5X"; compatible = "lg,bullhead", "qcom,msm8992"; /* required for bootloader to select correct board */ + qcom,msm-id = <251 0>, <252 0>; qcom,board-id = <0xb64 0>; qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; -- cgit v1.2.3 From d54df2210d2fc41fa094a415faa801be6d350d77 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:08 +0200 Subject: arm64: dts: qcom: bullhead: Move UART pinctrl to SoC This pinout is common for every 8992-based device and should therefore reside in the SoC device tree. Also convert addresses into phandles. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts index 4f70681e730d..5969b5cfdc85 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -23,15 +23,6 @@ stdout-path = "serial0:115200n8"; }; - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -48,6 +39,10 @@ }; }; +&blsp1_uart2 { + status = "okay"; +}; + &rpm_requests { pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; -- cgit v1.2.3 From 2912215f53919645da7149670d731729faba77fd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:09 +0200 Subject: arm64: dts: qcom: msm8992: Add a proper CPU map This commit adds cpu nodes for all 6 cores present on this SoC and the cpu-map. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 82 ++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 8ef1cb8ba8ef..f780cd39ded6 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -16,24 +16,92 @@ cpus { #address-cells = <2>; #size-cells = <0>; - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - }; - }; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; next-level-cache = <&L2_0>; + enable-method = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; }; }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + next-level-cache = <&L2_1>; + enable-method = "psci"; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + next-level-cache = <&L2_1>; + enable-method = "psci"; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + }; + }; }; clocks { -- cgit v1.2.3 From be577b8125f89af549111a648ed66d63b29c666d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:10 +0200 Subject: arm64: dts: qcom: msm8992: Add a SCM node Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index f780cd39ded6..aee33ed61858 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -118,6 +118,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-msm8994", "qcom,scm"; + }; + }; + memory { device_type = "memory"; /* We expect the bootloader to fill in the reg */ -- cgit v1.2.3 From ce13edfb7bfe1c9cf8d43c00fcdc49f4439b4341 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:11 +0200 Subject: arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index aee33ed61858..acce7be22e50 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -290,6 +290,22 @@ reg = <0xfc4ab000 0x4>; }; + spmi_bus: spmi@fc4c0000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xfc4cf000 0x1000>, + <0xfc4cb000 0x1000>, + <0xfc4ca000 0x1000>; + reg-names = "core", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + sfpb_mutex_regs: syscon@fd484000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 7f8bcc0c4cfec4ea0340a4fc1e39f55126ebbece Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:12 +0200 Subject: arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes Add support for I2C to enable support for peripherals such as touchscreens or sensors. Also add BLSP_UART2 interface. Please note that the naming scheme follows downstream and as abominable as it is, that's what we get. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 153 ++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index acce7be22e50..e8b801813f14 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -272,6 +272,101 @@ status = "disabled"; }; + blsp_i2c2: i2c@f9924000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9924000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Somebody was very creative with their numbering scheme downstream... */ + + blsp_i2c13: i2c@f9927000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9927000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c13_default>; + pinctrl-1 = <&i2c13_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@f9928000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9928000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_uart2: serial@f995e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995e000 0x1000>; + interrupt = ; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_default>; + pinctrl-1 = <&blsp2_uart2_sleep>; + status = "disabled"; + }; + + blsp_i2c7: i2c@f9963000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9963000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c7_default>; + pinctrl-1 = <&i2c7_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c5: i2c@f9967000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9967000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8994"; #clock-cells = <1>; @@ -337,6 +432,20 @@ bias-pull-down; }; + blsp2_uart2_default: blsp2-uart2-default { + function = "blsp_uart8"; + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_uart2_sleep: blsp2-uart2-sleep { + function = "gpio"; + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-down; + }; + sdc1_clk_on: clk-on { pins = "sdc1_clk"; bias-disable; @@ -397,6 +506,21 @@ bias-disable; }; + i2c5_default: i2c5-default { + /* Don't be fooled! Nobody knows the reason why though... */ + function = "blsp_i2c11"; + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep { + function = "gpio"; + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + i2c6_default: i2c6-default { function = "blsp_i2c6"; pins = "gpio28", "gpio27"; @@ -410,6 +534,35 @@ drive-strength = <2>; bias-disable; }; + + i2c7_default: i2c7-default { + function = "blsp_i2c7"; + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + + i2c7_sleep: i2c7-sleep { + function = "gpio"; + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + + i2c13_default: i2c13-default { + /* Not a typo either. */ + function = "blsp_i2c5"; + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + + i2c13_sleep: i2c13-sleep { + function = "gpio"; + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; }; }; -- cgit v1.2.3 From 0835375212681cdf26d120a4fb792ed524f24447 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:13 +0200 Subject: arm64: dts: qcom: msm8992: Add PMU node Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index e8b801813f14..c4c9a108ae1e 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -130,6 +130,11 @@ reg = <0 0 0 0>; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 329e16d5f8fcdcbe323c0f01c37f8fbba22d21d2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:14 +0200 Subject: arm64: dts: qcom: msm8992: Add PSCI support. This SoC's firmware does not fully support the PSCI spec, but it's good enough to bring the cores up. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index c4c9a108ae1e..bc3acc0cf9bf 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -135,6 +135,11 @@ interrupts = ; }; + psci { + compatible = "arm,psci-0.2"; + method = "hvc"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 75c8a10d9c19938313ed670bbbcdd80ef178732e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:15 +0200 Subject: arm64: dts: qcom: msm8992: Add RPMCC node This lets us use clocks provided by RPM. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-12-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index bc3acc0cf9bf..188fff2095f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -588,6 +588,11 @@ rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8994"; qcom,smd-channels = "rpm_requests"; + + rpmcc: rpmcc { + compatible = "qcom,rpmcc-msm8992"; + #clock-cells = <1>; + }; }; }; }; -- cgit v1.2.3 From 0f5cdb31e850e113af341a9f05e3b7b0d732b866 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:16 +0200 Subject: arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree This commit adds support for the Xiaomi Libra (Mi 4C) smartphone. It's based on the Qualcomm msm8992 SoC. It currently supports: * Screen console from bootloader * SDHCI * Regulator configuration * Serial console * I2C Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-13-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 364 ++++++++++++++++++++++ 2 files changed, 365 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1ea25cefe48b..cf1b576e4f6c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts new file mode 100644 index 000000000000..4f64ca3ea1ef --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8992.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include +#include + +/ { + model = "Xiaomi Mi 4C"; + compatible = "xiaomi,libra", "qcom,msm8992"; + /* required for bootloader to select correct board */ + qcom,msm-id = <251 0 252 0>; + qcom,pmic-id = <65545 65546 0 0>; + qcom,board-id = <12 0>; + + /* This enables graphical output via bootloader-enabled display */ + chosen { + bootargs = "earlycon=tty0 console=tty0"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@3404000 { + status= "okay"; + compatible = "simple-framebuffer"; + reg = <0 0x3404000 0 (1080 * 1920 * 3)>; + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@0 { + label = "Volume Up"; + gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* This is for getting crash logs using Android downstream kernels */ + ramoops@dfc00000 { + compatible = "ramoops"; + reg = <0x0 0xdfc00000 0x0 0x40000>; + console-size = <0x10000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + }; + + continuous_splash: framebuffer@3401000{ + reg = <0x0 0x3401000 0x0 0x2200000>; + no-map; + }; + + dfps_data_mem: dfps_data_mem@3400000 { + reg = <0x0 0x3400000 0x0 0x1000>; + no-map; + }; + + peripheral_region: peripheral_region@7400000 { + reg = <0x0 0x7400000 0x0 0x1c00000>; + no-map; + }; + + modem_region: modem_region@9000000 { + reg = <0x0 0x9000000 0x0 0x5a00000>; + no-map; + }; + + tzapp: modem_region@ea00000 { + reg = <0x0 0xea00000 0x0 0x1900000>; + no-map; + }; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + /* Atmel or Synaptics touchscreen */ +}; + +&blsp_i2c5 { + status = "okay"; + + /* Silabs si4705 FM transmitter */ +}; + +&blsp_i2c6 { + status = "okay"; + + /* NCI NFC, + * TI USB320 Type-C controller, + * Pericom 30216a USB (de)mux switch + */ +}; + +&blsp_i2c7 { + status = "okay"; + + /* cm36686 proximity and ambient light sensor */ +}; + +&blsp_i2c13 { + status = "okay"; + + /* ST lsm6db0 gyro/accelerometer */ +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&rpm_requests { + pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_l1-supply = <&pm8994_s7>; + vdd_l2_26_28-supply = <&pm8994_s3>; + vdd_l3_11-supply = <&pm8994_s3>; + vdd_l4_27_31-supply = <&pm8994_s3>; + vdd_l5_7-supply = <&pm8994_s3>; + vdd_l6_12_32-supply = <&pm8994_s5>; + vdd_l8_16_30-supply = <&vreg_vph_pwr>; + vdd_l9_10_18_22-supply = <&vreg_vph_pwr>; + vdd_l13_19_23_24-supply = <&vreg_vph_pwr>; + vdd_l14_15-supply = <&pm8994_s5>; + vdd_l17_29-supply = <&vreg_vph_pwr>; + vdd_l20_21-supply = <&vreg_vph_pwr>; + vdd_l25-supply = <&pm8994_s5>; + vdd_lvs1_2 = <&pm8994_s4>; + + pm8994_s1: s1 { + /* unused */ + status = "disabled"; + }; + + pm8994_s2: s2 { + /* unused */ + status = "disabled"; + }; + + pm8994_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8994_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-system-load = <325000>; + }; + + pm8994_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8994_s7: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l2: l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + pm8994_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8994_l5: l5 { + /* unused */ + status = "disabled"; + }; + + pm8994_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l7: l7 { + /* unused */ + status = "disabled"; + }; + + pm8994_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l11: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8994_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8994_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8994_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8994_l19: l19 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8994_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-set-load; + regulator-system-load = <570000>; + }; + + pm8994_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-always-on; + }; + + pm8994_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8994_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8994_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3150000>; + }; + + pm8994_l25: l25 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l26: l26 { + regulator-min-microvolt = <987500>; + regulator-max-microvolt = <987500>; + + }; + + pm8994_l27: l27 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8994_l28: l28 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8994_l29: l29 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8994_l30: l30 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8994_l31: l31 { + regulator-min-microvolt = <1262500>; + regulator-max-microvolt = <1262500>; + }; + + pm8994_l32: l32 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + + mmc-hs400-1_8v; + vmmc-supply = <&pm8994_l20>; + vqmmc-supply = <&pm8994_s4>; +}; -- cgit v1.2.3 From 9d56a1c21f1caf52ca4f6f578e98a0503aa8001d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2020 20:21:17 +0200 Subject: arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree Add device tree support for the Microsoft Lumia 950 smartphone. It is based on msm8992 and supports booting Linux via a custom EDK2 port. Currently it supports: * Screen console via EFIFB * Booting via EFI_STUB * SDHCI * I2C * PSCI core bringup Please note that there is an implementation of EL2 startup on this board, but it requires the user to resign from PSCI and use spin-table instead. This revision sticks with PSCI. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200625182118.131476-14-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8992-msft-lumia-talkman.dts | 39 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cf1b576e4f6c..d8f1466e6758 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts new file mode 100644 index 000000000000..3cc01f02219d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8992.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include +#include + +/ { + model = "Microsoft Lumia 950"; + compatible = "microsoft,talkman", "qcom,msm8992"; + + /* Most Lumia 950 users use GRUB to load their kernels, + * hence there is no need for msm-id and friends. + */ + + /* This enables graphical output via bootloader-enabled display. + * acpi=no is required due to WP platforms having ACPI support, but + * only for Windows-based OSes. + */ + chosen { + bootargs = "earlycon=efifb console=efifb acpi=no"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&sdhc_1 { + status = "okay"; + + mmc-hs200-1_8v; +}; -- cgit v1.2.3