From f03ad7f6c5ca38242d9d23e6d1c087c43b66e481 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Mar 2018 17:19:23 +0100 Subject: ARM64: dts: marvell: armada-cp110: Add registers clock for USB host nodes This extra clock is needed to access the registers of the USB host controller used on Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "usb: host: xhci-plat: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 355bb295e4d9..c35368d2a4cd 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -211,7 +211,9 @@ reg = <0x500000 0x4000>; dma-coherent; interrupts = ; - clocks = <&CP110_LABEL(clk) 1 22>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 22>, + <&CP110_LABEL(clk) 1 16>; status = "disabled"; }; @@ -221,7 +223,9 @@ reg = <0x510000 0x4000>; dma-coherent; interrupts = ; - clocks = <&CP110_LABEL(clk) 1 23>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 23>, + <&CP110_LABEL(clk) 1 16>; status = "disabled"; }; -- cgit v1.2.3 From f1ebfab99df1032166c531cd48f8f942d10fe190 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Mar 2018 17:19:24 +0100 Subject: ARM64: dts: marvell: armada-cp110: Add registers clock for XOR engine nodes This extra clock is needed to access the registers of the XOR engine controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "dmaengine: mv_xor_v2: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index c35368d2a4cd..a51c553b5120 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -244,7 +244,9 @@ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&CP110_LABEL(clk) 1 8>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 8>, + <&CP110_LABEL(clk) 1 14>; }; CP110_LABEL(xor1): xor@6c0000 { @@ -252,7 +254,9 @@ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&CP110_LABEL(clk) 1 7>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 7>, + <&CP110_LABEL(clk) 1 14>; }; CP110_LABEL(spi0): spi@700600 { -- cgit v1.2.3 From cc4d5aed829a08c64240f43a9dc3a471989c6054 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Mar 2018 17:19:25 +0100 Subject: ARM64: dts: marvell: armada-cp110: Add registers clock for the trng node This extra clock is needed to access the registers of the harware RNG used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "hwrng: omap - Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index a51c553b5120..c491adc90b8c 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -375,7 +375,9 @@ "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; interrupts = ; - clocks = <&CP110_LABEL(clk) 1 25>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 25>, + <&CP110_LABEL(clk) 1 17>; status = "okay"; }; -- cgit v1.2.3 From 3c7f7f1503d20b14e22f64c27dc13522f5d60707 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Mar 2018 17:19:26 +0100 Subject: ARM64: dts: marvell: armada-cp110: Add registers clock for the crypto node This extra clock is needed to access the registers of the safexcel EIP97 used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "crypto: inside-secure - fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index c491adc90b8c..b6947fcb8ce6 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -402,7 +402,9 @@ ; interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; - clocks = <&CP110_LABEL(clk) 1 26>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 26>, + <&CP110_LABEL(clk) 1 17>; dma-coherent; }; }; -- cgit v1.2.3 From ef04faf106c430c3f830f93f3b2fb652b5537d7a Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Mar 2018 17:19:27 +0100 Subject: ARM64: dts: marvell: armada-cp110: Add registers clock for the NAND node This extra clock is needed to access the registers of the NAND controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "mtd: nand: marvell: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index b6947fcb8ce6..9ffb86b9441e 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -365,7 +365,9 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&CP110_LABEL(clk) 1 2>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 2>, + <&CP110_LABEL(clk) 1 17>; marvell,system-controller = <&CP110_LABEL(syscon0)>; status = "disabled"; }; -- cgit v1.2.3 From b15c9d3550767d87d07d894e374e16bf8570ed9a Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 14 Mar 2018 17:19:28 +0100 Subject: ARM64: dts: marvell: armada-cp110: Add registers clock for the PCIe nodes This extra clock is needed to access the registers of the PCIe host controller used on CP110 component of the Armada 7K/8K SoCs. This follow the changes already made in the binding documentation (as well as in the driver): "PCI: armada8k: Fix clock resource by adding a register clock" Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index 9ffb86b9441e..48cad7919efa 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -433,7 +433,8 @@ interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = ; num-lanes = <1>; - clocks = <&CP110_LABEL(clk) 1 13>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>; status = "disabled"; }; @@ -460,7 +461,8 @@ interrupts = ; num-lanes = <1>; - clocks = <&CP110_LABEL(clk) 1 11>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>; status = "disabled"; }; @@ -487,7 +489,8 @@ interrupts = ; num-lanes = <1>; - clocks = <&CP110_LABEL(clk) 1 12>; + clock-names = "core", "reg"; + clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>; status = "disabled"; }; }; -- cgit v1.2.3 From 003456f564205ca3c3b8b4c9f9c22a0846d81fd7 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 16 Mar 2018 11:01:24 +0100 Subject: arm64: dts: armada-3720-espressobin: Document URL for schematic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The schematic of the espressobin is publicly available, add a comment where to find it. Signed-off-by: Uwe Kleine-König Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 31efd6a96e9d..ef7fd2ca2515 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -6,6 +6,9 @@ * Romain Perier * */ +/* + * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf + */ /dts-v1/; -- cgit v1.2.3