From 52b3dc559a4c240c33c58affdf8247bab485d422 Mon Sep 17 00:00:00 2001 From: James Morse Date: Wed, 30 Nov 2022 17:16:03 +0000 Subject: arm64/sysreg: Standardise naming for ID_ISAR0_EL1 To convert the 32bit id registers to use the sysreg generation, they must first have a regular pattern, to match the symbols the script generates. Ensure symbols for the ID_ISAR0_EL1 register have an _EL1 suffix, and use lower-case for feature names where the arm-arm does the same. To functional change. Signed-off-by: James Morse Link: https://lore.kernel.org/r/20221130171637.718182-5-james.morse@arm.com Signed-off-by: Will Deacon --- arch/arm64/include/asm/sysreg.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm64/include/asm/sysreg.h') diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7a719c9804fc..4dc80e00a467 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -710,13 +710,13 @@ #define ID_DFR1_MTPMU_SHIFT 0 -#define ID_ISAR0_DIVIDE_SHIFT 24 -#define ID_ISAR0_DEBUG_SHIFT 20 -#define ID_ISAR0_COPROC_SHIFT 16 -#define ID_ISAR0_CMPBRANCH_SHIFT 12 -#define ID_ISAR0_BITFIELD_SHIFT 8 -#define ID_ISAR0_BITCOUNT_SHIFT 4 -#define ID_ISAR0_SWAP_SHIFT 0 +#define ID_ISAR0_EL1_Divide_SHIFT 24 +#define ID_ISAR0_EL1_Debug_SHIFT 20 +#define ID_ISAR0_EL1_Coproc_SHIFT 16 +#define ID_ISAR0_EL1_CmpBranch_SHIFT 12 +#define ID_ISAR0_EL1_BitField_SHIFT 8 +#define ID_ISAR0_EL1_BitCount_SHIFT 4 +#define ID_ISAR0_EL1_Swap_SHIFT 0 #define ID_ISAR5_RDM_SHIFT 24 #define ID_ISAR5_CRC32_SHIFT 16 -- cgit v1.2.3