From 0b6f7014adc1cc12c7c3ba988594514602919eca Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 20 Oct 2019 15:42:28 +0200 Subject: arm64: dts: allwinner: h6: add USB3 device nodes Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and a custom PHY. Add device tree nodes for them. Signed-off-by: Ondrej Jirman Signed-off-by: Icenowy Zheng Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64/boot/dts') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 4abfed2e9ff6..8f3f81725fb7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -570,6 +570,38 @@ status = "disabled"; }; + dwc3: dwc3@5200000 { + compatible = "snps,dwc3"; + reg = <0x05200000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_XHCI>, + <&ccu CLK_BUS_XHCI>, + <&rtc 0>; + clock-names = "ref", "bus_early", "suspend"; + resets = <&ccu RST_BUS_XHCI>; + /* + * The datasheet of the chip doesn't declare the + * peripheral function, and there's no boards known + * to have a USB Type-B port routed to the port. + * In addition, no one has tested the peripheral + * function yet. + * So set the dr_mode to "host" in the DTSI file. + */ + dr_mode = "host"; + phys = <&usb3phy>; + phy-names = "usb3-phy"; + status = "disabled"; + }; + + usb3phy: phy@5210000 { + compatible = "allwinner,sun50i-h6-usb3-phy"; + reg = <0x5210000 0x10000>; + clocks = <&ccu CLK_USB_PHY1>; + resets = <&ccu RST_USB_PHY1>; + #phy-cells = <0>; + status = "disabled"; + }; + ehci3: usb@5311000 { compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; reg = <0x05311000 0x100>; -- cgit v1.2.3