From 195f140318a9510f27078847796461498384c862 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Fri, 4 Oct 2019 11:01:13 +0200 Subject: arm64: dts: meson: g12b: add cooling properties Add missing #colling-cells field for G12B SoC Add cooling-map for passive and hot trip point Tested-by: Christian Hewitt Tested-by: Kevin Hilman Reviewed-by: Neil Armstrong Reviewed-by: Amit Kucheria Signed-off-by: Guillaume La Roque Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts/amlogic/meson-g12b.dtsi') diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index b3f9e3a02963..6dbc3968045b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -50,6 +50,7 @@ enable-method = "psci"; capacity-dmips-mhz = <592>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -59,6 +60,7 @@ enable-method = "psci"; capacity-dmips-mhz = <592>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu100: cpu@100 { @@ -68,6 +70,7 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu101: cpu@101 { @@ -77,6 +80,7 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu102: cpu@102 { @@ -86,6 +90,7 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu103: cpu@103 { @@ -95,6 +100,7 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; + #cooling-cells = <2>; }; l2: l2-cache0 { -- cgit v1.2.3