From 15eb169bfec291faf25b158cfa9842b72f7803ad Mon Sep 17 00:00:00 2001 From: Pawel Moll Date: Fri, 20 May 2011 14:39:29 +0100 Subject: ARM: proc: add Cortex-A5 proc info This patch adds processor info for ARM Ltd. Cortex A5, which has SCU initialisation procedure identical to A9. Signed-off-by: Pawel Moll Signed-off-by: Will Deacon --- arch/arm/mm/proc-v7.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/mm/proc-v7.S') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index a759ccafeaca..3185da27a537 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -278,6 +278,7 @@ cpu_resume_l1_flags: * It is assumed that: * - cache type register is implemented */ +__v7_ca5mp_setup: __v7_ca9mp_setup: #ifdef CONFIG_SMP ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @@ -443,6 +444,16 @@ __v7_setup_stack: .long v7_cache_fns .endm + /* + * ARM Ltd. Cortex A5 processor. + */ + .type __v7_ca5mp_proc_info, #object +__v7_ca5mp_proc_info: + .long 0x410fc050 + .long 0xff0ffff0 + __v7_proc __v7_ca5mp_setup + .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info + /* * ARM Ltd. Cortex A9 processor. */ -- cgit v1.2.3