From cdcb5a074cd3e33e7bdb318487fde8a9e55d6159 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Thu, 21 Nov 2013 11:40:13 +0900 Subject: ARM: tegra: switch FUSE clock on before usage FUSE clock is enabled by most bootloaders, but we cannot expect it to be on in all contexts (e.g. kexec). Ensure the FUSE clock is enabled before any of its registers is touched. Since FUSE is touched very early during system boot (before the clock devices are registered), directly manipulate the clock register bit in case the clock device cannot be acquired. Signed-off-by: Alexandre Courbot Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/fuse.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index d4639c506622..d610a408c0e0 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "fuse.h" @@ -54,6 +55,7 @@ int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ int tegra_soc_speedo_id; enum tegra_revision tegra_revision; +static struct clk *fuse_clk; static int tegra_fuse_spare_bit; static void (*tegra_init_speedo_data)(void); @@ -77,6 +79,22 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { [TEGRA_REVISION_A04] = "A04", }; +static void tegra_fuse_enable_clk(void) +{ + if (IS_ERR(fuse_clk)) + fuse_clk = clk_get_sys(NULL, "fuse"); + if (IS_ERR(fuse_clk)) + return; + clk_prepare_enable(fuse_clk); +} + +static void tegra_fuse_disable_clk(void) +{ + if (IS_ERR(fuse_clk)) + return; + clk_disable_unprepare(fuse_clk); +} + u32 tegra_fuse_readl(unsigned long offset) { return tegra_apb_readl(TEGRA_FUSE_BASE + offset); @@ -84,7 +102,15 @@ u32 tegra_fuse_readl(unsigned long offset) bool tegra_spare_fuse(int bit) { - return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); + bool ret; + + tegra_fuse_enable_clk(); + + ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); + + tegra_fuse_disable_clk(); + + return ret; } static enum tegra_revision tegra_get_revision(u32 id) @@ -113,10 +139,14 @@ static void tegra_get_process_id(void) { u32 reg; + tegra_fuse_enable_clk(); + reg = tegra_fuse_readl(tegra_fuse_spare_bit); tegra_cpu_process_id = (reg >> 6) & 3; reg = tegra_fuse_readl(tegra_fuse_spare_bit); tegra_core_process_id = (reg >> 12) & 3; + + tegra_fuse_disable_clk(); } u32 tegra_read_chipid(void) @@ -159,6 +189,15 @@ void __init tegra_init_fuse(void) reg |= 1 << 28; writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); + /* + * Enable FUSE clock. This needs to be hardcoded because the clock + * subsystem is not active during early boot. + */ + reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14)); + reg |= 1 << 7; + writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14)); + fuse_clk = ERR_PTR(-EINVAL); + reg = tegra_fuse_readl(FUSE_SKU_INFO); randomness[0] = reg; tegra_sku_id = reg & 0xFF; -- cgit v1.2.3 From 2f1d70af28a94988c1e8fba2ae03d4c7e68e690b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 5 Nov 2013 14:10:53 -0700 Subject: ARM: tegra: don't hard-code DEBUG_LL baud rate Stop writing to the UART clock divider registers in the Tegra DEBUG_LL code. This allows the DEBUG_LL output to use whatever baud rate was set up by the bootloader. Some users are using higher rates than 115200. This removes the only usage of tegra_uart_config[3], so reduce the size allocated for that array. Finally, fix busyuart() so that it only waits for THRE and not TEMT. For some reason, TEMT doesn't get asserted (at least on Tegra30 Beaver) at 9600 baud, even though it does at 115200 baud. This sounds like a HW bug, but I haven't investigated. For reference, U-Boot's serial code has always only checked THRE, and not checked TEMT. Signed-off-by: Stephen Warren Tested-by: Paul Walmsley Reviewed-by: Thierry Reding --- arch/arm/include/debug/tegra.S | 30 +++--------------------------- arch/arm/mach-tegra/tegra.c | 4 +--- 2 files changed, 4 insertions(+), 30 deletions(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index a7b7cedef1a6..f98763f0bc17 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -156,28 +156,6 @@ 92: and \rv, \rp, #0xffffff @ offset within 1MB section add \rv, \rv, #UART_VIRTUAL_BASE str \rv, [\tmp, #8] @ Store in tegra_uart_virt - movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff - movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16 - ldr \rv, [\rv, #0] @ Load HIDREV - ubfx \rv, \rv, #8, #8 @ 15:8 are SoC version - cmp \rv, #0x20 @ Tegra20? - moveq \rv, #0x75 @ Tegra20 divisor - movne \rv, #0xdd @ Tegra30 divisor - str \rv, [\tmp, #12] @ Save divisor to scratch - /* uart[UART_LCR] = UART_LCR_WLEN8 | UART_LCR_DLAB; */ - mov \rv, #UART_LCR_WLEN8 | UART_LCR_DLAB - str \rv, [\rp, #UART_LCR << UART_SHIFT] - /* uart[UART_DLL] = div & 0xff; */ - ldr \rv, [\tmp, #12] - and \rv, \rv, #0xff - str \rv, [\rp, #UART_DLL << UART_SHIFT] - /* uart[UART_DLM] = div >> 8; */ - ldr \rv, [\tmp, #12] - lsr \rv, \rv, #8 - str \rv, [\rp, #UART_DLM << UART_SHIFT] - /* uart[UART_LCR] = UART_LCR_WLEN8; */ - mov \rv, #UART_LCR_WLEN8 - str \rv, [\rp, #UART_LCR << UART_SHIFT] b 100f .align @@ -205,8 +183,8 @@ cmp \rx, #0 beq 1002f 1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] - and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE - teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + and \rd, \rd, #UART_LSR_THRE + teq \rd, #UART_LSR_THRE bne 1001b 1002: .endm @@ -225,7 +203,7 @@ /* * Storage for the state maintained by the macros above. * - * In the kernel proper, this data is located in arch/arm/mach-tegra/common.c. + * In the kernel proper, this data is located in arch/arm/mach-tegra/tegra.c. * That's because this header is included from multiple files, and we only * want a single copy of the data. In particular, the UART probing code above * assumes it's running using physical addresses. This is true when this file @@ -247,6 +225,4 @@ tegra_uart_config: .word 0 /* Debug UART virtual address */ .word 0 - /* Scratch space for debug macro */ - .word 0 #endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 73368176c6e8..ea14d380fc0c 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -60,15 +60,13 @@ * kernel is loaded. The data is declared here rather than debug-macro.S so * that multiple inclusions of debug-macro.S point at the same data. */ -u32 tegra_uart_config[4] = { +u32 tegra_uart_config[3] = { /* Debug UART initialization required */ 1, /* Debug UART physical address */ 0, /* Debug UART virtual address */ 0, - /* Scratch space for debug macro */ - 0, }; static void __init tegra_init_cache(void) -- cgit v1.2.3 From 6dee8200b794a83c0fb144878fdf0ac52af28835 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 29 Oct 2013 13:47:21 -0600 Subject: ARM: tegra: use section-sized static mappings for LPAE too The static mappings for Tegra's PPSB and APB regions were sized at 1MB in order to allow mapping via sections in order to avoid burning RAM for PTEs. On LPAE, sections are 2MB, so the static mappings need to be larger in order to gain the same benefit. Set IO_{PPSB,APB}_SIZE to SECTION_SIZE so this adjusts automatically. While we're fiddling with iomap.h, compress IO_{IRAM,CPU}_VIRT together to save virtual address space in the vmalloc region; these two regions are mapped using PTEs. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/mach-tegra/iomap.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index 26b1c2ad0ceb..ee79808e93a3 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -19,6 +19,7 @@ #ifndef __MACH_TEGRA_IOMAP_H #define __MACH_TEGRA_IOMAP_H +#include #include #define TEGRA_IRAM_BASE 0x40000000 @@ -115,27 +116,26 @@ * two 256MB io windows (that actually only use about 64KB * at the start of each). * - * We will just map the first 1MB of each window (to minimize + * We will just map the first MMU section of each window (to minimize * pt entries needed) and provide a macro to transform physical * io addresses to an appropriate void __iomem *. - * */ #define IO_IRAM_PHYS 0x40000000 #define IO_IRAM_VIRT IOMEM(0xFE400000) #define IO_IRAM_SIZE SZ_256K -#define IO_CPU_PHYS 0x50040000 -#define IO_CPU_VIRT IOMEM(0xFE000000) +#define IO_CPU_PHYS 0x50040000 +#define IO_CPU_VIRT IOMEM(0xFE440000) #define IO_CPU_SIZE SZ_16K #define IO_PPSB_PHYS 0x60000000 #define IO_PPSB_VIRT IOMEM(0xFE200000) -#define IO_PPSB_SIZE SZ_1M +#define IO_PPSB_SIZE SECTION_SIZE #define IO_APB_PHYS 0x70000000 -#define IO_APB_VIRT IOMEM(0xFE300000) -#define IO_APB_SIZE SZ_1M +#define IO_APB_VIRT IOMEM(0xFE000000) +#define IO_APB_SIZE SECTION_SIZE #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) -- cgit v1.2.3 From 7e1161f8af73f0077aa80c1af671d272ed14f37a Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 5 Dec 2013 16:27:49 +0530 Subject: ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC The pincontrol driver for Tegra124 is build through config PINCTRL_TEGRA124. Select this config option whenever Tegra124 SoC is enabled. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f58b27..807e7bcd0ac3 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -63,6 +63,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER + select PINCTRL_TEGRA124 help Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU -- cgit v1.2.3 From 7e25eb01e648b4cfde566cc2520a2d7222c63fc8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 6 Dec 2013 16:27:12 +0100 Subject: ARM: tegra: Fix some whitespace oddities Some of the powergate code uses unusual spacing around == and has a tab instead of a space before an opening parenthesis. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index f6f5b54ff95e..d5f5bd24dd09 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -132,9 +132,9 @@ int tegra_powergate_remove_clamping(int id) * Tegra 2 has a bug where PCIE and VDE clamping masks are * swapped relatively to the partition ids */ - if (id == TEGRA_POWERGATE_VDEC) + if (id == TEGRA_POWERGATE_VDEC) mask = (1 << TEGRA_POWERGATE_PCIE); - else if (id == TEGRA_POWERGATE_PCIE) + else if (id == TEGRA_POWERGATE_PCIE) mask = (1 << TEGRA_POWERGATE_VDEC); else mask = (1 << id); -- cgit v1.2.3 From ccab7983bdb3d78da3fb918902a739fc79e018be Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 6 Dec 2013 16:27:13 +0100 Subject: ARM: tegra: Rename cpu0 powergate to crail This matches the name of the powergate as listed in the TRM. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index d5f5bd24dd09..ed4d3d15b8db 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -245,7 +245,7 @@ static const char * const powergate_name_t30[] = { }; static const char * const powergate_name_t114[] = { - [TEGRA_POWERGATE_CPU] = "cpu0", + [TEGRA_POWERGATE_CPU] = "crail", [TEGRA_POWERGATE_3D] = "3d", [TEGRA_POWERGATE_VENC] = "venc", [TEGRA_POWERGATE_VDEC] = "vdec", -- cgit v1.2.3 From 44374afee87b5384f2ee3c2e5e5b8419c1573efb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 6 Dec 2013 16:49:55 +0100 Subject: ARM: tegra: Export tegra_powergate_power_off() This function can be used by drivers, which in turn may be built as modules. Export the symbol so it is available to modules. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index ed4d3d15b8db..e8ccb2973333 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -109,6 +109,7 @@ int tegra_powergate_power_off(int id) return tegra_powergate_set(id, false); } +EXPORT_SYMBOL(tegra_powergate_power_off); int tegra_powergate_is_powered(int id) { -- cgit v1.2.3 From 201fc0f9163314d169bb6b9837f922a8a374f81b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 6 Dec 2013 16:49:56 +0100 Subject: ARM: tegra: Export tegra_powergate_remove_clamping() Drivers can use the tegra_powergate_remove_clamping() API during initialization. In order to allow such drivers to be built as modules, export the symbol. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index e8ccb2973333..a67c92acb4a6 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -144,6 +144,7 @@ int tegra_powergate_remove_clamping(int id) return 0; } +EXPORT_SYMBOL(tegra_powergate_remove_clamping); /* Must be called with clk disabled, and returns with clk enabled */ int tegra_powergate_sequence_power_up(int id, struct clk *clk, -- cgit v1.2.3 From 9a716579660aa87a4ab4b4d1cac0686fba3707ba Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 13 Dec 2013 17:31:03 +0100 Subject: ARM: tegra: Add Tegra124 powergate support Three new gates have been added for Tegra124: SOR, VIC and IRAM. In addition, PCIe and SATA gates are again supported, like on Tegra20 and Tegra30. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 42 +++++++++++++++++++++++++++++++++++++++++ include/linux/tegra-powergate.h | 3 +++ 2 files changed, 45 insertions(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index a67c92acb4a6..a8ac634eda77 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -59,6 +59,13 @@ static const u8 tegra114_cpu_domains[] = { TEGRA_POWERGATE_CPU3, }; +static const u8 tegra124_cpu_domains[] = { + TEGRA_POWERGATE_CPU0, + TEGRA_POWERGATE_CPU1, + TEGRA_POWERGATE_CPU2, + TEGRA_POWERGATE_CPU3, +}; + static DEFINE_SPINLOCK(tegra_powergate_lock); static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); @@ -206,6 +213,11 @@ int __init tegra_powergate_init(void) tegra_num_cpu_domains = 4; tegra_cpu_domains = tegra114_cpu_domains; break; + case TEGRA124: + tegra_num_powerdomains = 25; + tegra_num_cpu_domains = 4; + tegra_cpu_domains = tegra124_cpu_domains; + break; default: /* Unknown Tegra variant. Disable powergating */ tegra_num_powerdomains = 0; @@ -267,6 +279,33 @@ static const char * const powergate_name_t114[] = { [TEGRA_POWERGATE_XUSBC] = "xusbc", }; +static const char * const powergate_name_t124[] = { + [TEGRA_POWERGATE_CPU] = "crail", + [TEGRA_POWERGATE_3D] = "3d", + [TEGRA_POWERGATE_VENC] = "venc", + [TEGRA_POWERGATE_PCIE] = "pcie", + [TEGRA_POWERGATE_VDEC] = "vdec", + [TEGRA_POWERGATE_L2] = "l2", + [TEGRA_POWERGATE_MPE] = "mpe", + [TEGRA_POWERGATE_HEG] = "heg", + [TEGRA_POWERGATE_SATA] = "sata", + [TEGRA_POWERGATE_CPU1] = "cpu1", + [TEGRA_POWERGATE_CPU2] = "cpu2", + [TEGRA_POWERGATE_CPU3] = "cpu3", + [TEGRA_POWERGATE_CELP] = "celp", + [TEGRA_POWERGATE_CPU0] = "cpu0", + [TEGRA_POWERGATE_C0NC] = "c0nc", + [TEGRA_POWERGATE_C1NC] = "c1nc", + [TEGRA_POWERGATE_SOR] = "sor", + [TEGRA_POWERGATE_DIS] = "dis", + [TEGRA_POWERGATE_DISB] = "disb", + [TEGRA_POWERGATE_XUSBA] = "xusba", + [TEGRA_POWERGATE_XUSBB] = "xusbb", + [TEGRA_POWERGATE_XUSBC] = "xusbc", + [TEGRA_POWERGATE_VIC] = "vic", + [TEGRA_POWERGATE_IRAM] = "iram", +}; + static int powergate_show(struct seq_file *s, void *data) { int i; @@ -311,6 +350,9 @@ int __init tegra_powergate_debugfs_init(void) case TEGRA114: powergate_name = powergate_name_t114; break; + case TEGRA124: + powergate_name = powergate_name_t124; + break; } if (powergate_name) { diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h index afe442d2629a..bccad3cfff87 100644 --- a/include/linux/tegra-powergate.h +++ b/include/linux/tegra-powergate.h @@ -38,11 +38,14 @@ struct reset_control; #define TEGRA_POWERGATE_CPU0 14 #define TEGRA_POWERGATE_C0NC 15 #define TEGRA_POWERGATE_C1NC 16 +#define TEGRA_POWERGATE_SOR 17 #define TEGRA_POWERGATE_DIS 18 #define TEGRA_POWERGATE_DISB 19 #define TEGRA_POWERGATE_XUSBA 20 #define TEGRA_POWERGATE_XUSBB 21 #define TEGRA_POWERGATE_XUSBC 22 +#define TEGRA_POWERGATE_VIC 23 +#define TEGRA_POWERGATE_IRAM 24 #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D -- cgit v1.2.3 From c537376cbbbfea2b741b39ad37d5b44104b66e56 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 13 Dec 2013 17:31:04 +0100 Subject: ARM: tegra: Special-case the 3D clamps on Tegra124 A separate register is used to remove the clamps for the GPU on Tegra124. In order to be able to use the same API, special-case this particular partition. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index a8ac634eda77..0026fb6c984b 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -41,6 +41,8 @@ #define PWRGATE_STATUS 0x38 +#define GPU_RG_CNTRL 0x2d4 + static int tegra_num_powerdomains; static int tegra_num_cpu_domains; static const u8 *tegra_cpu_domains; @@ -136,6 +138,17 @@ int tegra_powergate_remove_clamping(int id) if (id < 0 || id >= tegra_num_powerdomains) return -EINVAL; + /* + * The Tegra124 GPU has a separate register (with different semantics) + * to remove clamps. + */ + if (tegra_chip_id == TEGRA124) { + if (id == TEGRA_POWERGATE_3D) { + pmc_write(0, GPU_RG_CNTRL); + return 0; + } + } + /* * Tegra 2 has a bug where PCIE and VDE clamping masks are * swapped relatively to the partition ids -- cgit v1.2.3 From 9d4450ae87398e248e8700e3507748e0d1751e25 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 16 Dec 2013 21:42:28 +0100 Subject: ARM: tegra: Add IO rail support Add tegra_io_rail_power_off() and tegra_io_rail_power_on() functions to put IO rails into or out of deep powerdown mode, respectively. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/powergate.c | 132 ++++++++++++++++++++++++++++++++++++++++ include/linux/tegra-powergate.h | 45 ++++++++++++++ 2 files changed, 177 insertions(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 0026fb6c984b..3d0c537d9b94 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -34,6 +34,10 @@ #include "fuse.h" #include "iomap.h" +#define DPD_SAMPLE 0x020 +#define DPD_SAMPLE_ENABLE (1 << 0) +#define DPD_SAMPLE_DISABLE (0 << 0) + #define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE_START (1 << 8) @@ -41,6 +45,17 @@ #define PWRGATE_STATUS 0x38 +#define IO_DPD_REQ 0x1b8 +#define IO_DPD_REQ_CODE_IDLE (0 << 30) +#define IO_DPD_REQ_CODE_OFF (1 << 30) +#define IO_DPD_REQ_CODE_ON (2 << 30) +#define IO_DPD_REQ_CODE_MASK (3 << 30) + +#define IO_DPD_STATUS 0x1bc +#define IO_DPD2_REQ 0x1c0 +#define IO_DPD2_STATUS 0x1c4 +#define SEL_DPD_TIM 0x1c8 + #define GPU_RG_CNTRL 0x2d4 static int tegra_num_powerdomains; @@ -379,3 +394,120 @@ int __init tegra_powergate_debugfs_init(void) } #endif + +static int tegra_io_rail_prepare(int id, unsigned long *request, + unsigned long *status, unsigned int *bit) +{ + unsigned long rate, value; + struct clk *clk; + + *bit = id % 32; + + /* + * There are two sets of 30 bits to select IO rails, but bits 30 and + * 31 are control bits rather than IO rail selection bits. + */ + if (id > 63 || *bit == 30 || *bit == 31) + return -EINVAL; + + if (id < 32) { + *status = IO_DPD_STATUS; + *request = IO_DPD_REQ; + } else { + *status = IO_DPD2_STATUS; + *request = IO_DPD2_REQ; + } + + clk = clk_get_sys(NULL, "pclk"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + rate = clk_get_rate(clk); + clk_put(clk); + + pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE); + + /* must be at least 200 ns, in APB (PCLK) clock cycles */ + value = DIV_ROUND_UP(1000000000, rate); + value = DIV_ROUND_UP(200, value); + pmc_write(value, SEL_DPD_TIM); + + return 0; +} + +static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, + unsigned long val, unsigned long timeout) +{ + unsigned long value; + + timeout = jiffies + msecs_to_jiffies(timeout); + + while (time_after(timeout, jiffies)) { + value = pmc_read(offset); + if ((value & mask) == val) + return 0; + + usleep_range(250, 1000); + } + + return -ETIMEDOUT; +} + +static void tegra_io_rail_unprepare(void) +{ + pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE); +} + +int tegra_io_rail_power_on(int id) +{ + unsigned long request, status, value; + unsigned int bit, mask; + int err; + + err = tegra_io_rail_prepare(id, &request, &status, &bit); + if (err < 0) + return err; + + mask = 1 << bit; + + value = pmc_read(request); + value |= mask; + value &= ~IO_DPD_REQ_CODE_MASK; + value |= IO_DPD_REQ_CODE_OFF; + pmc_write(value, request); + + err = tegra_io_rail_poll(status, mask, 0, 250); + if (err < 0) + return err; + + tegra_io_rail_unprepare(); + + return 0; +} + +int tegra_io_rail_power_off(int id) +{ + unsigned long request, status, value; + unsigned int bit, mask; + int err; + + err = tegra_io_rail_prepare(id, &request, &status, &bit); + if (err < 0) + return err; + + mask = 1 << bit; + + value = pmc_read(request); + value |= mask; + value &= ~IO_DPD_REQ_CODE_MASK; + value |= IO_DPD_REQ_CODE_ON; + pmc_write(value, request); + + err = tegra_io_rail_poll(status, mask, mask, 250); + if (err < 0) + return err; + + tegra_io_rail_unprepare(); + + return 0; +} diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h index bccad3cfff87..e6f2ab3014a7 100644 --- a/include/linux/tegra-powergate.h +++ b/include/linux/tegra-powergate.h @@ -49,6 +49,38 @@ struct reset_control; #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D +#define TEGRA_IO_RAIL_CSIA 0 +#define TEGRA_IO_RAIL_CSIB 1 +#define TEGRA_IO_RAIL_DSI 2 +#define TEGRA_IO_RAIL_MIPI_BIAS 3 +#define TEGRA_IO_RAIL_PEX_BIAS 4 +#define TEGRA_IO_RAIL_PEX_CLK1 5 +#define TEGRA_IO_RAIL_PEX_CLK2 6 +#define TEGRA_IO_RAIL_USB0 9 +#define TEGRA_IO_RAIL_USB1 10 +#define TEGRA_IO_RAIL_USB2 11 +#define TEGRA_IO_RAIL_USB_BIAS 12 +#define TEGRA_IO_RAIL_NAND 13 +#define TEGRA_IO_RAIL_UART 14 +#define TEGRA_IO_RAIL_BB 15 +#define TEGRA_IO_RAIL_AUDIO 17 +#define TEGRA_IO_RAIL_HSIC 19 +#define TEGRA_IO_RAIL_COMP 22 +#define TEGRA_IO_RAIL_HDMI 28 +#define TEGRA_IO_RAIL_PEX_CNTRL 32 +#define TEGRA_IO_RAIL_SDMMC1 33 +#define TEGRA_IO_RAIL_SDMMC3 34 +#define TEGRA_IO_RAIL_SDMMC4 35 +#define TEGRA_IO_RAIL_CAM 36 +#define TEGRA_IO_RAIL_RES 37 +#define TEGRA_IO_RAIL_HV 38 +#define TEGRA_IO_RAIL_DSIB 39 +#define TEGRA_IO_RAIL_DSIC 40 +#define TEGRA_IO_RAIL_DSID 41 +#define TEGRA_IO_RAIL_CSIE 44 +#define TEGRA_IO_RAIL_LVDS 57 +#define TEGRA_IO_RAIL_SYS_DDC 58 + #ifdef CONFIG_ARCH_TEGRA int tegra_powergate_is_powered(int id); int tegra_powergate_power_on(int id); @@ -58,6 +90,9 @@ int tegra_powergate_remove_clamping(int id); /* Must be called with clk disabled, and returns with clk enabled */ int tegra_powergate_sequence_power_up(int id, struct clk *clk, struct reset_control *rst); + +int tegra_io_rail_power_on(int id); +int tegra_io_rail_power_off(int id); #else static inline int tegra_powergate_is_powered(int id) { @@ -84,6 +119,16 @@ static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk, { return -ENOSYS; } + +static inline int tegra_io_rail_power_on(int id) +{ + return -ENOSYS; +} + +static inline int tegra_io_rail_power_off(int id) +{ + return -ENOSYS; +} #endif #endif /* _MACH_TEGRA_POWERGATE_H_ */ -- cgit v1.2.3