From c962184459ab75502b242efb04291c2cf8700bc3 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 18 Oct 2012 12:20:04 +0300 Subject: ARM: OMAP4: PM: add errata support Added similar PM errata flag support as omap3 has. This should be used in similar manner, set the flags during init time, and check the flag values during runtime. Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-omap2/pm.h') diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 67d66131cfa7..f76a0d0f839f 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -102,6 +102,13 @@ extern void enable_omap3630_toggle_l2_on_restore(void); static inline void enable_omap3630_toggle_l2_on_restore(void) { } #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ +#if defined(CONFIG_ARCH_OMAP4) +extern u16 pm44xx_errata; +#define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id)) +#else +#define IS_PM44XX_ERRATUM(id) 0 +#endif + #ifdef CONFIG_POWER_AVS_OMAP extern int omap_devinit_smartreflex(void); extern void omap_enable_smartreflex_on_init(void); -- cgit v1.2.3 From ff999b8a0983ee15668394ed49e38d3568fc6859 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 18 Oct 2012 12:20:05 +0300 Subject: ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change. On OMAP4+ devices, GIC register context is lost when MPUSS hits the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code gets executed and one of the steps in it is to restore the saved context of the GIC. The ROM Code GIC distributor restoration is split in two parts: CPU specific register done by each CPU and common register done by only one CPU. Below is the abstract flow. ............................................................... - MPUSS in OSWR state. - CPU0 wakes up on the event(interrupt) and start executing ROM code. [..] - CPU0 executes "GIC Restoration:" [...] - CPU0 swicthes to non-secure mode and jumps to OS resume code. [...] - CPU0 is online in OS - CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1 - CPU0 wakes up CPU1 with clock-domain force wakeup method. - CPU0 continues it's execution. [..] - CPU1 wakes up and start executing ROM code. [..] - CPU1 executes "GIC Restoration:" [..] - CPU1 swicthes to non-secure mode and jumps to OS resume code. [...] - CPU1 is online in OS and start executing. [...] - GIC Restoration: /* Common routine for HS and GP devices */ { if (GICD != 1) { /* This will be true in OSWR state */ if (GIC_SAR_BACKUP_STATE == SAVED) - CPU restores GIC distributor else - reconfigure GIC distributor to boot values. GICD.Enable secure = 1 } if (GIC_SAR_BACKUP_STATE == SAVED) - CPU restore its GIC CPU interface registers if saved. else - reconfigure its GIC CPU interface registers to boot values. } ............................................................... So as mentioned in the flow, GICD != 1 condition decides how the GIC registers are handled in ROM code wakeup path from OSWR. As evident from the flow, ROM code relies on the entire GICD register value and not specific register bits. The assumption was valid till CortexA9 r1pX version since there was only one banked bit to control secure and non-secure GICD. Secure view which ROM code sees: bit 0 == Enable Non-secure Non-secure view which HLOS sees: bit 0 == Enable secure But GICD register has changed between CortexA9 r1pX and r2pX. On r2pX GICD register is composed of 2 bits. Secure view which ROM code sees: bit 1 == Enable Non-secure bit 0 == Enable secure Non-secure view which HLOS sees: bit 0 == Enable Non-secure Hence on OMAP4460(r2pX) devices, if you go through the above flow again during CPU1 wakeup, GICD == 3 and hence ROM code fails to understand the real wakeup power state and reconfigures GIC distributor to boot values. This is nasty since you loose the entire interrupt controller context in a live system. The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path. Since ROM code can't be fixed on OMAP4460 devices, a work around needs to be implemented. As evident from the flow, as long as CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue won't happen. Below is the flow with the work-around. ............................................................... - MPUSS in OSWR state. - CPU0 wakes up on the event(interrupt) and start executing ROM code. [..] - CPU0 executes "GIC Restoration:" [..] - CPU0 swicthes to non-secure mode and jumps to OS resume code. [..] - CPU0 is online in OS. - CPU0 does GICD.Enable Non-secure = 0 - CPU0 wakes up CPU1 with clock domain force wakeup method. - CPU0 waits for GICD.Enable Non-secure = 1 - CPU0 coninues it's execution. [..] - CPU1 wakes up and start executing ROM code. [..] - CPU1 executes "GIC Restoration:" [..] - CPU1 swicthes to non-secure mode and jumps to OS resume code. [..] - CPU1 is online in OS - CPU1 does GICD.Enable Non-secure = 1 - CPU1 start executing [...] ............................................................... With this procedure, the GIC configuration done between the CPU0 wakeup and CPU1 wakeup will not be lost but during this short windows, the CPU0 will not receive interrupts. The BUG is applicable to only OMAP4460(r2pX) devices. OMAP4470 (also r2pX) is not affected by this bug because ROM code has been fixed. Signed-off-by: Santosh Shilimkar Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/common.h | 2 ++ arch/arm/mach-omap2/omap-headsmp.S | 38 +++++++++++++++++++++++++++++++ arch/arm/mach-omap2/omap-mpuss-lowpower.c | 9 +++++++- arch/arm/mach-omap2/omap-smp.c | 28 ++++++++++++++++++++++- arch/arm/mach-omap2/omap4-common.c | 8 ++++++- arch/arm/mach-omap2/pm.h | 2 ++ 6 files changed, 84 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-omap2/pm.h') diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 7045e4d61ac3..70993a9fcb50 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -275,6 +275,7 @@ static inline void __iomem *omap4_get_scu_base(void) #endif extern void __init gic_init_irq(void); +extern void gic_dist_disable(void); extern void omap_smc1(u32 fn, u32 arg); extern void __iomem *omap4_get_sar_ram_base(void); extern void omap_do_wfi(void); @@ -282,6 +283,7 @@ extern void omap_do_wfi(void); #ifdef CONFIG_SMP /* Needed for secondary core boot */ extern void omap_secondary_startup(void); +extern void omap_secondary_startup_4460(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 502e3135aad3..0ea09faf327b 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -18,6 +18,8 @@ #include #include +#include "omap44xx.h" + __CPUINIT /* Physical address needed since MMU not enabled yet on secondary core */ @@ -64,3 +66,39 @@ hold: ldr r12,=0x103 b secondary_startup ENDPROC(omap_secondary_startup) +ENTRY(omap_secondary_startup_4460) +hold_2: ldr r12,=0x103 + dsb + smc #0 @ read from AuxCoreBoot0 + mov r0, r0, lsr #9 + mrc p15, 0, r4, c0, c0, 5 + and r4, r4, #0x0f + cmp r0, r4 + bne hold_2 + + /* + * GIC distributor control register has changed between + * CortexA9 r1pX and r2pX. The Control Register secure + * banked version is now composed of 2 bits: + * bit 0 == Secure Enable + * bit 1 == Non-Secure Enable + * The Non-Secure banked register has not changed + * Because the ROM Code is based on the r1pX GIC, the CPU1 + * GIC restoration will cause a problem to CPU0 Non-Secure SW. + * The workaround must be: + * 1) Before doing the CPU1 wakeup, CPU0 must disable + * the GIC distributor + * 2) CPU1 must re-enable the GIC distributor on + * it's wakeup path. + */ + ldr r1, =OMAP44XX_GIC_DIST_BASE + ldr r0, [r1] + orr r0, #1 + str r0, [r1] + + /* + * we've been released from the wait loop,secondary_stack + * should now contain the SVC stack for this core + */ + b secondary_startup +ENDPROC(omap_secondary_startup_4460) diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index ff4e6a0e9c7c..c8bc3ad85f68 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -67,6 +67,7 @@ struct omap4_cpu_pm_info { void __iomem *scu_sar_addr; void __iomem *wkup_sar_addr; void __iomem *l2x0_sar_addr; + void (*secondary_startup)(void); }; static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); @@ -299,6 +300,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) { unsigned int cpu_state = 0; + struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); if (omap_rev() == OMAP4430_REV_ES1_0) return -ENXIO; @@ -308,7 +310,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) clear_cpu_prev_pwrst(cpu); set_cpu_next_pwrst(cpu, power_state); - set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup)); + set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); scu_pwrst_prepare(cpu, power_state); /* @@ -359,6 +361,11 @@ int __init omap4_mpuss_init(void) pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; + if (cpu_is_omap446x()) + pm_info->secondary_startup = omap_secondary_startup_4460; + else + pm_info->secondary_startup = omap_secondary_startup; + pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); if (!pm_info->pwrdm) { pr_err("Lookup failed for CPU1 pwrdm\n"); diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 4d05fa8a4e48..7d9c0e3fedc4 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -32,6 +32,7 @@ #include "iomap.h" #include "common.h" #include "clockdomain.h" +#include "pm.h" #define CPU_MASK 0xff0ffff0 #define CPU_CORTEX_A9 0x410FC090 @@ -118,6 +119,24 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * * 4.3.4.2 Power States of CPU0 and CPU1 */ if (booted) { + /* + * GIC distributor control register has changed between + * CortexA9 r1pX and r2pX. The Control Register secure + * banked version is now composed of 2 bits: + * bit 0 == Secure Enable + * bit 1 == Non-Secure Enable + * The Non-Secure banked register has not changed + * Because the ROM Code is based on the r1pX GIC, the CPU1 + * GIC restoration will cause a problem to CPU0 Non-Secure SW. + * The workaround must be: + * 1) Before doing the CPU1 wakeup, CPU0 must disable + * the GIC distributor + * 2) CPU1 must re-enable the GIC distributor on + * it's wakeup path. + */ + if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) + gic_dist_disable(); + clkdm_wakeup(cpu1_clkdm); clkdm_allow_idle(cpu1_clkdm); } else { @@ -138,7 +157,14 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct * static void __init wakeup_secondary(void) { + void *startup_addr = omap_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); + + if (cpu_is_omap446x()) { + startup_addr = omap_secondary_startup_4460; + pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; + } + /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing @@ -146,7 +172,7 @@ static void __init wakeup_secondary(void) * A barrier is added to ensure that write buffer is drained */ if (omap_secure_apis_support()) - omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); + omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else __raw_writel(virt_to_phys(omap5_secondary_startup), base + OMAP_AUX_CORE_BOOT_1); diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index e1f289748c5d..72cf396a0fc2 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -41,6 +41,7 @@ static void __iomem *l2cache_base; #endif static void __iomem *sar_ram_base; +static void __iomem *gic_dist_base_addr; #ifdef CONFIG_OMAP4_ERRATA_I688 /* Used to implement memory barrier on DRAM path */ @@ -95,7 +96,6 @@ void __init omap_barriers_init(void) void __init gic_init_irq(void) { void __iomem *omap_irq_base; - void __iomem *gic_dist_base_addr; /* Static mapping, never released */ gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K); @@ -110,6 +110,12 @@ void __init gic_init_irq(void) gic_init(0, 29, gic_dist_base_addr, omap_irq_base); } +void gic_dist_disable(void) +{ + if (gic_dist_base_addr) + __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL); +} + #ifdef CONFIG_CACHE_L2X0 void __iomem *omap4_get_l2cache_base(void) diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index f76a0d0f839f..fc3c96d5e013 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -102,6 +102,8 @@ extern void enable_omap3630_toggle_l2_on_restore(void); static inline void enable_omap3630_toggle_l2_on_restore(void) { } #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */ +#define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0) + #if defined(CONFIG_ARCH_OMAP4) extern u16 pm44xx_errata; #define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id)) -- cgit v1.2.3 From 908b75e850c4a6130b680ea7e59b00f80d4cd2d2 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 25 Sep 2012 19:33:39 +0300 Subject: ARM: OMAP: add support for oscillator setup This contains startup and shutdown times for the oscillator. By default use ULONG_MAX. Oscillator setup is used for calculating and setting up latencies for sleep modes that disable oscillator. Based on a patch from Nishanth Menon . Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm.c | 30 ++++++++++++++++++++++++++++++ arch/arm/mach-omap2/pm.h | 8 ++++++++ 2 files changed, 38 insertions(+) (limited to 'arch/arm/mach-omap2/pm.h') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index ea61c32957bd..109a02e02d72 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -39,6 +39,36 @@ static struct omap_device_pm_latency *pm_lats; */ int (*omap_pm_suspend)(void); +/** + * struct omap2_oscillator - Describe the board main oscillator latencies + * @startup_time: oscillator startup latency + * @shutdown_time: oscillator shutdown latency + */ +struct omap2_oscillator { + u32 startup_time; + u32 shutdown_time; +}; + +static struct omap2_oscillator oscillator = { + .startup_time = ULONG_MAX, + .shutdown_time = ULONG_MAX, +}; + +void omap_pm_setup_oscillator(u32 tstart, u32 tshut) +{ + oscillator.startup_time = tstart; + oscillator.shutdown_time = tshut; +} + +void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) +{ + if (!tstart || !tshut) + return; + + *tstart = oscillator.startup_time; + *tshut = oscillator.shutdown_time; +} + static int __init _init_omap_device(char *name) { struct omap_hwmod *oh; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 67d66131cfa7..429028852103 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -129,4 +129,12 @@ static inline int omap4_twl_init(void) } #endif +#ifdef CONFIG_PM +extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut); +extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut); +#else +static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { } +static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { } +#endif + #endif -- cgit v1.2.3 From 00bd228ea9f7aad23f7933fa62a13d975d4b213a Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 25 Sep 2012 19:33:48 +0300 Subject: ARM: OMAP4: VC: setup I2C parameters based on board data VC code now provides a table of pre-calculated I2C setup parameters, which will be used based on the capacitance value calculated for the I2C trace on the PCB. A default trace length of 6.3cm is used unless board defines its own value during init. The parameters set will be the I2C internal pull setup and the I2C timing parameters for high speed use mode. Full speed mode is not supported as of now. Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_twl.c | 3 + arch/arm/mach-omap2/pm.h | 2 + arch/arm/mach-omap2/vc.c | 149 ++++++++++++++++++++++++++++++++++++++--- arch/arm/mach-omap2/voltage.h | 1 + 4 files changed, 147 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-omap2/pm.h') diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c index ecae9890f0f2..611cb63d5ce6 100644 --- a/arch/arm/mach-omap2/omap_twl.c +++ b/arch/arm/mach-omap2/omap_twl.c @@ -183,6 +183,7 @@ static struct omap_voltdm_pmic omap4_mpu_pmic = { .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG, .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG, .i2c_high_speed = true, + .i2c_pad_load = 3, .vsel_to_uv = twl6030_vsel_to_uv, .uv_to_vsel = twl6030_uv_to_vsel, }; @@ -200,6 +201,7 @@ static struct omap_voltdm_pmic omap4_iva_pmic = { .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG, .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG, .i2c_high_speed = true, + .i2c_pad_load = 3, .vsel_to_uv = twl6030_vsel_to_uv, .uv_to_vsel = twl6030_uv_to_vsel, }; @@ -216,6 +218,7 @@ static struct omap_voltdm_pmic omap4_core_pmic = { .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR, .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG, .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG, + .i2c_pad_load = 3, .vsel_to_uv = twl6030_vsel_to_uv, .uv_to_vsel = twl6030_uv_to_vsel, }; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 429028852103..4db7b238a0d5 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -132,9 +132,11 @@ static inline int omap4_twl_init(void) #ifdef CONFIG_PM extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut); extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut); +extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm); #else static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { } static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { } +static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { } #endif #endif diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index d72b787a0d83..687aa86c0d5e 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -24,6 +24,7 @@ #include "prm44xx.h" #include "pm.h" #include "scrm44xx.h" +#include "control.h" /** * struct omap_vc_channel_cfg - describe the cfg_channel bitfield @@ -69,6 +70,9 @@ static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { }; static struct omap_vc_channel_cfg *vc_cfg_bits; + +/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */ +static u32 sr_i2c_pcb_length = 63; #define CFG_CHANNEL_MASK 0x1f /** @@ -464,22 +468,135 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode) /* OMAP4 specific voltage init functions */ static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) { - static bool is_initialized; - u32 vc_val; - omap4_set_timings(voltdm, true); omap4_set_timings(voltdm, false); +} + +struct i2c_init_data { + u8 loadbits; + u8 load; + u8 hsscll_38_4; + u8 hsscll_26; + u8 hsscll_19_2; + u8 hsscll_16_8; + u8 hsscll_12; +}; + +static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = { + { + .load = 50, + .loadbits = 0x3, + .hsscll_38_4 = 13, + .hsscll_26 = 11, + .hsscll_19_2 = 9, + .hsscll_16_8 = 9, + .hsscll_12 = 8, + }, + { + .load = 25, + .loadbits = 0x2, + .hsscll_38_4 = 13, + .hsscll_26 = 11, + .hsscll_19_2 = 9, + .hsscll_16_8 = 9, + .hsscll_12 = 8, + }, + { + .load = 12, + .loadbits = 0x1, + .hsscll_38_4 = 11, + .hsscll_26 = 10, + .hsscll_19_2 = 9, + .hsscll_16_8 = 9, + .hsscll_12 = 8, + }, + { + .load = 0, + .loadbits = 0x0, + .hsscll_38_4 = 12, + .hsscll_26 = 10, + .hsscll_19_2 = 9, + .hsscll_16_8 = 8, + .hsscll_12 = 8, + }, +}; + +/** + * omap4_vc_i2c_timing_init - sets up board I2C timing parameters + * @voltdm: voltagedomain pointer to get data from + * + * Use PMIC + board supplied settings for calculating the total I2C + * channel capacitance and set the timing parameters based on this. + * Pre-calculated values are provided in data tables, as it is not + * too straightforward to calculate these runtime. + */ +static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm) +{ + u32 capacitance; + u32 val; + u16 hsscll; + const struct i2c_init_data *i2c_data; + + if (!voltdm->pmic->i2c_high_speed) { + pr_warn("%s: only high speed supported!\n", __func__); + return; + } - if (is_initialized) + /* PCB trace capacitance, 0.125pF / mm => mm / 8 */ + capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8); + + /* OMAP pad capacitance */ + capacitance += 4; + + /* PMIC pad capacitance */ + capacitance += voltdm->pmic->i2c_pad_load; + + /* Search for capacitance match in the table */ + i2c_data = omap4_i2c_timing_data; + + while (i2c_data->load > capacitance) + i2c_data++; + + /* Select proper values based on sysclk frequency */ + switch (voltdm->sys_clk.rate) { + case 38400000: + hsscll = i2c_data->hsscll_38_4; + break; + case 26000000: + hsscll = i2c_data->hsscll_26; + break; + case 19200000: + hsscll = i2c_data->hsscll_19_2; + break; + case 16800000: + hsscll = i2c_data->hsscll_16_8; + break; + case 12000000: + hsscll = i2c_data->hsscll_12; + break; + default: + pr_warn("%s: unsupported sysclk rate: %d!\n", __func__, + voltdm->sys_clk.rate); return; + } + + /* Loadbits define pull setup for the I2C channels */ + val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; - /* XXX These are magic numbers and do not belong! */ - vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT); - voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); + /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ + __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + + OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); - is_initialized = true; + /* HSSCLH can always be zero */ + val = hsscll << OMAP4430_HSSCLL_SHIFT; + val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT); + + /* Write setup times to I2C config register */ + voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); } + + /** * omap_vc_i2c_init - initialize I2C interface to PMIC * @voltdm: voltage domain containing VC data @@ -519,6 +636,9 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) mcode << __ffs(vc->common->i2c_mcode_mask), vc->common->i2c_cfg_reg); + if (cpu_is_omap44xx()) + omap4_vc_i2c_timing_init(voltdm); + initialized = true; } @@ -546,6 +666,19 @@ static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) return voltdm->pmic->uv_to_vsel(uvolt); } +/** + * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB + * @mm: length of the PCB trace in millimetres + * + * Sets the PCB trace length for the I2C channel. By default uses 63mm. + * This is needed for properly calculating the capacitance value for + * the PCB trace, and for setting the SR I2C channel timing parameters. + */ +void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm) +{ + sr_i2c_pcb_length = mm; +} + void __init omap_vc_init_channel(struct voltagedomain *voltdm) { struct omap_vc_channel *vc = voltdm->vc; diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 78923f93efde..a0ce4f10ff13 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h @@ -139,6 +139,7 @@ struct omap_voltdm_pmic { u32 vddmax; u8 vp_timeout_us; bool i2c_high_speed; + u32 i2c_pad_load; u8 i2c_mcode; unsigned long (*vsel_to_uv) (const u8 vsel); u8 (*uv_to_vsel) (unsigned long uV); -- cgit v1.2.3 From 74d29168e9af59c9db1885e27493fbed4d24ef18 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 14 Nov 2012 17:13:04 -0800 Subject: ARM: OMAP2+: voltage: fixup oscillator handling when CONFIG_PM=n commit 908b75e8 (ARM: OMAP: add support for oscillator setup) added a new API for oscillator setup, but is broken when CONFIG_PM=n. The new functions have dummy definitions when CONFIG_PM=n, but also have full implementations available, which conflict. To fix, wrap the PM implmentations in #ifdef CONFIG_PM. Cc: Tero Kristo Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm.c | 2 ++ arch/arm/mach-omap2/pm.h | 2 +- arch/arm/mach-omap2/vc.c | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/pm.h') diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 109a02e02d72..ef668c756db7 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -39,6 +39,7 @@ static struct omap_device_pm_latency *pm_lats; */ int (*omap_pm_suspend)(void); +#ifdef CONFIG_PM /** * struct omap2_oscillator - Describe the board main oscillator latencies * @startup_time: oscillator startup latency @@ -68,6 +69,7 @@ void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) *tstart = oscillator.startup_time; *tshut = oscillator.shutdown_time; } +#endif static int __init _init_omap_device(char *name) { diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 4db7b238a0d5..02c291c8e470 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -135,7 +135,7 @@ extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut); extern void omap_pm_setup_sr_i2c_pcb_length(u32 mm); #else static inline void omap_pm_setup_oscillator(u32 tstart, u32 tshut) { } -static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { } +static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *tshut = 0; } static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { } #endif diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index 687aa86c0d5e..a89ec8affed4 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -666,6 +666,7 @@ static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) return voltdm->pmic->uv_to_vsel(uvolt); } +#ifdef CONFIG_PM /** * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB * @mm: length of the PCB trace in millimetres @@ -678,6 +679,7 @@ void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm) { sr_i2c_pcb_length = mm; } +#endif void __init omap_vc_init_channel(struct voltagedomain *voltdm) { -- cgit v1.2.3