From 52bd138d616409a45bbb32bd3536cbdadc524de6 Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Thu, 30 Aug 2012 12:53:22 -0700 Subject: ARM: OMAP2+: gpmc: update nand register helper Provide helper function for updating NAND register details for the necessary chip select. NAND drivers platform data can be updated with this information so that NAND driver can handle GPMC NAND operations by itself. Signed-off-by: Afzal Mohammed Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm/mach-omap2/gpmc.c') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index b2b5759ab0fe..5cce9b00c13e 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -682,6 +682,26 @@ int gpmc_prefetch_reset(int cs) } EXPORT_SYMBOL(gpmc_prefetch_reset); +void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) +{ + reg->gpmc_status = gpmc_base + GPMC_STATUS; + reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; + reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; + reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + + GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; + reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; + reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; + reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; + reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; + reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; + reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; + reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; + reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; + reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; +} + static void __init gpmc_mem_init(void) { int cs; -- cgit v1.2.3 From 6b6c32fc96d5a0ef1e8c5d9f1b24c3a07b878f6d Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Thu, 30 Aug 2012 12:53:23 -0700 Subject: ARM: OMAP2+: gpmc: Modify interrupt handling Modify interrupt handling such that interrupts can be handled by GPMC client drivers using standard interrupt APIs rather than requiring the drivers to have knowledge about GPMC interrupt handling. Currently only NAND related interrupts has been considered (which is the case even without this change) as the only user of GPMC interrupt is NAND. Signed-off-by: Afzal Mohammed Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 136 ++++++++++++++++++++++++++++----- arch/arm/plat-omap/include/plat/gpmc.h | 1 + 2 files changed, 120 insertions(+), 17 deletions(-) (limited to 'arch/arm/mach-omap2/gpmc.c') diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5cce9b00c13e..39c30d9bafd9 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -78,6 +78,15 @@ #define ENABLE_PREFETCH (0x1 << 7) #define DMA_MPU_MODE 2 +/* XXX: Only NAND irq has been considered,currently these are the only ones used + */ +#define GPMC_NR_IRQ 2 + +struct gpmc_client_irq { + unsigned irq; + u32 bitmask; +}; + /* Structure to save gpmc cs context */ struct gpmc_cs_config { u32 config1; @@ -105,6 +114,10 @@ struct omap3_gpmc_regs { struct gpmc_cs_config cs_context[GPMC_CS_NUM]; }; +static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; +static struct irq_chip gpmc_irq_chip; +static unsigned gpmc_irq_start; + static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; static DEFINE_SPINLOCK(gpmc_mem_lock); @@ -702,6 +715,97 @@ void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0; } +int gpmc_get_client_irq(unsigned irq_config) +{ + int i; + + if (hweight32(irq_config) > 1) + return 0; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (gpmc_client_irq[i].bitmask & irq_config) + return gpmc_client_irq[i].irq; + + return 0; +} + +static int gpmc_irq_endis(unsigned irq, bool endis) +{ + int i; + u32 regval; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (irq == gpmc_client_irq[i].irq) { + regval = gpmc_read_reg(GPMC_IRQENABLE); + if (endis) + regval |= gpmc_client_irq[i].bitmask; + else + regval &= ~gpmc_client_irq[i].bitmask; + gpmc_write_reg(GPMC_IRQENABLE, regval); + break; + } + + return 0; +} + +static void gpmc_irq_disable(struct irq_data *p) +{ + gpmc_irq_endis(p->irq, false); +} + +static void gpmc_irq_enable(struct irq_data *p) +{ + gpmc_irq_endis(p->irq, true); +} + +static void gpmc_irq_noop(struct irq_data *data) { } + +static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } + +static int gpmc_setup_irq(int gpmc_irq) +{ + int i; + u32 regval; + + if (!gpmc_irq) + return -EINVAL; + + gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); + if (IS_ERR_VALUE(gpmc_irq_start)) { + pr_err("irq_alloc_descs failed\n"); + return gpmc_irq_start; + } + + gpmc_irq_chip.name = "gpmc"; + gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; + gpmc_irq_chip.irq_enable = gpmc_irq_enable; + gpmc_irq_chip.irq_disable = gpmc_irq_disable; + gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; + gpmc_irq_chip.irq_ack = gpmc_irq_noop; + gpmc_irq_chip.irq_mask = gpmc_irq_noop; + gpmc_irq_chip.irq_unmask = gpmc_irq_noop; + + gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; + gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; + + for (i = 0; i < GPMC_NR_IRQ; i++) { + gpmc_client_irq[i].irq = gpmc_irq_start + i; + irq_set_chip_and_handler(gpmc_client_irq[i].irq, + &gpmc_irq_chip, handle_simple_irq); + set_irq_flags(gpmc_client_irq[i].irq, + IRQF_VALID | IRQF_NOAUTOEN); + } + + /* Disable interrupts */ + gpmc_write_reg(GPMC_IRQENABLE, 0); + + /* clear interrupts */ + regval = gpmc_read_reg(GPMC_IRQSTATUS); + gpmc_write_reg(GPMC_IRQSTATUS, regval); + + return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); +} + static void __init gpmc_mem_init(void) { int cs; @@ -731,8 +835,8 @@ static void __init gpmc_mem_init(void) static int __init gpmc_init(void) { - u32 l, irq; - int cs, ret = -EINVAL; + u32 l; + int ret = -EINVAL; int gpmc_irq; char *ck = NULL; @@ -781,16 +885,7 @@ static int __init gpmc_init(void) gpmc_write_reg(GPMC_SYSCONFIG, l); gpmc_mem_init(); - /* initalize the irq_chained */ - irq = OMAP_GPMC_IRQ_BASE; - for (cs = 0; cs < GPMC_CS_NUM; cs++) { - irq_set_chip_and_handler(irq, &dummy_irq_chip, - handle_simple_irq); - set_irq_flags(irq, IRQF_VALID); - irq++; - } - - ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL); + ret = gpmc_setup_irq(gpmc_irq); if (ret) pr_err("gpmc: irq-%d could not claim: err %d\n", gpmc_irq, ret); @@ -800,12 +895,19 @@ postcore_initcall(gpmc_init); static irqreturn_t gpmc_handle_irq(int irq, void *dev) { - u8 cs; + int i; + u32 regval; + + regval = gpmc_read_reg(GPMC_IRQSTATUS); + + if (!regval) + return IRQ_NONE; + + for (i = 0; i < GPMC_NR_IRQ; i++) + if (regval & gpmc_client_irq[i].bitmask) + generic_handle_irq(gpmc_client_irq[i].irq); - /* check cs to invoke the irq */ - cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; - if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) - generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); + gpmc_write_reg(GPMC_IRQSTATUS, regval); return IRQ_HANDLED; } diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h index 06198a51c4f0..2e6e2597178c 100644 --- a/arch/arm/plat-omap/include/plat/gpmc.h +++ b/arch/arm/plat-omap/include/plat/gpmc.h @@ -150,6 +150,7 @@ struct gpmc_nand_regs { }; extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); +extern int gpmc_get_client_irq(unsigned irq_config); extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); -- cgit v1.2.3 From 7d7e1eba7e92c2f9c76db80adc24836e7a114bfb Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 27 Aug 2012 17:43:01 -0700 Subject: ARM: OMAP2+: Prepare for irqs.h removal As the interrupts should only be defined in the platform_data, and eventually coming from device tree, there's no need to define them in header files. Let's remove the hardcoded references to irqs.h and fix up the includes so we don't rely on headers included in irqs.h. Note that we're defining OMAP_INTC_START as 0 to the interrupts. This will be needed when we enable SPARSE_IRQ. For some drivers we need to add #include for now until these drivers are fixed to remove cpu_is_omapxxxx() usage. While at it, sort som of the includes the standard way, and add the trailing commas where they are missing in the related data structures. Note that for drivers/staging/tidspbridge we just define things locally. Cc: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-2430sdp.c | 2 +- arch/arm/mach-omap2/board-4430sdp.c | 2 +- arch/arm/mach-omap2/board-am3517evm.c | 3 +- arch/arm/mach-omap2/board-cm-t3517.c | 4 +- arch/arm/mach-omap2/board-flash.c | 2 +- arch/arm/mach-omap2/board-igep0020.c | 2 + arch/arm/mach-omap2/board-n8x0.c | 3 +- arch/arm/mach-omap2/board-omap4panda.c | 2 +- arch/arm/mach-omap2/board-rm680.c | 3 +- arch/arm/mach-omap2/board-rx51-peripherals.c | 2 +- arch/arm/mach-omap2/board-ti8168evm.c | 1 - arch/arm/mach-omap2/board-zoom-debugboard.c | 1 + arch/arm/mach-omap2/board-zoom-peripherals.c | 3 +- arch/arm/mach-omap2/common-board-devices.c | 1 + arch/arm/mach-omap2/common.h | 2 + arch/arm/mach-omap2/cpuidle34xx.c | 1 - arch/arm/mach-omap2/devices.c | 17 ++- arch/arm/mach-omap2/gpmc-smc91x.c | 1 + arch/arm/mach-omap2/gpmc.c | 11 +- arch/arm/mach-omap2/io.c | 2 + arch/arm/mach-omap2/mailbox.c | 3 +- arch/arm/mach-omap2/mcbsp.c | 1 - arch/arm/mach-omap2/omap-iommu.c | 12 +- arch/arm/mach-omap2/omap-wakeupgen.c | 1 + arch/arm/mach-omap2/omap4-common.c | 7 +- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 23 ++-- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 71 +++++----- .../mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c | 108 ++++++++------- arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 6 +- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 149 +++++++++++---------- arch/arm/mach-omap2/omap_hwmod_common_data.h | 1 + arch/arm/mach-omap2/omap_l3_noc.c | 6 +- arch/arm/mach-omap2/omap_phy_internal.c | 2 + arch/arm/mach-omap2/pm24xx.c | 2 - arch/arm/mach-omap2/prcm.c | 1 - arch/arm/mach-omap2/prm2xxx_3xxx.c | 3 +- arch/arm/mach-omap2/prm44xx.c | 4 +- arch/arm/mach-omap2/prm_common.c | 1 - arch/arm/mach-omap2/serial.c | 1 + arch/arm/mach-omap2/soc.h | 1 + arch/arm/mach-omap2/timer.c | 10 +- arch/arm/mach-omap2/twl-common.c | 3 +- arch/arm/mach-omap2/twl-common.h | 6 +- arch/arm/mach-omap2/usb-host.c | 1 - arch/arm/mach-omap2/usb-musb.c | 1 - arch/arm/plat-omap/include/plat/omap44xx.h | 1 + drivers/dma/omap-dma.c | 2 + drivers/mfd/twl-core.c | 2 + drivers/mtd/onenand/omap2.c | 1 + drivers/video/omap2/dss/dispc.c | 1 + drivers/video/omap2/omapfb/omapfb-main.c | 1 + sound/soc/omap/mcbsp.c | 2 + sound/soc/omap/omap-mcbsp.c | 1 + sound/soc/omap/omap-pcm.c | 1 + 54 files changed, 263 insertions(+), 238 deletions(-) create mode 100644 arch/arm/mach-omap2/soc.h (limited to 'arch/arm/mach-omap2/gpmc.c') diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index cacc49889129..0900eac57d56 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -231,7 +231,7 @@ static int __init omap2430_i2c_init(void) sdp2430_i2c1_boardinfo[0].irq = gpio_to_irq(78); omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo, ARRAY_SIZE(sdp2430_i2c1_boardinfo)); - omap_pmic_init(2, 100, "twl4030", INT_24XX_SYS_NIRQ, + omap_pmic_init(2, 100, "twl4030", 7 + OMAP_INTC_START, &sdp2430_twldata); return 0; } diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index ee8260481273..31456eae7808 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -579,7 +579,7 @@ static int __init omap4_i2c_init(void) TWL_COMMON_REGULATOR_V1V8 | TWL_COMMON_REGULATOR_V2V1); omap4_pmic_init("twl6030", &sdp4430_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + &twl6040_data, 119 + OMAP44XX_IRQ_GIC_START); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 029ebdf70c43..f8bc86029bdc 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -296,8 +296,7 @@ static struct resource am3517_hecc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 57204f81ce2c..20fe233924ed 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c @@ -42,6 +42,7 @@ #include #include #include +#include #include @@ -89,8 +90,7 @@ static struct resource cm_t3517_hecc_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = INT_35XX_HECC0_IRQ, - .end = INT_35XX_HECC0_IRQ, + .start = 24 + OMAP_INTC_START, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c index 9ceec38610d5..901fa1f12409 100644 --- a/arch/arm/mach-omap2/board-flash.c +++ b/arch/arm/mach-omap2/board-flash.c @@ -16,8 +16,8 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 577554933862..bacb917191d1 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -32,6 +32,8 @@ #include "common.h" #include #include +#include + #include