From 4519c2bf433b97d091635eb51e4ba8ffa1c84d62 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 12 May 2009 17:26:32 -0600 Subject: OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/clock34xx.c') diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 0a14dca31e30..811360af60dc 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = { #define MAX_DPLL_WAIT_TRIES 1000000 +#define MIN_SDRC_DLL_LOCK_FREQ 83000000 + /** * omap3_dpll_recalc - recalculate DPLL rate * @clk: DPLL struct clk @@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { u32 new_div = 0; + u32 unlock_dll = 0; unsigned long validrate, sdrcrate; struct omap_sdrc_params *sp; @@ -729,6 +732,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) if (!sp) return -EINVAL; + if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { + pr_debug("clock: will unlock SDRC DLL\n"); + unlock_dll = 1; + } + pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, validrate); pr_info("clock: SDRC timing params used: %08x %08x %08x\n", @@ -739,7 +747,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) /* REVISIT: Add SDRC_MR changing to this code also */ omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, - sp->actim_ctrlb, new_div); + sp->actim_ctrlb, new_div, unlock_dll); return 0; } -- cgit v1.2.3 From b7aee4bfa7cad909220491214037731c1edb510a Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 12 May 2009 17:27:10 -0600 Subject: OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code The CORE DPLL M2 frequency change code should use pr_debug(), not pr_info(), for its debug messages. Same with omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR .. into pr_err(). Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 12 ++++++------ arch/arm/mach-omap2/clock34xx.c | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-omap2/clock34xx.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 4247a1534411..8935a8b26186 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -547,8 +547,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, const struct clksel_rate *clkr; u32 last_div = 0; - printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", - clk->name, target_rate); + pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", + clk->name, target_rate); *new_div = 1; @@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, /* Sanity check */ if (clkr->div <= last_div) - printk(KERN_ERR "clock: clksel_rate table not sorted " + pr_err("clock: clksel_rate table not sorted " "for clock %s", clk->name); last_div = clkr->div; @@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, } if (!clkr->div) { - printk(KERN_ERR "clock: Could not find divisor for target " + pr_err("clock: Could not find divisor for target " "rate %ld for clock %s parent %s\n", target_rate, clk->name, clk->parent->name); return ~0; @@ -582,8 +582,8 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, *new_div = clkr->div; - printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, - (clk->parent->rate / clkr->div)); + pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, + (clk->parent->rate / clkr->div)); return (clk->parent->rate / clkr->div); } diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 811360af60dc..2ee58fa5dc70 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -737,10 +737,10 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) unlock_dll = 1; } - pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, - validrate); - pr_info("clock: SDRC timing params used: %08x %08x %08x\n", - sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); + pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, + validrate); + pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", + sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); /* REVISIT: SRAM code doesn't support other M2 divisors yet */ WARN_ON(new_div != 1 && new_div != 2); -- cgit v1.2.3 From 7971687094ef48695aa56a0c03416b609bd4d1fd Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 12 May 2009 17:50:30 -0600 Subject: OMAP2xxx clock: rename clk_init_one() to clk_preinit() Rename clk_init_one() to clk_preinit() to distinguish its function from clk_init() and the individual struct clk init functions. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap1/clock.c | 2 +- arch/arm/mach-omap2/clock24xx.c | 2 +- arch/arm/mach-omap2/clock34xx.c | 2 +- arch/arm/plat-omap/clock.c | 4 ++-- arch/arm/plat-omap/include/mach/clock.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-omap2/clock34xx.c') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 336e51dc6127..436eed22801b 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -776,7 +776,7 @@ int __init omap1_clk_init(void) arm_idlect1_mask = ~0; for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) - clk_init_one(c->lk.clk); + clk_preinit(c->lk.clk); cpu_mask = 0; if (cpu_is_omap16xx()) diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index efc59c49341b..cc94672f9e2a 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -722,7 +722,7 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) - clk_init_one(c->lk.clk); + clk_preinit(c->lk.clk); osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 2ee58fa5dc70..62092f282de2 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -964,7 +964,7 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) - clk_init_one(c->lk.clk); + clk_preinit(c->lk.clk); for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) if (c->cpu & cpu_clkflg) { diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 29efc279287a..508c96ab24e9 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -240,13 +240,13 @@ void recalculate_root_clocks(void) } /** - * clk_init_one - initialize any fields in the struct clk before clk init + * clk_preinit - initialize any fields in the struct clk before clk init * @clk: struct clk * to initialize * * Initialize any struct clk fields needed before normal clk initialization * can run. No return value. */ -void clk_init_one(struct clk *clk) +void clk_preinit(struct clk *clk) { INIT_LIST_HEAD(&clk->children); } diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 073a2c5569f0..d7bd19c8ce3c 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -119,7 +119,7 @@ struct clk_functions { extern unsigned int mpurate; extern int clk_init(struct clk_functions *custom_clocks); -extern void clk_init_one(struct clk *clk); +extern void clk_preinit(struct clk *clk); extern int clk_register(struct clk *clk); extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); -- cgit v1.2.3