From 548d849574847b788fe846fe21a41386063be161 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 14:02:46 +0000 Subject: [ARM] omap: introduce clock operations structure Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ad721e0cbf7a..d3213f565d5f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -274,8 +274,8 @@ int _omap2_clk_enable(struct clk *clk) if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) return 0; - if (clk->enable) - return clk->enable(clk); + if (clk->ops && clk->ops->enable) + return clk->ops->enable(clk); if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", @@ -304,8 +304,8 @@ void _omap2_clk_disable(struct clk *clk) if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) return; - if (clk->disable) { - clk->disable(clk); + if (clk->ops && clk->ops->disable) { + clk->ops->disable(clk); return; } -- cgit v1.2.3 From 897dcded6fb6565f4d1c22a55d21f135403db132 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 16:35:03 +0000 Subject: [ARM] omap: provide a NULL clock operations structure ... and use it for clocks which are ALWAYS_ENABLED. These clocks use a non-NULL enable_reg pointer for other purposes (such as selecting clock rates.) Signed-off-by: Russell King --- arch/arm/mach-omap1/clock.c | 3 -- arch/arm/mach-omap1/clock.h | 78 ++++++++++++++---------------- arch/arm/mach-omap2/clock.c | 4 +- arch/arm/mach-omap2/clock24xx.h | 31 ++++++++---- arch/arm/mach-omap2/clock34xx.h | 85 ++++++++++++++++++++------------- arch/arm/plat-omap/clock.c | 23 ++++++++- arch/arm/plat-omap/include/mach/clock.h | 4 +- 7 files changed, 135 insertions(+), 93 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 25ef04da6b06..ff408105ffb2 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -515,9 +515,6 @@ static int omap1_clk_enable_generic(struct clk *clk) __u16 regval16; __u32 regval32; - if (clk->flags & ALWAYS_ENABLED) - return 0; - if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", clk->name); diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 5b93a2a897ad..8673832d829a 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -144,18 +144,18 @@ static struct mpu_rate rate_table[] = { static struct clk ck_ref = { .name = "ck_ref", - .ops = &clkops_generic, + .ops = &clkops_null, .rate = 12000000, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + CLOCK_IN_OMAP310, }; static struct clk ck_dpll1 = { .name = "ck_dpll1", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &ck_ref, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED, + CLOCK_IN_OMAP310 | RATE_PROPAGATES, }; static struct arm_idlect1_clk ck_dpll1out = { @@ -186,11 +186,10 @@ static struct clk sossi_ck = { static struct clk arm_ck = { .name = "arm_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &ck_dpll1, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | - ALWAYS_ENABLED, + CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES, .rate_offset = CKCTL_ARMDIV_OFFSET, .recalc = &omap1_ckctl_recalc, }; @@ -265,9 +264,9 @@ static struct arm_idlect1_clk armwdt_ck = { static struct clk arminth_ck16xx = { .name = "arminth_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &arm_ck, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP16XX, .recalc = &followparent_recalc, /* Note: On 16xx the frequency can be divided by 2 by programming * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 @@ -290,10 +289,10 @@ static struct clk dsp_ck = { static struct clk dspmmu_ck = { .name = "dspmmu_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &ck_dpll1, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - RATE_CKCTL | ALWAYS_ENABLED, + RATE_CKCTL, .rate_offset = CKCTL_DSPMMUDIV_OFFSET, .recalc = &omap1_ckctl_recalc, }; @@ -337,12 +336,12 @@ static struct clk dsptim_ck = { static struct arm_idlect1_clk tc_ck = { .clk = { .name = "tc_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &ck_dpll1, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | - ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, + CLOCK_IDLE_CONTROL, .rate_offset = CKCTL_TCDIV_OFFSET, .recalc = &omap1_ckctl_recalc, }, @@ -351,10 +350,9 @@ static struct arm_idlect1_clk tc_ck = { static struct clk arminth_ck1510 = { .name = "arminth_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .recalc = &followparent_recalc, /* Note: On 1510 the frequency follows TC_CK * @@ -365,10 +363,9 @@ static struct clk arminth_ck1510 = { static struct clk tipb_ck = { /* No-idle controlled by "tc_ck" */ .name = "tipb_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, .recalc = &followparent_recalc, }; @@ -406,18 +403,18 @@ static struct clk tc2_ck = { static struct clk dma_ck = { /* No-idle controlled by "tc_ck" */ .name = "dma_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &tc_ck.clk, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + CLOCK_IN_OMAP310, .recalc = &followparent_recalc, }; static struct clk dma_lcdfree_ck = { .name = "dma_lcdfree_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP16XX, .recalc = &followparent_recalc, }; @@ -451,17 +448,17 @@ static struct arm_idlect1_clk lb_ck = { static struct clk rhea1_ck = { .name = "rhea1_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP16XX, .recalc = &followparent_recalc, }; static struct clk rhea2_ck = { .name = "rhea2_ck", - .ops = &clkops_generic, + .ops = &clkops_null, .parent = &tc_ck.clk, - .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP16XX, .recalc = &followparent_recalc, }; @@ -493,13 +490,12 @@ static struct arm_idlect1_clk lcd_ck_1510 = { static struct clk uart1_1510 = { .name = "uart1_ck", - .ops = &clkops_generic, + .ops = &clkops_null, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 12000000, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ENABLE_REG_32BIT | ALWAYS_ENABLED | - CLOCK_NO_IDLE_PARENT, + ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ .set_rate = &omap1_set_uart_rate, @@ -523,13 +519,13 @@ static struct uart_clk uart1_16xx = { static struct clk uart2_ck = { .name = "uart2_ck", - .ops = &clkops_generic, + .ops = &clkops_null, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 12000000, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | - ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, + CLOCK_NO_IDLE_PARENT, .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ .set_rate = &omap1_set_uart_rate, @@ -538,13 +534,12 @@ static struct clk uart2_ck = { static struct clk uart3_1510 = { .name = "uart3_ck", - .ops = &clkops_generic, + .ops = &clkops_null, /* Direct from ULPD, no real parent */ .parent = &armper_ck.clk, .rate = 12000000, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | - ENABLE_REG_32BIT | ALWAYS_ENABLED | - CLOCK_NO_IDLE_PARENT, + ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ .set_rate = &omap1_set_uart_rate, @@ -680,9 +675,9 @@ static struct clk mmc2_ck = { static struct clk virtual_ck_mpu = { .name = "mpu", - .ops = &clkops_generic, + .ops = &clkops_null, .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_IN_OMAP310 | ALWAYS_ENABLED, + CLOCK_IN_OMAP310, .parent = &arm_ck, /* Is smarter alias for */ .recalc = &followparent_recalc, .set_rate = &omap1_select_table_rate, @@ -694,9 +689,9 @@ remains active during MPU idle whenever this is enabled */ static struct clk i2c_fck = { .name = "i2c_fck", .id = 1, - .ops = &clkops_generic, + .ops = &clkops_null, .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | - CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED, + CLOCK_NO_IDLE_PARENT, .parent = &armxor_ck.clk, .recalc = &followparent_recalc, }; @@ -704,9 +699,8 @@ static struct clk i2c_fck = { static struct clk i2c_ick = { .name = "i2c_ick", .id = 1, - .ops = &clkops_generic, - .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | - ALWAYS_ENABLED, + .ops = &clkops_null, + .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT, .parent = &armper_ck.clk, .recalc = &followparent_recalc, }; diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index d3213f565d5f..fa99c0b71d3f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -271,7 +271,7 @@ int _omap2_clk_enable(struct clk *clk) { u32 regval32; - if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) + if (clk->flags & PARENT_CONTROLS_CLOCK) return 0; if (clk->ops && clk->ops->enable) @@ -301,7 +301,7 @@ void _omap2_clk_disable(struct clk *clk) { u32 regval32; - if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) + if (clk->flags & PARENT_CONTROLS_CLOCK) return; if (clk->ops && clk->ops->disable) { diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 2aa0b5e65608..d4869377307a 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -619,9 +619,10 @@ static struct prcm_config rate_table[] = { /* Base external input clocks */ static struct clk func_32k_ck = { .name = "func_32k_ck", + .ops = &clkops_null, .rate = 32000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, + RATE_FIXED | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &propagate_rate, }; @@ -639,18 +640,20 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ /* Without modem likely 12MHz, with modem likely 13MHz */ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .name = "sys_ck", /* ~ ref_clk also */ + .ops = &clkops_null, .parent = &osc_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | RATE_PROPAGATES, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_sys_clk_recalc, }; static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", + .ops = &clkops_null, .rate = 54000000, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, + RATE_FIXED | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &propagate_rate, }; @@ -679,10 +682,11 @@ static struct dpll_data dpll_dd = { */ static struct clk dpll_ck = { .name = "dpll_ck", + .ops = &clkops_null, .parent = &sys_ck, /* Can be func_32k also */ .dpll_data = &dpll_dd, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | ALWAYS_ENABLED, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_dpllcore_recalc, .set_rate = &omap2_reprogram_dpllcore, @@ -751,9 +755,10 @@ static struct clk func_54m_ck = { static struct clk core_ck = { .name = "core_ck", + .ops = &clkops_null, .parent = &dpll_ck, /* can also be 32k */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | RATE_PROPAGATES, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -837,6 +842,7 @@ static struct clk func_12m_ck = { /* Secure timer, only available in secure mode */ static struct clk wdt1_osc_ck = { .name = "ck_wdt1_osc", + .ops = &clkops_null, /* RMK: missing? */ .parent = &osc_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .recalc = &followparent_recalc, @@ -996,9 +1002,10 @@ static const struct clksel mpu_clksel[] = { static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", + .ops = &clkops_null, .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP | + DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, .clkdm_name = "mpu_clkdm", .init = &omap2_init_clksel_parent, @@ -1168,9 +1175,10 @@ static const struct clksel core_l3_clksel[] = { static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .name = "core_l3_ck", + .ops = &clkops_null, .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP | + DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), @@ -1231,9 +1239,10 @@ static const struct clksel l4_clksel[] = { static struct clk l4_ck = { /* used both as an ick and fck */ .name = "l4_ck", + .ops = &clkops_null, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, + DELAYED_APP | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, @@ -2359,6 +2368,7 @@ static struct clk i2chs1_fck = { static struct clk gpmc_fck = { .name = "gpmc_fck", + .ops = &clkops_null, /* RMK: missing? */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, @@ -2368,6 +2378,7 @@ static struct clk gpmc_fck = { static struct clk sdma_fck = { .name = "sdma_fck", + .ops = &clkops_null, /* RMK: missing? */ .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", @@ -2376,6 +2387,7 @@ static struct clk sdma_fck = { static struct clk sdma_ick = { .name = "sdma_ick", + .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", @@ -2621,8 +2633,9 @@ static struct clk mmchsdb2_fck = { */ static struct clk virt_prcm_set = { .name = "virt_prcm_set", + .ops = &clkops_null, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - ALWAYS_ENABLED | DELAYED_APP, + DELAYED_APP, .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ .set_rate = &omap2_select_table_rate, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 8b188fb9beab..b56fd2897626 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -55,66 +55,66 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk); /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ static struct clk omap_32k_fck = { .name = "omap_32k_fck", + .ops = &clkops_null, .rate = 32768, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; static struct clk secure_32k_fck = { .name = "secure_32k_fck", + .ops = &clkops_null, .rate = 32768, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; /* Virtual source clocks for osc_sys_ck */ static struct clk virt_12m_ck = { .name = "virt_12m_ck", + .ops = &clkops_null, .rate = 12000000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; static struct clk virt_13m_ck = { .name = "virt_13m_ck", + .ops = &clkops_null, .rate = 13000000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; static struct clk virt_16_8m_ck = { .name = "virt_16_8m_ck", + .ops = &clkops_null, .rate = 16800000, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; static struct clk virt_19_2m_ck = { .name = "virt_19_2m_ck", + .ops = &clkops_null, .rate = 19200000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; static struct clk virt_26m_ck = { .name = "virt_26m_ck", + .ops = &clkops_null, .rate = 26000000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; static struct clk virt_38_4m_ck = { .name = "virt_38_4m_ck", + .ops = &clkops_null, .rate = 38400000, - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &propagate_rate, }; @@ -162,13 +162,13 @@ static const struct clksel osc_sys_clksel[] = { /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ static struct clk osc_sys_ck = { .name = "osc_sys_ck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP3430_PRM_CLKSEL, .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, .clksel = osc_sys_clksel, /* REVISIT: deal with autoextclkmode? */ - .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | - ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -187,25 +187,28 @@ static const struct clksel sys_clksel[] = { /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ static struct clk sys_ck = { .name = "sys_ck", + .ops = &clkops_null, .parent = &osc_sys_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, .clksel_mask = OMAP_SYSCLKDIV_MASK, .clksel = sys_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; static struct clk sys_altclk = { .name = "sys_altclk", - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .ops = &clkops_null, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &propagate_rate, }; /* Optional external clock input for some McBSPs */ static struct clk mcbsp_clks = { .name = "mcbsp_clks", - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .ops = &clkops_null, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &propagate_rate, }; @@ -278,9 +281,10 @@ static struct dpll_data dpll1_dd = { static struct clk dpll1_ck = { .name = "dpll1_ck", + .ops = &clkops_null, .parent = &sys_ck, .dpll_data = &dpll1_dd, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .recalc = &omap3_dpll_recalc, }; @@ -398,9 +402,10 @@ static struct dpll_data dpll3_dd = { static struct clk dpll3_ck = { .name = "dpll3_ck", + .ops = &clkops_null, .parent = &sys_ck, .dpll_data = &dpll3_dd, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .recalc = &omap3_dpll_recalc, }; @@ -2266,9 +2271,10 @@ static struct clk gpt1_fck = { static struct clk wkup_32k_fck = { .name = "wkup_32k_fck", + .ops = &clkops_null, .init = &omap2_init_clk_clkdm, .parent = &omap_32k_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2295,8 +2301,9 @@ static struct clk wdt2_fck = { static struct clk wkup_l4_ick = { .name = "wkup_l4_ick", + .ops = &clkops_null, .parent = &sys_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2514,9 +2521,10 @@ static struct clk gpt9_fck = { static struct clk per_32k_alwon_fck = { .name = "per_32k_alwon_fck", + .ops = &clkops_null, .parent = &omap_32k_fck, .clkdm_name = "per_clkdm", - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2859,11 +2867,12 @@ static const struct clksel emu_src_clksel[] = { */ static struct clk emu_src_ck = { .name = "emu_src_ck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2883,11 +2892,12 @@ static const struct clksel pclk_emu_clksel[] = { static struct clk pclk_fck = { .name = "pclk_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2906,11 +2916,12 @@ static const struct clksel pclkx2_emu_clksel[] = { static struct clk pclkx2_fck = { .name = "pclkx2_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2922,22 +2933,24 @@ static const struct clksel atclk_emu_clksel[] = { static struct clk atclk_fck = { .name = "atclk_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk traceclk_src_fck = { .name = "traceclk_src_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2956,11 +2969,12 @@ static const struct clksel traceclk_clksel[] = { static struct clk traceclk_fck = { .name = "traceclk_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2989,6 +3003,7 @@ static struct clk sr2_fck = { static struct clk sr_l4_ick = { .name = "sr_l4_ick", + .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ick, .flags = CLOCK_IN_OMAP343X, .clkdm_name = "core_l4_clkdm", @@ -3000,15 +3015,17 @@ static struct clk sr_l4_ick = { /* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_fck = { .name = "gpt12_fck", + .ops = &clkops_null, .parent = &secure_32k_fck, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; static struct clk wdt1_fck = { .name = "wdt1_fck", + .ops = &clkops_null, .parent = &secure_32k_fck, - .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, + .flags = CLOCK_IN_OMAP343X, .recalc = &followparent_recalc, }; diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index be6aab9c6834..529c4a9f012e 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -358,6 +358,23 @@ void clk_enable_init_clocks(void) } EXPORT_SYMBOL(clk_enable_init_clocks); +/* + * Low level helpers + */ +static int clkll_enable_null(struct clk *clk) +{ + return 0; +} + +static void clkll_disable_null(struct clk *clk) +{ +} + +const struct clkops clkops_null = { + .enable = clkll_enable_null, + .disable = clkll_disable_null, +}; + #ifdef CONFIG_CPU_FREQ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) { @@ -383,8 +400,10 @@ static int __init clk_disable_unused(void) unsigned long flags; list_for_each_entry(ck, &clocks, node) { - if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || - ck->enable_reg == 0) + if (ck->ops == &clkops_null) + continue; + + if (ck->usecount > 0 || ck->enable_reg == 0) continue; spin_lock_irqsave(&clockfw_lock, flags); diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 4fe5084e8cc2..c1e484463ed5 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -125,11 +125,13 @@ extern void clk_deny_idle(struct clk *clk); extern int clk_get_usecount(struct clk *clk); extern void clk_enable_init_clocks(void); +extern const struct clkops clkops_null; + /* Clock flags */ #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ #define RATE_FIXED (1 << 1) /* Fixed clock rate */ #define RATE_PROPAGATES (1 << 2) /* Program children too */ -#define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ +/* bits 3-4 are free */ #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ #define CLOCK_IDLE_CONTROL (1 << 7) -- cgit v1.2.3 From 57137181e3136d4c7b20b4b95b9817efd38f8f07 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 16:48:35 +0000 Subject: [ARM] omap: kill PARENT_CONTROLS_CLOCK PARENT_CONTROLS_CLOCK just makes enable/disable no-op, and is functionally an alias for ALWAYS_ENABLED. This can be handled in the same way, using clkops_null. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 6 - arch/arm/mach-omap2/clock24xx.h | 22 ++-- arch/arm/mach-omap2/clock34xx.h | 196 ++++++++++++++++---------------- arch/arm/plat-omap/include/mach/clock.h | 1 - 4 files changed, 114 insertions(+), 111 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index fa99c0b71d3f..21fbe29810ac 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -271,9 +271,6 @@ int _omap2_clk_enable(struct clk *clk) { u32 regval32; - if (clk->flags & PARENT_CONTROLS_CLOCK) - return 0; - if (clk->ops && clk->ops->enable) return clk->ops->enable(clk); @@ -301,9 +298,6 @@ void _omap2_clk_disable(struct clk *clk) { u32 regval32; - if (clk->flags & PARENT_CONTROLS_CLOCK) - return; - if (clk->ops && clk->ops->disable) { clk->ops->disable(clk); return; diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index d4869377307a..adc00e1064af 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -742,9 +742,10 @@ static const struct clksel func_54m_clksel[] = { static struct clk func_54m_ck = { .name = "func_54m_ck", + .ops = &clkops_null, .parent = &apll54_ck, /* can also be alt_clk */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -783,9 +784,10 @@ static const struct clksel func_96m_clksel[] = { /* The parent of this clock is not selectable on 2420. */ static struct clk func_96m_ck = { .name = "func_96m_ck", + .ops = &clkops_null, .parent = &apll96_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -816,9 +818,10 @@ static const struct clksel func_48m_clksel[] = { static struct clk func_48m_ck = { .name = "func_48m_ck", + .ops = &clkops_null, .parent = &apll96_ck, /* 96M or Alt */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -831,10 +834,11 @@ static struct clk func_48m_ck = { static struct clk func_12m_ck = { .name = "func_12m_ck", + .ops = &clkops_null, .parent = &func_48m_ck, .fixed_div = 4, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, + RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_fixed_divisor_recalc, }; @@ -917,9 +921,9 @@ static const struct clksel sys_clkout_clksel[] = { static struct clk sys_clkout = { .name = "sys_clkout", + .ops = &clkops_null, .parent = &sys_clkout_src, - .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, @@ -954,8 +958,9 @@ static const struct clksel sys_clkout2_clksel[] = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2 = { .name = "sys_clkout2", + .ops = &clkops_null, .parent = &sys_clkout2_src, - .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP242X, .clkdm_name = "wkup_clkdm", .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, @@ -1076,9 +1081,10 @@ static const struct clksel dsp_irate_ick_clksel[] = { /* This clock does not exist as such in the TRM. */ static struct clk dsp_irate_ick = { .name = "dsp_irate_ick", + .ops = &clkops_null, .parent = &dsp_fck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | - CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, + CONFIG_PARTICIPANT, .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, .clksel = dsp_irate_ick_clksel, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index b56fd2897626..203e2bd3b3b0 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -295,9 +295,9 @@ static struct clk dpll1_ck = { */ static struct clk dpll1_x2_ck = { .name = "dpll1_x2_ck", + .ops = &clkops_null, .parent = &dpll1_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap3_clkoutx2_recalc, }; @@ -313,13 +313,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = { */ static struct clk dpll1_x2m2_ck = { .name = "dpll1_x2m2_ck", + .ops = &clkops_null, .parent = &dpll1_x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -368,14 +368,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = { */ static struct clk dpll2_m2_ck = { .name = "dpll2_m2_ck", + .ops = &clkops_null, .parent = &dpll2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -416,9 +416,9 @@ static struct clk dpll3_ck = { */ static struct clk dpll3_x2_ck = { .name = "dpll3_x2_ck", + .ops = &clkops_null, .parent = &dpll3_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap3_clkoutx2_recalc, }; @@ -469,13 +469,13 @@ static const struct clksel div31_dpll3m2_clksel[] = { */ static struct clk dpll3_m2_ck = { .name = "dpll3_m2_ck", + .ops = &clkops_null, .parent = &dpll3_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -487,12 +487,12 @@ static const struct clksel core_ck_clksel[] = { static struct clk core_ck = { .name = "core_ck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = core_ck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -504,12 +504,12 @@ static const struct clksel dpll3_m2x2_ck_clksel[] = { static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = dpll3_m2x2_ck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -522,13 +522,13 @@ static const struct clksel div16_dpll3_clksel[] = { /* This virtual clock is the source for dpll3_m3x2_ck */ static struct clk dpll3_m3_ck = { .name = "dpll3_m3_ck", + .ops = &clkops_null, .parent = &dpll3_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -550,13 +550,13 @@ static const struct clksel emu_core_alwon_ck_clksel[] = { static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", + .ops = &clkops_null, .parent = &dpll3_m3x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = emu_core_alwon_ck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -599,9 +599,9 @@ static struct clk dpll4_ck = { */ static struct clk dpll4_x2_ck = { .name = "dpll4_x2_ck", + .ops = &clkops_null, .parent = &dpll4_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap3_clkoutx2_recalc, }; @@ -613,13 +613,13 @@ static const struct clksel div16_dpll4_clksel[] = { /* This virtual clock is the source for dpll4_m2x2_ck */ static struct clk dpll4_m2_ck = { .name = "dpll4_m2_ck", + .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3430_DIV_96M_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -641,21 +641,21 @@ static const struct clksel omap_96m_alwon_fck_clksel[] = { static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", + .ops = &clkops_null, .parent = &dpll4_m2x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = omap_96m_alwon_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; static struct clk omap_96m_fck = { .name = "omap_96m_fck", + .ops = &clkops_null, .parent = &omap_96m_alwon_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -667,26 +667,26 @@ static const struct clksel cm_96m_fck_clksel[] = { static struct clk cm_96m_fck = { .name = "cm_96m_fck", + .ops = &clkops_null, .parent = &dpll4_m2x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = cm_96m_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; /* This virtual clock is the source for dpll4_m3x2_ck */ static struct clk dpll4_m3_ck = { .name = "dpll4_m3_ck", + .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -709,13 +709,13 @@ static const struct clksel virt_omap_54m_fck_clksel[] = { static struct clk virt_omap_54m_fck = { .name = "virt_omap_54m_fck", + .ops = &clkops_null, .parent = &dpll4_m3x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = virt_omap_54m_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -737,12 +737,12 @@ static const struct clksel omap_54m_clksel[] = { static struct clk omap_54m_fck = { .name = "omap_54m_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_54M, .clksel = omap_54m_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -764,34 +764,34 @@ static const struct clksel omap_48m_clksel[] = { static struct clk omap_48m_fck = { .name = "omap_48m_fck", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_48M, .clksel = omap_48m_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; static struct clk omap_12m_fck = { .name = "omap_12m_fck", + .ops = &clkops_null, .parent = &omap_48m_fck, .fixed_div = 4, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_fixed_divisor_recalc, }; /* This virstual clock is the source for dpll4_m4x2_ck */ static struct clk dpll4_m4_ck = { .name = "dpll4_m4_ck", + .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -808,13 +808,13 @@ static struct clk dpll4_m4x2_ck = { /* This virtual clock is the source for dpll4_m5x2_ck */ static struct clk dpll4_m5_ck = { .name = "dpll4_m5_ck", + .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -831,13 +831,13 @@ static struct clk dpll4_m5x2_ck = { /* This virtual clock is the source for dpll4_m6x2_ck */ static struct clk dpll4_m6_ck = { .name = "dpll4_m6_ck", + .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, .clksel = div16_dpll4_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -854,9 +854,9 @@ static struct clk dpll4_m6x2_ck = { static struct clk emu_per_alwon_ck = { .name = "emu_per_alwon_ck", + .ops = &clkops_null, .parent = &dpll4_m6x2_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -900,13 +900,13 @@ static const struct clksel div16_dpll5_clksel[] = { static struct clk dpll5_m2_ck = { .name = "dpll5_m2_ck", + .ops = &clkops_null, .parent = &dpll5_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -918,13 +918,13 @@ static const struct clksel omap_120m_fck_clksel[] = { static struct clk omap_120m_fck = { .name = "omap_120m_fck", + .ops = &clkops_null, .parent = &dpll5_m2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .clksel = omap_120m_fck_clksel, - .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -986,11 +986,12 @@ static const struct clksel sys_clkout2_clksel[] = { static struct clk sys_clkout2 = { .name = "sys_clkout2", + .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X, .recalc = &omap2_clksel_recalc, }; @@ -998,9 +999,9 @@ static struct clk sys_clkout2 = { static struct clk corex2_fck = { .name = "corex2_fck", + .ops = &clkops_null, .parent = &dpll3_m2x2_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1017,13 +1018,13 @@ static const struct clksel div2_core_clksel[] = { */ static struct clk dpll1_fck = { .name = "dpll1_fck", + .ops = &clkops_null, .parent = &core_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1041,13 +1042,13 @@ static const struct clksel mpu_clksel[] = { static struct clk mpu_ck = { .name = "mpu_ck", + .ops = &clkops_null, .parent = &dpll1_x2m2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = mpu_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "mpu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1066,13 +1067,13 @@ static const struct clksel arm_fck_clksel[] = { static struct clk arm_fck = { .name = "arm_fck", + .ops = &clkops_null, .parent = &mpu_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1084,21 +1085,21 @@ static struct clk arm_fck = { */ static struct clk emu_mpu_alwon_ck = { .name = "emu_mpu_alwon_ck", + .ops = &clkops_null, .parent = &mpu_ck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; static struct clk dpll2_fck = { .name = "dpll2_fck", + .ops = &clkops_null, .parent = &core_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1134,13 +1135,13 @@ static struct clk iva2_ck = { static struct clk l3_ick = { .name = "l3_ick", + .ops = &clkops_null, .parent = &core_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1152,13 +1153,13 @@ static const struct clksel div2_l3_clksel[] = { static struct clk l4_ick = { .name = "l4_ick", + .ops = &clkops_null, .parent = &l3_ick, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, @@ -1171,12 +1172,13 @@ static const struct clksel div2_l4_clksel[] = { static struct clk rm_ick = { .name = "rm_ick", + .ops = &clkops_null, .parent = &l4_ick, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_RM_MASK, .clksel = div2_l4_clksel, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X, .recalc = &omap2_clksel_recalc, }; @@ -1202,21 +1204,22 @@ static struct clk gfx_l3_ck = { static struct clk gfx_l3_fck = { .name = "gfx_l3_fck", + .ops = &clkops_null, .parent = &gfx_l3_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_l3_clksel, - .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gfx_l3_ick = { .name = "gfx_l3_ick", + .ops = &clkops_null, .parent = &gfx_l3_ck, - .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP3430ES1, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; @@ -1365,9 +1368,9 @@ static struct clk usbtll_fck = { static struct clk core_96m_fck = { .name = "core_96m_fck", + .ops = &clkops_null, .parent = &omap_96m_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1499,9 +1502,9 @@ static struct clk mcbsp1_fck = { static struct clk core_48m_fck = { .name = "core_48m_fck", + .ops = &clkops_null, .parent = &omap_48m_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1577,9 +1580,9 @@ static struct clk fshostusb_fck = { static struct clk core_12m_fck = { .name = "core_12m_fck", + .ops = &clkops_null, .parent = &omap_12m_fck, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1625,9 +1628,10 @@ static struct clk ssi_ssr_fck = { static struct clk ssi_sst_fck = { .name = "ssi_sst_fck", + .ops = &clkops_null, .parent = &ssi_ssr_fck, .fixed_div = 2, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X, .recalc = &omap2_fixed_divisor_recalc, }; @@ -1641,10 +1645,10 @@ static struct clk ssi_sst_fck = { */ static struct clk core_l3_ick = { .name = "core_l3_ick", + .ops = &clkops_null, .parent = &l3_ick, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1671,9 +1675,9 @@ static struct clk sdrc_ick = { static struct clk gpmc_fck = { .name = "gpmc_fck", + .ops = &clkops_null, .parent = &core_l3_ick, - .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | - ENABLE_ON_INIT, + .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, /* huh? */ .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1682,9 +1686,9 @@ static struct clk gpmc_fck = { static struct clk security_l3_ick = { .name = "security_l3_ick", + .ops = &clkops_null, .parent = &l3_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1701,10 +1705,10 @@ static struct clk pka_ick = { static struct clk core_l4_ick = { .name = "core_l4_ick", + .ops = &clkops_null, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1984,9 +1988,9 @@ static struct clk omapctrl_ick = { static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2028,9 +2032,9 @@ static struct clk usb_l4_ick = { static struct clk security_l4_ick2 = { .name = "security_l4_ick2", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2387,20 +2391,20 @@ static struct clk gpt1_ick = { static struct clk per_96m_fck = { .name = "per_96m_fck", + .ops = &clkops_null, .parent = &omap_96m_alwon_fck, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk per_48m_fck = { .name = "per_48m_fck", + .ops = &clkops_null, .parent = &omap_48m_fck, .init = &omap2_init_clk_clkdm, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2590,9 +2594,9 @@ static struct clk wdt3_fck = { static struct clk per_l4_ick = { .name = "per_l4_ick", + .ops = &clkops_null, .parent = &l4_ick, - .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | - PARENT_CONTROLS_CLOCK, + .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index c1e484463ed5..40a2ac353ded 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -148,7 +148,6 @@ extern const struct clkops clkops_null; #define CLOCK_IN_OMAP242X (1 << 25) #define CLOCK_IN_OMAP243X (1 << 26) #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ -#define PARENT_CONTROLS_CLOCK (1 << 28) #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ -- cgit v1.2.3 From b36ee724208358bd892ad279efce629740517149 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 17:59:52 +0000 Subject: [ARM] omap: add default .ops to all remaining OMAP2 clocks Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 35 ++++++----- arch/arm/mach-omap2/clock.h | 2 + arch/arm/mach-omap2/clock24xx.h | 115 ++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/clock34xx.h | 133 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 271 insertions(+), 14 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 21fbe29810ac..8c09711d2eaf 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -264,16 +264,10 @@ static void omap2_clk_wait_ready(struct clk *clk) omap2_wait_clock_ready(st_reg, bit, clk->name); } -/* Enables clock without considering parent dependencies or use count - * REVISIT: Maybe change this to use clk->enable like on omap1? - */ -int _omap2_clk_enable(struct clk *clk) +static int omap2_dflt_clk_enable_wait(struct clk *clk) { u32 regval32; - if (clk->ops && clk->ops->enable) - return clk->ops->enable(clk); - if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", clk->name); @@ -293,16 +287,10 @@ int _omap2_clk_enable(struct clk *clk) return 0; } -/* Disables clock without considering parent dependencies or use count */ -void _omap2_clk_disable(struct clk *clk) +static void omap2_dflt_clk_disable(struct clk *clk) { u32 regval32; - if (clk->ops && clk->ops->disable) { - clk->ops->disable(clk); - return; - } - if (clk->enable_reg == NULL) { /* * 'Independent' here refers to a clock which is not @@ -322,6 +310,25 @@ void _omap2_clk_disable(struct clk *clk) wmb(); } +const struct clkops clkops_omap2_dflt_wait = { + .enable = omap2_dflt_clk_enable_wait, + .disable = omap2_dflt_clk_disable, +}; + +/* Enables clock without considering parent dependencies or use count + * REVISIT: Maybe change this to use clk->enable like on omap1? + */ +static int _omap2_clk_enable(struct clk *clk) +{ + return clk->ops->enable(clk); +} + +/* Disables clock without considering parent dependencies or use count */ +static void _omap2_clk_disable(struct clk *clk) +{ + clk->ops->disable(clk); +} + void omap2_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1fb330e0847d..d4bdb59b3000 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -51,6 +51,8 @@ u32 omap2_get_dpll_rate(struct clk *clk); int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); void omap2_clk_prepare_for_reboot(void); +extern const struct clkops clkops_omap2_dflt_wait; + extern u8 cpu_mask; /* clksel_rate data common to 24xx/343x */ diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index adc00e1064af..b59bf902ce7c 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -890,6 +890,7 @@ static const struct clksel common_clkout_src_clksel[] = { static struct clk sys_clkout_src = { .name = "sys_clkout_src", + .ops = &clkops_omap2_dflt_wait, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES, @@ -936,6 +937,7 @@ static struct clk sys_clkout = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", + .ops = &clkops_omap2_dflt_wait, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", @@ -972,6 +974,7 @@ static struct clk sys_clkout2 = { static struct clk emul_ck = { .name = "emul_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "wkup_clkdm", @@ -1051,6 +1054,7 @@ static const struct clksel dsp_fck_clksel[] = { static struct clk dsp_fck = { .name = "dsp_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, @@ -1096,6 +1100,7 @@ static struct clk dsp_irate_ick = { /* 2420 only */ static struct clk dsp_ick = { .name = "dsp_ick", /* apparently ipi and isp */ + .ops = &clkops_omap2_dflt_wait, .parent = &dsp_irate_ick, .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), @@ -1105,6 +1110,7 @@ static struct clk dsp_ick = { /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ static struct clk iva2_1_ick = { .name = "iva2_1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &dsp_irate_ick, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), @@ -1118,6 +1124,7 @@ static struct clk iva2_1_ick = { */ static struct clk iva1_ifck = { .name = "iva1_ifck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, @@ -1135,6 +1142,7 @@ static struct clk iva1_ifck = { /* IVA1 mpu/int/i/f clocks are /2 of parent */ static struct clk iva1_mpu_int_ifck = { .name = "iva1_mpu_int_ifck", + .ops = &clkops_omap2_dflt_wait, .parent = &iva1_ifck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "iva1_clkdm", @@ -1211,6 +1219,7 @@ static const struct clksel usb_l4_ick_clksel[] = { /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ static struct clk usb_l4_ick = { /* FS-USB interface clock */ .name = "usb_l4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, @@ -1284,6 +1293,7 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = { static struct clk ssi_ssr_sst_fck = { .name = "ssi_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, @@ -1320,6 +1330,7 @@ static const struct clksel gfx_fck_clksel[] = { static struct clk gfx_3d_fck = { .name = "gfx_3d_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "gfx_clkdm", @@ -1335,6 +1346,7 @@ static struct clk gfx_3d_fck = { static struct clk gfx_2d_fck = { .name = "gfx_2d_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "gfx_clkdm", @@ -1350,6 +1362,7 @@ static struct clk gfx_2d_fck = { static struct clk gfx_ick = { .name = "gfx_ick", /* From l3 */ + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "gfx_clkdm", @@ -1380,6 +1393,7 @@ static const struct clksel mdm_ick_clksel[] = { static struct clk mdm_ick = { /* used both as a ick and fck */ .name = "mdm_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "mdm_clkdm", @@ -1395,6 +1409,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ static struct clk mdm_osc_ck = { .name = "mdm_osc_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &osc_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "mdm_clkdm", @@ -1440,6 +1455,7 @@ static const struct clksel dss1_fck_clksel[] = { static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, /* really both l3 and l4 */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "dss_clkdm", @@ -1450,6 +1466,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ static struct clk dss1_fck = { .name = "dss1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, /* Core or sys */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, @@ -1483,6 +1500,7 @@ static const struct clksel dss2_fck_clksel[] = { static struct clk dss2_fck = { /* Alt clk used in power management */ .name = "dss2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, @@ -1498,6 +1516,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ static struct clk dss_54m_fck = { /* Alt clk used in power management */ .name = "dss_54m_fck", /* 54m tv clk */ + .ops = &clkops_omap2_dflt_wait, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "dss_clkdm", @@ -1526,6 +1545,7 @@ static const struct clksel omap24xx_gpt_clksel[] = { static struct clk gpt1_ick = { .name = "gpt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1536,6 +1556,7 @@ static struct clk gpt1_ick = { static struct clk gpt1_fck = { .name = "gpt1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1552,6 +1573,7 @@ static struct clk gpt1_fck = { static struct clk gpt2_ick = { .name = "gpt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1562,6 +1584,7 @@ static struct clk gpt2_ick = { static struct clk gpt2_fck = { .name = "gpt2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1576,6 +1599,7 @@ static struct clk gpt2_fck = { static struct clk gpt3_ick = { .name = "gpt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1586,6 +1610,7 @@ static struct clk gpt3_ick = { static struct clk gpt3_fck = { .name = "gpt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1600,6 +1625,7 @@ static struct clk gpt3_fck = { static struct clk gpt4_ick = { .name = "gpt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1610,6 +1636,7 @@ static struct clk gpt4_ick = { static struct clk gpt4_fck = { .name = "gpt4_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1624,6 +1651,7 @@ static struct clk gpt4_fck = { static struct clk gpt5_ick = { .name = "gpt5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1634,6 +1662,7 @@ static struct clk gpt5_ick = { static struct clk gpt5_fck = { .name = "gpt5_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1648,6 +1677,7 @@ static struct clk gpt5_fck = { static struct clk gpt6_ick = { .name = "gpt6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1658,6 +1688,7 @@ static struct clk gpt6_ick = { static struct clk gpt6_fck = { .name = "gpt6_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1672,6 +1703,7 @@ static struct clk gpt6_fck = { static struct clk gpt7_ick = { .name = "gpt7_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1681,6 +1713,7 @@ static struct clk gpt7_ick = { static struct clk gpt7_fck = { .name = "gpt7_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1695,6 +1728,7 @@ static struct clk gpt7_fck = { static struct clk gpt8_ick = { .name = "gpt8_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1705,6 +1739,7 @@ static struct clk gpt8_ick = { static struct clk gpt8_fck = { .name = "gpt8_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1719,6 +1754,7 @@ static struct clk gpt8_fck = { static struct clk gpt9_ick = { .name = "gpt9_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1729,6 +1765,7 @@ static struct clk gpt9_ick = { static struct clk gpt9_fck = { .name = "gpt9_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1743,6 +1780,7 @@ static struct clk gpt9_fck = { static struct clk gpt10_ick = { .name = "gpt10_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1753,6 +1791,7 @@ static struct clk gpt10_ick = { static struct clk gpt10_fck = { .name = "gpt10_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1767,6 +1806,7 @@ static struct clk gpt10_fck = { static struct clk gpt11_ick = { .name = "gpt11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1777,6 +1817,7 @@ static struct clk gpt11_ick = { static struct clk gpt11_fck = { .name = "gpt11_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1791,6 +1832,7 @@ static struct clk gpt11_fck = { static struct clk gpt12_ick = { .name = "gpt12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1801,6 +1843,7 @@ static struct clk gpt12_ick = { static struct clk gpt12_fck = { .name = "gpt12_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -1815,6 +1858,7 @@ static struct clk gpt12_fck = { static struct clk mcbsp1_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1826,6 +1870,7 @@ static struct clk mcbsp1_ick = { static struct clk mcbsp1_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1837,6 +1882,7 @@ static struct clk mcbsp1_fck = { static struct clk mcbsp2_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1848,6 +1894,7 @@ static struct clk mcbsp2_ick = { static struct clk mcbsp2_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1859,6 +1906,7 @@ static struct clk mcbsp2_fck = { static struct clk mcbsp3_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, @@ -1870,6 +1918,7 @@ static struct clk mcbsp3_ick = { static struct clk mcbsp3_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, @@ -1881,6 +1930,7 @@ static struct clk mcbsp3_fck = { static struct clk mcbsp4_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, @@ -1892,6 +1942,7 @@ static struct clk mcbsp4_ick = { static struct clk mcbsp4_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, @@ -1903,6 +1954,7 @@ static struct clk mcbsp4_fck = { static struct clk mcbsp5_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, @@ -1914,6 +1966,7 @@ static struct clk mcbsp5_ick = { static struct clk mcbsp5_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, @@ -1925,6 +1978,7 @@ static struct clk mcbsp5_fck = { static struct clk mcspi1_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, .clkdm_name = "core_l4_clkdm", @@ -1936,6 +1990,7 @@ static struct clk mcspi1_ick = { static struct clk mcspi1_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1947,6 +2002,7 @@ static struct clk mcspi1_fck = { static struct clk mcspi2_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1958,6 +2014,7 @@ static struct clk mcspi2_ick = { static struct clk mcspi2_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -1969,6 +2026,7 @@ static struct clk mcspi2_fck = { static struct clk mcspi3_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, @@ -1980,6 +2038,7 @@ static struct clk mcspi3_ick = { static struct clk mcspi3_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X, @@ -1991,6 +2050,7 @@ static struct clk mcspi3_fck = { static struct clk uart1_ick = { .name = "uart1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2001,6 +2061,7 @@ static struct clk uart1_ick = { static struct clk uart1_fck = { .name = "uart1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2011,6 +2072,7 @@ static struct clk uart1_fck = { static struct clk uart2_ick = { .name = "uart2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2021,6 +2083,7 @@ static struct clk uart2_ick = { static struct clk uart2_fck = { .name = "uart2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2031,6 +2094,7 @@ static struct clk uart2_fck = { static struct clk uart3_ick = { .name = "uart3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2041,6 +2105,7 @@ static struct clk uart3_ick = { static struct clk uart3_fck = { .name = "uart3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2051,6 +2116,7 @@ static struct clk uart3_fck = { static struct clk gpios_ick = { .name = "gpios_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2061,6 +2127,7 @@ static struct clk gpios_ick = { static struct clk gpios_fck = { .name = "gpios_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "wkup_clkdm", @@ -2071,6 +2138,7 @@ static struct clk gpios_fck = { static struct clk mpu_wdt_ick = { .name = "mpu_wdt_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2081,6 +2149,7 @@ static struct clk mpu_wdt_ick = { static struct clk mpu_wdt_fck = { .name = "mpu_wdt_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "wkup_clkdm", @@ -2091,6 +2160,7 @@ static struct clk mpu_wdt_fck = { static struct clk sync_32k_ick = { .name = "sync_32k_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, @@ -2102,6 +2172,7 @@ static struct clk sync_32k_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2112,6 +2183,7 @@ static struct clk wdt1_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, @@ -2123,6 +2195,7 @@ static struct clk omapctrl_ick = { static struct clk icr_ick = { .name = "icr_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2133,6 +2206,7 @@ static struct clk icr_ick = { static struct clk cam_ick = { .name = "cam_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2148,6 +2222,7 @@ static struct clk cam_ick = { */ static struct clk cam_fck = { .name = "cam_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", @@ -2158,6 +2233,7 @@ static struct clk cam_fck = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2168,6 +2244,7 @@ static struct clk mailboxes_ick = { static struct clk wdt4_ick = { .name = "wdt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2178,6 +2255,7 @@ static struct clk wdt4_ick = { static struct clk wdt4_fck = { .name = "wdt4_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2188,6 +2266,7 @@ static struct clk wdt4_fck = { static struct clk wdt3_ick = { .name = "wdt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2198,6 +2277,7 @@ static struct clk wdt3_ick = { static struct clk wdt3_fck = { .name = "wdt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2208,6 +2288,7 @@ static struct clk wdt3_fck = { static struct clk mspro_ick = { .name = "mspro_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2218,6 +2299,7 @@ static struct clk mspro_ick = { static struct clk mspro_fck = { .name = "mspro_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2228,6 +2310,7 @@ static struct clk mspro_fck = { static struct clk mmc_ick = { .name = "mmc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2238,6 +2321,7 @@ static struct clk mmc_ick = { static struct clk mmc_fck = { .name = "mmc_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2248,6 +2332,7 @@ static struct clk mmc_fck = { static struct clk fac_ick = { .name = "fac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2258,6 +2343,7 @@ static struct clk fac_ick = { static struct clk fac_fck = { .name = "fac_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2268,6 +2354,7 @@ static struct clk fac_fck = { static struct clk eac_ick = { .name = "eac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2278,6 +2365,7 @@ static struct clk eac_ick = { static struct clk eac_fck = { .name = "eac_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2288,6 +2376,7 @@ static struct clk eac_fck = { static struct clk hdq_ick = { .name = "hdq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2298,6 +2387,7 @@ static struct clk hdq_ick = { static struct clk hdq_fck = { .name = "hdq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2308,6 +2398,7 @@ static struct clk hdq_fck = { static struct clk i2c2_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -2319,6 +2410,7 @@ static struct clk i2c2_ick = { static struct clk i2c2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X, @@ -2330,6 +2422,7 @@ static struct clk i2c2_fck = { static struct clk i2chs2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, @@ -2341,6 +2434,7 @@ static struct clk i2chs2_fck = { static struct clk i2c1_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, @@ -2352,6 +2446,7 @@ static struct clk i2c1_ick = { static struct clk i2c1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_12m_ck, .flags = CLOCK_IN_OMAP242X, @@ -2363,6 +2458,7 @@ static struct clk i2c1_fck = { static struct clk i2chs1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, @@ -2402,6 +2498,7 @@ static struct clk sdma_ick = { static struct clk vlynq_ick = { .name = "vlynq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "core_l3_clkdm", @@ -2437,6 +2534,7 @@ static const struct clksel vlynq_fck_clksel[] = { static struct clk vlynq_fck = { .name = "vlynq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | DELAYED_APP, .clkdm_name = "core_l3_clkdm", @@ -2453,6 +2551,7 @@ static struct clk vlynq_fck = { static struct clk sdrc_ick = { .name = "sdrc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, .clkdm_name = "core_l4_clkdm", @@ -2463,6 +2562,7 @@ static struct clk sdrc_ick = { static struct clk des_ick = { .name = "des_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2473,6 +2573,7 @@ static struct clk des_ick = { static struct clk sha_ick = { .name = "sha_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2483,6 +2584,7 @@ static struct clk sha_ick = { static struct clk rng_ick = { .name = "rng_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2493,6 +2595,7 @@ static struct clk rng_ick = { static struct clk aes_ick = { .name = "aes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2503,6 +2606,7 @@ static struct clk aes_ick = { static struct clk pka_ick = { .name = "pka_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l4_clkdm", @@ -2513,6 +2617,7 @@ static struct clk pka_ick = { static struct clk usb_fck = { .name = "usb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_48m_ck, .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, .clkdm_name = "core_l3_clkdm", @@ -2523,6 +2628,7 @@ static struct clk usb_fck = { static struct clk usbhs_ick = { .name = "usbhs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", @@ -2533,6 +2639,7 @@ static struct clk usbhs_ick = { static struct clk mmchs1_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2543,6 +2650,7 @@ static struct clk mmchs1_ick = { static struct clk mmchs1_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", @@ -2553,6 +2661,7 @@ static struct clk mmchs1_fck = { static struct clk mmchs2_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, @@ -2564,6 +2673,7 @@ static struct clk mmchs2_ick = { static struct clk mmchs2_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP243X, @@ -2574,6 +2684,7 @@ static struct clk mmchs2_fck = { static struct clk gpio5_ick = { .name = "gpio5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2584,6 +2695,7 @@ static struct clk gpio5_ick = { static struct clk gpio5_fck = { .name = "gpio5_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2594,6 +2706,7 @@ static struct clk gpio5_fck = { static struct clk mdm_intc_ick = { .name = "mdm_intc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2604,6 +2717,7 @@ static struct clk mdm_intc_ick = { static struct clk mmchsdb1_fck = { .name = "mmchsdb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2614,6 +2728,7 @@ static struct clk mmchsdb1_fck = { static struct clk mmchsdb2_fck = { .name = "mmchsdb_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &func_32k_ck, .flags = CLOCK_IN_OMAP243X, diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 203e2bd3b3b0..0d6a11ca132d 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -216,6 +216,7 @@ static struct clk mcbsp_clks = { static struct clk sys_clkout1 = { .name = "sys_clkout1", + .ops = &clkops_omap2_dflt_wait, .parent = &osc_sys_ck, .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, @@ -535,6 +536,7 @@ static struct clk dpll3_m3_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll3_m3x2_ck = { .name = "dpll3_m3x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll3_m3_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, @@ -626,6 +628,7 @@ static struct clk dpll4_m2_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m2x2_ck = { .name = "dpll4_m2x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m2_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, @@ -693,6 +696,7 @@ static struct clk dpll4_m3_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m3x2_ck = { .name = "dpll4_m3x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m3_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), @@ -798,6 +802,7 @@ static struct clk dpll4_m4_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m4x2_ck = { .name = "dpll4_m4x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m4_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, @@ -821,6 +826,7 @@ static struct clk dpll4_m5_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m5x2_ck = { .name = "dpll4_m5x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m5_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, @@ -844,6 +850,7 @@ static struct clk dpll4_m6_ck = { /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m6x2_ck = { .name = "dpll4_m6x2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m6_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), @@ -960,6 +967,7 @@ static const struct clksel clkout2_src_clksel[] = { static struct clk clkout2_src_ck = { .name = "clkout2_src_ck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP3430_CM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, @@ -1118,6 +1126,7 @@ static const struct clksel iva2_clksel[] = { static struct clk iva2_ck = { .name = "iva2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll2_m2_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), @@ -1194,6 +1203,7 @@ static const struct clksel gfx_l3_clksel[] = { /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ static struct clk gfx_l3_ck = { .name = "gfx_l3_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), @@ -1226,6 +1236,7 @@ static struct clk gfx_l3_ick = { static struct clk gfx_cg1_ck = { .name = "gfx_cg1_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), @@ -1237,6 +1248,7 @@ static struct clk gfx_cg1_ck = { static struct clk gfx_cg2_ck = { .name = "gfx_cg2_ck", + .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), @@ -1268,6 +1280,7 @@ static const struct clksel sgx_clksel[] = { static struct clk sgx_fck = { .name = "sgx_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, @@ -1281,6 +1294,7 @@ static struct clk sgx_fck = { static struct clk sgx_ick = { .name = "sgx_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), @@ -1294,6 +1308,7 @@ static struct clk sgx_ick = { static struct clk d2d_26m_fck = { .name = "d2d_26m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1311,6 +1326,7 @@ static const struct clksel omap343x_gpt_clksel[] = { static struct clk gpt10_fck = { .name = "gpt10_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1325,6 +1341,7 @@ static struct clk gpt10_fck = { static struct clk gpt11_fck = { .name = "gpt11_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1339,6 +1356,7 @@ static struct clk gpt11_fck = { static struct clk cpefuse_fck = { .name = "cpefuse_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, @@ -1348,6 +1366,7 @@ static struct clk cpefuse_fck = { static struct clk ts_fck = { .name = "ts_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_32k_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_TS_SHIFT, @@ -1357,6 +1376,7 @@ static struct clk ts_fck = { static struct clk usbtll_fck = { .name = "usbtll_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_120m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, @@ -1377,6 +1397,7 @@ static struct clk core_96m_fck = { static struct clk mmchs3_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1388,6 +1409,7 @@ static struct clk mmchs3_fck = { static struct clk mmchs2_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1399,6 +1421,7 @@ static struct clk mmchs2_fck = { static struct clk mspro_fck = { .name = "mspro_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, @@ -1409,6 +1432,7 @@ static struct clk mspro_fck = { static struct clk mmchs1_fck = { .name = "mmchs_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, @@ -1419,6 +1443,7 @@ static struct clk mmchs1_fck = { static struct clk i2c3_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1430,6 +1455,7 @@ static struct clk i2c3_fck = { static struct clk i2c2_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1441,6 +1467,7 @@ static struct clk i2c2_fck = { static struct clk i2c1_fck = { .name = "i2c_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1472,6 +1499,7 @@ static const struct clksel mcbsp_15_clksel[] = { static struct clk mcbsp5_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 5, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1486,6 +1514,7 @@ static struct clk mcbsp5_fck = { static struct clk mcbsp1_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1511,6 +1540,7 @@ static struct clk core_48m_fck = { static struct clk mcspi4_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1521,6 +1551,7 @@ static struct clk mcspi4_fck = { static struct clk mcspi3_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1531,6 +1562,7 @@ static struct clk mcspi3_fck = { static struct clk mcspi2_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1541,6 +1573,7 @@ static struct clk mcspi2_fck = { static struct clk mcspi1_fck = { .name = "mcspi_fck", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), @@ -1551,6 +1584,7 @@ static struct clk mcspi1_fck = { static struct clk uart2_fck = { .name = "uart2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, @@ -1560,6 +1594,7 @@ static struct clk uart2_fck = { static struct clk uart1_fck = { .name = "uart1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, @@ -1569,6 +1604,7 @@ static struct clk uart1_fck = { static struct clk fshostusb_fck = { .name = "fshostusb_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, @@ -1589,6 +1625,7 @@ static struct clk core_12m_fck = { static struct clk hdq_fck = { .name = "hdq_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &core_12m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, @@ -1615,6 +1652,7 @@ static const struct clksel ssi_ssr_clksel[] = { static struct clk ssi_ssr_fck = { .name = "ssi_ssr_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, @@ -1655,6 +1693,7 @@ static struct clk core_l3_ick = { static struct clk hsotgusb_ick = { .name = "hsotgusb_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, @@ -1665,6 +1704,7 @@ static struct clk hsotgusb_ick = { static struct clk sdrc_ick = { .name = "sdrc_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SDRC_SHIFT, @@ -1694,6 +1734,7 @@ static struct clk security_l3_ick = { static struct clk pka_ick = { .name = "pka_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_PKA_SHIFT, @@ -1715,6 +1756,7 @@ static struct clk core_l4_ick = { static struct clk usbtll_ick = { .name = "usbtll_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, @@ -1725,6 +1767,7 @@ static struct clk usbtll_ick = { static struct clk mmchs3_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1737,6 +1780,7 @@ static struct clk mmchs3_ick = { /* Intersystem Communication Registers - chassis mode only */ static struct clk icr_ick = { .name = "icr_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, @@ -1747,6 +1791,7 @@ static struct clk icr_ick = { static struct clk aes2_ick = { .name = "aes2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, @@ -1757,6 +1802,7 @@ static struct clk aes2_ick = { static struct clk sha12_ick = { .name = "sha12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, @@ -1767,6 +1813,7 @@ static struct clk sha12_ick = { static struct clk des2_ick = { .name = "des2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, @@ -1777,6 +1824,7 @@ static struct clk des2_ick = { static struct clk mmchs2_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1788,6 +1836,7 @@ static struct clk mmchs2_ick = { static struct clk mmchs1_ick = { .name = "mmchs_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, @@ -1798,6 +1847,7 @@ static struct clk mmchs1_ick = { static struct clk mspro_ick = { .name = "mspro_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, @@ -1808,6 +1858,7 @@ static struct clk mspro_ick = { static struct clk hdq_ick = { .name = "hdq_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, @@ -1818,6 +1869,7 @@ static struct clk hdq_ick = { static struct clk mcspi4_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1829,6 +1881,7 @@ static struct clk mcspi4_ick = { static struct clk mcspi3_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1840,6 +1893,7 @@ static struct clk mcspi3_ick = { static struct clk mcspi2_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1851,6 +1905,7 @@ static struct clk mcspi2_ick = { static struct clk mcspi1_ick = { .name = "mcspi_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1862,6 +1917,7 @@ static struct clk mcspi1_ick = { static struct clk i2c3_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1873,6 +1929,7 @@ static struct clk i2c3_ick = { static struct clk i2c2_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1884,6 +1941,7 @@ static struct clk i2c2_ick = { static struct clk i2c1_ick = { .name = "i2c_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1895,6 +1953,7 @@ static struct clk i2c1_ick = { static struct clk uart2_ick = { .name = "uart2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, @@ -1905,6 +1964,7 @@ static struct clk uart2_ick = { static struct clk uart1_ick = { .name = "uart1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, @@ -1915,6 +1975,7 @@ static struct clk uart1_ick = { static struct clk gpt11_ick = { .name = "gpt11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, @@ -1925,6 +1986,7 @@ static struct clk gpt11_ick = { static struct clk gpt10_ick = { .name = "gpt10_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, @@ -1935,6 +1997,7 @@ static struct clk gpt10_ick = { static struct clk mcbsp5_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 5, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1946,6 +2009,7 @@ static struct clk mcbsp5_ick = { static struct clk mcbsp1_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 1, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -1957,6 +2021,7 @@ static struct clk mcbsp1_ick = { static struct clk fac_ick = { .name = "fac_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, @@ -1967,6 +2032,7 @@ static struct clk fac_ick = { static struct clk mailboxes_ick = { .name = "mailboxes_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, @@ -1977,6 +2043,7 @@ static struct clk mailboxes_ick = { static struct clk omapctrl_ick = { .name = "omapctrl_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, @@ -1997,6 +2064,7 @@ static struct clk ssi_l4_ick = { static struct clk ssi_ick = { .name = "ssi_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, @@ -2015,6 +2083,7 @@ static const struct clksel usb_l4_clksel[] = { static struct clk usb_l4_ick = { .name = "usb_l4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), @@ -2040,6 +2109,7 @@ static struct clk security_l4_ick2 = { static struct clk aes1_ick = { .name = "aes1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_AES1_SHIFT, @@ -2049,6 +2119,7 @@ static struct clk aes1_ick = { static struct clk rng_ick = { .name = "rng_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_RNG_SHIFT, @@ -2058,6 +2129,7 @@ static struct clk rng_ick = { static struct clk sha11_ick = { .name = "sha11_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_SHA11_SHIFT, @@ -2067,6 +2139,7 @@ static struct clk sha11_ick = { static struct clk des1_ick = { .name = "des1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_DES1_SHIFT, @@ -2083,6 +2156,7 @@ static const struct clksel dss1_alwon_fck_clksel[] = { static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m4x2_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2097,6 +2171,7 @@ static struct clk dss1_alwon_fck = { static struct clk dss_tv_fck = { .name = "dss_tv_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_54m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2108,6 +2183,7 @@ static struct clk dss_tv_fck = { static struct clk dss_96m_fck = { .name = "dss_96m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_96m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2119,6 +2195,7 @@ static struct clk dss_96m_fck = { static struct clk dss2_alwon_fck = { .name = "dss2_alwon_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2131,6 +2208,7 @@ static struct clk dss2_alwon_fck = { static struct clk dss_ick = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), @@ -2150,6 +2228,7 @@ static const struct clksel cam_mclk_clksel[] = { static struct clk cam_mclk = { .name = "cam_mclk", + .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m5x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), @@ -2165,6 +2244,7 @@ static struct clk cam_mclk = { static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), @@ -2178,6 +2258,7 @@ static struct clk cam_ick = { static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_120m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), @@ -2189,6 +2270,7 @@ static struct clk usbhost_120m_fck = { static struct clk usbhost_48m_fck = { .name = "usbhost_48m_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &omap_48m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), @@ -2201,6 +2283,7 @@ static struct clk usbhost_48m_fck = { static struct clk usbhost_ick = { /* Handles both L3 and L4 clocks */ .name = "usbhost_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), @@ -2212,6 +2295,7 @@ static struct clk usbhost_ick = { static struct clk usbhost_sar_fck = { .name = "usbhost_sar_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &osc_sys_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), @@ -2249,6 +2333,7 @@ static const struct clksel usim_clksel[] = { /* 3430ES2 only */ static struct clk usim_fck = { .name = "usim_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, @@ -2262,6 +2347,7 @@ static struct clk usim_fck = { /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ static struct clk gpt1_fck = { .name = "gpt1_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, @@ -2285,6 +2371,7 @@ static struct clk wkup_32k_fck = { static struct clk gpio1_dbck = { .name = "gpio1_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, @@ -2295,6 +2382,7 @@ static struct clk gpio1_dbck = { static struct clk wdt2_fck = { .name = "wdt2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, @@ -2316,6 +2404,7 @@ static struct clk wkup_l4_ick = { /* Never specifically named in the TRM, so we have to infer a likely name */ static struct clk usim_ick = { .name = "usim_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, @@ -2326,6 +2415,7 @@ static struct clk usim_ick = { static struct clk wdt2_ick = { .name = "wdt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, @@ -2336,6 +2426,7 @@ static struct clk wdt2_ick = { static struct clk wdt1_ick = { .name = "wdt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, @@ -2346,6 +2437,7 @@ static struct clk wdt1_ick = { static struct clk gpio1_ick = { .name = "gpio1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, @@ -2356,6 +2448,7 @@ static struct clk gpio1_ick = { static struct clk omap_32ksync_ick = { .name = "omap_32ksync_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, @@ -2367,6 +2460,7 @@ static struct clk omap_32ksync_ick = { /* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_ick = { .name = "gpt12_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, @@ -2377,6 +2471,7 @@ static struct clk gpt12_ick = { static struct clk gpt1_ick = { .name = "gpt1_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, @@ -2411,6 +2506,7 @@ static struct clk per_48m_fck = { static struct clk uart3_fck = { .name = "uart3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_48m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, @@ -2421,6 +2517,7 @@ static struct clk uart3_fck = { static struct clk gpt2_fck = { .name = "gpt2_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, @@ -2434,6 +2531,7 @@ static struct clk gpt2_fck = { static struct clk gpt3_fck = { .name = "gpt3_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, @@ -2447,6 +2545,7 @@ static struct clk gpt3_fck = { static struct clk gpt4_fck = { .name = "gpt4_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, @@ -2460,6 +2559,7 @@ static struct clk gpt4_fck = { static struct clk gpt5_fck = { .name = "gpt5_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, @@ -2473,6 +2573,7 @@ static struct clk gpt5_fck = { static struct clk gpt6_fck = { .name = "gpt6_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, @@ -2486,6 +2587,7 @@ static struct clk gpt6_fck = { static struct clk gpt7_fck = { .name = "gpt7_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, @@ -2499,6 +2601,7 @@ static struct clk gpt7_fck = { static struct clk gpt8_fck = { .name = "gpt8_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, @@ -2512,6 +2615,7 @@ static struct clk gpt8_fck = { static struct clk gpt9_fck = { .name = "gpt9_fck", + .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, @@ -2534,6 +2638,7 @@ static struct clk per_32k_alwon_fck = { static struct clk gpio6_dbck = { .name = "gpio6_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, @@ -2544,6 +2649,7 @@ static struct clk gpio6_dbck = { static struct clk gpio5_dbck = { .name = "gpio5_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, @@ -2554,6 +2660,7 @@ static struct clk gpio5_dbck = { static struct clk gpio4_dbck = { .name = "gpio4_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, @@ -2564,6 +2671,7 @@ static struct clk gpio4_dbck = { static struct clk gpio3_dbck = { .name = "gpio3_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, @@ -2574,6 +2682,7 @@ static struct clk gpio3_dbck = { static struct clk gpio2_dbck = { .name = "gpio2_dbck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, @@ -2584,6 +2693,7 @@ static struct clk gpio2_dbck = { static struct clk wdt3_fck = { .name = "wdt3_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, @@ -2603,6 +2713,7 @@ static struct clk per_l4_ick = { static struct clk gpio6_ick = { .name = "gpio6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, @@ -2613,6 +2724,7 @@ static struct clk gpio6_ick = { static struct clk gpio5_ick = { .name = "gpio5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, @@ -2623,6 +2735,7 @@ static struct clk gpio5_ick = { static struct clk gpio4_ick = { .name = "gpio4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, @@ -2633,6 +2746,7 @@ static struct clk gpio4_ick = { static struct clk gpio3_ick = { .name = "gpio3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, @@ -2643,6 +2757,7 @@ static struct clk gpio3_ick = { static struct clk gpio2_ick = { .name = "gpio2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, @@ -2653,6 +2768,7 @@ static struct clk gpio2_ick = { static struct clk wdt3_ick = { .name = "wdt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, @@ -2663,6 +2779,7 @@ static struct clk wdt3_ick = { static struct clk uart3_ick = { .name = "uart3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, @@ -2673,6 +2790,7 @@ static struct clk uart3_ick = { static struct clk gpt9_ick = { .name = "gpt9_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, @@ -2683,6 +2801,7 @@ static struct clk gpt9_ick = { static struct clk gpt8_ick = { .name = "gpt8_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, @@ -2693,6 +2812,7 @@ static struct clk gpt8_ick = { static struct clk gpt7_ick = { .name = "gpt7_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, @@ -2703,6 +2823,7 @@ static struct clk gpt7_ick = { static struct clk gpt6_ick = { .name = "gpt6_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, @@ -2713,6 +2834,7 @@ static struct clk gpt6_ick = { static struct clk gpt5_ick = { .name = "gpt5_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, @@ -2723,6 +2845,7 @@ static struct clk gpt5_ick = { static struct clk gpt4_ick = { .name = "gpt4_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, @@ -2733,6 +2856,7 @@ static struct clk gpt4_ick = { static struct clk gpt3_ick = { .name = "gpt3_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, @@ -2743,6 +2867,7 @@ static struct clk gpt3_ick = { static struct clk gpt2_ick = { .name = "gpt2_ick", + .ops = &clkops_omap2_dflt_wait, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, @@ -2753,6 +2878,7 @@ static struct clk gpt2_ick = { static struct clk mcbsp2_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 2, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), @@ -2764,6 +2890,7 @@ static struct clk mcbsp2_ick = { static struct clk mcbsp3_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 3, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), @@ -2775,6 +2902,7 @@ static struct clk mcbsp3_ick = { static struct clk mcbsp4_ick = { .name = "mcbsp_ick", + .ops = &clkops_omap2_dflt_wait, .id = 4, .parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), @@ -2792,6 +2920,7 @@ static const struct clksel mcbsp_234_clksel[] = { static struct clk mcbsp2_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 2, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), @@ -2806,6 +2935,7 @@ static struct clk mcbsp2_fck = { static struct clk mcbsp3_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 3, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), @@ -2820,6 +2950,7 @@ static struct clk mcbsp3_fck = { static struct clk mcbsp4_fck = { .name = "mcbsp_fck", + .ops = &clkops_omap2_dflt_wait, .id = 4, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), @@ -2988,6 +3119,7 @@ static struct clk traceclk_fck = { /* SmartReflex fclk (VDD1) */ static struct clk sr1_fck = { .name = "sr1_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, @@ -2998,6 +3130,7 @@ static struct clk sr1_fck = { /* SmartReflex fclk (VDD2) */ static struct clk sr2_fck = { .name = "sr2_fck", + .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, -- cgit v1.2.3 From bc51da4ee46d481dc3fbc57ec407594b80e92705 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 18:59:32 +0000 Subject: [ARM] omap: eliminate unnecessary conditionals in omap2_clk_wait_ready Rather than employing run-time tests in omap2_clk_wait_ready() to decide whether we need to wait for the clock to become ready, we can set the .ops appropriately. This change deals with the OMAP24xx and OMAP34xx conditionals only. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 42 +++++++++++++++++++++-------------------- arch/arm/mach-omap2/clock.h | 1 + arch/arm/mach-omap2/clock24xx.h | 10 +++++----- arch/arm/mach-omap2/clock34xx.h | 14 +++++++------- 4 files changed, 35 insertions(+), 32 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 8c09711d2eaf..986c9f582752 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -237,23 +237,6 @@ static void omap2_clk_wait_ready(struct clk *clk) else return; - /* REVISIT: What are the appropriate exclusions for 34XX? */ - /* No check for DSS or cam clocks */ - if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ - if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || - clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || - clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) - return; - } - - /* REVISIT: What are the appropriate exclusions for 34XX? */ - /* OMAP3: ignore DSS-mod clocks */ - if (cpu_is_omap34xx() && - (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || - ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && - clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) - return; - /* Check if both functional and interface clocks * are running. */ bit = 1 << clk->enable_bit; @@ -264,7 +247,7 @@ static void omap2_clk_wait_ready(struct clk *clk) omap2_wait_clock_ready(st_reg, bit, clk->name); } -static int omap2_dflt_clk_enable_wait(struct clk *clk) +static int omap2_dflt_clk_enable(struct clk *clk) { u32 regval32; @@ -282,11 +265,25 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk) __raw_writel(regval32, clk->enable_reg); wmb(); - omap2_clk_wait_ready(clk); - return 0; } +static int omap2_dflt_clk_enable_wait(struct clk *clk) +{ + int ret; + + if (unlikely(clk->enable_reg == NULL)) { + printk(KERN_ERR "clock.c: Enable for %s without enable code\n", + clk->name); + return 0; /* REVISIT: -EINVAL */ + } + + ret = omap2_dflt_clk_enable(clk); + if (ret == 0) + omap2_clk_wait_ready(clk); + return ret; +} + static void omap2_dflt_clk_disable(struct clk *clk) { u32 regval32; @@ -315,6 +312,11 @@ const struct clkops clkops_omap2_dflt_wait = { .disable = omap2_dflt_clk_disable, }; +const struct clkops clkops_omap2_dflt = { + .enable = omap2_dflt_clk_enable, + .disable = omap2_dflt_clk_disable, +}; + /* Enables clock without considering parent dependencies or use count * REVISIT: Maybe change this to use clk->enable like on omap1? */ diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index d4bdb59b3000..b0358b659b43 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -52,6 +52,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); void omap2_clk_prepare_for_reboot(void); extern const struct clkops clkops_omap2_dflt_wait; +extern const struct clkops clkops_omap2_dflt; extern u8 cpu_mask; diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index b59bf902ce7c..d386b3dfabae 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -1455,7 +1455,7 @@ static const struct clksel dss1_fck_clksel[] = { static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ .name = "dss_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &l4_ck, /* really both l3 and l4 */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "dss_clkdm", @@ -1466,7 +1466,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ static struct clk dss1_fck = { .name = "dss1_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &core_ck, /* Core or sys */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, @@ -1500,7 +1500,7 @@ static const struct clksel dss2_fck_clksel[] = { static struct clk dss2_fck = { /* Alt clk used in power management */ .name = "dss2_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP, @@ -2206,7 +2206,7 @@ static struct clk icr_ick = { static struct clk cam_ick = { .name = "cam_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &l4_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l4_clkdm", @@ -2222,7 +2222,7 @@ static struct clk cam_ick = { */ static struct clk cam_fck = { .name = "cam_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &func_96m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, .clkdm_name = "core_l3_clkdm", diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 0d6a11ca132d..1ff05d351b38 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -1652,7 +1652,7 @@ static const struct clksel ssi_ssr_clksel[] = { static struct clk ssi_ssr_fck = { .name = "ssi_ssr_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, @@ -2064,7 +2064,7 @@ static struct clk ssi_l4_ick = { static struct clk ssi_ick = { .name = "ssi_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, @@ -2156,7 +2156,7 @@ static const struct clksel dss1_alwon_fck_clksel[] = { static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &dpll4_m4x2_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2171,7 +2171,7 @@ static struct clk dss1_alwon_fck = { static struct clk dss_tv_fck = { .name = "dss_tv_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &omap_54m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2183,7 +2183,7 @@ static struct clk dss_tv_fck = { static struct clk dss_96m_fck = { .name = "dss_96m_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &omap_96m_fck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2195,7 +2195,7 @@ static struct clk dss_96m_fck = { static struct clk dss2_alwon_fck = { .name = "dss2_alwon_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &sys_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), @@ -2208,7 +2208,7 @@ static struct clk dss2_alwon_fck = { static struct clk dss_ick = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), -- cgit v1.2.3 From c1168dc31d8e0688168030ac66341897ed7ca32a Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 4 Nov 2008 21:24:00 +0000 Subject: [ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks The original code in omap2_clk_wait_ready() used to check the low 8 bits to determine whether they were within the FCLKEN or ICLKEN registers. Specifically, the test is satisfied when these offsets are used: CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN, CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4 OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2 If one of these offsets isn't used, omap2_clk_wait_ready() merely returns without doing anything. So we should use the non-wait clkops version instead and eliminate that conditional. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 14 ++++++-------- arch/arm/mach-omap2/clock24xx.h | 6 +++--- arch/arm/mach-omap2/clock34xx.h | 12 ++++++------ 3 files changed, 15 insertions(+), 17 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 986c9f582752..76afb7b4482c 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -228,14 +228,12 @@ static void omap2_clk_wait_ready(struct clk *clk) * it and pull it into struct clk itself somehow. */ reg = clk->enable_reg; - if ((((u32)reg & 0xff) >= CM_FCLKEN1) && - (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) - other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ - else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && - (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) - other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ - else - return; + + /* + * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes + * it's just a matter of XORing the bits. + */ + other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); /* Check if both functional and interface clocks * are running. */ diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index d386b3dfabae..486fd80143e4 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -890,7 +890,7 @@ static const struct clksel common_clkout_src_clksel[] = { static struct clk sys_clkout_src = { .name = "sys_clkout_src", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_PROPAGATES, @@ -937,7 +937,7 @@ static struct clk sys_clkout = { /* In 2430, new in 2420 ES2 */ static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", @@ -974,7 +974,7 @@ static struct clk sys_clkout2 = { static struct clk emul_ck = { .name = "emul_ck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, .flags = CLOCK_IN_OMAP242X, .clkdm_name = "wkup_clkdm", diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 1ff05d351b38..335ef88ada55 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -216,7 +216,7 @@ static struct clk mcbsp_clks = { static struct clk sys_clkout1 = { .name = "sys_clkout1", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &osc_sys_ck, .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, @@ -967,7 +967,7 @@ static const struct clksel clkout2_src_clksel[] = { static struct clk clkout2_src_ck = { .name = "clkout2_src_ck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, .enable_reg = OMAP3430_CM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, @@ -1356,7 +1356,7 @@ static struct clk gpt11_fck = { static struct clk cpefuse_fck = { .name = "cpefuse_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, @@ -1366,7 +1366,7 @@ static struct clk cpefuse_fck = { static struct clk ts_fck = { .name = "ts_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &omap_32k_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_TS_SHIFT, @@ -1376,7 +1376,7 @@ static struct clk ts_fck = { static struct clk usbtll_fck = { .name = "usbtll_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &omap_120m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, @@ -2295,7 +2295,7 @@ static struct clk usbhost_ick = { static struct clk usbhost_sar_fck = { .name = "usbhost_sar_fck", - .ops = &clkops_omap2_dflt_wait, + .ops = &clkops_omap2_dflt, .parent = &osc_sys_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), -- cgit v1.2.3 From c6af45085211db8720d6b94b3985ce7198d764e3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 Nov 2008 13:01:32 +0000 Subject: [ARM] omap: move clock propagation into core omap clock code Move the clock propagation calls for set_parent and set_rate into the core omap clock code, rather than having these calls scattered throughout the OMAP1 and OMAP2 implementations. Signed-off-by: Russell King --- arch/arm/mach-omap1/clock.c | 3 --- arch/arm/mach-omap2/clock.c | 6 ------ arch/arm/plat-omap/clock.c | 6 +++++- 3 files changed, 5 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index ff408105ffb2..ee1b9f20544a 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -628,9 +628,6 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) ret = 0; } - if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) - propagate_rate(clk); - return ret; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 76afb7b4482c..7a1d56af9e47 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -684,9 +684,6 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) if (clk->set_rate != NULL) ret = clk->set_rate(clk, rate); - if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) - propagate_rate(clk); - return ret; } @@ -774,9 +771,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) pr_debug("clock: set parent of %s to %s (new rate %ld)\n", clk->name, clk->parent->name, clk->rate); - if (unlikely(clk->flags & RATE_PROPAGATES)) - propagate_rate(clk); - return 0; } diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index ae77e10719f2..b7137c560db4 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -182,6 +182,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate) spin_lock_irqsave(&clockfw_lock, flags); if (arch_clock->clk_set_rate) ret = arch_clock->clk_set_rate(clk, rate); + if (ret == 0 && (clk->flags & RATE_PROPAGATES)) + propagate_rate(clk); spin_unlock_irqrestore(&clockfw_lock, flags); return ret; @@ -198,7 +200,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent) spin_lock_irqsave(&clockfw_lock, flags); if (arch_clock->clk_set_parent) - ret = arch_clock->clk_set_parent(clk, parent); + ret = arch_clock->clk_set_parent(clk, parent); + if (ret == 0 && (clk->flags & RATE_PROPAGATES)) + propagate_rate(clk); spin_unlock_irqrestore(&clockfw_lock, flags); return ret; -- cgit v1.2.3 From 9a5fedac187f30116013a8420149d4ca11a44f0d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 13 Nov 2008 13:44:15 +0000 Subject: [ARM] omap: move propagate_rate() calls into generic omap clock code propagate_rate() is recursive, so it makes sense to minimise the amount of stack which is used for each recursion. So, rather than recursing back into it from the ->recalc functions if RATE_PROPAGATES is set, do that test at the higher level. Signed-off-by: Russell King --- arch/arm/mach-omap1/clock.c | 6 ------ arch/arm/mach-omap2/clock.c | 6 ------ arch/arm/mach-omap2/clock24xx.c | 6 ++---- arch/arm/mach-omap2/clock24xx.h | 4 ---- arch/arm/mach-omap2/clock34xx.c | 5 ----- arch/arm/mach-omap2/clock34xx.h | 10 ---------- arch/arm/plat-omap/clock.c | 14 +++++++++----- 7 files changed, 11 insertions(+), 40 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 80a58e9dbba3..be500014dcb8 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -244,9 +244,6 @@ static void omap1_ckctl_recalc(struct clk * clk) if (unlikely(clk->rate == clk->parent->rate / dsor)) return; /* No change, quick exit */ clk->rate = clk->parent->rate / dsor; - - if (unlikely(clk->flags & RATE_PROPAGATES)) - propagate_rate(clk); } static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) @@ -267,9 +264,6 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) if (unlikely(clk->rate == clk->parent->rate / dsor)) return; /* No change, quick exit */ clk->rate = clk->parent->rate / dsor; - - if (unlikely(clk->flags & RATE_PROPAGATES)) - propagate_rate(clk); } /* MPU virtual clock functions */ diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7a1d56af9e47..53fda9977d55 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -167,9 +167,6 @@ void omap2_fixed_divisor_recalc(struct clk *clk) WARN_ON(!clk->fixed_div); clk->rate = clk->parent->rate / clk->fixed_div; - - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); } /** @@ -392,9 +389,6 @@ void omap2_clksel_recalc(struct clk *clk) clk->rate = clk->parent->rate / div; pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); - - if (unlikely(clk->flags & RATE_PROPAGATES)) - propagate_rate(clk); } /** diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 866a618c4d8d..3a0a1b8aa0bb 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -199,8 +199,6 @@ long omap2_dpllcore_round_rate(unsigned long target_rate) static void omap2_dpllcore_recalc(struct clk *clk) { clk->rate = omap2_get_dpll_rate_24xx(clk); - - propagate_rate(clk); } static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) @@ -442,13 +440,11 @@ static u32 omap2_get_sysclkdiv(void) static void omap2_osc_clk_recalc(struct clk *clk) { clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); - propagate_rate(clk); } static void omap2_sys_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); - propagate_rate(clk); } /* @@ -502,7 +498,9 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); omap2_osc_clk_recalc(&osc_ck); + propagate_rate(&osc_ck); omap2_sys_clk_recalc(&sys_ck); + propagate_rate(&sys_ck); for (clkp = onchip_24xx_clks; clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 486fd80143e4..e07dcba4b3e9 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -624,7 +624,6 @@ static struct clk func_32k_ck = { .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", - .recalc = &propagate_rate, }; /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ @@ -655,7 +654,6 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_FIXED | RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", - .recalc = &propagate_rate, }; /* @@ -702,7 +700,6 @@ static struct clk apll96_ck = { .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, - .recalc = &propagate_rate, }; static struct clk apll54_ck = { @@ -715,7 +712,6 @@ static struct clk apll54_ck = { .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, - .recalc = &propagate_rate, }; /* diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 2f2d43db2dd8..52698fb4fd04 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -57,8 +57,6 @@ static const struct clkops clkops_noncore_dpll_ops; static void omap3_dpll_recalc(struct clk *clk) { clk->rate = omap2_get_dpll_rate(clk); - - propagate_rate(clk); } /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ @@ -388,9 +386,6 @@ static void omap3_clkoutx2_recalc(struct clk *clk) clk->rate = clk->parent->rate; else clk->rate = clk->parent->rate * 2; - - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); } /* Common clock code */ diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 335ef88ada55..dcacec84f8ca 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -58,7 +58,6 @@ static struct clk omap_32k_fck = { .ops = &clkops_null, .rate = 32768, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static struct clk secure_32k_fck = { @@ -66,7 +65,6 @@ static struct clk secure_32k_fck = { .ops = &clkops_null, .rate = 32768, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; /* Virtual source clocks for osc_sys_ck */ @@ -75,7 +73,6 @@ static struct clk virt_12m_ck = { .ops = &clkops_null, .rate = 12000000, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static struct clk virt_13m_ck = { @@ -83,7 +80,6 @@ static struct clk virt_13m_ck = { .ops = &clkops_null, .rate = 13000000, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static struct clk virt_16_8m_ck = { @@ -91,7 +87,6 @@ static struct clk virt_16_8m_ck = { .ops = &clkops_null, .rate = 16800000, .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static struct clk virt_19_2m_ck = { @@ -99,7 +94,6 @@ static struct clk virt_19_2m_ck = { .ops = &clkops_null, .rate = 19200000, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static struct clk virt_26m_ck = { @@ -107,7 +101,6 @@ static struct clk virt_26m_ck = { .ops = &clkops_null, .rate = 26000000, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static struct clk virt_38_4m_ck = { @@ -115,7 +108,6 @@ static struct clk virt_38_4m_ck = { .ops = &clkops_null, .rate = 38400000, .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES, - .recalc = &propagate_rate, }; static const struct clksel_rate osc_sys_12m_rates[] = { @@ -201,7 +193,6 @@ static struct clk sys_altclk = { .name = "sys_altclk", .ops = &clkops_null, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &propagate_rate, }; /* Optional external clock input for some McBSPs */ @@ -209,7 +200,6 @@ static struct clk mcbsp_clks = { .name = "mcbsp_clks", .ops = &clkops_null, .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, - .recalc = &propagate_rate, }; /* PRM EXTERNAL CLOCK OUTPUT */ diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index b7137c560db4..df58f5d9a5ab 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -246,8 +246,6 @@ void followparent_recalc(struct clk *clk) return; clk->rate = clk->parent->rate; - if (unlikely(clk->flags & RATE_PROPAGATES)) - propagate_rate(clk); } /* Propagate rate to children */ @@ -261,8 +259,10 @@ void propagate_rate(struct clk * tclk) list_for_each_entry(clkp, &clocks, node) { if (likely(clkp->parent != tclk)) continue; - if (likely((u32)clkp->recalc)) + if (clkp->recalc) clkp->recalc(clkp); + if (clkp->flags & RATE_PROPAGATES) + propagate_rate(clkp); } } @@ -278,8 +278,12 @@ void recalculate_root_clocks(void) struct clk *clkp; list_for_each_entry(clkp, &clocks, node) { - if (unlikely(!clkp->parent) && likely((u32)clkp->recalc)) - clkp->recalc(clkp); + if (!clkp->parent) { + if (clkp->recalc) + clkp->recalc(clkp); + if (clkp->flags & RATE_PROPAGATES) + propagate_rate(clkp); + } } } -- cgit v1.2.3 From fecb494beef09e4caaa80313834af26f57091195 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 27 Jan 2009 19:12:50 -0700 Subject: [ARM] OMAP: Fix sparse, checkpatch warnings in OMAP2/3 PRCM/PM code Fix sparse & checkpatch warnings in OMAP2/3 PRCM & PM code. This mostly consists of: - converting pointer comparisons to integers in form similar to (ptr == 0) to the standard idiom (!ptr) - labeling a few non-static private functions as static - adding prototypes for *_init() functions in the appropriate header files, and getting rid of the corresponding open-coded extern prototypes in other C files - renaming the variable 'sclk' in mach-omap2/clock.c:omap2_get_apll_clkin to avoid shadowing an earlier declaration Clean up checkpatch issues. This mostly involves: - converting some asm/ includes to linux/ includes - cleaning up some whitespace - getting rid of braces for conditionals with single following statements Also take care of a few odds and ends, including: - getting rid of unlikely() and likely() - none of this code is particularly fast-path code, so the performance impact seems slim; and some of those likely() and unlikely() indicators are probably not as accurate as the ARM's branch predictor - removing some superfluous casts linux-omap source commit is 347df59f5d20fdf905afbc26b1328b0e28a8a01b. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 51 +++++++++++++-------------- arch/arm/mach-omap2/clock.h | 2 +- arch/arm/mach-omap2/clock24xx.c | 16 +++++---- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/plat-omap/include/mach/clock.h | 4 +-- arch/arm/plat-omap/include/mach/powerdomain.h | 1 + arch/arm/plat-omap/include/mach/prcm.h | 5 +-- arch/arm/plat-omap/include/mach/system.h | 4 +-- 8 files changed, 44 insertions(+), 41 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 53fda9977d55..886f73f3933a 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -26,7 +26,6 @@ #include #include -#include #include #include @@ -187,11 +186,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) * 24xx uses 0 to indicate not ready, and 1 to indicate ready. * 34xx reverses this, just to keep us on our toes */ - if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { + if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) ena = mask; - } else if (cpu_mask & RATE_IN_343X) { + else if (cpu_mask & RATE_IN_343X) ena = 0; - } /* Wait for lock */ while (((__raw_readl(reg) & mask) != ena) && @@ -267,7 +265,7 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk) { int ret; - if (unlikely(clk->enable_reg == NULL)) { + if (!clk->enable_reg) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", clk->name); return 0; /* REVISIT: -EINVAL */ @@ -283,7 +281,7 @@ static void omap2_dflt_clk_disable(struct clk *clk) { u32 regval32; - if (clk->enable_reg == NULL) { + if (!clk->enable_reg) { /* * 'Independent' here refers to a clock which is not * controlled by its parent. @@ -330,7 +328,7 @@ void omap2_clk_disable(struct clk *clk) { if (clk->usecount > 0 && !(--clk->usecount)) { _omap2_clk_disable(clk); - if (likely((u32)clk->parent)) + if (clk->parent) omap2_clk_disable(clk->parent); if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); @@ -343,10 +341,10 @@ int omap2_clk_enable(struct clk *clk) int ret = 0; if (clk->usecount++ == 0) { - if (likely((u32)clk->parent)) + if (clk->parent) ret = omap2_clk_enable(clk->parent); - if (unlikely(ret != 0)) { + if (ret != 0) { clk->usecount--; return ret; } @@ -356,7 +354,7 @@ int omap2_clk_enable(struct clk *clk) ret = _omap2_clk_enable(clk); - if (unlikely(ret != 0)) { + if (ret != 0) { if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); @@ -384,7 +382,7 @@ void omap2_clksel_recalc(struct clk *clk) if (div == 0) return; - if (unlikely(clk->rate == clk->parent->rate / div)) + if (clk->rate == (clk->parent->rate / div)) return; clk->rate = clk->parent->rate / div; @@ -400,8 +398,8 @@ void omap2_clksel_recalc(struct clk *clk) * the element associated with the supplied parent clock address. * Returns a pointer to the struct clksel on success or NULL on error. */ -const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, - struct clk *src_clk) +static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, + struct clk *src_clk) { const struct clksel *clks; @@ -450,7 +448,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, *new_div = 1; clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (clks == NULL) + if (!clks) return ~0; for (clkr = clks->rates; clkr->div; clkr++) { @@ -509,7 +507,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) /* Given a clock and a rate apply a clock specific rounding function */ long omap2_clk_round_rate(struct clk *clk, unsigned long rate) { - if (clk->round_rate != NULL) + if (clk->round_rate) return clk->round_rate(clk, rate); if (clk->flags & RATE_FIXED) @@ -535,7 +533,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) const struct clksel_rate *clkr; clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (clks == NULL) + if (!clks) return 0; for (clkr = clks->rates; clkr->div; clkr++) { @@ -571,7 +569,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) WARN_ON(div == 0); clks = omap2_get_clksel_by_parent(clk, clk->parent); - if (clks == NULL) + if (!clks) return 0; for (clkr = clks->rates; clkr->div; clkr++) { @@ -596,9 +594,9 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) * * Returns the address of the clksel register upon success or NULL on error. */ -void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) +static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) { - if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) + if (!clk->clksel_reg || (clk->clksel_mask == 0)) return NULL; *field_mask = clk->clksel_mask; @@ -618,7 +616,7 @@ u32 omap2_clksel_get_divisor(struct clk *clk) void __iomem *div_addr; div_addr = omap2_get_clksel(clk, &field_mask); - if (div_addr == NULL) + if (!div_addr) return 0; field_val = __raw_readl(div_addr) & field_mask; @@ -637,7 +635,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; div_addr = omap2_get_clksel(clk, &field_mask); - if (div_addr == NULL) + if (!div_addr) return -EINVAL; field_val = omap2_divisor_to_clksel(clk, new_div); @@ -675,7 +673,7 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ - if (clk->set_rate != NULL) + if (clk->set_rate) ret = clk->set_rate(clk, rate); return ret; @@ -696,7 +694,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr, *src_addr = NULL; clks = omap2_get_clksel_by_parent(clk, src_clk); - if (clks == NULL) + if (!clks) return 0; for (clkr = clks->rates; clkr->div; clkr++) { @@ -726,7 +724,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) void __iomem *src_addr; u32 field_val, field_mask, reg_val, parent_div; - if (unlikely(clk->flags & CONFIG_PARTICIPANT)) + if (clk->flags & CONFIG_PARTICIPANT) return -EINVAL; if (!clk->clksel) @@ -734,7 +732,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) field_val = omap2_clksel_get_src_field(&src_addr, new_parent, &field_mask, clk, &parent_div); - if (src_addr == NULL) + if (!src_addr) return -EINVAL; if (clk->usecount > 0) @@ -794,7 +792,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) return 0; } -static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) +static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, + unsigned int m, unsigned int n) { unsigned long long num; diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b0358b659b43..90077f0df78d 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -27,7 +27,7 @@ void omap2_clk_disable(struct clk *clk); long omap2_clk_round_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_rate(struct clk *clk, unsigned long rate); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); -int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance); +int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); #ifdef CONFIG_OMAP_RESET_CLOCKS diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index bd77ef2d5ae9..91ad2070264d 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -339,7 +339,7 @@ static const struct clkops clkops_fixed = { * Uses the current prcm set to tell if a rate is valid. * You can go slower, but not faster within a given rate set. */ -long omap2_dpllcore_round_rate(unsigned long target_rate) +static long omap2_dpllcore_round_rate(unsigned long target_rate) { u32 high, low, core_clk_src; @@ -550,7 +550,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) /* Major subsystem dividers */ tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); + cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + CM_CLKSEL1); + if (cpu_is_omap2430()) cm_write_mod_reg(prcm->cm_clksel_mdm, OMAP2430_MDM_MOD, CM_CLKSEL); @@ -582,20 +584,20 @@ static struct clk_functions omap2_clk_functions = { static u32 omap2_get_apll_clkin(void) { - u32 aplls, sclk = 0; + u32 aplls, srate = 0; aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; if (aplls == APLLS_CLKIN_19_2MHZ) - sclk = 19200000; + srate = 19200000; else if (aplls == APLLS_CLKIN_13MHZ) - sclk = 13000000; + srate = 13000000; else if (aplls == APLLS_CLKIN_12MHZ) - sclk = 12000000; + srate = 12000000; - return sclk; + return srate; } static u32 omap2_get_sysclkdiv(void) diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 55361c16c9d9..ea8ceaed09cb 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -103,7 +103,7 @@ static struct platform_suspend_ops omap_pm_ops = { .valid = suspend_valid_only_mem, }; -int __init omap2_pm_init(void) +static int __init omap2_pm_init(void) { return 0; } diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index f147aec91f12..6f49a3332890 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -113,12 +113,12 @@ struct clk_functions { extern unsigned int mpurate; -extern int clk_init(struct clk_functions * custom_clocks); +extern int clk_init(struct clk_functions *custom_clocks); extern int clk_register(struct clk *clk); extern void clk_unregister(struct clk *clk); extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); -extern void followparent_recalc(struct clk * clk); +extern void followparent_recalc(struct clk *clk); extern int clk_get_usecount(struct clk *clk); extern void clk_enable_init_clocks(void); diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h index 2806a9c8e4d7..4948cb7af5bf 100644 --- a/arch/arm/plat-omap/include/mach/powerdomain.h +++ b/arch/arm/plat-omap/include/mach/powerdomain.h @@ -145,6 +145,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_pwrst(struct powerdomain *pwrdm); int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h index 56eba0fd6f6a..24ac3c715912 100644 --- a/arch/arm/plat-omap/include/mach/prcm.h +++ b/arch/arm/plat-omap/include/mach/prcm.h @@ -20,10 +20,11 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#ifndef __ASM_ARM_ARCH_DPM_PRCM_H -#define __ASM_ARM_ARCH_DPM_PRCM_H +#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H +#define __ASM_ARM_ARCH_OMAP_PRCM_H u32 omap_prcm_get_reset_sources(void); +void omap_prcm_arch_reset(char mode); #endif diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h index 06923f261545..e9b95637f7fc 100644 --- a/arch/arm/plat-omap/include/mach/system.h +++ b/arch/arm/plat-omap/include/mach/system.h @@ -9,12 +9,12 @@ #include #include +#include + #ifndef CONFIG_MACH_VOICEBLUE #define voiceblue_reset() do {} while (0) #endif -extern void omap_prcm_arch_reset(char mode); - static inline void arch_idle(void) { cpu_do_idle(); -- cgit v1.2.3 From b32450409847dddf060a468707212d3493df4f63 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:08:38 -0700 Subject: [ARM] OMAP3 clock: remove unnecessary dpll_data dereferences Remove some clutter from omap2_dpll_round_rate(). linux-omap source commit is 4625dceb8583c02a6d67ededc9f6a8347b6b8cb7. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 886f73f3933a..2f0eaaad4819 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -877,19 +877,22 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) int m, n, r, e, scaled_max_m; unsigned long scaled_rt_rp, new_rate; int min_e = -1, min_e_m = -1, min_e_n = -1; + struct dpll_data *dd; if (!clk || !clk->dpll_data) return ~0; + dd = clk->dpll_data; + pr_debug("clock: starting DPLL round_rate for clock %s, target rate " "%ld\n", clk->name, target_rate); scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); - scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; + scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; - clk->dpll_data->last_rounded_rate = 0; + dd->last_rounded_rate = 0; - for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { + for (n = dd->max_divider; n >= DPLL_MIN_DIVIDER; n--) { /* Compute the scaled DPLL multiplier, based on the divider */ m = scaled_rt_rp * n; @@ -909,7 +912,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) "(new_rate = %ld)\n", n, m, e, new_rate); if (min_e == -1 || - min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { + min_e >= (int)(abs(e) - dd->rate_tolerance)) { min_e = e; min_e_m = m; min_e_n = n; @@ -932,17 +935,17 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) return ~0; } - clk->dpll_data->last_rounded_m = min_e_m; - clk->dpll_data->last_rounded_n = min_e_n; - clk->dpll_data->last_rounded_rate = - _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); + dd->last_rounded_m = min_e_m; + dd->last_rounded_n = min_e_n; + dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate, + min_e_m, min_e_n); pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", min_e, min_e_m, min_e_n); pr_debug("clock: final rate: %ld (target rate: %ld)\n", - clk->dpll_data->last_rounded_rate, target_rate); + dd->last_rounded_rate, target_rate); - return clk->dpll_data->last_rounded_rate; + return dd->last_rounded_rate; } /*------------------------------------------------------------------------- -- cgit v1.2.3 From 85a5f78d2b15a2e73b6486a24b77bb3ab67d5bbc Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:08:41 -0700 Subject: [ARM] OMAP3 clock: optimize DPLL rate rounding algorithm The previous DPLL rate rounding algorithm counted the divider (N) down from the maximum to 1. Since we currently use a broad DPLL rate tolerance, and lower N values are more power-efficient, we can often bypass several iterations through the loop by counting N upwards from 1. Peter de Schrijver put up with several test cycles of this patch - thanks Peter. linux-omap source commit is 6f6d82bb2f80fa20a841ac3e95a6f44a5a156188. Signed-off-by: Paul Walmsley Cc: Peter de Schrijver Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 2f0eaaad4819..76e20bcc4e8a 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -45,7 +45,7 @@ #define DPLL_MIN_DIVIDER 1 /* Possible error results from _dpll_test_mult */ -#define DPLL_MULT_UNDERFLOW (1 << 0) +#define DPLL_MULT_UNDERFLOW -1 /* * Scale factor to mitigate roundoff errors in DPLL rate rounding. @@ -826,7 +826,7 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, unsigned long target_rate, unsigned long parent_rate) { - int flags = 0, carry = 0; + int r = 0, carry = 0; /* Unscale m and round if necessary */ if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) @@ -847,13 +847,13 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, if (*m < DPLL_MIN_MULTIPLIER) { *m = DPLL_MIN_MULTIPLIER; *new_rate = 0; - flags = DPLL_MULT_UNDERFLOW; + r = DPLL_MULT_UNDERFLOW; } if (*new_rate == 0) *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); - return flags; + return r; } /** @@ -892,21 +892,27 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd->last_rounded_rate = 0; - for (n = dd->max_divider; n >= DPLL_MIN_DIVIDER; n--) { + for (n = DPLL_MIN_DIVIDER; n <= dd->max_divider; n++) { /* Compute the scaled DPLL multiplier, based on the divider */ m = scaled_rt_rp * n; /* - * Since we're counting n down, a m overflow means we can - * can immediately skip to the next n + * Since we're counting n up, a m overflow means we + * can bail out completely (since as n increases in + * the next iteration, there's no way that m can + * increase beyond the current m) */ if (m > scaled_max_m) - continue; + break; r = _dpll_test_mult(&m, n, &new_rate, target_rate, clk->parent->rate); + /* m can't be set low enough for this n - try with a larger n */ + if (r == DPLL_MULT_UNDERFLOW) + continue; + e = target_rate - new_rate; pr_debug("clock: n = %d: m = %d: rate error is %d " "(new_rate = %ld)\n", n, m, e, new_rate); @@ -918,16 +924,11 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) min_e_n = n; pr_debug("clock: found new least error %d\n", min_e); - } - /* - * Since we're counting n down, a m underflow means we - * can bail out completely (since as n decreases in - * the next iteration, there's no way that m can - * increase beyond the current m) - */ - if (r & DPLL_MULT_UNDERFLOW) - break; + /* We found good settings -- bail out now */ + if (min_e <= clk->dpll_data->rate_tolerance) + break; + } } if (min_e < 0) { -- cgit v1.2.3 From 95f538ac370d9625457ba00ef7c3bb91e2b92f89 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:08:44 -0700 Subject: [ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding The DPLL FREQSEL jitter correction bits are set based on a table in the 34xx TRM, Table 4-38, according to the DPLL's internal clock frequency "Fint." Several Fint frequency ranges are missing from this table. Previously, we allowed these Fint frequency ranges to be selected in the rate rounding code, but did not change the FREQSEL bits. Correspondence with the OMAP hardware team indicates that Fint values not in the table should not be used. So, prevent them from being selected during DPLL rate rounding. This removes warnings and also can prevent the chip from locking up. The first pass through the rate rounding code will update the DPLL max and min dividers appropriately, so later rate rounding passes will run faster than the first. Peter de Schrijver put up with several test cycles of this patch - thanks Peter. linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9. Signed-off-by: Paul Walmsley Cc: Peter de Schrijver Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 67 ++++++++++++++++++++++++++++++++- arch/arm/mach-omap2/clock24xx.h | 1 + arch/arm/mach-omap2/clock34xx.h | 5 +++ arch/arm/plat-omap/include/mach/clock.h | 1 + 4 files changed, 72 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 76e20bcc4e8a..752e34787f21 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -58,12 +58,68 @@ #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) +/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ +#define DPLL_FINT_BAND1_MIN 750000 +#define DPLL_FINT_BAND1_MAX 2100000 +#define DPLL_FINT_BAND2_MIN 7500000 +#define DPLL_FINT_BAND2_MAX 21000000 + +/* _dpll_test_fint() return codes */ +#define DPLL_FINT_UNDERFLOW -1 +#define DPLL_FINT_INVALID -2 + u8 cpu_mask; /*------------------------------------------------------------------------- * OMAP2/3 specific clock functions *-------------------------------------------------------------------------*/ +/* + * _dpll_test_fint - test whether an Fint value is valid for the DPLL + * @clk: DPLL struct clk to test + * @n: divider value (N) to test + * + * Tests whether a particular divider @n will result in a valid DPLL + * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter + * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate + * (assuming that it is counting N upwards), or -2 if the enclosing loop + * should skip to the next iteration (again assuming N is increasing). + */ +static int _dpll_test_fint(struct clk *clk, u8 n) +{ + struct dpll_data *dd; + long fint; + int ret = 0; + + dd = clk->dpll_data; + + /* DPLL divider must result in a valid jitter correction val */ + fint = clk->parent->rate / (n + 1); + if (fint < DPLL_FINT_BAND1_MIN) { + + pr_debug("rejecting n=%d due to Fint failure, " + "lowering max_divider\n", n); + dd->max_divider = n; + ret = DPLL_FINT_UNDERFLOW; + + } else if (fint > DPLL_FINT_BAND1_MAX && + fint < DPLL_FINT_BAND2_MIN) { + + pr_debug("rejecting n=%d due to Fint failure\n", n); + ret = DPLL_FINT_INVALID; + + } else if (fint > DPLL_FINT_BAND2_MAX) { + + pr_debug("rejecting n=%d due to Fint failure, " + "boosting min_divider\n", n); + dd->min_divider = n; + ret = DPLL_FINT_INVALID; + + } + + return ret; +} + /** * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk * @clk: OMAP clock struct ptr to use @@ -892,7 +948,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd->last_rounded_rate = 0; - for (n = DPLL_MIN_DIVIDER; n <= dd->max_divider; n++) { + for (n = dd->min_divider; n <= dd->max_divider; n++) { + + /* Is the (input clk, divider) pair valid for the DPLL? */ + r = _dpll_test_fint(clk, n); + if (r == DPLL_FINT_UNDERFLOW) + break; + else if (r == DPLL_FINT_INVALID) + continue; /* Compute the scaled DPLL multiplier, based on the divider */ m = scaled_rt_rp * n; @@ -926,7 +989,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) pr_debug("clock: found new least error %d\n", min_e); /* We found good settings -- bail out now */ - if (min_e <= clk->dpll_data->rate_tolerance) + if (min_e <= dd->rate_tolerance) break; } } diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 32dd8573e56b..7731ab6acd18 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -666,6 +666,7 @@ static struct dpll_data dpll_dd = { .mult_mask = OMAP24XX_DPLL_MULT_MASK, .div1_mask = OMAP24XX_DPLL_DIV_MASK, .max_multiplier = 1024, + .min_divider = 1, .max_divider = 16, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 7ee131202625..aadd296c05a2 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -268,6 +268,7 @@ static struct dpll_data dpll1_dd = { .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -341,6 +342,7 @@ static struct dpll_data dpll2_dd = { .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -400,6 +402,7 @@ static struct dpll_data dpll3_dd = { .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -591,6 +594,7 @@ static struct dpll_data dpll4_dd = { .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; @@ -930,6 +934,7 @@ static struct dpll_data dpll5_dd = { .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, + .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE }; diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 611df52a3242..cd69111cd33f 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -43,6 +43,7 @@ struct dpll_data { unsigned long last_rounded_rate; u16 last_rounded_m; u8 last_rounded_n; + u8 min_divider; u8 max_divider; u32 max_tolerance; u16 max_multiplier; -- cgit v1.2.3 From ee1eec36345871955730e36232937c9d814a6e20 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:18:19 -0700 Subject: [ARM] OMAP2/3 clock: clean up mach-omap2/clock.c This patch rolls up several cleanup patches. 1. Some unnecessarily verbose variable names are used in several clock.c functions; clean these up per CodingStyle. 2. Remove omap2_get_clksel() and just use clk->clksel_reg and clk->clksel_mask directly. 3. Get rid of void __iomem * usage in omap2_clksel_get_src_field. Prepend the function name with an underscore to highlight that it is a static function. linux-omap source commits are 7fa95e007ea2f3c4d0ecd2779d809756e7775894, af0ea23f1ee4a5bea3b026e38761b47089f9048a, and 91c0c979b47c44b08f80e4f8d4c990fb158d82c4. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 98 ++++++++++++++++----------------------------- 1 file changed, 35 insertions(+), 63 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 752e34787f21..5d7d4c52f37e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -298,7 +298,7 @@ static void omap2_clk_wait_ready(struct clk *clk) static int omap2_dflt_clk_enable(struct clk *clk) { - u32 regval32; + u32 v; if (unlikely(clk->enable_reg == NULL)) { printk(KERN_ERR "clock.c: Enable for %s without enable code\n", @@ -306,12 +306,12 @@ static int omap2_dflt_clk_enable(struct clk *clk) return 0; /* REVISIT: -EINVAL */ } - regval32 = __raw_readl(clk->enable_reg); + v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) - regval32 &= ~(1 << clk->enable_bit); + v &= ~(1 << clk->enable_bit); else - regval32 |= (1 << clk->enable_bit); - __raw_writel(regval32, clk->enable_reg); + v |= (1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); wmb(); return 0; @@ -335,7 +335,7 @@ static int omap2_dflt_clk_enable_wait(struct clk *clk) static void omap2_dflt_clk_disable(struct clk *clk) { - u32 regval32; + u32 v; if (!clk->enable_reg) { /* @@ -347,12 +347,12 @@ static void omap2_dflt_clk_disable(struct clk *clk) return; } - regval32 = __raw_readl(clk->enable_reg); + v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) - regval32 |= (1 << clk->enable_bit); + v |= (1 << clk->enable_bit); else - regval32 &= ~(1 << clk->enable_bit); - __raw_writel(regval32, clk->enable_reg); + v &= ~(1 << clk->enable_bit); + __raw_writel(v, clk->enable_reg); wmb(); } @@ -643,23 +643,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) return clkr->val; } -/** - * omap2_get_clksel - find clksel register addr & field mask for a clk - * @clk: struct clk to use - * @field_mask: ptr to u32 to store the register field mask - * - * Returns the address of the clksel register upon success or NULL on error. - */ -static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) -{ - if (!clk->clksel_reg || (clk->clksel_mask == 0)) - return NULL; - - *field_mask = clk->clksel_mask; - - return clk->clksel_reg; -} - /** * omap2_clksel_get_divisor - get current divider applied to parent clock. * @clk: OMAP struct clk to use. @@ -668,40 +651,36 @@ static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) */ u32 omap2_clksel_get_divisor(struct clk *clk) { - u32 field_mask, field_val; - void __iomem *div_addr; + u32 v; - div_addr = omap2_get_clksel(clk, &field_mask); - if (!div_addr) + if (!clk->clksel_mask) return 0; - field_val = __raw_readl(div_addr) & field_mask; - field_val >>= __ffs(field_mask); + v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; + v >>= __ffs(clk->clksel_mask); - return omap2_clksel_to_divisor(clk, field_val); + return omap2_clksel_to_divisor(clk, v); } int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { - u32 field_mask, field_val, reg_val, validrate, new_div = 0; - void __iomem *div_addr; + u32 v, field_val, validrate, new_div = 0; - validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); - if (validrate != rate) + if (!clk->clksel_mask) return -EINVAL; - div_addr = omap2_get_clksel(clk, &field_mask); - if (!div_addr) + validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); + if (validrate != rate) return -EINVAL; field_val = omap2_divisor_to_clksel(clk, new_div); if (field_val == ~0) return -EINVAL; - reg_val = __raw_readl(div_addr); - reg_val &= ~field_mask; - reg_val |= (field_val << __ffs(field_mask)); - __raw_writel(reg_val, div_addr); + v = __raw_readl(clk->clksel_reg); + v &= ~clk->clksel_mask; + v |= field_val << __ffs(clk->clksel_mask); + __raw_writel(v, clk->clksel_reg); wmb(); clk->rate = clk->parent->rate / new_div; @@ -737,18 +716,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) /* * Converts encoded control register address into a full address - * On error, *src_addr will be returned as 0. + * On error, the return value (parent_div) will be 0. */ -static u32 omap2_clksel_get_src_field(void __iomem **src_addr, - struct clk *src_clk, u32 *field_mask, - struct clk *clk, u32 *parent_div) +static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, + u32 *field_val) { const struct clksel *clks; const struct clksel_rate *clkr; - *parent_div = 0; - *src_addr = NULL; - clks = omap2_get_clksel_by_parent(clk, src_clk); if (!clks) return 0; @@ -768,17 +743,14 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr, /* Should never happen. Add a clksel mask to the struct clk. */ WARN_ON(clk->clksel_mask == 0); - *field_mask = clk->clksel_mask; - *src_addr = clk->clksel_reg; - *parent_div = clkr->div; + *field_val = clkr->val; - return clkr->val; + return clkr->div; } int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) { - void __iomem *src_addr; - u32 field_val, field_mask, reg_val, parent_div; + u32 field_val, v, parent_div; if (clk->flags & CONFIG_PARTICIPANT) return -EINVAL; @@ -786,18 +758,18 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) if (!clk->clksel) return -EINVAL; - field_val = omap2_clksel_get_src_field(&src_addr, new_parent, - &field_mask, clk, &parent_div); - if (!src_addr) + parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); + if (!parent_div) return -EINVAL; if (clk->usecount > 0) _omap2_clk_disable(clk); /* Set new source value (previous dividers if any in effect) */ - reg_val = __raw_readl(src_addr) & ~field_mask; - reg_val |= (field_val << __ffs(field_mask)); - __raw_writel(reg_val, src_addr); + v = __raw_readl(clk->clksel_reg); + v &= ~clk->clksel_mask; + v |= field_val << __ffs(clk->clksel_mask); + __raw_writel(v, clk->clksel_reg); wmb(); if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { -- cgit v1.2.3 From f8de9b2c45c4506702da4bd3a5bc7630754077f9 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:27:31 -0700 Subject: [ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.h Move the contents of the arch/arm/mach-omap2/memory.h file to the existing mach/sdrc.h file, and remove memory.h. Modify files which include memory.h to include asm/arch/sdrc.h instead. linux-omap source commit is e7ae2d89921372fc4b9712a32cc401d645597807. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/mach-omap2/clock24xx.c | 2 +- arch/arm/mach-omap2/clock34xx.c | 2 +- arch/arm/mach-omap2/io.c | 4 ++-- arch/arm/mach-omap2/memory.c | 9 ++++++- arch/arm/mach-omap2/memory.h | 43 ---------------------------------- arch/arm/plat-omap/include/mach/gpmc.h | 2 +- arch/arm/plat-omap/include/mach/sdrc.h | 21 +++++++++++++++++ 8 files changed, 35 insertions(+), 50 deletions(-) delete mode 100644 arch/arm/mach-omap2/memory.h (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 5d7d4c52f37e..18fddb660ff9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -29,7 +29,7 @@ #include #include -#include "memory.h" +#include #include "sdrc.h" #include "clock.h" #include "prm.h" diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index b9902666e4b7..83911ad48733 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -33,7 +33,7 @@ #include #include -#include "memory.h" +#include #include "clock.h" #include "prm.h" #include "prm-regbits-24xx.h" diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 3d756babb2f4..52385b1506e0 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -32,7 +32,7 @@ #include #include -#include "memory.h" +#include #include "clock.h" #include "prm.h" #include "prm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5ea64f926ed5..2b5f28a3c4b4 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -27,8 +27,8 @@ #include #include #include - -#include "memory.h" +#include +#include #include "clock.h" diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c index 882c70224292..93cb25715bac 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/memory.c @@ -29,9 +29,16 @@ #include "prm.h" -#include "memory.h" +#include #include "sdrc.h" +/* Memory timing, DLL mode flags */ +#define M_DDR 1 +#define M_LOCK_CTRL (1 << 2) +#define M_UNLOCK 0 +#define M_LOCK 1 + + void __iomem *omap2_sdrc_base; void __iomem *omap2_sms_base; diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h deleted file mode 100644 index bb3db80a7c46..000000000000 --- a/arch/arm/mach-omap2/memory.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/memory.h - * - * Interface for memory timing related functions for OMAP24XX - * - * Copyright (C) 2005 Texas Instruments Inc. - * Richard Woodruff - * - * Copyright (C) 2005 Nokia Corporation - * Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H -#define ARCH_ARM_MACH_OMAP2_MEMORY_H - -/* Memory timings */ -#define M_DDR 1 -#define M_LOCK_CTRL (1 << 2) -#define M_UNLOCK 0 -#define M_LOCK 1 - -struct memory_timings { - u32 m_type; /* ddr = 1, sdr = 0 */ - u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ - u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ - u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ - u32 base_cs; /* base chip select to use for calculations */ -}; - -extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); -extern u32 omap2_memory_get_slow_dll_ctrl(void); -extern u32 omap2_memory_get_fast_dll_ctrl(void); -extern u32 omap2_memory_get_type(void); -u32 omap2_dll_force_needed(void); -u32 omap2_reprogram_sdrc(u32 level, u32 force); -void __init omap2_init_memory(void); -void __init gpmc_init(void); - -#endif diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h index 45b678439bb7..921b16532ff5 100644 --- a/arch/arm/plat-omap/include/mach/gpmc.h +++ b/arch/arm/plat-omap/include/mach/gpmc.h @@ -103,6 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); extern void gpmc_cs_free(int cs); extern int gpmc_cs_set_reserved(int cs, int reserved); extern int gpmc_cs_reserved(int cs); -extern void gpmc_init(void); +extern void __init gpmc_init(void); #endif diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h index a98c6c3beb2c..c905b5268e56 100644 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ b/arch/arm/plat-omap/include/mach/sdrc.h @@ -74,4 +74,25 @@ #define SMS_SYSCONFIG 0x010 /* REVISIT: fill in other SMS registers here */ +#ifndef __ASSEMBLER__ + +struct memory_timings { + u32 m_type; /* ddr = 1, sdr = 0 */ + u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ + u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ + u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ + u32 base_cs; /* base chip select to use for calculations */ +}; + +extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); +extern u32 omap2_memory_get_slow_dll_ctrl(void); +extern u32 omap2_memory_get_fast_dll_ctrl(void); +extern u32 omap2_memory_get_type(void); +u32 omap2_dll_force_needed(void); +u32 omap2_reprogram_sdrc(u32 level, u32 force); +void __init omap2_init_memory(void); + +#endif + + #endif -- cgit v1.2.3 From 8463e20a58e8b8c88fab948b8610504cbf604294 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 28 Jan 2009 12:27:45 -0700 Subject: [ARM] OMAP3: PM: Make sure clk_disable_unused() order is correct Current implementation will disable clocks in the order defined in clock34xx.h, at least DPLL4_M2X2 will hang in certain cases (and prevent retention / off) if clocks are not disabled in correct order. This patch makes sure the parent clocks will be active when disabling a clock. linux-omap source commit is 672680063420ef8c8c4e7271984bb9cc08171d29. Signed-off-by: Tero Kristo Signed-off-by: Kevin Hilman Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 18fddb660ff9..478ca660fffd 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -1000,6 +1000,10 @@ void omap2_clk_disable_unused(struct clk *clk) return; printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); - _omap2_clk_disable(clk); + if (cpu_is_omap34xx()) { + omap2_clk_enable(clk); + omap2_clk_disable(clk); + } else + _omap2_clk_disable(clk); } #endif -- cgit v1.2.3 From 3f0a820c4c0b4670fb5f164baa5582e23c2ef118 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 31 Jan 2009 10:05:51 +0000 Subject: [ARM] omap: create a proper tree of clocks Traditionally, we've tracked the parent/child relationships between clk structures by setting the child's parent member to point at the upstream clock. As a result, when decending the tree, we have had to scan all clocks to find the children. Avoid this wasteful scanning by keeping a list of the clock's children. Signed-off-by: Russell King --- arch/arm/mach-omap1/clock.c | 3 ++ arch/arm/mach-omap1/clock.h | 7 +-- arch/arm/mach-omap2/clock.c | 4 +- arch/arm/mach-omap2/clock24xx.c | 3 ++ arch/arm/mach-omap2/clock24xx.h | 28 ++++------ arch/arm/mach-omap2/clock34xx.c | 3 ++ arch/arm/mach-omap2/clock34xx.h | 96 ++++++--------------------------- arch/arm/plat-omap/clock.c | 51 +++++++++++------- arch/arm/plat-omap/include/mach/clock.h | 7 ++- 9 files changed, 74 insertions(+), 128 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 1e477af666ee..ccf989f4aa7d 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -782,6 +782,9 @@ int __init omap1_clk_init(void) /* By default all idlect1 clocks are allowed to idle */ arm_idlect1_mask = ~0; + for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) + clk_init_one(c->lk.clk); + cpu_mask = 0; if (cpu_is_omap16xx()) cpu_mask |= CK_16XX; diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 1b4dd056d9bd..28bc74e93e8d 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -155,7 +155,6 @@ static struct clk ck_dpll1 = { .name = "ck_dpll1", .ops = &clkops_null, .parent = &ck_ref, - .flags = RATE_PROPAGATES, }; static struct arm_idlect1_clk ck_dpll1out = { @@ -163,8 +162,7 @@ static struct arm_idlect1_clk ck_dpll1out = { .name = "ck_dpll1out", .ops = &clkops_generic, .parent = &ck_dpll1, - .flags = CLOCK_IDLE_CONTROL | - ENABLE_REG_32BIT | RATE_PROPAGATES, + .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), .enable_bit = EN_CKOUT_ARM, .recalc = &followparent_recalc, @@ -187,7 +185,6 @@ static struct clk arm_ck = { .name = "arm_ck", .ops = &clkops_null, .parent = &ck_dpll1, - .flags = RATE_PROPAGATES, .rate_offset = CKCTL_ARMDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, @@ -328,7 +325,7 @@ static struct arm_idlect1_clk tc_ck = { .name = "tc_ck", .ops = &clkops_null, .parent = &ck_dpll1, - .flags = RATE_PROPAGATES | CLOCK_IDLE_CONTROL, + .flags = CLOCK_IDLE_CONTROL, .rate_offset = CKCTL_TCDIV_OFFSET, .recalc = &omap1_ckctl_recalc, .round_rate = omap1_clk_round_rate_ckctl_arm, diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 478ca660fffd..38a7898d0ce3 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -175,7 +175,7 @@ void omap2_init_clksel_parent(struct clk *clk) clk->name, clks->parent->name, ((clk->parent) ? clk->parent->name : "NULL")); - clk->parent = clks->parent; + clk_reparent(clk, clks->parent); }; found = 1; } @@ -780,7 +780,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) if (clk->usecount > 0) _omap2_clk_enable(clk); - clk->parent = new_parent; + clk_reparent(clk, new_parent); /* CLKSEL clocks follow their parents' rates, divided by a divisor */ clk->rate = new_parent->rate; diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 4564ae32ae02..1a885976c257 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -718,6 +718,9 @@ int __init omap2_clk_init(void) omap2_sys_clk_recalc(&sys_ck); propagate_rate(&sys_ck); + for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) + clk_init_one(c->lk.clk); + cpu_mask = 0; if (cpu_is_omap2420()) cpu_mask |= CK_242X; diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 7731ab6acd18..759489822ee9 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -621,7 +621,7 @@ static struct clk func_32k_ck = { .name = "func_32k_ck", .ops = &clkops_null, .rate = 32000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, .clkdm_name = "wkup_clkdm", }; @@ -629,7 +629,6 @@ static struct clk func_32k_ck = { static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ .name = "osc_ck", .ops = &clkops_oscck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_osc_clk_recalc, }; @@ -639,7 +638,6 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ .name = "sys_ck", /* ~ ref_clk also */ .ops = &clkops_null, .parent = &osc_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_sys_clk_recalc, }; @@ -648,7 +646,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ .name = "alt_ck", .ops = &clkops_null, .rate = 54000000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, .clkdm_name = "wkup_clkdm", }; @@ -680,7 +678,6 @@ static struct clk dpll_ck = { .ops = &clkops_null, .parent = &sys_ck, /* Can be func_32k also */ .dpll_data = &dpll_dd, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_dpllcore_recalc, .set_rate = &omap2_reprogram_dpllcore, @@ -691,7 +688,7 @@ static struct clk apll96_ck = { .ops = &clkops_fixed, .parent = &sys_ck, .rate = 96000000, - .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, + .flags = RATE_FIXED | ENABLE_ON_INIT, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, @@ -702,7 +699,7 @@ static struct clk apll54_ck = { .ops = &clkops_fixed, .parent = &sys_ck, .rate = 54000000, - .flags = RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, + .flags = RATE_FIXED | ENABLE_ON_INIT, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, @@ -734,7 +731,6 @@ static struct clk func_54m_ck = { .name = "func_54m_ck", .ops = &clkops_null, .parent = &apll54_ck, /* can also be alt_clk */ - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -747,7 +743,6 @@ static struct clk core_ck = { .name = "core_ck", .ops = &clkops_null, .parent = &dpll_ck, /* can also be 32k */ - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -774,7 +769,6 @@ static struct clk func_96m_ck = { .name = "func_96m_ck", .ops = &clkops_null, .parent = &apll96_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -807,7 +801,6 @@ static struct clk func_48m_ck = { .name = "func_48m_ck", .ops = &clkops_null, .parent = &apll96_ck, /* 96M or Alt */ - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), @@ -823,7 +816,6 @@ static struct clk func_12m_ck = { .ops = &clkops_null, .parent = &func_48m_ck, .fixed_div = 4, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &omap2_fixed_divisor_recalc, }; @@ -876,7 +868,6 @@ static struct clk sys_clkout_src = { .name = "sys_clkout_src", .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, @@ -921,7 +912,6 @@ static struct clk sys_clkout2_src = { .name = "sys_clkout2_src", .ops = &clkops_omap2_dflt, .parent = &func_54m_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, @@ -992,7 +982,7 @@ static struct clk mpu_ck = { /* Control cpu */ .name = "mpu_ck", .ops = &clkops_null, .parent = &core_ck, - .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "mpu_clkdm", .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), @@ -1034,7 +1024,7 @@ static struct clk dsp_fck = { .name = "dsp_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "dsp_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, @@ -1102,7 +1092,7 @@ static struct clk iva1_ifck = { .name = "iva1_ifck", .ops = &clkops_omap2_dflt_wait, .parent = &core_ck, - .flags = CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP, + .flags = CONFIG_PARTICIPANT | DELAYED_APP, .clkdm_name = "iva1_clkdm", .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, @@ -1165,7 +1155,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ .name = "core_l3_ck", .ops = &clkops_null, .parent = &core_ck, - .flags = DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES, + .flags = DELAYED_APP | CONFIG_PARTICIPANT, .clkdm_name = "core_l3_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, @@ -1227,7 +1217,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */ .name = "l4_ck", .ops = &clkops_null, .parent = &core_l3_ck, - .flags = DELAYED_APP | RATE_PROPAGATES, + .flags = DELAYED_APP, .clkdm_name = "core_l4_clkdm", .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 75eb2546bb06..a853b1e149ee 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -903,6 +903,9 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); + for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) + clk_init_one(c->lk.clk); + for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 681acf0427c1..2138a58f6346 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -60,14 +60,14 @@ static struct clk omap_32k_fck = { .name = "omap_32k_fck", .ops = &clkops_null, .rate = 32768, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static struct clk secure_32k_fck = { .name = "secure_32k_fck", .ops = &clkops_null, .rate = 32768, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; /* Virtual source clocks for osc_sys_ck */ @@ -75,42 +75,42 @@ static struct clk virt_12m_ck = { .name = "virt_12m_ck", .ops = &clkops_null, .rate = 12000000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static struct clk virt_13m_ck = { .name = "virt_13m_ck", .ops = &clkops_null, .rate = 13000000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static struct clk virt_16_8m_ck = { .name = "virt_16_8m_ck", .ops = &clkops_null, .rate = 16800000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static struct clk virt_19_2m_ck = { .name = "virt_19_2m_ck", .ops = &clkops_null, .rate = 19200000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static struct clk virt_26m_ck = { .name = "virt_26m_ck", .ops = &clkops_null, .rate = 26000000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static struct clk virt_38_4m_ck = { .name = "virt_38_4m_ck", .ops = &clkops_null, .rate = 38400000, - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, }; static const struct clksel_rate osc_sys_12m_rates[] = { @@ -163,7 +163,7 @@ static struct clk osc_sys_ck = { .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, .clksel = osc_sys_clksel, /* REVISIT: deal with autoextclkmode? */ - .flags = RATE_FIXED | RATE_PROPAGATES, + .flags = RATE_FIXED, .recalc = &omap2_clksel_recalc, }; @@ -188,21 +188,18 @@ static struct clk sys_ck = { .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, .clksel_mask = OMAP_SYSCLKDIV_MASK, .clksel = sys_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; static struct clk sys_altclk = { .name = "sys_altclk", .ops = &clkops_null, - .flags = RATE_PROPAGATES, }; /* Optional external clock input for some McBSPs */ static struct clk mcbsp_clks = { .name = "mcbsp_clks", .ops = &clkops_null, - .flags = RATE_PROPAGATES, }; /* PRM EXTERNAL CLOCK OUTPUT */ @@ -279,7 +276,6 @@ static struct clk dpll1_ck = { .ops = &clkops_null, .parent = &sys_ck, .dpll_data = &dpll1_dd, - .flags = RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .clkdm_name = "dpll1_clkdm", @@ -294,7 +290,6 @@ static struct clk dpll1_x2_ck = { .name = "dpll1_x2_ck", .ops = &clkops_null, .parent = &dpll1_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll1_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -317,7 +312,6 @@ static struct clk dpll1_x2m2_ck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll1_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -353,7 +347,6 @@ static struct clk dpll2_ck = { .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll2_dd, - .flags = RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .clkdm_name = "dpll2_clkdm", @@ -378,7 +371,6 @@ static struct clk dpll2_m2_ck = { OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll2_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -413,7 +405,6 @@ static struct clk dpll3_ck = { .ops = &clkops_null, .parent = &sys_ck, .dpll_data = &dpll3_dd, - .flags = RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_dpll_recalc, @@ -427,7 +418,6 @@ static struct clk dpll3_x2_ck = { .name = "dpll3_x2_ck", .ops = &clkops_null, .parent = &dpll3_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -481,7 +471,6 @@ static struct clk dpll3_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll3_clkdm", .round_rate = &omap2_clksel_round_rate, .set_rate = &omap3_core_dpll_m2_set_rate, @@ -501,7 +490,6 @@ static struct clk core_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = core_ck_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -518,7 +506,6 @@ static struct clk dpll3_m2x2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = dpll3_m2x2_ck_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -538,7 +525,6 @@ static struct clk dpll3_m3_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -550,7 +536,7 @@ static struct clk dpll3_m3x2_ck = { .parent = &dpll3_m3_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, - .flags = RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -569,7 +555,6 @@ static struct clk emu_core_alwon_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, .clksel = emu_core_alwon_ck_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -603,7 +588,6 @@ static struct clk dpll4_ck = { .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll4_dd, - .flags = RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_dpll4_set_rate, .clkdm_name = "dpll4_clkdm", @@ -619,7 +603,6 @@ static struct clk dpll4_x2_ck = { .name = "dpll4_x2_ck", .ops = &clkops_null, .parent = &dpll4_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -638,7 +621,6 @@ static struct clk dpll4_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3430_DIV_96M_MASK, .clksel = div16_dpll4_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -650,7 +632,7 @@ static struct clk dpll4_m2x2_ck = { .parent = &dpll4_m2_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, - .flags = RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -675,7 +657,6 @@ static struct clk omap_96m_alwon_fck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = omap_96m_alwon_fck_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -683,7 +664,6 @@ static struct clk cm_96m_fck = { .name = "cm_96m_fck", .ops = &clkops_null, .parent = &omap_96m_alwon_fck, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -711,7 +691,6 @@ static struct clk omap_96m_fck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_96M_MASK, .clksel = omap_96m_fck_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -724,7 +703,6 @@ static struct clk dpll4_m3_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, .clksel = div16_dpll4_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -737,7 +715,7 @@ static struct clk dpll4_m3x2_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, - .flags = RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -756,7 +734,6 @@ static struct clk virt_omap_54m_fck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, .clksel = virt_omap_54m_fck_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -783,7 +760,6 @@ static struct clk omap_54m_fck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_54M_MASK, .clksel = omap_54m_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -810,7 +786,6 @@ static struct clk omap_48m_fck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_48M_MASK, .clksel = omap_48m_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -819,7 +794,6 @@ static struct clk omap_12m_fck = { .ops = &clkops_null, .parent = &omap_48m_fck, .fixed_div = 4, - .flags = RATE_PROPAGATES, .recalc = &omap2_fixed_divisor_recalc, }; @@ -832,7 +806,6 @@ static struct clk dpll4_m4_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, .clksel = div16_dpll4_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, .set_rate = &omap2_clksel_set_rate, @@ -846,7 +819,7 @@ static struct clk dpll4_m4x2_ck = { .parent = &dpll4_m4_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -860,7 +833,6 @@ static struct clk dpll4_m5_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, .clksel = div16_dpll4_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -872,7 +844,7 @@ static struct clk dpll4_m5x2_ck = { .parent = &dpll4_m5_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, - .flags = RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -886,7 +858,6 @@ static struct clk dpll4_m6_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, .clksel = div16_dpll4_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -899,7 +870,7 @@ static struct clk dpll4_m6x2_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, - .flags = RATE_PROPAGATES | INVERT_ENABLE, + .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; @@ -908,7 +879,6 @@ static struct clk emu_per_alwon_ck = { .name = "emu_per_alwon_ck", .ops = &clkops_null, .parent = &dpll4_m6x2_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll4_clkdm", .recalc = &followparent_recalc, }; @@ -943,7 +913,6 @@ static struct clk dpll5_ck = { .ops = &clkops_noncore_dpll_ops, .parent = &sys_ck, .dpll_data = &dpll5_dd, - .flags = RATE_PROPAGATES, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .clkdm_name = "dpll5_clkdm", @@ -963,7 +932,6 @@ static struct clk dpll5_m2_ck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "dpll5_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -982,7 +950,6 @@ static struct clk omap_120m_fck = { .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .clksel = omap_120m_fck_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1025,7 +992,6 @@ static struct clk clkout2_src_ck = { .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, .clksel = clkout2_src_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "core_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1060,7 +1026,6 @@ static struct clk corex2_fck = { .name = "corex2_fck", .ops = &clkops_null, .parent = &dpll3_m2x2_ck, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1090,7 +1055,6 @@ static struct clk dpll1_fck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, .clksel = div4_core_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1114,7 +1078,6 @@ static struct clk mpu_ck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = mpu_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "mpu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1139,7 +1102,6 @@ static struct clk arm_fck = { .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1153,7 +1115,6 @@ static struct clk emu_mpu_alwon_ck = { .name = "emu_mpu_alwon_ck", .ops = &clkops_null, .parent = &mpu_ck, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1165,7 +1126,6 @@ static struct clk dpll2_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, .clksel = div4_core_clksel, - .flags = RATE_PROPAGATES, .recalc = &omap2_clksel_recalc, }; @@ -1193,7 +1153,6 @@ static struct clk iva2_ck = { OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, .clksel = iva2_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "iva2_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1213,7 +1172,6 @@ static struct clk l3_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1231,7 +1189,6 @@ static struct clk l4_ick = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, @@ -1281,7 +1238,6 @@ static struct clk gfx_l3_fck = { .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_l3_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1440,7 +1396,6 @@ static struct clk core_96m_fck = { .name = "core_96m_fck", .ops = &clkops_null, .parent = &omap_96m_fck, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1574,7 +1529,6 @@ static struct clk core_48m_fck = { .name = "core_48m_fck", .ops = &clkops_null, .parent = &omap_48m_fck, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1652,7 +1606,6 @@ static struct clk core_12m_fck = { .name = "core_12m_fck", .ops = &clkops_null, .parent = &omap_12m_fck, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -1692,7 +1645,6 @@ static struct clk ssi_ssr_fck = { .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -1718,7 +1670,6 @@ static struct clk core_l3_ick = { .ops = &clkops_null, .parent = &l3_ick, .init = &omap2_init_clk_clkdm, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; @@ -1759,7 +1710,6 @@ static struct clk security_l3_ick = { .name = "security_l3_ick", .ops = &clkops_null, .parent = &l3_ick, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -1779,7 +1729,6 @@ static struct clk core_l4_ick = { .ops = &clkops_null, .parent = &l4_ick, .init = &omap2_init_clk_clkdm, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2062,7 +2011,6 @@ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", .ops = &clkops_null, .parent = &l4_ick, - .flags = RATE_PROPAGATES, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; @@ -2106,7 +2054,6 @@ static struct clk security_l4_ick2 = { .name = "security_l4_ick2", .ops = &clkops_null, .parent = &l4_ick, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2350,7 +2297,6 @@ static struct clk wkup_32k_fck = { .ops = &clkops_null, .init = &omap2_init_clk_clkdm, .parent = &omap_32k_fck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2379,7 +2325,6 @@ static struct clk wkup_l4_ick = { .name = "wkup_l4_ick", .ops = &clkops_null, .parent = &sys_ck, - .flags = RATE_PROPAGATES, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; @@ -2466,7 +2411,6 @@ static struct clk per_96m_fck = { .ops = &clkops_null, .parent = &omap_96m_alwon_fck, .init = &omap2_init_clk_clkdm, - .flags = RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2476,7 +2420,6 @@ static struct clk per_48m_fck = { .ops = &clkops_null, .parent = &omap_48m_fck, .init = &omap2_init_clk_clkdm, - .flags = RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2600,7 +2543,6 @@ static struct clk per_32k_alwon_fck = { .ops = &clkops_null, .parent = &omap_32k_fck, .clkdm_name = "per_clkdm", - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -2668,7 +2610,6 @@ static struct clk per_l4_ick = { .name = "per_l4_ick", .ops = &clkops_null, .parent = &l4_ick, - .flags = RATE_PROPAGATES, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; @@ -2948,7 +2889,6 @@ static struct clk emu_src_ck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2973,7 +2913,6 @@ static struct clk pclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -2997,7 +2936,6 @@ static struct clk pclkx2_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3014,7 +2952,6 @@ static struct clk atclk_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3026,7 +2963,6 @@ static struct clk traceclk_src_fck = { .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, - .flags = RATE_PROPAGATES, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; @@ -3063,7 +2999,6 @@ static struct clk sr1_fck = { .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; @@ -3074,7 +3009,6 @@ static struct clk sr2_fck = { .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, - .flags = RATE_PROPAGATES, .recalc = &followparent_recalc, }; diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 54da27af0bd5..6a1737a74477 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -143,8 +143,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (ret == 0) { if (clk->recalc) clk->recalc(clk); - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); + propagate_rate(clk); } spin_unlock_irqrestore(&clockfw_lock, flags); @@ -166,8 +165,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) if (ret == 0) { if (clk->recalc) clk->recalc(clk); - if (clk->flags & RATE_PROPAGATES) - propagate_rate(clk); + propagate_rate(clk); } spin_unlock_irqrestore(&clockfw_lock, flags); @@ -214,24 +212,31 @@ void followparent_recalc(struct clk *clk) clk->rate = clk->parent->rate; } +void clk_reparent(struct clk *child, struct clk *parent) +{ + list_del_init(&child->sibling); + if (parent) + list_add(&child->sibling, &parent->children); + child->parent = parent; + + /* now do the debugfs renaming to reattach the child + to the proper parent */ +} + /* Propagate rate to children */ void propagate_rate(struct clk * tclk) { struct clk *clkp; - if (tclk == NULL || IS_ERR(tclk)) - return; - - list_for_each_entry(clkp, &clocks, node) { - if (likely(clkp->parent != tclk)) - continue; + list_for_each_entry(clkp, &tclk->children, sibling) { if (clkp->recalc) clkp->recalc(clkp); - if (clkp->flags & RATE_PROPAGATES) - propagate_rate(clkp); + propagate_rate(clkp); } } +static LIST_HEAD(root_clks); + /** * recalculate_root_clocks - recalculate and propagate all root clocks * @@ -243,16 +248,18 @@ void recalculate_root_clocks(void) { struct clk *clkp; - list_for_each_entry(clkp, &clocks, node) { - if (!clkp->parent) { - if (clkp->recalc) - clkp->recalc(clkp); - if (clkp->flags & RATE_PROPAGATES) - propagate_rate(clkp); - } + list_for_each_entry(clkp, &root_clks, sibling) { + if (clkp->recalc) + clkp->recalc(clkp); + propagate_rate(clkp); } } +void clk_init_one(struct clk *clk) +{ + INIT_LIST_HEAD(&clk->children); +} + int clk_register(struct clk *clk) { if (clk == NULL || IS_ERR(clk)) @@ -265,6 +272,11 @@ int clk_register(struct clk *clk) return 0; mutex_lock(&clocks_mutex); + if (clk->parent) + list_add(&clk->sibling, &clk->parent->children); + else + list_add(&clk->sibling, &root_clks); + list_add(&clk->node, &clocks); if (clk->init) clk->init(clk); @@ -280,6 +292,7 @@ void clk_unregister(struct clk *clk) return; mutex_lock(&clocks_mutex); + list_del(&clk->sibling); list_del(&clk->node); mutex_unlock(&clocks_mutex); } diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 8705902de1d6..af6ae4fa46d6 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -70,6 +70,8 @@ struct clk { const char *name; int id; struct clk *parent; + struct list_head children; + struct list_head sibling; /* node for children */ unsigned long rate; __u32 flags; void __iomem *enable_reg; @@ -115,7 +117,9 @@ struct clk_functions { extern unsigned int mpurate; extern int clk_init(struct clk_functions *custom_clocks); +extern void clk_init_one(struct clk *clk); extern int clk_register(struct clk *clk); +extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); @@ -131,8 +135,7 @@ extern const struct clkops clkops_null; /* Clock flags */ /* bit 0 is free */ #define RATE_FIXED (1 << 1) /* Fixed clock rate */ -#define RATE_PROPAGATES (1 << 2) /* Program children too */ -/* bits 3-4 are free */ +/* bits 2-4 are free */ #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ #define CLOCK_IDLE_CONTROL (1 << 7) #define CLOCK_NO_IDLE_PARENT (1 << 8) -- cgit v1.2.3 From de07fedd79999668c4c112a2ba3eaf3d7434235c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:35:01 -0700 Subject: [ARM] OMAP2/3 clock: don't use a barrier after clk_disable() clk_disable() previously used an ARM barrier, wmb(), to try to ensure that the hardware write completed before continuing. There are some problems with this approach. The first problem is that wmb() only ensures that the write leaves the ARM -- not that it actually reaches the endpoint device. In this case, the endpoint device - either the PRM, CM, or SCM - is three interconnects away from the ARM, and the final interconnect is low-speed. And the OCP interconnects will post the write, who knows how long that will take to complete. So the wmb() is not really what we want. Worse, the wmb() is indiscriminate; it will cause the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. This first problem could be fixed by doing a readback of the same PRM/CM/SCM register. Since these devices use a single OCP thread, this will cause the MPU to wait for the write to complete. But the primary problem is a conceptual one: clk_disable() should not need any kind of barrier. clk_enable() needs one since device driver code must not access a device until its clocks are known to be enabled. But clk_disable() has no such restriction. Since blocking the MPU on a PRM/CM/SCM write can be a very high-latency operation - several hundred MPU cycles - it's worth avoiding this barrier if possible. linux-omap source commit is f4aacad2c0ed1055622d5c1e910befece24ef0e2. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 38a7898d0ce3..0803c8c811f4 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -353,7 +353,7 @@ static void omap2_dflt_clk_disable(struct clk *clk) else v &= ~(1 << clk->enable_bit); __raw_writel(v, clk->enable_reg); - wmb(); + /* No OCP barrier needed here since it is a disable operation */ } const struct clkops clkops_omap2_dflt_wait = { -- cgit v1.2.3 From 439764cc18beb20ef409991e75e29b460db71d33 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:35:03 -0700 Subject: [ARM] OMAP2xxx clock: consolidate DELAYED_APP clock commits; fix barrier Consolidate the commit code for DELAYED_APP clocks into a subroutine, _omap2xxx_clk_commit(). Also convert the MPU barrier wmb() into an OCP barrier, since with an MPU barrier, we have no guarantee that the write actually reached the endpoint device. linux-omap source commit is 0f5bdb736515801b296125d16937a21ff7b3cfdc. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 0803c8c811f4..7f12230fef73 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -74,6 +74,28 @@ u8 cpu_mask; * OMAP2/3 specific clock functions *-------------------------------------------------------------------------*/ +/** + * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware + * @clk: struct clk * + * + * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes + * don't take effect until the VALID_CONFIG bit is written, write the + * VALID_CONFIG bit and wait for the write to complete. No return value. + */ +static void _omap2xxx_clk_commit(struct clk *clk) +{ + if (!cpu_is_omap24xx()) + return; + + if (!(clk->flags & DELAYED_APP)) + return; + + prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, + OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); + /* OCP barrier */ + prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); +} + /* * _dpll_test_fint - test whether an Fint value is valid for the DPLL * @clk: DPLL struct clk to test @@ -685,11 +707,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) clk->rate = clk->parent->rate / new_div; - if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - prm_write_mod_reg(OMAP24XX_VALID_CONFIG, - OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); - wmb(); - } + _omap2xxx_clk_commit(clk); return 0; } @@ -772,10 +790,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) __raw_writel(v, clk->clksel_reg); wmb(); - if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { - __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); - wmb(); - } + _omap2xxx_clk_commit(clk); if (clk->usecount > 0) _omap2_clk_enable(clk); -- cgit v1.2.3 From f11fda6a9173e8e6b152ba5cb26fa20095a4c60f Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 28 Jan 2009 12:35:06 -0700 Subject: [ARM] OMAP2/3 clock: convert remaining MPU barriers into OCP barriers Several parts of the OMAP2/3 clock code use wmb() to try to ensure that the hardware write completes before continuing. This approach is problematic: wmb() only ensures that the write leaves the ARM. It does not ensure that the write actually reaches the endpoint device. The endpoint device in this case - either the PRM, CM, or SCM - is three interconnects away from the ARM - and the final interconnect is low-speed. And the OCP interconnects will post the write, and who knows how long that will take to complete. So the wmb() is not what we want. Worse, the wmb() is indiscriminate; it causes the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. Fix this by converting the wmb()s into readbacks of the same PRM/CM/SCM register. Since the PRM/CM/SCM devices use a single OCP thread, this will cause the MPU to block while waiting for posted writes to that device to complete. linux-omap source commit is 260f5487848681b4d8ea7430a709a601bbcb21d1. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7f12230fef73..666274a8b10d 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -334,7 +334,7 @@ static int omap2_dflt_clk_enable(struct clk *clk) else v |= (1 << clk->enable_bit); __raw_writel(v, clk->enable_reg); - wmb(); + v = __raw_readl(clk->enable_reg); /* OCP barrier */ return 0; } @@ -703,7 +703,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) v &= ~clk->clksel_mask; v |= field_val << __ffs(clk->clksel_mask); __raw_writel(v, clk->clksel_reg); - wmb(); + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ clk->rate = clk->parent->rate / new_div; @@ -788,7 +788,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) v &= ~clk->clksel_mask; v |= field_val << __ffs(clk->clksel_mask); __raw_writel(v, clk->clksel_reg); - wmb(); + v = __raw_readl(clk->clksel_reg); /* OCP barrier */ _omap2xxx_clk_commit(clk); -- cgit v1.2.3 From a7f8c599c570fc0e2396e8fdccaeeeaefc41dac8 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 31 Jan 2009 11:00:17 +0000 Subject: [ARM] omap: fix usecount decrement bug Based upon a patch from Paul Walmsley : If _omap2_clk_enable() fails, the clock's usecount must be decremented by one no matter whether the clock has a parent or not. but reorganised a bit. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 666274a8b10d..222c2c0d4a64 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -419,30 +419,30 @@ int omap2_clk_enable(struct clk *clk) int ret = 0; if (clk->usecount++ == 0) { - if (clk->parent) + if (clk->parent) { ret = omap2_clk_enable(clk->parent); - - if (ret != 0) { - clk->usecount--; - return ret; + if (ret) + goto err; } if (clk->clkdm) omap2_clkdm_clk_enable(clk->clkdm, clk); ret = _omap2_clk_enable(clk); - - if (ret != 0) { + if (ret) { if (clk->clkdm) omap2_clkdm_clk_disable(clk->clkdm, clk); - if (clk->parent) { + if (clk->parent) omap2_clk_disable(clk->parent); - clk->usecount--; - } + + goto err; } } + return ret; +err: + clk->usecount--; return ret; } -- cgit v1.2.3 From 8263e5b31eae2bbf689ff08a7da334329c9f353b Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 31 Jan 2009 11:02:37 +0000 Subject: [ARM] omap: fix clockdomain enable/disable ordering Based on a patch from Paul Walmsley : omap2_clk_enable() should enable a clock's clockdomain before attempting to enable its parent clock's clockdomain. Similarly, in the unlikely event that the parent clock enable fails, the clockdomain should be disabled. linux-omap source commit is 6d6e285e5a7912b1ea68fadac387304c914aaba8. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 222c2c0d4a64..1b40d757500d 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -419,20 +419,17 @@ int omap2_clk_enable(struct clk *clk) int ret = 0; if (clk->usecount++ == 0) { + if (clk->clkdm) + omap2_clkdm_clk_enable(clk->clkdm, clk); + if (clk->parent) { ret = omap2_clk_enable(clk->parent); if (ret) goto err; } - if (clk->clkdm) - omap2_clkdm_clk_enable(clk->clkdm, clk); - ret = _omap2_clk_enable(clk); if (ret) { - if (clk->clkdm) - omap2_clkdm_clk_disable(clk->clkdm, clk); - if (clk->parent) omap2_clk_disable(clk->parent); @@ -442,6 +439,8 @@ int omap2_clk_enable(struct clk *clk) return ret; err: + if (clk->clkdm) + omap2_clkdm_clk_disable(clk->clkdm, clk); clk->usecount--; return ret; } -- cgit v1.2.3 From 8b9dbc16d4f5786c6c930ab028722e3ed7e4285b Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 12 Feb 2009 10:12:59 +0000 Subject: [ARM] omap: arrange for clock recalc methods to return the rate linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce introduces a way to "dry run" clock changes before they're committed. However, this involves putting logic to handle this into each and every recalc function, and unfortunately due to the caching, led to some bugs. Solve both of issues by making the recalc methods always return the clock rate for the clock, which the caller decides what to do with. Signed-off-by: Russell King --- arch/arm/mach-omap1/clock.c | 32 ++++++++++++-------------------- arch/arm/mach-omap1/clock.h | 10 +++++----- arch/arm/mach-omap2/clock.c | 17 +++++++++-------- arch/arm/mach-omap2/clock.h | 4 ++-- arch/arm/mach-omap2/clock24xx.c | 20 ++++++++++---------- arch/arm/mach-omap2/clock24xx.h | 10 +++++----- arch/arm/mach-omap2/clock34xx.c | 12 +++++++----- arch/arm/mach-omap2/clock34xx.h | 4 ++-- arch/arm/plat-omap/clock.c | 15 ++++++--------- arch/arm/plat-omap/include/mach/clock.h | 4 ++-- 10 files changed, 60 insertions(+), 68 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index ccf989f4aa7d..dafe4f71d15f 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -156,27 +156,25 @@ __u32 arm_idlect1_mask; * Omap1 specific clock functions *-------------------------------------------------------------------------*/ -static void omap1_watchdog_recalc(struct clk * clk) +static unsigned long omap1_watchdog_recalc(struct clk *clk) { - clk->rate = clk->parent->rate / 14; + return clk->parent->rate / 14; } -static void omap1_uart_recalc(struct clk * clk) +static unsigned long omap1_uart_recalc(struct clk *clk) { unsigned int val = __raw_readl(clk->enable_reg); - if (val & clk->enable_bit) - clk->rate = 48000000; - else - clk->rate = 12000000; + return val & clk->enable_bit ? 48000000 : 12000000; } -static void omap1_sossi_recalc(struct clk *clk) +static unsigned long omap1_sossi_recalc(struct clk *clk) { u32 div = omap_readl(MOD_CONF_CTRL_1); div = (div >> 17) & 0x7; div++; - clk->rate = clk->parent->rate / div; + + return clk->parent->rate / div; } static int omap1_clk_enable_dsp_domain(struct clk *clk) @@ -344,19 +342,15 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) return dsor_exp; } -static void omap1_ckctl_recalc(struct clk * clk) +static unsigned long omap1_ckctl_recalc(struct clk *clk) { - int dsor; - /* Calculate divisor encoded as 2-bit exponent */ - dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); + int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); - if (unlikely(clk->rate == clk->parent->rate / dsor)) - return; /* No change, quick exit */ - clk->rate = clk->parent->rate / dsor; + return clk->parent->rate / dsor; } -static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) +static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) { int dsor; @@ -371,9 +365,7 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); omap1_clk_disable(&api_ck.clk); - if (unlikely(clk->rate == clk->parent->rate / dsor)) - return; /* No change, quick exit */ - clk->rate = clk->parent->rate / dsor; + return clk->parent->rate / dsor; } /* MPU virtual clock functions */ diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 28bc74e93e8d..17f874271255 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h @@ -13,14 +13,14 @@ #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H #define __ARCH_ARM_MACH_OMAP1_CLOCK_H -static void omap1_ckctl_recalc(struct clk * clk); -static void omap1_watchdog_recalc(struct clk * clk); +static unsigned long omap1_ckctl_recalc(struct clk *clk); +static unsigned long omap1_watchdog_recalc(struct clk *clk); static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); -static void omap1_sossi_recalc(struct clk *clk); -static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); +static unsigned long omap1_sossi_recalc(struct clk *clk); +static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); -static void omap1_uart_recalc(struct clk * clk); +static unsigned long omap1_uart_recalc(struct clk *clk); static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); static void omap1_init_ext_clk(struct clk * clk); diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 1b40d757500d..5020cb1f2e7e 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -239,11 +239,11 @@ u32 omap2_get_dpll_rate(struct clk *clk) * Used for clocks that have the same value as the parent clock, * divided by some factor */ -void omap2_fixed_divisor_recalc(struct clk *clk) +unsigned long omap2_fixed_divisor_recalc(struct clk *clk) { WARN_ON(!clk->fixed_div); - clk->rate = clk->parent->rate / clk->fixed_div; + return clk->parent->rate / clk->fixed_div; } /** @@ -449,21 +449,22 @@ err: * Used for clocks that are part of CLKSEL_xyz governed clocks. * REVISIT: Maybe change to use clk->enable() functions like on omap1? */ -void omap2_clksel_recalc(struct clk *clk) +unsigned long omap2_clksel_recalc(struct clk *clk) { + unsigned long rate; u32 div = 0; pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); div = omap2_clksel_get_divisor(clk); if (div == 0) - return; + return clk->rate; - if (clk->rate == (clk->parent->rate / div)) - return; - clk->rate = clk->parent->rate / div; + rate = clk->parent->rate / div; + + pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); - pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); + return rate; } /** diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 90077f0df78d..ca6bf226859e 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -36,7 +36,7 @@ void omap2_clk_disable_unused(struct clk *clk); #define omap2_clk_disable_unused NULL #endif -void omap2_clksel_recalc(struct clk *clk); +unsigned long omap2_clksel_recalc(struct clk *clk); void omap2_init_clk_clkdm(struct clk *clk); void omap2_init_clksel_parent(struct clk *clk); u32 omap2_clksel_get_divisor(struct clk *clk); @@ -44,7 +44,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, u32 *new_div); u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); -void omap2_fixed_divisor_recalc(struct clk *clk); +unsigned long omap2_fixed_divisor_recalc(struct clk *clk); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); u32 omap2_get_dpll_rate(struct clk *clk); diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index 069f3e1827a6..f2b74e9b7d8d 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -369,9 +369,9 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } -static void omap2_dpllcore_recalc(struct clk *clk) +static unsigned long omap2_dpllcore_recalc(struct clk *clk) { - clk->rate = omap2_get_dpll_rate_24xx(clk); + return omap2_get_dpll_rate_24xx(clk); } static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) @@ -448,9 +448,9 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) * * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ -static void omap2_table_mpu_recalc(struct clk *clk) +static unsigned long omap2_table_mpu_recalc(struct clk *clk) { - clk->rate = curr_prcm_set->mpu_speed; + return curr_prcm_set->mpu_speed; } /* @@ -647,14 +647,14 @@ static u32 omap2_get_sysclkdiv(void) return div; } -static void omap2_osc_clk_recalc(struct clk *clk) +static unsigned long omap2_osc_clk_recalc(struct clk *clk) { - clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); + return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); } -static void omap2_sys_clk_recalc(struct clk *clk) +static unsigned long omap2_sys_clk_recalc(struct clk *clk) { - clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); + return clk->parent->rate / omap2_get_sysclkdiv(); } /* @@ -707,9 +707,9 @@ int __init omap2_clk_init(void) clk_init(&omap2_clk_functions); - omap2_osc_clk_recalc(&osc_ck); + osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); - omap2_sys_clk_recalc(&sys_ck); + sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); propagate_rate(&sys_ck); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 759489822ee9..11da6215392b 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -24,13 +24,13 @@ #include "cm-regbits-24xx.h" #include "sdrc.h" -static void omap2_table_mpu_recalc(struct clk *clk); +static unsigned long omap2_table_mpu_recalc(struct clk *clk); static int omap2_select_table_rate(struct clk *clk, unsigned long rate); static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); -static void omap2_sys_clk_recalc(struct clk *clk); -static void omap2_osc_clk_recalc(struct clk *clk); -static void omap2_sys_clk_recalc(struct clk *clk); -static void omap2_dpllcore_recalc(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_osc_clk_recalc(struct clk *clk); +static unsigned long omap2_sys_clk_recalc(struct clk *clk); +static unsigned long omap2_dpllcore_recalc(struct clk *clk); static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 3b6e27bc9fe3..fb0f53b96811 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -289,9 +289,9 @@ static struct omap_clk omap34xx_clks[] = { * * Recalculate and propagate the DPLL rate. */ -static void omap3_dpll_recalc(struct clk *clk) +static unsigned long omap3_dpll_recalc(struct clk *clk) { - clk->rate = omap2_get_dpll_rate(clk); + return omap2_get_dpll_rate(clk); } /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ @@ -787,9 +787,10 @@ static void omap3_dpll_deny_idle(struct clk *clk) * Using parent clock DPLL data, look up DPLL state. If locked, set our * rate to the dpll_clk * 2; otherwise, just use dpll_clk. */ -static void omap3_clkoutx2_recalc(struct clk *clk) +static unsigned long omap3_clkoutx2_recalc(struct clk *clk) { const struct dpll_data *dd; + unsigned long rate; u32 v; struct clk *pclk; @@ -808,9 +809,10 @@ static void omap3_clkoutx2_recalc(struct clk *clk) v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); if (v != DPLL_LOCKED) - clk->rate = clk->parent->rate; + rate = clk->parent->rate; else - clk->rate = clk->parent->rate * 2; + rate = clk->parent->rate * 2; + return rate; } /* Common clock code */ diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 2138a58f6346..764c7cd9fd84 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -27,8 +27,8 @@ #include "prm.h" #include "prm-regbits-34xx.h" -static void omap3_dpll_recalc(struct clk *clk); -static void omap3_clkoutx2_recalc(struct clk *clk); +static unsigned long omap3_dpll_recalc(struct clk *clk); +static unsigned long omap3_clkoutx2_recalc(struct clk *clk); static void omap3_dpll_allow_idle(struct clk *clk); static void omap3_dpll_deny_idle(struct clk *clk); static u32 omap3_dpll_autoidle_read(struct clk *clk); diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 9833d73511a1..08baa18497b2 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -126,7 +126,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) ret = arch_clock->clk_set_rate(clk, rate); if (ret == 0) { if (clk->recalc) - clk->recalc(clk); + clk->rate = clk->recalc(clk); propagate_rate(clk); } spin_unlock_irqrestore(&clockfw_lock, flags); @@ -148,7 +148,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) ret = arch_clock->clk_set_parent(clk, parent); if (ret == 0) { if (clk->recalc) - clk->recalc(clk); + clk->rate = clk->recalc(clk); propagate_rate(clk); } spin_unlock_irqrestore(&clockfw_lock, flags); @@ -188,12 +188,9 @@ static int __init omap_clk_setup(char *str) __setup("mpurate=", omap_clk_setup); /* Used for clocks that always have same value as the parent clock */ -void followparent_recalc(struct clk *clk) +unsigned long followparent_recalc(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) - return; - - clk->rate = clk->parent->rate; + return clk->parent->rate; } void clk_reparent(struct clk *child, struct clk *parent) @@ -214,7 +211,7 @@ void propagate_rate(struct clk * tclk) list_for_each_entry(clkp, &tclk->children, sibling) { if (clkp->recalc) - clkp->recalc(clkp); + clkp->rate = clkp->recalc(clkp); propagate_rate(clkp); } } @@ -234,7 +231,7 @@ void recalculate_root_clocks(void) list_for_each_entry(clkp, &root_clks, sibling) { if (clkp->recalc) - clkp->recalc(clkp); + clkp->rate = clkp->recalc(clkp); propagate_rate(clkp); } } diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 0ba28462a497..7b6f6bcbff94 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -75,7 +75,7 @@ struct clk { unsigned long rate; __u32 flags; void __iomem *enable_reg; - void (*recalc)(struct clk *); + unsigned long (*recalc)(struct clk *); int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); void (*init)(struct clk *); @@ -123,7 +123,7 @@ extern void clk_reparent(struct clk *child, struct clk *parent); extern void clk_unregister(struct clk *clk); extern void propagate_rate(struct clk *clk); extern void recalculate_root_clocks(void); -extern void followparent_recalc(struct clk *clk); +extern unsigned long followparent_recalc(struct clk *clk); extern void clk_enable_init_clocks(void); #ifdef CONFIG_CPU_FREQ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); -- cgit v1.2.3 From c0bf31320dea2cbcbab1f53ee15a8520f762409b Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 19 Feb 2009 13:29:22 +0000 Subject: [ARM] omap: add support for bypassing DPLLs This roughly corresponds with OMAP commits: 7d06c48, 3241b19, 88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8. For both OMAP2 and OMAP3, we note the reference and bypass clocks in the DPLL data structure. Whenever we modify the DPLL rate, we first ensure that both the reference and bypass clocks are enabled. Then, we decide whether to use the reference and DPLL, or the bypass clock if the desired rate is identical to the bypass rate, and program the DPLL appropriately. Finally, we update the clock's parent, and then disable the unused clocks. This keeps the parents correctly balanced, and more importantly ensures that the bypass clock is running whenever we reprogram the DPLL. This is especially important because the procedure for reprogramming the DPLL involves switching to the bypass clock. Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 47 +++++++-- arch/arm/mach-omap2/clock.h | 15 +++ arch/arm/mach-omap2/clock24xx.c | 39 ++++--- arch/arm/mach-omap2/clock24xx.h | 4 + arch/arm/mach-omap2/clock34xx.c | 90 ++++++++++++---- arch/arm/mach-omap2/clock34xx.h | 177 +++++--------------------------- arch/arm/mach-omap2/sdrc2xxx.c | 2 +- arch/arm/plat-omap/include/mach/clock.h | 11 +- 8 files changed, 186 insertions(+), 199 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 5020cb1f2e7e..40cb65ba1fac 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -211,25 +211,52 @@ void omap2_init_clksel_parent(struct clk *clk) return; } -/* Returns the DPLL rate */ +/** + * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate + * @clk: struct clk * of a DPLL + * + * DPLLs can be locked or bypassed - basically, enabled or disabled. + * When locked, the DPLL output depends on the M and N values. When + * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock + * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and + * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively + * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. + * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is + * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 + * if the clock @clk is not a DPLL. + */ u32 omap2_get_dpll_rate(struct clk *clk) { long long dpll_clk; - u32 dpll_mult, dpll_div, dpll; + u32 dpll_mult, dpll_div, v; struct dpll_data *dd; dd = clk->dpll_data; - /* REVISIT: What do we return on error? */ if (!dd) return 0; - dpll = __raw_readl(dd->mult_div1_reg); - dpll_mult = dpll & dd->mult_mask; + /* Return bypass rate if DPLL is bypassed */ + v = __raw_readl(dd->control_reg); + v &= dd->enable_mask; + v >>= __ffs(dd->enable_mask); + + if (cpu_is_omap24xx()) { + if (v == OMAP2XXX_EN_DPLL_LPBYPASS || + v == OMAP2XXX_EN_DPLL_FRBYPASS) + return dd->clk_bypass->rate; + } else if (cpu_is_omap34xx()) { + if (v == OMAP3XXX_EN_DPLL_LPBYPASS || + v == OMAP3XXX_EN_DPLL_FRBYPASS) + return dd->clk_bypass->rate; + } + + v = __raw_readl(dd->mult_div1_reg); + dpll_mult = v & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); - dpll_div = dpll & dd->div1_mask; + dpll_div = v & dd->div1_mask; dpll_div >>= __ffs(dd->div1_mask); - dpll_clk = (long long)clk->parent->rate * dpll_mult; + dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; do_div(dpll_clk, dpll_div + 1); return dpll_clk; @@ -930,7 +957,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) pr_debug("clock: starting DPLL round_rate for clock %s, target rate " "%ld\n", clk->name, target_rate); - scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); + scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; dd->last_rounded_rate = 0; @@ -957,7 +984,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) break; r = _dpll_test_mult(&m, n, &new_rate, target_rate, - clk->parent->rate); + dd->clk_ref->rate); /* m can't be set low enough for this n - try with a larger n */ if (r == DPLL_MULT_UNDERFLOW) @@ -988,7 +1015,7 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) dd->last_rounded_m = min_e_m; dd->last_rounded_n = min_e_n; - dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate, + dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, min_e_m, min_e_n); pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index ca6bf226859e..2679ddfa6424 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -21,6 +21,21 @@ /* The maximum error between a target DPLL rate and the rounded rate in Hz */ #define DEFAULT_DPLL_RATE_TOLERANCE 50000 +/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ +#define CORE_CLK_SRC_32K 0x0 +#define CORE_CLK_SRC_DPLL 0x1 +#define CORE_CLK_SRC_DPLL_X2 0x2 + +/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ +#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 +#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 +#define OMAP2XXX_EN_DPLL_LOCKED 0x3 + +/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ +#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 +#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 +#define OMAP3XXX_EN_DPLL_LOCKED 0x7 + int omap2_clk_init(void); int omap2_clk_enable(struct clk *clk); void omap2_clk_disable(struct clk *clk); diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index f2b74e9b7d8d..1e839c5a28c5 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c @@ -236,19 +236,32 @@ static struct clk *sclk; * Omap24xx specific clock functions *-------------------------------------------------------------------------*/ -/* This actually returns the rate of core_ck, not dpll_ck. */ -static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) +/** + * omap2xxx_clk_get_core_rate - return the CORE_CLK rate + * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") + * + * Returns the CORE_CLK rate. CORE_CLK can have one of three rate + * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz + * (the latter is unusual). This currently should be called with + * struct clk *dpll_ck, which is a composite clock of dpll_ck and + * core_ck. + */ +static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) { - long long dpll_clk; - u8 amult; + long long core_clk; + u32 v; - dpll_clk = omap2_get_dpll_rate(tclk); + core_clk = omap2_get_dpll_rate(clk); - amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); - amult &= OMAP24XX_CORE_CLK_SRC_MASK; - dpll_clk *= amult; + v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v &= OMAP24XX_CORE_CLK_SRC_MASK; + + if (v == CORE_CLK_SRC_32K) + core_clk = 32768; + else + core_clk *= v; - return dpll_clk; + return core_clk; } static int omap2_enable_osc_ck(struct clk *clk) @@ -371,7 +384,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) static unsigned long omap2_dpllcore_recalc(struct clk *clk) { - return omap2_get_dpll_rate_24xx(clk); + return omap2xxx_clk_get_core_rate(clk); } static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) @@ -381,7 +394,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) struct prcm_config tmpset; const struct dpll_data *dd; - cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); + cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; @@ -516,7 +529,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) } curr_prcm_set = prcm; - cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); + cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); if (prcm->dpll_speed == cur_rate / 2) { omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); @@ -728,7 +741,7 @@ int __init omap2_clk_init(void) } /* Check the MPU rate set by bootloader */ - clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); + clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index 11da6215392b..33c3e5b14323 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h @@ -663,6 +663,10 @@ static struct dpll_data dpll_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP24XX_DPLL_MULT_MASK, .div1_mask = OMAP24XX_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, + .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), + .enable_mask = OMAP24XX_EN_DPLL_MASK, .max_multiplier = 1024, .min_divider = 1, .max_divider = 16, diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index fb0f53b96811..0a14dca31e30 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -93,7 +93,6 @@ static struct omap_clk omap34xx_clks[] = { CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), - CLK(NULL, "virt_omap_54m_fck", &virt_omap_54m_fck, CK_343X), CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), @@ -110,7 +109,6 @@ static struct omap_clk omap34xx_clks[] = { CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), - CLK(NULL, "omap_120m_fck", &omap_120m_fck, CK_3430ES2), CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), @@ -344,7 +342,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) unsigned long fint; u16 f = 0; - fint = clk->parent->rate / (n + 1); + fint = clk->dpll_data->clk_ref->rate / (n + 1); pr_debug("clock: fint is %lu\n", fint); @@ -411,7 +409,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) } /* - * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness + * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness * @clk: pointer to a DPLL struct clk * * Instructs a non-CORE DPLL to enter low-power bypass mode. In @@ -501,14 +499,25 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) static int omap3_noncore_dpll_enable(struct clk *clk) { int r; + struct dpll_data *dd; if (clk == &dpll3_ck) return -EINVAL; - if (clk->parent->rate == omap2_get_dpll_rate(clk)) + dd = clk->dpll_data; + if (!dd) + return -EINVAL; + + if (clk->rate == dd->clk_bypass->rate) { + WARN_ON(clk->parent != dd->clk_bypass); r = _omap3_noncore_dpll_bypass(clk); - else + } else { + WARN_ON(clk->parent != dd->clk_ref); r = _omap3_noncore_dpll_lock(clk); + } + /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ + if (!r) + clk->rate = omap2_get_dpll_rate(clk); return r; } @@ -583,13 +592,18 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) * @clk: struct clk * of DPLL to set * @rate: rounded target rate * - * Program the DPLL with the rounded target rate. Returns -EINVAL upon - * error, or 0 upon success. + * Set the DPLL CLKOUT to the target rate. If the DPLL can enter + * low-power bypass, and the target rate is the bypass source clock + * rate, then configure the DPLL for bypass. Otherwise, round the + * target rate if it hasn't been done already, then program and lock + * the DPLL. Returns -EINVAL upon error, or 0 upon success. */ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { + struct clk *new_parent = NULL; u16 freqsel; struct dpll_data *dd; + int ret; if (!clk || !rate) return -EINVAL; @@ -601,18 +615,56 @@ static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) if (rate == omap2_get_dpll_rate(clk)) return 0; - if (dd->last_rounded_rate != rate) - omap2_dpll_round_rate(clk, rate); + /* + * Ensure both the bypass and ref clocks are enabled prior to + * doing anything; we need the bypass clock running to reprogram + * the DPLL. + */ + omap2_clk_enable(dd->clk_bypass); + omap2_clk_enable(dd->clk_ref); + + if (dd->clk_bypass->rate == rate && + (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { + pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); - if (dd->last_rounded_rate == 0) - return -EINVAL; + ret = _omap3_noncore_dpll_bypass(clk); + if (!ret) + new_parent = dd->clk_bypass; + } else { + if (dd->last_rounded_rate != rate) + omap2_dpll_round_rate(clk, rate); + + if (dd->last_rounded_rate == 0) + return -EINVAL; + + freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); + if (!freqsel) + WARN_ON(1); - freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); - if (!freqsel) - WARN_ON(1); + pr_debug("clock: %s: set rate: locking rate to %lu.\n", + clk->name, rate); - omap3_noncore_dpll_program(clk, dd->last_rounded_m, dd->last_rounded_n, - freqsel); + ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, + dd->last_rounded_n, freqsel); + if (!ret) + new_parent = dd->clk_ref; + } + if (!ret) { + /* + * Switch the parent clock in the heirarchy, and make sure + * that the new parent's usecount is correct. Note: we + * enable the new parent before disabling the old to avoid + * any unnecessary hardware disable->enable transitions. + */ + if (clk->usecount) { + omap2_clk_enable(new_parent); + omap2_clk_disable(clk->parent); + } + clk_reparent(clk, new_parent); + clk->rate = rate; + } + omap2_clk_disable(dd->clk_ref); + omap2_clk_disable(dd->clk_bypass); return 0; } @@ -804,11 +856,11 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk) dd = pclk->dpll_data; - WARN_ON(!dd->control_reg || !dd->enable_mask); + WARN_ON(!dd->enable_mask); v = __raw_readl(dd->control_reg) & dd->enable_mask; v >>= __ffs(dd->enable_mask); - if (v != DPLL_LOCKED) + if (v != OMAP3XXX_EN_DPLL_LOCKED) rate = clk->parent->rate; else rate = clk->parent->rate * 2; diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 764c7cd9fd84..70ec10deb654 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h @@ -48,6 +48,10 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); * DPLL5 supplies other peripheral clocks (USBHOST, USIM). */ +/* Forward declarations for DPLL bypass clocks */ +static struct clk dpll1_fck; +static struct clk dpll2_fck; + /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ #define DPLL_LOW_POWER_STOP 0x1 #define DPLL_LOW_POWER_BYPASS 0x5 @@ -217,16 +221,6 @@ static struct clk sys_clkout1 = { /* CM CLOCKS */ -static const struct clksel_rate dpll_bypass_rates[] = { - { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - -static const struct clksel_rate dpll_locked_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, - { .div = 0 } -}; - static const struct clksel_rate div16_dpll_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 2, .val = 2, .flags = RATE_IN_343X }, @@ -254,6 +248,8 @@ static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, + .clk_bypass = &dpll1_fck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, @@ -324,6 +320,8 @@ static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, + .clk_bypass = &dpll2_fck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, @@ -384,6 +382,8 @@ static struct dpll_data dpll3_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, @@ -477,37 +477,19 @@ static struct clk dpll3_m2_ck = { .recalc = &omap2_clksel_recalc, }; -static const struct clksel core_ck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk core_ck = { .name = "core_ck", .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, - .clksel = core_ck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel dpll3_m2x2_ck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } + .parent = &dpll3_m2_ck, + .recalc = &followparent_recalc, }; static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, - .clksel = dpll3_m2x2_ck_clksel, + .parent = &dpll3_x2_ck, .clkdm_name = "dpll3_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ @@ -541,22 +523,12 @@ static struct clk dpll3_m3x2_ck = { .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel emu_core_alwon_ck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", .ops = &clkops_null, .parent = &dpll3_m3x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, - .clksel = emu_core_alwon_ck_clksel, .clkdm_name = "dpll3_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; /* DPLL4 */ @@ -566,6 +538,8 @@ static struct dpll_data dpll4_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, @@ -637,12 +611,6 @@ static struct clk dpll4_m2x2_ck = { .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel omap_96m_alwon_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - /* * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: @@ -653,11 +621,7 @@ static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", .ops = &clkops_null, .parent = &dpll4_m2x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = omap_96m_alwon_fck_clksel, - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk cm_96m_fck = { @@ -720,23 +684,6 @@ static struct clk dpll4_m3x2_ck = { .recalc = &omap3_clkoutx2_recalc, }; -static const struct clksel virt_omap_54m_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - -static struct clk virt_omap_54m_fck = { - .name = "virt_omap_54m_fck", - .ops = &clkops_null, - .parent = &dpll4_m3x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = virt_omap_54m_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - static const struct clksel_rate omap_54m_d4m3x2_rates[] = { { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, { .div = 0 } @@ -748,7 +695,7 @@ static const struct clksel_rate omap_54m_alt_rates[] = { }; static const struct clksel omap_54m_clksel[] = { - { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, + { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, { .parent = NULL } }; @@ -891,6 +838,8 @@ static struct dpll_data dpll5_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, + .clk_bypass = &sys_ck, + .clk_ref = &sys_ck, .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, @@ -936,23 +885,6 @@ static struct clk dpll5_m2_ck = { .recalc = &omap2_clksel_recalc, }; -static const struct clksel omap_120m_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - -static struct clk omap_120m_fck = { - .name = "omap_120m_fck", - .ops = &clkops_null, - .parent = &dpll5_m2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), - .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, - .clksel = omap_120m_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - /* CM EXTERNAL CLOCK OUTPUTS */ static const struct clksel_rate clkout2_src_core_rates[] = { @@ -1058,28 +990,12 @@ static struct clk dpll1_fck = { .recalc = &omap2_clksel_recalc, }; -/* - * MPU clksel: - * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck - * derives from the high-frequency bypass clock originating from DPLL3, - * called 'dpll1_fck' - */ -static const struct clksel mpu_clksel[] = { - { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, - { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk mpu_ck = { .name = "mpu_ck", .ops = &clkops_null, .parent = &dpll1_x2m2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), - .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, - .clksel = mpu_clksel, .clkdm_name = "mpu_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ @@ -1129,19 +1045,6 @@ static struct clk dpll2_fck = { .recalc = &omap2_clksel_recalc, }; -/* - * IVA2 clksel: - * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck - * derives from the high-frequency bypass clock originating from DPLL3, - * called 'dpll2_fck' - */ - -static const struct clksel iva2_clksel[] = { - { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, - { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk iva2_ck = { .name = "iva2_ck", .ops = &clkops_omap2_dflt_wait, @@ -1149,12 +1052,8 @@ static struct clk iva2_ck = { .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, - OMAP3430_CM_IDLEST_PLL), - .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, - .clksel = iva2_clksel, .clkdm_name = "iva2_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; /* Common interface clocks */ @@ -1384,7 +1283,7 @@ static struct clk ts_fck = { static struct clk usbtll_fck = { .name = "usbtll_fck", .ops = &clkops_omap2_dflt, - .parent = &omap_120m_fck, + .parent = &dpll5_m2_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .recalc = &followparent_recalc, @@ -2094,24 +1993,14 @@ static struct clk des1_ick = { }; /* DSS */ -static const struct clksel dss1_alwon_fck_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk dss1_alwon_fck = { .name = "dss1_alwon_fck", .ops = &clkops_omap2_dflt, .parent = &dpll4_m4x2_ck, - .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = dss1_alwon_fck_clksel, .clkdm_name = "dss_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk dss_tv_fck = { @@ -2161,24 +2050,14 @@ static struct clk dss_ick = { /* CAM */ -static const struct clksel cam_mclk_clksel[] = { - { .parent = &sys_ck, .rates = dpll_bypass_rates }, - { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, - { .parent = NULL } -}; - static struct clk cam_mclk = { .name = "cam_mclk", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m5x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), - .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, - .clksel = cam_mclk_clksel, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .clkdm_name = "cam_clkdm", - .recalc = &omap2_clksel_recalc, + .recalc = &followparent_recalc, }; static struct clk cam_ick = { @@ -2209,7 +2088,7 @@ static struct clk csi2_96m_fck = { static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", .ops = &clkops_omap2_dflt_wait, - .parent = &omap_120m_fck, + .parent = &dpll5_m2_ck, .init = &omap2_init_clk_clkdm, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, @@ -2260,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = { static const struct clksel usim_clksel[] = { { .parent = &omap_96m_fck, .rates = usim_96m_rates }, - { .parent = &omap_120m_fck, .rates = usim_120m_rates }, + { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, { .parent = &sys_ck, .rates = div2_rates }, { .parent = NULL }, }; diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 3a47aba29031..0afdad5ae9fb 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -29,7 +29,7 @@ #include #include "prm.h" - +#include "clock.h" #include #include "sdrc.h" diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 7b6f6bcbff94..073a2c5569f0 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h @@ -39,6 +39,10 @@ struct dpll_data { void __iomem *mult_div1_reg; u32 mult_mask; u32 div1_mask; + struct clk *clk_bypass; + struct clk *clk_ref; + void __iomem *control_reg; + u32 enable_mask; unsigned int rate_tolerance; unsigned long last_rounded_rate; u16 last_rounded_m; @@ -49,10 +53,8 @@ struct dpll_data { u16 max_multiplier; # if defined(CONFIG_ARCH_OMAP3) u8 modes; - void __iomem *control_reg; void __iomem *autoidle_reg; void __iomem *idlest_reg; - u32 enable_mask; u32 autoidle_mask; u32 freqsel_mask; u32 idlest_mask; @@ -154,9 +156,4 @@ extern const struct clkops clkops_null; #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) -/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ -#define CORE_CLK_SRC_32K 0 -#define CORE_CLK_SRC_DPLL 1 -#define CORE_CLK_SRC_DPLL_X2 2 - #endif -- cgit v1.2.3 From 4da3782151300237db3abe070f716922889252e0 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 24 Feb 2009 12:46:31 +0000 Subject: [ARM] omap: clk_set_parent: deny changing parent if clock is enabled Richard Woodruff writes: | The historic usage of this has been against single use leaf clocks | (1st instance of gptimer). When it was used it did: | clk_get() | clk_set_parent() | clk_enable() | | This usage was ok for that. Use on a disabled clock is needed. | | If there are multiple users on the clock or it is enabled there are | problems. | | The call can still be unfriendly if 2 different drivers are using the | clock with their own clock get/enable. It might be the function should | return an error if usecount != 0 to stop surprises. It is all around | better if the parenting is done when the clock is off. This is a good reason to ensure that the clock is not enabled when clk_set_parent() is called. Acked-by: Richard Woodruff Signed-off-by: Russell King --- arch/arm/mach-omap2/clock.c | 6 ------ arch/arm/plat-omap/clock.c | 17 ++++++++++------- 2 files changed, 10 insertions(+), 13 deletions(-) (limited to 'arch/arm/mach-omap2/clock.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 40cb65ba1fac..f49bce997a0b 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -807,9 +807,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) if (!parent_div) return -EINVAL; - if (clk->usecount > 0) - _omap2_clk_disable(clk); - /* Set new source value (previous dividers if any in effect) */ v = __raw_readl(clk->clksel_reg); v &= ~clk->clksel_mask; @@ -819,9 +816,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) _omap2xxx_clk_commit(clk); - if (clk->usecount > 0) - _omap2_clk_enable(clk); - clk_reparent(clk, new_parent); /* CLKSEL clocks follow their parents' rates, divided by a divisor */ diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index 08baa18497b2..2e0614552ac8 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -144,13 +144,16 @@ int clk_set_parent(struct clk *clk, struct clk *parent) return ret; spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_set_parent) - ret = arch_clock->clk_set_parent(clk, parent); - if (ret == 0) { - if (clk->recalc) - clk->rate = clk->recalc(clk); - propagate_rate(clk); - } + if (clk->usecount == 0) { + if (arch_clock->clk_set_parent) + ret = arch_clock->clk_set_parent(clk, parent); + if (ret == 0) { + if (clk->recalc) + clk->rate = clk->recalc(clk); + propagate_rate(clk); + } + } else + ret = -EBUSY; spin_unlock_irqrestore(&clockfw_lock, flags); return ret; -- cgit v1.2.3