From 49cbe78637eb0503f45fc9b556ec08918a616534 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 20 Jan 2009 14:15:18 +0800 Subject: [ARM] pxa: add base support for Marvell's PXA168 processor line MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit """The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas Signed-off-by: Eric Miao --- arch/arm/mach-mmp/include/mach/addr-map.h | 34 ++++++++++++++++ arch/arm/mach-mmp/include/mach/clkdev.h | 7 ++++ arch/arm/mach-mmp/include/mach/cputype.h | 21 ++++++++++ arch/arm/mach-mmp/include/mach/debug-macro.S | 23 +++++++++++ arch/arm/mach-mmp/include/mach/devices.h | 27 +++++++++++++ arch/arm/mach-mmp/include/mach/dma.h | 13 +++++++ arch/arm/mach-mmp/include/mach/entry-macro.S | 25 ++++++++++++ arch/arm/mach-mmp/include/mach/hardware.h | 4 ++ arch/arm/mach-mmp/include/mach/io.h | 21 ++++++++++ arch/arm/mach-mmp/include/mach/irqs.h | 58 ++++++++++++++++++++++++++++ arch/arm/mach-mmp/include/mach/memory.h | 14 +++++++ arch/arm/mach-mmp/include/mach/pxa168.h | 23 +++++++++++ arch/arm/mach-mmp/include/mach/regs-apbc.h | 53 +++++++++++++++++++++++++ arch/arm/mach-mmp/include/mach/regs-apmu.h | 36 +++++++++++++++++ arch/arm/mach-mmp/include/mach/regs-icu.h | 31 +++++++++++++++ arch/arm/mach-mmp/include/mach/regs-timers.h | 44 +++++++++++++++++++++ arch/arm/mach-mmp/include/mach/system.h | 21 ++++++++++ arch/arm/mach-mmp/include/mach/timex.h | 9 +++++ arch/arm/mach-mmp/include/mach/uncompress.h | 41 ++++++++++++++++++++ arch/arm/mach-mmp/include/mach/vmalloc.h | 5 +++ 20 files changed, 510 insertions(+) create mode 100644 arch/arm/mach-mmp/include/mach/addr-map.h create mode 100644 arch/arm/mach-mmp/include/mach/clkdev.h create mode 100644 arch/arm/mach-mmp/include/mach/cputype.h create mode 100644 arch/arm/mach-mmp/include/mach/debug-macro.S create mode 100644 arch/arm/mach-mmp/include/mach/devices.h create mode 100644 arch/arm/mach-mmp/include/mach/dma.h create mode 100644 arch/arm/mach-mmp/include/mach/entry-macro.S create mode 100644 arch/arm/mach-mmp/include/mach/hardware.h create mode 100644 arch/arm/mach-mmp/include/mach/io.h create mode 100644 arch/arm/mach-mmp/include/mach/irqs.h create mode 100644 arch/arm/mach-mmp/include/mach/memory.h create mode 100644 arch/arm/mach-mmp/include/mach/pxa168.h create mode 100644 arch/arm/mach-mmp/include/mach/regs-apbc.h create mode 100644 arch/arm/mach-mmp/include/mach/regs-apmu.h create mode 100644 arch/arm/mach-mmp/include/mach/regs-icu.h create mode 100644 arch/arm/mach-mmp/include/mach/regs-timers.h create mode 100644 arch/arm/mach-mmp/include/mach/system.h create mode 100644 arch/arm/mach-mmp/include/mach/timex.h create mode 100644 arch/arm/mach-mmp/include/mach/uncompress.h create mode 100644 arch/arm/mach-mmp/include/mach/vmalloc.h (limited to 'arch/arm/mach-mmp/include') diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h new file mode 100644 index 000000000000..3254089a644d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/addr-map.h @@ -0,0 +1,34 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/addr-map.h + * + * Common address map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ADDR_MAP_H +#define __ASM_MACH_ADDR_MAP_H + +/* APB - Application Subsystem Peripheral Bus + * + * NOTE: the DMA controller registers are actually on the AXI fabric #1 + * slave port to AHB/APB bridge, due to its close relationship to those + * peripherals on APB, let's count it into the ABP mapping area. + */ +#define APB_PHYS_BASE 0xd4000000 +#define APB_VIRT_BASE 0xfe000000 +#define APB_PHYS_SIZE 0x00200000 + +#define AXI_PHYS_BASE 0xd4200000 +#define AXI_VIRT_BASE 0xfe200000 +#define AXI_PHYS_SIZE 0x00200000 + +/* Static Memory Controller - Chip Select 0 and 1 */ +#define SMC_CS0_PHYS_BASE 0x80000000 +#define SMC_CS0_PHYS_SIZE 0x10000000 +#define SMC_CS1_PHYS_BASE 0x90000000 +#define SMC_CS1_PHYS_SIZE 0x10000000 + +#endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h new file mode 100644 index 000000000000..2fb354e54e0d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/clkdev.h @@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h new file mode 100644 index 000000000000..4ceed7a50755 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/cputype.h @@ -0,0 +1,21 @@ +#ifndef __ASM_MACH_CPUTYPE_H +#define __ASM_MACH_CPUTYPE_H + +#include + +/* + * CPU Stepping OLD_ID CPU_ID CHIP_ID + * + * PXA168 A0 0x41159263 0x56158400 0x00A0A333 + */ + +#ifdef CONFIG_CPU_PXA168 +# define __cpu_is_pxa168(id) \ + ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; }) +#else +# define __cpu_is_pxa168(id) (0) +#endif + +#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) + +#endif /* __ASM_MACH_CPUTYPE_H */ diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S new file mode 100644 index 000000000000..a850f87de51d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S @@ -0,0 +1,23 @@ +/* arch/arm/mach-mmp/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copied from arch/arm/mach-pxa/include/mach/debug.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =APB_PHYS_BASE @ physical + ldrne \rx, =APB_VIRT_BASE @ virtual + orr \rx, \rx, #0x00017000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h new file mode 100644 index 000000000000..bc03388d5fde --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -0,0 +1,27 @@ +#include + +#define MAX_RESOURCE_DMA 2 + +/* structure for describing the on-chip devices */ +struct pxa_device_desc { + const char *dev_name; + const char *drv_name; + int id; + int irq; + unsigned long start; + unsigned long size; + int dma[MAX_RESOURCE_DMA]; +}; + +#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ +struct pxa_device_desc pxa168_device_##_name __initdata = { \ + .dev_name = "pxa168-" #_name, \ + .drv_name = _drv, \ + .id = _id, \ + .irq = IRQ_PXA168_##_irq, \ + .start = _start, \ + .size = _size, \ + .dma = { _dma }, \ +}; + +extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); diff --git a/arch/arm/mach-mmp/include/mach/dma.h b/arch/arm/mach-mmp/include/mach/dma.h new file mode 100644 index 000000000000..1d6914544da4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/dma.h @@ -0,0 +1,13 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/dma.h + */ + +#ifndef __ASM_MACH_DMA_H +#define __ASM_MACH_DMA_H + +#include + +#define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000) + +#include +#endif /* __ASM_MACH_DMA_H */ diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S new file mode 100644 index 000000000000..6d3cd35478b5 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S @@ -0,0 +1,25 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/entry-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =ICU_AP_IRQ_SEL_INT_NUM + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \tmp, [\base, #0] + and \irqnr, \tmp, #0x3f + tst \tmp, #(1 << 6) + .endm diff --git a/arch/arm/mach-mmp/include/mach/hardware.h b/arch/arm/mach-mmp/include/mach/hardware.h new file mode 100644 index 000000000000..99264a5ce5e4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/hardware.h @@ -0,0 +1,4 @@ +#ifndef __ASM_MACH_HARDWARE_H +#define __ASM_MACH_HARDWARE_H + +#endif /* __ASM_MACH_HARDWARE_H */ diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h new file mode 100644 index 000000000000..e7adf3d012c1 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/io.h @@ -0,0 +1,21 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/io.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_IO_H +#define __ASM_MACH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif /* __ASM_MACH_IO_H */ diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h new file mode 100644 index 000000000000..91ecb3fbca06 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -0,0 +1,58 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +/* + * Interrupt numbers for PXA168 + */ +#define IRQ_PXA168_NONE (-1) +#define IRQ_PXA168_SSP3 0 +#define IRQ_PXA168_SSP2 1 +#define IRQ_PXA168_SSP1 2 +#define IRQ_PXA168_SSP0 3 +#define IRQ_PXA168_PMIC_INT 4 +#define IRQ_PXA168_RTC_INT 5 +#define IRQ_PXA168_RTC_ALARM 6 +#define IRQ_PXA168_TWSI0 7 +#define IRQ_PXA168_GPU 8 +#define IRQ_PXA168_KEYPAD 9 +#define IRQ_PXA168_ONEWIRE 12 +#define IRQ_PXA168_TIMER1 13 +#define IRQ_PXA168_TIMER2 14 +#define IRQ_PXA168_TIMER3 15 +#define IRQ_PXA168_CMU 16 +#define IRQ_PXA168_SSP4 17 +#define IRQ_PXA168_MSP_WAKEUP 19 +#define IRQ_PXA168_CF_WAKEUP 20 +#define IRQ_PXA168_XD_WAKEUP 21 +#define IRQ_PXA168_MFU 22 +#define IRQ_PXA168_MSP 23 +#define IRQ_PXA168_CF 24 +#define IRQ_PXA168_XD 25 +#define IRQ_PXA168_DDR_INT 26 +#define IRQ_PXA168_UART1 27 +#define IRQ_PXA168_UART2 28 +#define IRQ_PXA168_WDT 35 +#define IRQ_PXA168_FRQ_CHANGE 38 +#define IRQ_PXA168_SDH1 39 +#define IRQ_PXA168_SDH2 40 +#define IRQ_PXA168_LCD 41 +#define IRQ_PXA168_CI 42 +#define IRQ_PXA168_USB1 44 +#define IRQ_PXA168_NAND 45 +#define IRQ_PXA168_HIFI_DMA 46 +#define IRQ_PXA168_DMA_INT0 47 +#define IRQ_PXA168_DMA_INT1 48 +#define IRQ_PXA168_GPIOX 49 +#define IRQ_PXA168_USB2 51 +#define IRQ_PXA168_AC97 57 +#define IRQ_PXA168_TWSI1 58 +#define IRQ_PXA168_PMU 60 +#define IRQ_PXA168_SM_INT 63 + +#define IRQ_GPIO_START 64 +#define IRQ_GPIO_NUM 128 +#define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) + +#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h new file mode 100644 index 000000000000..bdb21d70714c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/memory.h @@ -0,0 +1,14 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/memory.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_MEMORY_H +#define __ASM_MACH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h new file mode 100644 index 000000000000..ef0a8a2076e9 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_PXA168_H +#define __ASM_MACH_PXA168_H + +#include + +extern struct pxa_device_desc pxa168_device_uart1; +extern struct pxa_device_desc pxa168_device_uart2; + +static inline int pxa168_add_uart(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &pxa168_device_uart1; break; + case 2: d = &pxa168_device_uart2; break; + } + + if (d == NULL) + return -EINVAL; + + return pxa_register_device(d, NULL, 0); +} +#endif /* __ASM_MACH_PXA168_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h new file mode 100644 index 000000000000..e0ffae594873 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -0,0 +1,53 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h + * + * Application Peripheral Bus Clock Unit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_REGS_APBC_H +#define __ASM_MACH_REGS_APBC_H + +#include + +#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) +#define APBC_REG(x) (APBC_VIRT_BASE + (x)) + +/* + * APB clock register offsets for PXA168 + */ +#define APBC_PXA168_UART1 APBC_REG(0x000) +#define APBC_PXA168_UART2 APBC_REG(0x004) +#define APBC_PXA168_GPIO APBC_REG(0x008) +#define APBC_PXA168_PWM0 APBC_REG(0x00c) +#define APBC_PXA168_PWM1 APBC_REG(0x010) +#define APBC_PXA168_SSP1 APBC_REG(0x01c) +#define APBC_PXA168_SSP2 APBC_REG(0x020) +#define APBC_PXA168_RTC APBC_REG(0x028) +#define APBC_PXA168_TWSI0 APBC_REG(0x02c) +#define APBC_PXA168_KPC APBC_REG(0x030) +#define APBC_PXA168_TIMERS APBC_REG(0x034) +#define APBC_PXA168_AIB APBC_REG(0x03c) +#define APBC_PXA168_SW_JTAG APBC_REG(0x040) +#define APBC_PXA168_ONEWIRE APBC_REG(0x048) +#define APBC_PXA168_SSP3 APBC_REG(0x04c) +#define APBC_PXA168_ASFAR APBC_REG(0x050) +#define APBC_PXA168_ASSAR APBC_REG(0x054) +#define APBC_PXA168_SSP4 APBC_REG(0x058) +#define APBC_PXA168_SSP5 APBC_REG(0x05c) +#define APBC_PXA168_TWSI1 APBC_REG(0x06c) +#define APBC_PXA168_UART3 APBC_REG(0x070) +#define APBC_PXA168_AC97 APBC_REG(0x084) + +/* Common APB clock register bit definitions */ +#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ +#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ +#define APBC_RST (1 << 2) /* Reset Generation */ + +/* Functional Clock Selection Mask */ +#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) + +#endif /* __ASM_MACH_REGS_APBC_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h new file mode 100644 index 000000000000..919030514120 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -0,0 +1,36 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/regs-apmu.h + * + * Application Subsystem Power Management Unit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_REGS_APMU_H +#define __ASM_MACH_REGS_APMU_H + +#include + +#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) +#define APMU_REG(x) (APMU_VIRT_BASE + (x)) + +/* Clock Reset Control */ +#define APMU_IRE APMU_REG(0x048) +#define APMU_LCD APMU_REG(0x04c) +#define APMU_CCIC APMU_REG(0x050) +#define APMU_SDH0 APMU_REG(0x054) +#define APMU_SDH1 APMU_REG(0x058) +#define APMU_USB APMU_REG(0x05c) +#define APMU_NAND APMU_REG(0x060) +#define APMU_DMA APMU_REG(0x064) +#define APMU_GEU APMU_REG(0x068) +#define APMU_BUS APMU_REG(0x06c) + +#define APMU_FNCLK_EN (1 << 4) +#define APMU_AXICLK_EN (1 << 3) +#define APMU_FNRST_DIS (1 << 1) +#define APMU_AXIRST_DIS (1 << 0) + +#endif /* __ASM_MACH_REGS_APMU_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h new file mode 100644 index 000000000000..e5f08723e0cc --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-icu.h @@ -0,0 +1,31 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/regs-icu.h + * + * Interrupt Control Unit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_ICU_H +#define __ASM_MACH_ICU_H + +#include + +#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000) +#define ICU_REG(x) (ICU_VIRT_BASE + (x)) + +#define ICU_INT_CONF(n) ICU_REG((n) << 2) +#define ICU_INT_CONF_AP_INT (1 << 6) +#define ICU_INT_CONF_CP_INT (1 << 5) +#define ICU_INT_CONF_IRQ (1 << 4) +#define ICU_INT_CONF_MASK (0xf) + +#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ +#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ +#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */ +#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ +#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ + +#endif /* __ASM_MACH_ICU_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h new file mode 100644 index 000000000000..45589fec9fc7 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-timers.h @@ -0,0 +1,44 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/regs-timers.h + * + * Timers Module + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_REGS_TIMERS_H +#define __ASM_MACH_REGS_TIMERS_H + +#include + +#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000) +#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000) + +#define TMR_CCR (0x0000) +#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) +#define TMR_CR(n) (0x0028 + ((n) << 2)) +#define TMR_SR(n) (0x0034 + ((n) << 2)) +#define TMR_IER(n) (0x0040 + ((n) << 2)) +#define TMR_PLVR(n) (0x004c + ((n) << 2)) +#define TMR_PLCR(n) (0x0058 + ((n) << 2)) +#define TMR_WMER (0x0064) +#define TMR_WMR (0x0068) +#define TMR_WVR (0x006c) +#define TMR_WSR (0x0070) +#define TMR_ICR(n) (0x0074 + ((n) << 2)) +#define TMR_WICR (0x0080) +#define TMR_CER (0x0084) +#define TMR_CMR (0x0088) +#define TMR_ILR(n) (0x008c + ((n) << 2)) +#define TMR_WCR (0x0098) +#define TMR_WFAR (0x009c) +#define TMR_WSAR (0x00A0) +#define TMR_CVWR(n) (0x00A4 + ((n) << 2)) + +#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0) +#define TMR_CCR_CS_1(x) (((x) & 0x7) << 2) +#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5) + +#endif /* __ASM_MACH_REGS_TIMERS_H */ diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h new file mode 100644 index 000000000000..001edfefec19 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/system.h @@ -0,0 +1,21 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/system.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_MACH_SYSTEM_H +#define __ASM_MACH_SYSTEM_H + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + cpu_reset(0); +} +#endif /* __ASM_MACH_SYSTEM_H */ diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h new file mode 100644 index 000000000000..6cebbd0ca8f4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/timex.h @@ -0,0 +1,9 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/timex.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define CLOCK_TICK_RATE 3250000 diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h new file mode 100644 index 000000000000..c93d5fa5865c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/uncompress.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-mmp/include/mach/uncompress.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#define UART1_BASE (APB_PHYS_BASE + 0x36000) +#define UART2_BASE (APB_PHYS_BASE + 0x17000) +#define UART3_BASE (APB_PHYS_BASE + 0x18000) + +static inline void putc(char c) +{ + volatile unsigned long *UART = (unsigned long *)UART2_BASE; + + /* UART enabled? */ + if (!(UART[UART_IER] & UART_IER_UUE)) + return; + + while (!(UART[UART_LSR] & UART_LSR_THRE)) + barrier(); + + UART[UART_TX] = c; +} + +/* + * This does not append a newline + */ +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h new file mode 100644 index 000000000000..b60ccaf9fee7 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/vmalloc.h @@ -0,0 +1,5 @@ +/* + * linux/arch/arm/mach-mmp/include/mach/vmalloc.h + */ + +#define VMALLOC_END 0xfe000000 -- cgit v1.2.3 From e2bb6650ef94c64723e2dd35ab92410b9477bc64 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 20 Jan 2009 14:38:24 +0800 Subject: [ARM] pxa: add GPIO support for pxa168 Signed-off-by: Eric Miao --- arch/arm/Kconfig | 2 ++ arch/arm/mach-mmp/include/mach/gpio.h | 36 +++++++++++++++++++++++++++++++++++ arch/arm/mach-mmp/pxa168.c | 19 ++++++++++++++++++ 3 files changed, 57 insertions(+) create mode 100644 arch/arm/mach-mmp/include/mach/gpio.h (limited to 'arch/arm/mach-mmp/include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5385d8743c6a..daf35d778208 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -490,6 +490,8 @@ config ARCH_PXA config ARCH_MMP bool "Marvell PXA168" depends on MMU + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB select HAVE_CLK select COMMON_CLKDEV select GENERIC_TIME diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h new file mode 100644 index 000000000000..ab26d13295c4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/gpio.h @@ -0,0 +1,36 @@ +#ifndef __ASM_MACH_GPIO_H +#define __ASM_MACH_GPIO_H + +#include +#include +#include + +#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) + +#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) +#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) + +#define NR_BUILTIN_GPIO (128) + +#define gpio_to_bank(gpio) ((gpio) >> 5) +#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) +#define irq_to_gpio(irq) ((irq) - IRQ_GPIO_START) + + +#define __gpio_is_inverted(gpio) (0) +#define __gpio_is_occupied(gpio) (0) + +/* NOTE: these macros are defined here to make optimization of + * gpio_{get,set}_value() to work when 'gpio' is a constant. + * Usage of these macros otherwise is no longer recommended, + * use generic GPIO API whenever possible. + */ +#define GPIO_bit(gpio) (1 << ((gpio) & 0x1f)) + +#define GPLR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00) +#define GPDR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c) +#define GPSR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18) +#define GPCR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24) + +#include +#endif /* __ASM_MACH_GPIO_H */ diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 1935c7545117..1774682e988e 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -19,15 +20,33 @@ #include #include #include +#include #include #include #include "common.h" #include "clock.h" +#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) + +static void __init pxa168_init_gpio(void) +{ + int i; + + /* enable GPIO clock */ + __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); + + /* unmask GPIO edge detection for all 4 banks - APMASKx */ + for (i = 0; i < 4; i++) + __raw_writel(0xffffffff, APMASK(i)); + + pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); +} + void __init pxa168_init_irq(void) { icu_init_irq(); + pxa168_init_gpio(); } /* APB peripheral clocks */ -- cgit v1.2.3 From a7a89d9621ba877ae45784cf7d000182075df9c1 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Tue, 20 Jan 2009 17:20:56 +0800 Subject: [ARM] pxa: add MFP support for pxa168 Signed-off-by: Eric Miao --- arch/arm/mach-mmp/include/mach/mfp-pxa168.h | 258 ++++++++++++++++++++++++++++ arch/arm/mach-mmp/include/mach/mfp.h | 37 ++++ arch/arm/mach-mmp/pxa168.c | 15 ++ 3 files changed, 310 insertions(+) create mode 100644 arch/arm/mach-mmp/include/mach/mfp-pxa168.h create mode 100644 arch/arm/mach-mmp/include/mach/mfp.h (limited to 'arch/arm/mach-mmp/include') diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h new file mode 100644 index 000000000000..d0bdb6e3682b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -0,0 +1,258 @@ +#ifndef __ASM_MACH_MFP_PXA168_H +#define __ASM_MACH_MFP_PXA168_H + +#include + +/* GPIO */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF5) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF5) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF5) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF5) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF5) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF5) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF5) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF5) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF5) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF5) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF5) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF5) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF5) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF5) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF5) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF5) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF5) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF5) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF5) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF5) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF5) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF5) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF5) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF5) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF5) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF5) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF5) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF5) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF5) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF5) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) +#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) + +/* DFI */ +#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0) +#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0) +#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0) +#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0) +#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0) +#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0) +#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0) +#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0) +#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0) +#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0) +#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0) +#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0) +#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0) +#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0) +#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0) +#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0) + +#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0) +#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0) +#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0) +#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0) + +/* NAND */ +#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1) +#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0) +#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0) +#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0) +#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0) +#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1) +#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1) + +/* Static Memory Controller */ +#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3) +#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2) +#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2) +#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3) +#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0) +#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2) +#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0) +#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0) +#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0) +#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0) +#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0) +#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2) +#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2) +#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2) + +/* Compact Flash */ +#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3) +#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3) +#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3) +#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3) +#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3) +#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3) +#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3) +#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3) +#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3) +#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3) + +/* UART1 */ +#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST) +#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST) +#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST) +#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST) +#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1) +#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2) +#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1) +#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2) +#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1) +#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2) +#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1) +#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2) + +/* MMC1 */ +#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1) +#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1) +#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1) +#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1) +#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1) +#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1) +#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1) +#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1) +#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1) +#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1) +#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1) +#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1) + +/* LCD */ +#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1) +#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1) +#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1) +#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1) +#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1) +#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1) +#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1) +#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1) +#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1) +#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1) +#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1) +#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1) +#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1) +#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1) +#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1) +#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1) +#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1) +#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1) +#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1) +#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1) +#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1) +#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1) +#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1) +#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1) +#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1) +#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1) +#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1) +#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1) +#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1) +#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1) + +/* I2S */ +#define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6) +#define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1) +#define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1) +#define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2) +#define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2) + +#endif /* __ASM_MACH_MFP_PXA168_H */ diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h new file mode 100644 index 000000000000..277ea4cd0f9f --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp.h @@ -0,0 +1,37 @@ +#ifndef __ASM_MACH_MFP_H +#define __ASM_MACH_MFP_H + +#include + +/* + * NOTE: the MFPR register bit definitions on PXA168 processor lines are a + * bit different from those on PXA3xx. Bit [7:10] are now reserved, which + * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits. + * + * To cope with this difference and re-use the pxa3xx mfp code as much as + * possible, we make the following compromise: + * + * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) + * 2. DRIVE strength definitions redefined to include the reserved bit10 + * 3. Override MFP_CFG() and MFP_CFG_DRV() + * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() + */ + +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + +#undef MFP_CFG +#undef MFP_CFG_DRV +#undef MFP_CFG_LPM +#undef MFP_CFG_X +#undef MFP_CFG_DEFAULT + +#define MFP_CFG(pin, af) \ + (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) + +#define MFP_CFG_DRV(pin, af, drv) \ + (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) + +#endif /* __ASM_MACH_MFP_H */ diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 1774682e988e..ae924468658c 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -23,10 +23,23 @@ #include #include #include +#include #include "common.h" #include "clock.h" +#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) + +static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = +{ + MFP_ADDR_X(GPIO0, GPIO36, 0x04c), + MFP_ADDR_X(GPIO37, GPIO55, 0x000), + MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), + MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), + + MFP_ADDR_END, +}; + #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) static void __init pxa168_init_gpio(void) @@ -62,6 +75,8 @@ static struct clk_lookup pxa168_clkregs[] = { static int __init pxa168_init(void) { if (cpu_is_pxa168()) { + mfp_init_base(MFPR_VIRT_BASE); + mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); } -- cgit v1.2.3 From 14c6b5e7add9ec393ad61bceb6106b47c7f14bd3 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 20 Mar 2009 12:50:22 +0800 Subject: [ARM] pxa: add base support for Marvell PXA910 Signed-off-by: Bin Yang Signed-off-by: Eric Miao --- arch/arm/Kconfig | 4 +- arch/arm/mach-mmp/Kconfig | 8 +- arch/arm/mach-mmp/Makefile | 1 + arch/arm/mach-mmp/common.h | 2 + arch/arm/mach-mmp/include/mach/cputype.h | 9 ++ arch/arm/mach-mmp/include/mach/devices.h | 10 ++ arch/arm/mach-mmp/include/mach/irqs.h | 61 +++++++++++ arch/arm/mach-mmp/include/mach/mfp-pxa910.h | 157 +++++++++++++++++++++++++++ arch/arm/mach-mmp/include/mach/pxa910.h | 23 ++++ arch/arm/mach-mmp/include/mach/regs-apbc.h | 25 +++++ arch/arm/mach-mmp/pxa910.c | 158 ++++++++++++++++++++++++++++ arch/arm/plat-pxa/include/plat/mfp.h | 30 ++++++ 12 files changed, 485 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-mmp/include/mach/mfp-pxa910.h create mode 100644 arch/arm/mach-mmp/include/mach/pxa910.h create mode 100644 arch/arm/mach-mmp/pxa910.c (limited to 'arch/arm/mach-mmp/include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index daf35d778208..cb4486ad0f72 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -488,7 +488,7 @@ config ARCH_PXA Support for Intel/Marvell's PXA2xx/PXA3xx processor line. config ARCH_MMP - bool "Marvell PXA168" + bool "Marvell PXA168/910" depends on MMU select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB @@ -499,7 +499,7 @@ config ARCH_MMP select TICK_ONESHOT select PLAT_PXA help - Support for Marvell's PXA168 processor line. + Support for Marvell's PXA168/910 processor line. config ARCH_RPC bool "RiscPC" diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index b52326763556..ba2e377484f7 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -1,6 +1,6 @@ if ARCH_MMP -menu "Marvell PXA168 Implmentations" +menu "Marvell PXA168/910 Implmentations" config MACH_ASPENITE bool "Marvell's PXA168 Aspenite Development Board" @@ -24,4 +24,10 @@ config CPU_PXA168 help Select code specific to PXA168 +config CPU_PXA910 + bool + select CPU_MOHAWK + help + Select code specific to PXA910 + endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 0ac7644ec99d..93d2bc7459d6 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -6,6 +6,7 @@ obj-y += common.o clock.o devices.o irq.o time.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o +obj-$(CONFIG_CPU_PXA910) += pxa910.o # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index bf7a6a492de6..c33fbbc49417 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -5,7 +5,9 @@ struct sys_timer; extern void timer_init(int irq); extern struct sys_timer pxa168_timer; +extern struct sys_timer pxa910_timer; extern void __init pxa168_init_irq(void); +extern void __init pxa910_init_irq(void); extern void __init icu_init_irq(void); extern void __init pxa_map_io(void); diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h index 4ceed7a50755..25e797b09083 100644 --- a/arch/arm/mach-mmp/include/mach/cputype.h +++ b/arch/arm/mach-mmp/include/mach/cputype.h @@ -7,6 +7,7 @@ * CPU Stepping OLD_ID CPU_ID CHIP_ID * * PXA168 A0 0x41159263 0x56158400 0x00A0A333 + * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 */ #ifdef CONFIG_CPU_PXA168 @@ -16,6 +17,14 @@ # define __cpu_is_pxa168(id) (0) #endif +#ifdef CONFIG_CPU_PXA910 +# define __cpu_is_pxa910(id) \ + ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; }) +#else +# define __cpu_is_pxa910(id) (0) +#endif + #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) +#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) #endif /* __ASM_MACH_CPUTYPE_H */ diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index bc03388d5fde..24585397217e 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -24,4 +24,14 @@ struct pxa_device_desc pxa168_device_##_name __initdata = { \ .dma = { _dma }, \ }; +#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ +struct pxa_device_desc pxa910_device_##_name __initdata = { \ + .dev_name = "pxa910-" #_name, \ + .drv_name = _drv, \ + .id = _id, \ + .irq = IRQ_PXA910_##_irq, \ + .start = _start, \ + .size = _size, \ + .dma = { _dma }, \ +}; extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index 91ecb3fbca06..e83e45ebf7a4 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -49,6 +49,67 @@ #define IRQ_PXA168_PMU 60 #define IRQ_PXA168_SM_INT 63 +/* + * Interrupt numbers for PXA910 + */ +#define IRQ_PXA910_AIRQ 0 +#define IRQ_PXA910_SSP3 1 +#define IRQ_PXA910_SSP2 2 +#define IRQ_PXA910_SSP1 3 +#define IRQ_PXA910_PMIC_INT 4 +#define IRQ_PXA910_RTC_INT 5 +#define IRQ_PXA910_RTC_ALARM 6 +#define IRQ_PXA910_TWSI0 7 +#define IRQ_PXA910_GPU 8 +#define IRQ_PXA910_KEYPAD 9 +#define IRQ_PXA910_ROTARY 10 +#define IRQ_PXA910_TRACKBALL 11 +#define IRQ_PXA910_ONEWIRE 12 +#define IRQ_PXA910_AP1_TIMER1 13 +#define IRQ_PXA910_AP1_TIMER2 14 +#define IRQ_PXA910_AP1_TIMER3 15 +#define IRQ_PXA910_IPC_AP0 16 +#define IRQ_PXA910_IPC_AP1 17 +#define IRQ_PXA910_IPC_AP2 18 +#define IRQ_PXA910_IPC_AP3 19 +#define IRQ_PXA910_IPC_AP4 20 +#define IRQ_PXA910_IPC_CP0 21 +#define IRQ_PXA910_IPC_CP1 22 +#define IRQ_PXA910_IPC_CP2 23 +#define IRQ_PXA910_IPC_CP3 24 +#define IRQ_PXA910_IPC_CP4 25 +#define IRQ_PXA910_L2_DDR 26 +#define IRQ_PXA910_UART2 27 +#define IRQ_PXA910_UART3 28 +#define IRQ_PXA910_AP2_TIMER1 29 +#define IRQ_PXA910_AP2_TIMER2 30 +#define IRQ_PXA910_CP2_TIMER1 31 +#define IRQ_PXA910_CP2_TIMER2 32 +#define IRQ_PXA910_CP2_TIMER3 33 +#define IRQ_PXA910_GSSP 34 +#define IRQ_PXA910_CP2_WDT 35 +#define IRQ_PXA910_MAIN_PMU 36 +#define IRQ_PXA910_CP_FREQ_CHG 37 +#define IRQ_PXA910_AP_FREQ_CHG 38 +#define IRQ_PXA910_MMC 39 +#define IRQ_PXA910_AEU 40 +#define IRQ_PXA910_LCD 41 +#define IRQ_PXA910_CCIC 42 +#define IRQ_PXA910_IRE 43 +#define IRQ_PXA910_USB1 44 +#define IRQ_PXA910_NAND 45 +#define IRQ_PXA910_HIFI_DMA 46 +#define IRQ_PXA910_DMA_INT0 47 +#define IRQ_PXA910_DMA_INT1 48 +#define IRQ_PXA910_AP_GPIO 49 +#define IRQ_PXA910_AP2_TIMER3 50 +#define IRQ_PXA910_USB2 51 +#define IRQ_PXA910_TWSI1 54 +#define IRQ_PXA910_CP_GPIO 55 +#define IRQ_PXA910_UART1 59 /* Slow UART */ +#define IRQ_PXA910_AP_PMU 60 +#define IRQ_PXA910_SM_INT 63 /* from PinMux */ + #define IRQ_GPIO_START 64 #define IRQ_GPIO_NUM 128 #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h new file mode 100644 index 000000000000..48a1cbc7c56b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h @@ -0,0 +1,157 @@ +#ifndef __ASM_MACH_MFP_PXA910_H +#define __ASM_MACH_MFP_PXA910_H + +#include + +/* UART2 */ +#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) +#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) + +/* UART3 */ +#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4) +#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4) + +/*IRDA*/ +#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0) + +/* SMC */ +#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) +#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) +#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) +#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) +#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) +#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) + +/* I2C */ +#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2) +#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2) + +/* SSP1 (I2S) */ +#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM) +#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM) +#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM) +#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM) +#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM) +#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM) +#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM) + +/* DFI */ +#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0) +#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0) +#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0) +#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0) +#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0) +#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0) +#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0) +#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0) +#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0) +#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0) +#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0) +#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0) +#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0) +#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0) +#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0) +#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0) +#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0) +#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1) +#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0) +#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1) +#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1) +#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0) + +/*keypad*/ +#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) +#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) +#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) +#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) +#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) +#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) +#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) +#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) +#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) +#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) +#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) +#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) +#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) +#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) +#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) +#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) +#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) +#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) +#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) +#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) + +/* LCD */ +#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1) +#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1) +#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1) +#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1) +#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1) +#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1) +#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1) +#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1) +#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1) +#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1) +#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1) +#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1) +#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1) +#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1) +#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1) +#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1) +#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1) +#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1) +#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1) +#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1) +#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1) +#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1) +#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1) +#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1) +#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1) +#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1) +#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1) +#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1) + +#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3) +#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3) +#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3) +#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3) + +#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0) + +/*smart panel*/ +#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0) +#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0) +#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0) + +/*1wire*/ +#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3) + +/*CCIC*/ +#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM) +#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM) +#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM) +#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM) +#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM) +#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM) +#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM) +#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM) +#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM) +#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM) +#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM) +#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM) + +/* MMC1 */ +#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM) +#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM) +#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM) +#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM) +#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM) +#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM) +#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM) +#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM) +#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM) +#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM) +#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM) +#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM) + +#endif /* __ASM_MACH MFP_PXA910_H */ diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h new file mode 100644 index 000000000000..b7aeaf574c36 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -0,0 +1,23 @@ +#ifndef __ASM_MACH_PXA910_H +#define __ASM_MACH_PXA910_H + +#include + +extern struct pxa_device_desc pxa910_device_uart1; +extern struct pxa_device_desc pxa910_device_uart2; + +static inline int pxa910_add_uart(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &pxa910_device_uart1; break; + case 2: d = &pxa910_device_uart2; break; + } + + if (d == NULL) + return -EINVAL; + + return pxa_register_device(d, NULL, 0); +} +#endif /* __ASM_MACH_PXA910_H */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index e0ffae594873..c6b8c9dc2026 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -42,6 +42,31 @@ #define APBC_PXA168_UART3 APBC_REG(0x070) #define APBC_PXA168_AC97 APBC_REG(0x084) +/* + * APB Clock register offsets for PXA910 + */ +#define APBC_PXA910_UART0 APBC_REG(0x000) +#define APBC_PXA910_UART1 APBC_REG(0x004) +#define APBC_PXA910_GPIO APBC_REG(0x008) +#define APBC_PXA910_PWM0 APBC_REG(0x00c) +#define APBC_PXA910_PWM1 APBC_REG(0x010) +#define APBC_PXA910_PWM2 APBC_REG(0x014) +#define APBC_PXA910_PWM3 APBC_REG(0x018) +#define APBC_PXA910_SSP1 APBC_REG(0x01c) +#define APBC_PXA910_SSP2 APBC_REG(0x020) +#define APBC_PXA910_IPC APBC_REG(0x024) +#define APBC_PXA910_TWSI0 APBC_REG(0x02c) +#define APBC_PXA910_KPC APBC_REG(0x030) +#define APBC_PXA910_TIMERS APBC_REG(0x034) +#define APBC_PXA910_TBROT APBC_REG(0x038) +#define APBC_PXA910_AIB APBC_REG(0x03c) +#define APBC_PXA910_SW_JTAG APBC_REG(0x040) +#define APBC_PXA910_TIMERS1 APBC_REG(0x044) +#define APBC_PXA910_ONEWIRE APBC_REG(0x048) +#define APBC_PXA910_SSP3 APBC_REG(0x04c) +#define APBC_PXA910_ASFAR APBC_REG(0x050) +#define APBC_PXA910_ASSAR APBC_REG(0x054) + /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c new file mode 100644 index 000000000000..453f8f7758bf --- /dev/null +++ b/arch/arm/mach-mmp/pxa910.c @@ -0,0 +1,158 @@ +/* + * linux/arch/arm/mach-mmp/pxa910.c + * + * Code specific to PXA910 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "clock.h" + +#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) + +static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = +{ + MFP_ADDR_X(GPIO0, GPIO54, 0xdc), + MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), + MFP_ADDR_X(GPIO100, GPIO109, 0x238), + + MFP_ADDR(GPIO123, 0xcc), + MFP_ADDR(GPIO124, 0xd0), + + MFP_ADDR(DF_IO0, 0x40), + MFP_ADDR(DF_IO1, 0x3c), + MFP_ADDR(DF_IO2, 0x38), + MFP_ADDR(DF_IO3, 0x34), + MFP_ADDR(DF_IO4, 0x30), + MFP_ADDR(DF_IO5, 0x2c), + MFP_ADDR(DF_IO6, 0x28), + MFP_ADDR(DF_IO7, 0x24), + MFP_ADDR(DF_IO8, 0x20), + MFP_ADDR(DF_IO9, 0x1c), + MFP_ADDR(DF_IO10, 0x18), + MFP_ADDR(DF_IO11, 0x14), + MFP_ADDR(DF_IO12, 0x10), + MFP_ADDR(DF_IO13, 0xc), + MFP_ADDR(DF_IO14, 0x8), + MFP_ADDR(DF_IO15, 0x4), + + MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), + MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), + MFP_ADDR(SM_nCS0, 0x4c), + MFP_ADDR(SM_nCS1, 0x50), + MFP_ADDR(DF_WEn, 0x54), + MFP_ADDR(DF_REn, 0x58), + MFP_ADDR(DF_CLE_SM_OEn, 0x5c), + MFP_ADDR(DF_ALE_SM_WEn, 0x60), + MFP_ADDR(SM_SCLK, 0x64), + MFP_ADDR(DF_RDY0, 0x68), + MFP_ADDR(SM_BE0, 0x6c), + MFP_ADDR(SM_BE1, 0x70), + MFP_ADDR(SM_ADV, 0x74), + MFP_ADDR(DF_RDY1, 0x78), + MFP_ADDR(SM_ADVMUX, 0x7c), + MFP_ADDR(SM_RDY, 0x80), + + MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), + + MFP_ADDR_END, +}; + +#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) + +static void __init pxa910_init_gpio(void) +{ + int i; + + /* enable GPIO clock */ + __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO); + + /* unmask GPIO edge detection for all 4 banks - APMASKx */ + for (i = 0; i < 4; i++) + __raw_writel(0xffffffff, APMASK(i)); + + pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL); +} + +void __init pxa910_init_irq(void) +{ + icu_init_irq(); + pxa910_init_gpio(); +} + +/* APB peripheral clocks */ +static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); +static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); + +/* device and clock bindings */ +static struct clk_lookup pxa910_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), +}; + +static int __init pxa910_init(void) +{ + if (cpu_is_pxa910()) { + mfp_init_base(MFPR_VIRT_BASE); + mfp_init_addr(pxa910_mfp_addr_map); + pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); + clks_register(ARRAY_AND_SIZE(pxa910_clkregs)); + } + + return 0; +} +postcore_initcall(pxa910_init); + +/* system timer - clock enabled, 3.25MHz */ +#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) + +static void __init pxa910_timer_init(void) +{ + /* reset and configure */ + __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); + + timer_init(IRQ_PXA910_AP1_TIMER1); +} + +struct sys_timer pxa910_timer = { + .init = pxa910_timer_init, +}; + +/* on-chip devices */ + +/* NOTE: there are totally 3 UARTs on PXA910: + * + * UART1 - Slow UART (can be used both by AP and CP) + * UART2/3 - Fast UART + * + * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, + * they are re-ordered as: + * + * pxa910_device_uart1 - UART2 as FFUART + * pxa910_device_uart2 - UART3 as BTUART + * + * UART1 is not used by AP for the moment. + */ +PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); +PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index a22229cde096..64019464c8db 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h @@ -209,6 +209,36 @@ enum { MFP_PIN_DF_IO13, MFP_PIN_DF_IO14, MFP_PIN_DF_IO15, + MFP_PIN_DF_nCS0_SM_nCS2, + MFP_PIN_DF_nCS1_SM_nCS3, + MFP_PIN_SM_nCS0, + MFP_PIN_SM_nCS1, + MFP_PIN_DF_WEn, + MFP_PIN_DF_REn, + MFP_PIN_DF_CLE_SM_OEn, + MFP_PIN_DF_ALE_SM_WEn, + MFP_PIN_DF_RDY0, + MFP_PIN_DF_RDY1, + + MFP_PIN_SM_SCLK, + MFP_PIN_SM_BE0, + MFP_PIN_SM_BE1, + MFP_PIN_SM_ADV, + MFP_PIN_SM_ADVMUX, + MFP_PIN_SM_RDY, + + MFP_PIN_MMC1_DAT7, + MFP_PIN_MMC1_DAT6, + MFP_PIN_MMC1_DAT5, + MFP_PIN_MMC1_DAT4, + MFP_PIN_MMC1_DAT3, + MFP_PIN_MMC1_DAT2, + MFP_PIN_MMC1_DAT1, + MFP_PIN_MMC1_DAT0, + MFP_PIN_MMC1_CMD, + MFP_PIN_MMC1_CLK, + MFP_PIN_MMC1_CD, + MFP_PIN_MMC1_WP, /* additional pins on PXA930 */ MFP_PIN_GSIM_UIO, -- cgit v1.2.3