From b519c9c7e68d5e2e9d5aaff3843fda09342c79d7 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 18 Aug 2022 17:18:12 +0200 Subject: ARM: footbridge: remove addin mode This does not appear to have been used in many years, we can kill off some of the uglier code. Among other things, it avoids a randconfig issue when both modes are disabled: arch/arm/mach-footbridge/common.c:149:24: error: 'ebsa285_host_io_desc' defined but not used [-Werror=unused-variable] 149 | static struct map_desc ebsa285_host_io_desc[] __initdata = { | ^~~~~~~~~~~~~~~~~~~~ arch/arm/mach-footbridge/common.c:136:24: error: 'fb_common_io_desc' defined but not used [-Werror=unused-variable] 136 | static struct map_desc fb_common_io_desc[] __initdata = { | ^~~~~~~~~~~~~~~~~ The recently added phys_to_dma() functions are now trivial and could probably be removed again as a follow-up, if anyone knows how. Cc: Christoph Hellwig Tested-by: Marc Zyngier Signed-off-by: Arnd Bergmann --- arch/arm/mach-footbridge/dc21285.c | 61 +++++++++++++------------------------- 1 file changed, 20 insertions(+), 41 deletions(-) (limited to 'arch/arm/mach-footbridge/dc21285.c') diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index f9713dc561cf..372600bc15c8 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -245,9 +245,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) { struct resource *res; - if (nr || !footbridge_cfn_mode()) - return 0; - res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); if (!res) { printk("out of memory for root bus resources"); @@ -278,7 +275,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) void __init dc21285_preinit(void) { unsigned int mem_size, mem_mask; - int cfn_mode; pcibios_min_mem = 0x81000000; @@ -298,21 +294,15 @@ void __init dc21285_preinit(void) *CSR_CSRBASEOFFSET = 0; *CSR_PCIADDR_EXTN = 0; - cfn_mode = __footbridge_cfn_mode(); - printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in " - "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ? - "central function" : "addin"); - - if (footbridge_cfn_mode()) { - /* - * Clear any existing errors - we aren't - * interested in historical data... - */ - *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | - SA110_CNTL_RXSERR; - *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS; - } + "central function mode\n", *CSR_CLASSREV & 0xff); + + /* + * Clear any existing errors - we aren't + * interested in historical data... + */ + *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) | SA110_CNTL_RXSERR; + *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS; timer_setup(&serr_timer, dc21285_enable_error, 0); timer_setup(&perr_timer, dc21285_enable_error, 0); @@ -331,29 +321,18 @@ void __init dc21285_preinit(void) dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, 0, "PCI data parity", NULL); - if (cfn_mode) { - /* - * Map our SDRAM at a known address in PCI space, just in case - * the firmware had other ideas. Using a nonzero base is - * necessary, since some VGA cards forcefully use PCI addresses - * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). - */ - *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = 0; - *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); - *CSR_PCIROMBASE = 0; - *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS; - } else if (footbridge_cfn_mode() != 0) { - /* - * If we are not compiled to accept "add-in" mode, then - * we are using a constant virt_to_bus translation which - * can not hope to cater for the way the host BIOS has - * set up the machine. - */ - panic("PCI: this kernel is compiled for central " - "function mode only"); - } + /* + * Map our SDRAM at a known address in PCI space, just in case + * the firmware had other ideas. Using a nonzero base is + * necessary, since some VGA cards forcefully use PCI addresses + * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). + */ + *CSR_PCICSRBASE = 0xf4000000; + *CSR_PCICSRIOBASE = 0; + *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); + *CSR_PCIROMBASE = 0; + *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS; } void __init dc21285_postinit(void) -- cgit v1.2.3