From 3f9fb2a08f55c79b4c6cde423c1e8ddcc5a49781 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 13 Mar 2013 13:15:25 +0100 Subject: ARM: cns3xxx: make mach header files local The mach/cns3xxx.h and mach/pm.h header files are used only in the platform code itself, so there is no need to make them globally visible. This gets us closer to multiplatform configuration for cns3xxx. Signed-off-by: Arnd Bergmann --- arch/arm/mach-cns3xxx/cns3420vb.c | 5 +- arch/arm/mach-cns3xxx/cns3xxx.h | 629 +++++++++++++++++++++++ arch/arm/mach-cns3xxx/core.c | 2 +- arch/arm/mach-cns3xxx/devices.c | 5 +- arch/arm/mach-cns3xxx/include/mach/cns3xxx.h | 632 ------------------------ arch/arm/mach-cns3xxx/include/mach/pm.h | 23 - arch/arm/mach-cns3xxx/include/mach/uncompress.h | 2 +- arch/arm/mach-cns3xxx/pcie.c | 2 +- arch/arm/mach-cns3xxx/pm.c | 4 +- arch/arm/mach-cns3xxx/pm.h | 23 + 10 files changed, 661 insertions(+), 666 deletions(-) create mode 100644 arch/arm/mach-cns3xxx/cns3xxx.h delete mode 100644 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h delete mode 100644 arch/arm/mach-cns3xxx/include/mach/pm.h create mode 100644 arch/arm/mach-cns3xxx/pm.h (limited to 'arch/arm/mach-cns3xxx') diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index a71867e1d8d6..d863d8729edc 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -31,9 +31,8 @@ #include #include #include -#include -#include -#include +#include "cns3xxx.h" +#include "pm.h" #include "core.h" #include "devices.h" diff --git a/arch/arm/mach-cns3xxx/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h new file mode 100644 index 000000000000..d7d3a8d64282 --- /dev/null +++ b/arch/arm/mach-cns3xxx/cns3xxx.h @@ -0,0 +1,629 @@ +/* + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __MACH_BOARD_CNS3XXXH +#define __MACH_BOARD_CNS3XXXH + +/* + * Memory map + */ +#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ +#define CNS3XXX_FLASH_SIZE SZ_256M + +#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ + +#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ + +#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ +#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 + +#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ +#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 + +#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ +#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 + +#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ +#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 + +#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ +#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 + +#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ +#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 + +#define SMC_MEMC_STATUS_OFFSET 0x000 +#define SMC_MEMIF_CFG_OFFSET 0x004 +#define SMC_MEMC_CFG_SET_OFFSET 0x008 +#define SMC_MEMC_CFG_CLR_OFFSET 0x00C +#define SMC_DIRECT_CMD_OFFSET 0x010 +#define SMC_SET_CYCLES_OFFSET 0x014 +#define SMC_SET_OPMODE_OFFSET 0x018 +#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 +#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 +#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 +#define SMC_NAND_CYCLES0_0_OFFSET 0x100 +#define SMC_OPMODE0_0_OFFSET 0x104 +#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 +#define SMC_NAND_CYCLES0_1_OFFSET 0x120 +#define SMC_OPMODE0_1_OFFSET 0x124 +#define SMC_USER_STATUS_OFFSET 0x200 +#define SMC_USER_CONFIG_OFFSET 0x204 +#define SMC_ECC_STATUS_OFFSET 0x300 +#define SMC_ECC_MEMCFG_OFFSET 0x304 +#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 +#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C +#define SMC_ECC_ADDR0_OFFSET 0x310 +#define SMC_ECC_ADDR1_OFFSET 0x314 +#define SMC_ECC_VALUE0_OFFSET 0x318 +#define SMC_ECC_VALUE1_OFFSET 0x31C +#define SMC_ECC_VALUE2_OFFSET 0x320 +#define SMC_ECC_VALUE3_OFFSET 0x324 +#define SMC_PERIPH_ID_0_OFFSET 0xFE0 +#define SMC_PERIPH_ID_1_OFFSET 0xFE4 +#define SMC_PERIPH_ID_2_OFFSET 0xFE8 +#define SMC_PERIPH_ID_3_OFFSET 0xFEC +#define SMC_PCELL_ID_0_OFFSET 0xFF0 +#define SMC_PCELL_ID_1_OFFSET 0xFF4 +#define SMC_PCELL_ID_2_OFFSET 0xFF8 +#define SMC_PCELL_ID_3_OFFSET 0xFFC + +#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ +#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 + +#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ +#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 + +#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ +#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 + +#define RTC_SEC_OFFSET 0x00 +#define RTC_MIN_OFFSET 0x04 +#define RTC_HOUR_OFFSET 0x08 +#define RTC_DAY_OFFSET 0x0C +#define RTC_SEC_ALM_OFFSET 0x10 +#define RTC_MIN_ALM_OFFSET 0x14 +#define RTC_HOUR_ALM_OFFSET 0x18 +#define RTC_REC_OFFSET 0x1C +#define RTC_CTRL_OFFSET 0x20 +#define RTC_INTR_STS_OFFSET 0x34 + +#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ +#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ + +#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ +#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 + +#define PM_CLK_GATE_OFFSET 0x00 +#define PM_SOFT_RST_OFFSET 0x04 +#define PM_HS_CFG_OFFSET 0x08 +#define PM_CACTIVE_STA_OFFSET 0x0C +#define PM_PWR_STA_OFFSET 0x10 +#define PM_SYS_CLK_CTRL_OFFSET 0x14 +#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 +#define PM_PLL_HM_PD_OFFSET 0x1C + +#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ +#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 + +#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ +#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 + +#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ +#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 + +#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ +#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 + +#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ +#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 + +#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ +#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 + +#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ +#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 + +#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ +#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 + +#define TIMER1_COUNTER_OFFSET 0x00 +#define TIMER1_AUTO_RELOAD_OFFSET 0x04 +#define TIMER1_MATCH_V1_OFFSET 0x08 +#define TIMER1_MATCH_V2_OFFSET 0x0C + +#define TIMER2_COUNTER_OFFSET 0x10 +#define TIMER2_AUTO_RELOAD_OFFSET 0x14 +#define TIMER2_MATCH_V1_OFFSET 0x18 +#define TIMER2_MATCH_V2_OFFSET 0x1C + +#define TIMER1_2_CONTROL_OFFSET 0x30 +#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 +#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 + +#define TIMER_FREERUN_OFFSET 0x40 +#define TIMER_FREERUN_CONTROL_OFFSET 0x44 + +#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ +#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 + +#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ +#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 + +#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ +#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 + +#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ +#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 + +#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ +#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 + +#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ + +#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ +#define CNS3XXX_SATA2_SIZE SZ_16M +#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 + +#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ +#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 + +#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ +#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 + +#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ +#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 + +#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ +#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 + +#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ + +#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ +#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 + +#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ +#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 + +#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ +#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 + +#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ +#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 + +#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ +#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 + +#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ +#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 + +#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ +#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 + +#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ +#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 + +#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ +#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 + +#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ +#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 + +#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ +#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 + +#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ +#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 + +#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ +#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 + +/* + * Testchip peripheral and fpga gic regions + */ +#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ +#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 + +#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ +#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 + +#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 +#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 + +#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ +#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 + +#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ +#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 + +/* + * Misc block + */ +#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) + +#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) +#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) +#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) +#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) +#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) +#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) +#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) +#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) +#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) +#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) +#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) +#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) +#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) +#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) +#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) +#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) +#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) +#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) +#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) + +#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) + +#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) +#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) +#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) +#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) +#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) +#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) + +#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) +#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) +#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) +#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) +#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) +#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) +#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) +#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) +#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) +#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) +#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) +#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) +#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) +#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) +#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) +#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) +#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) + +/* + * Power management and clock control + */ +#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) + +#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) +#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) +#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) +#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) +#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) +#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) +#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) +#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) +#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) +#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) +#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) +#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) +#define PM_CSR_REG PMU_MEM_MAP(0x030) + +/* PM_CLK_GATE_REG */ +#define PM_CLK_GATE_REG_OFFSET_SDIO (25) +#define PM_CLK_GATE_REG_OFFSET_GPU (24) +#define PM_CLK_GATE_REG_OFFSET_CIM (23) +#define PM_CLK_GATE_REG_OFFSET_LCDC (22) +#define PM_CLK_GATE_REG_OFFSET_I2S (21) +#define PM_CLK_GATE_REG_OFFSET_RAID (20) +#define PM_CLK_GATE_REG_OFFSET_SATA (19) +#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) +#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) +#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) +#define PM_CLK_GATE_REG_OFFSET_TIMER (14) +#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) +#define PM_CLK_GATE_REG_OFFSET_HCIE (12) +#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) +#define PM_CLK_GATE_REG_OFFSET_GPIO (10) +#define PM_CLK_GATE_REG_OFFSET_UART3 (9) +#define PM_CLK_GATE_REG_OFFSET_UART2 (8) +#define PM_CLK_GATE_REG_OFFSET_UART1 (7) +#define PM_CLK_GATE_REG_OFFSET_RTC (5) +#define PM_CLK_GATE_REG_OFFSET_GDMA (4) +#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) +#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) +#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) + +/* PM_SOFT_RST_REG */ +#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) +#define PM_SOFT_RST_REG_OFFST_CPU1 (29) +#define PM_SOFT_RST_REG_OFFST_CPU0 (28) +#define PM_SOFT_RST_REG_OFFST_SDIO (25) +#define PM_SOFT_RST_REG_OFFST_GPU (24) +#define PM_SOFT_RST_REG_OFFST_CIM (23) +#define PM_SOFT_RST_REG_OFFST_LCDC (22) +#define PM_SOFT_RST_REG_OFFST_I2S (21) +#define PM_SOFT_RST_REG_OFFST_RAID (20) +#define PM_SOFT_RST_REG_OFFST_SATA (19) +#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) +#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) +#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) +#define PM_SOFT_RST_REG_OFFST_TIMER (14) +#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) +#define PM_SOFT_RST_REG_OFFST_HCIE (12) +#define PM_SOFT_RST_REG_OFFST_SWITCH (11) +#define PM_SOFT_RST_REG_OFFST_GPIO (10) +#define PM_SOFT_RST_REG_OFFST_UART3 (9) +#define PM_SOFT_RST_REG_OFFST_UART2 (8) +#define PM_SOFT_RST_REG_OFFST_UART1 (7) +#define PM_SOFT_RST_REG_OFFST_RTC (5) +#define PM_SOFT_RST_REG_OFFST_GDMA (4) +#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) +#define PM_SOFT_RST_REG_OFFST_DMC (2) +#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) +#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) +#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) + +/* PMHS_CFG_REG */ +#define PM_HS_CFG_REG_OFFSET_SDIO (25) +#define PM_HS_CFG_REG_OFFSET_GPU (24) +#define PM_HS_CFG_REG_OFFSET_CIM (23) +#define PM_HS_CFG_REG_OFFSET_LCDC (22) +#define PM_HS_CFG_REG_OFFSET_I2S (21) +#define PM_HS_CFG_REG_OFFSET_RAID (20) +#define PM_HS_CFG_REG_OFFSET_SATA (19) +#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) +#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) +#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) +#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) +#define PM_HS_CFG_REG_OFFSET_TIMER (14) +#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) +#define PM_HS_CFG_REG_OFFSET_HCIE (12) +#define PM_HS_CFG_REG_OFFSET_SWITCH (11) +#define PM_HS_CFG_REG_OFFSET_GPIO (10) +#define PM_HS_CFG_REG_OFFSET_UART3 (9) +#define PM_HS_CFG_REG_OFFSET_UART2 (8) +#define PM_HS_CFG_REG_OFFSET_UART1 (7) +#define PM_HS_CFG_REG_OFFSET_RTC (5) +#define PM_HS_CFG_REG_OFFSET_GDMA (4) +#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_HS_CFG_REG_OFFSET_DMC (2) +#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) +#define PM_HS_CFG_REG_MASK (0x03FFFFBE) +#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) + +/* PM_CACTIVE_STA_REG */ +#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) +#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) +#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) +#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) +#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) +#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) +#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) +#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) +#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) +#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) +#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) +#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) +#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) +#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) +#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) +#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) +#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) +#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) +#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) +#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) +#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) +#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) +#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) +#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) + +/* PM_PWR_STA_REG */ +#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) +#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) +#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) +#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) +#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) +#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) +#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) +#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) +#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) +#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) +#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) +#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) +#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) +#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) +#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) +#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) +#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) +#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) +#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) +#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) +#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) +#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) +#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) +#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) +#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) + +/* PM_CLK_CTRL_REG */ +#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) +#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) +#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) +#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) +#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) +#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) +#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) +#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) +#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) +#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) +#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) +#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) +#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) +#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) +#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) +#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) + +#define PM_CPU_CLK_DIV(DIV) { \ + PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ + PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ +} + +#define PM_PLL_CPU_SEL(CPU) { \ + PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ + PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ +} + +/* PM_PLL_LCD_I2S_CTRL_REG */ +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) +#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) + +/* PM_PLL_HM_PD_CTRL_REG */ +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) +#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) +#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) + +/* PM_WDT_CTRL_REG */ +#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) + +/* PM_CSR_REG - Clock Scaling Register*/ +#define PM_CSR_REG_OFFSET_CSR_EN (30) +#define PM_CSR_REG_OFFSET_CSR_NUM (0) + +#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< #include #include -#include +#include "cns3xxx.h" #include "core.h" static struct map_desc cns3xxx_io_desc[] __initdata = { diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c index 1e40c99b015f..7da78a2451f1 100644 --- a/arch/arm/mach-cns3xxx/devices.c +++ b/arch/arm/mach-cns3xxx/devices.c @@ -16,9 +16,8 @@ #include #include #include -#include -#include -#include +#include "cns3xxx.h" +#include "pm.h" #include "core.h" #include "devices.h" diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h deleted file mode 100644 index 191c8e57f289..000000000000 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ /dev/null @@ -1,632 +0,0 @@ -/* - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_BOARD_CNS3XXXH -#define __MACH_BOARD_CNS3XXXH - -/* - * Memory map - */ -#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ -#define CNS3XXX_FLASH_SIZE SZ_256M - -#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ - -#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ - -#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ -#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 - -#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ -#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 - -#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ -#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 - -#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ -#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 - -#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ -#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 - -#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ -#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 - -#define SMC_MEMC_STATUS_OFFSET 0x000 -#define SMC_MEMIF_CFG_OFFSET 0x004 -#define SMC_MEMC_CFG_SET_OFFSET 0x008 -#define SMC_MEMC_CFG_CLR_OFFSET 0x00C -#define SMC_DIRECT_CMD_OFFSET 0x010 -#define SMC_SET_CYCLES_OFFSET 0x014 -#define SMC_SET_OPMODE_OFFSET 0x018 -#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 -#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 -#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 -#define SMC_NAND_CYCLES0_0_OFFSET 0x100 -#define SMC_OPMODE0_0_OFFSET 0x104 -#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 -#define SMC_NAND_CYCLES0_1_OFFSET 0x120 -#define SMC_OPMODE0_1_OFFSET 0x124 -#define SMC_USER_STATUS_OFFSET 0x200 -#define SMC_USER_CONFIG_OFFSET 0x204 -#define SMC_ECC_STATUS_OFFSET 0x300 -#define SMC_ECC_MEMCFG_OFFSET 0x304 -#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 -#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C -#define SMC_ECC_ADDR0_OFFSET 0x310 -#define SMC_ECC_ADDR1_OFFSET 0x314 -#define SMC_ECC_VALUE0_OFFSET 0x318 -#define SMC_ECC_VALUE1_OFFSET 0x31C -#define SMC_ECC_VALUE2_OFFSET 0x320 -#define SMC_ECC_VALUE3_OFFSET 0x324 -#define SMC_PERIPH_ID_0_OFFSET 0xFE0 -#define SMC_PERIPH_ID_1_OFFSET 0xFE4 -#define SMC_PERIPH_ID_2_OFFSET 0xFE8 -#define SMC_PERIPH_ID_3_OFFSET 0xFEC -#define SMC_PCELL_ID_0_OFFSET 0xFF0 -#define SMC_PCELL_ID_1_OFFSET 0xFF4 -#define SMC_PCELL_ID_2_OFFSET 0xFF8 -#define SMC_PCELL_ID_3_OFFSET 0xFFC - -#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ -#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 - -#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ -#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 - -#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ -#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 - -#define RTC_SEC_OFFSET 0x00 -#define RTC_MIN_OFFSET 0x04 -#define RTC_HOUR_OFFSET 0x08 -#define RTC_DAY_OFFSET 0x0C -#define RTC_SEC_ALM_OFFSET 0x10 -#define RTC_MIN_ALM_OFFSET 0x14 -#define RTC_HOUR_ALM_OFFSET 0x18 -#define RTC_REC_OFFSET 0x1C -#define RTC_CTRL_OFFSET 0x20 -#define RTC_INTR_STS_OFFSET 0x34 - -#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ - -#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 - -#define PM_CLK_GATE_OFFSET 0x00 -#define PM_SOFT_RST_OFFSET 0x04 -#define PM_HS_CFG_OFFSET 0x08 -#define PM_CACTIVE_STA_OFFSET 0x0C -#define PM_PWR_STA_OFFSET 0x10 -#define PM_SYS_CLK_CTRL_OFFSET 0x14 -#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 -#define PM_PLL_HM_PD_OFFSET 0x1C - -#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 - -#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ -#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 - -#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ -#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 - -#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ -#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 - -#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ -#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 - -#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ -#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 - -#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ -#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 - -#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 - -#define TIMER1_COUNTER_OFFSET 0x00 -#define TIMER1_AUTO_RELOAD_OFFSET 0x04 -#define TIMER1_MATCH_V1_OFFSET 0x08 -#define TIMER1_MATCH_V2_OFFSET 0x0C - -#define TIMER2_COUNTER_OFFSET 0x10 -#define TIMER2_AUTO_RELOAD_OFFSET 0x14 -#define TIMER2_MATCH_V1_OFFSET 0x18 -#define TIMER2_MATCH_V2_OFFSET 0x1C - -#define TIMER1_2_CONTROL_OFFSET 0x30 -#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 -#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 - -#define TIMER_FREERUN_OFFSET 0x40 -#define TIMER_FREERUN_CONTROL_OFFSET 0x44 - -#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ -#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 - -#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ -#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 - -#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ -#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 - -#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ -#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 - -#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ -#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 - -#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ - -#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ -#define CNS3XXX_SATA2_SIZE SZ_16M -#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 - -#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ -#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 - -#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ -#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 - -#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ -#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 - -#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ -#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 - -#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ - -#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ -#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 - -#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ -#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 - -#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ -#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 - -#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ -#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000 - -#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ -#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 - -#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ -#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 - -#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ -#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000 - -#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ -#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000 - -#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ -#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 - -#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ -#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000 - -#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ -#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 - -#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ -#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 - -#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ -#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000 - -/* - * Testchip peripheral and fpga gic regions - */ -#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 - -#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 - -#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 - -#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 - -#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ -#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 - -/* - * Misc block - */ -#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) - -#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) -#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) -#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) -#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) -#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) -#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) -#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) -#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) -#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) -#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) -#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) -#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) -#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) -#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) -#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) - -/* - * Power management and clock control - */ -#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) - -#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) -#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) -#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) -#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) -#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) -#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) -#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) -#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) -#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) -#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) -#define PM_CSR_REG PMU_MEM_MAP(0x030) - -/* PM_CLK_GATE_REG */ -#define PM_CLK_GATE_REG_OFFSET_SDIO (25) -#define PM_CLK_GATE_REG_OFFSET_GPU (24) -#define PM_CLK_GATE_REG_OFFSET_CIM (23) -#define PM_CLK_GATE_REG_OFFSET_LCDC (22) -#define PM_CLK_GATE_REG_OFFSET_I2S (21) -#define PM_CLK_GATE_REG_OFFSET_RAID (20) -#define PM_CLK_GATE_REG_OFFSET_SATA (19) -#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) -#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) -#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) -#define PM_CLK_GATE_REG_OFFSET_TIMER (14) -#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) -#define PM_CLK_GATE_REG_OFFSET_HCIE (12) -#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) -#define PM_CLK_GATE_REG_OFFSET_GPIO (10) -#define PM_CLK_GATE_REG_OFFSET_UART3 (9) -#define PM_CLK_GATE_REG_OFFSET_UART2 (8) -#define PM_CLK_GATE_REG_OFFSET_UART1 (7) -#define PM_CLK_GATE_REG_OFFSET_RTC (5) -#define PM_CLK_GATE_REG_OFFSET_GDMA (4) -#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) -#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) -#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) - -/* PM_SOFT_RST_REG */ -#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) -#define PM_SOFT_RST_REG_OFFST_CPU1 (29) -#define PM_SOFT_RST_REG_OFFST_CPU0 (28) -#define PM_SOFT_RST_REG_OFFST_SDIO (25) -#define PM_SOFT_RST_REG_OFFST_GPU (24) -#define PM_SOFT_RST_REG_OFFST_CIM (23) -#define PM_SOFT_RST_REG_OFFST_LCDC (22) -#define PM_SOFT_RST_REG_OFFST_I2S (21) -#define PM_SOFT_RST_REG_OFFST_RAID (20) -#define PM_SOFT_RST_REG_OFFST_SATA (19) -#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) -#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) -#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) -#define PM_SOFT_RST_REG_OFFST_TIMER (14) -#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) -#define PM_SOFT_RST_REG_OFFST_HCIE (12) -#define PM_SOFT_RST_REG_OFFST_SWITCH (11) -#define PM_SOFT_RST_REG_OFFST_GPIO (10) -#define PM_SOFT_RST_REG_OFFST_UART3 (9) -#define PM_SOFT_RST_REG_OFFST_UART2 (8) -#define PM_SOFT_RST_REG_OFFST_UART1 (7) -#define PM_SOFT_RST_REG_OFFST_RTC (5) -#define PM_SOFT_RST_REG_OFFST_GDMA (4) -#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) -#define PM_SOFT_RST_REG_OFFST_DMC (2) -#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) -#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) -#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) - -/* PMHS_CFG_REG */ -#define PM_HS_CFG_REG_OFFSET_SDIO (25) -#define PM_HS_CFG_REG_OFFSET_GPU (24) -#define PM_HS_CFG_REG_OFFSET_CIM (23) -#define PM_HS_CFG_REG_OFFSET_LCDC (22) -#define PM_HS_CFG_REG_OFFSET_I2S (21) -#define PM_HS_CFG_REG_OFFSET_RAID (20) -#define PM_HS_CFG_REG_OFFSET_SATA (19) -#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) -#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) -#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) -#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) -#define PM_HS_CFG_REG_OFFSET_TIMER (14) -#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) -#define PM_HS_CFG_REG_OFFSET_HCIE (12) -#define PM_HS_CFG_REG_OFFSET_SWITCH (11) -#define PM_HS_CFG_REG_OFFSET_GPIO (10) -#define PM_HS_CFG_REG_OFFSET_UART3 (9) -#define PM_HS_CFG_REG_OFFSET_UART2 (8) -#define PM_HS_CFG_REG_OFFSET_UART1 (7) -#define PM_HS_CFG_REG_OFFSET_RTC (5) -#define PM_HS_CFG_REG_OFFSET_GDMA (4) -#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_HS_CFG_REG_OFFSET_DMC (2) -#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) -#define PM_HS_CFG_REG_MASK (0x03FFFFBE) -#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) - -/* PM_CACTIVE_STA_REG */ -#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) -#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) -#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) -#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) -#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) -#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) -#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) -#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) -#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) -#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) -#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) -#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) -#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) -#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) -#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) -#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) -#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) -#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) -#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) -#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) -#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) -#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) - -/* PM_PWR_STA_REG */ -#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) -#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) -#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) -#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) -#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) -#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) -#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) -#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) -#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) -#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) -#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) -#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) -#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) -#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) -#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) -#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) -#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) -#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) -#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) -#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) -#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) -#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) - -/* PM_CLK_CTRL_REG */ -#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) -#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) -#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) -#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) -#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) -#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) -#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) -#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) -#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) -#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) - -#define PM_CPU_CLK_DIV(DIV) { \ - PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ - PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ -} - -#define PM_PLL_CPU_SEL(CPU) { \ - PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ - PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ -} - -/* PM_PLL_LCD_I2S_CTRL_REG */ -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) - -/* PM_PLL_HM_PD_CTRL_REG */ -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) -#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) - -/* PM_WDT_CTRL_REG */ -#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) - -/* PM_CSR_REG - Clock Scaling Register*/ -#define PM_CSR_REG_OFFSET_CSR_EN (30) -#define PM_CSR_REG_OFFSET_CSR_NUM (0) - -#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< - -void cns3xxx_pwr_clk_en(unsigned int block); -void cns3xxx_pwr_clk_dis(unsigned int block); -void cns3xxx_pwr_power_up(unsigned int block); -void cns3xxx_pwr_power_down(unsigned int block); - -extern atomic_t usb_pwr_ref; - -#endif /* __CNS3XXX_PM_H */ diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h index 7a030b99df84..e2c642c1c66c 100644 --- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h +++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h @@ -8,7 +8,7 @@ */ #include -#include +#include "cns3xxx.h" #define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) #define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index 311328314163..c7b204bff386 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "cns3xxx.h" #include "core.h" enum cns3xxx_access_type { diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c index 36458080332a..79e3d47aad65 100644 --- a/arch/arm/mach-cns3xxx/pm.c +++ b/arch/arm/mach-cns3xxx/pm.c @@ -11,8 +11,8 @@ #include #include #include -#include -#include +#include "cns3xxx.h" +#include "pm.h" #include "core.h" void cns3xxx_pwr_clk_en(unsigned int block) diff --git a/arch/arm/mach-cns3xxx/pm.h b/arch/arm/mach-cns3xxx/pm.h new file mode 100644 index 000000000000..c2588cc991d1 --- /dev/null +++ b/arch/arm/mach-cns3xxx/pm.h @@ -0,0 +1,23 @@ +/* + * Copyright 2000 Deep Blue Solutions Ltd + * Copyright 2004 ARM Limited + * Copyright 2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + +#ifndef __CNS3XXX_PM_H +#define __CNS3XXX_PM_H + +#include + +void cns3xxx_pwr_clk_en(unsigned int block); +void cns3xxx_pwr_clk_dis(unsigned int block); +void cns3xxx_pwr_power_up(unsigned int block); +void cns3xxx_pwr_power_down(unsigned int block); + +extern atomic_t usb_pwr_ref; + +#endif /* __CNS3XXX_PM_H */ -- cgit v1.2.3 From 2f72a682f79d4eb2d96364d1a9abb7bd16c47afb Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 17:30:53 +0100 Subject: ARM: cns3xxx: enable sparse IRQ support This trivially enables sparse IRQ on cns3xxx by moving the nr_irqs definition from mach/irqs.h into the machine descriptor. These interrupts will still get statically assigned, so nothing changes here. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 1 + arch/arm/mach-cns3xxx/cns3420vb.c | 1 + arch/arm/mach-cns3xxx/include/mach/irqs.h | 24 ------------------------ 3 files changed, 2 insertions(+), 24 deletions(-) delete mode 100644 arch/arm/mach-cns3xxx/include/mach/irqs.h (limited to 'arch/arm/mach-cns3xxx') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5b714695b01b..8bad33e4f2bd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -390,6 +390,7 @@ config ARCH_CNS3XXX select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI + select SPARSE_IRQ help Support for Cavium Networks CNS3XXX platform. diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c index d863d8729edc..ce096d678aa4 100644 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ b/arch/arm/mach-cns3xxx/cns3420vb.c @@ -246,6 +246,7 @@ static void __init cns3420_map_io(void) MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") .atag_offset = 0x100, + .nr_irqs = NR_IRQS_CNS3XXX, .map_io = cns3420_map_io, .init_irq = cns3xxx_init_irq, .init_time = cns3xxx_timer_init, diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h deleted file mode 100644 index 2ab96f8085c8..000000000000 --- a/arch/arm/mach-cns3xxx/include/mach/irqs.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright 2000 Deep Blue Solutions Ltd. - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_IRQS_H -#define __MACH_IRQS_H - -#define IRQ_LOCALTIMER 29 -#define IRQ_LOCALWDOG 30 -#define IRQ_TC11MP_GIC_START 32 - -#include - -#ifndef NR_IRQS -#error "NR_IRQS not defined by the board-specific files" -#endif - -#endif -- cgit v1.2.3 From 29c9b7be7574c486534a79c45982ede00f6a25a9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 16:02:59 +0100 Subject: ARM: cns3xxx: move debug_ll code to include/debug/ This is needed in order to keep debug_ll functionality on cns3xxx working when we enable ARCH_MULTIPLATFORM. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 8 ++++++++ arch/arm/configs/cns3420vb_defconfig | 1 + arch/arm/include/debug/cns3xxx.S | 19 +++++++++++++++++++ arch/arm/mach-cns3xxx/include/mach/debug-macro.S | 19 ------------------- 4 files changed, 28 insertions(+), 19 deletions(-) create mode 100644 arch/arm/include/debug/cns3xxx.S delete mode 100644 arch/arm/mach-cns3xxx/include/mach/debug-macro.S (limited to 'arch/arm/mach-cns3xxx') diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index acddddac7ee4..52f410da464e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -103,6 +103,13 @@ choice Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. + config DEBUG_CNS3XXX + bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" + depends on ARCH_CNS3XXX + help + Say Y here if you want the debug print routines to direct + their output to the CNS3xxx UART0. + config DEBUG_DAVINCI_DA8XX_UART1 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" depends on ARCH_DAVINCI_DA8XX @@ -579,6 +586,7 @@ endchoice config DEBUG_LL_INCLUDE string + default "debug/cns3xxx.S" if DEBUG_CNS3XXX default "debug/icedcc.S" if DEBUG_ICEDCC default "debug/imx.S" if DEBUG_IMX1_UART || \ DEBUG_IMX25_UART || \ diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig index 313627adf46c..b79e98465dd9 100644 --- a/arch/arm/configs/cns3420vb_defconfig +++ b/arch/arm/configs/cns3420vb_defconfig @@ -21,6 +21,7 @@ CONFIG_MODVERSIONS=y CONFIG_IOSCHED_CFQ=m CONFIG_ARCH_CNS3XXX=y CONFIG_MACH_CNS3420VB=y +CONFIG_DEBUG_CNS3XXX=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 diff --git a/arch/arm/include/debug/cns3xxx.S b/arch/arm/include/debug/cns3xxx.S new file mode 100644 index 000000000000..d04c150baa1c --- /dev/null +++ b/arch/arm/include/debug/cns3xxx.S @@ -0,0 +1,19 @@ +/* + * Debugging macro include header + * + * Copyright 1994-1999 Russell King + * Copyright 2008 Cavium Networks + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + */ + + .macro addruart,rp,rv,tmp + mov \rp, #0x00009000 + orr \rv, \rp, #0xf0000000 @ virtual base + orr \rp, \rp, #0x10000000 + .endm + +#include diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S deleted file mode 100644 index d04c150baa1c..000000000000 --- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright 1994-1999 Russell King - * Copyright 2008 Cavium Networks - * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - - .macro addruart,rp,rv,tmp - mov \rp, #0x00009000 - orr \rv, \rp, #0xf0000000 @ virtual base - orr \rp, \rp, #0x10000000 - .endm - -#include -- cgit v1.2.3 From 15bc1fe67f66644c8093cc2d3304217d1c7de797 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 17:32:59 +0100 Subject: ARM: cns3xxx: enable multiplatform support This moves the cns3xxx configuration option inside of ARCH_MULTIPLATFORM, since there is no reason for not doing it now. We can then also remove the three header files that become obsolete. Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig | 12 ------ arch/arm/configs/cns3420vb_defconfig | 2 + arch/arm/mach-cns3xxx/Kconfig | 11 +++++ arch/arm/mach-cns3xxx/include/mach/timex.h | 12 ------ arch/arm/mach-cns3xxx/include/mach/uncompress.h | 53 ------------------------- 5 files changed, 13 insertions(+), 77 deletions(-) delete mode 100644 arch/arm/mach-cns3xxx/include/mach/timex.h delete mode 100644 arch/arm/mach-cns3xxx/include/mach/uncompress.h (limited to 'arch/arm/mach-cns3xxx') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8bad33e4f2bd..78ffcc62ae93 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -382,18 +382,6 @@ config ARCH_BCM2835 This enables support for the Broadcom BCM2835 SoC. This SoC is use in the Raspberry Pi, and Roku 2 devices. -config ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - select ARM_GIC - select CPU_V6K - select GENERIC_CLOCKEVENTS - select MIGHT_HAVE_CACHE_L2X0 - select MIGHT_HAVE_PCI - select PCI_DOMAINS if PCI - select SPARSE_IRQ - help - Support for Cavium Networks CNS3XXX platform. - config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig index b79e98465dd9..b1ff5cdba9a1 100644 --- a/arch/arm/configs/cns3420vb_defconfig +++ b/arch/arm/configs/cns3420vb_defconfig @@ -19,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_BLK_DEV_BSG is not set CONFIG_IOSCHED_CFQ=m +CONFIG_ARCH_MULTI_V6=y +#CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_CNS3XXX=y CONFIG_MACH_CNS3420VB=y CONFIG_DEBUG_CNS3XXX=y diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 9ebfcc46feb1..5720f3df1af2 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -1,3 +1,14 @@ +config ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6 + select ARM_GIC + select CPU_V6K + select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + help + Support for Cavium Networks CNS3XXX platform. + menu "CNS3XXX platform type" depends on ARCH_CNS3XXX diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h deleted file mode 100644 index 1fd04217cacb..000000000000 --- a/arch/arm/mach-cns3xxx/include/mach/timex.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Cavium Networks architecture timex specifications - * - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#define CLOCK_TICK_RATE (50000000 / 16) diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h deleted file mode 100644 index e2c642c1c66c..000000000000 --- a/arch/arm/mach-cns3xxx/include/mach/uncompress.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2003 ARM Limited - * Copyright 2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - */ - -#include -#include "cns3xxx.h" - -#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00)) -#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c)) -#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) -#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) - -/* - * Return the UART base address - */ -static inline unsigned long get_uart_base(void) -{ - if (machine_is_cns3420vb()) - return CNS3XXX_UART0_BASE; - else - return 0; -} - -/* - * This does not append a newline - */ -static inline void putc(int c) -{ - unsigned long base = get_uart_base(); - - while (AMBA_UART_FR(base) & (1 << 5)) - barrier(); - - AMBA_UART_DR(base) = c; -} - -static inline void flush(void) -{ - unsigned long base = get_uart_base(); - - while (AMBA_UART_FR(base) & (1 << 3)) - barrier(); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -- cgit v1.2.3 From 415f59142d9d9dd023deaeb3b4dfc1aecdd3983c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 14 Mar 2013 22:27:32 +0100 Subject: ARM: cns3xxx: initial DT support This adds very minimal support for booting cns3xxx using a device tree. It should support the same devices that cns3420vb provides but gets them from the DT. All devices that don't have their own binding are probed through auxdata. This is completely untested and likely incomplete. Booting through ATAGS is made optional, so it can be turned off by anybody who has a DTB file. Signed-off-by: Arnd Bergmann --- arch/arm/mach-cns3xxx/Kconfig | 1 + arch/arm/mach-cns3xxx/Makefile | 8 +-- arch/arm/mach-cns3xxx/core.c | 119 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-cns3xxx') diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig index 5720f3df1af2..dbf0df8bb0ac 100644 --- a/arch/arm/mach-cns3xxx/Kconfig +++ b/arch/arm/mach-cns3xxx/Kconfig @@ -14,6 +14,7 @@ menu "CNS3XXX platform type" config MACH_CNS3420VB bool "Support for CNS3420 Validation Board" + depends on ATAGS help Include support for the Cavium Networks CNS3420 MPCore Platform Baseboard. diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile index 11033f1c2e23..a1ff10848698 100644 --- a/arch/arm/mach-cns3xxx/Makefile +++ b/arch/arm/mach-cns3xxx/Makefile @@ -1,3 +1,5 @@ -obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o -obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o +cns3xxx-y += core.o pm.o +cns3xxx-$(CONFIG_ATAGS) += devices.o +cns3xxx-$(CONFIG_PCI) += pcie.o +cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c index 012ffdb9e142..49e657c15067 100644 --- a/arch/arm/mach-cns3xxx/core.c +++ b/arch/arm/mach-cns3xxx/core.c @@ -13,12 +13,18 @@ #include #include #include +#include +#include +#include +#include +#include #include #include #include #include #include "cns3xxx.h" #include "core.h" +#include "pm.h" static struct map_desc cns3xxx_io_desc[] __initdata = { { @@ -276,3 +282,116 @@ void __init cns3xxx_l2x0_init(void) } #endif /* CONFIG_CACHE_L2X0 */ + +static int csn3xxx_usb_power_on(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + * + * Set USB AHB INCR length to 16 + */ + if (atomic_inc_return(&usb_pwr_ref) == 1) { + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); + cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); + cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); + __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), + MISC_CHIP_CONFIG_REG); + } + + return 0; +} + +static void csn3xxx_usb_power_off(struct platform_device *pdev) +{ + /* + * EHCI and OHCI share the same clock and power, + * resetting twice would cause the 1st controller been reset. + * Therefore only do power up at the first up device, and + * power down at the last down device. + */ + if (atomic_dec_return(&usb_pwr_ref) == 0) + cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); +} + +static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { + .num_ports = 1, + .power_on = csn3xxx_usb_power_on, + .power_off = csn3xxx_usb_power_off, +}; + +static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { + { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, + { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, + { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, + { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, + {}, +}; + +static void __init cns3xxx_init(void) +{ + struct device_node *dn; + + cns3xxx_l2x0_init(); + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); + if (of_device_is_available(dn)) { + u32 tmp; + + tmp = __raw_readl(MISC_SATA_POWER_MODE); + tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ + tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ + __raw_writel(tmp, MISC_SATA_POWER_MODE); + + /* Enable SATA PHY */ + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); + cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); + + /* Enable SATA Clock */ + cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); + + /* De-Asscer SATA Reset */ + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); + } + + dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); + if (of_device_is_available(dn)) { + u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ + gpioa_pins |= 0x1fff0004; + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); + cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); + } + + pm_power_off = cns3xxx_power_off; + + of_platform_populate(NULL, of_default_bus_match_table, + cns3xxx_auxdata, NULL); +} + +static const char *cns3xxx_dt_compat[] __initdata = { + "cavium,cns3410", + "cavium,cns3420", + NULL, +}; + +DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") + .dt_compat = cns3xxx_dt_compat, + .nr_irqs = NR_IRQS_CNS3XXX, + .map_io = cns3xxx_map_io, + .init_irq = cns3xxx_init_irq, + .init_time = cns3xxx_timer_init, + .init_machine = cns3xxx_init, + .restart = cns3xxx_restart, +MACHINE_END -- cgit v1.2.3