From cde3f8607350666c4dd120dbbdbd9c70ffb2ea61 Mon Sep 17 00:00:00 2001 From: Artem Bityutskiy Date: Tue, 13 Oct 2009 08:54:30 +0100 Subject: ARM: 5759/1: Add register information of threads to coredump Defines ELF_CORE_COPY_TASK_REGS so that CPU register information of every thread is included in coredump. Without this, only the faulting thread is coredumped. Cc: Roger Quadros Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mika Westerberg Signed-off-by: Artem Bityutskiy Signed-off-by: Russell King --- arch/arm/include/asm/elf.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index c3b911ee9151..6aac3f5bb2f3 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -98,6 +98,9 @@ extern int elf_check_arch(const struct elf32_hdr *); extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk) +int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); +#define ELF_CORE_COPY_TASK_REGS dump_task_regs + #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 -- cgit v1.2.3 From daaeb6c93829806221b2ac533330c64f338ebb89 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Thu, 15 Oct 2009 15:06:47 +0100 Subject: ARM: 5763/1: ARM: SMP: Fix the BUG with CONFIG_PREEMPT enabled This patch fixes the BUG: using smp_processor_id() in preemptible Below is the stripped backtrace. BUG: using smp_processor_id() in preemptible [00000000] code: init/1 caller is flush_tlb_mm+0x44/0x70 Backtrace: [] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c) r7:00000000 r6:c00234f0 r5:00000001 r4:c7828000 [] (dump_stack+0x0/0x1c) from [] (debug_smp_processor_id+0xc0/0xf0) [] (debug_smp_processor_id+0x0/0xf0) from [] (flush_tlb_mm+0x44/0x70) r7:00000000 r6:c60b41a0 r5:c60b4154 r4:00000001 [] (flush_tlb_mm+0x0/0x70) from [] (dup_mm+0x304/0x38c) r5:c1f09058 r4:00000000 [] (dup_mm+0x0/0x38c) from [] (copy_process+0x7b8/0xeb0) [] (copy_process+0x0/0xeb0) from [] (do_fork+0x15c/0x29c) [] (do_fork+0x0/0x29c) from [] (sys_clone+0x34/0x3c) [] (sys_clone+0x0/0x3c) from [] (ret_fast_syscall+0x0/0x2c) Signed-off-by: Santosh Shilimkar Signed-off-by: Russell King --- arch/arm/include/asm/tlbflush.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index a45ab5dd8255..c2f1605de359 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -350,7 +350,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_WB)) dsb(); - if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) { + if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) { if (tlb_flag(TLB_V3_FULL)) asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_U_FULL)) @@ -360,6 +360,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_V4_I_FULL)) asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); } + put_cpu(); if (tlb_flag(TLB_V6_U_ASID)) asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc"); -- cgit v1.2.3 From df71dfd4ca01130f98d9dbfab76c440d72a177c6 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 24 Oct 2009 22:36:36 +0100 Subject: ARM: Fix errata 411920 workarounds Errata 411920 indicates that any "invalidate entire instruction cache" operation can fail if the right conditions are present. This is not limited just to those operations in flush.c, but elsewhere. Place the workaround in the already existing __flush_icache_all() function instead. Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 5 +++++ arch/arm/mm/context.c | 5 +---- arch/arm/mm/flush.c | 31 ++++++------------------------- 3 files changed, 12 insertions(+), 29 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index fd03fb63a332..3d0cdd21b882 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -414,9 +414,14 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page static inline void __flush_icache_all(void) { +#ifdef CONFIG_ARM_ERRATA_411920 + extern void v6_icache_inval_all(void); + v6_icache_inval_all(); +#else asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" : : "r" (0)); +#endif } #define ARCH_HAS_FLUSH_ANON_PAGE diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 6bda76a43199..a9e22e31eaa1 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -50,10 +50,7 @@ void __new_context(struct mm_struct *mm) isb(); flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { - asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" - "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n" - : - : "r" (0)); + __flush_icache_all(); dsb(); } } diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index b27942909b23..7f294f307c83 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -18,10 +18,6 @@ #include "mm.h" -#ifdef CONFIG_ARM_ERRATA_411920 -extern void v6_icache_inval_all(void); -#endif - #ifdef CONFIG_CPU_CACHE_VIPT #define ALIAS_FLUSH_START 0xffff4000 @@ -35,16 +31,11 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) flush_tlb_kernel_page(to); asm( "mcrr p15, 0, %1, %0, c14\n" - " mcr p15, 0, %2, c7, c10, 4\n" -#ifndef CONFIG_ARM_ERRATA_411920 - " mcr p15, 0, %2, c7, c5, 0\n" -#endif + " mcr p15, 0, %2, c7, c10, 4" : : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) : "cc"); -#ifdef CONFIG_ARM_ERRATA_411920 - v6_icache_inval_all(); -#endif + __flush_icache_all(); } void flush_cache_mm(struct mm_struct *mm) @@ -57,16 +48,11 @@ void flush_cache_mm(struct mm_struct *mm) if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" - " mcr p15, 0, %0, c7, c10, 4\n" -#ifndef CONFIG_ARM_ERRATA_411920 - " mcr p15, 0, %0, c7, c5, 0\n" -#endif + " mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "cc"); -#ifdef CONFIG_ARM_ERRATA_411920 - v6_icache_inval_all(); -#endif + __flush_icache_all(); } } @@ -81,16 +67,11 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned if (cache_is_vipt_aliasing()) { asm( "mcr p15, 0, %0, c7, c14, 0\n" - " mcr p15, 0, %0, c7, c10, 4\n" -#ifndef CONFIG_ARM_ERRATA_411920 - " mcr p15, 0, %0, c7, c5, 0\n" -#endif + " mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "cc"); -#ifdef CONFIG_ARM_ERRATA_411920 - v6_icache_inval_all(); -#endif + __flush_icache_all(); } } -- cgit v1.2.3 From cc20d42986d5807cbe4f5c7c8e3dab2e59ea0db3 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 9 Nov 2009 23:53:29 +0000 Subject: ARM: Use a definition for the userspace cmpxchg emulation syscall Use a definition for the cmpxchg SWI instead of hard-coding the number. Signed-off-by: Russell King Acked-by: Nicolas Pitre --- arch/arm/include/asm/unistd.h | 9 +++++++++ arch/arm/kernel/entry-armv.S | 7 ++++--- arch/arm/kernel/traps.c | 2 +- 3 files changed, 14 insertions(+), 4 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 7020217fc49f..4e506d09e5f9 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -402,6 +402,15 @@ #define __ARM_NR_usr32 (__ARM_NR_BASE+4) #define __ARM_NR_set_tls (__ARM_NR_BASE+5) +/* + * *NOTE*: This is a ghost syscall private to the kernel. Only the + * __kuser_cmpxchg code in entry-armv.S should be aware of its + * existence. Don't ever use this from user code. + */ +#ifdef __KERNEL__ +#define __ARM_NR_cmpxchg (__ARM_NR_BASE+0x00fff0) +#endif + /* * The following syscalls are obsolete and no longer available for EABI. */ diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0022b4d57f8b..d2903e3bc861 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -21,6 +21,7 @@ #include #include #include +#include #include "entry-header.S" @@ -908,10 +909,10 @@ __kuser_cmpxchg: @ 0xffff0fc0 * A special ghost syscall is used for that (see traps.c). */ stmfd sp!, {r7, lr} - mov r7, #0xff00 @ 0xfff0 into r7 for EABI - orr r7, r7, #0xf0 - swi #0x9ffff0 + ldr r7, =1f @ it's 20 bits + swi __ARM_NR_cmpxchg ldmfd sp!, {r7, pc} +1: .word __ARM_NR_cmpxchg #elif __LINUX_ARM_ARCH__ < 6 diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 1bbda04a5380..3f361a783f43 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -528,7 +528,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs) * __kuser_cmpxchg code in entry-armv.S should be aware of its * existence. Don't ever use this from user code. */ - case 0xfff0: + case NR(cmpxchg): for (;;) { extern void do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs); -- cgit v1.2.3 From 4ff1fa278b0bd1b2dd3c42efc0cb86788ffe05d5 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 18 Nov 2009 18:03:19 +0000 Subject: [ARM] kmap: fix build errors with DEBUG_HIGHMEM enabled d451564 broke ARM by requiring KM_IRQ_PTE, KM_NMI and KM_NMI_PTE to always be defined. Solve this by providing invalid definitions for these constants, but only if CONFIG_DEBUG_HIGHMEM is enabled. Signed-off-by: Russell King --- arch/arm/include/asm/kmap_types.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h index d16ec97ec9a9..c019949a5189 100644 --- a/arch/arm/include/asm/kmap_types.h +++ b/arch/arm/include/asm/kmap_types.h @@ -22,4 +22,10 @@ enum km_type { KM_TYPE_NR }; +#ifdef CONFIG_DEBUG_HIGHMEM +#define KM_NMI (-1) +#define KM_NMI_PTE (-1) +#define KM_IRQ_PTE (-1) +#endif + #endif -- cgit v1.2.3 From 2f0b192633f1fbf253b21c90938733491549edae Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 25 Oct 2009 10:40:02 +0000 Subject: ARM: Avoid duplicated implementation for VIVT cache flushing We had two copies of the wrapper code for VIVT cache flushing - one in asm/cacheflush.h and one in arch/arm/mm/flush.c. Reduce this down to one common copy. Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 20 +++++++++++++++----- arch/arm/mm/flush.c | 17 ++++------------- 2 files changed, 19 insertions(+), 18 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 3d0cdd21b882..61ae25caaacb 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -331,15 +331,15 @@ static inline void outer_flush_range(unsigned long start, unsigned long end) * Convert calls to our calling convention. */ #define flush_cache_all() __cpuc_flush_kern_all() -#ifndef CONFIG_CPU_CACHE_VIPT -static inline void flush_cache_mm(struct mm_struct *mm) + +static inline void vivt_flush_cache_mm(struct mm_struct *mm) { if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) __cpuc_flush_user_all(); } static inline void -flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) +vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), @@ -347,7 +347,7 @@ flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long } static inline void -flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) +vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) { if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { unsigned long addr = user_addr & PAGE_MASK; @@ -356,7 +356,7 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned l } static inline void -flush_ptrace_access(struct vm_area_struct *vma, struct page *page, +vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page, unsigned long uaddr, void *kaddr, unsigned long len, int write) { @@ -365,6 +365,16 @@ flush_ptrace_access(struct vm_area_struct *vma, struct page *page, __cpuc_coherent_kern_range(addr, addr + len); } } + +#ifndef CONFIG_CPU_CACHE_VIPT +#define flush_cache_mm(mm) \ + vivt_flush_cache_mm(mm) +#define flush_cache_range(vma,start,end) \ + vivt_flush_cache_range(vma,start,end) +#define flush_cache_page(vma,addr,pfn) \ + vivt_flush_cache_page(vma,addr,pfn) +#define flush_ptrace_access(vma,page,ua,ka,len,write) \ + vivt_flush_ptrace_access(vma,page,ua,ka,len,write) #else extern void flush_cache_mm(struct mm_struct *mm); extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 7f294f307c83..a480f161a4bb 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -41,8 +41,7 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) void flush_cache_mm(struct mm_struct *mm) { if (cache_is_vivt()) { - if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) - __cpuc_flush_user_all(); + vivt_flush_cache_mm(mm); return; } @@ -59,9 +58,7 @@ void flush_cache_mm(struct mm_struct *mm) void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { if (cache_is_vivt()) { - if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) - __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), - vma->vm_flags); + vivt_flush_cache_range(vma, start, end); return; } @@ -78,10 +75,7 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) { if (cache_is_vivt()) { - if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { - unsigned long addr = user_addr & PAGE_MASK; - __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); - } + vivt_flush_cache_page(vma, user_addr, pfn); return; } @@ -94,10 +88,7 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, unsigned long len, int write) { if (cache_is_vivt()) { - if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { - unsigned long addr = (unsigned long)kaddr; - __cpuc_coherent_kern_range(addr, addr + len); - } + vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write); return; } -- cgit v1.2.3 From 7b0a1003e780193e2a11c27f5059c26b65f60679 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 24 Oct 2009 14:11:59 +0100 Subject: ARM: Reduce __flush_dcache_page() visibility Signed-off-by: Russell King --- arch/arm/include/asm/cacheflush.h | 2 -- arch/arm/mm/fault-armv.c | 2 ++ arch/arm/mm/mm.h | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/include') diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 61ae25caaacb..9fd6d3ab68c0 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -420,8 +420,6 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, */ extern void flush_dcache_page(struct page *); -extern void __flush_dcache_page(struct address_space *mapping, struct page *page); - static inline void __flush_icache_all(void) { #ifdef CONFIG_ARM_ERRATA_411920 diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 4fbc7de8b4ac..729602291958 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -23,6 +23,8 @@ #include #include +#include "mm.h" + static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE; /* diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index c4f6f05198e0..a888363398f8 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h @@ -24,6 +24,8 @@ struct mem_type { const struct mem_type *get_mem_type(unsigned int type); +extern void __flush_dcache_page(struct address_space *mapping, struct page *page); + #endif struct map_desc; -- cgit v1.2.3