From 37917ce5b4ee51e3164738cb653266f1a7d53120 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:43 +0300 Subject: ARM: dts: lpc32xx: change hexadecimal values to lower case This is a non-functional change, all inconsistent hexadecimal values found in the file are now fixed. Taking a chance to interfere into some non-functional change I add my copyright notice for work done during the last few years. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 20b38f4ade37..5eb223dffbe7 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -1,6 +1,7 @@ /* * NXP LPC32xx SoC * + * Copyright (C) 2015-2019 Vladimir Zapolskiy * Copyright 2012 Roland Stigge * * The code contained herein is licensed under the GNU General Public @@ -232,7 +233,7 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; - reg = <0x2009C000 0x1000>; + reg = <0x2009c000 0x1000>; }; /* UART5 first since it is the default console, ttyS0 */ @@ -275,7 +276,7 @@ i2c1: i2c@400a0000 { compatible = "nxp,pnx-i2c"; - reg = <0x400A0000 0x100>; + reg = <0x400a0000 0x100>; interrupt-parent = <&sic1>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; @@ -286,7 +287,7 @@ i2c2: i2c@400a8000 { compatible = "nxp,pnx-i2c"; - reg = <0x400A8000 0x100>; + reg = <0x400a8000 0x100>; interrupt-parent = <&sic1>; interrupts = <18 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; @@ -297,7 +298,7 @@ mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; - reg = <0x400E8000 0x78>; + reg = <0x400e8000 0x78>; status = "disabled"; #pwm-cells = <2>; }; @@ -396,7 +397,7 @@ timer4: timer@4002c000 { compatible = "nxp,lpc3220-timer"; - reg = <0x4002C000 0x1000>; + reg = <0x4002c000 0x1000>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER4>; clock-names = "timerclk"; @@ -414,7 +415,7 @@ watchdog: watchdog@4003c000 { compatible = "nxp,pnx4008-wdt"; - reg = <0x4003C000 0x1000>; + reg = <0x4003c000 0x1000>; clocks = <&clk LPC32XX_CLK_WDOG>; }; @@ -453,7 +454,7 @@ timer1: timer@4004c000 { compatible = "nxp,lpc3220-timer"; - reg = <0x4004C000 0x1000>; + reg = <0x4004c000 0x1000>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_TIMER1>; clock-names = "timerclk"; @@ -479,7 +480,7 @@ pwm1: pwm@4005c000 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C000 0x4>; + reg = <0x4005c000 0x4>; clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clocks = <&clk LPC32XX_CLK_PWM1>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; @@ -488,7 +489,7 @@ pwm2: pwm@4005c004 { compatible = "nxp,lpc3220-pwm"; - reg = <0x4005C004 0x4>; + reg = <0x4005c004 0x4>; clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clocks = <&clk LPC32XX_CLK_PWM2>; assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>; -- cgit v1.2.3 From 903fa2ab79d832ef3dcf7424f0227799cbeda3da Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:44 +0300 Subject: ARM: dts: lpc32xx: disable I2S controllers by default The I2S controllers found on NXP LPC32xx SoCs are not yet in use by any boards supported in upstream, disable the controllers by default. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 5eb223dffbe7..aa1d9dd248fd 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -219,6 +219,7 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + status = "disabled"; }; sd: sd@20098000 { @@ -234,6 +235,7 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + status = "disabled"; }; /* UART5 first since it is the default console, ttyS0 */ -- cgit v1.2.3 From 4c546175dbe1b9bde68f547666a2c1f75d65b817 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:45 +0300 Subject: ARM: dts: lpc32xx: disable MAC controller by default NXP LPC3220 and LPC3230 SoCs do NOT contain a MAC controller, so, since for now there is just one dtsi file for all variants of NXP LPC32xx SoCs, it is reasonable to disable the controller by default and enable it in device tree files of particular boards. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-ea3250.dts | 1 + arch/arm/boot/dts/lpc3250-phy3250.dts | 1 + arch/arm/boot/dts/lpc32xx.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/lpc3250-ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index f46a11827ef6..4adf4c96f798 100644 --- a/arch/arm/boot/dts/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -201,6 +201,7 @@ &mac { phy-mode = "rmii"; use-iram; + status = "okay"; }; /* Here, choose exactly one from: ohci, usbd */ diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index ebd19258e22b..b99726d278f6 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -134,6 +134,7 @@ &mac { phy-mode = "rmii"; use-iram; + status = "okay"; }; /* Here, choose exactly one from: ohci, usbd */ diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index aa1d9dd248fd..a0fedab579b4 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -153,6 +153,7 @@ reg = <0x31060000 0x1000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MAC>; + status = "disabled"; }; emc: memory-controller@31080000 { -- cgit v1.2.3 From cea862386791e281c4e9ab07dd118321f6655435 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:46 +0300 Subject: ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them by one cell address value, set it as default to avoid duplication in board device tree files. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc3250-phy3250.dts | 2 -- arch/arm/boot/dts/lpc32xx.dtsi | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts index b99726d278f6..1b15f798794b 100644 --- a/arch/arm/boot/dts/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -202,8 +202,6 @@ }; &ssp0 { - #address-cells = <1>; - #size-cells = <0>; num-cs = <1>; cs-gpios = <&gpio 3 5 0>; status = "okay"; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index a0fedab579b4..bc32450de423 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -187,6 +187,8 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -194,6 +196,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -207,6 +211,8 @@ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -214,6 +220,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; -- cgit v1.2.3 From d5a71e4646a741f22863b12d0037e15b5844af90 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 19 Apr 2019 23:54:47 +0300 Subject: ARM: dts: lpc32xx: use SPDX license identifier Replace GPLv2+ header with the SPDX identifier. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index bc32450de423..7b7ec7b1217b 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -1,15 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * NXP LPC32xx SoC * * Copyright (C) 2015-2019 Vladimir Zapolskiy * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include -- cgit v1.2.3