From 37f0f245f92a1fbb4786762129b7b1f090720a43 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 8 Apr 2021 22:34:43 +0530 Subject: ARM: dts: qcom: sdx55: Add support for A7 PLL clock On SDX55 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210408170457.91409-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-sdx55.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/boot') diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index e4180bbc4655..41c90f598359 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -352,6 +352,14 @@ <0x17802000 0x1000>; }; + a7pll: clock@17808000 { + compatible = "qcom,sdx55-a7pll"; + reg = <0x17808000 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <0>; + }; + watchdog@17817000 { compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; reg = <0x17817000 0x1000>; -- cgit v1.2.3